1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "X86FastISel.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/VectorExtras.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/ADT/SmallSet.h"
41 #include "llvm/ADT/StringExtras.h"
44 // Forward declarations.
45 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
47 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
48 : TargetLowering(TM) {
49 Subtarget = &TM.getSubtarget<X86Subtarget>();
50 X86ScalarSSEf64 = Subtarget->hasSSE2();
51 X86ScalarSSEf32 = Subtarget->hasSSE1();
52 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
56 RegInfo = TM.getRegisterInfo();
58 // Set up the TargetLowering object.
60 // X86 is weird, it always uses i8 for shift amounts and setcc results.
61 setShiftAmountType(MVT::i8);
62 setSetCCResultContents(ZeroOrOneSetCCResult);
63 setSchedulingPreference(SchedulingForRegPressure);
64 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
65 setStackPointerRegisterToSaveRestore(X86StackPtr);
67 if (Subtarget->isTargetDarwin()) {
68 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(false);
70 setUseUnderscoreLongJmp(false);
71 } else if (Subtarget->isTargetMingw()) {
72 // MS runtime is weird: it exports _setjmp, but longjmp!
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(false);
76 setUseUnderscoreSetJmp(true);
77 setUseUnderscoreLongJmp(true);
80 // Set up the register classes.
81 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
84 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 // We don't accept any truncstore of integer registers.
90 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
91 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
92 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
93 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
94 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
95 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
97 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
99 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
100 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
101 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
103 if (Subtarget->is64Bit()) {
104 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
105 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
108 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
109 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
111 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
114 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
116 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
117 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
118 // SSE has no i16 to fp conversion, only i32
119 if (X86ScalarSSEf32) {
120 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
121 // f32 and f64 cases are Legal, f80 case is not
122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
124 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
125 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
128 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
129 // are Legal, f80 is custom lowered.
130 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
133 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
135 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
136 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
138 if (X86ScalarSSEf32) {
139 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
140 // f32 and f64 cases are Legal, f80 case is not
141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
143 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
144 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
147 // Handle FP_TO_UINT by promoting the destination to a larger signed
149 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
151 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
153 if (Subtarget->is64Bit()) {
154 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
155 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
157 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
158 // Expand FP_TO_UINT into a select.
159 // FIXME: We would like to use a Custom expander here eventually to do
160 // the optimal thing for SSE vs. the default expansion in the legalizer.
161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
163 // With SSE3 we can use fisttpll to convert to a signed i64.
164 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
167 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
168 if (!X86ScalarSSEf64) {
169 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
170 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
173 // Scalar integer divide and remainder are lowered to use operations that
174 // produce two results, to match the available instructions. This exposes
175 // the two-result form to trivial CSE, which is able to combine x/y and x%y
176 // into a single instruction.
178 // Scalar integer multiply-high is also lowered to use two-result
179 // operations, to match the available instructions. However, plain multiply
180 // (low) operations are left as Legal, as there are single-result
181 // instructions for this in x86. Using the two-result multiply instructions
182 // when both high and low results are needed must be arranged by dagcombine.
183 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
184 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
185 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
186 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
187 setOperationAction(ISD::SREM , MVT::i8 , Expand);
188 setOperationAction(ISD::UREM , MVT::i8 , Expand);
189 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
190 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
191 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
192 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
193 setOperationAction(ISD::SREM , MVT::i16 , Expand);
194 setOperationAction(ISD::UREM , MVT::i16 , Expand);
195 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
196 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
197 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
198 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
199 setOperationAction(ISD::SREM , MVT::i32 , Expand);
200 setOperationAction(ISD::UREM , MVT::i32 , Expand);
201 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
202 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
203 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
204 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
205 setOperationAction(ISD::SREM , MVT::i64 , Expand);
206 setOperationAction(ISD::UREM , MVT::i64 , Expand);
208 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
209 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
210 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
211 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
212 if (Subtarget->is64Bit())
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
217 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
218 setOperationAction(ISD::FREM , MVT::f32 , Expand);
219 setOperationAction(ISD::FREM , MVT::f64 , Expand);
220 setOperationAction(ISD::FREM , MVT::f80 , Expand);
221 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
223 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
224 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
225 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
226 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
227 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
228 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
229 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
230 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
231 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
232 if (Subtarget->is64Bit()) {
233 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
234 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
235 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
238 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
239 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
241 // These should be promoted to a larger select which is supported.
242 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
243 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
244 // X86 wants to expand cmov itself.
245 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
246 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
247 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
248 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
249 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
250 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
251 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
252 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
253 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
254 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
255 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
258 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
260 // X86 ret instruction may pop stack.
261 setOperationAction(ISD::RET , MVT::Other, Custom);
262 if (!Subtarget->is64Bit())
263 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
266 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
267 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
268 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
269 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
270 if (Subtarget->is64Bit())
271 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
272 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
273 if (Subtarget->is64Bit()) {
274 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
275 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
276 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
277 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
279 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
280 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
281 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
282 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
283 if (Subtarget->is64Bit()) {
284 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
285 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
286 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
289 if (Subtarget->hasSSE1())
290 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
292 if (!Subtarget->hasSSE2())
293 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
295 // Expand certain atomics
296 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i8, Custom);
297 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i16, Custom);
298 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i32, Custom);
299 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i64, Custom);
301 setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i8, Expand);
302 setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i16, Expand);
303 setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i32, Expand);
304 setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i64, Expand);
306 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
307 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
308 // FIXME - use subtarget debug flags
309 if (!Subtarget->isTargetDarwin() &&
310 !Subtarget->isTargetELF() &&
311 !Subtarget->isTargetCygMing()) {
312 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
313 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
316 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
317 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
318 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
319 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
320 if (Subtarget->is64Bit()) {
322 setExceptionPointerRegister(X86::RAX);
323 setExceptionSelectorRegister(X86::RDX);
325 setExceptionPointerRegister(X86::EAX);
326 setExceptionSelectorRegister(X86::EDX);
328 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
330 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
332 setOperationAction(ISD::TRAP, MVT::Other, Legal);
334 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
335 setOperationAction(ISD::VASTART , MVT::Other, Custom);
336 setOperationAction(ISD::VAEND , MVT::Other, Expand);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::VAARG , MVT::Other, Custom);
339 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
341 setOperationAction(ISD::VAARG , MVT::Other, Expand);
342 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
345 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
346 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
349 if (Subtarget->isTargetCygMing())
350 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
352 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
354 if (X86ScalarSSEf64) {
355 // f32 and f64 use SSE.
356 // Set up the FP register classes.
357 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
358 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
360 // Use ANDPD to simulate FABS.
361 setOperationAction(ISD::FABS , MVT::f64, Custom);
362 setOperationAction(ISD::FABS , MVT::f32, Custom);
364 // Use XORP to simulate FNEG.
365 setOperationAction(ISD::FNEG , MVT::f64, Custom);
366 setOperationAction(ISD::FNEG , MVT::f32, Custom);
368 // Use ANDPD and ORPD to simulate FCOPYSIGN.
369 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
370 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
372 // We don't support sin/cos/fmod
373 setOperationAction(ISD::FSIN , MVT::f64, Expand);
374 setOperationAction(ISD::FCOS , MVT::f64, Expand);
375 setOperationAction(ISD::FSIN , MVT::f32, Expand);
376 setOperationAction(ISD::FCOS , MVT::f32, Expand);
378 // Expand FP immediates into loads from the stack, except for the special
380 addLegalFPImmediate(APFloat(+0.0)); // xorpd
381 addLegalFPImmediate(APFloat(+0.0f)); // xorps
383 // Floating truncations from f80 and extensions to f80 go through memory.
384 // If optimizing, we lie about this though and handle it in
385 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
387 setConvertAction(MVT::f32, MVT::f80, Expand);
388 setConvertAction(MVT::f64, MVT::f80, Expand);
389 setConvertAction(MVT::f80, MVT::f32, Expand);
390 setConvertAction(MVT::f80, MVT::f64, Expand);
392 } else if (X86ScalarSSEf32) {
393 // Use SSE for f32, x87 for f64.
394 // Set up the FP register classes.
395 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
396 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
398 // Use ANDPS to simulate FABS.
399 setOperationAction(ISD::FABS , MVT::f32, Custom);
401 // Use XORP to simulate FNEG.
402 setOperationAction(ISD::FNEG , MVT::f32, Custom);
404 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
406 // Use ANDPS and ORPS to simulate FCOPYSIGN.
407 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
408 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
410 // We don't support sin/cos/fmod
411 setOperationAction(ISD::FSIN , MVT::f32, Expand);
412 setOperationAction(ISD::FCOS , MVT::f32, Expand);
414 // Special cases we handle for FP constants.
415 addLegalFPImmediate(APFloat(+0.0f)); // xorps
416 addLegalFPImmediate(APFloat(+0.0)); // FLD0
417 addLegalFPImmediate(APFloat(+1.0)); // FLD1
418 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
419 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
421 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
422 // this though and handle it in InstructionSelectPreprocess so that
423 // dagcombine2 can hack on these.
425 setConvertAction(MVT::f32, MVT::f64, Expand);
426 setConvertAction(MVT::f32, MVT::f80, Expand);
427 setConvertAction(MVT::f80, MVT::f32, Expand);
428 setConvertAction(MVT::f64, MVT::f32, Expand);
429 // And x87->x87 truncations also.
430 setConvertAction(MVT::f80, MVT::f64, Expand);
434 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
435 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
438 // f32 and f64 in x87.
439 // Set up the FP register classes.
440 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
441 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
443 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
444 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
445 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
446 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
448 // Floating truncations go through memory. If optimizing, we lie about
449 // this though and handle it in InstructionSelectPreprocess so that
450 // dagcombine2 can hack on these.
452 setConvertAction(MVT::f80, MVT::f32, Expand);
453 setConvertAction(MVT::f64, MVT::f32, Expand);
454 setConvertAction(MVT::f80, MVT::f64, Expand);
458 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
459 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
461 addLegalFPImmediate(APFloat(+0.0)); // FLD0
462 addLegalFPImmediate(APFloat(+1.0)); // FLD1
463 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
464 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
465 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
466 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
467 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
468 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
471 // Long double always uses X87.
472 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
473 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
474 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
476 APFloat TmpFlt(+0.0);
477 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
478 addLegalFPImmediate(TmpFlt); // FLD0
480 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
481 APFloat TmpFlt2(+1.0);
482 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
483 addLegalFPImmediate(TmpFlt2); // FLD1
484 TmpFlt2.changeSign();
485 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
489 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
490 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
493 // Always use a library call for pow.
494 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
495 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
496 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
498 // First set operation action for all vector types to expand. Then we
499 // will selectively turn on ones that can be effectively codegen'd.
500 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
501 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
502 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
503 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
504 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
505 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
506 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
507 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
508 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
509 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
510 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
511 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
512 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
513 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
514 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
515 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
516 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand);
517 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand);
518 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
519 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
520 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
521 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
522 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
523 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
524 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
525 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
526 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
527 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
528 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
542 if (Subtarget->hasMMX()) {
543 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
544 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
545 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
546 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
547 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
549 // FIXME: add MMX packed arithmetics
551 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
552 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
553 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
554 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
556 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
557 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
558 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
559 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
561 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
562 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
564 setOperationAction(ISD::AND, MVT::v8i8, Promote);
565 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
566 setOperationAction(ISD::AND, MVT::v4i16, Promote);
567 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
568 setOperationAction(ISD::AND, MVT::v2i32, Promote);
569 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
570 setOperationAction(ISD::AND, MVT::v1i64, Legal);
572 setOperationAction(ISD::OR, MVT::v8i8, Promote);
573 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
574 setOperationAction(ISD::OR, MVT::v4i16, Promote);
575 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
576 setOperationAction(ISD::OR, MVT::v2i32, Promote);
577 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
578 setOperationAction(ISD::OR, MVT::v1i64, Legal);
580 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
581 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
582 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
583 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
584 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
585 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
586 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
588 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
589 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
590 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
591 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
592 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
594 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
595 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
596 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
598 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
599 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
600 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
601 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
602 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
604 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
605 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
606 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
607 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
609 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
610 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
611 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
612 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
614 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
617 if (Subtarget->hasSSE1()) {
618 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
620 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
621 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
622 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
623 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
624 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
625 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
626 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
627 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
628 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
629 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
630 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
631 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
634 if (Subtarget->hasSSE2()) {
635 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
636 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
637 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
638 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
639 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
641 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
642 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
643 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
644 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
645 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
646 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
647 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
648 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
649 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
650 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
651 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
652 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
653 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
654 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
655 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
657 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
658 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
659 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
660 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
662 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
663 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
664 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
665 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
666 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
668 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
669 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
670 MVT VT = (MVT::SimpleValueType)i;
671 // Do not attempt to custom lower non-power-of-2 vectors
672 if (!isPowerOf2_32(VT.getVectorNumElements()))
674 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
675 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
676 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
678 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
679 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
680 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
681 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
684 if (Subtarget->is64Bit()) {
685 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
689 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
690 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
691 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
692 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
693 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
694 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
695 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
696 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
697 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
698 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
699 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
700 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
703 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
705 // Custom lower v2i64 and v2f64 selects.
706 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
707 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
708 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
709 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
713 if (Subtarget->hasSSE41()) {
714 // FIXME: Do we need to handle scalar-to-vector here?
715 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
716 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
718 // i8 and i16 vectors are custom , because the source register and source
719 // source memory operand types are not the same width. f32 vectors are
720 // custom since the immediate controlling the insert encodes additional
722 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
723 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
724 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
725 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
727 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
728 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
729 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
732 if (Subtarget->is64Bit()) {
733 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
734 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
738 if (Subtarget->hasSSE42()) {
739 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
742 // We want to custom lower some of our intrinsics.
743 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
745 // We have target-specific dag combine patterns for the following nodes:
746 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
747 setTargetDAGCombine(ISD::BUILD_VECTOR);
748 setTargetDAGCombine(ISD::SELECT);
749 setTargetDAGCombine(ISD::STORE);
751 computeRegisterProperties();
753 // FIXME: These should be based on subtarget info. Plus, the values should
754 // be smaller when we are in optimizing for size mode.
755 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
756 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
757 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
758 allowUnalignedMemoryAccesses = true; // x86 supports it!
759 setPrefLoopAlignment(16);
763 MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
768 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
769 /// the desired ByVal argument alignment.
770 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
773 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
774 if (VTy->getBitWidth() == 128)
776 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
777 unsigned EltAlign = 0;
778 getMaxByValAlign(ATy->getElementType(), EltAlign);
779 if (EltAlign > MaxAlign)
781 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
782 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
783 unsigned EltAlign = 0;
784 getMaxByValAlign(STy->getElementType(i), EltAlign);
785 if (EltAlign > MaxAlign)
794 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
795 /// function arguments in the caller parameter area. For X86, aggregates
796 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
797 /// are at 4-byte boundaries.
798 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
799 if (Subtarget->is64Bit())
800 return getTargetData()->getABITypeAlignment(Ty);
802 if (Subtarget->hasSSE1())
803 getMaxByValAlign(Ty, Align);
807 /// getOptimalMemOpType - Returns the target specific optimal type for load
808 /// and store operations as a result of memset, memcpy, and memmove
809 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
812 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
813 bool isSrcConst, bool isSrcStr) const {
814 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
816 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
818 if (Subtarget->is64Bit() && Size >= 8)
824 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
826 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
827 SelectionDAG &DAG) const {
828 if (usesGlobalOffsetTable())
829 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
830 if (!Subtarget->isPICStyleRIPRel())
831 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
835 //===----------------------------------------------------------------------===//
836 // Return Value Calling Convention Implementation
837 //===----------------------------------------------------------------------===//
839 #include "X86GenCallingConv.inc"
841 /// LowerRET - Lower an ISD::RET node.
842 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
843 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
845 SmallVector<CCValAssign, 16> RVLocs;
846 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
847 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
848 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
849 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
851 // If this is the first return lowered for this function, add the regs to the
852 // liveout set for the function.
853 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
854 for (unsigned i = 0; i != RVLocs.size(); ++i)
855 if (RVLocs[i].isRegLoc())
856 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
858 SDValue Chain = Op.getOperand(0);
860 // Handle tail call return.
861 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
862 if (Chain.getOpcode() == X86ISD::TAILCALL) {
863 SDValue TailCall = Chain;
864 SDValue TargetAddress = TailCall.getOperand(1);
865 SDValue StackAdjustment = TailCall.getOperand(2);
866 assert(((TargetAddress.getOpcode() == ISD::Register &&
867 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
868 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
869 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
870 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
871 "Expecting an global address, external symbol, or register");
872 assert(StackAdjustment.getOpcode() == ISD::Constant &&
873 "Expecting a const value");
875 SmallVector<SDValue,8> Operands;
876 Operands.push_back(Chain.getOperand(0));
877 Operands.push_back(TargetAddress);
878 Operands.push_back(StackAdjustment);
879 // Copy registers used by the call. Last operand is a flag so it is not
881 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
882 Operands.push_back(Chain.getOperand(i));
884 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
891 SmallVector<SDValue, 6> RetOps;
892 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
893 // Operand #1 = Bytes To Pop
894 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
896 // Copy the result values into the output registers.
897 for (unsigned i = 0; i != RVLocs.size(); ++i) {
898 CCValAssign &VA = RVLocs[i];
899 assert(VA.isRegLoc() && "Can only return in registers!");
900 SDValue ValToCopy = Op.getOperand(i*2+1);
902 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
903 // the RET instruction and handled by the FP Stackifier.
904 if (RVLocs[i].getLocReg() == X86::ST0 ||
905 RVLocs[i].getLocReg() == X86::ST1) {
906 // If this is a copy from an xmm register to ST(0), use an FPExtend to
907 // change the value to the FP stack register class.
908 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
909 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
910 RetOps.push_back(ValToCopy);
911 // Don't emit a copytoreg.
915 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
916 Flag = Chain.getValue(1);
919 // The x86-64 ABI for returning structs by value requires that we copy
920 // the sret argument into %rax for the return. We saved the argument into
921 // a virtual register in the entry block, so now we copy the value out
923 if (Subtarget->is64Bit() &&
924 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
925 MachineFunction &MF = DAG.getMachineFunction();
926 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
927 unsigned Reg = FuncInfo->getSRetReturnReg();
929 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
930 FuncInfo->setSRetReturnReg(Reg);
932 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
934 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
935 Flag = Chain.getValue(1);
938 RetOps[0] = Chain; // Update chain.
940 // Add the flag if we have it.
942 RetOps.push_back(Flag);
944 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
948 /// LowerCallResult - Lower the result values of an ISD::CALL into the
949 /// appropriate copies out of appropriate physical registers. This assumes that
950 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
951 /// being lowered. The returns a SDNode with the same number of values as the
953 SDNode *X86TargetLowering::
954 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
955 unsigned CallingConv, SelectionDAG &DAG) {
957 // Assign locations to each value returned by this call.
958 SmallVector<CCValAssign, 16> RVLocs;
959 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
960 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
961 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
963 SmallVector<SDValue, 8> ResultVals;
965 // Copy all of the result registers out of their specified physreg.
966 for (unsigned i = 0; i != RVLocs.size(); ++i) {
967 MVT CopyVT = RVLocs[i].getValVT();
969 // If this is a call to a function that returns an fp value on the floating
970 // point stack, but where we prefer to use the value in xmm registers, copy
971 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
972 if ((RVLocs[i].getLocReg() == X86::ST0 ||
973 RVLocs[i].getLocReg() == X86::ST1) &&
974 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
978 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
979 CopyVT, InFlag).getValue(1);
980 SDValue Val = Chain.getValue(0);
981 InFlag = Chain.getValue(2);
983 if (CopyVT != RVLocs[i].getValVT()) {
984 // Round the F80 the right size, which also moves to the appropriate xmm
986 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
987 // This truncation won't change the value.
988 DAG.getIntPtrConstant(1));
991 ResultVals.push_back(Val);
994 // Merge everything together with a MERGE_VALUES node.
995 ResultVals.push_back(Chain);
996 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
997 ResultVals.size()).Val;
1001 //===----------------------------------------------------------------------===//
1002 // C & StdCall & Fast Calling Convention implementation
1003 //===----------------------------------------------------------------------===//
1004 // StdCall calling convention seems to be standard for many Windows' API
1005 // routines and around. It differs from C calling convention just a little:
1006 // callee should clean up the stack, not caller. Symbols should be also
1007 // decorated in some fancy way :) It doesn't support any vector arguments.
1008 // For info on fast calling convention see Fast Calling Convention (tail call)
1009 // implementation LowerX86_32FastCCCallTo.
1011 /// AddLiveIn - This helper function adds the specified physical register to the
1012 /// MachineFunction as a live in value. It also creates a corresponding virtual
1013 /// register for it.
1014 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1015 const TargetRegisterClass *RC) {
1016 assert(RC->contains(PReg) && "Not the correct regclass!");
1017 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1018 MF.getRegInfo().addLiveIn(PReg, VReg);
1022 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1024 static bool CallIsStructReturn(SDValue Op) {
1025 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1029 return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet();
1032 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1033 /// return semantics.
1034 static bool ArgsAreStructReturn(SDValue Op) {
1035 unsigned NumArgs = Op.Val->getNumValues() - 1;
1039 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1042 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1043 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1045 bool X86TargetLowering::IsCalleePop(SDValue Op) {
1046 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1050 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1053 case CallingConv::X86_StdCall:
1054 return !Subtarget->is64Bit();
1055 case CallingConv::X86_FastCall:
1056 return !Subtarget->is64Bit();
1057 case CallingConv::Fast:
1058 return PerformTailCallOpt;
1062 /// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
1063 /// FORMAL_ARGUMENTS node.
1064 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDValue Op) const {
1065 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1067 if (Subtarget->is64Bit()) {
1068 if (Subtarget->isTargetWin64())
1069 return CC_X86_Win64_C;
1071 if (CC == CallingConv::Fast && PerformTailCallOpt)
1072 return CC_X86_64_TailCall;
1078 if (CC == CallingConv::X86_FastCall)
1079 return CC_X86_32_FastCall;
1080 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1081 return CC_X86_32_TailCall;
1086 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1087 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1089 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1090 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1091 if (CC == CallingConv::X86_FastCall)
1093 else if (CC == CallingConv::X86_StdCall)
1099 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1100 /// in a register before calling.
1101 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1102 return !IsTailCall && !Is64Bit &&
1103 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1104 Subtarget->isPICStyleGOT();
1107 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1108 /// address to be loaded in a register.
1110 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1111 return !Is64Bit && IsTailCall &&
1112 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1113 Subtarget->isPICStyleGOT();
1116 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1117 /// by "Src" to address "Dst" with size and alignment information specified by
1118 /// the specific parameter attribute. The copy will be passed as a byval
1119 /// function parameter.
1121 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1122 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1123 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1124 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1125 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1128 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1129 const CCValAssign &VA,
1130 MachineFrameInfo *MFI,
1132 SDValue Root, unsigned i) {
1133 // Create the nodes corresponding to a load from this parameter slot.
1134 ISD::ArgFlagsTy Flags =
1135 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1136 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1137 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1139 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1140 // changed with more analysis.
1141 // In case of tail call optimization mark all arguments mutable. Since they
1142 // could be overwritten by lowering of arguments in case of a tail call.
1143 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1144 VA.getLocMemOffset(), isImmutable);
1145 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1146 if (Flags.isByVal())
1148 return DAG.getLoad(VA.getValVT(), Root, FIN,
1149 PseudoSourceValue::getFixedStack(FI), 0);
1153 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1154 MachineFunction &MF = DAG.getMachineFunction();
1155 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1157 const Function* Fn = MF.getFunction();
1158 if (Fn->hasExternalLinkage() &&
1159 Subtarget->isTargetCygMing() &&
1160 Fn->getName() == "main")
1161 FuncInfo->setForceFramePointer(true);
1163 // Decorate the function name.
1164 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1166 MachineFrameInfo *MFI = MF.getFrameInfo();
1167 SDValue Root = Op.getOperand(0);
1168 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1169 unsigned CC = MF.getFunction()->getCallingConv();
1170 bool Is64Bit = Subtarget->is64Bit();
1171 bool IsWin64 = Subtarget->isTargetWin64();
1173 assert(!(isVarArg && CC == CallingConv::Fast) &&
1174 "Var args not supported with calling convention fastcc");
1176 // Assign locations to all of the incoming arguments.
1177 SmallVector<CCValAssign, 16> ArgLocs;
1178 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1179 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
1181 SmallVector<SDValue, 8> ArgValues;
1182 unsigned LastVal = ~0U;
1183 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1184 CCValAssign &VA = ArgLocs[i];
1185 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1187 assert(VA.getValNo() != LastVal &&
1188 "Don't support value assigned to multiple locs yet");
1189 LastVal = VA.getValNo();
1191 if (VA.isRegLoc()) {
1192 MVT RegVT = VA.getLocVT();
1193 TargetRegisterClass *RC;
1194 if (RegVT == MVT::i32)
1195 RC = X86::GR32RegisterClass;
1196 else if (Is64Bit && RegVT == MVT::i64)
1197 RC = X86::GR64RegisterClass;
1198 else if (RegVT == MVT::f32)
1199 RC = X86::FR32RegisterClass;
1200 else if (RegVT == MVT::f64)
1201 RC = X86::FR64RegisterClass;
1202 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1203 RC = X86::VR128RegisterClass;
1204 else if (RegVT.isVector()) {
1205 assert(RegVT.getSizeInBits() == 64);
1207 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1209 // Darwin calling convention passes MMX values in either GPRs or
1210 // XMMs in x86-64. Other targets pass them in memory.
1211 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1212 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1215 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1220 assert(0 && "Unknown argument type!");
1223 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1224 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1226 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1227 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1229 if (VA.getLocInfo() == CCValAssign::SExt)
1230 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1231 DAG.getValueType(VA.getValVT()));
1232 else if (VA.getLocInfo() == CCValAssign::ZExt)
1233 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1234 DAG.getValueType(VA.getValVT()));
1236 if (VA.getLocInfo() != CCValAssign::Full)
1237 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1239 // Handle MMX values passed in GPRs.
1240 if (Is64Bit && RegVT != VA.getLocVT()) {
1241 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1242 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1243 else if (RC == X86::VR128RegisterClass) {
1244 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1245 DAG.getConstant(0, MVT::i64));
1246 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1250 ArgValues.push_back(ArgValue);
1252 assert(VA.isMemLoc());
1253 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1257 // The x86-64 ABI for returning structs by value requires that we copy
1258 // the sret argument into %rax for the return. Save the argument into
1259 // a virtual register so that we can access it from the return points.
1260 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1261 MachineFunction &MF = DAG.getMachineFunction();
1262 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1263 unsigned Reg = FuncInfo->getSRetReturnReg();
1265 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1266 FuncInfo->setSRetReturnReg(Reg);
1268 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1269 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1272 unsigned StackSize = CCInfo.getNextStackOffset();
1273 // align stack specially for tail calls
1274 if (CC == CallingConv::Fast)
1275 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1277 // If the function takes variable number of arguments, make a frame index for
1278 // the start of the first vararg value... for expansion of llvm.va_start.
1280 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1281 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1284 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1286 // FIXME: We should really autogenerate these arrays
1287 static const unsigned GPR64ArgRegsWin64[] = {
1288 X86::RCX, X86::RDX, X86::R8, X86::R9
1290 static const unsigned XMMArgRegsWin64[] = {
1291 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1293 static const unsigned GPR64ArgRegs64Bit[] = {
1294 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1296 static const unsigned XMMArgRegs64Bit[] = {
1297 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1298 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1300 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1303 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1304 GPR64ArgRegs = GPR64ArgRegsWin64;
1305 XMMArgRegs = XMMArgRegsWin64;
1307 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1308 GPR64ArgRegs = GPR64ArgRegs64Bit;
1309 XMMArgRegs = XMMArgRegs64Bit;
1311 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1313 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1316 // For X86-64, if there are vararg parameters that are passed via
1317 // registers, then we must store them to their spots on the stack so they
1318 // may be loaded by deferencing the result of va_next.
1319 VarArgsGPOffset = NumIntRegs * 8;
1320 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1321 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1322 TotalNumXMMRegs * 16, 16);
1324 // Store the integer parameter registers.
1325 SmallVector<SDValue, 8> MemOps;
1326 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1327 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1328 DAG.getIntPtrConstant(VarArgsGPOffset));
1329 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1330 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1331 X86::GR64RegisterClass);
1332 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1334 DAG.getStore(Val.getValue(1), Val, FIN,
1335 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1336 MemOps.push_back(Store);
1337 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1338 DAG.getIntPtrConstant(8));
1341 // Now store the XMM (fp + vector) parameter registers.
1342 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1343 DAG.getIntPtrConstant(VarArgsFPOffset));
1344 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1345 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1346 X86::VR128RegisterClass);
1347 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1349 DAG.getStore(Val.getValue(1), Val, FIN,
1350 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1351 MemOps.push_back(Store);
1352 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1353 DAG.getIntPtrConstant(16));
1355 if (!MemOps.empty())
1356 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1357 &MemOps[0], MemOps.size());
1361 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1362 // arguments and the arguments after the retaddr has been pushed are
1364 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1365 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1366 (StackSize & 7) == 0)
1369 ArgValues.push_back(Root);
1371 // Some CCs need callee pop.
1372 if (IsCalleePop(Op)) {
1373 BytesToPopOnReturn = StackSize; // Callee pops everything.
1374 BytesCallerReserves = 0;
1376 BytesToPopOnReturn = 0; // Callee pops nothing.
1377 // If this is an sret function, the return should pop the hidden pointer.
1378 if (!Is64Bit && ArgsAreStructReturn(Op))
1379 BytesToPopOnReturn = 4;
1380 BytesCallerReserves = StackSize;
1384 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1385 if (CC == CallingConv::X86_FastCall)
1386 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1389 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1391 // Return the new list of results.
1392 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
1393 ArgValues.size()).getValue(Op.ResNo);
1397 X86TargetLowering::LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG,
1398 const SDValue &StackPtr,
1399 const CCValAssign &VA,
1402 unsigned LocMemOffset = VA.getLocMemOffset();
1403 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1404 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1405 ISD::ArgFlagsTy Flags =
1406 cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags();
1407 if (Flags.isByVal()) {
1408 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1410 return DAG.getStore(Chain, Arg, PtrOff,
1411 PseudoSourceValue::getStack(), LocMemOffset);
1414 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1415 /// optimization is performed and it is required.
1417 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1418 SDValue &OutRetAddr,
1423 if (!IsTailCall || FPDiff==0) return Chain;
1425 // Adjust the Return address stack slot.
1426 MVT VT = getPointerTy();
1427 OutRetAddr = getReturnAddressFrameIndex(DAG);
1428 // Load the "old" Return address.
1429 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1430 return SDValue(OutRetAddr.Val, 1);
1433 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1434 /// optimization is performed and it is required (FPDiff!=0).
1436 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1437 SDValue Chain, SDValue RetAddrFrIdx,
1438 bool Is64Bit, int FPDiff) {
1439 // Store the return address to the appropriate stack slot.
1440 if (!FPDiff) return Chain;
1441 // Calculate the new stack slot for the return address.
1442 int SlotSize = Is64Bit ? 8 : 4;
1443 int NewReturnAddrFI =
1444 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1445 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1446 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1447 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1448 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1452 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1453 MachineFunction &MF = DAG.getMachineFunction();
1454 SDValue Chain = Op.getOperand(0);
1455 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1456 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1457 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1458 && CC == CallingConv::Fast && PerformTailCallOpt;
1459 SDValue Callee = Op.getOperand(4);
1460 bool Is64Bit = Subtarget->is64Bit();
1461 bool IsStructRet = CallIsStructReturn(Op);
1463 assert(!(isVarArg && CC == CallingConv::Fast) &&
1464 "Var args not supported with calling convention fastcc");
1466 // Analyze operands of the call, assigning locations to each operand.
1467 SmallVector<CCValAssign, 16> ArgLocs;
1468 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1469 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
1471 // Get a count of how many bytes are to be pushed on the stack.
1472 unsigned NumBytes = CCInfo.getNextStackOffset();
1473 if (CC == CallingConv::Fast)
1474 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1476 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1477 // arguments and the arguments after the retaddr has been pushed are aligned.
1478 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1479 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1480 (NumBytes & 7) == 0)
1485 // Lower arguments at fp - stackoffset + fpdiff.
1486 unsigned NumBytesCallerPushed =
1487 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1488 FPDiff = NumBytesCallerPushed - NumBytes;
1490 // Set the delta of movement of the returnaddr stackslot.
1491 // But only set if delta is greater than previous delta.
1492 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1493 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1496 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
1498 SDValue RetAddrFrIdx;
1499 // Load return adress for tail calls.
1500 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1503 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1504 SmallVector<SDValue, 8> MemOpChains;
1507 // Walk the register/memloc assignments, inserting copies/loads. In the case
1508 // of tail call optimization arguments are handle later.
1509 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1510 CCValAssign &VA = ArgLocs[i];
1511 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
1512 bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->
1513 getArgFlags().isByVal();
1515 // Promote the value if needed.
1516 switch (VA.getLocInfo()) {
1517 default: assert(0 && "Unknown loc info!");
1518 case CCValAssign::Full: break;
1519 case CCValAssign::SExt:
1520 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1522 case CCValAssign::ZExt:
1523 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1525 case CCValAssign::AExt:
1526 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1530 if (VA.isRegLoc()) {
1532 MVT RegVT = VA.getLocVT();
1533 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1534 switch (VA.getLocReg()) {
1537 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1539 // Special case: passing MMX values in GPR registers.
1540 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1543 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1544 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1545 // Special case: passing MMX values in XMM registers.
1546 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1547 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1548 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1549 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1550 getMOVLMask(2, DAG));
1555 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1557 if (!IsTailCall || (IsTailCall && isByVal)) {
1558 assert(VA.isMemLoc());
1559 if (StackPtr.Val == 0)
1560 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1562 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1568 if (!MemOpChains.empty())
1569 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1570 &MemOpChains[0], MemOpChains.size());
1572 // Build a sequence of copy-to-reg nodes chained together with token chain
1573 // and flag operands which copy the outgoing args into registers.
1575 // Tail call byval lowering might overwrite argument registers so in case of
1576 // tail call optimization the copies to registers are lowered later.
1578 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1579 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1581 InFlag = Chain.getValue(1);
1584 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1586 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1587 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1588 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1590 InFlag = Chain.getValue(1);
1592 // If we are tail calling and generating PIC/GOT style code load the address
1593 // of the callee into ecx. The value in ecx is used as target of the tail
1594 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1595 // calls on PIC/GOT architectures. Normally we would just put the address of
1596 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1597 // restored (since ebx is callee saved) before jumping to the target@PLT.
1598 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1599 // Note: The actual moving to ecx is done further down.
1600 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1601 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1602 !G->getGlobal()->hasProtectedVisibility())
1603 Callee = LowerGlobalAddress(Callee, DAG);
1604 else if (isa<ExternalSymbolSDNode>(Callee))
1605 Callee = LowerExternalSymbol(Callee,DAG);
1608 if (Is64Bit && isVarArg) {
1609 // From AMD64 ABI document:
1610 // For calls that may call functions that use varargs or stdargs
1611 // (prototype-less calls or calls to functions containing ellipsis (...) in
1612 // the declaration) %al is used as hidden argument to specify the number
1613 // of SSE registers used. The contents of %al do not need to match exactly
1614 // the number of registers, but must be an ubound on the number of SSE
1615 // registers used and is in the range 0 - 8 inclusive.
1617 // FIXME: Verify this on Win64
1618 // Count the number of XMM registers allocated.
1619 static const unsigned XMMArgRegs[] = {
1620 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1621 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1623 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1625 Chain = DAG.getCopyToReg(Chain, X86::AL,
1626 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1627 InFlag = Chain.getValue(1);
1631 // For tail calls lower the arguments to the 'real' stack slot.
1633 SmallVector<SDValue, 8> MemOpChains2;
1636 // Do not flag preceeding copytoreg stuff together with the following stuff.
1638 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1639 CCValAssign &VA = ArgLocs[i];
1640 if (!VA.isRegLoc()) {
1641 assert(VA.isMemLoc());
1642 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
1643 SDValue FlagsOp = Op.getOperand(6+2*VA.getValNo());
1644 ISD::ArgFlagsTy Flags =
1645 cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags();
1646 // Create frame index.
1647 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1648 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1649 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1650 FIN = DAG.getFrameIndex(FI, getPointerTy());
1652 if (Flags.isByVal()) {
1653 // Copy relative to framepointer.
1654 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1655 if (StackPtr.Val == 0)
1656 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1657 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1659 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1662 // Store relative to framepointer.
1663 MemOpChains2.push_back(
1664 DAG.getStore(Chain, Arg, FIN,
1665 PseudoSourceValue::getFixedStack(FI), 0));
1670 if (!MemOpChains2.empty())
1671 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1672 &MemOpChains2[0], MemOpChains2.size());
1674 // Copy arguments to their registers.
1675 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1676 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1678 InFlag = Chain.getValue(1);
1682 // Store the return address to the appropriate stack slot.
1683 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1687 // If the callee is a GlobalAddress node (quite common, every direct call is)
1688 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1689 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1690 // We should use extra load for direct calls to dllimported functions in
1692 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1693 getTargetMachine(), true))
1694 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1695 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1696 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1697 } else if (IsTailCall) {
1698 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1700 Chain = DAG.getCopyToReg(Chain,
1701 DAG.getRegister(Opc, getPointerTy()),
1703 Callee = DAG.getRegister(Opc, getPointerTy());
1704 // Add register as live out.
1705 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1708 // Returns a chain & a flag for retval copy to use.
1709 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1710 SmallVector<SDValue, 8> Ops;
1713 Ops.push_back(Chain);
1714 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1715 Ops.push_back(DAG.getIntPtrConstant(0));
1717 Ops.push_back(InFlag);
1718 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1719 InFlag = Chain.getValue(1);
1721 // Returns a chain & a flag for retval copy to use.
1722 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1726 Ops.push_back(Chain);
1727 Ops.push_back(Callee);
1730 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1732 // Add argument registers to the end of the list so that they are known live
1734 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1735 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1736 RegsToPass[i].second.getValueType()));
1738 // Add an implicit use GOT pointer in EBX.
1739 if (!IsTailCall && !Is64Bit &&
1740 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1741 Subtarget->isPICStyleGOT())
1742 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1744 // Add an implicit use of AL for x86 vararg functions.
1745 if (Is64Bit && isVarArg)
1746 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1749 Ops.push_back(InFlag);
1752 assert(InFlag.Val &&
1753 "Flag must be set. Depend on flag being set in LowerRET");
1754 Chain = DAG.getNode(X86ISD::TAILCALL,
1755 Op.Val->getVTList(), &Ops[0], Ops.size());
1757 return SDValue(Chain.Val, Op.ResNo);
1760 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1761 InFlag = Chain.getValue(1);
1763 // Create the CALLSEQ_END node.
1764 unsigned NumBytesForCalleeToPush;
1765 if (IsCalleePop(Op))
1766 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1767 else if (!Is64Bit && IsStructRet)
1768 // If this is is a call to a struct-return function, the callee
1769 // pops the hidden struct pointer, so we have to push it back.
1770 // This is common for Darwin/X86, Linux & Mingw32 targets.
1771 NumBytesForCalleeToPush = 4;
1773 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1775 // Returns a flag for retval copy to use.
1776 Chain = DAG.getCALLSEQ_END(Chain,
1777 DAG.getIntPtrConstant(NumBytes),
1778 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
1780 InFlag = Chain.getValue(1);
1782 // Handle result values, copying them out of physregs into vregs that we
1784 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1788 //===----------------------------------------------------------------------===//
1789 // Fast Calling Convention (tail call) implementation
1790 //===----------------------------------------------------------------------===//
1792 // Like std call, callee cleans arguments, convention except that ECX is
1793 // reserved for storing the tail called function address. Only 2 registers are
1794 // free for argument passing (inreg). Tail call optimization is performed
1796 // * tailcallopt is enabled
1797 // * caller/callee are fastcc
1798 // On X86_64 architecture with GOT-style position independent code only local
1799 // (within module) calls are supported at the moment.
1800 // To keep the stack aligned according to platform abi the function
1801 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1802 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1803 // If a tail called function callee has more arguments than the caller the
1804 // caller needs to make sure that there is room to move the RETADDR to. This is
1805 // achieved by reserving an area the size of the argument delta right after the
1806 // original REtADDR, but before the saved framepointer or the spilled registers
1807 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1819 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1820 /// for a 16 byte align requirement.
1821 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1822 SelectionDAG& DAG) {
1823 if (PerformTailCallOpt) {
1824 MachineFunction &MF = DAG.getMachineFunction();
1825 const TargetMachine &TM = MF.getTarget();
1826 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1827 unsigned StackAlignment = TFI.getStackAlignment();
1828 uint64_t AlignMask = StackAlignment - 1;
1829 int64_t Offset = StackSize;
1830 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1831 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1832 // Number smaller than 12 so just add the difference.
1833 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1835 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1836 Offset = ((~AlignMask) & Offset) + StackAlignment +
1837 (StackAlignment-SlotSize);
1844 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1845 /// following the call is a return. A function is eligible if caller/callee
1846 /// calling conventions match, currently only fastcc supports tail calls, and
1847 /// the function CALL is immediatly followed by a RET.
1848 bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
1850 SelectionDAG& DAG) const {
1851 if (!PerformTailCallOpt)
1854 if (CheckTailCallReturnConstraints(Call, Ret)) {
1855 MachineFunction &MF = DAG.getMachineFunction();
1856 unsigned CallerCC = MF.getFunction()->getCallingConv();
1857 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1858 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1859 SDValue Callee = Call.getOperand(4);
1860 // On x86/32Bit PIC/GOT tail calls are supported.
1861 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1862 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1865 // Can only do local tail calls (in same module, hidden or protected) on
1866 // x86_64 PIC/GOT at the moment.
1867 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1868 return G->getGlobal()->hasHiddenVisibility()
1869 || G->getGlobal()->hasProtectedVisibility();
1876 FastISel *X86TargetLowering::createFastISel(MachineFunction &mf) {
1877 return X86::createFastISel(mf);
1881 //===----------------------------------------------------------------------===//
1882 // Other Lowering Hooks
1883 //===----------------------------------------------------------------------===//
1886 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1887 MachineFunction &MF = DAG.getMachineFunction();
1888 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1889 int ReturnAddrIndex = FuncInfo->getRAIndex();
1891 if (ReturnAddrIndex == 0) {
1892 // Set up a frame object for the return address.
1893 if (Subtarget->is64Bit())
1894 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1896 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1898 FuncInfo->setRAIndex(ReturnAddrIndex);
1901 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1906 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1907 /// specific condition code. It returns a false if it cannot do a direct
1908 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1910 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1911 unsigned &X86CC, SDValue &LHS, SDValue &RHS,
1912 SelectionDAG &DAG) {
1913 X86CC = X86::COND_INVALID;
1915 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1916 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1917 // X > -1 -> X == 0, jump !sign.
1918 RHS = DAG.getConstant(0, RHS.getValueType());
1919 X86CC = X86::COND_NS;
1921 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1922 // X < 0 -> X == 0, jump on sign.
1923 X86CC = X86::COND_S;
1925 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1927 RHS = DAG.getConstant(0, RHS.getValueType());
1928 X86CC = X86::COND_LE;
1933 switch (SetCCOpcode) {
1935 case ISD::SETEQ: X86CC = X86::COND_E; break;
1936 case ISD::SETGT: X86CC = X86::COND_G; break;
1937 case ISD::SETGE: X86CC = X86::COND_GE; break;
1938 case ISD::SETLT: X86CC = X86::COND_L; break;
1939 case ISD::SETLE: X86CC = X86::COND_LE; break;
1940 case ISD::SETNE: X86CC = X86::COND_NE; break;
1941 case ISD::SETULT: X86CC = X86::COND_B; break;
1942 case ISD::SETUGT: X86CC = X86::COND_A; break;
1943 case ISD::SETULE: X86CC = X86::COND_BE; break;
1944 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1947 // On a floating point condition, the flags are set as follows:
1949 // 0 | 0 | 0 | X > Y
1950 // 0 | 0 | 1 | X < Y
1951 // 1 | 0 | 0 | X == Y
1952 // 1 | 1 | 1 | unordered
1954 switch (SetCCOpcode) {
1957 case ISD::SETEQ: X86CC = X86::COND_E; break;
1958 case ISD::SETOLT: Flip = true; // Fallthrough
1960 case ISD::SETGT: X86CC = X86::COND_A; break;
1961 case ISD::SETOLE: Flip = true; // Fallthrough
1963 case ISD::SETGE: X86CC = X86::COND_AE; break;
1964 case ISD::SETUGT: Flip = true; // Fallthrough
1966 case ISD::SETLT: X86CC = X86::COND_B; break;
1967 case ISD::SETUGE: Flip = true; // Fallthrough
1969 case ISD::SETLE: X86CC = X86::COND_BE; break;
1971 case ISD::SETNE: X86CC = X86::COND_NE; break;
1972 case ISD::SETUO: X86CC = X86::COND_P; break;
1973 case ISD::SETO: X86CC = X86::COND_NP; break;
1976 std::swap(LHS, RHS);
1979 return X86CC != X86::COND_INVALID;
1982 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1983 /// code. Current x86 isa includes the following FP cmov instructions:
1984 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1985 static bool hasFPCMov(unsigned X86CC) {
2001 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2002 /// true if Op is undef or if its value falls within the specified range (L, H].
2003 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2004 if (Op.getOpcode() == ISD::UNDEF)
2007 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
2008 return (Val >= Low && Val < Hi);
2011 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2012 /// true if Op is undef or if its value equal to the specified value.
2013 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2014 if (Op.getOpcode() == ISD::UNDEF)
2016 return cast<ConstantSDNode>(Op)->getValue() == Val;
2019 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2020 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2021 bool X86::isPSHUFDMask(SDNode *N) {
2022 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2024 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2027 // Check if the value doesn't reference the second vector.
2028 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2029 SDValue Arg = N->getOperand(i);
2030 if (Arg.getOpcode() == ISD::UNDEF) continue;
2031 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2032 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
2039 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2040 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2041 bool X86::isPSHUFHWMask(SDNode *N) {
2042 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2044 if (N->getNumOperands() != 8)
2047 // Lower quadword copied in order.
2048 for (unsigned i = 0; i != 4; ++i) {
2049 SDValue Arg = N->getOperand(i);
2050 if (Arg.getOpcode() == ISD::UNDEF) continue;
2051 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2052 if (cast<ConstantSDNode>(Arg)->getValue() != i)
2056 // Upper quadword shuffled.
2057 for (unsigned i = 4; i != 8; ++i) {
2058 SDValue Arg = N->getOperand(i);
2059 if (Arg.getOpcode() == ISD::UNDEF) continue;
2060 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2061 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2062 if (Val < 4 || Val > 7)
2069 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2070 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2071 bool X86::isPSHUFLWMask(SDNode *N) {
2072 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2074 if (N->getNumOperands() != 8)
2077 // Upper quadword copied in order.
2078 for (unsigned i = 4; i != 8; ++i)
2079 if (!isUndefOrEqual(N->getOperand(i), i))
2082 // Lower quadword shuffled.
2083 for (unsigned i = 0; i != 4; ++i)
2084 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2090 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2091 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2092 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2093 if (NumElems != 2 && NumElems != 4) return false;
2095 unsigned Half = NumElems / 2;
2096 for (unsigned i = 0; i < Half; ++i)
2097 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2099 for (unsigned i = Half; i < NumElems; ++i)
2100 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2106 bool X86::isSHUFPMask(SDNode *N) {
2107 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2108 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2111 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2112 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2113 /// half elements to come from vector 1 (which would equal the dest.) and
2114 /// the upper half to come from vector 2.
2115 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2116 if (NumOps != 2 && NumOps != 4) return false;
2118 unsigned Half = NumOps / 2;
2119 for (unsigned i = 0; i < Half; ++i)
2120 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2122 for (unsigned i = Half; i < NumOps; ++i)
2123 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2128 static bool isCommutedSHUFP(SDNode *N) {
2129 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2130 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2133 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2134 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2135 bool X86::isMOVHLPSMask(SDNode *N) {
2136 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2138 if (N->getNumOperands() != 4)
2141 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2142 return isUndefOrEqual(N->getOperand(0), 6) &&
2143 isUndefOrEqual(N->getOperand(1), 7) &&
2144 isUndefOrEqual(N->getOperand(2), 2) &&
2145 isUndefOrEqual(N->getOperand(3), 3);
2148 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2149 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2151 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2152 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2154 if (N->getNumOperands() != 4)
2157 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2158 return isUndefOrEqual(N->getOperand(0), 2) &&
2159 isUndefOrEqual(N->getOperand(1), 3) &&
2160 isUndefOrEqual(N->getOperand(2), 2) &&
2161 isUndefOrEqual(N->getOperand(3), 3);
2164 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2165 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2166 bool X86::isMOVLPMask(SDNode *N) {
2167 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2169 unsigned NumElems = N->getNumOperands();
2170 if (NumElems != 2 && NumElems != 4)
2173 for (unsigned i = 0; i < NumElems/2; ++i)
2174 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2177 for (unsigned i = NumElems/2; i < NumElems; ++i)
2178 if (!isUndefOrEqual(N->getOperand(i), i))
2184 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2185 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2187 bool X86::isMOVHPMask(SDNode *N) {
2188 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2190 unsigned NumElems = N->getNumOperands();
2191 if (NumElems != 2 && NumElems != 4)
2194 for (unsigned i = 0; i < NumElems/2; ++i)
2195 if (!isUndefOrEqual(N->getOperand(i), i))
2198 for (unsigned i = 0; i < NumElems/2; ++i) {
2199 SDValue Arg = N->getOperand(i + NumElems/2);
2200 if (!isUndefOrEqual(Arg, i + NumElems))
2207 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2208 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2209 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2210 bool V2IsSplat = false) {
2211 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2214 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2215 SDValue BitI = Elts[i];
2216 SDValue BitI1 = Elts[i+1];
2217 if (!isUndefOrEqual(BitI, j))
2220 if (isUndefOrEqual(BitI1, NumElts))
2223 if (!isUndefOrEqual(BitI1, j + NumElts))
2231 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2232 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2233 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2236 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2237 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2238 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2239 bool V2IsSplat = false) {
2240 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2243 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2244 SDValue BitI = Elts[i];
2245 SDValue BitI1 = Elts[i+1];
2246 if (!isUndefOrEqual(BitI, j + NumElts/2))
2249 if (isUndefOrEqual(BitI1, NumElts))
2252 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2260 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2261 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2262 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2265 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2266 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2268 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2269 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2271 unsigned NumElems = N->getNumOperands();
2272 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2275 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2276 SDValue BitI = N->getOperand(i);
2277 SDValue BitI1 = N->getOperand(i+1);
2279 if (!isUndefOrEqual(BitI, j))
2281 if (!isUndefOrEqual(BitI1, j))
2288 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2289 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2291 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2292 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2294 unsigned NumElems = N->getNumOperands();
2295 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2298 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2299 SDValue BitI = N->getOperand(i);
2300 SDValue BitI1 = N->getOperand(i + 1);
2302 if (!isUndefOrEqual(BitI, j))
2304 if (!isUndefOrEqual(BitI1, j))
2311 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2312 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2313 /// MOVSD, and MOVD, i.e. setting the lowest element.
2314 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2315 if (NumElts != 2 && NumElts != 4)
2318 if (!isUndefOrEqual(Elts[0], NumElts))
2321 for (unsigned i = 1; i < NumElts; ++i) {
2322 if (!isUndefOrEqual(Elts[i], i))
2329 bool X86::isMOVLMask(SDNode *N) {
2330 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2331 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2334 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2335 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2336 /// element of vector 2 and the other elements to come from vector 1 in order.
2337 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2338 bool V2IsSplat = false,
2339 bool V2IsUndef = false) {
2340 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2343 if (!isUndefOrEqual(Ops[0], 0))
2346 for (unsigned i = 1; i < NumOps; ++i) {
2347 SDValue Arg = Ops[i];
2348 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2349 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2350 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2357 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2358 bool V2IsUndef = false) {
2359 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2360 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2361 V2IsSplat, V2IsUndef);
2364 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2365 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2366 bool X86::isMOVSHDUPMask(SDNode *N) {
2367 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2369 if (N->getNumOperands() != 4)
2372 // Expect 1, 1, 3, 3
2373 for (unsigned i = 0; i < 2; ++i) {
2374 SDValue Arg = N->getOperand(i);
2375 if (Arg.getOpcode() == ISD::UNDEF) continue;
2376 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2377 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2378 if (Val != 1) return false;
2382 for (unsigned i = 2; i < 4; ++i) {
2383 SDValue Arg = N->getOperand(i);
2384 if (Arg.getOpcode() == ISD::UNDEF) continue;
2385 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2386 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2387 if (Val != 3) return false;
2391 // Don't use movshdup if it can be done with a shufps.
2395 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2396 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2397 bool X86::isMOVSLDUPMask(SDNode *N) {
2398 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2400 if (N->getNumOperands() != 4)
2403 // Expect 0, 0, 2, 2
2404 for (unsigned i = 0; i < 2; ++i) {
2405 SDValue Arg = N->getOperand(i);
2406 if (Arg.getOpcode() == ISD::UNDEF) continue;
2407 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2408 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2409 if (Val != 0) return false;
2413 for (unsigned i = 2; i < 4; ++i) {
2414 SDValue Arg = N->getOperand(i);
2415 if (Arg.getOpcode() == ISD::UNDEF) continue;
2416 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2417 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2418 if (Val != 2) return false;
2422 // Don't use movshdup if it can be done with a shufps.
2426 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2427 /// specifies a identity operation on the LHS or RHS.
2428 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2429 unsigned NumElems = N->getNumOperands();
2430 for (unsigned i = 0; i < NumElems; ++i)
2431 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2436 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2437 /// a splat of a single element.
2438 static bool isSplatMask(SDNode *N) {
2439 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2441 // This is a splat operation if each element of the permute is the same, and
2442 // if the value doesn't reference the second vector.
2443 unsigned NumElems = N->getNumOperands();
2444 SDValue ElementBase;
2446 for (; i != NumElems; ++i) {
2447 SDValue Elt = N->getOperand(i);
2448 if (isa<ConstantSDNode>(Elt)) {
2454 if (!ElementBase.Val)
2457 for (; i != NumElems; ++i) {
2458 SDValue Arg = N->getOperand(i);
2459 if (Arg.getOpcode() == ISD::UNDEF) continue;
2460 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2461 if (Arg != ElementBase) return false;
2464 // Make sure it is a splat of the first vector operand.
2465 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2468 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2469 /// a splat of a single element and it's a 2 or 4 element mask.
2470 bool X86::isSplatMask(SDNode *N) {
2471 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2473 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2474 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2476 return ::isSplatMask(N);
2479 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2480 /// specifies a splat of zero element.
2481 bool X86::isSplatLoMask(SDNode *N) {
2482 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2484 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2485 if (!isUndefOrEqual(N->getOperand(i), 0))
2490 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2491 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2493 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2494 unsigned NumOperands = N->getNumOperands();
2495 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2497 for (unsigned i = 0; i < NumOperands; ++i) {
2499 SDValue Arg = N->getOperand(NumOperands-i-1);
2500 if (Arg.getOpcode() != ISD::UNDEF)
2501 Val = cast<ConstantSDNode>(Arg)->getValue();
2502 if (Val >= NumOperands) Val -= NumOperands;
2504 if (i != NumOperands - 1)
2511 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2512 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2514 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2516 // 8 nodes, but we only care about the last 4.
2517 for (unsigned i = 7; i >= 4; --i) {
2519 SDValue Arg = N->getOperand(i);
2520 if (Arg.getOpcode() != ISD::UNDEF)
2521 Val = cast<ConstantSDNode>(Arg)->getValue();
2530 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2531 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2533 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2535 // 8 nodes, but we only care about the first 4.
2536 for (int i = 3; i >= 0; --i) {
2538 SDValue Arg = N->getOperand(i);
2539 if (Arg.getOpcode() != ISD::UNDEF)
2540 Val = cast<ConstantSDNode>(Arg)->getValue();
2549 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2550 /// specifies a 8 element shuffle that can be broken into a pair of
2551 /// PSHUFHW and PSHUFLW.
2552 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2553 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2555 if (N->getNumOperands() != 8)
2558 // Lower quadword shuffled.
2559 for (unsigned i = 0; i != 4; ++i) {
2560 SDValue Arg = N->getOperand(i);
2561 if (Arg.getOpcode() == ISD::UNDEF) continue;
2562 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2563 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2568 // Upper quadword shuffled.
2569 for (unsigned i = 4; i != 8; ++i) {
2570 SDValue Arg = N->getOperand(i);
2571 if (Arg.getOpcode() == ISD::UNDEF) continue;
2572 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2573 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2574 if (Val < 4 || Val > 7)
2581 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2582 /// values in ther permute mask.
2583 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2584 SDValue &V2, SDValue &Mask,
2585 SelectionDAG &DAG) {
2586 MVT VT = Op.getValueType();
2587 MVT MaskVT = Mask.getValueType();
2588 MVT EltVT = MaskVT.getVectorElementType();
2589 unsigned NumElems = Mask.getNumOperands();
2590 SmallVector<SDValue, 8> MaskVec;
2592 for (unsigned i = 0; i != NumElems; ++i) {
2593 SDValue Arg = Mask.getOperand(i);
2594 if (Arg.getOpcode() == ISD::UNDEF) {
2595 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2598 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2599 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2601 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2603 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2607 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2608 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2611 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2612 /// the two vector operands have swapped position.
2614 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
2615 MVT MaskVT = Mask.getValueType();
2616 MVT EltVT = MaskVT.getVectorElementType();
2617 unsigned NumElems = Mask.getNumOperands();
2618 SmallVector<SDValue, 8> MaskVec;
2619 for (unsigned i = 0; i != NumElems; ++i) {
2620 SDValue Arg = Mask.getOperand(i);
2621 if (Arg.getOpcode() == ISD::UNDEF) {
2622 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2625 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2626 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2628 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2630 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2632 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2636 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2637 /// match movhlps. The lower half elements should come from upper half of
2638 /// V1 (and in order), and the upper half elements should come from the upper
2639 /// half of V2 (and in order).
2640 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2641 unsigned NumElems = Mask->getNumOperands();
2644 for (unsigned i = 0, e = 2; i != e; ++i)
2645 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2647 for (unsigned i = 2; i != 4; ++i)
2648 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2653 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2654 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2656 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2657 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2658 N = N->getOperand(0).Val;
2659 if (ISD::isNON_EXTLoad(N)) {
2661 *LD = cast<LoadSDNode>(N);
2668 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2669 /// match movlp{s|d}. The lower half elements should come from lower half of
2670 /// V1 (and in order), and the upper half elements should come from the upper
2671 /// half of V2 (and in order). And since V1 will become the source of the
2672 /// MOVLP, it must be either a vector load or a scalar load to vector.
2673 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2674 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2676 // Is V2 is a vector load, don't do this transformation. We will try to use
2677 // load folding shufps op.
2678 if (ISD::isNON_EXTLoad(V2))
2681 unsigned NumElems = Mask->getNumOperands();
2682 if (NumElems != 2 && NumElems != 4)
2684 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2685 if (!isUndefOrEqual(Mask->getOperand(i), i))
2687 for (unsigned i = NumElems/2; i != NumElems; ++i)
2688 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2693 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2695 static bool isSplatVector(SDNode *N) {
2696 if (N->getOpcode() != ISD::BUILD_VECTOR)
2699 SDValue SplatValue = N->getOperand(0);
2700 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2701 if (N->getOperand(i) != SplatValue)
2706 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2708 static bool isUndefShuffle(SDNode *N) {
2709 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2712 SDValue V1 = N->getOperand(0);
2713 SDValue V2 = N->getOperand(1);
2714 SDValue Mask = N->getOperand(2);
2715 unsigned NumElems = Mask.getNumOperands();
2716 for (unsigned i = 0; i != NumElems; ++i) {
2717 SDValue Arg = Mask.getOperand(i);
2718 if (Arg.getOpcode() != ISD::UNDEF) {
2719 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2720 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2722 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2729 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2731 static inline bool isZeroNode(SDValue Elt) {
2732 return ((isa<ConstantSDNode>(Elt) &&
2733 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2734 (isa<ConstantFPSDNode>(Elt) &&
2735 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2738 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2739 /// to an zero vector.
2740 static bool isZeroShuffle(SDNode *N) {
2741 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2744 SDValue V1 = N->getOperand(0);
2745 SDValue V2 = N->getOperand(1);
2746 SDValue Mask = N->getOperand(2);
2747 unsigned NumElems = Mask.getNumOperands();
2748 for (unsigned i = 0; i != NumElems; ++i) {
2749 SDValue Arg = Mask.getOperand(i);
2750 if (Arg.getOpcode() == ISD::UNDEF)
2753 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2754 if (Idx < NumElems) {
2755 unsigned Opc = V1.Val->getOpcode();
2756 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2758 if (Opc != ISD::BUILD_VECTOR ||
2759 !isZeroNode(V1.Val->getOperand(Idx)))
2761 } else if (Idx >= NumElems) {
2762 unsigned Opc = V2.Val->getOpcode();
2763 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2765 if (Opc != ISD::BUILD_VECTOR ||
2766 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2773 /// getZeroVector - Returns a vector of specified type with all zero elements.
2775 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2776 assert(VT.isVector() && "Expected a vector type");
2778 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2779 // type. This ensures they get CSE'd.
2781 if (VT.getSizeInBits() == 64) { // MMX
2782 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2783 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2784 } else if (HasSSE2) { // SSE2
2785 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2786 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2788 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2789 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2791 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2794 /// getOnesVector - Returns a vector of specified type with all bits set.
2796 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
2797 assert(VT.isVector() && "Expected a vector type");
2799 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2800 // type. This ensures they get CSE'd.
2801 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2803 if (VT.getSizeInBits() == 64) // MMX
2804 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2806 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2807 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2811 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2812 /// that point to V2 points to its first element.
2813 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2814 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2816 bool Changed = false;
2817 SmallVector<SDValue, 8> MaskVec;
2818 unsigned NumElems = Mask.getNumOperands();
2819 for (unsigned i = 0; i != NumElems; ++i) {
2820 SDValue Arg = Mask.getOperand(i);
2821 if (Arg.getOpcode() != ISD::UNDEF) {
2822 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2823 if (Val > NumElems) {
2824 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2828 MaskVec.push_back(Arg);
2832 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2833 &MaskVec[0], MaskVec.size());
2837 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2838 /// operation of specified width.
2839 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2840 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2841 MVT BaseVT = MaskVT.getVectorElementType();
2843 SmallVector<SDValue, 8> MaskVec;
2844 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2845 for (unsigned i = 1; i != NumElems; ++i)
2846 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2847 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2850 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2851 /// of specified width.
2852 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2853 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2854 MVT BaseVT = MaskVT.getVectorElementType();
2855 SmallVector<SDValue, 8> MaskVec;
2856 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2857 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2858 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2860 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2863 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2864 /// of specified width.
2865 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2866 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2867 MVT BaseVT = MaskVT.getVectorElementType();
2868 unsigned Half = NumElems/2;
2869 SmallVector<SDValue, 8> MaskVec;
2870 for (unsigned i = 0; i != Half; ++i) {
2871 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2872 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2874 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2877 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2878 /// element #0 of a vector with the specified index, leaving the rest of the
2879 /// elements in place.
2880 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2881 SelectionDAG &DAG) {
2882 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2883 MVT BaseVT = MaskVT.getVectorElementType();
2884 SmallVector<SDValue, 8> MaskVec;
2885 // Element #0 of the result gets the elt we are replacing.
2886 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2887 for (unsigned i = 1; i != NumElems; ++i)
2888 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2889 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2892 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2893 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
2894 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2895 MVT VT = Op.getValueType();
2898 SDValue V1 = Op.getOperand(0);
2899 SDValue Mask = Op.getOperand(2);
2900 unsigned NumElems = Mask.getNumOperands();
2901 // Special handling of v4f32 -> v4i32.
2902 if (VT != MVT::v4f32) {
2903 Mask = getUnpacklMask(NumElems, DAG);
2904 while (NumElems > 4) {
2905 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2908 Mask = getZeroVector(MVT::v4i32, true, DAG);
2911 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
2912 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
2913 DAG.getNode(ISD::UNDEF, PVT), Mask);
2914 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2917 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2918 /// vector of zero or undef vector. This produces a shuffle where the low
2919 /// element of V2 is swizzled into the zero/undef vector, landing at element
2920 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2921 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
2922 bool isZero, bool HasSSE2,
2923 SelectionDAG &DAG) {
2924 MVT VT = V2.getValueType();
2926 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
2927 unsigned NumElems = V2.getValueType().getVectorNumElements();
2928 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2929 MVT EVT = MaskVT.getVectorElementType();
2930 SmallVector<SDValue, 16> MaskVec;
2931 for (unsigned i = 0; i != NumElems; ++i)
2932 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2933 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2935 MaskVec.push_back(DAG.getConstant(i, EVT));
2936 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2937 &MaskVec[0], MaskVec.size());
2938 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2941 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
2942 /// a shuffle that is zero.
2944 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
2945 unsigned NumElems, bool Low,
2946 SelectionDAG &DAG) {
2947 unsigned NumZeros = 0;
2948 for (unsigned i = 0; i < NumElems; ++i) {
2949 unsigned Index = Low ? i : NumElems-i-1;
2950 SDValue Idx = Mask.getOperand(Index);
2951 if (Idx.getOpcode() == ISD::UNDEF) {
2955 SDValue Elt = DAG.getShuffleScalarElt(Op.Val, Index);
2956 if (Elt.Val && isZeroNode(Elt))
2964 /// isVectorShift - Returns true if the shuffle can be implemented as a
2965 /// logical left or right shift of a vector.
2966 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
2967 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
2968 unsigned NumElems = Mask.getNumOperands();
2971 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
2974 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
2979 bool SeenV1 = false;
2980 bool SeenV2 = false;
2981 for (unsigned i = NumZeros; i < NumElems; ++i) {
2982 unsigned Val = isLeft ? (i - NumZeros) : i;
2983 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
2984 if (Idx.getOpcode() == ISD::UNDEF)
2986 unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
2987 if (Index < NumElems)
2996 if (SeenV1 && SeenV2)
2999 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3005 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3007 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3008 unsigned NumNonZero, unsigned NumZero,
3009 SelectionDAG &DAG, TargetLowering &TLI) {
3015 for (unsigned i = 0; i < 16; ++i) {
3016 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3017 if (ThisIsNonZero && First) {
3019 V = getZeroVector(MVT::v8i16, true, DAG);
3021 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3026 SDValue ThisElt(0, 0), LastElt(0, 0);
3027 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3028 if (LastIsNonZero) {
3029 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3031 if (ThisIsNonZero) {
3032 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3033 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3034 ThisElt, DAG.getConstant(8, MVT::i8));
3036 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3041 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3042 DAG.getIntPtrConstant(i/2));
3046 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3049 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3051 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3052 unsigned NumNonZero, unsigned NumZero,
3053 SelectionDAG &DAG, TargetLowering &TLI) {
3059 for (unsigned i = 0; i < 8; ++i) {
3060 bool isNonZero = (NonZeros & (1 << i)) != 0;
3064 V = getZeroVector(MVT::v8i16, true, DAG);
3066 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3069 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3070 DAG.getIntPtrConstant(i));
3077 /// getVShift - Return a vector logical shift node.
3079 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3080 unsigned NumBits, SelectionDAG &DAG,
3081 const TargetLowering &TLI) {
3082 bool isMMX = VT.getSizeInBits() == 64;
3083 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3084 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3085 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3086 return DAG.getNode(ISD::BIT_CONVERT, VT,
3087 DAG.getNode(Opc, ShVT, SrcOp,
3088 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3092 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3093 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3094 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
3095 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3096 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3097 // eliminated on x86-32 hosts.
3098 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3101 if (ISD::isBuildVectorAllOnes(Op.Val))
3102 return getOnesVector(Op.getValueType(), DAG);
3103 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3106 MVT VT = Op.getValueType();
3107 MVT EVT = VT.getVectorElementType();
3108 unsigned EVTBits = EVT.getSizeInBits();
3110 unsigned NumElems = Op.getNumOperands();
3111 unsigned NumZero = 0;
3112 unsigned NumNonZero = 0;
3113 unsigned NonZeros = 0;
3114 bool IsAllConstants = true;
3115 SmallSet<SDValue, 8> Values;
3116 for (unsigned i = 0; i < NumElems; ++i) {
3117 SDValue Elt = Op.getOperand(i);
3118 if (Elt.getOpcode() == ISD::UNDEF)
3121 if (Elt.getOpcode() != ISD::Constant &&
3122 Elt.getOpcode() != ISD::ConstantFP)
3123 IsAllConstants = false;
3124 if (isZeroNode(Elt))
3127 NonZeros |= (1 << i);
3132 if (NumNonZero == 0) {
3133 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3134 return DAG.getNode(ISD::UNDEF, VT);
3137 // Special case for single non-zero, non-undef, element.
3138 if (NumNonZero == 1 && NumElems <= 4) {
3139 unsigned Idx = CountTrailingZeros_32(NonZeros);
3140 SDValue Item = Op.getOperand(Idx);
3142 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3143 // the value are obviously zero, truncate the value to i32 and do the
3144 // insertion that way. Only do this if the value is non-constant or if the
3145 // value is a constant being inserted into element 0. It is cheaper to do
3146 // a constant pool load than it is to do a movd + shuffle.
3147 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3148 (!IsAllConstants || Idx == 0)) {
3149 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3150 // Handle MMX and SSE both.
3151 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3152 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3154 // Truncate the value (which may itself be a constant) to i32, and
3155 // convert it to a vector with movd (S2V+shuffle to zero extend).
3156 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3157 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3158 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3159 Subtarget->hasSSE2(), DAG);
3161 // Now we have our 32-bit value zero extended in the low element of
3162 // a vector. If Idx != 0, swizzle it into place.
3165 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3166 getSwapEltZeroMask(VecElts, Idx, DAG)
3168 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3170 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3174 // If we have a constant or non-constant insertion into the low element of
3175 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3176 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3177 // depending on what the source datatype is. Because we can only get here
3178 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3180 // Don't do this for i64 values on x86-32.
3181 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3182 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3183 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3184 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3185 Subtarget->hasSSE2(), DAG);
3188 // Is it a vector logical left shift?
3189 if (NumElems == 2 && Idx == 1 &&
3190 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3191 unsigned NumBits = VT.getSizeInBits();
3192 return getVShift(true, VT,
3193 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3194 NumBits/2, DAG, *this);
3197 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3200 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3201 // is a non-constant being inserted into an element other than the low one,
3202 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3203 // movd/movss) to move this into the low element, then shuffle it into
3205 if (EVTBits == 32) {
3206 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3208 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3209 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3210 Subtarget->hasSSE2(), DAG);
3211 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3212 MVT MaskEVT = MaskVT.getVectorElementType();
3213 SmallVector<SDValue, 8> MaskVec;
3214 for (unsigned i = 0; i < NumElems; i++)
3215 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3216 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3217 &MaskVec[0], MaskVec.size());
3218 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3219 DAG.getNode(ISD::UNDEF, VT), Mask);
3223 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3224 if (Values.size() == 1)
3227 // A vector full of immediates; various special cases are already
3228 // handled, so this is best done with a single constant-pool load.
3232 // Let legalizer expand 2-wide build_vectors.
3233 if (EVTBits == 64) {
3234 if (NumNonZero == 1) {
3235 // One half is zero or undef.
3236 unsigned Idx = CountTrailingZeros_32(NonZeros);
3237 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3238 Op.getOperand(Idx));
3239 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3240 Subtarget->hasSSE2(), DAG);
3245 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3246 if (EVTBits == 8 && NumElems == 16) {
3247 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3249 if (V.Val) return V;
3252 if (EVTBits == 16 && NumElems == 8) {
3253 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3255 if (V.Val) return V;
3258 // If element VT is == 32 bits, turn it into a number of shuffles.
3259 SmallVector<SDValue, 8> V;
3261 if (NumElems == 4 && NumZero > 0) {
3262 for (unsigned i = 0; i < 4; ++i) {
3263 bool isZero = !(NonZeros & (1 << i));
3265 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3267 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3270 for (unsigned i = 0; i < 2; ++i) {
3271 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3274 V[i] = V[i*2]; // Must be a zero vector.
3277 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3278 getMOVLMask(NumElems, DAG));
3281 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3282 getMOVLMask(NumElems, DAG));
3285 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3286 getUnpacklMask(NumElems, DAG));
3291 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3292 MVT EVT = MaskVT.getVectorElementType();
3293 SmallVector<SDValue, 8> MaskVec;
3294 bool Reverse = (NonZeros & 0x3) == 2;
3295 for (unsigned i = 0; i < 2; ++i)
3297 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3299 MaskVec.push_back(DAG.getConstant(i, EVT));
3300 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3301 for (unsigned i = 0; i < 2; ++i)
3303 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3305 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3306 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3307 &MaskVec[0], MaskVec.size());
3308 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3311 if (Values.size() > 2) {
3312 // Expand into a number of unpckl*.
3314 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3315 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3316 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3317 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
3318 for (unsigned i = 0; i < NumElems; ++i)
3319 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3321 while (NumElems != 0) {
3322 for (unsigned i = 0; i < NumElems; ++i)
3323 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3334 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3335 SDValue PermMask, SelectionDAG &DAG,
3336 TargetLowering &TLI) {
3338 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3339 MVT MaskEVT = MaskVT.getVectorElementType();
3340 MVT PtrVT = TLI.getPointerTy();
3341 SmallVector<SDValue, 8> MaskElts(PermMask.Val->op_begin(),
3342 PermMask.Val->op_end());
3344 // First record which half of which vector the low elements come from.
3345 SmallVector<unsigned, 4> LowQuad(4);
3346 for (unsigned i = 0; i < 4; ++i) {
3347 SDValue Elt = MaskElts[i];
3348 if (Elt.getOpcode() == ISD::UNDEF)
3350 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3351 int QuadIdx = EltIdx / 4;
3354 int BestLowQuad = -1;
3355 unsigned MaxQuad = 1;
3356 for (unsigned i = 0; i < 4; ++i) {
3357 if (LowQuad[i] > MaxQuad) {
3359 MaxQuad = LowQuad[i];
3363 // Record which half of which vector the high elements come from.
3364 SmallVector<unsigned, 4> HighQuad(4);
3365 for (unsigned i = 4; i < 8; ++i) {
3366 SDValue Elt = MaskElts[i];
3367 if (Elt.getOpcode() == ISD::UNDEF)
3369 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3370 int QuadIdx = EltIdx / 4;
3371 ++HighQuad[QuadIdx];
3373 int BestHighQuad = -1;
3375 for (unsigned i = 0; i < 4; ++i) {
3376 if (HighQuad[i] > MaxQuad) {
3378 MaxQuad = HighQuad[i];
3382 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3383 if (BestLowQuad != -1 || BestHighQuad != -1) {
3384 // First sort the 4 chunks in order using shufpd.
3385 SmallVector<SDValue, 8> MaskVec;
3386 if (BestLowQuad != -1)
3387 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3389 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3390 if (BestHighQuad != -1)
3391 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3393 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3394 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3395 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3396 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3397 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3398 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3400 // Now sort high and low parts separately.
3401 BitVector InOrder(8);
3402 if (BestLowQuad != -1) {
3403 // Sort lower half in order using PSHUFLW.
3405 bool AnyOutOrder = false;
3406 for (unsigned i = 0; i != 4; ++i) {
3407 SDValue Elt = MaskElts[i];
3408 if (Elt.getOpcode() == ISD::UNDEF) {
3409 MaskVec.push_back(Elt);
3412 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3415 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3416 // If this element is in the right place after this shuffle, then
3418 if ((int)(EltIdx / 4) == BestLowQuad)
3423 for (unsigned i = 4; i != 8; ++i)
3424 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3425 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3426 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3430 if (BestHighQuad != -1) {
3431 // Sort high half in order using PSHUFHW if possible.
3433 for (unsigned i = 0; i != 4; ++i)
3434 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3435 bool AnyOutOrder = false;
3436 for (unsigned i = 4; i != 8; ++i) {
3437 SDValue Elt = MaskElts[i];
3438 if (Elt.getOpcode() == ISD::UNDEF) {
3439 MaskVec.push_back(Elt);
3442 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3445 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3446 // If this element is in the right place after this shuffle, then
3448 if ((int)(EltIdx / 4) == BestHighQuad)
3453 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3454 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3458 // The other elements are put in the right place using pextrw and pinsrw.
3459 for (unsigned i = 0; i != 8; ++i) {
3462 SDValue Elt = MaskElts[i];
3463 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3464 SDValue ExtOp = (EltIdx < 8)
3465 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3466 DAG.getConstant(EltIdx, PtrVT))
3467 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3468 DAG.getConstant(EltIdx - 8, PtrVT));
3469 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3470 DAG.getConstant(i, PtrVT));
3475 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3476 ///as few as possible.
3477 // First, let's find out how many elements are already in the right order.
3478 unsigned V1InOrder = 0;
3479 unsigned V1FromV1 = 0;
3480 unsigned V2InOrder = 0;
3481 unsigned V2FromV2 = 0;
3482 SmallVector<SDValue, 8> V1Elts;
3483 SmallVector<SDValue, 8> V2Elts;
3484 for (unsigned i = 0; i < 8; ++i) {
3485 SDValue Elt = MaskElts[i];
3486 if (Elt.getOpcode() == ISD::UNDEF) {
3487 V1Elts.push_back(Elt);
3488 V2Elts.push_back(Elt);
3493 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3495 V1Elts.push_back(Elt);
3496 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3498 } else if (EltIdx == i+8) {
3499 V1Elts.push_back(Elt);
3500 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3502 } else if (EltIdx < 8) {
3503 V1Elts.push_back(Elt);
3506 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3511 if (V2InOrder > V1InOrder) {
3512 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3514 std::swap(V1Elts, V2Elts);
3515 std::swap(V1FromV1, V2FromV2);
3518 if ((V1FromV1 + V1InOrder) != 8) {
3519 // Some elements are from V2.
3521 // If there are elements that are from V1 but out of place,
3522 // then first sort them in place
3523 SmallVector<SDValue, 8> MaskVec;
3524 for (unsigned i = 0; i < 8; ++i) {
3525 SDValue Elt = V1Elts[i];
3526 if (Elt.getOpcode() == ISD::UNDEF) {
3527 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3530 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3532 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3534 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3536 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3537 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3541 for (unsigned i = 0; i < 8; ++i) {
3542 SDValue Elt = V1Elts[i];
3543 if (Elt.getOpcode() == ISD::UNDEF)
3545 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3548 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3549 DAG.getConstant(EltIdx - 8, PtrVT));
3550 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3551 DAG.getConstant(i, PtrVT));
3555 // All elements are from V1.
3557 for (unsigned i = 0; i < 8; ++i) {
3558 SDValue Elt = V1Elts[i];
3559 if (Elt.getOpcode() == ISD::UNDEF)
3561 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3562 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3563 DAG.getConstant(EltIdx, PtrVT));
3564 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3565 DAG.getConstant(i, PtrVT));
3571 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3572 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3573 /// done when every pair / quad of shuffle mask elements point to elements in
3574 /// the right sequence. e.g.
3575 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3577 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3579 SDValue PermMask, SelectionDAG &DAG,
3580 TargetLowering &TLI) {
3581 unsigned NumElems = PermMask.getNumOperands();
3582 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3583 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3584 MVT MaskEltVT = MaskVT.getVectorElementType();
3586 switch (VT.getSimpleVT()) {
3587 default: assert(false && "Unexpected!");
3588 case MVT::v4f32: NewVT = MVT::v2f64; break;
3589 case MVT::v4i32: NewVT = MVT::v2i64; break;
3590 case MVT::v8i16: NewVT = MVT::v4i32; break;
3591 case MVT::v16i8: NewVT = MVT::v4i32; break;
3594 if (NewWidth == 2) {
3600 unsigned Scale = NumElems / NewWidth;
3601 SmallVector<SDValue, 8> MaskVec;
3602 for (unsigned i = 0; i < NumElems; i += Scale) {
3603 unsigned StartIdx = ~0U;
3604 for (unsigned j = 0; j < Scale; ++j) {
3605 SDValue Elt = PermMask.getOperand(i+j);
3606 if (Elt.getOpcode() == ISD::UNDEF)
3608 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3609 if (StartIdx == ~0U)
3610 StartIdx = EltIdx - (EltIdx % Scale);
3611 if (EltIdx != StartIdx + j)
3614 if (StartIdx == ~0U)
3615 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
3617 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3620 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3621 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3622 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3623 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3624 &MaskVec[0], MaskVec.size()));
3627 /// getVZextMovL - Return a zero-extending vector move low node.
3629 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3630 SDValue SrcOp, SelectionDAG &DAG,
3631 const X86Subtarget *Subtarget) {
3632 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3633 LoadSDNode *LD = NULL;
3634 if (!isScalarLoadToVector(SrcOp.Val, &LD))
3635 LD = dyn_cast<LoadSDNode>(SrcOp);
3637 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3639 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3640 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3641 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3642 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3643 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3645 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3646 return DAG.getNode(ISD::BIT_CONVERT, VT,
3647 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3648 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3649 SrcOp.getOperand(0).getOperand(0))));
3654 return DAG.getNode(ISD::BIT_CONVERT, VT,
3655 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3656 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3659 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3662 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3663 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
3664 MVT MaskVT = PermMask.getValueType();
3665 MVT MaskEVT = MaskVT.getVectorElementType();
3666 SmallVector<std::pair<int, int>, 8> Locs;
3668 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3671 for (unsigned i = 0; i != 4; ++i) {
3672 SDValue Elt = PermMask.getOperand(i);
3673 if (Elt.getOpcode() == ISD::UNDEF) {
3674 Locs[i] = std::make_pair(-1, -1);
3676 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3677 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3679 Locs[i] = std::make_pair(0, NumLo);
3683 Locs[i] = std::make_pair(1, NumHi);
3685 Mask1[2+NumHi] = Elt;
3691 if (NumLo <= 2 && NumHi <= 2) {
3692 // If no more than two elements come from either vector. This can be
3693 // implemented with two shuffles. First shuffle gather the elements.
3694 // The second shuffle, which takes the first shuffle as both of its
3695 // vector operands, put the elements into the right order.
3696 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3697 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3698 &Mask1[0], Mask1.size()));
3700 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3701 for (unsigned i = 0; i != 4; ++i) {
3702 if (Locs[i].first == -1)
3705 unsigned Idx = (i < 2) ? 0 : 4;
3706 Idx += Locs[i].first * 2 + Locs[i].second;
3707 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3711 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3712 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3713 &Mask2[0], Mask2.size()));
3714 } else if (NumLo == 3 || NumHi == 3) {
3715 // Otherwise, we must have three elements from one vector, call it X, and
3716 // one element from the other, call it Y. First, use a shufps to build an
3717 // intermediate vector with the one element from Y and the element from X
3718 // that will be in the same half in the final destination (the indexes don't
3719 // matter). Then, use a shufps to build the final vector, taking the half
3720 // containing the element from Y from the intermediate, and the other half
3723 // Normalize it so the 3 elements come from V1.
3724 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3728 // Find the element from V2.
3730 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3731 SDValue Elt = PermMask.getOperand(HiIndex);
3732 if (Elt.getOpcode() == ISD::UNDEF)
3734 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3739 Mask1[0] = PermMask.getOperand(HiIndex);
3740 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3741 Mask1[2] = PermMask.getOperand(HiIndex^1);
3742 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3743 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3744 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3747 Mask1[0] = PermMask.getOperand(0);
3748 Mask1[1] = PermMask.getOperand(1);
3749 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3750 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3751 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3752 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3754 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3755 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3756 Mask1[2] = PermMask.getOperand(2);
3757 Mask1[3] = PermMask.getOperand(3);
3758 if (Mask1[2].getOpcode() != ISD::UNDEF)
3759 Mask1[2] = DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getValue()+4,
3761 if (Mask1[3].getOpcode() != ISD::UNDEF)
3762 Mask1[3] = DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getValue()+4,
3764 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3765 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3769 // Break it into (shuffle shuffle_hi, shuffle_lo).
3771 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3772 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3773 SmallVector<SDValue,8> *MaskPtr = &LoMask;
3774 unsigned MaskIdx = 0;
3777 for (unsigned i = 0; i != 4; ++i) {
3784 SDValue Elt = PermMask.getOperand(i);
3785 if (Elt.getOpcode() == ISD::UNDEF) {
3786 Locs[i] = std::make_pair(-1, -1);
3787 } else if (cast<ConstantSDNode>(Elt)->getValue() < 4) {
3788 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3789 (*MaskPtr)[LoIdx] = Elt;
3792 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3793 (*MaskPtr)[HiIdx] = Elt;
3798 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3799 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3800 &LoMask[0], LoMask.size()));
3801 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3802 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3803 &HiMask[0], HiMask.size()));
3804 SmallVector<SDValue, 8> MaskOps;
3805 for (unsigned i = 0; i != 4; ++i) {
3806 if (Locs[i].first == -1) {
3807 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3809 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3810 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3813 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3814 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3815 &MaskOps[0], MaskOps.size()));
3819 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3820 SDValue V1 = Op.getOperand(0);
3821 SDValue V2 = Op.getOperand(1);
3822 SDValue PermMask = Op.getOperand(2);
3823 MVT VT = Op.getValueType();
3824 unsigned NumElems = PermMask.getNumOperands();
3825 bool isMMX = VT.getSizeInBits() == 64;
3826 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3827 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3828 bool V1IsSplat = false;
3829 bool V2IsSplat = false;
3831 if (isUndefShuffle(Op.Val))
3832 return DAG.getNode(ISD::UNDEF, VT);
3834 if (isZeroShuffle(Op.Val))
3835 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3837 if (isIdentityMask(PermMask.Val))
3839 else if (isIdentityMask(PermMask.Val, true))
3842 if (isSplatMask(PermMask.Val)) {
3843 if (isMMX || NumElems < 4) return Op;
3844 // Promote it to a v4{if}32 splat.
3845 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
3848 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3850 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3851 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3853 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3854 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3855 // FIXME: Figure out a cleaner way to do this.
3856 // Try to make use of movq to zero out the top part.
3857 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3858 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3861 SDValue NewV1 = NewOp.getOperand(0);
3862 SDValue NewV2 = NewOp.getOperand(1);
3863 SDValue NewMask = NewOp.getOperand(2);
3864 if (isCommutedMOVL(NewMask.Val, true, false)) {
3865 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3866 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
3869 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3870 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3872 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3873 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
3878 // Check if this can be converted into a logical shift.
3879 bool isLeft = false;
3882 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
3883 if (isShift && ShVal.hasOneUse()) {
3884 // If the shifted value has multiple uses, it may be cheaper to use
3885 // v_set0 + movlhps or movhlps, etc.
3886 MVT EVT = VT.getVectorElementType();
3887 ShAmt *= EVT.getSizeInBits();
3888 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3891 if (X86::isMOVLMask(PermMask.Val)) {
3894 if (ISD::isBuildVectorAllZeros(V1.Val))
3895 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
3900 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.Val) ||
3901 X86::isMOVSLDUPMask(PermMask.Val) ||
3902 X86::isMOVHLPSMask(PermMask.Val) ||
3903 X86::isMOVHPMask(PermMask.Val) ||
3904 X86::isMOVLPMask(PermMask.Val)))
3907 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3908 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3909 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3912 // No better options. Use a vshl / vsrl.
3913 MVT EVT = VT.getVectorElementType();
3914 ShAmt *= EVT.getSizeInBits();
3915 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3918 bool Commuted = false;
3919 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3920 // 1,1,1,1 -> v8i16 though.
3921 V1IsSplat = isSplatVector(V1.Val);
3922 V2IsSplat = isSplatVector(V2.Val);
3924 // Canonicalize the splat or undef, if present, to be on the RHS.
3925 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3926 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3927 std::swap(V1IsSplat, V2IsSplat);
3928 std::swap(V1IsUndef, V2IsUndef);
3932 // FIXME: Figure out a cleaner way to do this.
3933 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3934 if (V2IsUndef) return V1;
3935 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3937 // V2 is a splat, so the mask may be malformed. That is, it may point
3938 // to any V2 element. The instruction selectior won't like this. Get
3939 // a corrected mask and commute to form a proper MOVS{S|D}.
3940 SDValue NewMask = getMOVLMask(NumElems, DAG);
3941 if (NewMask.Val != PermMask.Val)
3942 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3947 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3948 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3949 X86::isUNPCKLMask(PermMask.Val) ||
3950 X86::isUNPCKHMask(PermMask.Val))
3954 // Normalize mask so all entries that point to V2 points to its first
3955 // element then try to match unpck{h|l} again. If match, return a
3956 // new vector_shuffle with the corrected mask.
3957 SDValue NewMask = NormalizeMask(PermMask, DAG);
3958 if (NewMask.Val != PermMask.Val) {
3959 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3960 SDValue NewMask = getUnpacklMask(NumElems, DAG);
3961 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3962 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3963 SDValue NewMask = getUnpackhMask(NumElems, DAG);
3964 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3969 // Normalize the node to match x86 shuffle ops if needed
3970 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3971 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3974 // Commute is back and try unpck* again.
3975 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3976 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3977 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3978 X86::isUNPCKLMask(PermMask.Val) ||
3979 X86::isUNPCKHMask(PermMask.Val))
3983 // Try PSHUF* first, then SHUFP*.
3984 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
3985 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3986 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.Val)) {
3987 if (V2.getOpcode() != ISD::UNDEF)
3988 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3989 DAG.getNode(ISD::UNDEF, VT), PermMask);
3994 if (Subtarget->hasSSE2() &&
3995 (X86::isPSHUFDMask(PermMask.Val) ||
3996 X86::isPSHUFHWMask(PermMask.Val) ||
3997 X86::isPSHUFLWMask(PermMask.Val))) {
3999 if (VT == MVT::v4f32) {
4001 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4002 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4003 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4004 } else if (V2.getOpcode() != ISD::UNDEF)
4005 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4006 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4008 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
4012 // Binary or unary shufps.
4013 if (X86::isSHUFPMask(PermMask.Val) ||
4014 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.Val)))
4018 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4019 if (VT == MVT::v8i16) {
4020 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
4025 // Handle all 4 wide cases with a number of shuffles except for MMX.
4026 if (NumElems == 4 && !isMMX)
4027 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
4033 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4034 SelectionDAG &DAG) {
4035 MVT VT = Op.getValueType();
4036 if (VT.getSizeInBits() == 8) {
4037 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
4038 Op.getOperand(0), Op.getOperand(1));
4039 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4040 DAG.getValueType(VT));
4041 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4042 } else if (VT.getSizeInBits() == 16) {
4043 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
4044 Op.getOperand(0), Op.getOperand(1));
4045 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4046 DAG.getValueType(VT));
4047 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4048 } else if (VT == MVT::f32) {
4049 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4050 // the result back to FR32 register. It's only worth matching if the
4051 // result has a single use which is a store or a bitcast to i32.
4052 if (!Op.hasOneUse())
4054 SDNode *User = *Op.Val->use_begin();
4055 if (User->getOpcode() != ISD::STORE &&
4056 (User->getOpcode() != ISD::BIT_CONVERT ||
4057 User->getValueType(0) != MVT::i32))
4059 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4060 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4062 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
4069 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4070 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4073 if (Subtarget->hasSSE41()) {
4074 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4079 MVT VT = Op.getValueType();
4080 // TODO: handle v16i8.
4081 if (VT.getSizeInBits() == 16) {
4082 SDValue Vec = Op.getOperand(0);
4083 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4085 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4086 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4087 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4089 // Transform it so it match pextrw which produces a 32-bit result.
4090 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4091 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4092 Op.getOperand(0), Op.getOperand(1));
4093 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4094 DAG.getValueType(VT));
4095 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4096 } else if (VT.getSizeInBits() == 32) {
4097 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4100 // SHUFPS the element to the lowest double word, then movss.
4101 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4102 SmallVector<SDValue, 8> IdxVec;
4104 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4106 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4108 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4110 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4111 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4112 &IdxVec[0], IdxVec.size());
4113 SDValue Vec = Op.getOperand(0);
4114 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4115 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4116 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4117 DAG.getIntPtrConstant(0));
4118 } else if (VT.getSizeInBits() == 64) {
4119 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4120 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4121 // to match extract_elt for f64.
4122 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4126 // UNPCKHPD the element to the lowest double word, then movsd.
4127 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4128 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4129 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4130 SmallVector<SDValue, 8> IdxVec;
4131 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4133 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4134 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4135 &IdxVec[0], IdxVec.size());
4136 SDValue Vec = Op.getOperand(0);
4137 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4138 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4139 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4140 DAG.getIntPtrConstant(0));
4147 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4148 MVT VT = Op.getValueType();
4149 MVT EVT = VT.getVectorElementType();
4151 SDValue N0 = Op.getOperand(0);
4152 SDValue N1 = Op.getOperand(1);
4153 SDValue N2 = Op.getOperand(2);
4155 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4156 isa<ConstantSDNode>(N2)) {
4157 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4159 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4161 if (N1.getValueType() != MVT::i32)
4162 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4163 if (N2.getValueType() != MVT::i32)
4164 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
4165 return DAG.getNode(Opc, VT, N0, N1, N2);
4166 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4167 // Bits [7:6] of the constant are the source select. This will always be
4168 // zero here. The DAG Combiner may combine an extract_elt index into these
4169 // bits. For example (insert (extract, 3), 2) could be matched by putting
4170 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4171 // Bits [5:4] of the constant are the destination select. This is the
4172 // value of the incoming immediate.
4173 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4174 // combine either bitwise AND or insert of float 0.0 to set these bits.
4175 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4);
4176 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4182 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4183 MVT VT = Op.getValueType();
4184 MVT EVT = VT.getVectorElementType();
4186 if (Subtarget->hasSSE41())
4187 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4192 SDValue N0 = Op.getOperand(0);
4193 SDValue N1 = Op.getOperand(1);
4194 SDValue N2 = Op.getOperand(2);
4196 if (EVT.getSizeInBits() == 16) {
4197 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4198 // as its second argument.
4199 if (N1.getValueType() != MVT::i32)
4200 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4201 if (N2.getValueType() != MVT::i32)
4202 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
4203 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4209 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4210 if (Op.getValueType() == MVT::v2f32)
4211 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4212 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4213 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4214 Op.getOperand(0))));
4216 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4217 MVT VT = MVT::v2i32;
4218 switch (Op.getValueType().getSimpleVT()) {
4225 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4226 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4229 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4230 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4231 // one of the above mentioned nodes. It has to be wrapped because otherwise
4232 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4233 // be used to form addressing mode. These wrapped nodes will be selected
4236 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4237 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4238 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4240 CP->getAlignment());
4241 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4242 // With PIC, the address is actually $g + Offset.
4243 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4244 !Subtarget->isPICStyleRIPRel()) {
4245 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4246 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4254 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4255 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4256 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
4257 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4258 // With PIC, the address is actually $g + Offset.
4259 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4260 !Subtarget->isPICStyleRIPRel()) {
4261 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4262 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4266 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4267 // load the value at address GV, not the value of GV itself. This means that
4268 // the GlobalAddress must be in the base or index register of the address, not
4269 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4270 // The same applies for external symbols during PIC codegen
4271 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
4272 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4273 PseudoSourceValue::getGOT(), 0);
4278 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4280 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4283 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4284 DAG.getNode(X86ISD::GlobalBaseReg,
4286 InFlag = Chain.getValue(1);
4288 // emit leal symbol@TLSGD(,%ebx,1), %eax
4289 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4290 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4291 GA->getValueType(0),
4293 SDValue Ops[] = { Chain, TGA, InFlag };
4294 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4295 InFlag = Result.getValue(2);
4296 Chain = Result.getValue(1);
4298 // call ___tls_get_addr. This function receives its argument in
4299 // the register EAX.
4300 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4301 InFlag = Chain.getValue(1);
4303 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4304 SDValue Ops1[] = { Chain,
4305 DAG.getTargetExternalSymbol("___tls_get_addr",
4307 DAG.getRegister(X86::EAX, PtrVT),
4308 DAG.getRegister(X86::EBX, PtrVT),
4310 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4311 InFlag = Chain.getValue(1);
4313 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4316 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4318 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4320 SDValue InFlag, Chain;
4322 // emit leaq symbol@TLSGD(%rip), %rdi
4323 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4324 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4325 GA->getValueType(0),
4327 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4328 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4329 Chain = Result.getValue(1);
4330 InFlag = Result.getValue(2);
4332 // call __tls_get_addr. This function receives its argument in
4333 // the register RDI.
4334 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4335 InFlag = Chain.getValue(1);
4337 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4338 SDValue Ops1[] = { Chain,
4339 DAG.getTargetExternalSymbol("__tls_get_addr",
4341 DAG.getRegister(X86::RDI, PtrVT),
4343 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4344 InFlag = Chain.getValue(1);
4346 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4349 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4350 // "local exec" model.
4351 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4353 // Get the Thread Pointer
4354 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4355 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4357 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4358 GA->getValueType(0),
4360 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4362 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4363 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4364 PseudoSourceValue::getGOT(), 0);
4366 // The address of the thread local variable is the add of the thread
4367 // pointer with the offset of the variable.
4368 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4372 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4373 // TODO: implement the "local dynamic" model
4374 // TODO: implement the "initial exec"model for pic executables
4375 assert(Subtarget->isTargetELF() &&
4376 "TLS not implemented for non-ELF targets");
4377 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4378 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4379 // otherwise use the "Local Exec"TLS Model
4380 if (Subtarget->is64Bit()) {
4381 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4383 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4384 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4386 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4391 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4392 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4393 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4394 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4395 // With PIC, the address is actually $g + Offset.
4396 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4397 !Subtarget->isPICStyleRIPRel()) {
4398 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4399 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4406 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4407 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4408 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4409 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4410 // With PIC, the address is actually $g + Offset.
4411 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4412 !Subtarget->isPICStyleRIPRel()) {
4413 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4414 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4421 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4422 /// take a 2 x i32 value to shift plus a shift amount.
4423 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4424 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4425 MVT VT = Op.getValueType();
4426 unsigned VTBits = VT.getSizeInBits();
4427 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4428 SDValue ShOpLo = Op.getOperand(0);
4429 SDValue ShOpHi = Op.getOperand(1);
4430 SDValue ShAmt = Op.getOperand(2);
4431 SDValue Tmp1 = isSRA ?
4432 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4433 DAG.getConstant(0, VT);
4436 if (Op.getOpcode() == ISD::SHL_PARTS) {
4437 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4438 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4440 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4441 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4444 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4445 DAG.getConstant(VTBits, MVT::i8));
4446 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
4447 AndNode, DAG.getConstant(0, MVT::i8));
4450 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4451 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4452 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4454 if (Op.getOpcode() == ISD::SHL_PARTS) {
4455 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4456 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4458 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4459 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4462 SDValue Ops[2] = { Lo, Hi };
4463 return DAG.getMergeValues(Ops, 2);
4466 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4467 MVT SrcVT = Op.getOperand(0).getValueType();
4468 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4469 "Unknown SINT_TO_FP to lower!");
4471 // These are really Legal; caller falls through into that case.
4472 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4474 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4475 Subtarget->is64Bit())
4478 unsigned Size = SrcVT.getSizeInBits()/8;
4479 MachineFunction &MF = DAG.getMachineFunction();
4480 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4481 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4482 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4484 PseudoSourceValue::getFixedStack(SSFI), 0);
4488 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4490 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4492 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4493 SmallVector<SDValue, 8> Ops;
4494 Ops.push_back(Chain);
4495 Ops.push_back(StackSlot);
4496 Ops.push_back(DAG.getValueType(SrcVT));
4497 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4498 Tys, &Ops[0], Ops.size());
4501 Chain = Result.getValue(1);
4502 SDValue InFlag = Result.getValue(2);
4504 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4505 // shouldn't be necessary except that RFP cannot be live across
4506 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4507 MachineFunction &MF = DAG.getMachineFunction();
4508 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4509 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4510 Tys = DAG.getVTList(MVT::Other);
4511 SmallVector<SDValue, 8> Ops;
4512 Ops.push_back(Chain);
4513 Ops.push_back(Result);
4514 Ops.push_back(StackSlot);
4515 Ops.push_back(DAG.getValueType(Op.getValueType()));
4516 Ops.push_back(InFlag);
4517 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4518 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4519 PseudoSourceValue::getFixedStack(SSFI), 0);
4525 std::pair<SDValue,SDValue> X86TargetLowering::
4526 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
4527 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4528 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4529 "Unknown FP_TO_SINT to lower!");
4531 // These are really Legal.
4532 if (Op.getValueType() == MVT::i32 &&
4533 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4534 return std::make_pair(SDValue(), SDValue());
4535 if (Subtarget->is64Bit() &&
4536 Op.getValueType() == MVT::i64 &&
4537 Op.getOperand(0).getValueType() != MVT::f80)
4538 return std::make_pair(SDValue(), SDValue());
4540 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4542 MachineFunction &MF = DAG.getMachineFunction();
4543 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4544 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4545 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4547 switch (Op.getValueType().getSimpleVT()) {
4548 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4549 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4550 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4551 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4554 SDValue Chain = DAG.getEntryNode();
4555 SDValue Value = Op.getOperand(0);
4556 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4557 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4558 Chain = DAG.getStore(Chain, Value, StackSlot,
4559 PseudoSourceValue::getFixedStack(SSFI), 0);
4560 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4562 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4564 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4565 Chain = Value.getValue(1);
4566 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4567 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4570 // Build the FP_TO_INT*_IN_MEM
4571 SDValue Ops[] = { Chain, Value, StackSlot };
4572 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4574 return std::make_pair(FIST, StackSlot);
4577 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4578 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4579 SDValue FIST = Vals.first, StackSlot = Vals.second;
4580 if (FIST.Val == 0) return SDValue();
4583 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4586 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4587 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
4588 SDValue FIST = Vals.first, StackSlot = Vals.second;
4589 if (FIST.Val == 0) return 0;
4591 MVT VT = N->getValueType(0);
4593 // Return a load from the stack slot.
4594 SDValue Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0);
4596 // Use MERGE_VALUES to drop the chain result value and get a node with one
4597 // result. This requires turning off getMergeValues simplification, since
4598 // otherwise it will give us Res back.
4599 return DAG.getMergeValues(&Res, 1, false).Val;
4602 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
4603 MVT VT = Op.getValueType();
4606 EltVT = VT.getVectorElementType();
4607 std::vector<Constant*> CV;
4608 if (EltVT == MVT::f64) {
4609 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4613 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4619 Constant *C = ConstantVector::get(CV);
4620 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4621 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4622 PseudoSourceValue::getConstantPool(), 0,
4624 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4627 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
4628 MVT VT = Op.getValueType();
4630 unsigned EltNum = 1;
4631 if (VT.isVector()) {
4632 EltVT = VT.getVectorElementType();
4633 EltNum = VT.getVectorNumElements();
4635 std::vector<Constant*> CV;
4636 if (EltVT == MVT::f64) {
4637 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4641 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4647 Constant *C = ConstantVector::get(CV);
4648 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4649 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4650 PseudoSourceValue::getConstantPool(), 0,
4652 if (VT.isVector()) {
4653 return DAG.getNode(ISD::BIT_CONVERT, VT,
4654 DAG.getNode(ISD::XOR, MVT::v2i64,
4655 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4656 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4658 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4662 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
4663 SDValue Op0 = Op.getOperand(0);
4664 SDValue Op1 = Op.getOperand(1);
4665 MVT VT = Op.getValueType();
4666 MVT SrcVT = Op1.getValueType();
4668 // If second operand is smaller, extend it first.
4669 if (SrcVT.bitsLT(VT)) {
4670 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4673 // And if it is bigger, shrink it first.
4674 if (SrcVT.bitsGT(VT)) {
4675 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4679 // At this point the operands and the result should have the same
4680 // type, and that won't be f80 since that is not custom lowered.
4682 // First get the sign bit of second operand.
4683 std::vector<Constant*> CV;
4684 if (SrcVT == MVT::f64) {
4685 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4686 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4688 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4689 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4690 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4691 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4693 Constant *C = ConstantVector::get(CV);
4694 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4695 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4696 PseudoSourceValue::getConstantPool(), 0,
4698 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4700 // Shift sign bit right or left if the two operands have different types.
4701 if (SrcVT.bitsGT(VT)) {
4702 // Op0 is MVT::f32, Op1 is MVT::f64.
4703 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4704 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4705 DAG.getConstant(32, MVT::i32));
4706 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4707 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4708 DAG.getIntPtrConstant(0));
4711 // Clear first operand sign bit.
4713 if (VT == MVT::f64) {
4714 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4715 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4717 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4718 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4719 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4720 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4722 C = ConstantVector::get(CV);
4723 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4724 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4725 PseudoSourceValue::getConstantPool(), 0,
4727 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4729 // Or the value with the sign bit.
4730 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4733 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
4734 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4736 SDValue Op0 = Op.getOperand(0);
4737 SDValue Op1 = Op.getOperand(1);
4738 SDValue CC = Op.getOperand(2);
4739 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4740 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4743 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4745 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4746 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4747 DAG.getConstant(X86CC, MVT::i8), Cond);
4750 assert(isFP && "Illegal integer SetCC!");
4752 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4753 switch (SetCCOpcode) {
4754 default: assert(false && "Illegal floating point SetCC!");
4755 case ISD::SETOEQ: { // !PF & ZF
4756 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4757 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4758 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4759 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4760 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4762 case ISD::SETUNE: { // PF | !ZF
4763 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4764 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4765 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4766 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4767 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4772 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4774 SDValue Op0 = Op.getOperand(0);
4775 SDValue Op1 = Op.getOperand(1);
4776 SDValue CC = Op.getOperand(2);
4777 MVT VT = Op.getValueType();
4778 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4779 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4783 MVT VT0 = Op0.getValueType();
4784 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
4785 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
4788 switch (SetCCOpcode) {
4791 case ISD::SETEQ: SSECC = 0; break;
4793 case ISD::SETGT: Swap = true; // Fallthrough
4795 case ISD::SETOLT: SSECC = 1; break;
4797 case ISD::SETGE: Swap = true; // Fallthrough
4799 case ISD::SETOLE: SSECC = 2; break;
4800 case ISD::SETUO: SSECC = 3; break;
4802 case ISD::SETNE: SSECC = 4; break;
4803 case ISD::SETULE: Swap = true;
4804 case ISD::SETUGE: SSECC = 5; break;
4805 case ISD::SETULT: Swap = true;
4806 case ISD::SETUGT: SSECC = 6; break;
4807 case ISD::SETO: SSECC = 7; break;
4810 std::swap(Op0, Op1);
4812 // In the two special cases we can't handle, emit two comparisons.
4814 if (SetCCOpcode == ISD::SETUEQ) {
4816 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
4817 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
4818 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
4820 else if (SetCCOpcode == ISD::SETONE) {
4822 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
4823 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
4824 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
4826 assert(0 && "Illegal FP comparison");
4828 // Handle all other FP comparisons here.
4829 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
4832 // We are handling one of the integer comparisons here. Since SSE only has
4833 // GT and EQ comparisons for integer, swapping operands and multiple
4834 // operations may be required for some comparisons.
4835 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
4836 bool Swap = false, Invert = false, FlipSigns = false;
4838 switch (VT.getSimpleVT()) {
4840 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
4841 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
4842 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
4843 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
4846 switch (SetCCOpcode) {
4848 case ISD::SETNE: Invert = true;
4849 case ISD::SETEQ: Opc = EQOpc; break;
4850 case ISD::SETLT: Swap = true;
4851 case ISD::SETGT: Opc = GTOpc; break;
4852 case ISD::SETGE: Swap = true;
4853 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
4854 case ISD::SETULT: Swap = true;
4855 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
4856 case ISD::SETUGE: Swap = true;
4857 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
4860 std::swap(Op0, Op1);
4862 // Since SSE has no unsigned integer comparisons, we need to flip the sign
4863 // bits of the inputs before performing those operations.
4865 MVT EltVT = VT.getVectorElementType();
4866 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
4867 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
4868 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
4870 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
4871 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
4874 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
4876 // If the logical-not of the result is required, perform that now.
4878 MVT EltVT = VT.getVectorElementType();
4879 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
4880 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
4881 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
4883 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
4888 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
4889 bool addTest = true;
4890 SDValue Cond = Op.getOperand(0);
4893 if (Cond.getOpcode() == ISD::SETCC)
4894 Cond = LowerSETCC(Cond, DAG);
4896 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4897 // setting operand in place of the X86ISD::SETCC.
4898 if (Cond.getOpcode() == X86ISD::SETCC) {
4899 CC = Cond.getOperand(0);
4901 SDValue Cmp = Cond.getOperand(1);
4902 unsigned Opc = Cmp.getOpcode();
4903 MVT VT = Op.getValueType();
4905 bool IllegalFPCMov = false;
4906 if (VT.isFloatingPoint() && !VT.isVector() &&
4907 !isScalarFPTypeInSSEReg(VT)) // FPStack?
4908 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4910 if ((Opc == X86ISD::CMP ||
4911 Opc == X86ISD::COMI ||
4912 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4919 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4920 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4923 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4925 SmallVector<SDValue, 4> Ops;
4926 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4927 // condition is true.
4928 Ops.push_back(Op.getOperand(2));
4929 Ops.push_back(Op.getOperand(1));
4931 Ops.push_back(Cond);
4932 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4935 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
4936 bool addTest = true;
4937 SDValue Chain = Op.getOperand(0);
4938 SDValue Cond = Op.getOperand(1);
4939 SDValue Dest = Op.getOperand(2);
4942 if (Cond.getOpcode() == ISD::SETCC)
4943 Cond = LowerSETCC(Cond, DAG);
4945 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4946 // setting operand in place of the X86ISD::SETCC.
4947 if (Cond.getOpcode() == X86ISD::SETCC) {
4948 CC = Cond.getOperand(0);
4950 SDValue Cmp = Cond.getOperand(1);
4951 unsigned Opc = Cmp.getOpcode();
4952 if (Opc == X86ISD::CMP ||
4953 Opc == X86ISD::COMI ||
4954 Opc == X86ISD::UCOMI) {
4961 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4962 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4964 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
4965 Chain, Op.getOperand(2), CC, Cond);
4969 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4970 // Calls to _alloca is needed to probe the stack when allocating more than 4k
4971 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
4972 // that the guard pages used by the OS virtual memory manager are allocated in
4973 // correct sequence.
4975 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4976 SelectionDAG &DAG) {
4977 assert(Subtarget->isTargetCygMing() &&
4978 "This should be used only on Cygwin/Mingw targets");
4981 SDValue Chain = Op.getOperand(0);
4982 SDValue Size = Op.getOperand(1);
4983 // FIXME: Ensure alignment here
4987 MVT IntPtr = getPointerTy();
4988 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
4990 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0));
4992 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4993 Flag = Chain.getValue(1);
4995 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4996 SDValue Ops[] = { Chain,
4997 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4998 DAG.getRegister(X86::EAX, IntPtr),
4999 DAG.getRegister(X86StackPtr, SPTy),
5001 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
5002 Flag = Chain.getValue(1);
5004 Chain = DAG.getCALLSEQ_END(Chain,
5005 DAG.getIntPtrConstant(0),
5006 DAG.getIntPtrConstant(0),
5009 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
5011 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5012 return DAG.getMergeValues(Ops1, 2);
5016 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
5018 SDValue Dst, SDValue Src,
5019 SDValue Size, unsigned Align,
5020 const Value *DstSV, uint64_t DstSVOff) {
5021 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5023 /// If not DWORD aligned or size is more than the threshold, call the library.
5024 /// The libc version is likely to be faster for these cases. It can use the
5025 /// address value and run time information about the CPU.
5026 if ((Align & 3) == 0 ||
5028 ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) {
5029 SDValue InFlag(0, 0);
5031 // Check to see if there is a specialized entry-point for memory zeroing.
5032 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5033 if (const char *bzeroEntry =
5034 V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5035 MVT IntPtr = getPointerTy();
5036 const Type *IntPtrTy = getTargetData()->getIntPtrType();
5037 TargetLowering::ArgListTy Args;
5038 TargetLowering::ArgListEntry Entry;
5040 Entry.Ty = IntPtrTy;
5041 Args.push_back(Entry);
5043 Args.push_back(Entry);
5044 std::pair<SDValue,SDValue> CallResult =
5045 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
5046 false, DAG.getExternalSymbol(bzeroEntry, IntPtr),
5048 return CallResult.second;
5051 // Otherwise have the target-independent code call memset.
5055 uint64_t SizeVal = ConstantSize->getValue();
5056 SDValue InFlag(0, 0);
5059 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5060 unsigned BytesLeft = 0;
5061 bool TwoRepStos = false;
5064 uint64_t Val = ValC->getValue() & 255;
5066 // If the value is a constant, then we can potentially use larger sets.
5067 switch (Align & 3) {
5068 case 2: // WORD aligned
5071 Val = (Val << 8) | Val;
5073 case 0: // DWORD aligned
5076 Val = (Val << 8) | Val;
5077 Val = (Val << 16) | Val;
5078 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5081 Val = (Val << 32) | Val;
5084 default: // Byte aligned
5087 Count = DAG.getIntPtrConstant(SizeVal);
5091 if (AVT.bitsGT(MVT::i8)) {
5092 unsigned UBytes = AVT.getSizeInBits() / 8;
5093 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5094 BytesLeft = SizeVal % UBytes;
5097 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5099 InFlag = Chain.getValue(1);
5102 Count = DAG.getIntPtrConstant(SizeVal);
5103 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
5104 InFlag = Chain.getValue(1);
5107 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5109 InFlag = Chain.getValue(1);
5110 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5112 InFlag = Chain.getValue(1);
5114 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5115 SmallVector<SDValue, 8> Ops;
5116 Ops.push_back(Chain);
5117 Ops.push_back(DAG.getValueType(AVT));
5118 Ops.push_back(InFlag);
5119 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5122 InFlag = Chain.getValue(1);
5124 MVT CVT = Count.getValueType();
5125 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
5126 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5127 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5129 InFlag = Chain.getValue(1);
5130 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5132 Ops.push_back(Chain);
5133 Ops.push_back(DAG.getValueType(MVT::i8));
5134 Ops.push_back(InFlag);
5135 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5136 } else if (BytesLeft) {
5137 // Handle the last 1 - 7 bytes.
5138 unsigned Offset = SizeVal - BytesLeft;
5139 MVT AddrVT = Dst.getValueType();
5140 MVT SizeVT = Size.getValueType();
5142 Chain = DAG.getMemset(Chain,
5143 DAG.getNode(ISD::ADD, AddrVT, Dst,
5144 DAG.getConstant(Offset, AddrVT)),
5146 DAG.getConstant(BytesLeft, SizeVT),
5147 Align, DstSV, DstSVOff + Offset);
5150 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5155 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
5157 SDValue Dst, SDValue Src,
5158 SDValue Size, unsigned Align,
5160 const Value *DstSV, uint64_t DstSVOff,
5161 const Value *SrcSV, uint64_t SrcSVOff){
5163 // This requires the copy size to be a constant, preferrably
5164 // within a subtarget-specific limit.
5165 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5168 uint64_t SizeVal = ConstantSize->getValue();
5169 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5173 unsigned BytesLeft = 0;
5174 if (Align >= 8 && Subtarget->is64Bit())
5176 else if (Align >= 4)
5178 else if (Align >= 2)
5183 unsigned UBytes = AVT.getSizeInBits() / 8;
5184 unsigned CountVal = SizeVal / UBytes;
5185 SDValue Count = DAG.getIntPtrConstant(CountVal);
5186 BytesLeft = SizeVal % UBytes;
5188 SDValue InFlag(0, 0);
5189 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5191 InFlag = Chain.getValue(1);
5192 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5194 InFlag = Chain.getValue(1);
5195 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5197 InFlag = Chain.getValue(1);
5199 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5200 SmallVector<SDValue, 8> Ops;
5201 Ops.push_back(Chain);
5202 Ops.push_back(DAG.getValueType(AVT));
5203 Ops.push_back(InFlag);
5204 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5206 SmallVector<SDValue, 4> Results;
5207 Results.push_back(RepMovs);
5209 // Handle the last 1 - 7 bytes.
5210 unsigned Offset = SizeVal - BytesLeft;
5211 MVT DstVT = Dst.getValueType();
5212 MVT SrcVT = Src.getValueType();
5213 MVT SizeVT = Size.getValueType();
5214 Results.push_back(DAG.getMemcpy(Chain,
5215 DAG.getNode(ISD::ADD, DstVT, Dst,
5216 DAG.getConstant(Offset, DstVT)),
5217 DAG.getNode(ISD::ADD, SrcVT, Src,
5218 DAG.getConstant(Offset, SrcVT)),
5219 DAG.getConstant(BytesLeft, SizeVT),
5220 Align, AlwaysInline,
5221 DstSV, DstSVOff + Offset,
5222 SrcSV, SrcSVOff + Offset));
5225 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5228 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
5229 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
5230 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5231 SDValue TheChain = N->getOperand(0);
5232 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
5233 if (Subtarget->is64Bit()) {
5234 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
5235 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
5236 MVT::i64, rax.getValue(2));
5237 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
5238 DAG.getConstant(32, MVT::i8));
5240 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
5243 return DAG.getMergeValues(Ops, 2).Val;
5246 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
5247 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
5248 MVT::i32, eax.getValue(2));
5249 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
5250 SDValue Ops[] = { eax, edx };
5251 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
5253 // Use a MERGE_VALUES to return the value and chain.
5254 Ops[1] = edx.getValue(1);
5255 return DAG.getMergeValues(Ops, 2).Val;
5258 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5259 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5261 if (!Subtarget->is64Bit()) {
5262 // vastart just stores the address of the VarArgsFrameIndex slot into the
5263 // memory location argument.
5264 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5265 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5269 // gp_offset (0 - 6 * 8)
5270 // fp_offset (48 - 48 + 8 * 16)
5271 // overflow_arg_area (point to parameters coming in memory).
5273 SmallVector<SDValue, 8> MemOps;
5274 SDValue FIN = Op.getOperand(1);
5276 SDValue Store = DAG.getStore(Op.getOperand(0),
5277 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5279 MemOps.push_back(Store);
5282 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5283 Store = DAG.getStore(Op.getOperand(0),
5284 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5286 MemOps.push_back(Store);
5288 // Store ptr to overflow_arg_area
5289 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5290 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5291 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5292 MemOps.push_back(Store);
5294 // Store ptr to reg_save_area.
5295 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5296 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5297 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5298 MemOps.push_back(Store);
5299 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5302 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5303 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5304 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5305 SDValue Chain = Op.getOperand(0);
5306 SDValue SrcPtr = Op.getOperand(1);
5307 SDValue SrcSV = Op.getOperand(2);
5309 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5314 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5315 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5316 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5317 SDValue Chain = Op.getOperand(0);
5318 SDValue DstPtr = Op.getOperand(1);
5319 SDValue SrcPtr = Op.getOperand(2);
5320 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5321 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5323 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5324 DAG.getIntPtrConstant(24), 8, false,
5325 DstSV, 0, SrcSV, 0);
5329 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5330 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
5332 default: return SDValue(); // Don't custom lower most intrinsics.
5333 // Comparison intrinsics.
5334 case Intrinsic::x86_sse_comieq_ss:
5335 case Intrinsic::x86_sse_comilt_ss:
5336 case Intrinsic::x86_sse_comile_ss:
5337 case Intrinsic::x86_sse_comigt_ss:
5338 case Intrinsic::x86_sse_comige_ss:
5339 case Intrinsic::x86_sse_comineq_ss:
5340 case Intrinsic::x86_sse_ucomieq_ss:
5341 case Intrinsic::x86_sse_ucomilt_ss:
5342 case Intrinsic::x86_sse_ucomile_ss:
5343 case Intrinsic::x86_sse_ucomigt_ss:
5344 case Intrinsic::x86_sse_ucomige_ss:
5345 case Intrinsic::x86_sse_ucomineq_ss:
5346 case Intrinsic::x86_sse2_comieq_sd:
5347 case Intrinsic::x86_sse2_comilt_sd:
5348 case Intrinsic::x86_sse2_comile_sd:
5349 case Intrinsic::x86_sse2_comigt_sd:
5350 case Intrinsic::x86_sse2_comige_sd:
5351 case Intrinsic::x86_sse2_comineq_sd:
5352 case Intrinsic::x86_sse2_ucomieq_sd:
5353 case Intrinsic::x86_sse2_ucomilt_sd:
5354 case Intrinsic::x86_sse2_ucomile_sd:
5355 case Intrinsic::x86_sse2_ucomigt_sd:
5356 case Intrinsic::x86_sse2_ucomige_sd:
5357 case Intrinsic::x86_sse2_ucomineq_sd: {
5359 ISD::CondCode CC = ISD::SETCC_INVALID;
5362 case Intrinsic::x86_sse_comieq_ss:
5363 case Intrinsic::x86_sse2_comieq_sd:
5367 case Intrinsic::x86_sse_comilt_ss:
5368 case Intrinsic::x86_sse2_comilt_sd:
5372 case Intrinsic::x86_sse_comile_ss:
5373 case Intrinsic::x86_sse2_comile_sd:
5377 case Intrinsic::x86_sse_comigt_ss:
5378 case Intrinsic::x86_sse2_comigt_sd:
5382 case Intrinsic::x86_sse_comige_ss:
5383 case Intrinsic::x86_sse2_comige_sd:
5387 case Intrinsic::x86_sse_comineq_ss:
5388 case Intrinsic::x86_sse2_comineq_sd:
5392 case Intrinsic::x86_sse_ucomieq_ss:
5393 case Intrinsic::x86_sse2_ucomieq_sd:
5394 Opc = X86ISD::UCOMI;
5397 case Intrinsic::x86_sse_ucomilt_ss:
5398 case Intrinsic::x86_sse2_ucomilt_sd:
5399 Opc = X86ISD::UCOMI;
5402 case Intrinsic::x86_sse_ucomile_ss:
5403 case Intrinsic::x86_sse2_ucomile_sd:
5404 Opc = X86ISD::UCOMI;
5407 case Intrinsic::x86_sse_ucomigt_ss:
5408 case Intrinsic::x86_sse2_ucomigt_sd:
5409 Opc = X86ISD::UCOMI;
5412 case Intrinsic::x86_sse_ucomige_ss:
5413 case Intrinsic::x86_sse2_ucomige_sd:
5414 Opc = X86ISD::UCOMI;
5417 case Intrinsic::x86_sse_ucomineq_ss:
5418 case Intrinsic::x86_sse2_ucomineq_sd:
5419 Opc = X86ISD::UCOMI;
5425 SDValue LHS = Op.getOperand(1);
5426 SDValue RHS = Op.getOperand(2);
5427 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5429 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5430 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5431 DAG.getConstant(X86CC, MVT::i8), Cond);
5432 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
5435 // Fix vector shift instructions where the last operand is a non-immediate
5437 case Intrinsic::x86_sse2_pslli_w:
5438 case Intrinsic::x86_sse2_pslli_d:
5439 case Intrinsic::x86_sse2_pslli_q:
5440 case Intrinsic::x86_sse2_psrli_w:
5441 case Intrinsic::x86_sse2_psrli_d:
5442 case Intrinsic::x86_sse2_psrli_q:
5443 case Intrinsic::x86_sse2_psrai_w:
5444 case Intrinsic::x86_sse2_psrai_d:
5445 case Intrinsic::x86_mmx_pslli_w:
5446 case Intrinsic::x86_mmx_pslli_d:
5447 case Intrinsic::x86_mmx_pslli_q:
5448 case Intrinsic::x86_mmx_psrli_w:
5449 case Intrinsic::x86_mmx_psrli_d:
5450 case Intrinsic::x86_mmx_psrli_q:
5451 case Intrinsic::x86_mmx_psrai_w:
5452 case Intrinsic::x86_mmx_psrai_d: {
5453 SDValue ShAmt = Op.getOperand(2);
5454 if (isa<ConstantSDNode>(ShAmt))
5457 unsigned NewIntNo = 0;
5458 MVT ShAmtVT = MVT::v4i32;
5460 case Intrinsic::x86_sse2_pslli_w:
5461 NewIntNo = Intrinsic::x86_sse2_psll_w;
5463 case Intrinsic::x86_sse2_pslli_d:
5464 NewIntNo = Intrinsic::x86_sse2_psll_d;
5466 case Intrinsic::x86_sse2_pslli_q:
5467 NewIntNo = Intrinsic::x86_sse2_psll_q;
5469 case Intrinsic::x86_sse2_psrli_w:
5470 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5472 case Intrinsic::x86_sse2_psrli_d:
5473 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5475 case Intrinsic::x86_sse2_psrli_q:
5476 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5478 case Intrinsic::x86_sse2_psrai_w:
5479 NewIntNo = Intrinsic::x86_sse2_psra_w;
5481 case Intrinsic::x86_sse2_psrai_d:
5482 NewIntNo = Intrinsic::x86_sse2_psra_d;
5485 ShAmtVT = MVT::v2i32;
5487 case Intrinsic::x86_mmx_pslli_w:
5488 NewIntNo = Intrinsic::x86_mmx_psll_w;
5490 case Intrinsic::x86_mmx_pslli_d:
5491 NewIntNo = Intrinsic::x86_mmx_psll_d;
5493 case Intrinsic::x86_mmx_pslli_q:
5494 NewIntNo = Intrinsic::x86_mmx_psll_q;
5496 case Intrinsic::x86_mmx_psrli_w:
5497 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5499 case Intrinsic::x86_mmx_psrli_d:
5500 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5502 case Intrinsic::x86_mmx_psrli_q:
5503 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5505 case Intrinsic::x86_mmx_psrai_w:
5506 NewIntNo = Intrinsic::x86_mmx_psra_w;
5508 case Intrinsic::x86_mmx_psrai_d:
5509 NewIntNo = Intrinsic::x86_mmx_psra_d;
5511 default: abort(); // Can't reach here.
5516 MVT VT = Op.getValueType();
5517 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5518 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5519 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5520 DAG.getConstant(NewIntNo, MVT::i32),
5521 Op.getOperand(1), ShAmt);
5526 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5527 // Depths > 0 not supported yet!
5528 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5531 // Just load the return address
5532 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5533 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5536 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5537 // Depths > 0 not supported yet!
5538 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5541 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5542 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
5543 DAG.getIntPtrConstant(!Subtarget->is64Bit() ? 4 : 8));
5546 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
5547 SelectionDAG &DAG) {
5548 // Is not yet supported on x86-64
5549 if (Subtarget->is64Bit())
5552 return DAG.getIntPtrConstant(8);
5555 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
5557 assert(!Subtarget->is64Bit() &&
5558 "Lowering of eh_return builtin is not supported yet on x86-64");
5560 MachineFunction &MF = DAG.getMachineFunction();
5561 SDValue Chain = Op.getOperand(0);
5562 SDValue Offset = Op.getOperand(1);
5563 SDValue Handler = Op.getOperand(2);
5565 SDValue Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
5568 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5569 DAG.getIntPtrConstant(-4UL));
5570 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5571 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5572 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
5573 MF.getRegInfo().addLiveOut(X86::ECX);
5575 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
5576 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
5579 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
5580 SelectionDAG &DAG) {
5581 SDValue Root = Op.getOperand(0);
5582 SDValue Trmp = Op.getOperand(1); // trampoline
5583 SDValue FPtr = Op.getOperand(2); // nested function
5584 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
5586 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5588 const X86InstrInfo *TII =
5589 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5591 if (Subtarget->is64Bit()) {
5592 SDValue OutChains[6];
5594 // Large code-model.
5596 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5597 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5599 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5600 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5602 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5604 // Load the pointer to the nested function into R11.
5605 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5606 SDValue Addr = Trmp;
5607 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5610 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5611 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5613 // Load the 'nest' parameter value into R10.
5614 // R10 is specified in X86CallingConv.td
5615 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5616 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5617 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5620 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5621 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5623 // Jump to the nested function.
5624 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5625 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5626 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5629 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5630 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5631 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5635 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5636 return DAG.getMergeValues(Ops, 2);
5638 const Function *Func =
5639 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5640 unsigned CC = Func->getCallingConv();
5645 assert(0 && "Unsupported calling convention");
5646 case CallingConv::C:
5647 case CallingConv::X86_StdCall: {
5648 // Pass 'nest' parameter in ECX.
5649 // Must be kept in sync with X86CallingConv.td
5652 // Check that ECX wasn't needed by an 'inreg' parameter.
5653 const FunctionType *FTy = Func->getFunctionType();
5654 const PAListPtr &Attrs = Func->getParamAttrs();
5656 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5657 unsigned InRegCount = 0;
5660 for (FunctionType::param_iterator I = FTy->param_begin(),
5661 E = FTy->param_end(); I != E; ++I, ++Idx)
5662 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg))
5663 // FIXME: should only count parameters that are lowered to integers.
5664 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
5666 if (InRegCount > 2) {
5667 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5673 case CallingConv::X86_FastCall:
5674 // Pass 'nest' parameter in EAX.
5675 // Must be kept in sync with X86CallingConv.td
5680 SDValue OutChains[4];
5683 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5684 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5686 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5687 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
5688 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
5691 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
5692 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
5694 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
5695 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5696 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
5697 TrmpAddr, 5, false, 1);
5699 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
5700 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
5703 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
5704 return DAG.getMergeValues(Ops, 2);
5708 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
5710 The rounding mode is in bits 11:10 of FPSR, and has the following
5717 FLT_ROUNDS, on the other hand, expects the following:
5724 To perform the conversion, we do:
5725 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5728 MachineFunction &MF = DAG.getMachineFunction();
5729 const TargetMachine &TM = MF.getTarget();
5730 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5731 unsigned StackAlignment = TFI.getStackAlignment();
5732 MVT VT = Op.getValueType();
5734 // Save FP Control Word to stack slot
5735 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
5736 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5738 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
5739 DAG.getEntryNode(), StackSlot);
5741 // Load FP Control Word from stack slot
5742 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
5744 // Transform as necessary
5746 DAG.getNode(ISD::SRL, MVT::i16,
5747 DAG.getNode(ISD::AND, MVT::i16,
5748 CWD, DAG.getConstant(0x800, MVT::i16)),
5749 DAG.getConstant(11, MVT::i8));
5751 DAG.getNode(ISD::SRL, MVT::i16,
5752 DAG.getNode(ISD::AND, MVT::i16,
5753 CWD, DAG.getConstant(0x400, MVT::i16)),
5754 DAG.getConstant(9, MVT::i8));
5757 DAG.getNode(ISD::AND, MVT::i16,
5758 DAG.getNode(ISD::ADD, MVT::i16,
5759 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5760 DAG.getConstant(1, MVT::i16)),
5761 DAG.getConstant(3, MVT::i16));
5764 return DAG.getNode((VT.getSizeInBits() < 16 ?
5765 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5768 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
5769 MVT VT = Op.getValueType();
5771 unsigned NumBits = VT.getSizeInBits();
5773 Op = Op.getOperand(0);
5774 if (VT == MVT::i8) {
5775 // Zero extend to i32 since there is not an i8 bsr.
5777 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5780 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5781 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5782 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5784 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5785 SmallVector<SDValue, 4> Ops;
5787 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5788 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5789 Ops.push_back(Op.getValue(1));
5790 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5792 // Finally xor with NumBits-1.
5793 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5796 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5800 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
5801 MVT VT = Op.getValueType();
5803 unsigned NumBits = VT.getSizeInBits();
5805 Op = Op.getOperand(0);
5806 if (VT == MVT::i8) {
5808 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5811 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5812 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5813 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5815 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5816 SmallVector<SDValue, 4> Ops;
5818 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5819 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5820 Ops.push_back(Op.getValue(1));
5821 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5824 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5828 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
5829 MVT T = Op.getValueType();
5832 switch(T.getSimpleVT()) {
5834 assert(false && "Invalid value type!");
5835 case MVT::i8: Reg = X86::AL; size = 1; break;
5836 case MVT::i16: Reg = X86::AX; size = 2; break;
5837 case MVT::i32: Reg = X86::EAX; size = 4; break;
5839 if (Subtarget->is64Bit()) {
5840 Reg = X86::RAX; size = 8;
5841 } else //Should go away when LowerType stuff lands
5842 return SDValue(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0);
5845 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
5846 Op.getOperand(3), SDValue());
5847 SDValue Ops[] = { cpIn.getValue(0),
5850 DAG.getTargetConstant(size, MVT::i8),
5852 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5853 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5855 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
5859 SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op, SelectionDAG &DAG) {
5860 MVT T = Op->getValueType(0);
5861 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
5862 SDValue cpInL, cpInH;
5863 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5864 DAG.getConstant(0, MVT::i32));
5865 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5866 DAG.getConstant(1, MVT::i32));
5867 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
5869 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
5870 cpInH, cpInL.getValue(1));
5871 SDValue swapInL, swapInH;
5872 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5873 DAG.getConstant(0, MVT::i32));
5874 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5875 DAG.getConstant(1, MVT::i32));
5876 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
5877 swapInL, cpInH.getValue(1));
5878 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
5879 swapInH, swapInL.getValue(1));
5880 SDValue Ops[] = { swapInH.getValue(0),
5882 swapInH.getValue(1)};
5883 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5884 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
5885 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
5886 Result.getValue(1));
5887 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
5888 cpOutL.getValue(2));
5889 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
5890 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
5891 SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
5892 return DAG.getMergeValues(Vals, 2).Val;
5895 SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) {
5896 MVT T = Op->getValueType(0);
5897 SDValue negOp = DAG.getNode(ISD::SUB, T,
5898 DAG.getConstant(0, T), Op->getOperand(2));
5899 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, Op->getOperand(0),
5900 Op->getOperand(1), negOp,
5901 cast<AtomicSDNode>(Op)->getSrcValue(),
5902 cast<AtomicSDNode>(Op)->getAlignment()).Val;
5905 /// LowerOperation - Provide custom lowering hooks for some operations.
5907 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5908 switch (Op.getOpcode()) {
5909 default: assert(0 && "Should not custom lower this!");
5910 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
5911 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5912 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5913 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5914 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5915 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5916 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5917 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5918 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5919 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5920 case ISD::SHL_PARTS:
5921 case ISD::SRA_PARTS:
5922 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5923 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5924 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5925 case ISD::FABS: return LowerFABS(Op, DAG);
5926 case ISD::FNEG: return LowerFNEG(Op, DAG);
5927 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5928 case ISD::SETCC: return LowerSETCC(Op, DAG);
5929 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
5930 case ISD::SELECT: return LowerSELECT(Op, DAG);
5931 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5932 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5933 case ISD::CALL: return LowerCALL(Op, DAG);
5934 case ISD::RET: return LowerRET(Op, DAG);
5935 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5936 case ISD::VASTART: return LowerVASTART(Op, DAG);
5937 case ISD::VAARG: return LowerVAARG(Op, DAG);
5938 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
5939 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5940 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5941 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5942 case ISD::FRAME_TO_ARGS_OFFSET:
5943 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
5944 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
5945 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
5946 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
5947 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5948 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5949 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
5951 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5952 case ISD::READCYCLECOUNTER:
5953 return SDValue(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
5957 /// ReplaceNodeResults - Replace a node with an illegal result type
5958 /// with a new node built out of custom code.
5959 SDNode *X86TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
5960 switch (N->getOpcode()) {
5961 default: assert(0 && "Should not custom lower this!");
5962 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5963 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
5964 case ISD::ATOMIC_CMP_SWAP: return ExpandATOMIC_CMP_SWAP(N, DAG);
5965 case ISD::ATOMIC_LOAD_SUB: return ExpandATOMIC_LOAD_SUB(N,DAG);
5969 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5971 default: return NULL;
5972 case X86ISD::BSF: return "X86ISD::BSF";
5973 case X86ISD::BSR: return "X86ISD::BSR";
5974 case X86ISD::SHLD: return "X86ISD::SHLD";
5975 case X86ISD::SHRD: return "X86ISD::SHRD";
5976 case X86ISD::FAND: return "X86ISD::FAND";
5977 case X86ISD::FOR: return "X86ISD::FOR";
5978 case X86ISD::FXOR: return "X86ISD::FXOR";
5979 case X86ISD::FSRL: return "X86ISD::FSRL";
5980 case X86ISD::FILD: return "X86ISD::FILD";
5981 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
5982 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5983 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5984 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
5985 case X86ISD::FLD: return "X86ISD::FLD";
5986 case X86ISD::FST: return "X86ISD::FST";
5987 case X86ISD::CALL: return "X86ISD::CALL";
5988 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5989 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5990 case X86ISD::CMP: return "X86ISD::CMP";
5991 case X86ISD::COMI: return "X86ISD::COMI";
5992 case X86ISD::UCOMI: return "X86ISD::UCOMI";
5993 case X86ISD::SETCC: return "X86ISD::SETCC";
5994 case X86ISD::CMOV: return "X86ISD::CMOV";
5995 case X86ISD::BRCOND: return "X86ISD::BRCOND";
5996 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
5997 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5998 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
5999 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6000 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6001 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6002 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6003 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6004 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6005 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6006 case X86ISD::FMAX: return "X86ISD::FMAX";
6007 case X86ISD::FMIN: return "X86ISD::FMIN";
6008 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6009 case X86ISD::FRCP: return "X86ISD::FRCP";
6010 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6011 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6012 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6013 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6014 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6015 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6016 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6017 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6018 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6019 case X86ISD::VSHL: return "X86ISD::VSHL";
6020 case X86ISD::VSRL: return "X86ISD::VSRL";
6021 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6022 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6023 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6024 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6025 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6026 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6027 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6028 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6029 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6030 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6034 // isLegalAddressingMode - Return true if the addressing mode represented
6035 // by AM is legal for this target, for a load/store of the specified type.
6036 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6037 const Type *Ty) const {
6038 // X86 supports extremely general addressing modes.
6040 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6041 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6045 // We can only fold this if we don't need an extra load.
6046 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6049 // X86-64 only supports addr of globals in small code model.
6050 if (Subtarget->is64Bit()) {
6051 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6053 // If lower 4G is not available, then we must use rip-relative addressing.
6054 if (AM.BaseOffs || AM.Scale > 1)
6065 // These scales always work.
6070 // These scales are formed with basereg+scalereg. Only accept if there is
6075 default: // Other stuff never works.
6083 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6084 if (!Ty1->isInteger() || !Ty2->isInteger())
6086 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6087 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6088 if (NumBits1 <= NumBits2)
6090 return Subtarget->is64Bit() || NumBits1 < 64;
6093 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6094 if (!VT1.isInteger() || !VT2.isInteger())
6096 unsigned NumBits1 = VT1.getSizeInBits();
6097 unsigned NumBits2 = VT2.getSizeInBits();
6098 if (NumBits1 <= NumBits2)
6100 return Subtarget->is64Bit() || NumBits1 < 64;
6103 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6104 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6105 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6106 /// are assumed to be legal.
6108 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6109 // Only do shuffles on 128-bit vector types for now.
6110 if (VT.getSizeInBits() == 64) return false;
6111 return (Mask.Val->getNumOperands() <= 4 ||
6112 isIdentityMask(Mask.Val) ||
6113 isIdentityMask(Mask.Val, true) ||
6114 isSplatMask(Mask.Val) ||
6115 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
6116 X86::isUNPCKLMask(Mask.Val) ||
6117 X86::isUNPCKHMask(Mask.Val) ||
6118 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
6119 X86::isUNPCKH_v_undef_Mask(Mask.Val));
6123 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6124 MVT EVT, SelectionDAG &DAG) const {
6125 unsigned NumElts = BVOps.size();
6126 // Only do shuffles on 128-bit vector types for now.
6127 if (EVT.getSizeInBits() * NumElts == 64) return false;
6128 if (NumElts == 2) return true;
6130 return (isMOVLMask(&BVOps[0], 4) ||
6131 isCommutedMOVL(&BVOps[0], 4, true) ||
6132 isSHUFPMask(&BVOps[0], 4) ||
6133 isCommutedSHUFP(&BVOps[0], 4));
6138 //===----------------------------------------------------------------------===//
6139 // X86 Scheduler Hooks
6140 //===----------------------------------------------------------------------===//
6142 // private utility function
6144 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6145 MachineBasicBlock *MBB,
6153 TargetRegisterClass *RC,
6155 // For the atomic bitwise operator, we generate
6158 // ld t1 = [bitinstr.addr]
6159 // op t2 = t1, [bitinstr.val]
6161 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6163 // fallthrough -->nextMBB
6164 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6165 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6166 MachineFunction::iterator MBBIter = MBB;
6169 /// First build the CFG
6170 MachineFunction *F = MBB->getParent();
6171 MachineBasicBlock *thisMBB = MBB;
6172 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6173 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6174 F->insert(MBBIter, newMBB);
6175 F->insert(MBBIter, nextMBB);
6177 // Move all successors to thisMBB to nextMBB
6178 nextMBB->transferSuccessors(thisMBB);
6180 // Update thisMBB to fall through to newMBB
6181 thisMBB->addSuccessor(newMBB);
6183 // newMBB jumps to itself and fall through to nextMBB
6184 newMBB->addSuccessor(nextMBB);
6185 newMBB->addSuccessor(newMBB);
6187 // Insert instructions into newMBB based on incoming instruction
6188 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6189 MachineOperand& destOper = bInstr->getOperand(0);
6190 MachineOperand* argOpers[6];
6191 int numArgs = bInstr->getNumOperands() - 1;
6192 for (int i=0; i < numArgs; ++i)
6193 argOpers[i] = &bInstr->getOperand(i+1);
6195 // x86 address has 4 operands: base, index, scale, and displacement
6196 int lastAddrIndx = 3; // [0,3]
6199 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6200 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
6201 for (int i=0; i <= lastAddrIndx; ++i)
6202 (*MIB).addOperand(*argOpers[i]);
6204 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
6206 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
6211 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6212 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6213 && "invalid operand");
6214 if (argOpers[valArgIndx]->isReg())
6215 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6217 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6219 (*MIB).addOperand(*argOpers[valArgIndx]);
6221 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
6224 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
6225 for (int i=0; i <= lastAddrIndx; ++i)
6226 (*MIB).addOperand(*argOpers[i]);
6228 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6229 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6231 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6235 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6237 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6241 // private utility function
6243 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6244 MachineBasicBlock *MBB,
6246 // For the atomic min/max operator, we generate
6249 // ld t1 = [min/max.addr]
6250 // mov t2 = [min/max.val]
6252 // cmov[cond] t2 = t1
6254 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6256 // fallthrough -->nextMBB
6258 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6259 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6260 MachineFunction::iterator MBBIter = MBB;
6263 /// First build the CFG
6264 MachineFunction *F = MBB->getParent();
6265 MachineBasicBlock *thisMBB = MBB;
6266 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6267 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6268 F->insert(MBBIter, newMBB);
6269 F->insert(MBBIter, nextMBB);
6271 // Move all successors to thisMBB to nextMBB
6272 nextMBB->transferSuccessors(thisMBB);
6274 // Update thisMBB to fall through to newMBB
6275 thisMBB->addSuccessor(newMBB);
6277 // newMBB jumps to newMBB and fall through to nextMBB
6278 newMBB->addSuccessor(nextMBB);
6279 newMBB->addSuccessor(newMBB);
6281 // Insert instructions into newMBB based on incoming instruction
6282 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6283 MachineOperand& destOper = mInstr->getOperand(0);
6284 MachineOperand* argOpers[6];
6285 int numArgs = mInstr->getNumOperands() - 1;
6286 for (int i=0; i < numArgs; ++i)
6287 argOpers[i] = &mInstr->getOperand(i+1);
6289 // x86 address has 4 operands: base, index, scale, and displacement
6290 int lastAddrIndx = 3; // [0,3]
6293 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6294 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6295 for (int i=0; i <= lastAddrIndx; ++i)
6296 (*MIB).addOperand(*argOpers[i]);
6298 // We only support register and immediate values
6299 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6300 && "invalid operand");
6302 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6303 if (argOpers[valArgIndx]->isReg())
6304 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6306 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6307 (*MIB).addOperand(*argOpers[valArgIndx]);
6309 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6312 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6317 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6318 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6322 // Cmp and exchange if none has modified the memory location
6323 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6324 for (int i=0; i <= lastAddrIndx; ++i)
6325 (*MIB).addOperand(*argOpers[i]);
6327 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6328 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
6330 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6331 MIB.addReg(X86::EAX);
6334 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6336 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
6342 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6343 MachineBasicBlock *BB) {
6344 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6345 switch (MI->getOpcode()) {
6346 default: assert(false && "Unexpected instr type to insert");
6347 case X86::CMOV_FR32:
6348 case X86::CMOV_FR64:
6349 case X86::CMOV_V4F32:
6350 case X86::CMOV_V2F64:
6351 case X86::CMOV_V2I64: {
6352 // To "insert" a SELECT_CC instruction, we actually have to insert the
6353 // diamond control-flow pattern. The incoming instruction knows the
6354 // destination vreg to set, the condition code register to branch on, the
6355 // true/false values to select between, and a branch opcode to use.
6356 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6357 MachineFunction::iterator It = BB;
6363 // cmpTY ccX, r1, r2
6365 // fallthrough --> copy0MBB
6366 MachineBasicBlock *thisMBB = BB;
6367 MachineFunction *F = BB->getParent();
6368 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6369 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6371 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
6372 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6373 F->insert(It, copy0MBB);
6374 F->insert(It, sinkMBB);
6375 // Update machine-CFG edges by transferring all successors of the current
6376 // block to the new block which will contain the Phi node for the select.
6377 sinkMBB->transferSuccessors(BB);
6379 // Add the true and fallthrough blocks as its successors.
6380 BB->addSuccessor(copy0MBB);
6381 BB->addSuccessor(sinkMBB);
6384 // %FalseValue = ...
6385 // # fallthrough to sinkMBB
6388 // Update machine-CFG edges
6389 BB->addSuccessor(sinkMBB);
6392 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6395 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
6396 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6397 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6399 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6403 case X86::FP32_TO_INT16_IN_MEM:
6404 case X86::FP32_TO_INT32_IN_MEM:
6405 case X86::FP32_TO_INT64_IN_MEM:
6406 case X86::FP64_TO_INT16_IN_MEM:
6407 case X86::FP64_TO_INT32_IN_MEM:
6408 case X86::FP64_TO_INT64_IN_MEM:
6409 case X86::FP80_TO_INT16_IN_MEM:
6410 case X86::FP80_TO_INT32_IN_MEM:
6411 case X86::FP80_TO_INT64_IN_MEM: {
6412 // Change the floating point control register to use "round towards zero"
6413 // mode when truncating to an integer value.
6414 MachineFunction *F = BB->getParent();
6415 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
6416 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
6418 // Load the old value of the high byte of the control word...
6420 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
6421 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
6423 // Set the high part to be round to zero...
6424 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
6427 // Reload the modified control word now...
6428 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6430 // Restore the memory image of control word to original value
6431 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
6434 // Get the X86 opcode to use.
6436 switch (MI->getOpcode()) {
6437 default: assert(0 && "illegal opcode!");
6438 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
6439 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
6440 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
6441 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
6442 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
6443 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
6444 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
6445 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
6446 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
6450 MachineOperand &Op = MI->getOperand(0);
6451 if (Op.isRegister()) {
6452 AM.BaseType = X86AddressMode::RegBase;
6453 AM.Base.Reg = Op.getReg();
6455 AM.BaseType = X86AddressMode::FrameIndexBase;
6456 AM.Base.FrameIndex = Op.getIndex();
6458 Op = MI->getOperand(1);
6459 if (Op.isImmediate())
6460 AM.Scale = Op.getImm();
6461 Op = MI->getOperand(2);
6462 if (Op.isImmediate())
6463 AM.IndexReg = Op.getImm();
6464 Op = MI->getOperand(3);
6465 if (Op.isGlobalAddress()) {
6466 AM.GV = Op.getGlobal();
6468 AM.Disp = Op.getImm();
6470 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
6471 .addReg(MI->getOperand(4).getReg());
6473 // Reload the original control word now.
6474 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6476 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6479 case X86::ATOMAND32:
6480 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6481 X86::AND32ri, X86::MOV32rm,
6482 X86::LCMPXCHG32, X86::MOV32rr,
6483 X86::NOT32r, X86::EAX,
6484 X86::GR32RegisterClass);
6486 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
6487 X86::OR32ri, X86::MOV32rm,
6488 X86::LCMPXCHG32, X86::MOV32rr,
6489 X86::NOT32r, X86::EAX,
6490 X86::GR32RegisterClass);
6491 case X86::ATOMXOR32:
6492 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
6493 X86::XOR32ri, X86::MOV32rm,
6494 X86::LCMPXCHG32, X86::MOV32rr,
6495 X86::NOT32r, X86::EAX,
6496 X86::GR32RegisterClass);
6497 case X86::ATOMNAND32:
6498 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6499 X86::AND32ri, X86::MOV32rm,
6500 X86::LCMPXCHG32, X86::MOV32rr,
6501 X86::NOT32r, X86::EAX,
6502 X86::GR32RegisterClass, true);
6503 case X86::ATOMMIN32:
6504 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
6505 case X86::ATOMMAX32:
6506 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
6507 case X86::ATOMUMIN32:
6508 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
6509 case X86::ATOMUMAX32:
6510 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
6512 case X86::ATOMAND16:
6513 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6514 X86::AND16ri, X86::MOV16rm,
6515 X86::LCMPXCHG16, X86::MOV16rr,
6516 X86::NOT16r, X86::AX,
6517 X86::GR16RegisterClass);
6519 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
6520 X86::OR16ri, X86::MOV16rm,
6521 X86::LCMPXCHG16, X86::MOV16rr,
6522 X86::NOT16r, X86::AX,
6523 X86::GR16RegisterClass);
6524 case X86::ATOMXOR16:
6525 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
6526 X86::XOR16ri, X86::MOV16rm,
6527 X86::LCMPXCHG16, X86::MOV16rr,
6528 X86::NOT16r, X86::AX,
6529 X86::GR16RegisterClass);
6530 case X86::ATOMNAND16:
6531 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6532 X86::AND16ri, X86::MOV16rm,
6533 X86::LCMPXCHG16, X86::MOV16rr,
6534 X86::NOT16r, X86::AX,
6535 X86::GR16RegisterClass, true);
6536 case X86::ATOMMIN16:
6537 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
6538 case X86::ATOMMAX16:
6539 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
6540 case X86::ATOMUMIN16:
6541 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
6542 case X86::ATOMUMAX16:
6543 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
6546 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6547 X86::AND8ri, X86::MOV8rm,
6548 X86::LCMPXCHG8, X86::MOV8rr,
6549 X86::NOT8r, X86::AL,
6550 X86::GR8RegisterClass);
6552 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
6553 X86::OR8ri, X86::MOV8rm,
6554 X86::LCMPXCHG8, X86::MOV8rr,
6555 X86::NOT8r, X86::AL,
6556 X86::GR8RegisterClass);
6558 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
6559 X86::XOR8ri, X86::MOV8rm,
6560 X86::LCMPXCHG8, X86::MOV8rr,
6561 X86::NOT8r, X86::AL,
6562 X86::GR8RegisterClass);
6563 case X86::ATOMNAND8:
6564 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6565 X86::AND8ri, X86::MOV8rm,
6566 X86::LCMPXCHG8, X86::MOV8rr,
6567 X86::NOT8r, X86::AL,
6568 X86::GR8RegisterClass, true);
6569 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
6570 case X86::ATOMAND64:
6571 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6572 X86::AND64ri32, X86::MOV64rm,
6573 X86::LCMPXCHG64, X86::MOV64rr,
6574 X86::NOT64r, X86::RAX,
6575 X86::GR64RegisterClass);
6577 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
6578 X86::OR64ri32, X86::MOV64rm,
6579 X86::LCMPXCHG64, X86::MOV64rr,
6580 X86::NOT64r, X86::RAX,
6581 X86::GR64RegisterClass);
6582 case X86::ATOMXOR64:
6583 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
6584 X86::XOR64ri32, X86::MOV64rm,
6585 X86::LCMPXCHG64, X86::MOV64rr,
6586 X86::NOT64r, X86::RAX,
6587 X86::GR64RegisterClass);
6588 case X86::ATOMNAND64:
6589 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6590 X86::AND64ri32, X86::MOV64rm,
6591 X86::LCMPXCHG64, X86::MOV64rr,
6592 X86::NOT64r, X86::RAX,
6593 X86::GR64RegisterClass, true);
6594 case X86::ATOMMIN64:
6595 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
6596 case X86::ATOMMAX64:
6597 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
6598 case X86::ATOMUMIN64:
6599 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
6600 case X86::ATOMUMAX64:
6601 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
6605 //===----------------------------------------------------------------------===//
6606 // X86 Optimization Hooks
6607 //===----------------------------------------------------------------------===//
6609 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6613 const SelectionDAG &DAG,
6614 unsigned Depth) const {
6615 unsigned Opc = Op.getOpcode();
6616 assert((Opc >= ISD::BUILTIN_OP_END ||
6617 Opc == ISD::INTRINSIC_WO_CHAIN ||
6618 Opc == ISD::INTRINSIC_W_CHAIN ||
6619 Opc == ISD::INTRINSIC_VOID) &&
6620 "Should use MaskedValueIsZero if you don't know whether Op"
6621 " is a target node!");
6623 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
6627 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
6628 Mask.getBitWidth() - 1);
6633 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
6634 /// node is a GlobalAddress + offset.
6635 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
6636 GlobalValue* &GA, int64_t &Offset) const{
6637 if (N->getOpcode() == X86ISD::Wrapper) {
6638 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
6639 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
6643 return TargetLowering::isGAPlusOffset(N, GA, Offset);
6646 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
6647 const TargetLowering &TLI) {
6650 if (TLI.isGAPlusOffset(Base, GV, Offset))
6651 return (GV->getAlignment() >= N && (Offset % N) == 0);
6652 // DAG combine handles the stack object case.
6656 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
6657 unsigned NumElems, MVT EVT,
6659 SelectionDAG &DAG, MachineFrameInfo *MFI,
6660 const TargetLowering &TLI) {
6662 for (unsigned i = 0; i < NumElems; ++i) {
6663 SDValue Idx = PermMask.getOperand(i);
6664 if (Idx.getOpcode() == ISD::UNDEF) {
6670 SDValue Elt = DAG.getShuffleScalarElt(N, i);
6672 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.Val)))
6676 if (Base->getOpcode() == ISD::UNDEF)
6680 if (Elt.getOpcode() == ISD::UNDEF)
6683 if (!TLI.isConsecutiveLoad(Elt.Val, Base,
6684 EVT.getSizeInBits()/8, i, MFI))
6690 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
6691 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
6692 /// if the load addresses are consecutive, non-overlapping, and in the right
6694 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
6695 const TargetLowering &TLI) {
6696 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6697 MVT VT = N->getValueType(0);
6698 MVT EVT = VT.getVectorElementType();
6699 SDValue PermMask = N->getOperand(2);
6700 unsigned NumElems = PermMask.getNumOperands();
6701 SDNode *Base = NULL;
6702 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
6706 LoadSDNode *LD = cast<LoadSDNode>(Base);
6707 if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
6708 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6709 LD->getSrcValueOffset(), LD->isVolatile());
6710 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6711 LD->getSrcValueOffset(), LD->isVolatile(),
6712 LD->getAlignment());
6715 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
6716 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
6717 const X86Subtarget *Subtarget,
6718 const TargetLowering &TLI) {
6719 unsigned NumOps = N->getNumOperands();
6721 // Ignore single operand BUILD_VECTOR.
6725 MVT VT = N->getValueType(0);
6726 MVT EVT = VT.getVectorElementType();
6727 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
6728 // We are looking for load i64 and zero extend. We want to transform
6729 // it before legalizer has a chance to expand it. Also look for i64
6730 // BUILD_PAIR bit casted to f64.
6732 // This must be an insertion into a zero vector.
6733 SDValue HighElt = N->getOperand(1);
6734 if (!isZeroNode(HighElt))
6737 // Value must be a load.
6738 SDNode *Base = N->getOperand(0).Val;
6739 if (!isa<LoadSDNode>(Base)) {
6740 if (Base->getOpcode() != ISD::BIT_CONVERT)
6742 Base = Base->getOperand(0).Val;
6743 if (!isa<LoadSDNode>(Base))
6747 // Transform it into VZEXT_LOAD addr.
6748 LoadSDNode *LD = cast<LoadSDNode>(Base);
6750 // Load must not be an extload.
6751 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
6754 return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr());
6757 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
6758 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
6759 const X86Subtarget *Subtarget) {
6760 SDValue Cond = N->getOperand(0);
6762 // If we have SSE[12] support, try to form min/max nodes.
6763 if (Subtarget->hasSSE2() &&
6764 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
6765 if (Cond.getOpcode() == ISD::SETCC) {
6766 // Get the LHS/RHS of the select.
6767 SDValue LHS = N->getOperand(1);
6768 SDValue RHS = N->getOperand(2);
6769 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
6771 unsigned Opcode = 0;
6772 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
6775 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
6778 if (!UnsafeFPMath) break;
6780 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
6782 Opcode = X86ISD::FMIN;
6785 case ISD::SETOGT: // (X > Y) ? X : Y -> max
6788 if (!UnsafeFPMath) break;
6790 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
6792 Opcode = X86ISD::FMAX;
6795 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
6798 case ISD::SETOGT: // (X > Y) ? Y : X -> min
6801 if (!UnsafeFPMath) break;
6803 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
6805 Opcode = X86ISD::FMIN;
6808 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
6811 if (!UnsafeFPMath) break;
6813 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
6815 Opcode = X86ISD::FMAX;
6821 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
6829 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
6830 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
6831 const X86Subtarget *Subtarget) {
6832 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
6833 // the FP state in cases where an emms may be missing.
6834 // A preferable solution to the general problem is to figure out the right
6835 // places to insert EMMS. This qualifies as a quick hack.
6836 StoreSDNode *St = cast<StoreSDNode>(N);
6837 if (St->getValue().getValueType().isVector() &&
6838 St->getValue().getValueType().getSizeInBits() == 64 &&
6839 isa<LoadSDNode>(St->getValue()) &&
6840 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
6841 St->getChain().hasOneUse() && !St->isVolatile()) {
6842 SDNode* LdVal = St->getValue().Val;
6844 int TokenFactorIndex = -1;
6845 SmallVector<SDValue, 8> Ops;
6846 SDNode* ChainVal = St->getChain().Val;
6847 // Must be a store of a load. We currently handle two cases: the load
6848 // is a direct child, and it's under an intervening TokenFactor. It is
6849 // possible to dig deeper under nested TokenFactors.
6850 if (ChainVal == LdVal)
6851 Ld = cast<LoadSDNode>(St->getChain());
6852 else if (St->getValue().hasOneUse() &&
6853 ChainVal->getOpcode() == ISD::TokenFactor) {
6854 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
6855 if (ChainVal->getOperand(i).Val == LdVal) {
6856 TokenFactorIndex = i;
6857 Ld = cast<LoadSDNode>(St->getValue());
6859 Ops.push_back(ChainVal->getOperand(i));
6863 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
6864 if (Subtarget->is64Bit()) {
6865 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
6866 Ld->getBasePtr(), Ld->getSrcValue(),
6867 Ld->getSrcValueOffset(), Ld->isVolatile(),
6868 Ld->getAlignment());
6869 SDValue NewChain = NewLd.getValue(1);
6870 if (TokenFactorIndex != -1) {
6871 Ops.push_back(NewChain);
6872 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6875 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
6876 St->getSrcValue(), St->getSrcValueOffset(),
6877 St->isVolatile(), St->getAlignment());
6880 // Otherwise, lower to two 32-bit copies.
6881 SDValue LoAddr = Ld->getBasePtr();
6882 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6883 DAG.getConstant(4, MVT::i32));
6885 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
6886 Ld->getSrcValue(), Ld->getSrcValueOffset(),
6887 Ld->isVolatile(), Ld->getAlignment());
6888 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
6889 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
6891 MinAlign(Ld->getAlignment(), 4));
6893 SDValue NewChain = LoLd.getValue(1);
6894 if (TokenFactorIndex != -1) {
6895 Ops.push_back(LoLd);
6896 Ops.push_back(HiLd);
6897 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6901 LoAddr = St->getBasePtr();
6902 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6903 DAG.getConstant(4, MVT::i32));
6905 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
6906 St->getSrcValue(), St->getSrcValueOffset(),
6907 St->isVolatile(), St->getAlignment());
6908 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
6909 St->getSrcValue(), St->getSrcValueOffset()+4,
6911 MinAlign(St->getAlignment(), 4));
6912 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
6918 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
6919 /// X86ISD::FXOR nodes.
6920 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
6921 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
6922 // F[X]OR(0.0, x) -> x
6923 // F[X]OR(x, 0.0) -> x
6924 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6925 if (C->getValueAPF().isPosZero())
6926 return N->getOperand(1);
6927 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6928 if (C->getValueAPF().isPosZero())
6929 return N->getOperand(0);
6933 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
6934 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
6935 // FAND(0.0, x) -> 0.0
6936 // FAND(x, 0.0) -> 0.0
6937 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6938 if (C->getValueAPF().isPosZero())
6939 return N->getOperand(0);
6940 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6941 if (C->getValueAPF().isPosZero())
6942 return N->getOperand(1);
6947 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
6948 DAGCombinerInfo &DCI) const {
6949 SelectionDAG &DAG = DCI.DAG;
6950 switch (N->getOpcode()) {
6952 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
6953 case ISD::BUILD_VECTOR:
6954 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
6955 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
6956 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
6958 case X86ISD::FOR: return PerformFORCombine(N, DAG);
6959 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
6965 //===----------------------------------------------------------------------===//
6966 // X86 Inline Assembly Support
6967 //===----------------------------------------------------------------------===//
6969 /// getConstraintType - Given a constraint letter, return the type of
6970 /// constraint it is for this target.
6971 X86TargetLowering::ConstraintType
6972 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
6973 if (Constraint.size() == 1) {
6974 switch (Constraint[0]) {
6985 return C_RegisterClass;
6990 return TargetLowering::getConstraintType(Constraint);
6993 /// LowerXConstraint - try to replace an X constraint, which matches anything,
6994 /// with another that has more specific requirements based on the type of the
6995 /// corresponding operand.
6996 const char *X86TargetLowering::
6997 LowerXConstraint(MVT ConstraintVT) const {
6998 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
6999 // 'f' like normal targets.
7000 if (ConstraintVT.isFloatingPoint()) {
7001 if (Subtarget->hasSSE2())
7003 if (Subtarget->hasSSE1())
7007 return TargetLowering::LowerXConstraint(ConstraintVT);
7010 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7011 /// vector. If it is invalid, don't add anything to Ops.
7012 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7014 std::vector<SDValue>&Ops,
7015 SelectionDAG &DAG) const {
7016 SDValue Result(0, 0);
7018 switch (Constraint) {
7021 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7022 if (C->getValue() <= 31) {
7023 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
7029 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7030 if (C->getValue() <= 255) {
7031 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
7037 // Literal immediates are always ok.
7038 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
7039 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
7043 // If we are in non-pic codegen mode, we allow the address of a global (with
7044 // an optional displacement) to be used with 'i'.
7045 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
7048 // Match either (GA) or (GA+C)
7050 Offset = GA->getOffset();
7051 } else if (Op.getOpcode() == ISD::ADD) {
7052 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7053 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7055 Offset = GA->getOffset()+C->getValue();
7057 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7058 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7060 Offset = GA->getOffset()+C->getValue();
7067 // If addressing this global requires a load (e.g. in PIC mode), we can't
7069 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
7073 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
7079 // Otherwise, not valid for this mode.
7085 Ops.push_back(Result);
7088 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7091 std::vector<unsigned> X86TargetLowering::
7092 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7094 if (Constraint.size() == 1) {
7095 // FIXME: not handling fp-stack yet!
7096 switch (Constraint[0]) { // GCC X86 Constraint Letters
7097 default: break; // Unknown constraint letter
7098 case 'A': // EAX/EDX
7099 if (VT == MVT::i32 || VT == MVT::i64)
7100 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
7102 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
7105 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
7106 else if (VT == MVT::i16)
7107 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
7108 else if (VT == MVT::i8)
7109 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
7110 else if (VT == MVT::i64)
7111 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
7116 return std::vector<unsigned>();
7119 std::pair<unsigned, const TargetRegisterClass*>
7120 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7122 // First, see if this is a constraint that directly corresponds to an LLVM
7124 if (Constraint.size() == 1) {
7125 // GCC Constraint Letters
7126 switch (Constraint[0]) {
7128 case 'r': // GENERAL_REGS
7129 case 'R': // LEGACY_REGS
7130 case 'l': // INDEX_REGS
7131 if (VT == MVT::i64 && Subtarget->is64Bit())
7132 return std::make_pair(0U, X86::GR64RegisterClass);
7134 return std::make_pair(0U, X86::GR32RegisterClass);
7135 else if (VT == MVT::i16)
7136 return std::make_pair(0U, X86::GR16RegisterClass);
7137 else if (VT == MVT::i8)
7138 return std::make_pair(0U, X86::GR8RegisterClass);
7140 case 'f': // FP Stack registers.
7141 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
7142 // value to the correct fpstack register class.
7143 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
7144 return std::make_pair(0U, X86::RFP32RegisterClass);
7145 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
7146 return std::make_pair(0U, X86::RFP64RegisterClass);
7147 return std::make_pair(0U, X86::RFP80RegisterClass);
7148 case 'y': // MMX_REGS if MMX allowed.
7149 if (!Subtarget->hasMMX()) break;
7150 return std::make_pair(0U, X86::VR64RegisterClass);
7152 case 'Y': // SSE_REGS if SSE2 allowed
7153 if (!Subtarget->hasSSE2()) break;
7155 case 'x': // SSE_REGS if SSE1 allowed
7156 if (!Subtarget->hasSSE1()) break;
7158 switch (VT.getSimpleVT()) {
7160 // Scalar SSE types.
7163 return std::make_pair(0U, X86::FR32RegisterClass);
7166 return std::make_pair(0U, X86::FR64RegisterClass);
7174 return std::make_pair(0U, X86::VR128RegisterClass);
7180 // Use the default implementation in TargetLowering to convert the register
7181 // constraint into a member of a register class.
7182 std::pair<unsigned, const TargetRegisterClass*> Res;
7183 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7185 // Not found as a standard register?
7186 if (Res.second == 0) {
7187 // GCC calls "st(0)" just plain "st".
7188 if (StringsEqualNoCase("{st}", Constraint)) {
7189 Res.first = X86::ST0;
7190 Res.second = X86::RFP80RegisterClass;
7196 // Otherwise, check to see if this is a register class of the wrong value
7197 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
7198 // turn into {ax},{dx}.
7199 if (Res.second->hasType(VT))
7200 return Res; // Correct type already, nothing to do.
7202 // All of the single-register GCC register classes map their values onto
7203 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
7204 // really want an 8-bit or 32-bit register, map to the appropriate register
7205 // class and return the appropriate register.
7206 if (Res.second != X86::GR16RegisterClass)
7209 if (VT == MVT::i8) {
7210 unsigned DestReg = 0;
7211 switch (Res.first) {
7213 case X86::AX: DestReg = X86::AL; break;
7214 case X86::DX: DestReg = X86::DL; break;
7215 case X86::CX: DestReg = X86::CL; break;
7216 case X86::BX: DestReg = X86::BL; break;
7219 Res.first = DestReg;
7220 Res.second = Res.second = X86::GR8RegisterClass;
7222 } else if (VT == MVT::i32) {
7223 unsigned DestReg = 0;
7224 switch (Res.first) {
7226 case X86::AX: DestReg = X86::EAX; break;
7227 case X86::DX: DestReg = X86::EDX; break;
7228 case X86::CX: DestReg = X86::ECX; break;
7229 case X86::BX: DestReg = X86::EBX; break;
7230 case X86::SI: DestReg = X86::ESI; break;
7231 case X86::DI: DestReg = X86::EDI; break;
7232 case X86::BP: DestReg = X86::EBP; break;
7233 case X86::SP: DestReg = X86::ESP; break;
7236 Res.first = DestReg;
7237 Res.second = Res.second = X86::GR32RegisterClass;
7239 } else if (VT == MVT::i64) {
7240 unsigned DestReg = 0;
7241 switch (Res.first) {
7243 case X86::AX: DestReg = X86::RAX; break;
7244 case X86::DX: DestReg = X86::RDX; break;
7245 case X86::CX: DestReg = X86::RCX; break;
7246 case X86::BX: DestReg = X86::RBX; break;
7247 case X86::SI: DestReg = X86::RSI; break;
7248 case X86::DI: DestReg = X86::RDI; break;
7249 case X86::BP: DestReg = X86::RBP; break;
7250 case X86::SP: DestReg = X86::RSP; break;
7253 Res.first = DestReg;
7254 Res.second = Res.second = X86::GR64RegisterClass;