1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::XOR, MVT::i1, Legal);
1332 setOperationAction(ISD::OR, MVT::i1, Legal);
1333 setOperationAction(ISD::AND, MVT::i1, Legal);
1334 setOperationAction(ISD::SUB, MVT::i1, Custom);
1335 setOperationAction(ISD::ADD, MVT::i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::i1, Custom);
1337 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1343 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1350 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1356 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1360 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1379 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1381 if (Subtarget->hasVLX()){
1382 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1385 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1388 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1394 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1401 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1407 if (Subtarget->hasVLX()) {
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1418 if (Subtarget->hasVLX()) {
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 if (Subtarget->hasDQI()) {
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1444 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1464 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1518 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1520 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1521 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1524 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1535 if (Subtarget->hasDQI()) {
1536 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1537 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1538 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1540 // Custom lower several nodes.
1541 for (MVT VT : MVT::vector_valuetypes()) {
1542 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 setOperationAction(ISD::AND, VT, Legal);
1545 setOperationAction(ISD::OR, VT, Legal);
1546 setOperationAction(ISD::XOR, VT, Legal);
1548 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1549 setOperationAction(ISD::MGATHER, VT, Custom);
1550 setOperationAction(ISD::MSCATTER, VT, Custom);
1552 // Extract subvector is special because the value type
1553 // (result) is 256/128-bit but the source is 512-bit wide.
1554 if (VT.is128BitVector() || VT.is256BitVector()) {
1555 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1557 if (VT.getVectorElementType() == MVT::i1)
1558 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1560 // Do not attempt to custom lower other non-512-bit vectors
1561 if (!VT.is512BitVector())
1564 if (EltSize >= 32) {
1565 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1566 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1567 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1568 setOperationAction(ISD::VSELECT, VT, Legal);
1569 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1570 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1571 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1572 setOperationAction(ISD::MLOAD, VT, Legal);
1573 setOperationAction(ISD::MSTORE, VT, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 MVT VT = (MVT::SimpleValueType)i;
1579 // Do not attempt to promote non-512-bit vectors.
1580 if (!VT.is512BitVector())
1583 setOperationAction(ISD::SELECT, VT, Promote);
1584 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1588 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1589 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1590 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1592 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1593 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1595 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1596 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1597 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1598 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1599 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1602 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1603 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1604 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1605 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1606 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1607 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1608 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1609 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1610 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1611 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1612 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1613 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1614 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1615 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1616 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1617 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1618 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1619 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1620 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1621 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1622 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1623 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1624 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1625 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1626 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1627 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1628 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1629 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1630 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1631 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1632 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1633 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1635 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1636 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1637 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1638 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1639 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1640 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1641 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1642 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1644 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1645 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1646 if (Subtarget->hasVLX())
1647 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1649 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1650 const MVT VT = (MVT::SimpleValueType)i;
1652 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1654 // Do not attempt to promote non-512-bit vectors.
1655 if (!VT.is512BitVector())
1659 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1660 setOperationAction(ISD::VSELECT, VT, Legal);
1665 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1666 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1667 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1669 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1670 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1671 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1672 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1673 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1674 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1675 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1676 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1677 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1678 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1679 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1680 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1682 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1683 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1684 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1685 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1686 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1687 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1688 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1689 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1691 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1692 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1693 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1694 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1695 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1696 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1697 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1698 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1701 // We want to custom lower some of our intrinsics.
1702 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1703 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1704 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1705 if (!Subtarget->is64Bit())
1706 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1708 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1709 // handle type legalization for these operations here.
1711 // FIXME: We really should do custom legalization for addition and
1712 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1713 // than generic legalization for 64-bit multiplication-with-overflow, though.
1714 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1715 // Add/Sub/Mul with overflow operations are custom lowered.
1717 setOperationAction(ISD::SADDO, VT, Custom);
1718 setOperationAction(ISD::UADDO, VT, Custom);
1719 setOperationAction(ISD::SSUBO, VT, Custom);
1720 setOperationAction(ISD::USUBO, VT, Custom);
1721 setOperationAction(ISD::SMULO, VT, Custom);
1722 setOperationAction(ISD::UMULO, VT, Custom);
1725 if (!Subtarget->is64Bit()) {
1726 // These libcalls are not available in 32-bit.
1727 setLibcallName(RTLIB::SHL_I128, nullptr);
1728 setLibcallName(RTLIB::SRL_I128, nullptr);
1729 setLibcallName(RTLIB::SRA_I128, nullptr);
1732 // Combine sin / cos into one node or libcall if possible.
1733 if (Subtarget->hasSinCos()) {
1734 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1735 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1736 if (Subtarget->isTargetDarwin()) {
1737 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1738 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1739 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1740 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1744 if (Subtarget->isTargetWin64()) {
1745 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1746 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1747 setOperationAction(ISD::SREM, MVT::i128, Custom);
1748 setOperationAction(ISD::UREM, MVT::i128, Custom);
1749 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1750 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1753 // We have target-specific dag combine patterns for the following nodes:
1754 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1755 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1756 setTargetDAGCombine(ISD::BITCAST);
1757 setTargetDAGCombine(ISD::VSELECT);
1758 setTargetDAGCombine(ISD::SELECT);
1759 setTargetDAGCombine(ISD::SHL);
1760 setTargetDAGCombine(ISD::SRA);
1761 setTargetDAGCombine(ISD::SRL);
1762 setTargetDAGCombine(ISD::OR);
1763 setTargetDAGCombine(ISD::AND);
1764 setTargetDAGCombine(ISD::ADD);
1765 setTargetDAGCombine(ISD::FADD);
1766 setTargetDAGCombine(ISD::FSUB);
1767 setTargetDAGCombine(ISD::FMA);
1768 setTargetDAGCombine(ISD::SUB);
1769 setTargetDAGCombine(ISD::LOAD);
1770 setTargetDAGCombine(ISD::MLOAD);
1771 setTargetDAGCombine(ISD::STORE);
1772 setTargetDAGCombine(ISD::MSTORE);
1773 setTargetDAGCombine(ISD::ZERO_EXTEND);
1774 setTargetDAGCombine(ISD::ANY_EXTEND);
1775 setTargetDAGCombine(ISD::SIGN_EXTEND);
1776 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1777 setTargetDAGCombine(ISD::SINT_TO_FP);
1778 setTargetDAGCombine(ISD::UINT_TO_FP);
1779 setTargetDAGCombine(ISD::SETCC);
1780 setTargetDAGCombine(ISD::BUILD_VECTOR);
1781 setTargetDAGCombine(ISD::MUL);
1782 setTargetDAGCombine(ISD::XOR);
1784 computeRegisterProperties(Subtarget->getRegisterInfo());
1786 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1787 MaxStoresPerMemsetOptSize = 8;
1788 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1789 MaxStoresPerMemcpyOptSize = 4;
1790 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1791 MaxStoresPerMemmoveOptSize = 4;
1792 setPrefLoopAlignment(4); // 2^4 bytes.
1794 // A predictable cmov does not hurt on an in-order CPU.
1795 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1796 PredictableSelectIsExpensive = !Subtarget->isAtom();
1797 EnableExtLdPromotion = true;
1798 setPrefFunctionAlignment(4); // 2^4 bytes.
1800 verifyIntrinsicTables();
1803 // This has so far only been implemented for 64-bit MachO.
1804 bool X86TargetLowering::useLoadStackGuardNode() const {
1805 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1808 TargetLoweringBase::LegalizeTypeAction
1809 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1810 if (ExperimentalVectorWideningLegalization &&
1811 VT.getVectorNumElements() != 1 &&
1812 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1813 return TypeWidenVector;
1815 return TargetLoweringBase::getPreferredVectorAction(VT);
1818 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1821 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1823 const unsigned NumElts = VT.getVectorNumElements();
1824 const EVT EltVT = VT.getVectorElementType();
1825 if (VT.is512BitVector()) {
1826 if (Subtarget->hasAVX512())
1827 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1828 EltVT == MVT::f32 || EltVT == MVT::f64)
1830 case 8: return MVT::v8i1;
1831 case 16: return MVT::v16i1;
1833 if (Subtarget->hasBWI())
1834 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1836 case 32: return MVT::v32i1;
1837 case 64: return MVT::v64i1;
1841 if (VT.is256BitVector() || VT.is128BitVector()) {
1842 if (Subtarget->hasVLX())
1843 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1844 EltVT == MVT::f32 || EltVT == MVT::f64)
1846 case 2: return MVT::v2i1;
1847 case 4: return MVT::v4i1;
1848 case 8: return MVT::v8i1;
1850 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1851 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1853 case 8: return MVT::v8i1;
1854 case 16: return MVT::v16i1;
1855 case 32: return MVT::v32i1;
1859 return VT.changeVectorElementTypeToInteger();
1862 /// Helper for getByValTypeAlignment to determine
1863 /// the desired ByVal argument alignment.
1864 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1867 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1868 if (VTy->getBitWidth() == 128)
1870 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1871 unsigned EltAlign = 0;
1872 getMaxByValAlign(ATy->getElementType(), EltAlign);
1873 if (EltAlign > MaxAlign)
1874 MaxAlign = EltAlign;
1875 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1876 for (auto *EltTy : STy->elements()) {
1877 unsigned EltAlign = 0;
1878 getMaxByValAlign(EltTy, EltAlign);
1879 if (EltAlign > MaxAlign)
1880 MaxAlign = EltAlign;
1887 /// Return the desired alignment for ByVal aggregate
1888 /// function arguments in the caller parameter area. For X86, aggregates
1889 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1890 /// are at 4-byte boundaries.
1891 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1892 const DataLayout &DL) const {
1893 if (Subtarget->is64Bit()) {
1894 // Max of 8 and alignment of type.
1895 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1902 if (Subtarget->hasSSE1())
1903 getMaxByValAlign(Ty, Align);
1907 /// Returns the target specific optimal type for load
1908 /// and store operations as a result of memset, memcpy, and memmove
1909 /// lowering. If DstAlign is zero that means it's safe to destination
1910 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1911 /// means there isn't a need to check it against alignment requirement,
1912 /// probably because the source does not need to be loaded. If 'IsMemset' is
1913 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1914 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1915 /// source is constant so it does not need to be loaded.
1916 /// It returns EVT::Other if the type should be determined using generic
1917 /// target-independent logic.
1919 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1920 unsigned DstAlign, unsigned SrcAlign,
1921 bool IsMemset, bool ZeroMemset,
1923 MachineFunction &MF) const {
1924 const Function *F = MF.getFunction();
1925 if ((!IsMemset || ZeroMemset) &&
1926 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1928 (!Subtarget->isUnalignedMem16Slow() ||
1929 ((DstAlign == 0 || DstAlign >= 16) &&
1930 (SrcAlign == 0 || SrcAlign >= 16)))) {
1932 // FIXME: Check if unaligned 32-byte accesses are slow.
1933 if (Subtarget->hasInt256())
1935 if (Subtarget->hasFp256())
1938 if (Subtarget->hasSSE2())
1940 if (Subtarget->hasSSE1())
1942 } else if (!MemcpyStrSrc && Size >= 8 &&
1943 !Subtarget->is64Bit() &&
1944 Subtarget->hasSSE2()) {
1945 // Do not use f64 to lower memcpy if source is string constant. It's
1946 // better to use i32 to avoid the loads.
1950 // This is a compromise. If we reach here, unaligned accesses may be slow on
1951 // this target. However, creating smaller, aligned accesses could be even
1952 // slower and would certainly be a lot more code.
1953 if (Subtarget->is64Bit() && Size >= 8)
1958 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1960 return X86ScalarSSEf32;
1961 else if (VT == MVT::f64)
1962 return X86ScalarSSEf64;
1967 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1972 switch (VT.getSizeInBits()) {
1974 // 8-byte and under are always assumed to be fast.
1978 *Fast = !Subtarget->isUnalignedMem16Slow();
1981 *Fast = !Subtarget->isUnalignedMem32Slow();
1983 // TODO: What about AVX-512 (512-bit) accesses?
1986 // Misaligned accesses of any size are always allowed.
1990 /// Return the entry encoding for a jump table in the
1991 /// current function. The returned value is a member of the
1992 /// MachineJumpTableInfo::JTEntryKind enum.
1993 unsigned X86TargetLowering::getJumpTableEncoding() const {
1994 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1996 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1997 Subtarget->isPICStyleGOT())
1998 return MachineJumpTableInfo::EK_Custom32;
2000 // Otherwise, use the normal jump table encoding heuristics.
2001 return TargetLowering::getJumpTableEncoding();
2004 bool X86TargetLowering::useSoftFloat() const {
2005 return Subtarget->useSoftFloat();
2009 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2010 const MachineBasicBlock *MBB,
2011 unsigned uid,MCContext &Ctx) const{
2012 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2013 Subtarget->isPICStyleGOT());
2014 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2016 return MCSymbolRefExpr::create(MBB->getSymbol(),
2017 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2020 /// Returns relocation base for the given PIC jumptable.
2021 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2022 SelectionDAG &DAG) const {
2023 if (!Subtarget->is64Bit())
2024 // This doesn't have SDLoc associated with it, but is not really the
2025 // same as a Register.
2026 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2027 getPointerTy(DAG.getDataLayout()));
2031 /// This returns the relocation base for the given PIC jumptable,
2032 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2033 const MCExpr *X86TargetLowering::
2034 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2035 MCContext &Ctx) const {
2036 // X86-64 uses RIP relative addressing based on the jump table label.
2037 if (Subtarget->isPICStyleRIPRel())
2038 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2040 // Otherwise, the reference is relative to the PIC base.
2041 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2044 std::pair<const TargetRegisterClass *, uint8_t>
2045 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2047 const TargetRegisterClass *RRC = nullptr;
2049 switch (VT.SimpleTy) {
2051 return TargetLowering::findRepresentativeClass(TRI, VT);
2052 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2053 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2056 RRC = &X86::VR64RegClass;
2058 case MVT::f32: case MVT::f64:
2059 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2060 case MVT::v4f32: case MVT::v2f64:
2061 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2063 RRC = &X86::VR128RegClass;
2066 return std::make_pair(RRC, Cost);
2069 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2070 unsigned &Offset) const {
2071 if (!Subtarget->isTargetLinux())
2074 if (Subtarget->is64Bit()) {
2075 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2077 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2089 /// Android provides a fixed TLS slot for the SafeStack pointer.
2090 /// See the definition of TLS_SLOT_SAFESTACK in
2091 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2092 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2093 unsigned &Offset) const {
2094 if (!Subtarget->isTargetAndroid())
2097 if (Subtarget->is64Bit()) {
2098 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2100 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2112 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2113 unsigned DestAS) const {
2114 assert(SrcAS != DestAS && "Expected different address spaces!");
2116 return SrcAS < 256 && DestAS < 256;
2119 //===----------------------------------------------------------------------===//
2120 // Return Value Calling Convention Implementation
2121 //===----------------------------------------------------------------------===//
2123 #include "X86GenCallingConv.inc"
2125 bool X86TargetLowering::CanLowerReturn(
2126 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2127 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2128 SmallVector<CCValAssign, 16> RVLocs;
2129 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2130 return CCInfo.CheckReturn(Outs, RetCC_X86);
2133 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2134 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2139 X86TargetLowering::LowerReturn(SDValue Chain,
2140 CallingConv::ID CallConv, bool isVarArg,
2141 const SmallVectorImpl<ISD::OutputArg> &Outs,
2142 const SmallVectorImpl<SDValue> &OutVals,
2143 SDLoc dl, SelectionDAG &DAG) const {
2144 MachineFunction &MF = DAG.getMachineFunction();
2145 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2147 SmallVector<CCValAssign, 16> RVLocs;
2148 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2149 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2152 SmallVector<SDValue, 6> RetOps;
2153 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2154 // Operand #1 = Bytes To Pop
2155 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2158 // Copy the result values into the output registers.
2159 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2160 CCValAssign &VA = RVLocs[i];
2161 assert(VA.isRegLoc() && "Can only return in registers!");
2162 SDValue ValToCopy = OutVals[i];
2163 EVT ValVT = ValToCopy.getValueType();
2165 // Promote values to the appropriate types.
2166 if (VA.getLocInfo() == CCValAssign::SExt)
2167 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2168 else if (VA.getLocInfo() == CCValAssign::ZExt)
2169 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2170 else if (VA.getLocInfo() == CCValAssign::AExt) {
2171 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2172 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2174 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2176 else if (VA.getLocInfo() == CCValAssign::BCvt)
2177 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2179 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2180 "Unexpected FP-extend for return value.");
2182 // If this is x86-64, and we disabled SSE, we can't return FP values,
2183 // or SSE or MMX vectors.
2184 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2185 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2186 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2187 report_fatal_error("SSE register return with SSE disabled");
2189 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2190 // llvm-gcc has never done it right and no one has noticed, so this
2191 // should be OK for now.
2192 if (ValVT == MVT::f64 &&
2193 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2194 report_fatal_error("SSE2 register return with SSE2 disabled");
2196 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2197 // the RET instruction and handled by the FP Stackifier.
2198 if (VA.getLocReg() == X86::FP0 ||
2199 VA.getLocReg() == X86::FP1) {
2200 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2201 // change the value to the FP stack register class.
2202 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2203 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2204 RetOps.push_back(ValToCopy);
2205 // Don't emit a copytoreg.
2209 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2210 // which is returned in RAX / RDX.
2211 if (Subtarget->is64Bit()) {
2212 if (ValVT == MVT::x86mmx) {
2213 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2214 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2215 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2217 // If we don't have SSE2 available, convert to v4f32 so the generated
2218 // register is legal.
2219 if (!Subtarget->hasSSE2())
2220 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2225 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2226 Flag = Chain.getValue(1);
2227 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2230 // All x86 ABIs require that for returning structs by value we copy
2231 // the sret argument into %rax/%eax (depending on ABI) for the return.
2232 // We saved the argument into a virtual register in the entry block,
2233 // so now we copy the value out and into %rax/%eax.
2235 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2236 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2237 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2238 // either case FuncInfo->setSRetReturnReg() will have been called.
2239 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2240 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2241 getPointerTy(MF.getDataLayout()));
2244 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2245 X86::RAX : X86::EAX;
2246 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2247 Flag = Chain.getValue(1);
2249 // RAX/EAX now acts like a return value.
2251 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2254 RetOps[0] = Chain; // Update chain.
2256 // Add the flag if we have it.
2258 RetOps.push_back(Flag);
2260 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2263 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2264 if (N->getNumValues() != 1)
2266 if (!N->hasNUsesOfValue(1, 0))
2269 SDValue TCChain = Chain;
2270 SDNode *Copy = *N->use_begin();
2271 if (Copy->getOpcode() == ISD::CopyToReg) {
2272 // If the copy has a glue operand, we conservatively assume it isn't safe to
2273 // perform a tail call.
2274 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2276 TCChain = Copy->getOperand(0);
2277 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2280 bool HasRet = false;
2281 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2283 if (UI->getOpcode() != X86ISD::RET_FLAG)
2285 // If we are returning more than one value, we can definitely
2286 // not make a tail call see PR19530
2287 if (UI->getNumOperands() > 4)
2289 if (UI->getNumOperands() == 4 &&
2290 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2303 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2304 ISD::NodeType ExtendKind) const {
2306 // TODO: Is this also valid on 32-bit?
2307 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2308 ReturnMVT = MVT::i8;
2310 ReturnMVT = MVT::i32;
2312 EVT MinVT = getRegisterType(Context, ReturnMVT);
2313 return VT.bitsLT(MinVT) ? MinVT : VT;
2316 /// Lower the result values of a call into the
2317 /// appropriate copies out of appropriate physical registers.
2320 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2321 CallingConv::ID CallConv, bool isVarArg,
2322 const SmallVectorImpl<ISD::InputArg> &Ins,
2323 SDLoc dl, SelectionDAG &DAG,
2324 SmallVectorImpl<SDValue> &InVals) const {
2326 // Assign locations to each value returned by this call.
2327 SmallVector<CCValAssign, 16> RVLocs;
2328 bool Is64Bit = Subtarget->is64Bit();
2329 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2331 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2333 // Copy all of the result registers out of their specified physreg.
2334 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2335 CCValAssign &VA = RVLocs[i];
2336 EVT CopyVT = VA.getLocVT();
2338 // If this is x86-64, and we disabled SSE, we can't return FP values
2339 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2340 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2341 report_fatal_error("SSE register return with SSE disabled");
2344 // If we prefer to use the value in xmm registers, copy it out as f80 and
2345 // use a truncate to move it from fp stack reg to xmm reg.
2346 bool RoundAfterCopy = false;
2347 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2348 isScalarFPTypeInSSEReg(VA.getValVT())) {
2350 RoundAfterCopy = (CopyVT != VA.getLocVT());
2353 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2354 CopyVT, InFlag).getValue(1);
2355 SDValue Val = Chain.getValue(0);
2358 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2359 // This truncation won't change the value.
2360 DAG.getIntPtrConstant(1, dl));
2362 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2363 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2365 InFlag = Chain.getValue(2);
2366 InVals.push_back(Val);
2372 //===----------------------------------------------------------------------===//
2373 // C & StdCall & Fast Calling Convention implementation
2374 //===----------------------------------------------------------------------===//
2375 // StdCall calling convention seems to be standard for many Windows' API
2376 // routines and around. It differs from C calling convention just a little:
2377 // callee should clean up the stack, not caller. Symbols should be also
2378 // decorated in some fancy way :) It doesn't support any vector arguments.
2379 // For info on fast calling convention see Fast Calling Convention (tail call)
2380 // implementation LowerX86_32FastCCCallTo.
2382 /// CallIsStructReturn - Determines whether a call uses struct return
2384 enum StructReturnType {
2389 static StructReturnType
2390 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2392 return NotStructReturn;
2394 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2395 if (!Flags.isSRet())
2396 return NotStructReturn;
2397 if (Flags.isInReg())
2398 return RegStructReturn;
2399 return StackStructReturn;
2402 /// Determines whether a function uses struct return semantics.
2403 static StructReturnType
2404 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2406 return NotStructReturn;
2408 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2409 if (!Flags.isSRet())
2410 return NotStructReturn;
2411 if (Flags.isInReg())
2412 return RegStructReturn;
2413 return StackStructReturn;
2416 /// Make a copy of an aggregate at address specified by "Src" to address
2417 /// "Dst" with size and alignment information specified by the specific
2418 /// parameter attribute. The copy will be passed as a byval function parameter.
2420 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2421 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2423 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2425 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2426 /*isVolatile*/false, /*AlwaysInline=*/true,
2427 /*isTailCall*/false,
2428 MachinePointerInfo(), MachinePointerInfo());
2431 /// Return true if the calling convention is one that
2432 /// supports tail call optimization.
2433 static bool IsTailCallConvention(CallingConv::ID CC) {
2434 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2435 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2438 /// \brief Return true if the calling convention is a C calling convention.
2439 static bool IsCCallConvention(CallingConv::ID CC) {
2440 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2441 CC == CallingConv::X86_64_SysV);
2444 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2446 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2447 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2451 CallingConv::ID CalleeCC = CS.getCallingConv();
2452 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2458 /// Return true if the function is being made into
2459 /// a tailcall target by changing its ABI.
2460 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2461 bool GuaranteedTailCallOpt) {
2462 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2466 X86TargetLowering::LowerMemArgument(SDValue Chain,
2467 CallingConv::ID CallConv,
2468 const SmallVectorImpl<ISD::InputArg> &Ins,
2469 SDLoc dl, SelectionDAG &DAG,
2470 const CCValAssign &VA,
2471 MachineFrameInfo *MFI,
2473 // Create the nodes corresponding to a load from this parameter slot.
2474 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2475 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2476 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2477 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2480 // If value is passed by pointer we have address passed instead of the value
2482 bool ExtendedInMem = VA.isExtInLoc() &&
2483 VA.getValVT().getScalarType() == MVT::i1;
2485 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2486 ValVT = VA.getLocVT();
2488 ValVT = VA.getValVT();
2490 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2491 // changed with more analysis.
2492 // In case of tail call optimization mark all arguments mutable. Since they
2493 // could be overwritten by lowering of arguments in case of a tail call.
2494 if (Flags.isByVal()) {
2495 unsigned Bytes = Flags.getByValSize();
2496 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2497 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2498 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2500 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2501 VA.getLocMemOffset(), isImmutable);
2502 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2503 SDValue Val = DAG.getLoad(
2504 ValVT, dl, Chain, FIN,
2505 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2507 return ExtendedInMem ?
2508 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2512 // FIXME: Get this from tablegen.
2513 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2514 const X86Subtarget *Subtarget) {
2515 assert(Subtarget->is64Bit());
2517 if (Subtarget->isCallingConvWin64(CallConv)) {
2518 static const MCPhysReg GPR64ArgRegsWin64[] = {
2519 X86::RCX, X86::RDX, X86::R8, X86::R9
2521 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2524 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2525 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2527 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2530 // FIXME: Get this from tablegen.
2531 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2532 CallingConv::ID CallConv,
2533 const X86Subtarget *Subtarget) {
2534 assert(Subtarget->is64Bit());
2535 if (Subtarget->isCallingConvWin64(CallConv)) {
2536 // The XMM registers which might contain var arg parameters are shadowed
2537 // in their paired GPR. So we only need to save the GPR to their home
2539 // TODO: __vectorcall will change this.
2543 const Function *Fn = MF.getFunction();
2544 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2545 bool isSoftFloat = Subtarget->useSoftFloat();
2546 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2547 "SSE register cannot be used when SSE is disabled!");
2548 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2549 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2553 static const MCPhysReg XMMArgRegs64Bit[] = {
2554 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2555 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2557 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2560 SDValue X86TargetLowering::LowerFormalArguments(
2561 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2562 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2563 SmallVectorImpl<SDValue> &InVals) const {
2564 MachineFunction &MF = DAG.getMachineFunction();
2565 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2566 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2568 const Function* Fn = MF.getFunction();
2569 if (Fn->hasExternalLinkage() &&
2570 Subtarget->isTargetCygMing() &&
2571 Fn->getName() == "main")
2572 FuncInfo->setForceFramePointer(true);
2574 MachineFrameInfo *MFI = MF.getFrameInfo();
2575 bool Is64Bit = Subtarget->is64Bit();
2576 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2578 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2579 "Var args not supported with calling convention fastcc, ghc or hipe");
2581 // Assign locations to all of the incoming arguments.
2582 SmallVector<CCValAssign, 16> ArgLocs;
2583 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2585 // Allocate shadow area for Win64
2587 CCInfo.AllocateStack(32, 8);
2589 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2591 unsigned LastVal = ~0U;
2593 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2594 CCValAssign &VA = ArgLocs[i];
2595 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2597 assert(VA.getValNo() != LastVal &&
2598 "Don't support value assigned to multiple locs yet");
2600 LastVal = VA.getValNo();
2602 if (VA.isRegLoc()) {
2603 EVT RegVT = VA.getLocVT();
2604 const TargetRegisterClass *RC;
2605 if (RegVT == MVT::i32)
2606 RC = &X86::GR32RegClass;
2607 else if (Is64Bit && RegVT == MVT::i64)
2608 RC = &X86::GR64RegClass;
2609 else if (RegVT == MVT::f32)
2610 RC = &X86::FR32RegClass;
2611 else if (RegVT == MVT::f64)
2612 RC = &X86::FR64RegClass;
2613 else if (RegVT.is512BitVector())
2614 RC = &X86::VR512RegClass;
2615 else if (RegVT.is256BitVector())
2616 RC = &X86::VR256RegClass;
2617 else if (RegVT.is128BitVector())
2618 RC = &X86::VR128RegClass;
2619 else if (RegVT == MVT::x86mmx)
2620 RC = &X86::VR64RegClass;
2621 else if (RegVT == MVT::i1)
2622 RC = &X86::VK1RegClass;
2623 else if (RegVT == MVT::v8i1)
2624 RC = &X86::VK8RegClass;
2625 else if (RegVT == MVT::v16i1)
2626 RC = &X86::VK16RegClass;
2627 else if (RegVT == MVT::v32i1)
2628 RC = &X86::VK32RegClass;
2629 else if (RegVT == MVT::v64i1)
2630 RC = &X86::VK64RegClass;
2632 llvm_unreachable("Unknown argument type!");
2634 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2635 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2637 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2638 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2640 if (VA.getLocInfo() == CCValAssign::SExt)
2641 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2642 DAG.getValueType(VA.getValVT()));
2643 else if (VA.getLocInfo() == CCValAssign::ZExt)
2644 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2645 DAG.getValueType(VA.getValVT()));
2646 else if (VA.getLocInfo() == CCValAssign::BCvt)
2647 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2649 if (VA.isExtInLoc()) {
2650 // Handle MMX values passed in XMM regs.
2651 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2652 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2654 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2657 assert(VA.isMemLoc());
2658 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2661 // If value is passed via pointer - do a load.
2662 if (VA.getLocInfo() == CCValAssign::Indirect)
2663 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2664 MachinePointerInfo(), false, false, false, 0);
2666 InVals.push_back(ArgValue);
2669 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2670 // All x86 ABIs require that for returning structs by value we copy the
2671 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2672 // the argument into a virtual register so that we can access it from the
2674 if (Ins[i].Flags.isSRet()) {
2675 unsigned Reg = FuncInfo->getSRetReturnReg();
2677 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2678 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2679 FuncInfo->setSRetReturnReg(Reg);
2681 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2682 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2687 unsigned StackSize = CCInfo.getNextStackOffset();
2688 // Align stack specially for tail calls.
2689 if (FuncIsMadeTailCallSafe(CallConv,
2690 MF.getTarget().Options.GuaranteedTailCallOpt))
2691 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2693 // If the function takes variable number of arguments, make a frame index for
2694 // the start of the first vararg value... for expansion of llvm.va_start. We
2695 // can skip this if there are no va_start calls.
2696 if (MFI->hasVAStart() &&
2697 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2698 CallConv != CallingConv::X86_ThisCall))) {
2699 FuncInfo->setVarArgsFrameIndex(
2700 MFI->CreateFixedObject(1, StackSize, true));
2703 MachineModuleInfo &MMI = MF.getMMI();
2704 const Function *WinEHParent = nullptr;
2705 if (MMI.hasWinEHFuncInfo(Fn))
2706 WinEHParent = MMI.getWinEHParent(Fn);
2707 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2709 // Figure out if XMM registers are in use.
2710 assert(!(Subtarget->useSoftFloat() &&
2711 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2712 "SSE register cannot be used when SSE is disabled!");
2714 // 64-bit calling conventions support varargs and register parameters, so we
2715 // have to do extra work to spill them in the prologue.
2716 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2717 // Find the first unallocated argument registers.
2718 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2719 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2720 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2721 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2722 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2723 "SSE register cannot be used when SSE is disabled!");
2725 // Gather all the live in physical registers.
2726 SmallVector<SDValue, 6> LiveGPRs;
2727 SmallVector<SDValue, 8> LiveXMMRegs;
2729 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2730 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2732 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2734 if (!ArgXMMs.empty()) {
2735 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2736 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2737 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2738 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2739 LiveXMMRegs.push_back(
2740 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2745 // Get to the caller-allocated home save location. Add 8 to account
2746 // for the return address.
2747 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2748 FuncInfo->setRegSaveFrameIndex(
2749 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2750 // Fixup to set vararg frame on shadow area (4 x i64).
2752 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2754 // For X86-64, if there are vararg parameters that are passed via
2755 // registers, then we must store them to their spots on the stack so
2756 // they may be loaded by deferencing the result of va_next.
2757 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2758 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2759 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2760 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2763 // Store the integer parameter registers.
2764 SmallVector<SDValue, 8> MemOps;
2765 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2766 getPointerTy(DAG.getDataLayout()));
2767 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2768 for (SDValue Val : LiveGPRs) {
2769 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2770 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2772 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2773 MachinePointerInfo::getFixedStack(
2774 DAG.getMachineFunction(),
2775 FuncInfo->getRegSaveFrameIndex(), Offset),
2777 MemOps.push_back(Store);
2781 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2782 // Now store the XMM (fp + vector) parameter registers.
2783 SmallVector<SDValue, 12> SaveXMMOps;
2784 SaveXMMOps.push_back(Chain);
2785 SaveXMMOps.push_back(ALVal);
2786 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2787 FuncInfo->getRegSaveFrameIndex(), dl));
2788 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2789 FuncInfo->getVarArgsFPOffset(), dl));
2790 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2792 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2793 MVT::Other, SaveXMMOps));
2796 if (!MemOps.empty())
2797 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2800 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2801 // Find the largest legal vector type.
2802 MVT VecVT = MVT::Other;
2803 // FIXME: Only some x86_32 calling conventions support AVX512.
2804 if (Subtarget->hasAVX512() &&
2805 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2806 CallConv == CallingConv::Intel_OCL_BI)))
2807 VecVT = MVT::v16f32;
2808 else if (Subtarget->hasAVX())
2810 else if (Subtarget->hasSSE2())
2813 // We forward some GPRs and some vector types.
2814 SmallVector<MVT, 2> RegParmTypes;
2815 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2816 RegParmTypes.push_back(IntVT);
2817 if (VecVT != MVT::Other)
2818 RegParmTypes.push_back(VecVT);
2820 // Compute the set of forwarded registers. The rest are scratch.
2821 SmallVectorImpl<ForwardedRegister> &Forwards =
2822 FuncInfo->getForwardedMustTailRegParms();
2823 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2825 // Conservatively forward AL on x86_64, since it might be used for varargs.
2826 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2827 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2828 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2831 // Copy all forwards from physical to virtual registers.
2832 for (ForwardedRegister &F : Forwards) {
2833 // FIXME: Can we use a less constrained schedule?
2834 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2835 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2836 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2840 // Some CCs need callee pop.
2841 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2842 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2843 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2845 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2846 // If this is an sret function, the return should pop the hidden pointer.
2847 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2848 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2849 argsAreStructReturn(Ins) == StackStructReturn)
2850 FuncInfo->setBytesToPopOnReturn(4);
2854 // RegSaveFrameIndex is X86-64 only.
2855 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2856 if (CallConv == CallingConv::X86_FastCall ||
2857 CallConv == CallingConv::X86_ThisCall)
2858 // fastcc functions can't have varargs.
2859 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2862 FuncInfo->setArgumentStackSize(StackSize);
2864 if (IsWinEHParent) {
2866 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2867 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2868 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2869 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2870 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2871 MachinePointerInfo::getFixedStack(
2872 DAG.getMachineFunction(), UnwindHelpFI),
2873 /*isVolatile=*/true,
2874 /*isNonTemporal=*/false, /*Alignment=*/0);
2876 // Functions using Win32 EH are considered to have opaque SP adjustments
2877 // to force local variables to be addressed from the frame or base
2879 MFI->setHasOpaqueSPAdjustment(true);
2887 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2888 SDValue StackPtr, SDValue Arg,
2889 SDLoc dl, SelectionDAG &DAG,
2890 const CCValAssign &VA,
2891 ISD::ArgFlagsTy Flags) const {
2892 unsigned LocMemOffset = VA.getLocMemOffset();
2893 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2894 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2896 if (Flags.isByVal())
2897 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2899 return DAG.getStore(
2900 Chain, dl, Arg, PtrOff,
2901 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2905 /// Emit a load of return address if tail call
2906 /// optimization is performed and it is required.
2908 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2909 SDValue &OutRetAddr, SDValue Chain,
2910 bool IsTailCall, bool Is64Bit,
2911 int FPDiff, SDLoc dl) const {
2912 // Adjust the Return address stack slot.
2913 EVT VT = getPointerTy(DAG.getDataLayout());
2914 OutRetAddr = getReturnAddressFrameIndex(DAG);
2916 // Load the "old" Return address.
2917 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2918 false, false, false, 0);
2919 return SDValue(OutRetAddr.getNode(), 1);
2922 /// Emit a store of the return address if tail call
2923 /// optimization is performed and it is required (FPDiff!=0).
2924 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2925 SDValue Chain, SDValue RetAddrFrIdx,
2926 EVT PtrVT, unsigned SlotSize,
2927 int FPDiff, SDLoc dl) {
2928 // Store the return address to the appropriate stack slot.
2929 if (!FPDiff) return Chain;
2930 // Calculate the new stack slot for the return address.
2931 int NewReturnAddrFI =
2932 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2934 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2935 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2936 MachinePointerInfo::getFixedStack(
2937 DAG.getMachineFunction(), NewReturnAddrFI),
2942 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2943 /// operation of specified width.
2944 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2946 unsigned NumElems = VT.getVectorNumElements();
2947 SmallVector<int, 8> Mask;
2948 Mask.push_back(NumElems);
2949 for (unsigned i = 1; i != NumElems; ++i)
2951 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2955 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2956 SmallVectorImpl<SDValue> &InVals) const {
2957 SelectionDAG &DAG = CLI.DAG;
2959 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2960 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2961 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2962 SDValue Chain = CLI.Chain;
2963 SDValue Callee = CLI.Callee;
2964 CallingConv::ID CallConv = CLI.CallConv;
2965 bool &isTailCall = CLI.IsTailCall;
2966 bool isVarArg = CLI.IsVarArg;
2968 MachineFunction &MF = DAG.getMachineFunction();
2969 bool Is64Bit = Subtarget->is64Bit();
2970 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2971 StructReturnType SR = callIsStructReturn(Outs);
2972 bool IsSibcall = false;
2973 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2974 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2976 if (Attr.getValueAsString() == "true")
2979 if (Subtarget->isPICStyleGOT() &&
2980 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2981 // If we are using a GOT, disable tail calls to external symbols with
2982 // default visibility. Tail calling such a symbol requires using a GOT
2983 // relocation, which forces early binding of the symbol. This breaks code
2984 // that require lazy function symbol resolution. Using musttail or
2985 // GuaranteedTailCallOpt will override this.
2986 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2987 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2988 G->getGlobal()->hasDefaultVisibility()))
2992 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2994 // Force this to be a tail call. The verifier rules are enough to ensure
2995 // that we can lower this successfully without moving the return address
2998 } else if (isTailCall) {
2999 // Check if it's really possible to do a tail call.
3000 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3001 isVarArg, SR != NotStructReturn,
3002 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3003 Outs, OutVals, Ins, DAG);
3005 // Sibcalls are automatically detected tailcalls which do not require
3007 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3014 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3015 "Var args not supported with calling convention fastcc, ghc or hipe");
3017 // Analyze operands of the call, assigning locations to each operand.
3018 SmallVector<CCValAssign, 16> ArgLocs;
3019 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3021 // Allocate shadow area for Win64
3023 CCInfo.AllocateStack(32, 8);
3025 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3027 // Get a count of how many bytes are to be pushed on the stack.
3028 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3030 // This is a sibcall. The memory operands are available in caller's
3031 // own caller's stack.
3033 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3034 IsTailCallConvention(CallConv))
3035 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3038 if (isTailCall && !IsSibcall && !IsMustTail) {
3039 // Lower arguments at fp - stackoffset + fpdiff.
3040 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3042 FPDiff = NumBytesCallerPushed - NumBytes;
3044 // Set the delta of movement of the returnaddr stackslot.
3045 // But only set if delta is greater than previous delta.
3046 if (FPDiff < X86Info->getTCReturnAddrDelta())
3047 X86Info->setTCReturnAddrDelta(FPDiff);
3050 unsigned NumBytesToPush = NumBytes;
3051 unsigned NumBytesToPop = NumBytes;
3053 // If we have an inalloca argument, all stack space has already been allocated
3054 // for us and be right at the top of the stack. We don't support multiple
3055 // arguments passed in memory when using inalloca.
3056 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3058 if (!ArgLocs.back().isMemLoc())
3059 report_fatal_error("cannot use inalloca attribute on a register "
3061 if (ArgLocs.back().getLocMemOffset() != 0)
3062 report_fatal_error("any parameter with the inalloca attribute must be "
3063 "the only memory argument");
3067 Chain = DAG.getCALLSEQ_START(
3068 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3070 SDValue RetAddrFrIdx;
3071 // Load return address for tail calls.
3072 if (isTailCall && FPDiff)
3073 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3074 Is64Bit, FPDiff, dl);
3076 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3077 SmallVector<SDValue, 8> MemOpChains;
3080 // Walk the register/memloc assignments, inserting copies/loads. In the case
3081 // of tail call optimization arguments are handle later.
3082 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3083 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3084 // Skip inalloca arguments, they have already been written.
3085 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3086 if (Flags.isInAlloca())
3089 CCValAssign &VA = ArgLocs[i];
3090 EVT RegVT = VA.getLocVT();
3091 SDValue Arg = OutVals[i];
3092 bool isByVal = Flags.isByVal();
3094 // Promote the value if needed.
3095 switch (VA.getLocInfo()) {
3096 default: llvm_unreachable("Unknown loc info!");
3097 case CCValAssign::Full: break;
3098 case CCValAssign::SExt:
3099 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3101 case CCValAssign::ZExt:
3102 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3104 case CCValAssign::AExt:
3105 if (Arg.getValueType().isVector() &&
3106 Arg.getValueType().getScalarType() == MVT::i1)
3107 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3108 else if (RegVT.is128BitVector()) {
3109 // Special case: passing MMX values in XMM registers.
3110 Arg = DAG.getBitcast(MVT::i64, Arg);
3111 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3112 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3114 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3116 case CCValAssign::BCvt:
3117 Arg = DAG.getBitcast(RegVT, Arg);
3119 case CCValAssign::Indirect: {
3120 // Store the argument.
3121 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3122 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3123 Chain = DAG.getStore(
3124 Chain, dl, Arg, SpillSlot,
3125 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3132 if (VA.isRegLoc()) {
3133 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3134 if (isVarArg && IsWin64) {
3135 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3136 // shadow reg if callee is a varargs function.
3137 unsigned ShadowReg = 0;
3138 switch (VA.getLocReg()) {
3139 case X86::XMM0: ShadowReg = X86::RCX; break;
3140 case X86::XMM1: ShadowReg = X86::RDX; break;
3141 case X86::XMM2: ShadowReg = X86::R8; break;
3142 case X86::XMM3: ShadowReg = X86::R9; break;
3145 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3147 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3148 assert(VA.isMemLoc());
3149 if (!StackPtr.getNode())
3150 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3151 getPointerTy(DAG.getDataLayout()));
3152 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3153 dl, DAG, VA, Flags));
3157 if (!MemOpChains.empty())
3158 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3160 if (Subtarget->isPICStyleGOT()) {
3161 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3164 RegsToPass.push_back(std::make_pair(
3165 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3166 getPointerTy(DAG.getDataLayout()))));
3168 // If we are tail calling and generating PIC/GOT style code load the
3169 // address of the callee into ECX. The value in ecx is used as target of
3170 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3171 // for tail calls on PIC/GOT architectures. Normally we would just put the
3172 // address of GOT into ebx and then call target@PLT. But for tail calls
3173 // ebx would be restored (since ebx is callee saved) before jumping to the
3176 // Note: The actual moving to ECX is done further down.
3177 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3178 if (G && !G->getGlobal()->hasLocalLinkage() &&
3179 G->getGlobal()->hasDefaultVisibility())
3180 Callee = LowerGlobalAddress(Callee, DAG);
3181 else if (isa<ExternalSymbolSDNode>(Callee))
3182 Callee = LowerExternalSymbol(Callee, DAG);
3186 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3187 // From AMD64 ABI document:
3188 // For calls that may call functions that use varargs or stdargs
3189 // (prototype-less calls or calls to functions containing ellipsis (...) in
3190 // the declaration) %al is used as hidden argument to specify the number
3191 // of SSE registers used. The contents of %al do not need to match exactly
3192 // the number of registers, but must be an ubound on the number of SSE
3193 // registers used and is in the range 0 - 8 inclusive.
3195 // Count the number of XMM registers allocated.
3196 static const MCPhysReg XMMArgRegs[] = {
3197 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3198 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3200 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3201 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3202 && "SSE registers cannot be used when SSE is disabled");
3204 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3205 DAG.getConstant(NumXMMRegs, dl,
3209 if (isVarArg && IsMustTail) {
3210 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3211 for (const auto &F : Forwards) {
3212 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3213 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3217 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3218 // don't need this because the eligibility check rejects calls that require
3219 // shuffling arguments passed in memory.
3220 if (!IsSibcall && isTailCall) {
3221 // Force all the incoming stack arguments to be loaded from the stack
3222 // before any new outgoing arguments are stored to the stack, because the
3223 // outgoing stack slots may alias the incoming argument stack slots, and
3224 // the alias isn't otherwise explicit. This is slightly more conservative
3225 // than necessary, because it means that each store effectively depends
3226 // on every argument instead of just those arguments it would clobber.
3227 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3229 SmallVector<SDValue, 8> MemOpChains2;
3232 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3233 CCValAssign &VA = ArgLocs[i];
3236 assert(VA.isMemLoc());
3237 SDValue Arg = OutVals[i];
3238 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3239 // Skip inalloca arguments. They don't require any work.
3240 if (Flags.isInAlloca())
3242 // Create frame index.
3243 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3244 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3245 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3246 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3248 if (Flags.isByVal()) {
3249 // Copy relative to framepointer.
3250 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3251 if (!StackPtr.getNode())
3252 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3253 getPointerTy(DAG.getDataLayout()));
3254 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3257 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3261 // Store relative to framepointer.
3262 MemOpChains2.push_back(DAG.getStore(
3263 ArgChain, dl, Arg, FIN,
3264 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3269 if (!MemOpChains2.empty())
3270 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3272 // Store the return address to the appropriate stack slot.
3273 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3274 getPointerTy(DAG.getDataLayout()),
3275 RegInfo->getSlotSize(), FPDiff, dl);
3278 // Build a sequence of copy-to-reg nodes chained together with token chain
3279 // and flag operands which copy the outgoing args into registers.
3281 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3282 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3283 RegsToPass[i].second, InFlag);
3284 InFlag = Chain.getValue(1);
3287 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3288 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3289 // In the 64-bit large code model, we have to make all calls
3290 // through a register, since the call instruction's 32-bit
3291 // pc-relative offset may not be large enough to hold the whole
3293 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3294 // If the callee is a GlobalAddress node (quite common, every direct call
3295 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3297 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3299 // We should use extra load for direct calls to dllimported functions in
3301 const GlobalValue *GV = G->getGlobal();
3302 if (!GV->hasDLLImportStorageClass()) {
3303 unsigned char OpFlags = 0;
3304 bool ExtraLoad = false;
3305 unsigned WrapperKind = ISD::DELETED_NODE;
3307 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3308 // external symbols most go through the PLT in PIC mode. If the symbol
3309 // has hidden or protected visibility, or if it is static or local, then
3310 // we don't need to use the PLT - we can directly call it.
3311 if (Subtarget->isTargetELF() &&
3312 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3313 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3314 OpFlags = X86II::MO_PLT;
3315 } else if (Subtarget->isPICStyleStubAny() &&
3316 !GV->isStrongDefinitionForLinker() &&
3317 (!Subtarget->getTargetTriple().isMacOSX() ||
3318 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3319 // PC-relative references to external symbols should go through $stub,
3320 // unless we're building with the leopard linker or later, which
3321 // automatically synthesizes these stubs.
3322 OpFlags = X86II::MO_DARWIN_STUB;
3323 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3324 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3325 // If the function is marked as non-lazy, generate an indirect call
3326 // which loads from the GOT directly. This avoids runtime overhead
3327 // at the cost of eager binding (and one extra byte of encoding).
3328 OpFlags = X86II::MO_GOTPCREL;
3329 WrapperKind = X86ISD::WrapperRIP;
3333 Callee = DAG.getTargetGlobalAddress(
3334 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3336 // Add a wrapper if needed.
3337 if (WrapperKind != ISD::DELETED_NODE)
3338 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3339 getPointerTy(DAG.getDataLayout()), Callee);
3340 // Add extra indirection if needed.
3342 Callee = DAG.getLoad(
3343 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3344 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3347 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3348 unsigned char OpFlags = 0;
3350 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3351 // external symbols should go through the PLT.
3352 if (Subtarget->isTargetELF() &&
3353 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3354 OpFlags = X86II::MO_PLT;
3355 } else if (Subtarget->isPICStyleStubAny() &&
3356 (!Subtarget->getTargetTriple().isMacOSX() ||
3357 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3358 // PC-relative references to external symbols should go through $stub,
3359 // unless we're building with the leopard linker or later, which
3360 // automatically synthesizes these stubs.
3361 OpFlags = X86II::MO_DARWIN_STUB;
3364 Callee = DAG.getTargetExternalSymbol(
3365 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3366 } else if (Subtarget->isTarget64BitILP32() &&
3367 Callee->getValueType(0) == MVT::i32) {
3368 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3369 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3372 // Returns a chain & a flag for retval copy to use.
3373 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3374 SmallVector<SDValue, 8> Ops;
3376 if (!IsSibcall && isTailCall) {
3377 Chain = DAG.getCALLSEQ_END(Chain,
3378 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3379 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3380 InFlag = Chain.getValue(1);
3383 Ops.push_back(Chain);
3384 Ops.push_back(Callee);
3387 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3389 // Add argument registers to the end of the list so that they are known live
3391 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3392 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3393 RegsToPass[i].second.getValueType()));
3395 // Add a register mask operand representing the call-preserved registers.
3396 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3397 assert(Mask && "Missing call preserved mask for calling convention");
3399 // If this is an invoke in a 32-bit function using a funclet-based
3400 // personality, assume the function clobbers all registers. If an exception
3401 // is thrown, the runtime will not restore CSRs.
3402 // FIXME: Model this more precisely so that we can register allocate across
3403 // the normal edge and spill and fill across the exceptional edge.
3404 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3405 const Function *CallerFn = MF.getFunction();
3406 EHPersonality Pers =
3407 CallerFn->hasPersonalityFn()
3408 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3409 : EHPersonality::Unknown;
3410 if (isFuncletEHPersonality(Pers))
3411 Mask = RegInfo->getNoPreservedMask();
3414 Ops.push_back(DAG.getRegisterMask(Mask));
3416 if (InFlag.getNode())
3417 Ops.push_back(InFlag);
3421 //// If this is the first return lowered for this function, add the regs
3422 //// to the liveout set for the function.
3423 // This isn't right, although it's probably harmless on x86; liveouts
3424 // should be computed from returns not tail calls. Consider a void
3425 // function making a tail call to a function returning int.
3426 MF.getFrameInfo()->setHasTailCall();
3427 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3430 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3431 InFlag = Chain.getValue(1);
3433 // Create the CALLSEQ_END node.
3434 unsigned NumBytesForCalleeToPop;
3435 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3436 DAG.getTarget().Options.GuaranteedTailCallOpt))
3437 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3438 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3439 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3440 SR == StackStructReturn)
3441 // If this is a call to a struct-return function, the callee
3442 // pops the hidden struct pointer, so we have to push it back.
3443 // This is common for Darwin/X86, Linux & Mingw32 targets.
3444 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3445 NumBytesForCalleeToPop = 4;
3447 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3449 // Returns a flag for retval copy to use.
3451 Chain = DAG.getCALLSEQ_END(Chain,
3452 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3453 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3456 InFlag = Chain.getValue(1);
3459 // Handle result values, copying them out of physregs into vregs that we
3461 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3462 Ins, dl, DAG, InVals);
3465 //===----------------------------------------------------------------------===//
3466 // Fast Calling Convention (tail call) implementation
3467 //===----------------------------------------------------------------------===//
3469 // Like std call, callee cleans arguments, convention except that ECX is
3470 // reserved for storing the tail called function address. Only 2 registers are
3471 // free for argument passing (inreg). Tail call optimization is performed
3473 // * tailcallopt is enabled
3474 // * caller/callee are fastcc
3475 // On X86_64 architecture with GOT-style position independent code only local
3476 // (within module) calls are supported at the moment.
3477 // To keep the stack aligned according to platform abi the function
3478 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3479 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3480 // If a tail called function callee has more arguments than the caller the
3481 // caller needs to make sure that there is room to move the RETADDR to. This is
3482 // achieved by reserving an area the size of the argument delta right after the
3483 // original RETADDR, but before the saved framepointer or the spilled registers
3484 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3496 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3499 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3500 SelectionDAG& DAG) const {
3501 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3502 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3503 unsigned StackAlignment = TFI.getStackAlignment();
3504 uint64_t AlignMask = StackAlignment - 1;
3505 int64_t Offset = StackSize;
3506 unsigned SlotSize = RegInfo->getSlotSize();
3507 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3508 // Number smaller than 12 so just add the difference.
3509 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3511 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3512 Offset = ((~AlignMask) & Offset) + StackAlignment +
3513 (StackAlignment-SlotSize);
3518 /// Return true if the given stack call argument is already available in the
3519 /// same position (relatively) of the caller's incoming argument stack.
3521 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3522 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3523 const X86InstrInfo *TII) {
3524 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3526 if (Arg.getOpcode() == ISD::CopyFromReg) {
3527 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3528 if (!TargetRegisterInfo::isVirtualRegister(VR))
3530 MachineInstr *Def = MRI->getVRegDef(VR);
3533 if (!Flags.isByVal()) {
3534 if (!TII->isLoadFromStackSlot(Def, FI))
3537 unsigned Opcode = Def->getOpcode();
3538 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3539 Opcode == X86::LEA64_32r) &&
3540 Def->getOperand(1).isFI()) {
3541 FI = Def->getOperand(1).getIndex();
3542 Bytes = Flags.getByValSize();
3546 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3547 if (Flags.isByVal())
3548 // ByVal argument is passed in as a pointer but it's now being
3549 // dereferenced. e.g.
3550 // define @foo(%struct.X* %A) {
3551 // tail call @bar(%struct.X* byval %A)
3554 SDValue Ptr = Ld->getBasePtr();
3555 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3558 FI = FINode->getIndex();
3559 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3560 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3561 FI = FINode->getIndex();
3562 Bytes = Flags.getByValSize();
3566 assert(FI != INT_MAX);
3567 if (!MFI->isFixedObjectIndex(FI))
3569 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3572 /// Check whether the call is eligible for tail call optimization. Targets
3573 /// that want to do tail call optimization should implement this function.
3574 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3575 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3576 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3577 const SmallVectorImpl<ISD::OutputArg> &Outs,
3578 const SmallVectorImpl<SDValue> &OutVals,
3579 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3580 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3583 // If -tailcallopt is specified, make fastcc functions tail-callable.
3584 const MachineFunction &MF = DAG.getMachineFunction();
3585 const Function *CallerF = MF.getFunction();
3587 // If the function return type is x86_fp80 and the callee return type is not,
3588 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3589 // perform a tailcall optimization here.
3590 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3593 CallingConv::ID CallerCC = CallerF->getCallingConv();
3594 bool CCMatch = CallerCC == CalleeCC;
3595 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3596 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3598 // Win64 functions have extra shadow space for argument homing. Don't do the
3599 // sibcall if the caller and callee have mismatched expectations for this
3601 if (IsCalleeWin64 != IsCallerWin64)
3604 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3605 if (IsTailCallConvention(CalleeCC) && CCMatch)
3610 // Look for obvious safe cases to perform tail call optimization that do not
3611 // require ABI changes. This is what gcc calls sibcall.
3613 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3614 // emit a special epilogue.
3615 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3616 if (RegInfo->needsStackRealignment(MF))
3619 // Also avoid sibcall optimization if either caller or callee uses struct
3620 // return semantics.
3621 if (isCalleeStructRet || isCallerStructRet)
3624 // An stdcall/thiscall caller is expected to clean up its arguments; the
3625 // callee isn't going to do that.
3626 // FIXME: this is more restrictive than needed. We could produce a tailcall
3627 // when the stack adjustment matches. For example, with a thiscall that takes
3628 // only one argument.
3629 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3630 CallerCC == CallingConv::X86_ThisCall))
3633 // Do not sibcall optimize vararg calls unless all arguments are passed via
3635 if (isVarArg && !Outs.empty()) {
3637 // Optimizing for varargs on Win64 is unlikely to be safe without
3638 // additional testing.
3639 if (IsCalleeWin64 || IsCallerWin64)
3642 SmallVector<CCValAssign, 16> ArgLocs;
3643 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3646 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3647 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3648 if (!ArgLocs[i].isRegLoc())
3652 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3653 // stack. Therefore, if it's not used by the call it is not safe to optimize
3654 // this into a sibcall.
3655 bool Unused = false;
3656 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3663 SmallVector<CCValAssign, 16> RVLocs;
3664 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3666 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3667 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3668 CCValAssign &VA = RVLocs[i];
3669 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3674 // If the calling conventions do not match, then we'd better make sure the
3675 // results are returned in the same way as what the caller expects.
3677 SmallVector<CCValAssign, 16> RVLocs1;
3678 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3680 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3682 SmallVector<CCValAssign, 16> RVLocs2;
3683 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3685 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3687 if (RVLocs1.size() != RVLocs2.size())
3689 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3690 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3692 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3694 if (RVLocs1[i].isRegLoc()) {
3695 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3698 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3704 // If the callee takes no arguments then go on to check the results of the
3706 if (!Outs.empty()) {
3707 // Check if stack adjustment is needed. For now, do not do this if any
3708 // argument is passed on the stack.
3709 SmallVector<CCValAssign, 16> ArgLocs;
3710 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3713 // Allocate shadow area for Win64
3715 CCInfo.AllocateStack(32, 8);
3717 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3718 if (CCInfo.getNextStackOffset()) {
3719 MachineFunction &MF = DAG.getMachineFunction();
3720 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3723 // Check if the arguments are already laid out in the right way as
3724 // the caller's fixed stack objects.
3725 MachineFrameInfo *MFI = MF.getFrameInfo();
3726 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3727 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3728 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3729 CCValAssign &VA = ArgLocs[i];
3730 SDValue Arg = OutVals[i];
3731 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3732 if (VA.getLocInfo() == CCValAssign::Indirect)
3734 if (!VA.isRegLoc()) {
3735 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3742 // If the tailcall address may be in a register, then make sure it's
3743 // possible to register allocate for it. In 32-bit, the call address can
3744 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3745 // callee-saved registers are restored. These happen to be the same
3746 // registers used to pass 'inreg' arguments so watch out for those.
3747 if (!Subtarget->is64Bit() &&
3748 ((!isa<GlobalAddressSDNode>(Callee) &&
3749 !isa<ExternalSymbolSDNode>(Callee)) ||
3750 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3751 unsigned NumInRegs = 0;
3752 // In PIC we need an extra register to formulate the address computation
3754 unsigned MaxInRegs =
3755 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3757 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3758 CCValAssign &VA = ArgLocs[i];
3761 unsigned Reg = VA.getLocReg();
3764 case X86::EAX: case X86::EDX: case X86::ECX:
3765 if (++NumInRegs == MaxInRegs)
3777 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3778 const TargetLibraryInfo *libInfo) const {
3779 return X86::createFastISel(funcInfo, libInfo);
3782 //===----------------------------------------------------------------------===//
3783 // Other Lowering Hooks
3784 //===----------------------------------------------------------------------===//
3786 static bool MayFoldLoad(SDValue Op) {
3787 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3790 static bool MayFoldIntoStore(SDValue Op) {
3791 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3794 static bool isTargetShuffle(unsigned Opcode) {
3796 default: return false;
3797 case X86ISD::BLENDI:
3798 case X86ISD::PSHUFB:
3799 case X86ISD::PSHUFD:
3800 case X86ISD::PSHUFHW:
3801 case X86ISD::PSHUFLW:
3803 case X86ISD::PALIGNR:
3804 case X86ISD::MOVLHPS:
3805 case X86ISD::MOVLHPD:
3806 case X86ISD::MOVHLPS:
3807 case X86ISD::MOVLPS:
3808 case X86ISD::MOVLPD:
3809 case X86ISD::MOVSHDUP:
3810 case X86ISD::MOVSLDUP:
3811 case X86ISD::MOVDDUP:
3814 case X86ISD::UNPCKL:
3815 case X86ISD::UNPCKH:
3816 case X86ISD::VPERMILPI:
3817 case X86ISD::VPERM2X128:
3818 case X86ISD::VPERMI:
3819 case X86ISD::VPERMV:
3820 case X86ISD::VPERMV3:
3825 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3826 SDValue V1, unsigned TargetMask,
3827 SelectionDAG &DAG) {
3829 default: llvm_unreachable("Unknown x86 shuffle node");
3830 case X86ISD::PSHUFD:
3831 case X86ISD::PSHUFHW:
3832 case X86ISD::PSHUFLW:
3833 case X86ISD::VPERMILPI:
3834 case X86ISD::VPERMI:
3835 return DAG.getNode(Opc, dl, VT, V1,
3836 DAG.getConstant(TargetMask, dl, MVT::i8));
3840 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3841 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3843 default: llvm_unreachable("Unknown x86 shuffle node");
3844 case X86ISD::MOVLHPS:
3845 case X86ISD::MOVLHPD:
3846 case X86ISD::MOVHLPS:
3847 case X86ISD::MOVLPS:
3848 case X86ISD::MOVLPD:
3851 case X86ISD::UNPCKL:
3852 case X86ISD::UNPCKH:
3853 return DAG.getNode(Opc, dl, VT, V1, V2);
3857 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3858 MachineFunction &MF = DAG.getMachineFunction();
3859 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3860 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3861 int ReturnAddrIndex = FuncInfo->getRAIndex();
3863 if (ReturnAddrIndex == 0) {
3864 // Set up a frame object for the return address.
3865 unsigned SlotSize = RegInfo->getSlotSize();
3866 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3869 FuncInfo->setRAIndex(ReturnAddrIndex);
3872 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3875 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3876 bool hasSymbolicDisplacement) {
3877 // Offset should fit into 32 bit immediate field.
3878 if (!isInt<32>(Offset))
3881 // If we don't have a symbolic displacement - we don't have any extra
3883 if (!hasSymbolicDisplacement)
3886 // FIXME: Some tweaks might be needed for medium code model.
3887 if (M != CodeModel::Small && M != CodeModel::Kernel)
3890 // For small code model we assume that latest object is 16MB before end of 31
3891 // bits boundary. We may also accept pretty large negative constants knowing
3892 // that all objects are in the positive half of address space.
3893 if (M == CodeModel::Small && Offset < 16*1024*1024)
3896 // For kernel code model we know that all object resist in the negative half
3897 // of 32bits address space. We may not accept negative offsets, since they may
3898 // be just off and we may accept pretty large positive ones.
3899 if (M == CodeModel::Kernel && Offset >= 0)
3905 /// Determines whether the callee is required to pop its own arguments.
3906 /// Callee pop is necessary to support tail calls.
3907 bool X86::isCalleePop(CallingConv::ID CallingConv,
3908 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3910 if (IsTailCallConvention(CallingConv))
3911 return IsVarArg ? false : TailCallOpt;
3913 switch (CallingConv) {
3916 case CallingConv::X86_StdCall:
3917 case CallingConv::X86_FastCall:
3918 case CallingConv::X86_ThisCall:
3923 /// \brief Return true if the condition is an unsigned comparison operation.
3924 static bool isX86CCUnsigned(unsigned X86CC) {
3926 default: llvm_unreachable("Invalid integer condition!");
3927 case X86::COND_E: return true;
3928 case X86::COND_G: return false;
3929 case X86::COND_GE: return false;
3930 case X86::COND_L: return false;
3931 case X86::COND_LE: return false;
3932 case X86::COND_NE: return true;
3933 case X86::COND_B: return true;
3934 case X86::COND_A: return true;
3935 case X86::COND_BE: return true;
3936 case X86::COND_AE: return true;
3938 llvm_unreachable("covered switch fell through?!");
3941 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3942 /// condition code, returning the condition code and the LHS/RHS of the
3943 /// comparison to make.
3944 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3945 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3947 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3948 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3949 // X > -1 -> X == 0, jump !sign.
3950 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3951 return X86::COND_NS;
3953 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3954 // X < 0 -> X == 0, jump on sign.
3957 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3959 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3960 return X86::COND_LE;
3964 switch (SetCCOpcode) {
3965 default: llvm_unreachable("Invalid integer condition!");
3966 case ISD::SETEQ: return X86::COND_E;
3967 case ISD::SETGT: return X86::COND_G;
3968 case ISD::SETGE: return X86::COND_GE;
3969 case ISD::SETLT: return X86::COND_L;
3970 case ISD::SETLE: return X86::COND_LE;
3971 case ISD::SETNE: return X86::COND_NE;
3972 case ISD::SETULT: return X86::COND_B;
3973 case ISD::SETUGT: return X86::COND_A;
3974 case ISD::SETULE: return X86::COND_BE;
3975 case ISD::SETUGE: return X86::COND_AE;
3979 // First determine if it is required or is profitable to flip the operands.
3981 // If LHS is a foldable load, but RHS is not, flip the condition.
3982 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3983 !ISD::isNON_EXTLoad(RHS.getNode())) {
3984 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3985 std::swap(LHS, RHS);
3988 switch (SetCCOpcode) {
3994 std::swap(LHS, RHS);
3998 // On a floating point condition, the flags are set as follows:
4000 // 0 | 0 | 0 | X > Y
4001 // 0 | 0 | 1 | X < Y
4002 // 1 | 0 | 0 | X == Y
4003 // 1 | 1 | 1 | unordered
4004 switch (SetCCOpcode) {
4005 default: llvm_unreachable("Condcode should be pre-legalized away");
4007 case ISD::SETEQ: return X86::COND_E;
4008 case ISD::SETOLT: // flipped
4010 case ISD::SETGT: return X86::COND_A;
4011 case ISD::SETOLE: // flipped
4013 case ISD::SETGE: return X86::COND_AE;
4014 case ISD::SETUGT: // flipped
4016 case ISD::SETLT: return X86::COND_B;
4017 case ISD::SETUGE: // flipped
4019 case ISD::SETLE: return X86::COND_BE;
4021 case ISD::SETNE: return X86::COND_NE;
4022 case ISD::SETUO: return X86::COND_P;
4023 case ISD::SETO: return X86::COND_NP;
4025 case ISD::SETUNE: return X86::COND_INVALID;
4029 /// Is there a floating point cmov for the specific X86 condition code?
4030 /// Current x86 isa includes the following FP cmov instructions:
4031 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4032 static bool hasFPCMov(unsigned X86CC) {
4048 /// Returns true if the target can instruction select the
4049 /// specified FP immediate natively. If false, the legalizer will
4050 /// materialize the FP immediate as a load from a constant pool.
4051 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4052 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4053 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4059 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4060 ISD::LoadExtType ExtTy,
4062 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4063 // relocation target a movq or addq instruction: don't let the load shrink.
4064 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4065 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4066 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4067 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4071 /// \brief Returns true if it is beneficial to convert a load of a constant
4072 /// to just the constant itself.
4073 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4075 assert(Ty->isIntegerTy());
4077 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4078 if (BitSize == 0 || BitSize > 64)
4083 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4084 unsigned Index) const {
4085 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4088 return (Index == 0 || Index == ResVT.getVectorNumElements());
4091 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4092 // Speculate cttz only if we can directly use TZCNT.
4093 return Subtarget->hasBMI();
4096 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4097 // Speculate ctlz only if we can directly use LZCNT.
4098 return Subtarget->hasLZCNT();
4101 /// Return true if every element in Mask, beginning
4102 /// from position Pos and ending in Pos+Size is undef.
4103 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4104 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4110 /// Return true if Val is undef or if its value falls within the
4111 /// specified range (L, H].
4112 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4113 return (Val < 0) || (Val >= Low && Val < Hi);
4116 /// Val is either less than zero (undef) or equal to the specified value.
4117 static bool isUndefOrEqual(int Val, int CmpVal) {
4118 return (Val < 0 || Val == CmpVal);
4121 /// Return true if every element in Mask, beginning
4122 /// from position Pos and ending in Pos+Size, falls within the specified
4123 /// sequential range (Low, Low+Size]. or is undef.
4124 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4125 unsigned Pos, unsigned Size, int Low) {
4126 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4127 if (!isUndefOrEqual(Mask[i], Low))
4132 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4133 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4134 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4135 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4136 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4139 // The index should be aligned on a vecWidth-bit boundary.
4141 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4143 MVT VT = N->getSimpleValueType(0);
4144 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4145 bool Result = (Index * ElSize) % vecWidth == 0;
4150 /// Return true if the specified INSERT_SUBVECTOR
4151 /// operand specifies a subvector insert that is suitable for input to
4152 /// insertion of 128 or 256-bit subvectors
4153 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4154 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4155 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4157 // The index should be aligned on a vecWidth-bit boundary.
4159 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4161 MVT VT = N->getSimpleValueType(0);
4162 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4163 bool Result = (Index * ElSize) % vecWidth == 0;
4168 bool X86::isVINSERT128Index(SDNode *N) {
4169 return isVINSERTIndex(N, 128);
4172 bool X86::isVINSERT256Index(SDNode *N) {
4173 return isVINSERTIndex(N, 256);
4176 bool X86::isVEXTRACT128Index(SDNode *N) {
4177 return isVEXTRACTIndex(N, 128);
4180 bool X86::isVEXTRACT256Index(SDNode *N) {
4181 return isVEXTRACTIndex(N, 256);
4184 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4185 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4186 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4187 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4190 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4192 MVT VecVT = N->getOperand(0).getSimpleValueType();
4193 MVT ElVT = VecVT.getVectorElementType();
4195 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4196 return Index / NumElemsPerChunk;
4199 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4200 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4201 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4202 llvm_unreachable("Illegal insert subvector for VINSERT");
4205 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4207 MVT VecVT = N->getSimpleValueType(0);
4208 MVT ElVT = VecVT.getVectorElementType();
4210 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4211 return Index / NumElemsPerChunk;
4214 /// Return the appropriate immediate to extract the specified
4215 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4216 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4217 return getExtractVEXTRACTImmediate(N, 128);
4220 /// Return the appropriate immediate to extract the specified
4221 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4222 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4223 return getExtractVEXTRACTImmediate(N, 256);
4226 /// Return the appropriate immediate to insert at the specified
4227 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4228 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4229 return getInsertVINSERTImmediate(N, 128);
4232 /// Return the appropriate immediate to insert at the specified
4233 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4234 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4235 return getInsertVINSERTImmediate(N, 256);
4238 /// Returns true if V is a constant integer zero.
4239 static bool isZero(SDValue V) {
4240 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4241 return C && C->isNullValue();
4244 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4245 bool X86::isZeroNode(SDValue Elt) {
4248 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4249 return CFP->getValueAPF().isPosZero();
4253 /// Returns a vector of specified type with all zero elements.
4254 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4255 SelectionDAG &DAG, SDLoc dl) {
4256 assert(VT.isVector() && "Expected a vector type");
4258 // Always build SSE zero vectors as <4 x i32> bitcasted
4259 // to their dest type. This ensures they get CSE'd.
4261 if (VT.is128BitVector()) { // SSE
4262 if (Subtarget->hasSSE2()) { // SSE2
4263 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4264 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4266 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4267 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4269 } else if (VT.is256BitVector()) { // AVX
4270 if (Subtarget->hasInt256()) { // AVX2
4271 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4272 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4273 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4275 // 256-bit logic and arithmetic instructions in AVX are all
4276 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4277 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4278 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4279 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4281 } else if (VT.is512BitVector()) { // AVX-512
4282 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4283 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4284 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4285 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4286 } else if (VT.getScalarType() == MVT::i1) {
4288 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4289 && "Unexpected vector type");
4290 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4291 && "Unexpected vector type");
4292 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4293 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4294 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4296 llvm_unreachable("Unexpected vector type");
4298 return DAG.getBitcast(VT, Vec);
4301 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4302 SelectionDAG &DAG, SDLoc dl,
4303 unsigned vectorWidth) {
4304 assert((vectorWidth == 128 || vectorWidth == 256) &&
4305 "Unsupported vector width");
4306 EVT VT = Vec.getValueType();
4307 EVT ElVT = VT.getVectorElementType();
4308 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4309 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4310 VT.getVectorNumElements()/Factor);
4312 // Extract from UNDEF is UNDEF.
4313 if (Vec.getOpcode() == ISD::UNDEF)
4314 return DAG.getUNDEF(ResultVT);
4316 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4317 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4319 // This is the index of the first element of the vectorWidth-bit chunk
4321 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4324 // If the input is a buildvector just emit a smaller one.
4325 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4326 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4327 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4330 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4331 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4334 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4335 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4336 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4337 /// instructions or a simple subregister reference. Idx is an index in the
4338 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4339 /// lowering EXTRACT_VECTOR_ELT operations easier.
4340 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4341 SelectionDAG &DAG, SDLoc dl) {
4342 assert((Vec.getValueType().is256BitVector() ||
4343 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4344 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4347 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4348 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4349 SelectionDAG &DAG, SDLoc dl) {
4350 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4351 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4354 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4355 unsigned IdxVal, SelectionDAG &DAG,
4356 SDLoc dl, unsigned vectorWidth) {
4357 assert((vectorWidth == 128 || vectorWidth == 256) &&
4358 "Unsupported vector width");
4359 // Inserting UNDEF is Result
4360 if (Vec.getOpcode() == ISD::UNDEF)
4362 EVT VT = Vec.getValueType();
4363 EVT ElVT = VT.getVectorElementType();
4364 EVT ResultVT = Result.getValueType();
4366 // Insert the relevant vectorWidth bits.
4367 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4369 // This is the index of the first element of the vectorWidth-bit chunk
4371 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4374 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4375 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4378 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4379 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4380 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4381 /// simple superregister reference. Idx is an index in the 128 bits
4382 /// we want. It need not be aligned to a 128-bit boundary. That makes
4383 /// lowering INSERT_VECTOR_ELT operations easier.
4384 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4385 SelectionDAG &DAG, SDLoc dl) {
4386 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4388 // For insertion into the zero index (low half) of a 256-bit vector, it is
4389 // more efficient to generate a blend with immediate instead of an insert*128.
4390 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4391 // extend the subvector to the size of the result vector. Make sure that
4392 // we are not recursing on that node by checking for undef here.
4393 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4394 Result.getOpcode() != ISD::UNDEF) {
4395 EVT ResultVT = Result.getValueType();
4396 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4397 SDValue Undef = DAG.getUNDEF(ResultVT);
4398 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4401 // The blend instruction, and therefore its mask, depend on the data type.
4402 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4403 if (ScalarType.isFloatingPoint()) {
4404 // Choose either vblendps (float) or vblendpd (double).
4405 unsigned ScalarSize = ScalarType.getSizeInBits();
4406 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4407 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4408 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4409 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4412 const X86Subtarget &Subtarget =
4413 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4415 // AVX2 is needed for 256-bit integer blend support.
4416 // Integers must be cast to 32-bit because there is only vpblendd;
4417 // vpblendw can't be used for this because it has a handicapped mask.
4419 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4420 // is still more efficient than using the wrong domain vinsertf128 that
4421 // will be created by InsertSubVector().
4422 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4424 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4425 Vec256 = DAG.getBitcast(CastVT, Vec256);
4426 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4427 return DAG.getBitcast(ResultVT, Vec256);
4430 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4433 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4434 SelectionDAG &DAG, SDLoc dl) {
4435 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4436 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4439 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4440 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4441 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4442 /// large BUILD_VECTORS.
4443 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4444 unsigned NumElems, SelectionDAG &DAG,
4446 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4447 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4450 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4451 unsigned NumElems, SelectionDAG &DAG,
4453 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4454 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4457 /// Returns a vector of specified type with all bits set.
4458 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4459 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4460 /// Then bitcast to their original type, ensuring they get CSE'd.
4461 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4462 SelectionDAG &DAG, SDLoc dl) {
4463 assert(VT.isVector() && "Expected a vector type");
4465 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4467 if (VT.is512BitVector()) {
4468 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4469 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4470 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4471 } else if (VT.is256BitVector()) {
4472 if (Subtarget->hasInt256()) { // AVX2
4473 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4474 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4476 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4477 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4479 } else if (VT.is128BitVector()) {
4480 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4482 llvm_unreachable("Unexpected vector type");
4484 return DAG.getBitcast(VT, Vec);
4487 /// Returns a vector_shuffle node for an unpackl operation.
4488 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4490 unsigned NumElems = VT.getVectorNumElements();
4491 SmallVector<int, 8> Mask;
4492 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4494 Mask.push_back(i + NumElems);
4496 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4499 /// Returns a vector_shuffle node for an unpackh operation.
4500 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4502 unsigned NumElems = VT.getVectorNumElements();
4503 SmallVector<int, 8> Mask;
4504 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4505 Mask.push_back(i + Half);
4506 Mask.push_back(i + NumElems + Half);
4508 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4511 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4512 /// This produces a shuffle where the low element of V2 is swizzled into the
4513 /// zero/undef vector, landing at element Idx.
4514 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4515 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4517 const X86Subtarget *Subtarget,
4518 SelectionDAG &DAG) {
4519 MVT VT = V2.getSimpleValueType();
4521 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4522 unsigned NumElems = VT.getVectorNumElements();
4523 SmallVector<int, 16> MaskVec;
4524 for (unsigned i = 0; i != NumElems; ++i)
4525 // If this is the insertion idx, put the low elt of V2 here.
4526 MaskVec.push_back(i == Idx ? NumElems : i);
4527 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4530 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4531 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4532 /// uses one source. Note that this will set IsUnary for shuffles which use a
4533 /// single input multiple times, and in those cases it will
4534 /// adjust the mask to only have indices within that single input.
4535 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4536 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4537 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4538 unsigned NumElems = VT.getVectorNumElements();
4542 bool IsFakeUnary = false;
4543 switch(N->getOpcode()) {
4544 case X86ISD::BLENDI:
4545 ImmN = N->getOperand(N->getNumOperands()-1);
4546 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4549 ImmN = N->getOperand(N->getNumOperands()-1);
4550 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4551 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4553 case X86ISD::UNPCKH:
4554 DecodeUNPCKHMask(VT, Mask);
4555 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4557 case X86ISD::UNPCKL:
4558 DecodeUNPCKLMask(VT, Mask);
4559 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4561 case X86ISD::MOVHLPS:
4562 DecodeMOVHLPSMask(NumElems, Mask);
4563 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4565 case X86ISD::MOVLHPS:
4566 DecodeMOVLHPSMask(NumElems, Mask);
4567 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4569 case X86ISD::PALIGNR:
4570 ImmN = N->getOperand(N->getNumOperands()-1);
4571 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4573 case X86ISD::PSHUFD:
4574 case X86ISD::VPERMILPI:
4575 ImmN = N->getOperand(N->getNumOperands()-1);
4576 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4579 case X86ISD::PSHUFHW:
4580 ImmN = N->getOperand(N->getNumOperands()-1);
4581 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4584 case X86ISD::PSHUFLW:
4585 ImmN = N->getOperand(N->getNumOperands()-1);
4586 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4589 case X86ISD::PSHUFB: {
4591 SDValue MaskNode = N->getOperand(1);
4592 while (MaskNode->getOpcode() == ISD::BITCAST)
4593 MaskNode = MaskNode->getOperand(0);
4595 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4596 // If we have a build-vector, then things are easy.
4597 EVT VT = MaskNode.getValueType();
4598 assert(VT.isVector() &&
4599 "Can't produce a non-vector with a build_vector!");
4600 if (!VT.isInteger())
4603 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4605 SmallVector<uint64_t, 32> RawMask;
4606 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4607 SDValue Op = MaskNode->getOperand(i);
4608 if (Op->getOpcode() == ISD::UNDEF) {
4609 RawMask.push_back((uint64_t)SM_SentinelUndef);
4612 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4615 APInt MaskElement = CN->getAPIntValue();
4617 // We now have to decode the element which could be any integer size and
4618 // extract each byte of it.
4619 for (int j = 0; j < NumBytesPerElement; ++j) {
4620 // Note that this is x86 and so always little endian: the low byte is
4621 // the first byte of the mask.
4622 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4623 MaskElement = MaskElement.lshr(8);
4626 DecodePSHUFBMask(RawMask, Mask);
4630 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4634 SDValue Ptr = MaskLoad->getBasePtr();
4635 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4636 Ptr->getOpcode() == X86ISD::WrapperRIP)
4637 Ptr = Ptr->getOperand(0);
4639 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4640 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4643 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4644 DecodePSHUFBMask(C, Mask);
4652 case X86ISD::VPERMI:
4653 ImmN = N->getOperand(N->getNumOperands()-1);
4654 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4659 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4661 case X86ISD::VPERM2X128:
4662 ImmN = N->getOperand(N->getNumOperands()-1);
4663 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4664 if (Mask.empty()) return false;
4665 // Mask only contains negative index if an element is zero.
4666 if (std::any_of(Mask.begin(), Mask.end(),
4667 [](int M){ return M == SM_SentinelZero; }))
4670 case X86ISD::MOVSLDUP:
4671 DecodeMOVSLDUPMask(VT, Mask);
4674 case X86ISD::MOVSHDUP:
4675 DecodeMOVSHDUPMask(VT, Mask);
4678 case X86ISD::MOVDDUP:
4679 DecodeMOVDDUPMask(VT, Mask);
4682 case X86ISD::MOVLHPD:
4683 case X86ISD::MOVLPD:
4684 case X86ISD::MOVLPS:
4685 // Not yet implemented
4687 case X86ISD::VPERMV: {
4689 SDValue MaskNode = N->getOperand(0);
4690 while (MaskNode->getOpcode() == ISD::BITCAST)
4691 MaskNode = MaskNode->getOperand(0);
4693 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4694 SmallVector<uint64_t, 32> RawMask;
4695 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4696 // If we have a build-vector, then things are easy.
4697 assert(MaskNode.getValueType().isInteger() &&
4698 MaskNode.getValueType().getVectorNumElements() ==
4699 VT.getVectorNumElements());
4701 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4702 SDValue Op = MaskNode->getOperand(i);
4703 if (Op->getOpcode() == ISD::UNDEF)
4704 RawMask.push_back((uint64_t)SM_SentinelUndef);
4705 else if (isa<ConstantSDNode>(Op)) {
4706 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4707 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4711 DecodeVPERMVMask(RawMask, Mask);
4714 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4715 unsigned NumEltsInMask = MaskNode->getNumOperands();
4716 MaskNode = MaskNode->getOperand(0);
4717 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4719 APInt MaskEltValue = CN->getAPIntValue();
4720 for (unsigned i = 0; i < NumEltsInMask; ++i)
4721 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4722 DecodeVPERMVMask(RawMask, Mask);
4725 // It may be a scalar load
4728 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4732 SDValue Ptr = MaskLoad->getBasePtr();
4733 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4734 Ptr->getOpcode() == X86ISD::WrapperRIP)
4735 Ptr = Ptr->getOperand(0);
4737 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4738 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4741 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4743 DecodeVPERMVMask(C, VT, Mask);
4750 case X86ISD::VPERMV3: {
4752 SDValue MaskNode = N->getOperand(1);
4753 while (MaskNode->getOpcode() == ISD::BITCAST)
4754 MaskNode = MaskNode->getOperand(1);
4756 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4757 // If we have a build-vector, then things are easy.
4758 assert(MaskNode.getValueType().isInteger() &&
4759 MaskNode.getValueType().getVectorNumElements() ==
4760 VT.getVectorNumElements());
4762 SmallVector<uint64_t, 32> RawMask;
4763 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4765 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4766 SDValue Op = MaskNode->getOperand(i);
4767 if (Op->getOpcode() == ISD::UNDEF)
4768 RawMask.push_back((uint64_t)SM_SentinelUndef);
4770 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4773 APInt MaskElement = CN->getAPIntValue();
4774 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4777 DecodeVPERMV3Mask(RawMask, Mask);
4781 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4785 SDValue Ptr = MaskLoad->getBasePtr();
4786 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4787 Ptr->getOpcode() == X86ISD::WrapperRIP)
4788 Ptr = Ptr->getOperand(0);
4790 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4791 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4794 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4796 DecodeVPERMV3Mask(C, VT, Mask);
4803 default: llvm_unreachable("unknown target shuffle node");
4806 // If we have a fake unary shuffle, the shuffle mask is spread across two
4807 // inputs that are actually the same node. Re-map the mask to always point
4808 // into the first input.
4811 if (M >= (int)Mask.size())
4817 /// Returns the scalar element that will make up the ith
4818 /// element of the result of the vector shuffle.
4819 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4822 return SDValue(); // Limit search depth.
4824 SDValue V = SDValue(N, 0);
4825 EVT VT = V.getValueType();
4826 unsigned Opcode = V.getOpcode();
4828 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4829 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4830 int Elt = SV->getMaskElt(Index);
4833 return DAG.getUNDEF(VT.getVectorElementType());
4835 unsigned NumElems = VT.getVectorNumElements();
4836 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4837 : SV->getOperand(1);
4838 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4841 // Recurse into target specific vector shuffles to find scalars.
4842 if (isTargetShuffle(Opcode)) {
4843 MVT ShufVT = V.getSimpleValueType();
4844 unsigned NumElems = ShufVT.getVectorNumElements();
4845 SmallVector<int, 16> ShuffleMask;
4848 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4851 int Elt = ShuffleMask[Index];
4853 return DAG.getUNDEF(ShufVT.getVectorElementType());
4855 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4857 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4861 // Actual nodes that may contain scalar elements
4862 if (Opcode == ISD::BITCAST) {
4863 V = V.getOperand(0);
4864 EVT SrcVT = V.getValueType();
4865 unsigned NumElems = VT.getVectorNumElements();
4867 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4871 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4872 return (Index == 0) ? V.getOperand(0)
4873 : DAG.getUNDEF(VT.getVectorElementType());
4875 if (V.getOpcode() == ISD::BUILD_VECTOR)
4876 return V.getOperand(Index);
4881 /// Custom lower build_vector of v16i8.
4882 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4883 unsigned NumNonZero, unsigned NumZero,
4885 const X86Subtarget* Subtarget,
4886 const TargetLowering &TLI) {
4894 // SSE4.1 - use PINSRB to insert each byte directly.
4895 if (Subtarget->hasSSE41()) {
4896 for (unsigned i = 0; i < 16; ++i) {
4897 bool isNonZero = (NonZeros & (1 << i)) != 0;
4901 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4903 V = DAG.getUNDEF(MVT::v16i8);
4906 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4907 MVT::v16i8, V, Op.getOperand(i),
4908 DAG.getIntPtrConstant(i, dl));
4915 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4916 for (unsigned i = 0; i < 16; ++i) {
4917 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4918 if (ThisIsNonZero && First) {
4920 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4922 V = DAG.getUNDEF(MVT::v8i16);
4927 SDValue ThisElt, LastElt;
4928 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4929 if (LastIsNonZero) {
4930 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4931 MVT::i16, Op.getOperand(i-1));
4933 if (ThisIsNonZero) {
4934 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4935 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4936 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4938 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4942 if (ThisElt.getNode())
4943 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4944 DAG.getIntPtrConstant(i/2, dl));
4948 return DAG.getBitcast(MVT::v16i8, V);
4951 /// Custom lower build_vector of v8i16.
4952 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4953 unsigned NumNonZero, unsigned NumZero,
4955 const X86Subtarget* Subtarget,
4956 const TargetLowering &TLI) {
4963 for (unsigned i = 0; i < 8; ++i) {
4964 bool isNonZero = (NonZeros & (1 << i)) != 0;
4968 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4970 V = DAG.getUNDEF(MVT::v8i16);
4973 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4974 MVT::v8i16, V, Op.getOperand(i),
4975 DAG.getIntPtrConstant(i, dl));
4982 /// Custom lower build_vector of v4i32 or v4f32.
4983 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4984 const X86Subtarget *Subtarget,
4985 const TargetLowering &TLI) {
4986 // Find all zeroable elements.
4987 std::bitset<4> Zeroable;
4988 for (int i=0; i < 4; ++i) {
4989 SDValue Elt = Op->getOperand(i);
4990 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4992 assert(Zeroable.size() - Zeroable.count() > 1 &&
4993 "We expect at least two non-zero elements!");
4995 // We only know how to deal with build_vector nodes where elements are either
4996 // zeroable or extract_vector_elt with constant index.
4997 SDValue FirstNonZero;
4998 unsigned FirstNonZeroIdx;
4999 for (unsigned i=0; i < 4; ++i) {
5002 SDValue Elt = Op->getOperand(i);
5003 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5004 !isa<ConstantSDNode>(Elt.getOperand(1)))
5006 // Make sure that this node is extracting from a 128-bit vector.
5007 MVT VT = Elt.getOperand(0).getSimpleValueType();
5008 if (!VT.is128BitVector())
5010 if (!FirstNonZero.getNode()) {
5012 FirstNonZeroIdx = i;
5016 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5017 SDValue V1 = FirstNonZero.getOperand(0);
5018 MVT VT = V1.getSimpleValueType();
5020 // See if this build_vector can be lowered as a blend with zero.
5022 unsigned EltMaskIdx, EltIdx;
5024 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5025 if (Zeroable[EltIdx]) {
5026 // The zero vector will be on the right hand side.
5027 Mask[EltIdx] = EltIdx+4;
5031 Elt = Op->getOperand(EltIdx);
5032 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5033 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5034 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5036 Mask[EltIdx] = EltIdx;
5040 // Let the shuffle legalizer deal with blend operations.
5041 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5042 if (V1.getSimpleValueType() != VT)
5043 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5044 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5047 // See if we can lower this build_vector to a INSERTPS.
5048 if (!Subtarget->hasSSE41())
5051 SDValue V2 = Elt.getOperand(0);
5052 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5055 bool CanFold = true;
5056 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5060 SDValue Current = Op->getOperand(i);
5061 SDValue SrcVector = Current->getOperand(0);
5064 CanFold = SrcVector == V1 &&
5065 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5071 assert(V1.getNode() && "Expected at least two non-zero elements!");
5072 if (V1.getSimpleValueType() != MVT::v4f32)
5073 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5074 if (V2.getSimpleValueType() != MVT::v4f32)
5075 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5077 // Ok, we can emit an INSERTPS instruction.
5078 unsigned ZMask = Zeroable.to_ulong();
5080 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5081 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5083 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5084 DAG.getIntPtrConstant(InsertPSMask, DL));
5085 return DAG.getBitcast(VT, Result);
5088 /// Return a vector logical shift node.
5089 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5090 unsigned NumBits, SelectionDAG &DAG,
5091 const TargetLowering &TLI, SDLoc dl) {
5092 assert(VT.is128BitVector() && "Unknown type for VShift");
5093 MVT ShVT = MVT::v2i64;
5094 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5095 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5096 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5097 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5098 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5099 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5103 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5105 // Check if the scalar load can be widened into a vector load. And if
5106 // the address is "base + cst" see if the cst can be "absorbed" into
5107 // the shuffle mask.
5108 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5109 SDValue Ptr = LD->getBasePtr();
5110 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5112 EVT PVT = LD->getValueType(0);
5113 if (PVT != MVT::i32 && PVT != MVT::f32)
5118 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5119 FI = FINode->getIndex();
5121 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5122 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5123 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5124 Offset = Ptr.getConstantOperandVal(1);
5125 Ptr = Ptr.getOperand(0);
5130 // FIXME: 256-bit vector instructions don't require a strict alignment,
5131 // improve this code to support it better.
5132 unsigned RequiredAlign = VT.getSizeInBits()/8;
5133 SDValue Chain = LD->getChain();
5134 // Make sure the stack object alignment is at least 16 or 32.
5135 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5136 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5137 if (MFI->isFixedObjectIndex(FI)) {
5138 // Can't change the alignment. FIXME: It's possible to compute
5139 // the exact stack offset and reference FI + adjust offset instead.
5140 // If someone *really* cares about this. That's the way to implement it.
5143 MFI->setObjectAlignment(FI, RequiredAlign);
5147 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5148 // Ptr + (Offset & ~15).
5151 if ((Offset % RequiredAlign) & 3)
5153 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5156 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5157 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5160 int EltNo = (Offset - StartOffset) >> 2;
5161 unsigned NumElems = VT.getVectorNumElements();
5163 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5164 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5165 LD->getPointerInfo().getWithOffset(StartOffset),
5166 false, false, false, 0);
5168 SmallVector<int, 8> Mask(NumElems, EltNo);
5170 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5176 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5177 /// elements can be replaced by a single large load which has the same value as
5178 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5180 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5182 /// FIXME: we'd also like to handle the case where the last elements are zero
5183 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5184 /// There's even a handy isZeroNode for that purpose.
5185 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5186 SDLoc &DL, SelectionDAG &DAG,
5187 bool isAfterLegalize) {
5188 unsigned NumElems = Elts.size();
5190 LoadSDNode *LDBase = nullptr;
5191 unsigned LastLoadedElt = -1U;
5193 // For each element in the initializer, see if we've found a load or an undef.
5194 // If we don't find an initial load element, or later load elements are
5195 // non-consecutive, bail out.
5196 for (unsigned i = 0; i < NumElems; ++i) {
5197 SDValue Elt = Elts[i];
5198 // Look through a bitcast.
5199 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5200 Elt = Elt.getOperand(0);
5201 if (!Elt.getNode() ||
5202 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5205 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5207 LDBase = cast<LoadSDNode>(Elt.getNode());
5211 if (Elt.getOpcode() == ISD::UNDEF)
5214 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5215 EVT LdVT = Elt.getValueType();
5216 // Each loaded element must be the correct fractional portion of the
5217 // requested vector load.
5218 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5220 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5225 // If we have found an entire vector of loads and undefs, then return a large
5226 // load of the entire vector width starting at the base pointer. If we found
5227 // consecutive loads for the low half, generate a vzext_load node.
5228 if (LastLoadedElt == NumElems - 1) {
5229 assert(LDBase && "Did not find base load for merging consecutive loads");
5230 EVT EltVT = LDBase->getValueType(0);
5231 // Ensure that the input vector size for the merged loads matches the
5232 // cumulative size of the input elements.
5233 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5236 if (isAfterLegalize &&
5237 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5240 SDValue NewLd = SDValue();
5242 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5243 LDBase->getPointerInfo(), LDBase->isVolatile(),
5244 LDBase->isNonTemporal(), LDBase->isInvariant(),
5245 LDBase->getAlignment());
5247 if (LDBase->hasAnyUseOfValue(1)) {
5248 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5250 SDValue(NewLd.getNode(), 1));
5251 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5252 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5253 SDValue(NewLd.getNode(), 1));
5259 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5260 //of a v4i32 / v4f32. It's probably worth generalizing.
5261 EVT EltVT = VT.getVectorElementType();
5262 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5263 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5264 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5265 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5267 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5268 LDBase->getPointerInfo(),
5269 LDBase->getAlignment(),
5270 false/*isVolatile*/, true/*ReadMem*/,
5273 // Make sure the newly-created LOAD is in the same position as LDBase in
5274 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5275 // update uses of LDBase's output chain to use the TokenFactor.
5276 if (LDBase->hasAnyUseOfValue(1)) {
5277 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5278 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5279 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5280 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5281 SDValue(ResNode.getNode(), 1));
5284 return DAG.getBitcast(VT, ResNode);
5289 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5290 /// to generate a splat value for the following cases:
5291 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5292 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5293 /// a scalar load, or a constant.
5294 /// The VBROADCAST node is returned when a pattern is found,
5295 /// or SDValue() otherwise.
5296 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5297 SelectionDAG &DAG) {
5298 // VBROADCAST requires AVX.
5299 // TODO: Splats could be generated for non-AVX CPUs using SSE
5300 // instructions, but there's less potential gain for only 128-bit vectors.
5301 if (!Subtarget->hasAVX())
5304 MVT VT = Op.getSimpleValueType();
5307 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5308 "Unsupported vector type for broadcast.");
5313 switch (Op.getOpcode()) {
5315 // Unknown pattern found.
5318 case ISD::BUILD_VECTOR: {
5319 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5320 BitVector UndefElements;
5321 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5323 // We need a splat of a single value to use broadcast, and it doesn't
5324 // make any sense if the value is only in one element of the vector.
5325 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5329 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5330 Ld.getOpcode() == ISD::ConstantFP);
5332 // Make sure that all of the users of a non-constant load are from the
5333 // BUILD_VECTOR node.
5334 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5339 case ISD::VECTOR_SHUFFLE: {
5340 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5342 // Shuffles must have a splat mask where the first element is
5344 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5347 SDValue Sc = Op.getOperand(0);
5348 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5349 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5351 if (!Subtarget->hasInt256())
5354 // Use the register form of the broadcast instruction available on AVX2.
5355 if (VT.getSizeInBits() >= 256)
5356 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5357 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5360 Ld = Sc.getOperand(0);
5361 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5362 Ld.getOpcode() == ISD::ConstantFP);
5364 // The scalar_to_vector node and the suspected
5365 // load node must have exactly one user.
5366 // Constants may have multiple users.
5368 // AVX-512 has register version of the broadcast
5369 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5370 Ld.getValueType().getSizeInBits() >= 32;
5371 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5378 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5379 bool IsGE256 = (VT.getSizeInBits() >= 256);
5381 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5382 // instruction to save 8 or more bytes of constant pool data.
5383 // TODO: If multiple splats are generated to load the same constant,
5384 // it may be detrimental to overall size. There needs to be a way to detect
5385 // that condition to know if this is truly a size win.
5386 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5388 // Handle broadcasting a single constant scalar from the constant pool
5390 // On Sandybridge (no AVX2), it is still better to load a constant vector
5391 // from the constant pool and not to broadcast it from a scalar.
5392 // But override that restriction when optimizing for size.
5393 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5394 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5395 EVT CVT = Ld.getValueType();
5396 assert(!CVT.isVector() && "Must not broadcast a vector type");
5398 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5399 // For size optimization, also splat v2f64 and v2i64, and for size opt
5400 // with AVX2, also splat i8 and i16.
5401 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5402 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5403 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5404 const Constant *C = nullptr;
5405 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5406 C = CI->getConstantIntValue();
5407 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5408 C = CF->getConstantFPValue();
5410 assert(C && "Invalid constant type");
5412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5414 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5415 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5417 CVT, dl, DAG.getEntryNode(), CP,
5418 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5419 false, false, Alignment);
5421 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5425 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5427 // Handle AVX2 in-register broadcasts.
5428 if (!IsLoad && Subtarget->hasInt256() &&
5429 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5430 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5432 // The scalar source must be a normal load.
5436 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5437 (Subtarget->hasVLX() && ScalarSize == 64))
5438 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5440 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5441 // double since there is no vbroadcastsd xmm
5442 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5443 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5444 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5447 // Unsupported broadcast.
5451 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5452 /// underlying vector and index.
5454 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5456 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5458 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5459 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5462 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5464 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5466 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5467 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5470 // In this case the vector is the extract_subvector expression and the index
5471 // is 2, as specified by the shuffle.
5472 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5473 SDValue ShuffleVec = SVOp->getOperand(0);
5474 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5475 assert(ShuffleVecVT.getVectorElementType() ==
5476 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5478 int ShuffleIdx = SVOp->getMaskElt(Idx);
5479 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5480 ExtractedFromVec = ShuffleVec;
5486 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5487 MVT VT = Op.getSimpleValueType();
5489 // Skip if insert_vec_elt is not supported.
5490 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5491 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5495 unsigned NumElems = Op.getNumOperands();
5499 SmallVector<unsigned, 4> InsertIndices;
5500 SmallVector<int, 8> Mask(NumElems, -1);
5502 for (unsigned i = 0; i != NumElems; ++i) {
5503 unsigned Opc = Op.getOperand(i).getOpcode();
5505 if (Opc == ISD::UNDEF)
5508 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5509 // Quit if more than 1 elements need inserting.
5510 if (InsertIndices.size() > 1)
5513 InsertIndices.push_back(i);
5517 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5518 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5519 // Quit if non-constant index.
5520 if (!isa<ConstantSDNode>(ExtIdx))
5522 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5524 // Quit if extracted from vector of different type.
5525 if (ExtractedFromVec.getValueType() != VT)
5528 if (!VecIn1.getNode())
5529 VecIn1 = ExtractedFromVec;
5530 else if (VecIn1 != ExtractedFromVec) {
5531 if (!VecIn2.getNode())
5532 VecIn2 = ExtractedFromVec;
5533 else if (VecIn2 != ExtractedFromVec)
5534 // Quit if more than 2 vectors to shuffle
5538 if (ExtractedFromVec == VecIn1)
5540 else if (ExtractedFromVec == VecIn2)
5541 Mask[i] = Idx + NumElems;
5544 if (!VecIn1.getNode())
5547 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5548 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5549 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5550 unsigned Idx = InsertIndices[i];
5551 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5552 DAG.getIntPtrConstant(Idx, DL));
5558 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5559 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5560 Op.getScalarValueSizeInBits() == 1 &&
5561 "Can not convert non-constant vector");
5562 uint64_t Immediate = 0;
5563 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5564 SDValue In = Op.getOperand(idx);
5565 if (In.getOpcode() != ISD::UNDEF)
5566 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5570 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5571 return DAG.getConstant(Immediate, dl, VT);
5573 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5575 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5577 MVT VT = Op.getSimpleValueType();
5578 assert((VT.getVectorElementType() == MVT::i1) &&
5579 "Unexpected type in LowerBUILD_VECTORvXi1!");
5582 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5583 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5584 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5585 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5588 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5589 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5590 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5591 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5594 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5595 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5596 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5597 return DAG.getBitcast(VT, Imm);
5598 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5599 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5600 DAG.getIntPtrConstant(0, dl));
5603 // Vector has one or more non-const elements
5604 uint64_t Immediate = 0;
5605 SmallVector<unsigned, 16> NonConstIdx;
5606 bool IsSplat = true;
5607 bool HasConstElts = false;
5609 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5610 SDValue In = Op.getOperand(idx);
5611 if (In.getOpcode() == ISD::UNDEF)
5613 if (!isa<ConstantSDNode>(In))
5614 NonConstIdx.push_back(idx);
5616 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5617 HasConstElts = true;
5621 else if (In != Op.getOperand(SplatIdx))
5625 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5627 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5628 DAG.getConstant(1, dl, VT),
5629 DAG.getConstant(0, dl, VT));
5631 // insert elements one by one
5635 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5636 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5638 else if (HasConstElts)
5639 Imm = DAG.getConstant(0, dl, VT);
5641 Imm = DAG.getUNDEF(VT);
5642 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5643 DstVec = DAG.getBitcast(VT, Imm);
5645 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5646 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5647 DAG.getIntPtrConstant(0, dl));
5650 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5651 unsigned InsertIdx = NonConstIdx[i];
5652 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5653 Op.getOperand(InsertIdx),
5654 DAG.getIntPtrConstant(InsertIdx, dl));
5659 /// \brief Return true if \p N implements a horizontal binop and return the
5660 /// operands for the horizontal binop into V0 and V1.
5662 /// This is a helper function of LowerToHorizontalOp().
5663 /// This function checks that the build_vector \p N in input implements a
5664 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5665 /// operation to match.
5666 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5667 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5668 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5671 /// This function only analyzes elements of \p N whose indices are
5672 /// in range [BaseIdx, LastIdx).
5673 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5675 unsigned BaseIdx, unsigned LastIdx,
5676 SDValue &V0, SDValue &V1) {
5677 EVT VT = N->getValueType(0);
5679 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5680 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5681 "Invalid Vector in input!");
5683 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5684 bool CanFold = true;
5685 unsigned ExpectedVExtractIdx = BaseIdx;
5686 unsigned NumElts = LastIdx - BaseIdx;
5687 V0 = DAG.getUNDEF(VT);
5688 V1 = DAG.getUNDEF(VT);
5690 // Check if N implements a horizontal binop.
5691 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5692 SDValue Op = N->getOperand(i + BaseIdx);
5695 if (Op->getOpcode() == ISD::UNDEF) {
5696 // Update the expected vector extract index.
5697 if (i * 2 == NumElts)
5698 ExpectedVExtractIdx = BaseIdx;
5699 ExpectedVExtractIdx += 2;
5703 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5708 SDValue Op0 = Op.getOperand(0);
5709 SDValue Op1 = Op.getOperand(1);
5711 // Try to match the following pattern:
5712 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5713 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5714 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5715 Op0.getOperand(0) == Op1.getOperand(0) &&
5716 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5717 isa<ConstantSDNode>(Op1.getOperand(1)));
5721 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5722 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5724 if (i * 2 < NumElts) {
5725 if (V0.getOpcode() == ISD::UNDEF) {
5726 V0 = Op0.getOperand(0);
5727 if (V0.getValueType() != VT)
5731 if (V1.getOpcode() == ISD::UNDEF) {
5732 V1 = Op0.getOperand(0);
5733 if (V1.getValueType() != VT)
5736 if (i * 2 == NumElts)
5737 ExpectedVExtractIdx = BaseIdx;
5740 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5741 if (I0 == ExpectedVExtractIdx)
5742 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5743 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5744 // Try to match the following dag sequence:
5745 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5746 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5750 ExpectedVExtractIdx += 2;
5756 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5757 /// a concat_vector.
5759 /// This is a helper function of LowerToHorizontalOp().
5760 /// This function expects two 256-bit vectors called V0 and V1.
5761 /// At first, each vector is split into two separate 128-bit vectors.
5762 /// Then, the resulting 128-bit vectors are used to implement two
5763 /// horizontal binary operations.
5765 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5767 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5768 /// the two new horizontal binop.
5769 /// When Mode is set, the first horizontal binop dag node would take as input
5770 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5771 /// horizontal binop dag node would take as input the lower 128-bit of V1
5772 /// and the upper 128-bit of V1.
5774 /// HADD V0_LO, V0_HI
5775 /// HADD V1_LO, V1_HI
5777 /// Otherwise, the first horizontal binop dag node takes as input the lower
5778 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5779 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5781 /// HADD V0_LO, V1_LO
5782 /// HADD V0_HI, V1_HI
5784 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5785 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5786 /// the upper 128-bits of the result.
5787 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5788 SDLoc DL, SelectionDAG &DAG,
5789 unsigned X86Opcode, bool Mode,
5790 bool isUndefLO, bool isUndefHI) {
5791 EVT VT = V0.getValueType();
5792 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5793 "Invalid nodes in input!");
5795 unsigned NumElts = VT.getVectorNumElements();
5796 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5797 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5798 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5799 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5800 EVT NewVT = V0_LO.getValueType();
5802 SDValue LO = DAG.getUNDEF(NewVT);
5803 SDValue HI = DAG.getUNDEF(NewVT);
5806 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5807 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5808 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5809 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5810 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5812 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5813 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5814 V1_LO->getOpcode() != ISD::UNDEF))
5815 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5817 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5818 V1_HI->getOpcode() != ISD::UNDEF))
5819 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5822 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5825 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5827 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5828 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5829 EVT VT = BV->getValueType(0);
5830 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5831 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5835 unsigned NumElts = VT.getVectorNumElements();
5836 SDValue InVec0 = DAG.getUNDEF(VT);
5837 SDValue InVec1 = DAG.getUNDEF(VT);
5839 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5840 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5842 // Odd-numbered elements in the input build vector are obtained from
5843 // adding two integer/float elements.
5844 // Even-numbered elements in the input build vector are obtained from
5845 // subtracting two integer/float elements.
5846 unsigned ExpectedOpcode = ISD::FSUB;
5847 unsigned NextExpectedOpcode = ISD::FADD;
5848 bool AddFound = false;
5849 bool SubFound = false;
5851 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5852 SDValue Op = BV->getOperand(i);
5854 // Skip 'undef' values.
5855 unsigned Opcode = Op.getOpcode();
5856 if (Opcode == ISD::UNDEF) {
5857 std::swap(ExpectedOpcode, NextExpectedOpcode);
5861 // Early exit if we found an unexpected opcode.
5862 if (Opcode != ExpectedOpcode)
5865 SDValue Op0 = Op.getOperand(0);
5866 SDValue Op1 = Op.getOperand(1);
5868 // Try to match the following pattern:
5869 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5870 // Early exit if we cannot match that sequence.
5871 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5872 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5873 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5874 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5875 Op0.getOperand(1) != Op1.getOperand(1))
5878 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5882 // We found a valid add/sub node. Update the information accordingly.
5888 // Update InVec0 and InVec1.
5889 if (InVec0.getOpcode() == ISD::UNDEF) {
5890 InVec0 = Op0.getOperand(0);
5891 if (InVec0.getValueType() != VT)
5894 if (InVec1.getOpcode() == ISD::UNDEF) {
5895 InVec1 = Op1.getOperand(0);
5896 if (InVec1.getValueType() != VT)
5900 // Make sure that operands in input to each add/sub node always
5901 // come from a same pair of vectors.
5902 if (InVec0 != Op0.getOperand(0)) {
5903 if (ExpectedOpcode == ISD::FSUB)
5906 // FADD is commutable. Try to commute the operands
5907 // and then test again.
5908 std::swap(Op0, Op1);
5909 if (InVec0 != Op0.getOperand(0))
5913 if (InVec1 != Op1.getOperand(0))
5916 // Update the pair of expected opcodes.
5917 std::swap(ExpectedOpcode, NextExpectedOpcode);
5920 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5921 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5922 InVec1.getOpcode() != ISD::UNDEF)
5923 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5928 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5929 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5930 const X86Subtarget *Subtarget,
5931 SelectionDAG &DAG) {
5932 EVT VT = BV->getValueType(0);
5933 unsigned NumElts = VT.getVectorNumElements();
5934 unsigned NumUndefsLO = 0;
5935 unsigned NumUndefsHI = 0;
5936 unsigned Half = NumElts/2;
5938 // Count the number of UNDEF operands in the build_vector in input.
5939 for (unsigned i = 0, e = Half; i != e; ++i)
5940 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5943 for (unsigned i = Half, e = NumElts; i != e; ++i)
5944 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5947 // Early exit if this is either a build_vector of all UNDEFs or all the
5948 // operands but one are UNDEF.
5949 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5953 SDValue InVec0, InVec1;
5954 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5955 // Try to match an SSE3 float HADD/HSUB.
5956 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5957 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5959 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5960 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5961 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5962 // Try to match an SSSE3 integer HADD/HSUB.
5963 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5964 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5966 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5967 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5970 if (!Subtarget->hasAVX())
5973 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5974 // Try to match an AVX horizontal add/sub of packed single/double
5975 // precision floating point values from 256-bit vectors.
5976 SDValue InVec2, InVec3;
5977 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5978 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5979 ((InVec0.getOpcode() == ISD::UNDEF ||
5980 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5981 ((InVec1.getOpcode() == ISD::UNDEF ||
5982 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5983 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5985 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5986 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5987 ((InVec0.getOpcode() == ISD::UNDEF ||
5988 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5989 ((InVec1.getOpcode() == ISD::UNDEF ||
5990 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5991 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5992 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5993 // Try to match an AVX2 horizontal add/sub of signed integers.
5994 SDValue InVec2, InVec3;
5996 bool CanFold = true;
5998 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5999 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6000 ((InVec0.getOpcode() == ISD::UNDEF ||
6001 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6002 ((InVec1.getOpcode() == ISD::UNDEF ||
6003 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6004 X86Opcode = X86ISD::HADD;
6005 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6006 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6007 ((InVec0.getOpcode() == ISD::UNDEF ||
6008 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6009 ((InVec1.getOpcode() == ISD::UNDEF ||
6010 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6011 X86Opcode = X86ISD::HSUB;
6016 // Fold this build_vector into a single horizontal add/sub.
6017 // Do this only if the target has AVX2.
6018 if (Subtarget->hasAVX2())
6019 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6021 // Do not try to expand this build_vector into a pair of horizontal
6022 // add/sub if we can emit a pair of scalar add/sub.
6023 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6026 // Convert this build_vector into a pair of horizontal binop followed by
6028 bool isUndefLO = NumUndefsLO == Half;
6029 bool isUndefHI = NumUndefsHI == Half;
6030 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6031 isUndefLO, isUndefHI);
6035 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6036 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6038 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6039 X86Opcode = X86ISD::HADD;
6040 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6041 X86Opcode = X86ISD::HSUB;
6042 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6043 X86Opcode = X86ISD::FHADD;
6044 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6045 X86Opcode = X86ISD::FHSUB;
6049 // Don't try to expand this build_vector into a pair of horizontal add/sub
6050 // if we can simply emit a pair of scalar add/sub.
6051 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6054 // Convert this build_vector into two horizontal add/sub followed by
6056 bool isUndefLO = NumUndefsLO == Half;
6057 bool isUndefHI = NumUndefsHI == Half;
6058 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6059 isUndefLO, isUndefHI);
6066 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6069 MVT VT = Op.getSimpleValueType();
6070 MVT ExtVT = VT.getVectorElementType();
6071 unsigned NumElems = Op.getNumOperands();
6073 // Generate vectors for predicate vectors.
6074 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6075 return LowerBUILD_VECTORvXi1(Op, DAG);
6077 // Vectors containing all zeros can be matched by pxor and xorps later
6078 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6079 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6080 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6081 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6084 return getZeroVector(VT, Subtarget, DAG, dl);
6087 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6088 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6089 // vpcmpeqd on 256-bit vectors.
6090 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6091 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6094 if (!VT.is512BitVector())
6095 return getOnesVector(VT, Subtarget, DAG, dl);
6098 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6099 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6101 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6102 return HorizontalOp;
6103 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6106 unsigned EVTBits = ExtVT.getSizeInBits();
6108 unsigned NumZero = 0;
6109 unsigned NumNonZero = 0;
6110 unsigned NonZeros = 0;
6111 bool IsAllConstants = true;
6112 SmallSet<SDValue, 8> Values;
6113 for (unsigned i = 0; i < NumElems; ++i) {
6114 SDValue Elt = Op.getOperand(i);
6115 if (Elt.getOpcode() == ISD::UNDEF)
6118 if (Elt.getOpcode() != ISD::Constant &&
6119 Elt.getOpcode() != ISD::ConstantFP)
6120 IsAllConstants = false;
6121 if (X86::isZeroNode(Elt))
6124 NonZeros |= (1 << i);
6129 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6130 if (NumNonZero == 0)
6131 return DAG.getUNDEF(VT);
6133 // Special case for single non-zero, non-undef, element.
6134 if (NumNonZero == 1) {
6135 unsigned Idx = countTrailingZeros(NonZeros);
6136 SDValue Item = Op.getOperand(Idx);
6138 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6139 // the value are obviously zero, truncate the value to i32 and do the
6140 // insertion that way. Only do this if the value is non-constant or if the
6141 // value is a constant being inserted into element 0. It is cheaper to do
6142 // a constant pool load than it is to do a movd + shuffle.
6143 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6144 (!IsAllConstants || Idx == 0)) {
6145 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6147 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6148 EVT VecVT = MVT::v4i32;
6150 // Truncate the value (which may itself be a constant) to i32, and
6151 // convert it to a vector with movd (S2V+shuffle to zero extend).
6152 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6153 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6154 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6155 Item, Idx * 2, true, Subtarget, DAG));
6159 // If we have a constant or non-constant insertion into the low element of
6160 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6161 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6162 // depending on what the source datatype is.
6165 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6167 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6168 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6169 if (VT.is512BitVector()) {
6170 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6171 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6172 Item, DAG.getIntPtrConstant(0, dl));
6174 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6175 "Expected an SSE value type!");
6176 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6177 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6178 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6181 // We can't directly insert an i8 or i16 into a vector, so zero extend
6183 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6184 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6185 if (VT.is256BitVector()) {
6186 if (Subtarget->hasAVX()) {
6187 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6188 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6190 // Without AVX, we need to extend to a 128-bit vector and then
6191 // insert into the 256-bit vector.
6192 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6193 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6194 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6197 assert(VT.is128BitVector() && "Expected an SSE value type!");
6198 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6199 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6201 return DAG.getBitcast(VT, Item);
6205 // Is it a vector logical left shift?
6206 if (NumElems == 2 && Idx == 1 &&
6207 X86::isZeroNode(Op.getOperand(0)) &&
6208 !X86::isZeroNode(Op.getOperand(1))) {
6209 unsigned NumBits = VT.getSizeInBits();
6210 return getVShift(true, VT,
6211 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6212 VT, Op.getOperand(1)),
6213 NumBits/2, DAG, *this, dl);
6216 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6219 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6220 // is a non-constant being inserted into an element other than the low one,
6221 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6222 // movd/movss) to move this into the low element, then shuffle it into
6224 if (EVTBits == 32) {
6225 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6226 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6230 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6231 if (Values.size() == 1) {
6232 if (EVTBits == 32) {
6233 // Instead of a shuffle like this:
6234 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6235 // Check if it's possible to issue this instead.
6236 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6237 unsigned Idx = countTrailingZeros(NonZeros);
6238 SDValue Item = Op.getOperand(Idx);
6239 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6240 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6245 // A vector full of immediates; various special cases are already
6246 // handled, so this is best done with a single constant-pool load.
6250 // For AVX-length vectors, see if we can use a vector load to get all of the
6251 // elements, otherwise build the individual 128-bit pieces and use
6252 // shuffles to put them in place.
6253 if (VT.is256BitVector() || VT.is512BitVector()) {
6254 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6256 // Check for a build vector of consecutive loads.
6257 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6260 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6262 // Build both the lower and upper subvector.
6263 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6264 makeArrayRef(&V[0], NumElems/2));
6265 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6266 makeArrayRef(&V[NumElems / 2], NumElems/2));
6268 // Recreate the wider vector with the lower and upper part.
6269 if (VT.is256BitVector())
6270 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6271 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6274 // Let legalizer expand 2-wide build_vectors.
6275 if (EVTBits == 64) {
6276 if (NumNonZero == 1) {
6277 // One half is zero or undef.
6278 unsigned Idx = countTrailingZeros(NonZeros);
6279 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6280 Op.getOperand(Idx));
6281 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6286 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6287 if (EVTBits == 8 && NumElems == 16)
6288 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6292 if (EVTBits == 16 && NumElems == 8)
6293 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6297 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6298 if (EVTBits == 32 && NumElems == 4)
6299 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6302 // If element VT is == 32 bits, turn it into a number of shuffles.
6303 SmallVector<SDValue, 8> V(NumElems);
6304 if (NumElems == 4 && NumZero > 0) {
6305 for (unsigned i = 0; i < 4; ++i) {
6306 bool isZero = !(NonZeros & (1 << i));
6308 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6310 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6313 for (unsigned i = 0; i < 2; ++i) {
6314 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6317 V[i] = V[i*2]; // Must be a zero vector.
6320 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6323 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6326 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6331 bool Reverse1 = (NonZeros & 0x3) == 2;
6332 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6336 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6337 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6339 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6342 if (Values.size() > 1 && VT.is128BitVector()) {
6343 // Check for a build vector of consecutive loads.
6344 for (unsigned i = 0; i < NumElems; ++i)
6345 V[i] = Op.getOperand(i);
6347 // Check for elements which are consecutive loads.
6348 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6351 // Check for a build vector from mostly shuffle plus few inserting.
6352 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6355 // For SSE 4.1, use insertps to put the high elements into the low element.
6356 if (Subtarget->hasSSE41()) {
6358 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6359 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6361 Result = DAG.getUNDEF(VT);
6363 for (unsigned i = 1; i < NumElems; ++i) {
6364 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6365 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6366 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6371 // Otherwise, expand into a number of unpckl*, start by extending each of
6372 // our (non-undef) elements to the full vector width with the element in the
6373 // bottom slot of the vector (which generates no code for SSE).
6374 for (unsigned i = 0; i < NumElems; ++i) {
6375 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6376 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6378 V[i] = DAG.getUNDEF(VT);
6381 // Next, we iteratively mix elements, e.g. for v4f32:
6382 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6383 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6384 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6385 unsigned EltStride = NumElems >> 1;
6386 while (EltStride != 0) {
6387 for (unsigned i = 0; i < EltStride; ++i) {
6388 // If V[i+EltStride] is undef and this is the first round of mixing,
6389 // then it is safe to just drop this shuffle: V[i] is already in the
6390 // right place, the one element (since it's the first round) being
6391 // inserted as undef can be dropped. This isn't safe for successive
6392 // rounds because they will permute elements within both vectors.
6393 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6394 EltStride == NumElems/2)
6397 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6406 // 256-bit AVX can use the vinsertf128 instruction
6407 // to create 256-bit vectors from two other 128-bit ones.
6408 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6410 MVT ResVT = Op.getSimpleValueType();
6412 assert((ResVT.is256BitVector() ||
6413 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6415 SDValue V1 = Op.getOperand(0);
6416 SDValue V2 = Op.getOperand(1);
6417 unsigned NumElems = ResVT.getVectorNumElements();
6418 if (ResVT.is256BitVector())
6419 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6421 if (Op.getNumOperands() == 4) {
6422 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6423 ResVT.getVectorNumElements()/2);
6424 SDValue V3 = Op.getOperand(2);
6425 SDValue V4 = Op.getOperand(3);
6426 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6427 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6429 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6432 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6433 const X86Subtarget *Subtarget,
6434 SelectionDAG & DAG) {
6436 MVT ResVT = Op.getSimpleValueType();
6437 unsigned NumOfOperands = Op.getNumOperands();
6439 assert(isPowerOf2_32(NumOfOperands) &&
6440 "Unexpected number of operands in CONCAT_VECTORS");
6442 if (NumOfOperands > 2) {
6443 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6444 ResVT.getVectorNumElements()/2);
6445 SmallVector<SDValue, 2> Ops;
6446 for (unsigned i = 0; i < NumOfOperands/2; i++)
6447 Ops.push_back(Op.getOperand(i));
6448 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6450 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6451 Ops.push_back(Op.getOperand(i));
6452 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6453 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6456 SDValue V1 = Op.getOperand(0);
6457 SDValue V2 = Op.getOperand(1);
6458 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6459 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6461 if (IsZeroV1 && IsZeroV2)
6462 return getZeroVector(ResVT, Subtarget, DAG, dl);
6464 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6465 SDValue Undef = DAG.getUNDEF(ResVT);
6466 unsigned NumElems = ResVT.getVectorNumElements();
6467 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6469 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6470 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6474 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6475 // Zero the upper bits of V1
6476 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6477 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6480 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6483 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6484 const X86Subtarget *Subtarget,
6485 SelectionDAG &DAG) {
6486 MVT VT = Op.getSimpleValueType();
6487 if (VT.getVectorElementType() == MVT::i1)
6488 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6490 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6491 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6492 Op.getNumOperands() == 4)));
6494 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6495 // from two other 128-bit ones.
6497 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6498 return LowerAVXCONCAT_VECTORS(Op, DAG);
6501 //===----------------------------------------------------------------------===//
6502 // Vector shuffle lowering
6504 // This is an experimental code path for lowering vector shuffles on x86. It is
6505 // designed to handle arbitrary vector shuffles and blends, gracefully
6506 // degrading performance as necessary. It works hard to recognize idiomatic
6507 // shuffles and lower them to optimal instruction patterns without leaving
6508 // a framework that allows reasonably efficient handling of all vector shuffle
6510 //===----------------------------------------------------------------------===//
6512 /// \brief Tiny helper function to identify a no-op mask.
6514 /// This is a somewhat boring predicate function. It checks whether the mask
6515 /// array input, which is assumed to be a single-input shuffle mask of the kind
6516 /// used by the X86 shuffle instructions (not a fully general
6517 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6518 /// in-place shuffle are 'no-op's.
6519 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6520 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6521 if (Mask[i] != -1 && Mask[i] != i)
6526 /// \brief Helper function to classify a mask as a single-input mask.
6528 /// This isn't a generic single-input test because in the vector shuffle
6529 /// lowering we canonicalize single inputs to be the first input operand. This
6530 /// means we can more quickly test for a single input by only checking whether
6531 /// an input from the second operand exists. We also assume that the size of
6532 /// mask corresponds to the size of the input vectors which isn't true in the
6533 /// fully general case.
6534 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6536 if (M >= (int)Mask.size())
6541 /// \brief Test whether there are elements crossing 128-bit lanes in this
6544 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6545 /// and we routinely test for these.
6546 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6547 int LaneSize = 128 / VT.getScalarSizeInBits();
6548 int Size = Mask.size();
6549 for (int i = 0; i < Size; ++i)
6550 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6555 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6557 /// This checks a shuffle mask to see if it is performing the same
6558 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6559 /// that it is also not lane-crossing. It may however involve a blend from the
6560 /// same lane of a second vector.
6562 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6563 /// non-trivial to compute in the face of undef lanes. The representation is
6564 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6565 /// entries from both V1 and V2 inputs to the wider mask.
6567 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6568 SmallVectorImpl<int> &RepeatedMask) {
6569 int LaneSize = 128 / VT.getScalarSizeInBits();
6570 RepeatedMask.resize(LaneSize, -1);
6571 int Size = Mask.size();
6572 for (int i = 0; i < Size; ++i) {
6575 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6576 // This entry crosses lanes, so there is no way to model this shuffle.
6579 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6580 if (RepeatedMask[i % LaneSize] == -1)
6581 // This is the first non-undef entry in this slot of a 128-bit lane.
6582 RepeatedMask[i % LaneSize] =
6583 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6584 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6585 // Found a mismatch with the repeated mask.
6591 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6594 /// This is a fast way to test a shuffle mask against a fixed pattern:
6596 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6598 /// It returns true if the mask is exactly as wide as the argument list, and
6599 /// each element of the mask is either -1 (signifying undef) or the value given
6600 /// in the argument.
6601 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6602 ArrayRef<int> ExpectedMask) {
6603 if (Mask.size() != ExpectedMask.size())
6606 int Size = Mask.size();
6608 // If the values are build vectors, we can look through them to find
6609 // equivalent inputs that make the shuffles equivalent.
6610 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6611 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6613 for (int i = 0; i < Size; ++i)
6614 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6615 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6616 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6617 if (!MaskBV || !ExpectedBV ||
6618 MaskBV->getOperand(Mask[i] % Size) !=
6619 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6626 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6628 /// This helper function produces an 8-bit shuffle immediate corresponding to
6629 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6630 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6633 /// NB: We rely heavily on "undef" masks preserving the input lane.
6634 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6635 SelectionDAG &DAG) {
6636 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6637 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6638 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6639 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6640 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6643 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6644 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6645 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6646 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6647 return DAG.getConstant(Imm, DL, MVT::i8);
6650 /// \brief Compute whether each element of a shuffle is zeroable.
6652 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6653 /// Either it is an undef element in the shuffle mask, the element of the input
6654 /// referenced is undef, or the element of the input referenced is known to be
6655 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6656 /// as many lanes with this technique as possible to simplify the remaining
6658 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6659 SDValue V1, SDValue V2) {
6660 SmallBitVector Zeroable(Mask.size(), false);
6662 while (V1.getOpcode() == ISD::BITCAST)
6663 V1 = V1->getOperand(0);
6664 while (V2.getOpcode() == ISD::BITCAST)
6665 V2 = V2->getOperand(0);
6667 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6668 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6670 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6672 // Handle the easy cases.
6673 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6678 // If this is an index into a build_vector node (which has the same number
6679 // of elements), dig out the input value and use it.
6680 SDValue V = M < Size ? V1 : V2;
6681 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6684 SDValue Input = V.getOperand(M % Size);
6685 // The UNDEF opcode check really should be dead code here, but not quite
6686 // worth asserting on (it isn't invalid, just unexpected).
6687 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6694 // X86 has dedicated unpack instructions that can handle specific blend
6695 // operations: UNPCKH and UNPCKL.
6696 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6697 SDValue V1, SDValue V2,
6698 SelectionDAG &DAG) {
6699 int NumElts = VT.getVectorNumElements();
6702 bool UnpcklSwapped = true;
6703 bool UnpckhSwapped = true;
6704 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6706 for (int i = 0; i < NumElts; ++i) {
6707 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6709 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6710 int HiPos = LoPos + NumEltsInLane / 2;
6711 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6712 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6716 if (Mask[i] != LoPos)
6718 if (Mask[i] != HiPos)
6720 if (Mask[i] != LoPosSwapped)
6721 UnpcklSwapped = false;
6722 if (Mask[i] != HiPosSwapped)
6723 UnpckhSwapped = false;
6724 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6728 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6730 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6732 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6734 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6736 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6740 /// \brief Try to emit a bitmask instruction for a shuffle.
6742 /// This handles cases where we can model a blend exactly as a bitmask due to
6743 /// one of the inputs being zeroable.
6744 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6745 SDValue V2, ArrayRef<int> Mask,
6746 SelectionDAG &DAG) {
6747 MVT EltVT = VT.getScalarType();
6748 int NumEltBits = EltVT.getSizeInBits();
6749 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6750 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6751 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6753 if (EltVT.isFloatingPoint()) {
6754 Zero = DAG.getBitcast(EltVT, Zero);
6755 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6757 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6758 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6760 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6763 if (Mask[i] % Size != i)
6764 return SDValue(); // Not a blend.
6766 V = Mask[i] < Size ? V1 : V2;
6767 else if (V != (Mask[i] < Size ? V1 : V2))
6768 return SDValue(); // Can only let one input through the mask.
6770 VMaskOps[i] = AllOnes;
6773 return SDValue(); // No non-zeroable elements!
6775 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6776 V = DAG.getNode(VT.isFloatingPoint()
6777 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6782 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6784 /// This is used as a fallback approach when first class blend instructions are
6785 /// unavailable. Currently it is only suitable for integer vectors, but could
6786 /// be generalized for floating point vectors if desirable.
6787 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6788 SDValue V2, ArrayRef<int> Mask,
6789 SelectionDAG &DAG) {
6790 assert(VT.isInteger() && "Only supports integer vector types!");
6791 MVT EltVT = VT.getScalarType();
6792 int NumEltBits = EltVT.getSizeInBits();
6793 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6794 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6796 SmallVector<SDValue, 16> MaskOps;
6797 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6798 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6799 return SDValue(); // Shuffled input!
6800 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6803 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6804 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6805 // We have to cast V2 around.
6806 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6807 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6808 DAG.getBitcast(MaskVT, V1Mask),
6809 DAG.getBitcast(MaskVT, V2)));
6810 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6813 /// \brief Try to emit a blend instruction for a shuffle.
6815 /// This doesn't do any checks for the availability of instructions for blending
6816 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6817 /// be matched in the backend with the type given. What it does check for is
6818 /// that the shuffle mask is in fact a blend.
6819 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6820 SDValue V2, ArrayRef<int> Mask,
6821 const X86Subtarget *Subtarget,
6822 SelectionDAG &DAG) {
6823 unsigned BlendMask = 0;
6824 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6825 if (Mask[i] >= Size) {
6826 if (Mask[i] != i + Size)
6827 return SDValue(); // Shuffled V2 input!
6828 BlendMask |= 1u << i;
6831 if (Mask[i] >= 0 && Mask[i] != i)
6832 return SDValue(); // Shuffled V1 input!
6834 switch (VT.SimpleTy) {
6839 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6840 DAG.getConstant(BlendMask, DL, MVT::i8));
6844 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6848 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6849 // that instruction.
6850 if (Subtarget->hasAVX2()) {
6851 // Scale the blend by the number of 32-bit dwords per element.
6852 int Scale = VT.getScalarSizeInBits() / 32;
6854 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6855 if (Mask[i] >= Size)
6856 for (int j = 0; j < Scale; ++j)
6857 BlendMask |= 1u << (i * Scale + j);
6859 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6860 V1 = DAG.getBitcast(BlendVT, V1);
6861 V2 = DAG.getBitcast(BlendVT, V2);
6862 return DAG.getBitcast(
6863 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6864 DAG.getConstant(BlendMask, DL, MVT::i8)));
6868 // For integer shuffles we need to expand the mask and cast the inputs to
6869 // v8i16s prior to blending.
6870 int Scale = 8 / VT.getVectorNumElements();
6872 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6873 if (Mask[i] >= Size)
6874 for (int j = 0; j < Scale; ++j)
6875 BlendMask |= 1u << (i * Scale + j);
6877 V1 = DAG.getBitcast(MVT::v8i16, V1);
6878 V2 = DAG.getBitcast(MVT::v8i16, V2);
6879 return DAG.getBitcast(VT,
6880 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6881 DAG.getConstant(BlendMask, DL, MVT::i8)));
6885 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6886 SmallVector<int, 8> RepeatedMask;
6887 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6888 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6889 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6891 for (int i = 0; i < 8; ++i)
6892 if (RepeatedMask[i] >= 16)
6893 BlendMask |= 1u << i;
6894 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6895 DAG.getConstant(BlendMask, DL, MVT::i8));
6901 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6902 "256-bit byte-blends require AVX2 support!");
6904 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6905 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6908 // Scale the blend by the number of bytes per element.
6909 int Scale = VT.getScalarSizeInBits() / 8;
6911 // This form of blend is always done on bytes. Compute the byte vector
6913 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6915 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6916 // mix of LLVM's code generator and the x86 backend. We tell the code
6917 // generator that boolean values in the elements of an x86 vector register
6918 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6919 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6920 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6921 // of the element (the remaining are ignored) and 0 in that high bit would
6922 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6923 // the LLVM model for boolean values in vector elements gets the relevant
6924 // bit set, it is set backwards and over constrained relative to x86's
6926 SmallVector<SDValue, 32> VSELECTMask;
6927 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6928 for (int j = 0; j < Scale; ++j)
6929 VSELECTMask.push_back(
6930 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6931 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6934 V1 = DAG.getBitcast(BlendVT, V1);
6935 V2 = DAG.getBitcast(BlendVT, V2);
6936 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6937 DAG.getNode(ISD::BUILD_VECTOR, DL,
6938 BlendVT, VSELECTMask),
6943 llvm_unreachable("Not a supported integer vector type!");
6947 /// \brief Try to lower as a blend of elements from two inputs followed by
6948 /// a single-input permutation.
6950 /// This matches the pattern where we can blend elements from two inputs and
6951 /// then reduce the shuffle to a single-input permutation.
6952 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6955 SelectionDAG &DAG) {
6956 // We build up the blend mask while checking whether a blend is a viable way
6957 // to reduce the shuffle.
6958 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6959 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6961 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6965 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6967 if (BlendMask[Mask[i] % Size] == -1)
6968 BlendMask[Mask[i] % Size] = Mask[i];
6969 else if (BlendMask[Mask[i] % Size] != Mask[i])
6970 return SDValue(); // Can't blend in the needed input!
6972 PermuteMask[i] = Mask[i] % Size;
6975 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6976 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6979 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6980 /// blends and permutes.
6982 /// This matches the extremely common pattern for handling combined
6983 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6984 /// operations. It will try to pick the best arrangement of shuffles and
6986 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6990 SelectionDAG &DAG) {
6991 // Shuffle the input elements into the desired positions in V1 and V2 and
6992 // blend them together.
6993 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6994 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6995 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6996 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6997 if (Mask[i] >= 0 && Mask[i] < Size) {
6998 V1Mask[i] = Mask[i];
7000 } else if (Mask[i] >= Size) {
7001 V2Mask[i] = Mask[i] - Size;
7002 BlendMask[i] = i + Size;
7005 // Try to lower with the simpler initial blend strategy unless one of the
7006 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7007 // shuffle may be able to fold with a load or other benefit. However, when
7008 // we'll have to do 2x as many shuffles in order to achieve this, blending
7009 // first is a better strategy.
7010 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7011 if (SDValue BlendPerm =
7012 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7015 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7016 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7017 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7020 /// \brief Try to lower a vector shuffle as a byte rotation.
7022 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7023 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7024 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7025 /// try to generically lower a vector shuffle through such an pattern. It
7026 /// does not check for the profitability of lowering either as PALIGNR or
7027 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7028 /// This matches shuffle vectors that look like:
7030 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7032 /// Essentially it concatenates V1 and V2, shifts right by some number of
7033 /// elements, and takes the low elements as the result. Note that while this is
7034 /// specified as a *right shift* because x86 is little-endian, it is a *left
7035 /// rotate* of the vector lanes.
7036 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7039 const X86Subtarget *Subtarget,
7040 SelectionDAG &DAG) {
7041 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7043 int NumElts = Mask.size();
7044 int NumLanes = VT.getSizeInBits() / 128;
7045 int NumLaneElts = NumElts / NumLanes;
7047 // We need to detect various ways of spelling a rotation:
7048 // [11, 12, 13, 14, 15, 0, 1, 2]
7049 // [-1, 12, 13, 14, -1, -1, 1, -1]
7050 // [-1, -1, -1, -1, -1, -1, 1, 2]
7051 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7052 // [-1, 4, 5, 6, -1, -1, 9, -1]
7053 // [-1, 4, 5, 6, -1, -1, -1, -1]
7056 for (int l = 0; l < NumElts; l += NumLaneElts) {
7057 for (int i = 0; i < NumLaneElts; ++i) {
7058 if (Mask[l + i] == -1)
7060 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7062 // Get the mod-Size index and lane correct it.
7063 int LaneIdx = (Mask[l + i] % NumElts) - l;
7064 // Make sure it was in this lane.
7065 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7068 // Determine where a rotated vector would have started.
7069 int StartIdx = i - LaneIdx;
7071 // The identity rotation isn't interesting, stop.
7074 // If we found the tail of a vector the rotation must be the missing
7075 // front. If we found the head of a vector, it must be how much of the
7077 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7080 Rotation = CandidateRotation;
7081 else if (Rotation != CandidateRotation)
7082 // The rotations don't match, so we can't match this mask.
7085 // Compute which value this mask is pointing at.
7086 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7088 // Compute which of the two target values this index should be assigned
7089 // to. This reflects whether the high elements are remaining or the low
7090 // elements are remaining.
7091 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7093 // Either set up this value if we've not encountered it before, or check
7094 // that it remains consistent.
7097 else if (TargetV != MaskV)
7098 // This may be a rotation, but it pulls from the inputs in some
7099 // unsupported interleaving.
7104 // Check that we successfully analyzed the mask, and normalize the results.
7105 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7106 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7112 // The actual rotate instruction rotates bytes, so we need to scale the
7113 // rotation based on how many bytes are in the vector lane.
7114 int Scale = 16 / NumLaneElts;
7116 // SSSE3 targets can use the palignr instruction.
7117 if (Subtarget->hasSSSE3()) {
7118 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7119 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7120 Lo = DAG.getBitcast(AlignVT, Lo);
7121 Hi = DAG.getBitcast(AlignVT, Hi);
7123 return DAG.getBitcast(
7124 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7125 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7128 assert(VT.getSizeInBits() == 128 &&
7129 "Rotate-based lowering only supports 128-bit lowering!");
7130 assert(Mask.size() <= 16 &&
7131 "Can shuffle at most 16 bytes in a 128-bit vector!");
7133 // Default SSE2 implementation
7134 int LoByteShift = 16 - Rotation * Scale;
7135 int HiByteShift = Rotation * Scale;
7137 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7138 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7139 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7141 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7142 DAG.getConstant(LoByteShift, DL, MVT::i8));
7143 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7144 DAG.getConstant(HiByteShift, DL, MVT::i8));
7145 return DAG.getBitcast(VT,
7146 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7149 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7151 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7152 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7153 /// matches elements from one of the input vectors shuffled to the left or
7154 /// right with zeroable elements 'shifted in'. It handles both the strictly
7155 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7158 /// PSHL : (little-endian) left bit shift.
7159 /// [ zz, 0, zz, 2 ]
7160 /// [ -1, 4, zz, -1 ]
7161 /// PSRL : (little-endian) right bit shift.
7163 /// [ -1, -1, 7, zz]
7164 /// PSLLDQ : (little-endian) left byte shift
7165 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7166 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7167 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7168 /// PSRLDQ : (little-endian) right byte shift
7169 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7170 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7171 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7172 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7173 SDValue V2, ArrayRef<int> Mask,
7174 SelectionDAG &DAG) {
7175 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7177 int Size = Mask.size();
7178 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7180 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7181 for (int i = 0; i < Size; i += Scale)
7182 for (int j = 0; j < Shift; ++j)
7183 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7189 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7190 for (int i = 0; i != Size; i += Scale) {
7191 unsigned Pos = Left ? i + Shift : i;
7192 unsigned Low = Left ? i : i + Shift;
7193 unsigned Len = Scale - Shift;
7194 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7195 Low + (V == V1 ? 0 : Size)))
7199 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7200 bool ByteShift = ShiftEltBits > 64;
7201 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7202 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7203 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7205 // Normalize the scale for byte shifts to still produce an i64 element
7207 Scale = ByteShift ? Scale / 2 : Scale;
7209 // We need to round trip through the appropriate type for the shift.
7210 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7211 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7212 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7213 "Illegal integer vector type");
7214 V = DAG.getBitcast(ShiftVT, V);
7216 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7217 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7218 return DAG.getBitcast(VT, V);
7221 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7222 // keep doubling the size of the integer elements up to that. We can
7223 // then shift the elements of the integer vector by whole multiples of
7224 // their width within the elements of the larger integer vector. Test each
7225 // multiple to see if we can find a match with the moved element indices
7226 // and that the shifted in elements are all zeroable.
7227 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7228 for (int Shift = 1; Shift != Scale; ++Shift)
7229 for (bool Left : {true, false})
7230 if (CheckZeros(Shift, Scale, Left))
7231 for (SDValue V : {V1, V2})
7232 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7239 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7240 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7241 SDValue V2, ArrayRef<int> Mask,
7242 SelectionDAG &DAG) {
7243 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7244 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7246 int Size = Mask.size();
7247 int HalfSize = Size / 2;
7248 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7250 // Upper half must be undefined.
7251 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7254 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7255 // Remainder of lower half result is zero and upper half is all undef.
7256 auto LowerAsEXTRQ = [&]() {
7257 // Determine the extraction length from the part of the
7258 // lower half that isn't zeroable.
7260 for (; Len >= 0; --Len)
7261 if (!Zeroable[Len - 1])
7263 assert(Len > 0 && "Zeroable shuffle mask");
7265 // Attempt to match first Len sequential elements from the lower half.
7268 for (int i = 0; i != Len; ++i) {
7272 SDValue &V = (M < Size ? V1 : V2);
7275 // All mask elements must be in the lower half.
7279 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7290 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7291 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7292 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7293 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7294 DAG.getConstant(BitLen, DL, MVT::i8),
7295 DAG.getConstant(BitIdx, DL, MVT::i8));
7298 if (SDValue ExtrQ = LowerAsEXTRQ())
7301 // INSERTQ: Extract lowest Len elements from lower half of second source and
7302 // insert over first source, starting at Idx.
7303 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7304 auto LowerAsInsertQ = [&]() {
7305 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7308 // Attempt to match first source from mask before insertion point.
7309 if (isUndefInRange(Mask, 0, Idx)) {
7311 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7313 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7319 // Extend the extraction length looking to match both the insertion of
7320 // the second source and the remaining elements of the first.
7321 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7326 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7328 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7334 // Match the remaining elements of the lower half.
7335 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7337 } else if ((!Base || (Base == V1)) &&
7338 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7340 } else if ((!Base || (Base == V2)) &&
7341 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7348 // We may not have a base (first source) - this can safely be undefined.
7350 Base = DAG.getUNDEF(VT);
7352 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7353 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7354 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7355 DAG.getConstant(BitLen, DL, MVT::i8),
7356 DAG.getConstant(BitIdx, DL, MVT::i8));
7363 if (SDValue InsertQ = LowerAsInsertQ())
7369 /// \brief Lower a vector shuffle as a zero or any extension.
7371 /// Given a specific number of elements, element bit width, and extension
7372 /// stride, produce either a zero or any extension based on the available
7373 /// features of the subtarget. The extended elements are consecutive and
7374 /// begin and can start from an offseted element index in the input; to
7375 /// avoid excess shuffling the offset must either being in the bottom lane
7376 /// or at the start of a higher lane. All extended elements must be from
7378 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7379 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7380 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7381 assert(Scale > 1 && "Need a scale to extend.");
7382 int EltBits = VT.getScalarSizeInBits();
7383 int NumElements = VT.getVectorNumElements();
7384 int NumEltsPerLane = 128 / EltBits;
7385 int OffsetLane = Offset / NumEltsPerLane;
7386 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7387 "Only 8, 16, and 32 bit elements can be extended.");
7388 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7389 assert(0 <= Offset && "Extension offset must be positive.");
7390 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7391 "Extension offset must be in the first lane or start an upper lane.");
7393 // Check that an index is in same lane as the base offset.
7394 auto SafeOffset = [&](int Idx) {
7395 return OffsetLane == (Idx / NumEltsPerLane);
7398 // Shift along an input so that the offset base moves to the first element.
7399 auto ShuffleOffset = [&](SDValue V) {
7403 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7404 for (int i = 0; i * Scale < NumElements; ++i) {
7405 int SrcIdx = i + Offset;
7406 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7408 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7411 // Found a valid zext mask! Try various lowering strategies based on the
7412 // input type and available ISA extensions.
7413 if (Subtarget->hasSSE41()) {
7414 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7415 // PUNPCK will catch this in a later shuffle match.
7416 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7418 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7419 NumElements / Scale);
7420 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7421 return DAG.getBitcast(VT, InputV);
7424 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7426 // For any extends we can cheat for larger element sizes and use shuffle
7427 // instructions that can fold with a load and/or copy.
7428 if (AnyExt && EltBits == 32) {
7429 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7431 return DAG.getBitcast(
7432 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7433 DAG.getBitcast(MVT::v4i32, InputV),
7434 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7436 if (AnyExt && EltBits == 16 && Scale > 2) {
7437 int PSHUFDMask[4] = {Offset / 2, -1,
7438 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7439 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7440 DAG.getBitcast(MVT::v4i32, InputV),
7441 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7442 int PSHUFWMask[4] = {1, -1, -1, -1};
7443 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7444 return DAG.getBitcast(
7445 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7446 DAG.getBitcast(MVT::v8i16, InputV),
7447 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7450 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7452 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7453 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7454 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7456 int LoIdx = Offset * EltBits;
7457 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7458 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7459 DAG.getConstant(EltBits, DL, MVT::i8),
7460 DAG.getConstant(LoIdx, DL, MVT::i8)));
7462 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7463 !SafeOffset(Offset + 1))
7464 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7466 int HiIdx = (Offset + 1) * EltBits;
7467 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7468 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7469 DAG.getConstant(EltBits, DL, MVT::i8),
7470 DAG.getConstant(HiIdx, DL, MVT::i8)));
7471 return DAG.getNode(ISD::BITCAST, DL, VT,
7472 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7475 // If this would require more than 2 unpack instructions to expand, use
7476 // pshufb when available. We can only use more than 2 unpack instructions
7477 // when zero extending i8 elements which also makes it easier to use pshufb.
7478 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7479 assert(NumElements == 16 && "Unexpected byte vector width!");
7480 SDValue PSHUFBMask[16];
7481 for (int i = 0; i < 16; ++i) {
7482 int Idx = Offset + (i / Scale);
7483 PSHUFBMask[i] = DAG.getConstant(
7484 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7486 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7487 return DAG.getBitcast(VT,
7488 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7489 DAG.getNode(ISD::BUILD_VECTOR, DL,
7490 MVT::v16i8, PSHUFBMask)));
7493 // If we are extending from an offset, ensure we start on a boundary that
7494 // we can unpack from.
7495 int AlignToUnpack = Offset % (NumElements / Scale);
7496 if (AlignToUnpack) {
7497 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7498 for (int i = AlignToUnpack; i < NumElements; ++i)
7499 ShMask[i - AlignToUnpack] = i;
7500 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7501 Offset -= AlignToUnpack;
7504 // Otherwise emit a sequence of unpacks.
7506 unsigned UnpackLoHi = X86ISD::UNPCKL;
7507 if (Offset >= (NumElements / 2)) {
7508 UnpackLoHi = X86ISD::UNPCKH;
7509 Offset -= (NumElements / 2);
7512 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7513 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7514 : getZeroVector(InputVT, Subtarget, DAG, DL);
7515 InputV = DAG.getBitcast(InputVT, InputV);
7516 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7520 } while (Scale > 1);
7521 return DAG.getBitcast(VT, InputV);
7524 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7526 /// This routine will try to do everything in its power to cleverly lower
7527 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7528 /// check for the profitability of this lowering, it tries to aggressively
7529 /// match this pattern. It will use all of the micro-architectural details it
7530 /// can to emit an efficient lowering. It handles both blends with all-zero
7531 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7532 /// masking out later).
7534 /// The reason we have dedicated lowering for zext-style shuffles is that they
7535 /// are both incredibly common and often quite performance sensitive.
7536 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7537 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7538 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7539 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7541 int Bits = VT.getSizeInBits();
7542 int NumLanes = Bits / 128;
7543 int NumElements = VT.getVectorNumElements();
7544 int NumEltsPerLane = NumElements / NumLanes;
7545 assert(VT.getScalarSizeInBits() <= 32 &&
7546 "Exceeds 32-bit integer zero extension limit");
7547 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7549 // Define a helper function to check a particular ext-scale and lower to it if
7551 auto Lower = [&](int Scale) -> SDValue {
7556 for (int i = 0; i < NumElements; ++i) {
7559 continue; // Valid anywhere but doesn't tell us anything.
7560 if (i % Scale != 0) {
7561 // Each of the extended elements need to be zeroable.
7565 // We no longer are in the anyext case.
7570 // Each of the base elements needs to be consecutive indices into the
7571 // same input vector.
7572 SDValue V = M < NumElements ? V1 : V2;
7573 M = M % NumElements;
7576 Offset = M - (i / Scale);
7577 } else if (InputV != V)
7578 return SDValue(); // Flip-flopping inputs.
7580 // Offset must start in the lowest 128-bit lane or at the start of an
7582 // FIXME: Is it ever worth allowing a negative base offset?
7583 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7584 (Offset % NumEltsPerLane) == 0))
7587 // If we are offsetting, all referenced entries must come from the same
7589 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7592 if ((M % NumElements) != (Offset + (i / Scale)))
7593 return SDValue(); // Non-consecutive strided elements.
7597 // If we fail to find an input, we have a zero-shuffle which should always
7598 // have already been handled.
7599 // FIXME: Maybe handle this here in case during blending we end up with one?
7603 // If we are offsetting, don't extend if we only match a single input, we
7604 // can always do better by using a basic PSHUF or PUNPCK.
7605 if (Offset != 0 && Matches < 2)
7608 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7609 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7612 // The widest scale possible for extending is to a 64-bit integer.
7613 assert(Bits % 64 == 0 &&
7614 "The number of bits in a vector must be divisible by 64 on x86!");
7615 int NumExtElements = Bits / 64;
7617 // Each iteration, try extending the elements half as much, but into twice as
7619 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7620 assert(NumElements % NumExtElements == 0 &&
7621 "The input vector size must be divisible by the extended size.");
7622 if (SDValue V = Lower(NumElements / NumExtElements))
7626 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7630 // Returns one of the source operands if the shuffle can be reduced to a
7631 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7632 auto CanZExtLowHalf = [&]() {
7633 for (int i = NumElements / 2; i != NumElements; ++i)
7636 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7638 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7643 if (SDValue V = CanZExtLowHalf()) {
7644 V = DAG.getBitcast(MVT::v2i64, V);
7645 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7646 return DAG.getBitcast(VT, V);
7649 // No viable ext lowering found.
7653 /// \brief Try to get a scalar value for a specific element of a vector.
7655 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7656 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7657 SelectionDAG &DAG) {
7658 MVT VT = V.getSimpleValueType();
7659 MVT EltVT = VT.getVectorElementType();
7660 while (V.getOpcode() == ISD::BITCAST)
7661 V = V.getOperand(0);
7662 // If the bitcasts shift the element size, we can't extract an equivalent
7664 MVT NewVT = V.getSimpleValueType();
7665 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7668 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7669 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7670 // Ensure the scalar operand is the same size as the destination.
7671 // FIXME: Add support for scalar truncation where possible.
7672 SDValue S = V.getOperand(Idx);
7673 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7674 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7680 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7682 /// This is particularly important because the set of instructions varies
7683 /// significantly based on whether the operand is a load or not.
7684 static bool isShuffleFoldableLoad(SDValue V) {
7685 while (V.getOpcode() == ISD::BITCAST)
7686 V = V.getOperand(0);
7688 return ISD::isNON_EXTLoad(V.getNode());
7691 /// \brief Try to lower insertion of a single element into a zero vector.
7693 /// This is a common pattern that we have especially efficient patterns to lower
7694 /// across all subtarget feature sets.
7695 static SDValue lowerVectorShuffleAsElementInsertion(
7696 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7697 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7698 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7700 MVT EltVT = VT.getVectorElementType();
7702 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7703 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7705 bool IsV1Zeroable = true;
7706 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7707 if (i != V2Index && !Zeroable[i]) {
7708 IsV1Zeroable = false;
7712 // Check for a single input from a SCALAR_TO_VECTOR node.
7713 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7714 // all the smarts here sunk into that routine. However, the current
7715 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7716 // vector shuffle lowering is dead.
7717 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7719 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7720 // We need to zext the scalar if it is smaller than an i32.
7721 V2S = DAG.getBitcast(EltVT, V2S);
7722 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7723 // Using zext to expand a narrow element won't work for non-zero
7728 // Zero-extend directly to i32.
7730 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7732 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7733 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7734 EltVT == MVT::i16) {
7735 // Either not inserting from the low element of the input or the input
7736 // element size is too small to use VZEXT_MOVL to clear the high bits.
7740 if (!IsV1Zeroable) {
7741 // If V1 can't be treated as a zero vector we have fewer options to lower
7742 // this. We can't support integer vectors or non-zero targets cheaply, and
7743 // the V1 elements can't be permuted in any way.
7744 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7745 if (!VT.isFloatingPoint() || V2Index != 0)
7747 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7748 V1Mask[V2Index] = -1;
7749 if (!isNoopShuffleMask(V1Mask))
7751 // This is essentially a special case blend operation, but if we have
7752 // general purpose blend operations, they are always faster. Bail and let
7753 // the rest of the lowering handle these as blends.
7754 if (Subtarget->hasSSE41())
7757 // Otherwise, use MOVSD or MOVSS.
7758 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7759 "Only two types of floating point element types to handle!");
7760 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7764 // This lowering only works for the low element with floating point vectors.
7765 if (VT.isFloatingPoint() && V2Index != 0)
7768 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7770 V2 = DAG.getBitcast(VT, V2);
7773 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7774 // the desired position. Otherwise it is more efficient to do a vector
7775 // shift left. We know that we can do a vector shift left because all
7776 // the inputs are zero.
7777 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7778 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7779 V2Shuffle[V2Index] = 0;
7780 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7782 V2 = DAG.getBitcast(MVT::v2i64, V2);
7784 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7785 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7786 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7787 DAG.getDataLayout(), VT)));
7788 V2 = DAG.getBitcast(VT, V2);
7794 /// \brief Try to lower broadcast of a single element.
7796 /// For convenience, this code also bundles all of the subtarget feature set
7797 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7798 /// a convenient way to factor it out.
7799 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7801 const X86Subtarget *Subtarget,
7802 SelectionDAG &DAG) {
7803 if (!Subtarget->hasAVX())
7805 if (VT.isInteger() && !Subtarget->hasAVX2())
7808 // Check that the mask is a broadcast.
7809 int BroadcastIdx = -1;
7811 if (M >= 0 && BroadcastIdx == -1)
7813 else if (M >= 0 && M != BroadcastIdx)
7816 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7817 "a sorted mask where the broadcast "
7820 // Go up the chain of (vector) values to find a scalar load that we can
7821 // combine with the broadcast.
7823 switch (V.getOpcode()) {
7824 case ISD::CONCAT_VECTORS: {
7825 int OperandSize = Mask.size() / V.getNumOperands();
7826 V = V.getOperand(BroadcastIdx / OperandSize);
7827 BroadcastIdx %= OperandSize;
7831 case ISD::INSERT_SUBVECTOR: {
7832 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7833 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7837 int BeginIdx = (int)ConstantIdx->getZExtValue();
7839 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7840 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7841 BroadcastIdx -= BeginIdx;
7852 // Check if this is a broadcast of a scalar. We special case lowering
7853 // for scalars so that we can more effectively fold with loads.
7854 // First, look through bitcast: if the original value has a larger element
7855 // type than the shuffle, the broadcast element is in essence truncated.
7856 // Make that explicit to ease folding.
7857 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7858 EVT EltVT = VT.getVectorElementType();
7859 SDValue V0 = V.getOperand(0);
7860 EVT V0VT = V0.getValueType();
7862 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7863 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7864 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7865 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7870 // Also check the simpler case, where we can directly reuse the scalar.
7871 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7872 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7873 V = V.getOperand(BroadcastIdx);
7875 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7876 // Only AVX2 has register broadcasts.
7877 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7879 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7880 // We can't broadcast from a vector register without AVX2, and we can only
7881 // broadcast from the zero-element of a vector register.
7885 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7888 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7889 // INSERTPS when the V1 elements are already in the correct locations
7890 // because otherwise we can just always use two SHUFPS instructions which
7891 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7892 // perform INSERTPS if a single V1 element is out of place and all V2
7893 // elements are zeroable.
7894 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7896 SelectionDAG &DAG) {
7897 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7898 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7899 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7900 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7902 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7905 int V1DstIndex = -1;
7906 int V2DstIndex = -1;
7907 bool V1UsedInPlace = false;
7909 for (int i = 0; i < 4; ++i) {
7910 // Synthesize a zero mask from the zeroable elements (includes undefs).
7916 // Flag if we use any V1 inputs in place.
7918 V1UsedInPlace = true;
7922 // We can only insert a single non-zeroable element.
7923 if (V1DstIndex != -1 || V2DstIndex != -1)
7927 // V1 input out of place for insertion.
7930 // V2 input for insertion.
7935 // Don't bother if we have no (non-zeroable) element for insertion.
7936 if (V1DstIndex == -1 && V2DstIndex == -1)
7939 // Determine element insertion src/dst indices. The src index is from the
7940 // start of the inserted vector, not the start of the concatenated vector.
7941 unsigned V2SrcIndex = 0;
7942 if (V1DstIndex != -1) {
7943 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7944 // and don't use the original V2 at all.
7945 V2SrcIndex = Mask[V1DstIndex];
7946 V2DstIndex = V1DstIndex;
7949 V2SrcIndex = Mask[V2DstIndex] - 4;
7952 // If no V1 inputs are used in place, then the result is created only from
7953 // the zero mask and the V2 insertion - so remove V1 dependency.
7955 V1 = DAG.getUNDEF(MVT::v4f32);
7957 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7958 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7960 // Insert the V2 element into the desired position.
7962 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7963 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7966 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7967 /// UNPCK instruction.
7969 /// This specifically targets cases where we end up with alternating between
7970 /// the two inputs, and so can permute them into something that feeds a single
7971 /// UNPCK instruction. Note that this routine only targets integer vectors
7972 /// because for floating point vectors we have a generalized SHUFPS lowering
7973 /// strategy that handles everything that doesn't *exactly* match an unpack,
7974 /// making this clever lowering unnecessary.
7975 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
7976 SDValue V1, SDValue V2,
7978 SelectionDAG &DAG) {
7979 assert(!VT.isFloatingPoint() &&
7980 "This routine only supports integer vectors.");
7981 assert(!isSingleInputShuffleMask(Mask) &&
7982 "This routine should only be used when blending two inputs.");
7983 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7985 int Size = Mask.size();
7987 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7988 return M >= 0 && M % Size < Size / 2;
7990 int NumHiInputs = std::count_if(
7991 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7993 bool UnpackLo = NumLoInputs >= NumHiInputs;
7995 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7996 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7997 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7999 for (int i = 0; i < Size; ++i) {
8003 // Each element of the unpack contains Scale elements from this mask.
8004 int UnpackIdx = i / Scale;
8006 // We only handle the case where V1 feeds the first slots of the unpack.
8007 // We rely on canonicalization to ensure this is the case.
8008 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8011 // Setup the mask for this input. The indexing is tricky as we have to
8012 // handle the unpack stride.
8013 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8014 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8018 // If we will have to shuffle both inputs to use the unpack, check whether
8019 // we can just unpack first and shuffle the result. If so, skip this unpack.
8020 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8021 !isNoopShuffleMask(V2Mask))
8024 // Shuffle the inputs into place.
8025 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8026 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8028 // Cast the inputs to the type we will use to unpack them.
8029 V1 = DAG.getBitcast(UnpackVT, V1);
8030 V2 = DAG.getBitcast(UnpackVT, V2);
8032 // Unpack the inputs and cast the result back to the desired type.
8033 return DAG.getBitcast(
8034 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8038 // We try each unpack from the largest to the smallest to try and find one
8039 // that fits this mask.
8040 int OrigNumElements = VT.getVectorNumElements();
8041 int OrigScalarSize = VT.getScalarSizeInBits();
8042 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8043 int Scale = ScalarSize / OrigScalarSize;
8044 int NumElements = OrigNumElements / Scale;
8045 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8046 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8050 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8052 if (NumLoInputs == 0 || NumHiInputs == 0) {
8053 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8054 "We have to have *some* inputs!");
8055 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8057 // FIXME: We could consider the total complexity of the permute of each
8058 // possible unpacking. Or at the least we should consider how many
8059 // half-crossings are created.
8060 // FIXME: We could consider commuting the unpacks.
8062 SmallVector<int, 32> PermMask;
8063 PermMask.assign(Size, -1);
8064 for (int i = 0; i < Size; ++i) {
8068 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8071 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8073 return DAG.getVectorShuffle(
8074 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8076 DAG.getUNDEF(VT), PermMask);
8082 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8084 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8085 /// support for floating point shuffles but not integer shuffles. These
8086 /// instructions will incur a domain crossing penalty on some chips though so
8087 /// it is better to avoid lowering through this for integer vectors where
8089 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8090 const X86Subtarget *Subtarget,
8091 SelectionDAG &DAG) {
8093 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8094 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8095 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8096 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8097 ArrayRef<int> Mask = SVOp->getMask();
8098 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8100 if (isSingleInputShuffleMask(Mask)) {
8101 // Use low duplicate instructions for masks that match their pattern.
8102 if (Subtarget->hasSSE3())
8103 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8104 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8106 // Straight shuffle of a single input vector. Simulate this by using the
8107 // single input as both of the "inputs" to this instruction..
8108 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8110 if (Subtarget->hasAVX()) {
8111 // If we have AVX, we can use VPERMILPS which will allow folding a load
8112 // into the shuffle.
8113 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8114 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8117 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8118 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8120 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8121 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8123 // If we have a single input, insert that into V1 if we can do so cheaply.
8124 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8125 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8126 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8128 // Try inverting the insertion since for v2 masks it is easy to do and we
8129 // can't reliably sort the mask one way or the other.
8130 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8131 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8132 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8133 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8137 // Try to use one of the special instruction patterns to handle two common
8138 // blend patterns if a zero-blend above didn't work.
8139 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8140 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8141 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8142 // We can either use a special instruction to load over the low double or
8143 // to move just the low double.
8145 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8147 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8149 if (Subtarget->hasSSE41())
8150 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8154 // Use dedicated unpack instructions for masks that match their pattern.
8155 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8156 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8157 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8158 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8160 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8161 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8162 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8165 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8167 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8168 /// the integer unit to minimize domain crossing penalties. However, for blends
8169 /// it falls back to the floating point shuffle operation with appropriate bit
8171 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8172 const X86Subtarget *Subtarget,
8173 SelectionDAG &DAG) {
8175 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8176 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8177 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8178 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8179 ArrayRef<int> Mask = SVOp->getMask();
8180 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8182 if (isSingleInputShuffleMask(Mask)) {
8183 // Check for being able to broadcast a single element.
8184 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8185 Mask, Subtarget, DAG))
8188 // Straight shuffle of a single input vector. For everything from SSE2
8189 // onward this has a single fast instruction with no scary immediates.
8190 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8191 V1 = DAG.getBitcast(MVT::v4i32, V1);
8192 int WidenedMask[4] = {
8193 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8194 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8195 return DAG.getBitcast(
8197 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8198 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8200 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8201 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8202 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8203 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8205 // If we have a blend of two PACKUS operations an the blend aligns with the
8206 // low and half halves, we can just merge the PACKUS operations. This is
8207 // particularly important as it lets us merge shuffles that this routine itself
8209 auto GetPackNode = [](SDValue V) {
8210 while (V.getOpcode() == ISD::BITCAST)
8211 V = V.getOperand(0);
8213 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8215 if (SDValue V1Pack = GetPackNode(V1))
8216 if (SDValue V2Pack = GetPackNode(V2))
8217 return DAG.getBitcast(MVT::v2i64,
8218 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8219 Mask[0] == 0 ? V1Pack.getOperand(0)
8220 : V1Pack.getOperand(1),
8221 Mask[1] == 2 ? V2Pack.getOperand(0)
8222 : V2Pack.getOperand(1)));
8224 // Try to use shift instructions.
8226 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8229 // When loading a scalar and then shuffling it into a vector we can often do
8230 // the insertion cheaply.
8231 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8232 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8234 // Try inverting the insertion since for v2 masks it is easy to do and we
8235 // can't reliably sort the mask one way or the other.
8236 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8237 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8238 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8241 // We have different paths for blend lowering, but they all must use the
8242 // *exact* same predicate.
8243 bool IsBlendSupported = Subtarget->hasSSE41();
8244 if (IsBlendSupported)
8245 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8249 // Use dedicated unpack instructions for masks that match their pattern.
8250 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8251 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8252 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8253 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8255 // Try to use byte rotation instructions.
8256 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8257 if (Subtarget->hasSSSE3())
8258 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8259 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8262 // If we have direct support for blends, we should lower by decomposing into
8263 // a permute. That will be faster than the domain cross.
8264 if (IsBlendSupported)
8265 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8268 // We implement this with SHUFPD which is pretty lame because it will likely
8269 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8270 // However, all the alternatives are still more cycles and newer chips don't
8271 // have this problem. It would be really nice if x86 had better shuffles here.
8272 V1 = DAG.getBitcast(MVT::v2f64, V1);
8273 V2 = DAG.getBitcast(MVT::v2f64, V2);
8274 return DAG.getBitcast(MVT::v2i64,
8275 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8278 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8280 /// This is used to disable more specialized lowerings when the shufps lowering
8281 /// will happen to be efficient.
8282 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8283 // This routine only handles 128-bit shufps.
8284 assert(Mask.size() == 4 && "Unsupported mask size!");
8286 // To lower with a single SHUFPS we need to have the low half and high half
8287 // each requiring a single input.
8288 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8290 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8296 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8298 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8299 /// It makes no assumptions about whether this is the *best* lowering, it simply
8301 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8302 ArrayRef<int> Mask, SDValue V1,
8303 SDValue V2, SelectionDAG &DAG) {
8304 SDValue LowV = V1, HighV = V2;
8305 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8308 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8310 if (NumV2Elements == 1) {
8312 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8315 // Compute the index adjacent to V2Index and in the same half by toggling
8317 int V2AdjIndex = V2Index ^ 1;
8319 if (Mask[V2AdjIndex] == -1) {
8320 // Handles all the cases where we have a single V2 element and an undef.
8321 // This will only ever happen in the high lanes because we commute the
8322 // vector otherwise.
8324 std::swap(LowV, HighV);
8325 NewMask[V2Index] -= 4;
8327 // Handle the case where the V2 element ends up adjacent to a V1 element.
8328 // To make this work, blend them together as the first step.
8329 int V1Index = V2AdjIndex;
8330 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8331 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8332 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8334 // Now proceed to reconstruct the final blend as we have the necessary
8335 // high or low half formed.
8342 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8343 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8345 } else if (NumV2Elements == 2) {
8346 if (Mask[0] < 4 && Mask[1] < 4) {
8347 // Handle the easy case where we have V1 in the low lanes and V2 in the
8351 } else if (Mask[2] < 4 && Mask[3] < 4) {
8352 // We also handle the reversed case because this utility may get called
8353 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8354 // arrange things in the right direction.
8360 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8361 // trying to place elements directly, just blend them and set up the final
8362 // shuffle to place them.
8364 // The first two blend mask elements are for V1, the second two are for
8366 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8367 Mask[2] < 4 ? Mask[2] : Mask[3],
8368 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8369 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8370 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8371 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8373 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8376 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8377 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8378 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8379 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8382 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8383 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8386 /// \brief Lower 4-lane 32-bit floating point shuffles.
8388 /// Uses instructions exclusively from the floating point unit to minimize
8389 /// domain crossing penalties, as these are sufficient to implement all v4f32
8391 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8392 const X86Subtarget *Subtarget,
8393 SelectionDAG &DAG) {
8395 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8396 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8397 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8398 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8399 ArrayRef<int> Mask = SVOp->getMask();
8400 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8403 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8405 if (NumV2Elements == 0) {
8406 // Check for being able to broadcast a single element.
8407 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8408 Mask, Subtarget, DAG))
8411 // Use even/odd duplicate instructions for masks that match their pattern.
8412 if (Subtarget->hasSSE3()) {
8413 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8414 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8415 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8416 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8419 if (Subtarget->hasAVX()) {
8420 // If we have AVX, we can use VPERMILPS which will allow folding a load
8421 // into the shuffle.
8422 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8423 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8426 // Otherwise, use a straight shuffle of a single input vector. We pass the
8427 // input vector to both operands to simulate this with a SHUFPS.
8428 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8429 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8432 // There are special ways we can lower some single-element blends. However, we
8433 // have custom ways we can lower more complex single-element blends below that
8434 // we defer to if both this and BLENDPS fail to match, so restrict this to
8435 // when the V2 input is targeting element 0 of the mask -- that is the fast
8437 if (NumV2Elements == 1 && Mask[0] >= 4)
8438 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8439 Mask, Subtarget, DAG))
8442 if (Subtarget->hasSSE41()) {
8443 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8447 // Use INSERTPS if we can complete the shuffle efficiently.
8448 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8451 if (!isSingleSHUFPSMask(Mask))
8452 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8453 DL, MVT::v4f32, V1, V2, Mask, DAG))
8457 // Use dedicated unpack instructions for masks that match their pattern.
8458 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8459 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8460 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8461 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8462 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8463 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8464 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8465 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8467 // Otherwise fall back to a SHUFPS lowering strategy.
8468 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8471 /// \brief Lower 4-lane i32 vector shuffles.
8473 /// We try to handle these with integer-domain shuffles where we can, but for
8474 /// blends we use the floating point domain blend instructions.
8475 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8476 const X86Subtarget *Subtarget,
8477 SelectionDAG &DAG) {
8479 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8480 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8481 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8482 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8483 ArrayRef<int> Mask = SVOp->getMask();
8484 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8486 // Whenever we can lower this as a zext, that instruction is strictly faster
8487 // than any alternative. It also allows us to fold memory operands into the
8488 // shuffle in many cases.
8489 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8490 Mask, Subtarget, DAG))
8494 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8496 if (NumV2Elements == 0) {
8497 // Check for being able to broadcast a single element.
8498 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8499 Mask, Subtarget, DAG))
8502 // Straight shuffle of a single input vector. For everything from SSE2
8503 // onward this has a single fast instruction with no scary immediates.
8504 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8505 // but we aren't actually going to use the UNPCK instruction because doing
8506 // so prevents folding a load into this instruction or making a copy.
8507 const int UnpackLoMask[] = {0, 0, 1, 1};
8508 const int UnpackHiMask[] = {2, 2, 3, 3};
8509 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8510 Mask = UnpackLoMask;
8511 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8512 Mask = UnpackHiMask;
8514 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8515 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8518 // Try to use shift instructions.
8520 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8523 // There are special ways we can lower some single-element blends.
8524 if (NumV2Elements == 1)
8525 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8526 Mask, Subtarget, DAG))
8529 // We have different paths for blend lowering, but they all must use the
8530 // *exact* same predicate.
8531 bool IsBlendSupported = Subtarget->hasSSE41();
8532 if (IsBlendSupported)
8533 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8537 if (SDValue Masked =
8538 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8541 // Use dedicated unpack instructions for masks that match their pattern.
8542 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8543 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8544 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8545 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8546 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8547 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8548 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8549 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8551 // Try to use byte rotation instructions.
8552 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8553 if (Subtarget->hasSSSE3())
8554 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8555 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8558 // If we have direct support for blends, we should lower by decomposing into
8559 // a permute. That will be faster than the domain cross.
8560 if (IsBlendSupported)
8561 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8564 // Try to lower by permuting the inputs into an unpack instruction.
8565 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8569 // We implement this with SHUFPS because it can blend from two vectors.
8570 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8571 // up the inputs, bypassing domain shift penalties that we would encur if we
8572 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8574 return DAG.getBitcast(
8576 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8577 DAG.getBitcast(MVT::v4f32, V2), Mask));
8580 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8581 /// shuffle lowering, and the most complex part.
8583 /// The lowering strategy is to try to form pairs of input lanes which are
8584 /// targeted at the same half of the final vector, and then use a dword shuffle
8585 /// to place them onto the right half, and finally unpack the paired lanes into
8586 /// their final position.
8588 /// The exact breakdown of how to form these dword pairs and align them on the
8589 /// correct sides is really tricky. See the comments within the function for
8590 /// more of the details.
8592 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8593 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8594 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8595 /// vector, form the analogous 128-bit 8-element Mask.
8596 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8597 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8598 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8599 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8600 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8602 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8603 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8604 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8606 SmallVector<int, 4> LoInputs;
8607 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8608 [](int M) { return M >= 0; });
8609 std::sort(LoInputs.begin(), LoInputs.end());
8610 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8611 SmallVector<int, 4> HiInputs;
8612 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8613 [](int M) { return M >= 0; });
8614 std::sort(HiInputs.begin(), HiInputs.end());
8615 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8617 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8618 int NumHToL = LoInputs.size() - NumLToL;
8620 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8621 int NumHToH = HiInputs.size() - NumLToH;
8622 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8623 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8624 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8625 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8627 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8628 // such inputs we can swap two of the dwords across the half mark and end up
8629 // with <=2 inputs to each half in each half. Once there, we can fall through
8630 // to the generic code below. For example:
8632 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8633 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8635 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8636 // and an existing 2-into-2 on the other half. In this case we may have to
8637 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8638 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8639 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8640 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8641 // half than the one we target for fixing) will be fixed when we re-enter this
8642 // path. We will also combine away any sequence of PSHUFD instructions that
8643 // result into a single instruction. Here is an example of the tricky case:
8645 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8646 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8648 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8650 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8651 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8653 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8654 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8656 // The result is fine to be handled by the generic logic.
8657 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8658 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8659 int AOffset, int BOffset) {
8660 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8661 "Must call this with A having 3 or 1 inputs from the A half.");
8662 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8663 "Must call this with B having 1 or 3 inputs from the B half.");
8664 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8665 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8667 bool ThreeAInputs = AToAInputs.size() == 3;
8669 // Compute the index of dword with only one word among the three inputs in
8670 // a half by taking the sum of the half with three inputs and subtracting
8671 // the sum of the actual three inputs. The difference is the remaining
8674 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8675 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8676 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8677 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8678 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8679 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8680 int TripleNonInputIdx =
8681 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8682 TripleDWord = TripleNonInputIdx / 2;
8684 // We use xor with one to compute the adjacent DWord to whichever one the
8686 OneInputDWord = (OneInput / 2) ^ 1;
8688 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8689 // and BToA inputs. If there is also such a problem with the BToB and AToB
8690 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8691 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8692 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8693 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8694 // Compute how many inputs will be flipped by swapping these DWords. We
8696 // to balance this to ensure we don't form a 3-1 shuffle in the other
8698 int NumFlippedAToBInputs =
8699 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8700 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8701 int NumFlippedBToBInputs =
8702 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8703 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8704 if ((NumFlippedAToBInputs == 1 &&
8705 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8706 (NumFlippedBToBInputs == 1 &&
8707 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8708 // We choose whether to fix the A half or B half based on whether that
8709 // half has zero flipped inputs. At zero, we may not be able to fix it
8710 // with that half. We also bias towards fixing the B half because that
8711 // will more commonly be the high half, and we have to bias one way.
8712 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8713 ArrayRef<int> Inputs) {
8714 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8715 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8716 PinnedIdx ^ 1) != Inputs.end();
8717 // Determine whether the free index is in the flipped dword or the
8718 // unflipped dword based on where the pinned index is. We use this bit
8719 // in an xor to conditionally select the adjacent dword.
8720 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8721 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8722 FixFreeIdx) != Inputs.end();
8723 if (IsFixIdxInput == IsFixFreeIdxInput)
8725 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8726 FixFreeIdx) != Inputs.end();
8727 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8728 "We need to be changing the number of flipped inputs!");
8729 int PSHUFHalfMask[] = {0, 1, 2, 3};
8730 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8731 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8733 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8736 if (M != -1 && M == FixIdx)
8738 else if (M != -1 && M == FixFreeIdx)
8741 if (NumFlippedBToBInputs != 0) {
8743 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8744 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8746 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8747 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8748 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8753 int PSHUFDMask[] = {0, 1, 2, 3};
8754 PSHUFDMask[ADWord] = BDWord;
8755 PSHUFDMask[BDWord] = ADWord;
8758 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8759 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8761 // Adjust the mask to match the new locations of A and B.
8763 if (M != -1 && M/2 == ADWord)
8764 M = 2 * BDWord + M % 2;
8765 else if (M != -1 && M/2 == BDWord)
8766 M = 2 * ADWord + M % 2;
8768 // Recurse back into this routine to re-compute state now that this isn't
8769 // a 3 and 1 problem.
8770 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8773 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8774 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8775 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8776 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8778 // At this point there are at most two inputs to the low and high halves from
8779 // each half. That means the inputs can always be grouped into dwords and
8780 // those dwords can then be moved to the correct half with a dword shuffle.
8781 // We use at most one low and one high word shuffle to collect these paired
8782 // inputs into dwords, and finally a dword shuffle to place them.
8783 int PSHUFLMask[4] = {-1, -1, -1, -1};
8784 int PSHUFHMask[4] = {-1, -1, -1, -1};
8785 int PSHUFDMask[4] = {-1, -1, -1, -1};
8787 // First fix the masks for all the inputs that are staying in their
8788 // original halves. This will then dictate the targets of the cross-half
8790 auto fixInPlaceInputs =
8791 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8792 MutableArrayRef<int> SourceHalfMask,
8793 MutableArrayRef<int> HalfMask, int HalfOffset) {
8794 if (InPlaceInputs.empty())
8796 if (InPlaceInputs.size() == 1) {
8797 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8798 InPlaceInputs[0] - HalfOffset;
8799 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8802 if (IncomingInputs.empty()) {
8803 // Just fix all of the in place inputs.
8804 for (int Input : InPlaceInputs) {
8805 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8806 PSHUFDMask[Input / 2] = Input / 2;
8811 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8812 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8813 InPlaceInputs[0] - HalfOffset;
8814 // Put the second input next to the first so that they are packed into
8815 // a dword. We find the adjacent index by toggling the low bit.
8816 int AdjIndex = InPlaceInputs[0] ^ 1;
8817 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8818 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8819 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8821 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8822 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8824 // Now gather the cross-half inputs and place them into a free dword of
8825 // their target half.
8826 // FIXME: This operation could almost certainly be simplified dramatically to
8827 // look more like the 3-1 fixing operation.
8828 auto moveInputsToRightHalf = [&PSHUFDMask](
8829 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8830 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8831 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8833 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8834 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8836 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8838 int LowWord = Word & ~1;
8839 int HighWord = Word | 1;
8840 return isWordClobbered(SourceHalfMask, LowWord) ||
8841 isWordClobbered(SourceHalfMask, HighWord);
8844 if (IncomingInputs.empty())
8847 if (ExistingInputs.empty()) {
8848 // Map any dwords with inputs from them into the right half.
8849 for (int Input : IncomingInputs) {
8850 // If the source half mask maps over the inputs, turn those into
8851 // swaps and use the swapped lane.
8852 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8853 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8854 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8855 Input - SourceOffset;
8856 // We have to swap the uses in our half mask in one sweep.
8857 for (int &M : HalfMask)
8858 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8860 else if (M == Input)
8861 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8863 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8864 Input - SourceOffset &&
8865 "Previous placement doesn't match!");
8867 // Note that this correctly re-maps both when we do a swap and when
8868 // we observe the other side of the swap above. We rely on that to
8869 // avoid swapping the members of the input list directly.
8870 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8873 // Map the input's dword into the correct half.
8874 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8875 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8877 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8879 "Previous placement doesn't match!");
8882 // And just directly shift any other-half mask elements to be same-half
8883 // as we will have mirrored the dword containing the element into the
8884 // same position within that half.
8885 for (int &M : HalfMask)
8886 if (M >= SourceOffset && M < SourceOffset + 4) {
8887 M = M - SourceOffset + DestOffset;
8888 assert(M >= 0 && "This should never wrap below zero!");
8893 // Ensure we have the input in a viable dword of its current half. This
8894 // is particularly tricky because the original position may be clobbered
8895 // by inputs being moved and *staying* in that half.
8896 if (IncomingInputs.size() == 1) {
8897 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8898 int InputFixed = std::find(std::begin(SourceHalfMask),
8899 std::end(SourceHalfMask), -1) -
8900 std::begin(SourceHalfMask) + SourceOffset;
8901 SourceHalfMask[InputFixed - SourceOffset] =
8902 IncomingInputs[0] - SourceOffset;
8903 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8905 IncomingInputs[0] = InputFixed;
8907 } else if (IncomingInputs.size() == 2) {
8908 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8909 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8910 // We have two non-adjacent or clobbered inputs we need to extract from
8911 // the source half. To do this, we need to map them into some adjacent
8912 // dword slot in the source mask.
8913 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8914 IncomingInputs[1] - SourceOffset};
8916 // If there is a free slot in the source half mask adjacent to one of
8917 // the inputs, place the other input in it. We use (Index XOR 1) to
8918 // compute an adjacent index.
8919 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8920 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8921 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8922 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8923 InputsFixed[1] = InputsFixed[0] ^ 1;
8924 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8925 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8926 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8927 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8928 InputsFixed[0] = InputsFixed[1] ^ 1;
8929 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8930 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8931 // The two inputs are in the same DWord but it is clobbered and the
8932 // adjacent DWord isn't used at all. Move both inputs to the free
8934 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8935 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8936 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8937 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8939 // The only way we hit this point is if there is no clobbering
8940 // (because there are no off-half inputs to this half) and there is no
8941 // free slot adjacent to one of the inputs. In this case, we have to
8942 // swap an input with a non-input.
8943 for (int i = 0; i < 4; ++i)
8944 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8945 "We can't handle any clobbers here!");
8946 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8947 "Cannot have adjacent inputs here!");
8949 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8950 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8952 // We also have to update the final source mask in this case because
8953 // it may need to undo the above swap.
8954 for (int &M : FinalSourceHalfMask)
8955 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8956 M = InputsFixed[1] + SourceOffset;
8957 else if (M == InputsFixed[1] + SourceOffset)
8958 M = (InputsFixed[0] ^ 1) + SourceOffset;
8960 InputsFixed[1] = InputsFixed[0] ^ 1;
8963 // Point everything at the fixed inputs.
8964 for (int &M : HalfMask)
8965 if (M == IncomingInputs[0])
8966 M = InputsFixed[0] + SourceOffset;
8967 else if (M == IncomingInputs[1])
8968 M = InputsFixed[1] + SourceOffset;
8970 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8971 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8974 llvm_unreachable("Unhandled input size!");
8977 // Now hoist the DWord down to the right half.
8978 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8979 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8980 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8981 for (int &M : HalfMask)
8982 for (int Input : IncomingInputs)
8984 M = FreeDWord * 2 + Input % 2;
8986 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8987 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8988 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8989 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8991 // Now enact all the shuffles we've computed to move the inputs into their
8993 if (!isNoopShuffleMask(PSHUFLMask))
8994 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8995 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8996 if (!isNoopShuffleMask(PSHUFHMask))
8997 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8998 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8999 if (!isNoopShuffleMask(PSHUFDMask))
9002 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9003 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9005 // At this point, each half should contain all its inputs, and we can then
9006 // just shuffle them into their final position.
9007 assert(std::count_if(LoMask.begin(), LoMask.end(),
9008 [](int M) { return M >= 4; }) == 0 &&
9009 "Failed to lift all the high half inputs to the low mask!");
9010 assert(std::count_if(HiMask.begin(), HiMask.end(),
9011 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9012 "Failed to lift all the low half inputs to the high mask!");
9014 // Do a half shuffle for the low mask.
9015 if (!isNoopShuffleMask(LoMask))
9016 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9017 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9019 // Do a half shuffle with the high mask after shifting its values down.
9020 for (int &M : HiMask)
9023 if (!isNoopShuffleMask(HiMask))
9024 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9025 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9030 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9031 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9032 SDValue V2, ArrayRef<int> Mask,
9033 SelectionDAG &DAG, bool &V1InUse,
9035 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9041 int Size = Mask.size();
9042 int Scale = 16 / Size;
9043 for (int i = 0; i < 16; ++i) {
9044 if (Mask[i / Scale] == -1) {
9045 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9047 const int ZeroMask = 0x80;
9048 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9050 int V2Idx = Mask[i / Scale] < Size
9052 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9053 if (Zeroable[i / Scale])
9054 V1Idx = V2Idx = ZeroMask;
9055 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9056 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9057 V1InUse |= (ZeroMask != V1Idx);
9058 V2InUse |= (ZeroMask != V2Idx);
9063 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9064 DAG.getBitcast(MVT::v16i8, V1),
9065 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9067 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9068 DAG.getBitcast(MVT::v16i8, V2),
9069 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9071 // If we need shuffled inputs from both, blend the two.
9073 if (V1InUse && V2InUse)
9074 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9076 V = V1InUse ? V1 : V2;
9078 // Cast the result back to the correct type.
9079 return DAG.getBitcast(VT, V);
9082 /// \brief Generic lowering of 8-lane i16 shuffles.
9084 /// This handles both single-input shuffles and combined shuffle/blends with
9085 /// two inputs. The single input shuffles are immediately delegated to
9086 /// a dedicated lowering routine.
9088 /// The blends are lowered in one of three fundamental ways. If there are few
9089 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9090 /// of the input is significantly cheaper when lowered as an interleaving of
9091 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9092 /// halves of the inputs separately (making them have relatively few inputs)
9093 /// and then concatenate them.
9094 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9095 const X86Subtarget *Subtarget,
9096 SelectionDAG &DAG) {
9098 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9099 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9100 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9101 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9102 ArrayRef<int> OrigMask = SVOp->getMask();
9103 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9104 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9105 MutableArrayRef<int> Mask(MaskStorage);
9107 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9109 // Whenever we can lower this as a zext, that instruction is strictly faster
9110 // than any alternative.
9111 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9112 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9115 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9117 auto isV2 = [](int M) { return M >= 8; };
9119 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9121 if (NumV2Inputs == 0) {
9122 // Check for being able to broadcast a single element.
9123 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9124 Mask, Subtarget, DAG))
9127 // Try to use shift instructions.
9129 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9132 // Use dedicated unpack instructions for masks that match their pattern.
9133 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9134 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9135 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9136 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9138 // Try to use byte rotation instructions.
9139 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9140 Mask, Subtarget, DAG))
9143 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9147 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9148 "All single-input shuffles should be canonicalized to be V1-input "
9151 // Try to use shift instructions.
9153 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9156 // See if we can use SSE4A Extraction / Insertion.
9157 if (Subtarget->hasSSE4A())
9158 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9161 // There are special ways we can lower some single-element blends.
9162 if (NumV2Inputs == 1)
9163 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9164 Mask, Subtarget, DAG))
9167 // We have different paths for blend lowering, but they all must use the
9168 // *exact* same predicate.
9169 bool IsBlendSupported = Subtarget->hasSSE41();
9170 if (IsBlendSupported)
9171 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9175 if (SDValue Masked =
9176 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9179 // Use dedicated unpack instructions for masks that match their pattern.
9180 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9181 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9182 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9183 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9185 // Try to use byte rotation instructions.
9186 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9187 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9190 if (SDValue BitBlend =
9191 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9194 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9198 // If we can't directly blend but can use PSHUFB, that will be better as it
9199 // can both shuffle and set up the inefficient blend.
9200 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9201 bool V1InUse, V2InUse;
9202 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9206 // We can always bit-blend if we have to so the fallback strategy is to
9207 // decompose into single-input permutes and blends.
9208 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9212 /// \brief Check whether a compaction lowering can be done by dropping even
9213 /// elements and compute how many times even elements must be dropped.
9215 /// This handles shuffles which take every Nth element where N is a power of
9216 /// two. Example shuffle masks:
9218 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9219 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9220 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9221 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9222 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9223 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9225 /// Any of these lanes can of course be undef.
9227 /// This routine only supports N <= 3.
9228 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9231 /// \returns N above, or the number of times even elements must be dropped if
9232 /// there is such a number. Otherwise returns zero.
9233 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9234 // Figure out whether we're looping over two inputs or just one.
9235 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9237 // The modulus for the shuffle vector entries is based on whether this is
9238 // a single input or not.
9239 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9240 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9241 "We should only be called with masks with a power-of-2 size!");
9243 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9245 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9246 // and 2^3 simultaneously. This is because we may have ambiguity with
9247 // partially undef inputs.
9248 bool ViableForN[3] = {true, true, true};
9250 for (int i = 0, e = Mask.size(); i < e; ++i) {
9251 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9256 bool IsAnyViable = false;
9257 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9258 if (ViableForN[j]) {
9261 // The shuffle mask must be equal to (i * 2^N) % M.
9262 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9265 ViableForN[j] = false;
9267 // Early exit if we exhaust the possible powers of two.
9272 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9276 // Return 0 as there is no viable power of two.
9280 /// \brief Generic lowering of v16i8 shuffles.
9282 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9283 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9284 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9285 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9287 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9288 const X86Subtarget *Subtarget,
9289 SelectionDAG &DAG) {
9291 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9292 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9293 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9294 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9295 ArrayRef<int> Mask = SVOp->getMask();
9296 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9298 // Try to use shift instructions.
9300 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9303 // Try to use byte rotation instructions.
9304 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9305 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9308 // Try to use a zext lowering.
9309 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9310 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9313 // See if we can use SSE4A Extraction / Insertion.
9314 if (Subtarget->hasSSE4A())
9315 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9319 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9321 // For single-input shuffles, there are some nicer lowering tricks we can use.
9322 if (NumV2Elements == 0) {
9323 // Check for being able to broadcast a single element.
9324 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9325 Mask, Subtarget, DAG))
9328 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9329 // Notably, this handles splat and partial-splat shuffles more efficiently.
9330 // However, it only makes sense if the pre-duplication shuffle simplifies
9331 // things significantly. Currently, this means we need to be able to
9332 // express the pre-duplication shuffle as an i16 shuffle.
9334 // FIXME: We should check for other patterns which can be widened into an
9335 // i16 shuffle as well.
9336 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9337 for (int i = 0; i < 16; i += 2)
9338 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9343 auto tryToWidenViaDuplication = [&]() -> SDValue {
9344 if (!canWidenViaDuplication(Mask))
9346 SmallVector<int, 4> LoInputs;
9347 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9348 [](int M) { return M >= 0 && M < 8; });
9349 std::sort(LoInputs.begin(), LoInputs.end());
9350 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9352 SmallVector<int, 4> HiInputs;
9353 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9354 [](int M) { return M >= 8; });
9355 std::sort(HiInputs.begin(), HiInputs.end());
9356 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9359 bool TargetLo = LoInputs.size() >= HiInputs.size();
9360 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9361 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9363 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9364 SmallDenseMap<int, int, 8> LaneMap;
9365 for (int I : InPlaceInputs) {
9366 PreDupI16Shuffle[I/2] = I/2;
9369 int j = TargetLo ? 0 : 4, je = j + 4;
9370 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9371 // Check if j is already a shuffle of this input. This happens when
9372 // there are two adjacent bytes after we move the low one.
9373 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9374 // If we haven't yet mapped the input, search for a slot into which
9376 while (j < je && PreDupI16Shuffle[j] != -1)
9380 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9383 // Map this input with the i16 shuffle.
9384 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9387 // Update the lane map based on the mapping we ended up with.
9388 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9390 V1 = DAG.getBitcast(
9392 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9393 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9395 // Unpack the bytes to form the i16s that will be shuffled into place.
9396 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9397 MVT::v16i8, V1, V1);
9399 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9400 for (int i = 0; i < 16; ++i)
9401 if (Mask[i] != -1) {
9402 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9403 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9404 if (PostDupI16Shuffle[i / 2] == -1)
9405 PostDupI16Shuffle[i / 2] = MappedMask;
9407 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9408 "Conflicting entrties in the original shuffle!");
9410 return DAG.getBitcast(
9412 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9413 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9415 if (SDValue V = tryToWidenViaDuplication())
9419 if (SDValue Masked =
9420 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9423 // Use dedicated unpack instructions for masks that match their pattern.
9424 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9425 0, 16, 1, 17, 2, 18, 3, 19,
9427 4, 20, 5, 21, 6, 22, 7, 23}))
9428 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9429 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9430 8, 24, 9, 25, 10, 26, 11, 27,
9432 12, 28, 13, 29, 14, 30, 15, 31}))
9433 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9435 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9436 // with PSHUFB. It is important to do this before we attempt to generate any
9437 // blends but after all of the single-input lowerings. If the single input
9438 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9439 // want to preserve that and we can DAG combine any longer sequences into
9440 // a PSHUFB in the end. But once we start blending from multiple inputs,
9441 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9442 // and there are *very* few patterns that would actually be faster than the
9443 // PSHUFB approach because of its ability to zero lanes.
9445 // FIXME: The only exceptions to the above are blends which are exact
9446 // interleavings with direct instructions supporting them. We currently don't
9447 // handle those well here.
9448 if (Subtarget->hasSSSE3()) {
9449 bool V1InUse = false;
9450 bool V2InUse = false;
9452 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9453 DAG, V1InUse, V2InUse);
9455 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9456 // do so. This avoids using them to handle blends-with-zero which is
9457 // important as a single pshufb is significantly faster for that.
9458 if (V1InUse && V2InUse) {
9459 if (Subtarget->hasSSE41())
9460 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9461 Mask, Subtarget, DAG))
9464 // We can use an unpack to do the blending rather than an or in some
9465 // cases. Even though the or may be (very minorly) more efficient, we
9466 // preference this lowering because there are common cases where part of
9467 // the complexity of the shuffles goes away when we do the final blend as
9469 // FIXME: It might be worth trying to detect if the unpack-feeding
9470 // shuffles will both be pshufb, in which case we shouldn't bother with
9472 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9473 DL, MVT::v16i8, V1, V2, Mask, DAG))
9480 // There are special ways we can lower some single-element blends.
9481 if (NumV2Elements == 1)
9482 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9483 Mask, Subtarget, DAG))
9486 if (SDValue BitBlend =
9487 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9490 // Check whether a compaction lowering can be done. This handles shuffles
9491 // which take every Nth element for some even N. See the helper function for
9494 // We special case these as they can be particularly efficiently handled with
9495 // the PACKUSB instruction on x86 and they show up in common patterns of
9496 // rearranging bytes to truncate wide elements.
9497 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9498 // NumEvenDrops is the power of two stride of the elements. Another way of
9499 // thinking about it is that we need to drop the even elements this many
9500 // times to get the original input.
9501 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9503 // First we need to zero all the dropped bytes.
9504 assert(NumEvenDrops <= 3 &&
9505 "No support for dropping even elements more than 3 times.");
9506 // We use the mask type to pick which bytes are preserved based on how many
9507 // elements are dropped.
9508 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9509 SDValue ByteClearMask = DAG.getBitcast(
9510 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9511 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9513 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9515 // Now pack things back together.
9516 V1 = DAG.getBitcast(MVT::v8i16, V1);
9517 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9518 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9519 for (int i = 1; i < NumEvenDrops; ++i) {
9520 Result = DAG.getBitcast(MVT::v8i16, Result);
9521 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9527 // Handle multi-input cases by blending single-input shuffles.
9528 if (NumV2Elements > 0)
9529 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9532 // The fallback path for single-input shuffles widens this into two v8i16
9533 // vectors with unpacks, shuffles those, and then pulls them back together
9537 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9538 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9539 for (int i = 0; i < 16; ++i)
9541 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9543 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9545 SDValue VLoHalf, VHiHalf;
9546 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9547 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9549 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9550 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9551 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9552 [](int M) { return M >= 0 && M % 2 == 1; })) {
9553 // Use a mask to drop the high bytes.
9554 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9555 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9556 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9558 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9559 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9561 // Squash the masks to point directly into VLoHalf.
9562 for (int &M : LoBlendMask)
9565 for (int &M : HiBlendMask)
9569 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9570 // VHiHalf so that we can blend them as i16s.
9571 VLoHalf = DAG.getBitcast(
9572 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9573 VHiHalf = DAG.getBitcast(
9574 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9577 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9578 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9580 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9583 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9585 /// This routine breaks down the specific type of 128-bit shuffle and
9586 /// dispatches to the lowering routines accordingly.
9587 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9588 MVT VT, const X86Subtarget *Subtarget,
9589 SelectionDAG &DAG) {
9590 switch (VT.SimpleTy) {
9592 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9594 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9596 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9598 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9600 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9602 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9605 llvm_unreachable("Unimplemented!");
9609 /// \brief Helper function to test whether a shuffle mask could be
9610 /// simplified by widening the elements being shuffled.
9612 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9613 /// leaves it in an unspecified state.
9615 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9616 /// shuffle masks. The latter have the special property of a '-2' representing
9617 /// a zero-ed lane of a vector.
9618 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9619 SmallVectorImpl<int> &WidenedMask) {
9620 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9621 // If both elements are undef, its trivial.
9622 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9623 WidenedMask.push_back(SM_SentinelUndef);
9627 // Check for an undef mask and a mask value properly aligned to fit with
9628 // a pair of values. If we find such a case, use the non-undef mask's value.
9629 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9630 WidenedMask.push_back(Mask[i + 1] / 2);
9633 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9634 WidenedMask.push_back(Mask[i] / 2);
9638 // When zeroing, we need to spread the zeroing across both lanes to widen.
9639 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9640 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9641 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9642 WidenedMask.push_back(SM_SentinelZero);
9648 // Finally check if the two mask values are adjacent and aligned with
9650 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9651 WidenedMask.push_back(Mask[i] / 2);
9655 // Otherwise we can't safely widen the elements used in this shuffle.
9658 assert(WidenedMask.size() == Mask.size() / 2 &&
9659 "Incorrect size of mask after widening the elements!");
9664 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9666 /// This routine just extracts two subvectors, shuffles them independently, and
9667 /// then concatenates them back together. This should work effectively with all
9668 /// AVX vector shuffle types.
9669 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9670 SDValue V2, ArrayRef<int> Mask,
9671 SelectionDAG &DAG) {
9672 assert(VT.getSizeInBits() >= 256 &&
9673 "Only for 256-bit or wider vector shuffles!");
9674 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9675 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9677 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9678 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9680 int NumElements = VT.getVectorNumElements();
9681 int SplitNumElements = NumElements / 2;
9682 MVT ScalarVT = VT.getScalarType();
9683 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9685 // Rather than splitting build-vectors, just build two narrower build
9686 // vectors. This helps shuffling with splats and zeros.
9687 auto SplitVector = [&](SDValue V) {
9688 while (V.getOpcode() == ISD::BITCAST)
9689 V = V->getOperand(0);
9691 MVT OrigVT = V.getSimpleValueType();
9692 int OrigNumElements = OrigVT.getVectorNumElements();
9693 int OrigSplitNumElements = OrigNumElements / 2;
9694 MVT OrigScalarVT = OrigVT.getScalarType();
9695 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9699 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9701 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9702 DAG.getIntPtrConstant(0, DL));
9703 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9704 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9707 SmallVector<SDValue, 16> LoOps, HiOps;
9708 for (int i = 0; i < OrigSplitNumElements; ++i) {
9709 LoOps.push_back(BV->getOperand(i));
9710 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9712 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9713 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9715 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9716 DAG.getBitcast(SplitVT, HiV));
9719 SDValue LoV1, HiV1, LoV2, HiV2;
9720 std::tie(LoV1, HiV1) = SplitVector(V1);
9721 std::tie(LoV2, HiV2) = SplitVector(V2);
9723 // Now create two 4-way blends of these half-width vectors.
9724 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9725 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9726 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9727 for (int i = 0; i < SplitNumElements; ++i) {
9728 int M = HalfMask[i];
9729 if (M >= NumElements) {
9730 if (M >= NumElements + SplitNumElements)
9734 V2BlendMask.push_back(M - NumElements);
9735 V1BlendMask.push_back(-1);
9736 BlendMask.push_back(SplitNumElements + i);
9737 } else if (M >= 0) {
9738 if (M >= SplitNumElements)
9742 V2BlendMask.push_back(-1);
9743 V1BlendMask.push_back(M);
9744 BlendMask.push_back(i);
9746 V2BlendMask.push_back(-1);
9747 V1BlendMask.push_back(-1);
9748 BlendMask.push_back(-1);
9752 // Because the lowering happens after all combining takes place, we need to
9753 // manually combine these blend masks as much as possible so that we create
9754 // a minimal number of high-level vector shuffle nodes.
9756 // First try just blending the halves of V1 or V2.
9757 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9758 return DAG.getUNDEF(SplitVT);
9759 if (!UseLoV2 && !UseHiV2)
9760 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9761 if (!UseLoV1 && !UseHiV1)
9762 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9764 SDValue V1Blend, V2Blend;
9765 if (UseLoV1 && UseHiV1) {
9767 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9769 // We only use half of V1 so map the usage down into the final blend mask.
9770 V1Blend = UseLoV1 ? LoV1 : HiV1;
9771 for (int i = 0; i < SplitNumElements; ++i)
9772 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9773 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9775 if (UseLoV2 && UseHiV2) {
9777 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9779 // We only use half of V2 so map the usage down into the final blend mask.
9780 V2Blend = UseLoV2 ? LoV2 : HiV2;
9781 for (int i = 0; i < SplitNumElements; ++i)
9782 if (BlendMask[i] >= SplitNumElements)
9783 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9785 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9787 SDValue Lo = HalfBlend(LoMask);
9788 SDValue Hi = HalfBlend(HiMask);
9789 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9792 /// \brief Either split a vector in halves or decompose the shuffles and the
9795 /// This is provided as a good fallback for many lowerings of non-single-input
9796 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9797 /// between splitting the shuffle into 128-bit components and stitching those
9798 /// back together vs. extracting the single-input shuffles and blending those
9800 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9801 SDValue V2, ArrayRef<int> Mask,
9802 SelectionDAG &DAG) {
9803 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9804 "lower single-input shuffles as it "
9805 "could then recurse on itself.");
9806 int Size = Mask.size();
9808 // If this can be modeled as a broadcast of two elements followed by a blend,
9809 // prefer that lowering. This is especially important because broadcasts can
9810 // often fold with memory operands.
9811 auto DoBothBroadcast = [&] {
9812 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9815 if (V2BroadcastIdx == -1)
9816 V2BroadcastIdx = M - Size;
9817 else if (M - Size != V2BroadcastIdx)
9819 } else if (M >= 0) {
9820 if (V1BroadcastIdx == -1)
9822 else if (M != V1BroadcastIdx)
9827 if (DoBothBroadcast())
9828 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9831 // If the inputs all stem from a single 128-bit lane of each input, then we
9832 // split them rather than blending because the split will decompose to
9833 // unusually few instructions.
9834 int LaneCount = VT.getSizeInBits() / 128;
9835 int LaneSize = Size / LaneCount;
9836 SmallBitVector LaneInputs[2];
9837 LaneInputs[0].resize(LaneCount, false);
9838 LaneInputs[1].resize(LaneCount, false);
9839 for (int i = 0; i < Size; ++i)
9841 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9842 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9843 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9845 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9846 // that the decomposed single-input shuffles don't end up here.
9847 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9850 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9851 /// a permutation and blend of those lanes.
9853 /// This essentially blends the out-of-lane inputs to each lane into the lane
9854 /// from a permuted copy of the vector. This lowering strategy results in four
9855 /// instructions in the worst case for a single-input cross lane shuffle which
9856 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9857 /// of. Special cases for each particular shuffle pattern should be handled
9858 /// prior to trying this lowering.
9859 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9860 SDValue V1, SDValue V2,
9862 SelectionDAG &DAG) {
9863 // FIXME: This should probably be generalized for 512-bit vectors as well.
9864 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9865 int LaneSize = Mask.size() / 2;
9867 // If there are only inputs from one 128-bit lane, splitting will in fact be
9868 // less expensive. The flags track whether the given lane contains an element
9869 // that crosses to another lane.
9870 bool LaneCrossing[2] = {false, false};
9871 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9872 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9873 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9874 if (!LaneCrossing[0] || !LaneCrossing[1])
9875 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9877 if (isSingleInputShuffleMask(Mask)) {
9878 SmallVector<int, 32> FlippedBlendMask;
9879 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9880 FlippedBlendMask.push_back(
9881 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9883 : Mask[i] % LaneSize +
9884 (i / LaneSize) * LaneSize + Size));
9886 // Flip the vector, and blend the results which should now be in-lane. The
9887 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9888 // 5 for the high source. The value 3 selects the high half of source 2 and
9889 // the value 2 selects the low half of source 2. We only use source 2 to
9890 // allow folding it into a memory operand.
9891 unsigned PERMMask = 3 | 2 << 4;
9892 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9893 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9894 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9897 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9898 // will be handled by the above logic and a blend of the results, much like
9899 // other patterns in AVX.
9900 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9903 /// \brief Handle lowering 2-lane 128-bit shuffles.
9904 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9905 SDValue V2, ArrayRef<int> Mask,
9906 const X86Subtarget *Subtarget,
9907 SelectionDAG &DAG) {
9908 // TODO: If minimizing size and one of the inputs is a zero vector and the
9909 // the zero vector has only one use, we could use a VPERM2X128 to save the
9910 // instruction bytes needed to explicitly generate the zero vector.
9912 // Blends are faster and handle all the non-lane-crossing cases.
9913 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9917 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9918 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9920 // If either input operand is a zero vector, use VPERM2X128 because its mask
9921 // allows us to replace the zero input with an implicit zero.
9922 if (!IsV1Zero && !IsV2Zero) {
9923 // Check for patterns which can be matched with a single insert of a 128-bit
9925 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9926 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9927 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9928 VT.getVectorNumElements() / 2);
9929 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9930 DAG.getIntPtrConstant(0, DL));
9931 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9932 OnlyUsesV1 ? V1 : V2,
9933 DAG.getIntPtrConstant(0, DL));
9934 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9938 // Otherwise form a 128-bit permutation. After accounting for undefs,
9939 // convert the 64-bit shuffle mask selection values into 128-bit
9940 // selection bits by dividing the indexes by 2 and shifting into positions
9941 // defined by a vperm2*128 instruction's immediate control byte.
9943 // The immediate permute control byte looks like this:
9944 // [1:0] - select 128 bits from sources for low half of destination
9946 // [3] - zero low half of destination
9947 // [5:4] - select 128 bits from sources for high half of destination
9949 // [7] - zero high half of destination
9951 int MaskLO = Mask[0];
9952 if (MaskLO == SM_SentinelUndef)
9953 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9955 int MaskHI = Mask[2];
9956 if (MaskHI == SM_SentinelUndef)
9957 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9959 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9961 // If either input is a zero vector, replace it with an undef input.
9962 // Shuffle mask values < 4 are selecting elements of V1.
9963 // Shuffle mask values >= 4 are selecting elements of V2.
9964 // Adjust each half of the permute mask by clearing the half that was
9965 // selecting the zero vector and setting the zero mask bit.
9967 V1 = DAG.getUNDEF(VT);
9969 PermMask = (PermMask & 0xf0) | 0x08;
9971 PermMask = (PermMask & 0x0f) | 0x80;
9974 V2 = DAG.getUNDEF(VT);
9976 PermMask = (PermMask & 0xf0) | 0x08;
9978 PermMask = (PermMask & 0x0f) | 0x80;
9981 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9982 DAG.getConstant(PermMask, DL, MVT::i8));
9985 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9986 /// shuffling each lane.
9988 /// This will only succeed when the result of fixing the 128-bit lanes results
9989 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9990 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9991 /// the lane crosses early and then use simpler shuffles within each lane.
9993 /// FIXME: It might be worthwhile at some point to support this without
9994 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9995 /// in x86 only floating point has interesting non-repeating shuffles, and even
9996 /// those are still *marginally* more expensive.
9997 static SDValue lowerVectorShuffleByMerging128BitLanes(
9998 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9999 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10000 assert(!isSingleInputShuffleMask(Mask) &&
10001 "This is only useful with multiple inputs.");
10003 int Size = Mask.size();
10004 int LaneSize = 128 / VT.getScalarSizeInBits();
10005 int NumLanes = Size / LaneSize;
10006 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10008 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10009 // check whether the in-128-bit lane shuffles share a repeating pattern.
10010 SmallVector<int, 4> Lanes;
10011 Lanes.resize(NumLanes, -1);
10012 SmallVector<int, 4> InLaneMask;
10013 InLaneMask.resize(LaneSize, -1);
10014 for (int i = 0; i < Size; ++i) {
10018 int j = i / LaneSize;
10020 if (Lanes[j] < 0) {
10021 // First entry we've seen for this lane.
10022 Lanes[j] = Mask[i] / LaneSize;
10023 } else if (Lanes[j] != Mask[i] / LaneSize) {
10024 // This doesn't match the lane selected previously!
10028 // Check that within each lane we have a consistent shuffle mask.
10029 int k = i % LaneSize;
10030 if (InLaneMask[k] < 0) {
10031 InLaneMask[k] = Mask[i] % LaneSize;
10032 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10033 // This doesn't fit a repeating in-lane mask.
10038 // First shuffle the lanes into place.
10039 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10040 VT.getSizeInBits() / 64);
10041 SmallVector<int, 8> LaneMask;
10042 LaneMask.resize(NumLanes * 2, -1);
10043 for (int i = 0; i < NumLanes; ++i)
10044 if (Lanes[i] >= 0) {
10045 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10046 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10049 V1 = DAG.getBitcast(LaneVT, V1);
10050 V2 = DAG.getBitcast(LaneVT, V2);
10051 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10053 // Cast it back to the type we actually want.
10054 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10056 // Now do a simple shuffle that isn't lane crossing.
10057 SmallVector<int, 8> NewMask;
10058 NewMask.resize(Size, -1);
10059 for (int i = 0; i < Size; ++i)
10061 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10062 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10063 "Must not introduce lane crosses at this point!");
10065 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10068 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10071 /// This returns true if the elements from a particular input are already in the
10072 /// slot required by the given mask and require no permutation.
10073 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10074 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10075 int Size = Mask.size();
10076 for (int i = 0; i < Size; ++i)
10077 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10083 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10084 ArrayRef<int> Mask, SDValue V1,
10085 SDValue V2, SelectionDAG &DAG) {
10087 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10088 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10089 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10090 int NumElts = VT.getVectorNumElements();
10091 bool ShufpdMask = true;
10092 bool CommutableMask = true;
10093 unsigned Immediate = 0;
10094 for (int i = 0; i < NumElts; ++i) {
10097 int Val = (i & 6) + NumElts * (i & 1);
10098 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10099 if (Mask[i] < Val || Mask[i] > Val + 1)
10100 ShufpdMask = false;
10101 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10102 CommutableMask = false;
10103 Immediate |= (Mask[i] % 2) << i;
10106 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10107 DAG.getConstant(Immediate, DL, MVT::i8));
10108 if (CommutableMask)
10109 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10110 DAG.getConstant(Immediate, DL, MVT::i8));
10114 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10116 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10117 /// isn't available.
10118 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10119 const X86Subtarget *Subtarget,
10120 SelectionDAG &DAG) {
10122 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10123 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10124 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10125 ArrayRef<int> Mask = SVOp->getMask();
10126 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10128 SmallVector<int, 4> WidenedMask;
10129 if (canWidenShuffleElements(Mask, WidenedMask))
10130 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10133 if (isSingleInputShuffleMask(Mask)) {
10134 // Check for being able to broadcast a single element.
10135 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10136 Mask, Subtarget, DAG))
10139 // Use low duplicate instructions for masks that match their pattern.
10140 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10141 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10143 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10144 // Non-half-crossing single input shuffles can be lowerid with an
10145 // interleaved permutation.
10146 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10147 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10148 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10149 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10152 // With AVX2 we have direct support for this permutation.
10153 if (Subtarget->hasAVX2())
10154 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10155 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10157 // Otherwise, fall back.
10158 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10162 // X86 has dedicated unpack instructions that can handle specific blend
10163 // operations: UNPCKH and UNPCKL.
10164 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10165 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10166 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10167 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10168 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10169 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10170 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10171 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10173 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10177 // Check if the blend happens to exactly fit that of SHUFPD.
10179 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10182 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10183 // shuffle. However, if we have AVX2 and either inputs are already in place,
10184 // we will be able to shuffle even across lanes the other input in a single
10185 // instruction so skip this pattern.
10186 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10187 isShuffleMaskInputInPlace(1, Mask))))
10188 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10189 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10192 // If we have AVX2 then we always want to lower with a blend because an v4 we
10193 // can fully permute the elements.
10194 if (Subtarget->hasAVX2())
10195 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10198 // Otherwise fall back on generic lowering.
10199 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10202 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10204 /// This routine is only called when we have AVX2 and thus a reasonable
10205 /// instruction set for v4i64 shuffling..
10206 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10207 const X86Subtarget *Subtarget,
10208 SelectionDAG &DAG) {
10210 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10211 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10212 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10213 ArrayRef<int> Mask = SVOp->getMask();
10214 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10215 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10217 SmallVector<int, 4> WidenedMask;
10218 if (canWidenShuffleElements(Mask, WidenedMask))
10219 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10222 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10226 // Check for being able to broadcast a single element.
10227 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10228 Mask, Subtarget, DAG))
10231 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10232 // use lower latency instructions that will operate on both 128-bit lanes.
10233 SmallVector<int, 2> RepeatedMask;
10234 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10235 if (isSingleInputShuffleMask(Mask)) {
10236 int PSHUFDMask[] = {-1, -1, -1, -1};
10237 for (int i = 0; i < 2; ++i)
10238 if (RepeatedMask[i] >= 0) {
10239 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10240 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10242 return DAG.getBitcast(
10244 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10245 DAG.getBitcast(MVT::v8i32, V1),
10246 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10250 // AVX2 provides a direct instruction for permuting a single input across
10252 if (isSingleInputShuffleMask(Mask))
10253 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10254 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10256 // Try to use shift instructions.
10257 if (SDValue Shift =
10258 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10261 // Use dedicated unpack instructions for masks that match their pattern.
10262 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10263 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10264 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10265 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10266 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10267 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10268 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10269 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10271 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10272 // shuffle. However, if we have AVX2 and either inputs are already in place,
10273 // we will be able to shuffle even across lanes the other input in a single
10274 // instruction so skip this pattern.
10275 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10276 isShuffleMaskInputInPlace(1, Mask))))
10277 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10278 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10281 // Otherwise fall back on generic blend lowering.
10282 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10286 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10288 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10289 /// isn't available.
10290 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10291 const X86Subtarget *Subtarget,
10292 SelectionDAG &DAG) {
10294 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10295 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10296 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10297 ArrayRef<int> Mask = SVOp->getMask();
10298 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10300 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10304 // Check for being able to broadcast a single element.
10305 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10306 Mask, Subtarget, DAG))
10309 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10310 // options to efficiently lower the shuffle.
10311 SmallVector<int, 4> RepeatedMask;
10312 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10313 assert(RepeatedMask.size() == 4 &&
10314 "Repeated masks must be half the mask width!");
10316 // Use even/odd duplicate instructions for masks that match their pattern.
10317 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10318 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10319 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10320 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10322 if (isSingleInputShuffleMask(Mask))
10323 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10324 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10326 // Use dedicated unpack instructions for masks that match their pattern.
10327 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10328 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10329 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10330 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10331 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10332 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10333 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10334 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10336 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10337 // have already handled any direct blends. We also need to squash the
10338 // repeated mask into a simulated v4f32 mask.
10339 for (int i = 0; i < 4; ++i)
10340 if (RepeatedMask[i] >= 8)
10341 RepeatedMask[i] -= 4;
10342 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10345 // If we have a single input shuffle with different shuffle patterns in the
10346 // two 128-bit lanes use the variable mask to VPERMILPS.
10347 if (isSingleInputShuffleMask(Mask)) {
10348 SDValue VPermMask[8];
10349 for (int i = 0; i < 8; ++i)
10350 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10351 : DAG.getConstant(Mask[i], DL, MVT::i32);
10352 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10353 return DAG.getNode(
10354 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10355 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10357 if (Subtarget->hasAVX2())
10358 return DAG.getNode(
10359 X86ISD::VPERMV, DL, MVT::v8f32,
10360 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10361 MVT::v8i32, VPermMask)),
10364 // Otherwise, fall back.
10365 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10369 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10371 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10372 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10375 // If we have AVX2 then we always want to lower with a blend because at v8 we
10376 // can fully permute the elements.
10377 if (Subtarget->hasAVX2())
10378 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10381 // Otherwise fall back on generic lowering.
10382 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10385 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10387 /// This routine is only called when we have AVX2 and thus a reasonable
10388 /// instruction set for v8i32 shuffling..
10389 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10390 const X86Subtarget *Subtarget,
10391 SelectionDAG &DAG) {
10393 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10394 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10395 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10396 ArrayRef<int> Mask = SVOp->getMask();
10397 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10398 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10400 // Whenever we can lower this as a zext, that instruction is strictly faster
10401 // than any alternative. It also allows us to fold memory operands into the
10402 // shuffle in many cases.
10403 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10404 Mask, Subtarget, DAG))
10407 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10411 // Check for being able to broadcast a single element.
10412 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10413 Mask, Subtarget, DAG))
10416 // If the shuffle mask is repeated in each 128-bit lane we can use more
10417 // efficient instructions that mirror the shuffles across the two 128-bit
10419 SmallVector<int, 4> RepeatedMask;
10420 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10421 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10422 if (isSingleInputShuffleMask(Mask))
10423 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10424 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10426 // Use dedicated unpack instructions for masks that match their pattern.
10427 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10428 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10429 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10430 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10431 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10432 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10433 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10434 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10437 // Try to use shift instructions.
10438 if (SDValue Shift =
10439 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10442 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10443 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10446 // If the shuffle patterns aren't repeated but it is a single input, directly
10447 // generate a cross-lane VPERMD instruction.
10448 if (isSingleInputShuffleMask(Mask)) {
10449 SDValue VPermMask[8];
10450 for (int i = 0; i < 8; ++i)
10451 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10452 : DAG.getConstant(Mask[i], DL, MVT::i32);
10453 return DAG.getNode(
10454 X86ISD::VPERMV, DL, MVT::v8i32,
10455 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10458 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10460 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10461 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10464 // Otherwise fall back on generic blend lowering.
10465 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10469 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10471 /// This routine is only called when we have AVX2 and thus a reasonable
10472 /// instruction set for v16i16 shuffling..
10473 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10474 const X86Subtarget *Subtarget,
10475 SelectionDAG &DAG) {
10477 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10478 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10479 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10480 ArrayRef<int> Mask = SVOp->getMask();
10481 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10482 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10484 // Whenever we can lower this as a zext, that instruction is strictly faster
10485 // than any alternative. It also allows us to fold memory operands into the
10486 // shuffle in many cases.
10487 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10488 Mask, Subtarget, DAG))
10491 // Check for being able to broadcast a single element.
10492 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10493 Mask, Subtarget, DAG))
10496 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10500 // Use dedicated unpack instructions for masks that match their pattern.
10501 if (isShuffleEquivalent(V1, V2, Mask,
10502 {// First 128-bit lane:
10503 0, 16, 1, 17, 2, 18, 3, 19,
10504 // Second 128-bit lane:
10505 8, 24, 9, 25, 10, 26, 11, 27}))
10506 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10507 if (isShuffleEquivalent(V1, V2, Mask,
10508 {// First 128-bit lane:
10509 4, 20, 5, 21, 6, 22, 7, 23,
10510 // Second 128-bit lane:
10511 12, 28, 13, 29, 14, 30, 15, 31}))
10512 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10514 // Try to use shift instructions.
10515 if (SDValue Shift =
10516 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10519 // Try to use byte rotation instructions.
10520 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10521 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10524 if (isSingleInputShuffleMask(Mask)) {
10525 // There are no generalized cross-lane shuffle operations available on i16
10527 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10528 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10531 SmallVector<int, 8> RepeatedMask;
10532 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10533 // As this is a single-input shuffle, the repeated mask should be
10534 // a strictly valid v8i16 mask that we can pass through to the v8i16
10535 // lowering to handle even the v16 case.
10536 return lowerV8I16GeneralSingleInputVectorShuffle(
10537 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10540 SDValue PSHUFBMask[32];
10541 for (int i = 0; i < 16; ++i) {
10542 if (Mask[i] == -1) {
10543 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10547 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10548 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10549 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10550 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10552 return DAG.getBitcast(MVT::v16i16,
10553 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10554 DAG.getBitcast(MVT::v32i8, V1),
10555 DAG.getNode(ISD::BUILD_VECTOR, DL,
10556 MVT::v32i8, PSHUFBMask)));
10559 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10561 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10562 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10565 // Otherwise fall back on generic lowering.
10566 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10569 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10571 /// This routine is only called when we have AVX2 and thus a reasonable
10572 /// instruction set for v32i8 shuffling..
10573 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10574 const X86Subtarget *Subtarget,
10575 SelectionDAG &DAG) {
10577 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10578 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10579 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10580 ArrayRef<int> Mask = SVOp->getMask();
10581 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10582 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10584 // Whenever we can lower this as a zext, that instruction is strictly faster
10585 // than any alternative. It also allows us to fold memory operands into the
10586 // shuffle in many cases.
10587 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10588 Mask, Subtarget, DAG))
10591 // Check for being able to broadcast a single element.
10592 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10593 Mask, Subtarget, DAG))
10596 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10600 // Use dedicated unpack instructions for masks that match their pattern.
10601 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10603 if (isShuffleEquivalent(
10605 {// First 128-bit lane:
10606 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10607 // Second 128-bit lane:
10608 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10609 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10610 if (isShuffleEquivalent(
10612 {// First 128-bit lane:
10613 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10614 // Second 128-bit lane:
10615 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10616 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10618 // Try to use shift instructions.
10619 if (SDValue Shift =
10620 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10623 // Try to use byte rotation instructions.
10624 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10625 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10628 if (isSingleInputShuffleMask(Mask)) {
10629 // There are no generalized cross-lane shuffle operations available on i8
10631 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10632 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10635 SDValue PSHUFBMask[32];
10636 for (int i = 0; i < 32; ++i)
10639 ? DAG.getUNDEF(MVT::i8)
10640 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10643 return DAG.getNode(
10644 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10645 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10648 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10650 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10651 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10654 // Otherwise fall back on generic lowering.
10655 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10658 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10660 /// This routine either breaks down the specific type of a 256-bit x86 vector
10661 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10662 /// together based on the available instructions.
10663 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10664 MVT VT, const X86Subtarget *Subtarget,
10665 SelectionDAG &DAG) {
10667 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10668 ArrayRef<int> Mask = SVOp->getMask();
10670 // If we have a single input to the zero element, insert that into V1 if we
10671 // can do so cheaply.
10672 int NumElts = VT.getVectorNumElements();
10673 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10674 return M >= NumElts;
10677 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10678 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10679 DL, VT, V1, V2, Mask, Subtarget, DAG))
10682 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10683 // can check for those subtargets here and avoid much of the subtarget
10684 // querying in the per-vector-type lowering routines. With AVX1 we have
10685 // essentially *zero* ability to manipulate a 256-bit vector with integer
10686 // types. Since we'll use floating point types there eventually, just
10687 // immediately cast everything to a float and operate entirely in that domain.
10688 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10689 int ElementBits = VT.getScalarSizeInBits();
10690 if (ElementBits < 32)
10691 // No floating point type available, decompose into 128-bit vectors.
10692 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10694 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10695 VT.getVectorNumElements());
10696 V1 = DAG.getBitcast(FpVT, V1);
10697 V2 = DAG.getBitcast(FpVT, V2);
10698 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10701 switch (VT.SimpleTy) {
10703 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10705 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10707 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10709 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10711 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10713 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10716 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10720 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10721 ArrayRef<int> Mask, SDValue V1,
10722 SDValue V2, SelectionDAG &DAG) {
10724 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10726 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10727 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10729 SmallVector<SDValue, 32> VPermMask;
10730 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10731 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10732 DAG.getConstant(Mask[i], DL, MaskEltVT));
10733 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10735 if (isSingleInputShuffleMask(Mask))
10736 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10738 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10741 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10742 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10743 const X86Subtarget *Subtarget,
10744 SelectionDAG &DAG) {
10746 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10747 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10748 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10749 ArrayRef<int> Mask = SVOp->getMask();
10750 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10752 if (SDValue Unpck =
10753 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10756 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10759 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10760 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10761 const X86Subtarget *Subtarget,
10762 SelectionDAG &DAG) {
10764 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10765 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10766 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10767 ArrayRef<int> Mask = SVOp->getMask();
10768 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10770 if (SDValue Unpck =
10771 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10774 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10777 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10778 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10779 const X86Subtarget *Subtarget,
10780 SelectionDAG &DAG) {
10782 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10783 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10784 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10785 ArrayRef<int> Mask = SVOp->getMask();
10786 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10788 if (SDValue Unpck =
10789 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10792 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10795 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10796 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10797 const X86Subtarget *Subtarget,
10798 SelectionDAG &DAG) {
10800 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10801 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10802 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10803 ArrayRef<int> Mask = SVOp->getMask();
10804 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10806 if (SDValue Unpck =
10807 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10810 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10813 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10814 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10815 const X86Subtarget *Subtarget,
10816 SelectionDAG &DAG) {
10818 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10819 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10820 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10821 ArrayRef<int> Mask = SVOp->getMask();
10822 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10823 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10825 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10828 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10829 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10830 const X86Subtarget *Subtarget,
10831 SelectionDAG &DAG) {
10833 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10834 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10835 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10836 ArrayRef<int> Mask = SVOp->getMask();
10837 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10838 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10840 // FIXME: Implement direct support for this type!
10841 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10844 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10846 /// This routine either breaks down the specific type of a 512-bit x86 vector
10847 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10848 /// together based on the available instructions.
10849 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10850 MVT VT, const X86Subtarget *Subtarget,
10851 SelectionDAG &DAG) {
10853 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10854 ArrayRef<int> Mask = SVOp->getMask();
10855 assert(Subtarget->hasAVX512() &&
10856 "Cannot lower 512-bit vectors w/ basic ISA!");
10858 // Check for being able to broadcast a single element.
10859 if (SDValue Broadcast =
10860 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10863 // Dispatch to each element type for lowering. If we don't have supprot for
10864 // specific element type shuffles at 512 bits, immediately split them and
10865 // lower them. Each lowering routine of a given type is allowed to assume that
10866 // the requisite ISA extensions for that element type are available.
10867 switch (VT.SimpleTy) {
10869 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10871 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10873 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10875 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10877 if (Subtarget->hasBWI())
10878 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10881 if (Subtarget->hasBWI())
10882 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10886 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10889 // Otherwise fall back on splitting.
10890 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10893 // Lower vXi1 vector shuffles.
10894 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10895 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10896 // vector, shuffle and then truncate it back.
10897 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10898 MVT VT, const X86Subtarget *Subtarget,
10899 SelectionDAG &DAG) {
10901 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10902 ArrayRef<int> Mask = SVOp->getMask();
10903 assert(Subtarget->hasAVX512() &&
10904 "Cannot lower 512-bit vectors w/o basic ISA!");
10906 switch (VT.SimpleTy) {
10908 assert(false && "Expected a vector of i1 elements");
10911 ExtVT = MVT::v2i64;
10914 ExtVT = MVT::v4i32;
10917 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10920 ExtVT = MVT::v16i32;
10923 ExtVT = MVT::v32i16;
10926 ExtVT = MVT::v64i8;
10930 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10931 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10932 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10933 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10935 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10938 V2 = DAG.getUNDEF(ExtVT);
10939 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10940 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10941 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10942 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10944 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10945 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10946 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10948 /// \brief Top-level lowering for x86 vector shuffles.
10950 /// This handles decomposition, canonicalization, and lowering of all x86
10951 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10952 /// above in helper routines. The canonicalization attempts to widen shuffles
10953 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10954 /// s.t. only one of the two inputs needs to be tested, etc.
10955 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10956 SelectionDAG &DAG) {
10957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10958 ArrayRef<int> Mask = SVOp->getMask();
10959 SDValue V1 = Op.getOperand(0);
10960 SDValue V2 = Op.getOperand(1);
10961 MVT VT = Op.getSimpleValueType();
10962 int NumElements = VT.getVectorNumElements();
10964 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
10966 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
10967 "Can't lower MMX shuffles");
10969 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10970 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10971 if (V1IsUndef && V2IsUndef)
10972 return DAG.getUNDEF(VT);
10974 // When we create a shuffle node we put the UNDEF node to second operand,
10975 // but in some cases the first operand may be transformed to UNDEF.
10976 // In this case we should just commute the node.
10978 return DAG.getCommutedVectorShuffle(*SVOp);
10980 // Check for non-undef masks pointing at an undef vector and make the masks
10981 // undef as well. This makes it easier to match the shuffle based solely on
10985 if (M >= NumElements) {
10986 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10987 for (int &M : NewMask)
10988 if (M >= NumElements)
10990 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10993 // We actually see shuffles that are entirely re-arrangements of a set of
10994 // zero inputs. This mostly happens while decomposing complex shuffles into
10995 // simple ones. Directly lower these as a buildvector of zeros.
10996 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10997 if (Zeroable.all())
10998 return getZeroVector(VT, Subtarget, DAG, dl);
11000 // Try to collapse shuffles into using a vector type with fewer elements but
11001 // wider element types. We cap this to not form integers or floating point
11002 // elements wider than 64 bits, but it might be interesting to form i128
11003 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11004 SmallVector<int, 16> WidenedMask;
11005 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11006 canWidenShuffleElements(Mask, WidenedMask)) {
11007 MVT NewEltVT = VT.isFloatingPoint()
11008 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11009 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11010 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11011 // Make sure that the new vector type is legal. For example, v2f64 isn't
11013 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11014 V1 = DAG.getBitcast(NewVT, V1);
11015 V2 = DAG.getBitcast(NewVT, V2);
11016 return DAG.getBitcast(
11017 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11021 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11022 for (int M : SVOp->getMask())
11024 ++NumUndefElements;
11025 else if (M < NumElements)
11030 // Commute the shuffle as needed such that more elements come from V1 than
11031 // V2. This allows us to match the shuffle pattern strictly on how many
11032 // elements come from V1 without handling the symmetric cases.
11033 if (NumV2Elements > NumV1Elements)
11034 return DAG.getCommutedVectorShuffle(*SVOp);
11036 // When the number of V1 and V2 elements are the same, try to minimize the
11037 // number of uses of V2 in the low half of the vector. When that is tied,
11038 // ensure that the sum of indices for V1 is equal to or lower than the sum
11039 // indices for V2. When those are equal, try to ensure that the number of odd
11040 // indices for V1 is lower than the number of odd indices for V2.
11041 if (NumV1Elements == NumV2Elements) {
11042 int LowV1Elements = 0, LowV2Elements = 0;
11043 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11044 if (M >= NumElements)
11048 if (LowV2Elements > LowV1Elements) {
11049 return DAG.getCommutedVectorShuffle(*SVOp);
11050 } else if (LowV2Elements == LowV1Elements) {
11051 int SumV1Indices = 0, SumV2Indices = 0;
11052 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11053 if (SVOp->getMask()[i] >= NumElements)
11055 else if (SVOp->getMask()[i] >= 0)
11057 if (SumV2Indices < SumV1Indices) {
11058 return DAG.getCommutedVectorShuffle(*SVOp);
11059 } else if (SumV2Indices == SumV1Indices) {
11060 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11061 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11062 if (SVOp->getMask()[i] >= NumElements)
11063 NumV2OddIndices += i % 2;
11064 else if (SVOp->getMask()[i] >= 0)
11065 NumV1OddIndices += i % 2;
11066 if (NumV2OddIndices < NumV1OddIndices)
11067 return DAG.getCommutedVectorShuffle(*SVOp);
11072 // For each vector width, delegate to a specialized lowering routine.
11073 if (VT.getSizeInBits() == 128)
11074 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11076 if (VT.getSizeInBits() == 256)
11077 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11079 if (VT.getSizeInBits() == 512)
11080 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11083 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11084 llvm_unreachable("Unimplemented!");
11087 // This function assumes its argument is a BUILD_VECTOR of constants or
11088 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11090 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11091 unsigned &MaskValue) {
11093 unsigned NumElems = BuildVector->getNumOperands();
11095 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11096 // We don't handle the >2 lanes case right now.
11097 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11101 unsigned NumElemsInLane = NumElems / NumLanes;
11103 // Blend for v16i16 should be symmetric for the both lanes.
11104 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11105 SDValue EltCond = BuildVector->getOperand(i);
11106 SDValue SndLaneEltCond =
11107 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11109 int Lane1Cond = -1, Lane2Cond = -1;
11110 if (isa<ConstantSDNode>(EltCond))
11111 Lane1Cond = !isZero(EltCond);
11112 if (isa<ConstantSDNode>(SndLaneEltCond))
11113 Lane2Cond = !isZero(SndLaneEltCond);
11115 unsigned LaneMask = 0;
11116 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11117 // Lane1Cond != 0, means we want the first argument.
11118 // Lane1Cond == 0, means we want the second argument.
11119 // The encoding of this argument is 0 for the first argument, 1
11120 // for the second. Therefore, invert the condition.
11121 LaneMask = !Lane1Cond << i;
11122 else if (Lane1Cond < 0)
11123 LaneMask = !Lane2Cond << i;
11127 MaskValue |= LaneMask;
11129 MaskValue |= LaneMask << NumElemsInLane;
11134 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11135 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11136 const X86Subtarget *Subtarget,
11137 SelectionDAG &DAG) {
11138 SDValue Cond = Op.getOperand(0);
11139 SDValue LHS = Op.getOperand(1);
11140 SDValue RHS = Op.getOperand(2);
11142 MVT VT = Op.getSimpleValueType();
11144 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11146 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11148 // Only non-legal VSELECTs reach this lowering, convert those into generic
11149 // shuffles and re-use the shuffle lowering path for blends.
11150 SmallVector<int, 32> Mask;
11151 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11152 SDValue CondElt = CondBV->getOperand(i);
11154 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11156 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11159 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11160 // A vselect where all conditions and data are constants can be optimized into
11161 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11162 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11163 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11164 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11167 // Try to lower this to a blend-style vector shuffle. This can handle all
11168 // constant condition cases.
11169 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11172 // Variable blends are only legal from SSE4.1 onward.
11173 if (!Subtarget->hasSSE41())
11176 // Only some types will be legal on some subtargets. If we can emit a legal
11177 // VSELECT-matching blend, return Op, and but if we need to expand, return
11179 switch (Op.getSimpleValueType().SimpleTy) {
11181 // Most of the vector types have blends past SSE4.1.
11185 // The byte blends for AVX vectors were introduced only in AVX2.
11186 if (Subtarget->hasAVX2())
11193 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11194 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11197 // FIXME: We should custom lower this by fixing the condition and using i8
11203 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11204 MVT VT = Op.getSimpleValueType();
11207 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11210 if (VT.getSizeInBits() == 8) {
11211 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11212 Op.getOperand(0), Op.getOperand(1));
11213 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11214 DAG.getValueType(VT));
11215 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11218 if (VT.getSizeInBits() == 16) {
11219 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11220 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11222 return DAG.getNode(
11223 ISD::TRUNCATE, dl, MVT::i16,
11224 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11225 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11226 Op.getOperand(1)));
11227 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11228 Op.getOperand(0), Op.getOperand(1));
11229 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11230 DAG.getValueType(VT));
11231 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11234 if (VT == MVT::f32) {
11235 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11236 // the result back to FR32 register. It's only worth matching if the
11237 // result has a single use which is a store or a bitcast to i32. And in
11238 // the case of a store, it's not worth it if the index is a constant 0,
11239 // because a MOVSSmr can be used instead, which is smaller and faster.
11240 if (!Op.hasOneUse())
11242 SDNode *User = *Op.getNode()->use_begin();
11243 if ((User->getOpcode() != ISD::STORE ||
11244 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11245 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11246 (User->getOpcode() != ISD::BITCAST ||
11247 User->getValueType(0) != MVT::i32))
11249 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11250 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11252 return DAG.getBitcast(MVT::f32, Extract);
11255 if (VT == MVT::i32 || VT == MVT::i64) {
11256 // ExtractPS/pextrq works with constant index.
11257 if (isa<ConstantSDNode>(Op.getOperand(1)))
11263 /// Extract one bit from mask vector, like v16i1 or v8i1.
11264 /// AVX-512 feature.
11266 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11267 SDValue Vec = Op.getOperand(0);
11269 MVT VecVT = Vec.getSimpleValueType();
11270 SDValue Idx = Op.getOperand(1);
11271 MVT EltVT = Op.getSimpleValueType();
11273 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11274 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11275 "Unexpected vector type in ExtractBitFromMaskVector");
11277 // variable index can't be handled in mask registers,
11278 // extend vector to VR512
11279 if (!isa<ConstantSDNode>(Idx)) {
11280 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11281 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11282 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11283 ExtVT.getVectorElementType(), Ext, Idx);
11284 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11287 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11288 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11289 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11290 rc = getRegClassFor(MVT::v16i1);
11291 unsigned MaxSift = rc->getSize()*8 - 1;
11292 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11293 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11294 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11295 DAG.getConstant(MaxSift, dl, MVT::i8));
11296 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11297 DAG.getIntPtrConstant(0, dl));
11301 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11302 SelectionDAG &DAG) const {
11304 SDValue Vec = Op.getOperand(0);
11305 MVT VecVT = Vec.getSimpleValueType();
11306 SDValue Idx = Op.getOperand(1);
11308 if (Op.getSimpleValueType() == MVT::i1)
11309 return ExtractBitFromMaskVector(Op, DAG);
11311 if (!isa<ConstantSDNode>(Idx)) {
11312 if (VecVT.is512BitVector() ||
11313 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11314 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11317 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11318 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11319 MaskEltVT.getSizeInBits());
11321 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11322 auto PtrVT = getPointerTy(DAG.getDataLayout());
11323 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11324 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11325 DAG.getConstant(0, dl, PtrVT));
11326 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11327 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11328 DAG.getConstant(0, dl, PtrVT));
11333 // If this is a 256-bit vector result, first extract the 128-bit vector and
11334 // then extract the element from the 128-bit vector.
11335 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11337 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11338 // Get the 128-bit vector.
11339 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11340 MVT EltVT = VecVT.getVectorElementType();
11342 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11344 //if (IdxVal >= NumElems/2)
11345 // IdxVal -= NumElems/2;
11346 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11348 DAG.getConstant(IdxVal, dl, MVT::i32));
11351 assert(VecVT.is128BitVector() && "Unexpected vector length");
11353 if (Subtarget->hasSSE41())
11354 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11357 MVT VT = Op.getSimpleValueType();
11358 // TODO: handle v16i8.
11359 if (VT.getSizeInBits() == 16) {
11360 SDValue Vec = Op.getOperand(0);
11361 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11363 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11364 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11365 DAG.getBitcast(MVT::v4i32, Vec),
11366 Op.getOperand(1)));
11367 // Transform it so it match pextrw which produces a 32-bit result.
11368 MVT EltVT = MVT::i32;
11369 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11370 Op.getOperand(0), Op.getOperand(1));
11371 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11372 DAG.getValueType(VT));
11373 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11376 if (VT.getSizeInBits() == 32) {
11377 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11381 // SHUFPS the element to the lowest double word, then movss.
11382 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11383 MVT VVT = Op.getOperand(0).getSimpleValueType();
11384 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11385 DAG.getUNDEF(VVT), Mask);
11386 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11387 DAG.getIntPtrConstant(0, dl));
11390 if (VT.getSizeInBits() == 64) {
11391 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11392 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11393 // to match extract_elt for f64.
11394 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11398 // UNPCKHPD the element to the lowest double word, then movsd.
11399 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11400 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11401 int Mask[2] = { 1, -1 };
11402 MVT VVT = Op.getOperand(0).getSimpleValueType();
11403 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11404 DAG.getUNDEF(VVT), Mask);
11405 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11406 DAG.getIntPtrConstant(0, dl));
11412 /// Insert one bit to mask vector, like v16i1 or v8i1.
11413 /// AVX-512 feature.
11415 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11417 SDValue Vec = Op.getOperand(0);
11418 SDValue Elt = Op.getOperand(1);
11419 SDValue Idx = Op.getOperand(2);
11420 MVT VecVT = Vec.getSimpleValueType();
11422 if (!isa<ConstantSDNode>(Idx)) {
11423 // Non constant index. Extend source and destination,
11424 // insert element and then truncate the result.
11425 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11426 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11427 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11428 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11429 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11430 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11433 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11434 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11436 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11437 DAG.getConstant(IdxVal, dl, MVT::i8));
11438 if (Vec.getOpcode() == ISD::UNDEF)
11440 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11443 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11444 SelectionDAG &DAG) const {
11445 MVT VT = Op.getSimpleValueType();
11446 MVT EltVT = VT.getVectorElementType();
11448 if (EltVT == MVT::i1)
11449 return InsertBitToMaskVector(Op, DAG);
11452 SDValue N0 = Op.getOperand(0);
11453 SDValue N1 = Op.getOperand(1);
11454 SDValue N2 = Op.getOperand(2);
11455 if (!isa<ConstantSDNode>(N2))
11457 auto *N2C = cast<ConstantSDNode>(N2);
11458 unsigned IdxVal = N2C->getZExtValue();
11460 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11461 // into that, and then insert the subvector back into the result.
11462 if (VT.is256BitVector() || VT.is512BitVector()) {
11463 // With a 256-bit vector, we can insert into the zero element efficiently
11464 // using a blend if we have AVX or AVX2 and the right data type.
11465 if (VT.is256BitVector() && IdxVal == 0) {
11466 // TODO: It is worthwhile to cast integer to floating point and back
11467 // and incur a domain crossing penalty if that's what we'll end up
11468 // doing anyway after extracting to a 128-bit vector.
11469 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11470 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11471 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11472 N2 = DAG.getIntPtrConstant(1, dl);
11473 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11477 // Get the desired 128-bit vector chunk.
11478 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11480 // Insert the element into the desired chunk.
11481 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11482 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11484 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11485 DAG.getConstant(IdxIn128, dl, MVT::i32));
11487 // Insert the changed part back into the bigger vector
11488 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11490 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11492 if (Subtarget->hasSSE41()) {
11493 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11495 if (VT == MVT::v8i16) {
11496 Opc = X86ISD::PINSRW;
11498 assert(VT == MVT::v16i8);
11499 Opc = X86ISD::PINSRB;
11502 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11504 if (N1.getValueType() != MVT::i32)
11505 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11506 if (N2.getValueType() != MVT::i32)
11507 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11508 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11511 if (EltVT == MVT::f32) {
11512 // Bits [7:6] of the constant are the source select. This will always be
11513 // zero here. The DAG Combiner may combine an extract_elt index into
11514 // these bits. For example (insert (extract, 3), 2) could be matched by
11515 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11516 // Bits [5:4] of the constant are the destination select. This is the
11517 // value of the incoming immediate.
11518 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11519 // combine either bitwise AND or insert of float 0.0 to set these bits.
11521 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11522 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11523 // If this is an insertion of 32-bits into the low 32-bits of
11524 // a vector, we prefer to generate a blend with immediate rather
11525 // than an insertps. Blends are simpler operations in hardware and so
11526 // will always have equal or better performance than insertps.
11527 // But if optimizing for size and there's a load folding opportunity,
11528 // generate insertps because blendps does not have a 32-bit memory
11530 N2 = DAG.getIntPtrConstant(1, dl);
11531 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11532 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11534 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11535 // Create this as a scalar to vector..
11536 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11537 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11540 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11541 // PINSR* works with constant index.
11546 if (EltVT == MVT::i8)
11549 if (EltVT.getSizeInBits() == 16) {
11550 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11551 // as its second argument.
11552 if (N1.getValueType() != MVT::i32)
11553 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11554 if (N2.getValueType() != MVT::i32)
11555 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11556 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11561 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11563 MVT OpVT = Op.getSimpleValueType();
11565 // If this is a 256-bit vector result, first insert into a 128-bit
11566 // vector and then insert into the 256-bit vector.
11567 if (!OpVT.is128BitVector()) {
11568 // Insert into a 128-bit vector.
11569 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11570 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11571 OpVT.getVectorNumElements() / SizeFactor);
11573 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11575 // Insert the 128-bit vector.
11576 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11579 if (OpVT == MVT::v1i64 &&
11580 Op.getOperand(0).getValueType() == MVT::i64)
11581 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11583 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11584 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11585 return DAG.getBitcast(
11586 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11589 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11590 // a simple subregister reference or explicit instructions to grab
11591 // upper bits of a vector.
11592 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11593 SelectionDAG &DAG) {
11595 SDValue In = Op.getOperand(0);
11596 SDValue Idx = Op.getOperand(1);
11597 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11598 MVT ResVT = Op.getSimpleValueType();
11599 MVT InVT = In.getSimpleValueType();
11601 if (Subtarget->hasFp256()) {
11602 if (ResVT.is128BitVector() &&
11603 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11604 isa<ConstantSDNode>(Idx)) {
11605 return Extract128BitVector(In, IdxVal, DAG, dl);
11607 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11608 isa<ConstantSDNode>(Idx)) {
11609 return Extract256BitVector(In, IdxVal, DAG, dl);
11615 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11616 // simple superregister reference or explicit instructions to insert
11617 // the upper bits of a vector.
11618 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11619 SelectionDAG &DAG) {
11620 if (!Subtarget->hasAVX())
11624 SDValue Vec = Op.getOperand(0);
11625 SDValue SubVec = Op.getOperand(1);
11626 SDValue Idx = Op.getOperand(2);
11628 if (!isa<ConstantSDNode>(Idx))
11631 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11632 MVT OpVT = Op.getSimpleValueType();
11633 MVT SubVecVT = SubVec.getSimpleValueType();
11635 // Fold two 16-byte subvector loads into one 32-byte load:
11636 // (insert_subvector (insert_subvector undef, (load addr), 0),
11637 // (load addr + 16), Elts/2)
11639 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11640 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11641 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11642 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11643 if (Idx2 && Idx2->getZExtValue() == 0) {
11644 SDValue SubVec2 = Vec.getOperand(1);
11645 // If needed, look through a bitcast to get to the load.
11646 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11647 SubVec2 = SubVec2.getOperand(0);
11649 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11651 unsigned Alignment = FirstLd->getAlignment();
11652 unsigned AS = FirstLd->getAddressSpace();
11653 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11654 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11655 OpVT, AS, Alignment, &Fast) && Fast) {
11656 SDValue Ops[] = { SubVec2, SubVec };
11657 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11664 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11665 SubVecVT.is128BitVector())
11666 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11668 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11669 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11671 if (OpVT.getVectorElementType() == MVT::i1) {
11672 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11674 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11675 SDValue Undef = DAG.getUNDEF(OpVT);
11676 unsigned NumElems = OpVT.getVectorNumElements();
11677 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11679 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11680 // Zero upper bits of the Vec
11681 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11682 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11684 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11686 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11687 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11690 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11692 // Zero upper bits of the Vec2
11693 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11694 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11695 // Zero lower bits of the Vec
11696 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11697 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11698 // Merge them together
11699 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11705 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11706 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11707 // one of the above mentioned nodes. It has to be wrapped because otherwise
11708 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11709 // be used to form addressing mode. These wrapped nodes will be selected
11712 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11713 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11715 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11716 // global base reg.
11717 unsigned char OpFlag = 0;
11718 unsigned WrapperKind = X86ISD::Wrapper;
11719 CodeModel::Model M = DAG.getTarget().getCodeModel();
11721 if (Subtarget->isPICStyleRIPRel() &&
11722 (M == CodeModel::Small || M == CodeModel::Kernel))
11723 WrapperKind = X86ISD::WrapperRIP;
11724 else if (Subtarget->isPICStyleGOT())
11725 OpFlag = X86II::MO_GOTOFF;
11726 else if (Subtarget->isPICStyleStubPIC())
11727 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11729 auto PtrVT = getPointerTy(DAG.getDataLayout());
11730 SDValue Result = DAG.getTargetConstantPool(
11731 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11733 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11734 // With PIC, the address is actually $g + Offset.
11737 DAG.getNode(ISD::ADD, DL, PtrVT,
11738 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11744 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11745 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11747 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11748 // global base reg.
11749 unsigned char OpFlag = 0;
11750 unsigned WrapperKind = X86ISD::Wrapper;
11751 CodeModel::Model M = DAG.getTarget().getCodeModel();
11753 if (Subtarget->isPICStyleRIPRel() &&
11754 (M == CodeModel::Small || M == CodeModel::Kernel))
11755 WrapperKind = X86ISD::WrapperRIP;
11756 else if (Subtarget->isPICStyleGOT())
11757 OpFlag = X86II::MO_GOTOFF;
11758 else if (Subtarget->isPICStyleStubPIC())
11759 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11761 auto PtrVT = getPointerTy(DAG.getDataLayout());
11762 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11764 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11766 // With PIC, the address is actually $g + Offset.
11769 DAG.getNode(ISD::ADD, DL, PtrVT,
11770 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11776 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11777 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11779 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11780 // global base reg.
11781 unsigned char OpFlag = 0;
11782 unsigned WrapperKind = X86ISD::Wrapper;
11783 CodeModel::Model M = DAG.getTarget().getCodeModel();
11785 if (Subtarget->isPICStyleRIPRel() &&
11786 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11787 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11788 OpFlag = X86II::MO_GOTPCREL;
11789 WrapperKind = X86ISD::WrapperRIP;
11790 } else if (Subtarget->isPICStyleGOT()) {
11791 OpFlag = X86II::MO_GOT;
11792 } else if (Subtarget->isPICStyleStubPIC()) {
11793 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11794 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11795 OpFlag = X86II::MO_DARWIN_NONLAZY;
11798 auto PtrVT = getPointerTy(DAG.getDataLayout());
11799 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11802 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11804 // With PIC, the address is actually $g + Offset.
11805 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11806 !Subtarget->is64Bit()) {
11808 DAG.getNode(ISD::ADD, DL, PtrVT,
11809 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11812 // For symbols that require a load from a stub to get the address, emit the
11814 if (isGlobalStubReference(OpFlag))
11815 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11816 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11817 false, false, false, 0);
11823 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11824 // Create the TargetBlockAddressAddress node.
11825 unsigned char OpFlags =
11826 Subtarget->ClassifyBlockAddressReference();
11827 CodeModel::Model M = DAG.getTarget().getCodeModel();
11828 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11829 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11831 auto PtrVT = getPointerTy(DAG.getDataLayout());
11832 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11834 if (Subtarget->isPICStyleRIPRel() &&
11835 (M == CodeModel::Small || M == CodeModel::Kernel))
11836 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11838 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11840 // With PIC, the address is actually $g + Offset.
11841 if (isGlobalRelativeToPICBase(OpFlags)) {
11842 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11843 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11850 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11851 int64_t Offset, SelectionDAG &DAG) const {
11852 // Create the TargetGlobalAddress node, folding in the constant
11853 // offset if it is legal.
11854 unsigned char OpFlags =
11855 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11856 CodeModel::Model M = DAG.getTarget().getCodeModel();
11857 auto PtrVT = getPointerTy(DAG.getDataLayout());
11859 if (OpFlags == X86II::MO_NO_FLAG &&
11860 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11861 // A direct static reference to a global.
11862 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11865 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11868 if (Subtarget->isPICStyleRIPRel() &&
11869 (M == CodeModel::Small || M == CodeModel::Kernel))
11870 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11872 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11874 // With PIC, the address is actually $g + Offset.
11875 if (isGlobalRelativeToPICBase(OpFlags)) {
11876 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11877 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11880 // For globals that require a load from a stub to get the address, emit the
11882 if (isGlobalStubReference(OpFlags))
11883 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11884 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11885 false, false, false, 0);
11887 // If there was a non-zero offset that we didn't fold, create an explicit
11888 // addition for it.
11890 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11891 DAG.getConstant(Offset, dl, PtrVT));
11897 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11898 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11899 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11900 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11904 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11905 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11906 unsigned char OperandFlags, bool LocalDynamic = false) {
11907 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11908 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11910 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11911 GA->getValueType(0),
11915 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11919 SDValue Ops[] = { Chain, TGA, *InFlag };
11920 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11922 SDValue Ops[] = { Chain, TGA };
11923 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11926 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11927 MFI->setAdjustsStack(true);
11928 MFI->setHasCalls(true);
11930 SDValue Flag = Chain.getValue(1);
11931 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11934 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11936 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11939 SDLoc dl(GA); // ? function entry point might be better
11940 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11941 DAG.getNode(X86ISD::GlobalBaseReg,
11942 SDLoc(), PtrVT), InFlag);
11943 InFlag = Chain.getValue(1);
11945 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11948 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11950 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11952 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11953 X86::RAX, X86II::MO_TLSGD);
11956 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11962 // Get the start address of the TLS block for this module.
11963 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11964 .getInfo<X86MachineFunctionInfo>();
11965 MFI->incNumLocalDynamicTLSAccesses();
11969 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11970 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11973 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11974 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11975 InFlag = Chain.getValue(1);
11976 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11977 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11980 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11984 unsigned char OperandFlags = X86II::MO_DTPOFF;
11985 unsigned WrapperKind = X86ISD::Wrapper;
11986 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11987 GA->getValueType(0),
11988 GA->getOffset(), OperandFlags);
11989 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11991 // Add x@dtpoff with the base.
11992 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11995 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11996 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11997 const EVT PtrVT, TLSModel::Model model,
11998 bool is64Bit, bool isPIC) {
12001 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12002 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12003 is64Bit ? 257 : 256));
12005 SDValue ThreadPointer =
12006 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12007 MachinePointerInfo(Ptr), false, false, false, 0);
12009 unsigned char OperandFlags = 0;
12010 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12012 unsigned WrapperKind = X86ISD::Wrapper;
12013 if (model == TLSModel::LocalExec) {
12014 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12015 } else if (model == TLSModel::InitialExec) {
12017 OperandFlags = X86II::MO_GOTTPOFF;
12018 WrapperKind = X86ISD::WrapperRIP;
12020 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12023 llvm_unreachable("Unexpected model");
12026 // emit "addl x@ntpoff,%eax" (local exec)
12027 // or "addl x@indntpoff,%eax" (initial exec)
12028 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12030 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12031 GA->getOffset(), OperandFlags);
12032 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12034 if (model == TLSModel::InitialExec) {
12035 if (isPIC && !is64Bit) {
12036 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12037 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12041 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12042 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12043 false, false, false, 0);
12046 // The address of the thread local variable is the add of the thread
12047 // pointer with the offset of the variable.
12048 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12052 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12054 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12055 const GlobalValue *GV = GA->getGlobal();
12056 auto PtrVT = getPointerTy(DAG.getDataLayout());
12058 if (Subtarget->isTargetELF()) {
12059 if (DAG.getTarget().Options.EmulatedTLS)
12060 return LowerToTLSEmulatedModel(GA, DAG);
12061 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12063 case TLSModel::GeneralDynamic:
12064 if (Subtarget->is64Bit())
12065 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12066 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12067 case TLSModel::LocalDynamic:
12068 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12069 Subtarget->is64Bit());
12070 case TLSModel::InitialExec:
12071 case TLSModel::LocalExec:
12072 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12073 DAG.getTarget().getRelocationModel() ==
12076 llvm_unreachable("Unknown TLS model.");
12079 if (Subtarget->isTargetDarwin()) {
12080 // Darwin only has one model of TLS. Lower to that.
12081 unsigned char OpFlag = 0;
12082 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12083 X86ISD::WrapperRIP : X86ISD::Wrapper;
12085 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12086 // global base reg.
12087 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12088 !Subtarget->is64Bit();
12090 OpFlag = X86II::MO_TLVP_PIC_BASE;
12092 OpFlag = X86II::MO_TLVP;
12094 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12095 GA->getValueType(0),
12096 GA->getOffset(), OpFlag);
12097 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12099 // With PIC32, the address is actually $g + Offset.
12101 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12102 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12105 // Lowering the machine isd will make sure everything is in the right
12107 SDValue Chain = DAG.getEntryNode();
12108 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12109 SDValue Args[] = { Chain, Offset };
12110 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12112 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12113 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12114 MFI->setAdjustsStack(true);
12116 // And our return value (tls address) is in the standard call return value
12118 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12119 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12122 if (Subtarget->isTargetKnownWindowsMSVC() ||
12123 Subtarget->isTargetWindowsGNU()) {
12124 // Just use the implicit TLS architecture
12125 // Need to generate someting similar to:
12126 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12128 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12129 // mov rcx, qword [rdx+rcx*8]
12130 // mov eax, .tls$:tlsvar
12131 // [rax+rcx] contains the address
12132 // Windows 64bit: gs:0x58
12133 // Windows 32bit: fs:__tls_array
12136 SDValue Chain = DAG.getEntryNode();
12138 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12139 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12140 // use its literal value of 0x2C.
12141 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12142 ? Type::getInt8PtrTy(*DAG.getContext(),
12144 : Type::getInt32PtrTy(*DAG.getContext(),
12147 SDValue TlsArray = Subtarget->is64Bit()
12148 ? DAG.getIntPtrConstant(0x58, dl)
12149 : (Subtarget->isTargetWindowsGNU()
12150 ? DAG.getIntPtrConstant(0x2C, dl)
12151 : DAG.getExternalSymbol("_tls_array", PtrVT));
12153 SDValue ThreadPointer =
12154 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12158 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12159 res = ThreadPointer;
12161 // Load the _tls_index variable
12162 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12163 if (Subtarget->is64Bit())
12164 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12165 MachinePointerInfo(), MVT::i32, false, false,
12168 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12171 auto &DL = DAG.getDataLayout();
12173 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12174 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12176 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12179 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12182 // Get the offset of start of .tls section
12183 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12184 GA->getValueType(0),
12185 GA->getOffset(), X86II::MO_SECREL);
12186 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12188 // The address of the thread local variable is the add of the thread
12189 // pointer with the offset of the variable.
12190 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12193 llvm_unreachable("TLS not implemented for this target.");
12196 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12197 /// and take a 2 x i32 value to shift plus a shift amount.
12198 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12199 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12200 MVT VT = Op.getSimpleValueType();
12201 unsigned VTBits = VT.getSizeInBits();
12203 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12204 SDValue ShOpLo = Op.getOperand(0);
12205 SDValue ShOpHi = Op.getOperand(1);
12206 SDValue ShAmt = Op.getOperand(2);
12207 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12208 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12210 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12211 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12212 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12213 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12214 : DAG.getConstant(0, dl, VT);
12216 SDValue Tmp2, Tmp3;
12217 if (Op.getOpcode() == ISD::SHL_PARTS) {
12218 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12219 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12221 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12222 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12225 // If the shift amount is larger or equal than the width of a part we can't
12226 // rely on the results of shld/shrd. Insert a test and select the appropriate
12227 // values for large shift amounts.
12228 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12229 DAG.getConstant(VTBits, dl, MVT::i8));
12230 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12231 AndNode, DAG.getConstant(0, dl, MVT::i8));
12234 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12235 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12236 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12238 if (Op.getOpcode() == ISD::SHL_PARTS) {
12239 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12240 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12242 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12243 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12246 SDValue Ops[2] = { Lo, Hi };
12247 return DAG.getMergeValues(Ops, dl);
12250 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12251 SelectionDAG &DAG) const {
12252 SDValue Src = Op.getOperand(0);
12253 MVT SrcVT = Src.getSimpleValueType();
12254 MVT VT = Op.getSimpleValueType();
12257 if (SrcVT.isVector()) {
12258 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12259 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12260 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12261 DAG.getUNDEF(SrcVT)));
12263 if (SrcVT.getVectorElementType() == MVT::i1) {
12264 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12265 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12266 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12271 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12272 "Unknown SINT_TO_FP to lower!");
12274 // These are really Legal; return the operand so the caller accepts it as
12276 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12278 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12279 Subtarget->is64Bit()) {
12283 unsigned Size = SrcVT.getSizeInBits()/8;
12284 MachineFunction &MF = DAG.getMachineFunction();
12285 auto PtrVT = getPointerTy(MF.getDataLayout());
12286 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12287 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12288 SDValue Chain = DAG.getStore(
12289 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12290 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12292 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12295 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12297 SelectionDAG &DAG) const {
12301 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12303 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12305 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12307 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12309 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12310 MachineMemOperand *MMO;
12312 int SSFI = FI->getIndex();
12313 MMO = DAG.getMachineFunction().getMachineMemOperand(
12314 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12315 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12317 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12318 StackSlot = StackSlot.getOperand(1);
12320 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12321 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12323 Tys, Ops, SrcVT, MMO);
12326 Chain = Result.getValue(1);
12327 SDValue InFlag = Result.getValue(2);
12329 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12330 // shouldn't be necessary except that RFP cannot be live across
12331 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12332 MachineFunction &MF = DAG.getMachineFunction();
12333 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12334 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12335 auto PtrVT = getPointerTy(MF.getDataLayout());
12336 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12337 Tys = DAG.getVTList(MVT::Other);
12339 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12341 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12342 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12343 MachineMemOperand::MOStore, SSFISize, SSFISize);
12345 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12346 Ops, Op.getValueType(), MMO);
12347 Result = DAG.getLoad(
12348 Op.getValueType(), DL, Chain, StackSlot,
12349 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12350 false, false, false, 0);
12356 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12357 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12358 SelectionDAG &DAG) const {
12359 // This algorithm is not obvious. Here it is what we're trying to output:
12362 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12363 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12365 haddpd %xmm0, %xmm0
12367 pshufd $0x4e, %xmm0, %xmm1
12373 LLVMContext *Context = DAG.getContext();
12375 // Build some magic constants.
12376 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12377 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12378 auto PtrVT = getPointerTy(DAG.getDataLayout());
12379 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12381 SmallVector<Constant*,2> CV1;
12383 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12384 APInt(64, 0x4330000000000000ULL))));
12386 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12387 APInt(64, 0x4530000000000000ULL))));
12388 Constant *C1 = ConstantVector::get(CV1);
12389 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12391 // Load the 64-bit value into an XMM register.
12392 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12395 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12396 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12397 false, false, false, 16);
12399 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12402 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12403 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12404 false, false, false, 16);
12405 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12406 // TODO: Are there any fast-math-flags to propagate here?
12407 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12410 if (Subtarget->hasSSE3()) {
12411 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12412 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12414 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12415 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12417 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12418 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12421 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12422 DAG.getIntPtrConstant(0, dl));
12425 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12426 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12427 SelectionDAG &DAG) const {
12429 // FP constant to bias correct the final result.
12430 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12433 // Load the 32-bit value into an XMM register.
12434 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12437 // Zero out the upper parts of the register.
12438 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12440 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12441 DAG.getBitcast(MVT::v2f64, Load),
12442 DAG.getIntPtrConstant(0, dl));
12444 // Or the load with the bias.
12445 SDValue Or = DAG.getNode(
12446 ISD::OR, dl, MVT::v2i64,
12447 DAG.getBitcast(MVT::v2i64,
12448 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12449 DAG.getBitcast(MVT::v2i64,
12450 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12452 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12453 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12455 // Subtract the bias.
12456 // TODO: Are there any fast-math-flags to propagate here?
12457 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12459 // Handle final rounding.
12460 EVT DestVT = Op.getValueType();
12462 if (DestVT.bitsLT(MVT::f64))
12463 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12464 DAG.getIntPtrConstant(0, dl));
12465 if (DestVT.bitsGT(MVT::f64))
12466 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12468 // Handle final rounding.
12472 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12473 const X86Subtarget &Subtarget) {
12474 // The algorithm is the following:
12475 // #ifdef __SSE4_1__
12476 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12477 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12478 // (uint4) 0x53000000, 0xaa);
12480 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12481 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12483 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12484 // return (float4) lo + fhi;
12486 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12487 // reassociate the two FADDs, and if we do that, the algorithm fails
12488 // spectacularly (PR24512).
12489 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12490 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12491 // there's also the MachineCombiner reassociations happening on Machine IR.
12492 if (DAG.getTarget().Options.UnsafeFPMath)
12496 SDValue V = Op->getOperand(0);
12497 EVT VecIntVT = V.getValueType();
12498 bool Is128 = VecIntVT == MVT::v4i32;
12499 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12500 // If we convert to something else than the supported type, e.g., to v4f64,
12502 if (VecFloatVT != Op->getValueType(0))
12505 unsigned NumElts = VecIntVT.getVectorNumElements();
12506 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12507 "Unsupported custom type");
12508 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12510 // In the #idef/#else code, we have in common:
12511 // - The vector of constants:
12517 // Create the splat vector for 0x4b000000.
12518 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12519 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12520 CstLow, CstLow, CstLow, CstLow};
12521 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12522 makeArrayRef(&CstLowArray[0], NumElts));
12523 // Create the splat vector for 0x53000000.
12524 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12525 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12526 CstHigh, CstHigh, CstHigh, CstHigh};
12527 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12528 makeArrayRef(&CstHighArray[0], NumElts));
12530 // Create the right shift.
12531 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12532 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12533 CstShift, CstShift, CstShift, CstShift};
12534 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12535 makeArrayRef(&CstShiftArray[0], NumElts));
12536 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12539 if (Subtarget.hasSSE41()) {
12540 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12541 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12542 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12543 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12544 // Low will be bitcasted right away, so do not bother bitcasting back to its
12546 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12547 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12548 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12549 // (uint4) 0x53000000, 0xaa);
12550 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12551 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12552 // High will be bitcasted right away, so do not bother bitcasting back to
12553 // its original type.
12554 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12555 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12557 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12558 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12559 CstMask, CstMask, CstMask);
12560 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12561 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12562 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12564 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12565 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12568 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12569 SDValue CstFAdd = DAG.getConstantFP(
12570 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12571 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12572 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12573 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12574 makeArrayRef(&CstFAddArray[0], NumElts));
12576 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12577 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12578 // TODO: Are there any fast-math-flags to propagate here?
12580 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12581 // return (float4) lo + fhi;
12582 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12583 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12586 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12587 SelectionDAG &DAG) const {
12588 SDValue N0 = Op.getOperand(0);
12589 MVT SVT = N0.getSimpleValueType();
12592 switch (SVT.SimpleTy) {
12594 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12599 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12600 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12601 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12605 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12608 if (Subtarget->hasAVX512())
12609 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12610 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12612 llvm_unreachable(nullptr);
12615 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12616 SelectionDAG &DAG) const {
12617 SDValue N0 = Op.getOperand(0);
12619 auto PtrVT = getPointerTy(DAG.getDataLayout());
12621 if (Op.getValueType().isVector())
12622 return lowerUINT_TO_FP_vec(Op, DAG);
12624 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12625 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12626 // the optimization here.
12627 if (DAG.SignBitIsZero(N0))
12628 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12630 MVT SrcVT = N0.getSimpleValueType();
12631 MVT DstVT = Op.getSimpleValueType();
12633 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12634 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12635 // Conversions from unsigned i32 to f32/f64 are legal,
12636 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12640 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12641 return LowerUINT_TO_FP_i64(Op, DAG);
12642 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12643 return LowerUINT_TO_FP_i32(Op, DAG);
12644 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12647 // Make a 64-bit buffer, and use it to build an FILD.
12648 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12649 if (SrcVT == MVT::i32) {
12650 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12651 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12652 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12653 StackSlot, MachinePointerInfo(),
12655 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12656 OffsetSlot, MachinePointerInfo(),
12658 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12662 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12663 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12664 StackSlot, MachinePointerInfo(),
12666 // For i64 source, we need to add the appropriate power of 2 if the input
12667 // was negative. This is the same as the optimization in
12668 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12669 // we must be careful to do the computation in x87 extended precision, not
12670 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12671 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12672 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12673 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12674 MachineMemOperand::MOLoad, 8, 8);
12676 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12677 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12678 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12681 APInt FF(32, 0x5F800000ULL);
12683 // Check whether the sign bit is set.
12684 SDValue SignSet = DAG.getSetCC(
12685 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12686 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12688 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12689 SDValue FudgePtr = DAG.getConstantPool(
12690 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12692 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12693 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12694 SDValue Four = DAG.getIntPtrConstant(4, dl);
12695 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12697 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12699 // Load the value out, extending it from f32 to f80.
12700 // FIXME: Avoid the extend by constructing the right constant pool?
12701 SDValue Fudge = DAG.getExtLoad(
12702 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12703 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12704 false, false, false, 4);
12705 // Extend everything to 80 bits to force it to be done on x87.
12706 // TODO: Are there any fast-math-flags to propagate here?
12707 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12708 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12709 DAG.getIntPtrConstant(0, dl));
12712 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12713 // is legal, or has an f16 source (which needs to be promoted to f32),
12714 // just return an <SDValue(), SDValue()> pair.
12715 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12716 // to i16, i32 or i64, and we lower it to a legal sequence.
12717 // If lowered to the final integer result we return a <result, SDValue()> pair.
12718 // Otherwise we lower it to a sequence ending with a FIST, return a
12719 // <FIST, StackSlot> pair, and the caller is responsible for loading
12720 // the final integer result from StackSlot.
12721 std::pair<SDValue,SDValue>
12722 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12723 bool IsSigned, bool IsReplace) const {
12726 EVT DstTy = Op.getValueType();
12727 EVT TheVT = Op.getOperand(0).getValueType();
12728 auto PtrVT = getPointerTy(DAG.getDataLayout());
12730 if (TheVT == MVT::f16)
12731 // We need to promote the f16 to f32 before using the lowering
12732 // in this routine.
12733 return std::make_pair(SDValue(), SDValue());
12735 assert((TheVT == MVT::f32 ||
12736 TheVT == MVT::f64 ||
12737 TheVT == MVT::f80) &&
12738 "Unexpected FP operand type in FP_TO_INTHelper");
12740 // If using FIST to compute an unsigned i64, we'll need some fixup
12741 // to handle values above the maximum signed i64. A FIST is always
12742 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12743 bool UnsignedFixup = !IsSigned &&
12744 DstTy == MVT::i64 &&
12745 (!Subtarget->is64Bit() ||
12746 !isScalarFPTypeInSSEReg(TheVT));
12748 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12749 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12750 // The low 32 bits of the fist result will have the correct uint32 result.
12751 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12755 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12756 DstTy.getSimpleVT() >= MVT::i16 &&
12757 "Unknown FP_TO_INT to lower!");
12759 // These are really Legal.
12760 if (DstTy == MVT::i32 &&
12761 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12762 return std::make_pair(SDValue(), SDValue());
12763 if (Subtarget->is64Bit() &&
12764 DstTy == MVT::i64 &&
12765 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12766 return std::make_pair(SDValue(), SDValue());
12768 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12770 MachineFunction &MF = DAG.getMachineFunction();
12771 unsigned MemSize = DstTy.getSizeInBits()/8;
12772 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12773 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12776 switch (DstTy.getSimpleVT().SimpleTy) {
12777 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12778 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12779 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12780 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12783 SDValue Chain = DAG.getEntryNode();
12784 SDValue Value = Op.getOperand(0);
12785 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12787 if (UnsignedFixup) {
12789 // Conversion to unsigned i64 is implemented with a select,
12790 // depending on whether the source value fits in the range
12791 // of a signed i64. Let Thresh be the FP equivalent of
12792 // 0x8000000000000000ULL.
12794 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12795 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12796 // Fist-to-mem64 FistSrc
12797 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12798 // to XOR'ing the high 32 bits with Adjust.
12800 // Being a power of 2, Thresh is exactly representable in all FP formats.
12801 // For X87 we'd like to use the smallest FP type for this constant, but
12802 // for DAG type consistency we have to match the FP operand type.
12804 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12805 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12806 bool LosesInfo = false;
12807 if (TheVT == MVT::f64)
12808 // The rounding mode is irrelevant as the conversion should be exact.
12809 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12811 else if (TheVT == MVT::f80)
12812 Status = Thresh.convert(APFloat::x87DoubleExtended,
12813 APFloat::rmNearestTiesToEven, &LosesInfo);
12815 assert(Status == APFloat::opOK && !LosesInfo &&
12816 "FP conversion should have been exact");
12818 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12820 SDValue Cmp = DAG.getSetCC(DL,
12821 getSetCCResultType(DAG.getDataLayout(),
12822 *DAG.getContext(), TheVT),
12823 Value, ThreshVal, ISD::SETLT);
12824 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12825 DAG.getConstant(0, DL, MVT::i32),
12826 DAG.getConstant(0x80000000, DL, MVT::i32));
12827 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12828 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12829 *DAG.getContext(), TheVT),
12830 Value, ThreshVal, ISD::SETLT);
12831 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12834 // FIXME This causes a redundant load/store if the SSE-class value is already
12835 // in memory, such as if it is on the callstack.
12836 if (isScalarFPTypeInSSEReg(TheVT)) {
12837 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12838 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12839 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12841 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12843 Chain, StackSlot, DAG.getValueType(TheVT)
12846 MachineMemOperand *MMO =
12847 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12848 MachineMemOperand::MOLoad, MemSize, MemSize);
12849 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12850 Chain = Value.getValue(1);
12851 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12852 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12855 MachineMemOperand *MMO =
12856 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12857 MachineMemOperand::MOStore, MemSize, MemSize);
12859 if (UnsignedFixup) {
12861 // Insert the FIST, load its result as two i32's,
12862 // and XOR the high i32 with Adjust.
12864 SDValue FistOps[] = { Chain, Value, StackSlot };
12865 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12866 FistOps, DstTy, MMO);
12868 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12869 MachinePointerInfo(),
12870 false, false, false, 0);
12871 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12872 DAG.getConstant(4, DL, PtrVT));
12874 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12875 MachinePointerInfo(),
12876 false, false, false, 0);
12877 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12879 if (Subtarget->is64Bit()) {
12880 // Join High32 and Low32 into a 64-bit result.
12881 // (High32 << 32) | Low32
12882 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12883 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12884 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12885 DAG.getConstant(32, DL, MVT::i8));
12886 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12887 return std::make_pair(Result, SDValue());
12890 SDValue ResultOps[] = { Low32, High32 };
12892 SDValue pair = IsReplace
12893 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12894 : DAG.getMergeValues(ResultOps, DL);
12895 return std::make_pair(pair, SDValue());
12897 // Build the FP_TO_INT*_IN_MEM
12898 SDValue Ops[] = { Chain, Value, StackSlot };
12899 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12901 return std::make_pair(FIST, StackSlot);
12905 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12906 const X86Subtarget *Subtarget) {
12907 MVT VT = Op->getSimpleValueType(0);
12908 SDValue In = Op->getOperand(0);
12909 MVT InVT = In.getSimpleValueType();
12912 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12913 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12915 // Optimize vectors in AVX mode:
12918 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12919 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12920 // Concat upper and lower parts.
12923 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12924 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12925 // Concat upper and lower parts.
12928 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12929 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12930 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12933 if (Subtarget->hasInt256())
12934 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12936 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12937 SDValue Undef = DAG.getUNDEF(InVT);
12938 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12939 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12940 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12942 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12943 VT.getVectorNumElements()/2);
12945 OpLo = DAG.getBitcast(HVT, OpLo);
12946 OpHi = DAG.getBitcast(HVT, OpHi);
12948 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12951 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12952 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12953 MVT VT = Op->getSimpleValueType(0);
12954 SDValue In = Op->getOperand(0);
12955 MVT InVT = In.getSimpleValueType();
12957 unsigned int NumElts = VT.getVectorNumElements();
12958 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12961 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12962 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12964 assert(InVT.getVectorElementType() == MVT::i1);
12965 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12967 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12969 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12971 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12972 if (VT.is512BitVector())
12974 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12977 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12978 SelectionDAG &DAG) {
12979 if (Subtarget->hasFp256())
12980 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12986 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12987 SelectionDAG &DAG) {
12989 MVT VT = Op.getSimpleValueType();
12990 SDValue In = Op.getOperand(0);
12991 MVT SVT = In.getSimpleValueType();
12993 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12994 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12996 if (Subtarget->hasFp256())
12997 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13000 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13001 VT.getVectorNumElements() != SVT.getVectorNumElements());
13005 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13007 MVT VT = Op.getSimpleValueType();
13008 SDValue In = Op.getOperand(0);
13009 MVT InVT = In.getSimpleValueType();
13011 if (VT == MVT::i1) {
13012 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13013 "Invalid scalar TRUNCATE operation");
13014 if (InVT.getSizeInBits() >= 32)
13016 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13017 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13019 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13020 "Invalid TRUNCATE operation");
13022 // move vector to mask - truncate solution for SKX
13023 if (VT.getVectorElementType() == MVT::i1) {
13024 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13025 Subtarget->hasBWI())
13026 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13027 if ((InVT.is256BitVector() || InVT.is128BitVector())
13028 && InVT.getScalarSizeInBits() <= 16 &&
13029 Subtarget->hasBWI() && Subtarget->hasVLX())
13030 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13031 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13032 Subtarget->hasDQI())
13033 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13034 if ((InVT.is256BitVector() || InVT.is128BitVector())
13035 && InVT.getScalarSizeInBits() >= 32 &&
13036 Subtarget->hasDQI() && Subtarget->hasVLX())
13037 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13040 if (VT.getVectorElementType() == MVT::i1) {
13041 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13042 unsigned NumElts = InVT.getVectorNumElements();
13043 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13044 if (InVT.getSizeInBits() < 512) {
13045 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13046 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13051 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13052 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13053 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13056 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13057 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13058 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13059 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13061 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13062 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13063 if (Subtarget->hasInt256()) {
13064 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13065 In = DAG.getBitcast(MVT::v8i32, In);
13066 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13068 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13069 DAG.getIntPtrConstant(0, DL));
13072 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13073 DAG.getIntPtrConstant(0, DL));
13074 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13075 DAG.getIntPtrConstant(2, DL));
13076 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13077 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13078 static const int ShufMask[] = {0, 2, 4, 6};
13079 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13082 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13083 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13084 if (Subtarget->hasInt256()) {
13085 In = DAG.getBitcast(MVT::v32i8, In);
13087 SmallVector<SDValue,32> pshufbMask;
13088 for (unsigned i = 0; i < 2; ++i) {
13089 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13090 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13091 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13092 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13093 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13094 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13095 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13096 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13097 for (unsigned j = 0; j < 8; ++j)
13098 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13100 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13101 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13102 In = DAG.getBitcast(MVT::v4i64, In);
13104 static const int ShufMask[] = {0, 2, -1, -1};
13105 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13107 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13108 DAG.getIntPtrConstant(0, DL));
13109 return DAG.getBitcast(VT, In);
13112 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13113 DAG.getIntPtrConstant(0, DL));
13115 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13116 DAG.getIntPtrConstant(4, DL));
13118 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13119 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13121 // The PSHUFB mask:
13122 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13123 -1, -1, -1, -1, -1, -1, -1, -1};
13125 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13126 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13127 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13129 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13130 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13132 // The MOVLHPS Mask:
13133 static const int ShufMask2[] = {0, 1, 4, 5};
13134 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13135 return DAG.getBitcast(MVT::v8i16, res);
13138 // Handle truncation of V256 to V128 using shuffles.
13139 if (!VT.is128BitVector() || !InVT.is256BitVector())
13142 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13144 unsigned NumElems = VT.getVectorNumElements();
13145 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13147 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13148 // Prepare truncation shuffle mask
13149 for (unsigned i = 0; i != NumElems; ++i)
13150 MaskVec[i] = i * 2;
13151 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13152 DAG.getUNDEF(NVT), &MaskVec[0]);
13153 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13154 DAG.getIntPtrConstant(0, DL));
13157 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13158 SelectionDAG &DAG) const {
13159 assert(!Op.getSimpleValueType().isVector());
13161 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13162 /*IsSigned=*/ true, /*IsReplace=*/ false);
13163 SDValue FIST = Vals.first, StackSlot = Vals.second;
13164 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13165 if (!FIST.getNode())
13168 if (StackSlot.getNode())
13169 // Load the result.
13170 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13171 FIST, StackSlot, MachinePointerInfo(),
13172 false, false, false, 0);
13174 // The node is the result.
13178 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13179 SelectionDAG &DAG) const {
13180 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13181 /*IsSigned=*/ false, /*IsReplace=*/ false);
13182 SDValue FIST = Vals.first, StackSlot = Vals.second;
13183 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13184 if (!FIST.getNode())
13187 if (StackSlot.getNode())
13188 // Load the result.
13189 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13190 FIST, StackSlot, MachinePointerInfo(),
13191 false, false, false, 0);
13193 // The node is the result.
13197 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13199 MVT VT = Op.getSimpleValueType();
13200 SDValue In = Op.getOperand(0);
13201 MVT SVT = In.getSimpleValueType();
13203 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13205 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13206 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13207 In, DAG.getUNDEF(SVT)));
13210 /// The only differences between FABS and FNEG are the mask and the logic op.
13211 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13212 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13213 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13214 "Wrong opcode for lowering FABS or FNEG.");
13216 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13218 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13219 // into an FNABS. We'll lower the FABS after that if it is still in use.
13221 for (SDNode *User : Op->uses())
13222 if (User->getOpcode() == ISD::FNEG)
13226 MVT VT = Op.getSimpleValueType();
13228 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13229 // decide if we should generate a 16-byte constant mask when we only need 4 or
13230 // 8 bytes for the scalar case.
13236 if (VT.isVector()) {
13238 EltVT = VT.getVectorElementType();
13239 NumElts = VT.getVectorNumElements();
13241 // There are no scalar bitwise logical SSE/AVX instructions, so we
13242 // generate a 16-byte vector constant and logic op even for the scalar case.
13243 // Using a 16-byte mask allows folding the load of the mask with
13244 // the logic op, so it can save (~4 bytes) on code size.
13245 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13247 NumElts = (VT == MVT::f64) ? 2 : 4;
13250 unsigned EltBits = EltVT.getSizeInBits();
13251 LLVMContext *Context = DAG.getContext();
13252 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13254 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13255 Constant *C = ConstantInt::get(*Context, MaskElt);
13256 C = ConstantVector::getSplat(NumElts, C);
13257 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13258 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13259 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13261 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13262 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13263 false, false, false, Alignment);
13265 SDValue Op0 = Op.getOperand(0);
13266 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13268 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13269 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13272 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13274 // For the scalar case extend to a 128-bit vector, perform the logic op,
13275 // and extract the scalar result back out.
13276 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13277 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13278 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13279 DAG.getIntPtrConstant(0, dl));
13282 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13283 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13284 LLVMContext *Context = DAG.getContext();
13285 SDValue Op0 = Op.getOperand(0);
13286 SDValue Op1 = Op.getOperand(1);
13288 MVT VT = Op.getSimpleValueType();
13289 MVT SrcVT = Op1.getSimpleValueType();
13291 // If second operand is smaller, extend it first.
13292 if (SrcVT.bitsLT(VT)) {
13293 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13296 // And if it is bigger, shrink it first.
13297 if (SrcVT.bitsGT(VT)) {
13298 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13302 // At this point the operands and the result should have the same
13303 // type, and that won't be f80 since that is not custom lowered.
13305 const fltSemantics &Sem =
13306 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13307 const unsigned SizeInBits = VT.getSizeInBits();
13309 SmallVector<Constant *, 4> CV(
13310 VT == MVT::f64 ? 2 : 4,
13311 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13313 // First, clear all bits but the sign bit from the second operand (sign).
13314 CV[0] = ConstantFP::get(*Context,
13315 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13316 Constant *C = ConstantVector::get(CV);
13317 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13318 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13320 // Perform all logic operations as 16-byte vectors because there are no
13321 // scalar FP logic instructions in SSE. This allows load folding of the
13322 // constants into the logic instructions.
13323 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13325 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13326 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13327 false, false, false, 16);
13328 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13329 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13331 // Next, clear the sign bit from the first operand (magnitude).
13332 // If it's a constant, we can clear it here.
13333 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13334 APFloat APF = Op0CN->getValueAPF();
13335 // If the magnitude is a positive zero, the sign bit alone is enough.
13336 if (APF.isPosZero())
13337 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13338 DAG.getIntPtrConstant(0, dl));
13340 CV[0] = ConstantFP::get(*Context, APF);
13342 CV[0] = ConstantFP::get(
13344 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13346 C = ConstantVector::get(CV);
13347 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13349 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13350 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13351 false, false, false, 16);
13352 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13353 if (!isa<ConstantFPSDNode>(Op0)) {
13354 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13355 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13357 // OR the magnitude value with the sign bit.
13358 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13359 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13360 DAG.getIntPtrConstant(0, dl));
13363 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13364 SDValue N0 = Op.getOperand(0);
13366 MVT VT = Op.getSimpleValueType();
13368 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13369 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13370 DAG.getConstant(1, dl, VT));
13371 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13374 // Check whether an OR'd tree is PTEST-able.
13375 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13376 SelectionDAG &DAG) {
13377 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13379 if (!Subtarget->hasSSE41())
13382 if (!Op->hasOneUse())
13385 SDNode *N = Op.getNode();
13388 SmallVector<SDValue, 8> Opnds;
13389 DenseMap<SDValue, unsigned> VecInMap;
13390 SmallVector<SDValue, 8> VecIns;
13391 EVT VT = MVT::Other;
13393 // Recognize a special case where a vector is casted into wide integer to
13395 Opnds.push_back(N->getOperand(0));
13396 Opnds.push_back(N->getOperand(1));
13398 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13399 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13400 // BFS traverse all OR'd operands.
13401 if (I->getOpcode() == ISD::OR) {
13402 Opnds.push_back(I->getOperand(0));
13403 Opnds.push_back(I->getOperand(1));
13404 // Re-evaluate the number of nodes to be traversed.
13405 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13409 // Quit if a non-EXTRACT_VECTOR_ELT
13410 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13413 // Quit if without a constant index.
13414 SDValue Idx = I->getOperand(1);
13415 if (!isa<ConstantSDNode>(Idx))
13418 SDValue ExtractedFromVec = I->getOperand(0);
13419 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13420 if (M == VecInMap.end()) {
13421 VT = ExtractedFromVec.getValueType();
13422 // Quit if not 128/256-bit vector.
13423 if (!VT.is128BitVector() && !VT.is256BitVector())
13425 // Quit if not the same type.
13426 if (VecInMap.begin() != VecInMap.end() &&
13427 VT != VecInMap.begin()->first.getValueType())
13429 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13430 VecIns.push_back(ExtractedFromVec);
13432 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13435 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13436 "Not extracted from 128-/256-bit vector.");
13438 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13440 for (DenseMap<SDValue, unsigned>::const_iterator
13441 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13442 // Quit if not all elements are used.
13443 if (I->second != FullMask)
13447 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13449 // Cast all vectors into TestVT for PTEST.
13450 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13451 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13453 // If more than one full vectors are evaluated, OR them first before PTEST.
13454 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13455 // Each iteration will OR 2 nodes and append the result until there is only
13456 // 1 node left, i.e. the final OR'd value of all vectors.
13457 SDValue LHS = VecIns[Slot];
13458 SDValue RHS = VecIns[Slot + 1];
13459 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13462 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13463 VecIns.back(), VecIns.back());
13466 /// \brief return true if \c Op has a use that doesn't just read flags.
13467 static bool hasNonFlagsUse(SDValue Op) {
13468 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13470 SDNode *User = *UI;
13471 unsigned UOpNo = UI.getOperandNo();
13472 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13473 // Look pass truncate.
13474 UOpNo = User->use_begin().getOperandNo();
13475 User = *User->use_begin();
13478 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13479 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13485 /// Emit nodes that will be selected as "test Op0,Op0", or something
13487 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13488 SelectionDAG &DAG) const {
13489 if (Op.getValueType() == MVT::i1) {
13490 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13491 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13492 DAG.getConstant(0, dl, MVT::i8));
13494 // CF and OF aren't always set the way we want. Determine which
13495 // of these we need.
13496 bool NeedCF = false;
13497 bool NeedOF = false;
13500 case X86::COND_A: case X86::COND_AE:
13501 case X86::COND_B: case X86::COND_BE:
13504 case X86::COND_G: case X86::COND_GE:
13505 case X86::COND_L: case X86::COND_LE:
13506 case X86::COND_O: case X86::COND_NO: {
13507 // Check if we really need to set the
13508 // Overflow flag. If NoSignedWrap is present
13509 // that is not actually needed.
13510 switch (Op->getOpcode()) {
13515 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13516 if (BinNode->Flags.hasNoSignedWrap())
13526 // See if we can use the EFLAGS value from the operand instead of
13527 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13528 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13529 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13530 // Emit a CMP with 0, which is the TEST pattern.
13531 //if (Op.getValueType() == MVT::i1)
13532 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13533 // DAG.getConstant(0, MVT::i1));
13534 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13535 DAG.getConstant(0, dl, Op.getValueType()));
13537 unsigned Opcode = 0;
13538 unsigned NumOperands = 0;
13540 // Truncate operations may prevent the merge of the SETCC instruction
13541 // and the arithmetic instruction before it. Attempt to truncate the operands
13542 // of the arithmetic instruction and use a reduced bit-width instruction.
13543 bool NeedTruncation = false;
13544 SDValue ArithOp = Op;
13545 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13546 SDValue Arith = Op->getOperand(0);
13547 // Both the trunc and the arithmetic op need to have one user each.
13548 if (Arith->hasOneUse())
13549 switch (Arith.getOpcode()) {
13556 NeedTruncation = true;
13562 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13563 // which may be the result of a CAST. We use the variable 'Op', which is the
13564 // non-casted variable when we check for possible users.
13565 switch (ArithOp.getOpcode()) {
13567 // Due to an isel shortcoming, be conservative if this add is likely to be
13568 // selected as part of a load-modify-store instruction. When the root node
13569 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13570 // uses of other nodes in the match, such as the ADD in this case. This
13571 // leads to the ADD being left around and reselected, with the result being
13572 // two adds in the output. Alas, even if none our users are stores, that
13573 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13574 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13575 // climbing the DAG back to the root, and it doesn't seem to be worth the
13577 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13578 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13579 if (UI->getOpcode() != ISD::CopyToReg &&
13580 UI->getOpcode() != ISD::SETCC &&
13581 UI->getOpcode() != ISD::STORE)
13584 if (ConstantSDNode *C =
13585 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13586 // An add of one will be selected as an INC.
13587 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13588 Opcode = X86ISD::INC;
13593 // An add of negative one (subtract of one) will be selected as a DEC.
13594 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13595 Opcode = X86ISD::DEC;
13601 // Otherwise use a regular EFLAGS-setting add.
13602 Opcode = X86ISD::ADD;
13607 // If we have a constant logical shift that's only used in a comparison
13608 // against zero turn it into an equivalent AND. This allows turning it into
13609 // a TEST instruction later.
13610 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13611 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13612 EVT VT = Op.getValueType();
13613 unsigned BitWidth = VT.getSizeInBits();
13614 unsigned ShAmt = Op->getConstantOperandVal(1);
13615 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13617 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13618 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13619 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13620 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13622 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13623 DAG.getConstant(Mask, dl, VT));
13624 DAG.ReplaceAllUsesWith(Op, New);
13630 // If the primary and result isn't used, don't bother using X86ISD::AND,
13631 // because a TEST instruction will be better.
13632 if (!hasNonFlagsUse(Op))
13638 // Due to the ISEL shortcoming noted above, be conservative if this op is
13639 // likely to be selected as part of a load-modify-store instruction.
13640 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13641 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13642 if (UI->getOpcode() == ISD::STORE)
13645 // Otherwise use a regular EFLAGS-setting instruction.
13646 switch (ArithOp.getOpcode()) {
13647 default: llvm_unreachable("unexpected operator!");
13648 case ISD::SUB: Opcode = X86ISD::SUB; break;
13649 case ISD::XOR: Opcode = X86ISD::XOR; break;
13650 case ISD::AND: Opcode = X86ISD::AND; break;
13652 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13653 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13654 if (EFLAGS.getNode())
13657 Opcode = X86ISD::OR;
13671 return SDValue(Op.getNode(), 1);
13677 // If we found that truncation is beneficial, perform the truncation and
13679 if (NeedTruncation) {
13680 EVT VT = Op.getValueType();
13681 SDValue WideVal = Op->getOperand(0);
13682 EVT WideVT = WideVal.getValueType();
13683 unsigned ConvertedOp = 0;
13684 // Use a target machine opcode to prevent further DAGCombine
13685 // optimizations that may separate the arithmetic operations
13686 // from the setcc node.
13687 switch (WideVal.getOpcode()) {
13689 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13690 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13691 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13692 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13693 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13697 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13698 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13699 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13700 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13701 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13707 // Emit a CMP with 0, which is the TEST pattern.
13708 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13709 DAG.getConstant(0, dl, Op.getValueType()));
13711 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13712 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13714 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13715 DAG.ReplaceAllUsesWith(Op, New);
13716 return SDValue(New.getNode(), 1);
13719 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13721 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13722 SDLoc dl, SelectionDAG &DAG) const {
13723 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13724 if (C->getAPIntValue() == 0)
13725 return EmitTest(Op0, X86CC, dl, DAG);
13727 if (Op0.getValueType() == MVT::i1)
13728 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13731 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13732 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13733 // Do the comparison at i32 if it's smaller, besides the Atom case.
13734 // This avoids subregister aliasing issues. Keep the smaller reference
13735 // if we're optimizing for size, however, as that'll allow better folding
13736 // of memory operations.
13737 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13738 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13739 !Subtarget->isAtom()) {
13740 unsigned ExtendOp =
13741 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13742 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13743 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13745 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13746 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13747 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13749 return SDValue(Sub.getNode(), 1);
13751 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13754 /// Convert a comparison if required by the subtarget.
13755 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13756 SelectionDAG &DAG) const {
13757 // If the subtarget does not support the FUCOMI instruction, floating-point
13758 // comparisons have to be converted.
13759 if (Subtarget->hasCMov() ||
13760 Cmp.getOpcode() != X86ISD::CMP ||
13761 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13762 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13765 // The instruction selector will select an FUCOM instruction instead of
13766 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13767 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13768 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13770 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13771 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13772 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13773 DAG.getConstant(8, dl, MVT::i8));
13774 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13775 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13778 /// The minimum architected relative accuracy is 2^-12. We need one
13779 /// Newton-Raphson step to have a good float result (24 bits of precision).
13780 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13781 DAGCombinerInfo &DCI,
13782 unsigned &RefinementSteps,
13783 bool &UseOneConstNR) const {
13784 EVT VT = Op.getValueType();
13785 const char *RecipOp;
13787 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13788 // TODO: Add support for AVX512 (v16f32).
13789 // It is likely not profitable to do this for f64 because a double-precision
13790 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13791 // instructions: convert to single, rsqrtss, convert back to double, refine
13792 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13793 // along with FMA, this could be a throughput win.
13794 if (VT == MVT::f32 && Subtarget->hasSSE1())
13796 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13797 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13798 RecipOp = "vec-sqrtf";
13802 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13803 if (!Recips.isEnabled(RecipOp))
13806 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13807 UseOneConstNR = false;
13808 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13811 /// The minimum architected relative accuracy is 2^-12. We need one
13812 /// Newton-Raphson step to have a good float result (24 bits of precision).
13813 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13814 DAGCombinerInfo &DCI,
13815 unsigned &RefinementSteps) const {
13816 EVT VT = Op.getValueType();
13817 const char *RecipOp;
13819 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13820 // TODO: Add support for AVX512 (v16f32).
13821 // It is likely not profitable to do this for f64 because a double-precision
13822 // reciprocal estimate with refinement on x86 prior to FMA requires
13823 // 15 instructions: convert to single, rcpss, convert back to double, refine
13824 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13825 // along with FMA, this could be a throughput win.
13826 if (VT == MVT::f32 && Subtarget->hasSSE1())
13828 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13829 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13830 RecipOp = "vec-divf";
13834 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13835 if (!Recips.isEnabled(RecipOp))
13838 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13839 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13842 /// If we have at least two divisions that use the same divisor, convert to
13843 /// multplication by a reciprocal. This may need to be adjusted for a given
13844 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13845 /// This is because we still need one division to calculate the reciprocal and
13846 /// then we need two multiplies by that reciprocal as replacements for the
13847 /// original divisions.
13848 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13852 static bool isAllOnes(SDValue V) {
13853 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13854 return C && C->isAllOnesValue();
13857 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13858 /// if it's possible.
13859 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13860 SDLoc dl, SelectionDAG &DAG) const {
13861 SDValue Op0 = And.getOperand(0);
13862 SDValue Op1 = And.getOperand(1);
13863 if (Op0.getOpcode() == ISD::TRUNCATE)
13864 Op0 = Op0.getOperand(0);
13865 if (Op1.getOpcode() == ISD::TRUNCATE)
13866 Op1 = Op1.getOperand(0);
13869 if (Op1.getOpcode() == ISD::SHL)
13870 std::swap(Op0, Op1);
13871 if (Op0.getOpcode() == ISD::SHL) {
13872 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13873 if (And00C->getZExtValue() == 1) {
13874 // If we looked past a truncate, check that it's only truncating away
13876 unsigned BitWidth = Op0.getValueSizeInBits();
13877 unsigned AndBitWidth = And.getValueSizeInBits();
13878 if (BitWidth > AndBitWidth) {
13880 DAG.computeKnownBits(Op0, Zeros, Ones);
13881 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13885 RHS = Op0.getOperand(1);
13887 } else if (Op1.getOpcode() == ISD::Constant) {
13888 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13889 uint64_t AndRHSVal = AndRHS->getZExtValue();
13890 SDValue AndLHS = Op0;
13892 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13893 LHS = AndLHS.getOperand(0);
13894 RHS = AndLHS.getOperand(1);
13897 // Use BT if the immediate can't be encoded in a TEST instruction.
13898 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13900 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13904 if (LHS.getNode()) {
13905 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13906 // instruction. Since the shift amount is in-range-or-undefined, we know
13907 // that doing a bittest on the i32 value is ok. We extend to i32 because
13908 // the encoding for the i16 version is larger than the i32 version.
13909 // Also promote i16 to i32 for performance / code size reason.
13910 if (LHS.getValueType() == MVT::i8 ||
13911 LHS.getValueType() == MVT::i16)
13912 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13914 // If the operand types disagree, extend the shift amount to match. Since
13915 // BT ignores high bits (like shifts) we can use anyextend.
13916 if (LHS.getValueType() != RHS.getValueType())
13917 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13919 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13920 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13921 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13922 DAG.getConstant(Cond, dl, MVT::i8), BT);
13928 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13930 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13935 // SSE Condition code mapping:
13944 switch (SetCCOpcode) {
13945 default: llvm_unreachable("Unexpected SETCC condition");
13947 case ISD::SETEQ: SSECC = 0; break;
13949 case ISD::SETGT: Swap = true; // Fallthrough
13951 case ISD::SETOLT: SSECC = 1; break;
13953 case ISD::SETGE: Swap = true; // Fallthrough
13955 case ISD::SETOLE: SSECC = 2; break;
13956 case ISD::SETUO: SSECC = 3; break;
13958 case ISD::SETNE: SSECC = 4; break;
13959 case ISD::SETULE: Swap = true; // Fallthrough
13960 case ISD::SETUGE: SSECC = 5; break;
13961 case ISD::SETULT: Swap = true; // Fallthrough
13962 case ISD::SETUGT: SSECC = 6; break;
13963 case ISD::SETO: SSECC = 7; break;
13965 case ISD::SETONE: SSECC = 8; break;
13968 std::swap(Op0, Op1);
13973 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13974 // ones, and then concatenate the result back.
13975 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13976 MVT VT = Op.getSimpleValueType();
13978 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13979 "Unsupported value type for operation");
13981 unsigned NumElems = VT.getVectorNumElements();
13983 SDValue CC = Op.getOperand(2);
13985 // Extract the LHS vectors
13986 SDValue LHS = Op.getOperand(0);
13987 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13988 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13990 // Extract the RHS vectors
13991 SDValue RHS = Op.getOperand(1);
13992 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13993 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13995 // Issue the operation on the smaller types and concatenate the result back
13996 MVT EltVT = VT.getVectorElementType();
13997 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13998 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13999 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14000 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14003 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14004 SDValue Op0 = Op.getOperand(0);
14005 SDValue Op1 = Op.getOperand(1);
14006 SDValue CC = Op.getOperand(2);
14007 MVT VT = Op.getSimpleValueType();
14010 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
14011 "Unexpected type for boolean compare operation");
14012 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14013 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14014 DAG.getConstant(-1, dl, VT));
14015 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14016 DAG.getConstant(-1, dl, VT));
14017 switch (SetCCOpcode) {
14018 default: llvm_unreachable("Unexpected SETCC condition");
14020 // (x == y) -> ~(x ^ y)
14021 return DAG.getNode(ISD::XOR, dl, VT,
14022 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14023 DAG.getConstant(-1, dl, VT));
14025 // (x != y) -> (x ^ y)
14026 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14029 // (x > y) -> (x & ~y)
14030 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14033 // (x < y) -> (~x & y)
14034 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14037 // (x <= y) -> (~x | y)
14038 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14041 // (x >=y) -> (x | ~y)
14042 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14046 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14047 const X86Subtarget *Subtarget) {
14048 SDValue Op0 = Op.getOperand(0);
14049 SDValue Op1 = Op.getOperand(1);
14050 SDValue CC = Op.getOperand(2);
14051 MVT VT = Op.getSimpleValueType();
14054 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14055 Op.getValueType().getScalarType() == MVT::i1 &&
14056 "Cannot set masked compare for this operation");
14058 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14060 bool Unsigned = false;
14063 switch (SetCCOpcode) {
14064 default: llvm_unreachable("Unexpected SETCC condition");
14065 case ISD::SETNE: SSECC = 4; break;
14066 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14067 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14068 case ISD::SETLT: Swap = true; //fall-through
14069 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14070 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14071 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14072 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14073 case ISD::SETULE: Unsigned = true; //fall-through
14074 case ISD::SETLE: SSECC = 2; break;
14078 std::swap(Op0, Op1);
14080 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14081 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14082 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14083 DAG.getConstant(SSECC, dl, MVT::i8));
14086 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14087 /// operand \p Op1. If non-trivial (for example because it's not constant)
14088 /// return an empty value.
14089 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14091 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14095 MVT VT = Op1.getSimpleValueType();
14096 MVT EVT = VT.getVectorElementType();
14097 unsigned n = VT.getVectorNumElements();
14098 SmallVector<SDValue, 8> ULTOp1;
14100 for (unsigned i = 0; i < n; ++i) {
14101 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14102 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14105 // Avoid underflow.
14106 APInt Val = Elt->getAPIntValue();
14110 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14113 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14116 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14117 SelectionDAG &DAG) {
14118 SDValue Op0 = Op.getOperand(0);
14119 SDValue Op1 = Op.getOperand(1);
14120 SDValue CC = Op.getOperand(2);
14121 MVT VT = Op.getSimpleValueType();
14122 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14123 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14128 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14129 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14132 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14133 unsigned Opc = X86ISD::CMPP;
14134 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14135 assert(VT.getVectorNumElements() <= 16);
14136 Opc = X86ISD::CMPM;
14138 // In the two special cases we can't handle, emit two comparisons.
14141 unsigned CombineOpc;
14142 if (SetCCOpcode == ISD::SETUEQ) {
14143 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14145 assert(SetCCOpcode == ISD::SETONE);
14146 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14149 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14150 DAG.getConstant(CC0, dl, MVT::i8));
14151 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14152 DAG.getConstant(CC1, dl, MVT::i8));
14153 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14155 // Handle all other FP comparisons here.
14156 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14157 DAG.getConstant(SSECC, dl, MVT::i8));
14160 // Break 256-bit integer vector compare into smaller ones.
14161 if (VT.is256BitVector() && !Subtarget->hasInt256())
14162 return Lower256IntVSETCC(Op, DAG);
14164 EVT OpVT = Op1.getValueType();
14165 if (OpVT.getVectorElementType() == MVT::i1)
14166 return LowerBoolVSETCC_AVX512(Op, DAG);
14168 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14169 if (Subtarget->hasAVX512()) {
14170 if (Op1.getValueType().is512BitVector() ||
14171 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14172 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14173 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14175 // In AVX-512 architecture setcc returns mask with i1 elements,
14176 // But there is no compare instruction for i8 and i16 elements in KNL.
14177 // We are not talking about 512-bit operands in this case, these
14178 // types are illegal.
14180 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14181 OpVT.getVectorElementType().getSizeInBits() >= 8))
14182 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14183 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14186 // We are handling one of the integer comparisons here. Since SSE only has
14187 // GT and EQ comparisons for integer, swapping operands and multiple
14188 // operations may be required for some comparisons.
14190 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14191 bool Subus = false;
14193 switch (SetCCOpcode) {
14194 default: llvm_unreachable("Unexpected SETCC condition");
14195 case ISD::SETNE: Invert = true;
14196 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14197 case ISD::SETLT: Swap = true;
14198 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14199 case ISD::SETGE: Swap = true;
14200 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14201 Invert = true; break;
14202 case ISD::SETULT: Swap = true;
14203 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14204 FlipSigns = true; break;
14205 case ISD::SETUGE: Swap = true;
14206 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14207 FlipSigns = true; Invert = true; break;
14210 // Special case: Use min/max operations for SETULE/SETUGE
14211 MVT VET = VT.getVectorElementType();
14213 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14214 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14217 switch (SetCCOpcode) {
14219 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14220 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14223 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14226 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14227 if (!MinMax && hasSubus) {
14228 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14230 // t = psubus Op0, Op1
14231 // pcmpeq t, <0..0>
14232 switch (SetCCOpcode) {
14234 case ISD::SETULT: {
14235 // If the comparison is against a constant we can turn this into a
14236 // setule. With psubus, setule does not require a swap. This is
14237 // beneficial because the constant in the register is no longer
14238 // destructed as the destination so it can be hoisted out of a loop.
14239 // Only do this pre-AVX since vpcmp* is no longer destructive.
14240 if (Subtarget->hasAVX())
14242 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14243 if (ULEOp1.getNode()) {
14245 Subus = true; Invert = false; Swap = false;
14249 // Psubus is better than flip-sign because it requires no inversion.
14250 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14251 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14255 Opc = X86ISD::SUBUS;
14261 std::swap(Op0, Op1);
14263 // Check that the operation in question is available (most are plain SSE2,
14264 // but PCMPGTQ and PCMPEQQ have different requirements).
14265 if (VT == MVT::v2i64) {
14266 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14267 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14269 // First cast everything to the right type.
14270 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14271 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14273 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14274 // bits of the inputs before performing those operations. The lower
14275 // compare is always unsigned.
14278 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14280 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14281 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14282 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14283 Sign, Zero, Sign, Zero);
14285 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14286 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14288 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14289 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14290 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14292 // Create masks for only the low parts/high parts of the 64 bit integers.
14293 static const int MaskHi[] = { 1, 1, 3, 3 };
14294 static const int MaskLo[] = { 0, 0, 2, 2 };
14295 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14296 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14297 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14299 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14300 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14303 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14305 return DAG.getBitcast(VT, Result);
14308 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14309 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14310 // pcmpeqd + pshufd + pand.
14311 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14313 // First cast everything to the right type.
14314 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14315 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14318 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14320 // Make sure the lower and upper halves are both all-ones.
14321 static const int Mask[] = { 1, 0, 3, 2 };
14322 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14323 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14326 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14328 return DAG.getBitcast(VT, Result);
14332 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14333 // bits of the inputs before performing those operations.
14335 EVT EltVT = VT.getVectorElementType();
14336 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14338 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14339 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14342 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14344 // If the logical-not of the result is required, perform that now.
14346 Result = DAG.getNOT(dl, Result, VT);
14349 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14352 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14353 getZeroVector(VT, Subtarget, DAG, dl));
14358 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14360 MVT VT = Op.getSimpleValueType();
14362 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14364 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14365 && "SetCC type must be 8-bit or 1-bit integer");
14366 SDValue Op0 = Op.getOperand(0);
14367 SDValue Op1 = Op.getOperand(1);
14369 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14371 // Optimize to BT if possible.
14372 // Lower (X & (1 << N)) == 0 to BT(X, N).
14373 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14374 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14375 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14376 Op1.getOpcode() == ISD::Constant &&
14377 cast<ConstantSDNode>(Op1)->isNullValue() &&
14378 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14379 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14380 if (NewSetCC.getNode()) {
14382 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14387 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14389 if (Op1.getOpcode() == ISD::Constant &&
14390 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14391 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14392 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14394 // If the input is a setcc, then reuse the input setcc or use a new one with
14395 // the inverted condition.
14396 if (Op0.getOpcode() == X86ISD::SETCC) {
14397 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14398 bool Invert = (CC == ISD::SETNE) ^
14399 cast<ConstantSDNode>(Op1)->isNullValue();
14403 CCode = X86::GetOppositeBranchCondition(CCode);
14404 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14405 DAG.getConstant(CCode, dl, MVT::i8),
14406 Op0.getOperand(1));
14408 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14412 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14413 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14414 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14416 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14417 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14420 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14421 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14422 if (X86CC == X86::COND_INVALID)
14425 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14426 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14427 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14428 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14430 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14434 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14435 static bool isX86LogicalCmp(SDValue Op) {
14436 unsigned Opc = Op.getNode()->getOpcode();
14437 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14438 Opc == X86ISD::SAHF)
14440 if (Op.getResNo() == 1 &&
14441 (Opc == X86ISD::ADD ||
14442 Opc == X86ISD::SUB ||
14443 Opc == X86ISD::ADC ||
14444 Opc == X86ISD::SBB ||
14445 Opc == X86ISD::SMUL ||
14446 Opc == X86ISD::UMUL ||
14447 Opc == X86ISD::INC ||
14448 Opc == X86ISD::DEC ||
14449 Opc == X86ISD::OR ||
14450 Opc == X86ISD::XOR ||
14451 Opc == X86ISD::AND))
14454 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14460 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14461 if (V.getOpcode() != ISD::TRUNCATE)
14464 SDValue VOp0 = V.getOperand(0);
14465 unsigned InBits = VOp0.getValueSizeInBits();
14466 unsigned Bits = V.getValueSizeInBits();
14467 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14470 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14471 bool addTest = true;
14472 SDValue Cond = Op.getOperand(0);
14473 SDValue Op1 = Op.getOperand(1);
14474 SDValue Op2 = Op.getOperand(2);
14476 EVT VT = Op1.getValueType();
14479 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14480 // are available or VBLENDV if AVX is available.
14481 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14482 if (Cond.getOpcode() == ISD::SETCC &&
14483 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14484 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14485 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14486 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14487 int SSECC = translateX86FSETCC(
14488 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14491 if (Subtarget->hasAVX512()) {
14492 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14493 DAG.getConstant(SSECC, DL, MVT::i8));
14494 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14497 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14498 DAG.getConstant(SSECC, DL, MVT::i8));
14500 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14501 // of 3 logic instructions for size savings and potentially speed.
14502 // Unfortunately, there is no scalar form of VBLENDV.
14504 // If either operand is a constant, don't try this. We can expect to
14505 // optimize away at least one of the logic instructions later in that
14506 // case, so that sequence would be faster than a variable blend.
14508 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14509 // uses XMM0 as the selection register. That may need just as many
14510 // instructions as the AND/ANDN/OR sequence due to register moves, so
14513 if (Subtarget->hasAVX() &&
14514 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14516 // Convert to vectors, do a VSELECT, and convert back to scalar.
14517 // All of the conversions should be optimized away.
14519 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14520 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14521 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14522 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14524 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14525 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14527 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14529 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14530 VSel, DAG.getIntPtrConstant(0, DL));
14532 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14533 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14534 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14538 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14540 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14541 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14542 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14543 Op1Scalar = Op1.getOperand(0);
14545 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14546 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14547 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14548 Op2Scalar = Op2.getOperand(0);
14549 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14550 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14551 Op1Scalar.getValueType(),
14552 Cond, Op1Scalar, Op2Scalar);
14553 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14554 return DAG.getBitcast(VT, newSelect);
14555 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14556 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14557 DAG.getIntPtrConstant(0, DL));
14561 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14562 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14563 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14564 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14565 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14566 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14567 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14569 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14572 if (Cond.getOpcode() == ISD::SETCC) {
14573 SDValue NewCond = LowerSETCC(Cond, DAG);
14574 if (NewCond.getNode())
14578 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14579 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14580 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14581 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14582 if (Cond.getOpcode() == X86ISD::SETCC &&
14583 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14584 isZero(Cond.getOperand(1).getOperand(1))) {
14585 SDValue Cmp = Cond.getOperand(1);
14587 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14589 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14590 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14591 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14593 SDValue CmpOp0 = Cmp.getOperand(0);
14594 // Apply further optimizations for special cases
14595 // (select (x != 0), -1, 0) -> neg & sbb
14596 // (select (x == 0), 0, -1) -> neg & sbb
14597 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14598 if (YC->isNullValue() &&
14599 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14600 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14601 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14602 DAG.getConstant(0, DL,
14603 CmpOp0.getValueType()),
14605 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14606 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14607 SDValue(Neg.getNode(), 1));
14611 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14612 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14613 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14615 SDValue Res = // Res = 0 or -1.
14616 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14617 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14619 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14620 Res = DAG.getNOT(DL, Res, Res.getValueType());
14622 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14623 if (!N2C || !N2C->isNullValue())
14624 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14629 // Look past (and (setcc_carry (cmp ...)), 1).
14630 if (Cond.getOpcode() == ISD::AND &&
14631 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14632 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14633 if (C && C->getAPIntValue() == 1)
14634 Cond = Cond.getOperand(0);
14637 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14638 // setting operand in place of the X86ISD::SETCC.
14639 unsigned CondOpcode = Cond.getOpcode();
14640 if (CondOpcode == X86ISD::SETCC ||
14641 CondOpcode == X86ISD::SETCC_CARRY) {
14642 CC = Cond.getOperand(0);
14644 SDValue Cmp = Cond.getOperand(1);
14645 unsigned Opc = Cmp.getOpcode();
14646 MVT VT = Op.getSimpleValueType();
14648 bool IllegalFPCMov = false;
14649 if (VT.isFloatingPoint() && !VT.isVector() &&
14650 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14651 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14653 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14654 Opc == X86ISD::BT) { // FIXME
14658 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14659 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14660 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14661 Cond.getOperand(0).getValueType() != MVT::i8)) {
14662 SDValue LHS = Cond.getOperand(0);
14663 SDValue RHS = Cond.getOperand(1);
14664 unsigned X86Opcode;
14667 switch (CondOpcode) {
14668 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14669 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14670 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14671 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14672 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14673 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14674 default: llvm_unreachable("unexpected overflowing operator");
14676 if (CondOpcode == ISD::UMULO)
14677 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14680 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14682 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14684 if (CondOpcode == ISD::UMULO)
14685 Cond = X86Op.getValue(2);
14687 Cond = X86Op.getValue(1);
14689 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14694 // Look past the truncate if the high bits are known zero.
14695 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14696 Cond = Cond.getOperand(0);
14698 // We know the result of AND is compared against zero. Try to match
14700 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14701 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14702 if (NewSetCC.getNode()) {
14703 CC = NewSetCC.getOperand(0);
14704 Cond = NewSetCC.getOperand(1);
14711 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14712 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14715 // a < b ? -1 : 0 -> RES = ~setcc_carry
14716 // a < b ? 0 : -1 -> RES = setcc_carry
14717 // a >= b ? -1 : 0 -> RES = setcc_carry
14718 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14719 if (Cond.getOpcode() == X86ISD::SUB) {
14720 Cond = ConvertCmpIfNecessary(Cond, DAG);
14721 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14723 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14724 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14725 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14726 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14728 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14729 return DAG.getNOT(DL, Res, Res.getValueType());
14734 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14735 // widen the cmov and push the truncate through. This avoids introducing a new
14736 // branch during isel and doesn't add any extensions.
14737 if (Op.getValueType() == MVT::i8 &&
14738 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14739 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14740 if (T1.getValueType() == T2.getValueType() &&
14741 // Blacklist CopyFromReg to avoid partial register stalls.
14742 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14743 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14744 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14745 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14749 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14750 // condition is true.
14751 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14752 SDValue Ops[] = { Op2, Op1, CC, Cond };
14753 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14756 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14757 const X86Subtarget *Subtarget,
14758 SelectionDAG &DAG) {
14759 MVT VT = Op->getSimpleValueType(0);
14760 SDValue In = Op->getOperand(0);
14761 MVT InVT = In.getSimpleValueType();
14762 MVT VTElt = VT.getVectorElementType();
14763 MVT InVTElt = InVT.getVectorElementType();
14767 if ((InVTElt == MVT::i1) &&
14768 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14769 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14771 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14772 VTElt.getSizeInBits() <= 16)) ||
14774 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14775 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14777 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14778 VTElt.getSizeInBits() >= 32))))
14779 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14781 unsigned int NumElts = VT.getVectorNumElements();
14783 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14786 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14787 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14788 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14789 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14792 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14793 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14795 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14798 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14800 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14801 if (VT.is512BitVector())
14803 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14806 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14807 const X86Subtarget *Subtarget,
14808 SelectionDAG &DAG) {
14809 SDValue In = Op->getOperand(0);
14810 MVT VT = Op->getSimpleValueType(0);
14811 MVT InVT = In.getSimpleValueType();
14812 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14814 MVT InSVT = InVT.getScalarType();
14815 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14817 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14819 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14824 // SSE41 targets can use the pmovsx* instructions directly.
14825 if (Subtarget->hasSSE41())
14826 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14828 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14832 // As SRAI is only available on i16/i32 types, we expand only up to i32
14833 // and handle i64 separately.
14834 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14835 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14836 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14837 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14838 Curr = DAG.getBitcast(CurrVT, Curr);
14841 SDValue SignExt = Curr;
14842 if (CurrVT != InVT) {
14843 unsigned SignExtShift =
14844 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14845 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14846 DAG.getConstant(SignExtShift, dl, MVT::i8));
14852 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14853 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14854 DAG.getConstant(31, dl, MVT::i8));
14855 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14856 return DAG.getBitcast(VT, Ext);
14862 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14863 SelectionDAG &DAG) {
14864 MVT VT = Op->getSimpleValueType(0);
14865 SDValue In = Op->getOperand(0);
14866 MVT InVT = In.getSimpleValueType();
14869 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14870 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14872 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14873 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14874 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14877 if (Subtarget->hasInt256())
14878 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14880 // Optimize vectors in AVX mode
14881 // Sign extend v8i16 to v8i32 and
14884 // Divide input vector into two parts
14885 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14886 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14887 // concat the vectors to original VT
14889 unsigned NumElems = InVT.getVectorNumElements();
14890 SDValue Undef = DAG.getUNDEF(InVT);
14892 SmallVector<int,8> ShufMask1(NumElems, -1);
14893 for (unsigned i = 0; i != NumElems/2; ++i)
14896 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14898 SmallVector<int,8> ShufMask2(NumElems, -1);
14899 for (unsigned i = 0; i != NumElems/2; ++i)
14900 ShufMask2[i] = i + NumElems/2;
14902 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14904 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14905 VT.getVectorNumElements()/2);
14907 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14908 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14910 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14913 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14914 // may emit an illegal shuffle but the expansion is still better than scalar
14915 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14916 // we'll emit a shuffle and a arithmetic shift.
14917 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14918 // TODO: It is possible to support ZExt by zeroing the undef values during
14919 // the shuffle phase or after the shuffle.
14920 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14921 SelectionDAG &DAG) {
14922 MVT RegVT = Op.getSimpleValueType();
14923 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14924 assert(RegVT.isInteger() &&
14925 "We only custom lower integer vector sext loads.");
14927 // Nothing useful we can do without SSE2 shuffles.
14928 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14930 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14932 EVT MemVT = Ld->getMemoryVT();
14933 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14934 unsigned RegSz = RegVT.getSizeInBits();
14936 ISD::LoadExtType Ext = Ld->getExtensionType();
14938 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14939 && "Only anyext and sext are currently implemented.");
14940 assert(MemVT != RegVT && "Cannot extend to the same type");
14941 assert(MemVT.isVector() && "Must load a vector from memory");
14943 unsigned NumElems = RegVT.getVectorNumElements();
14944 unsigned MemSz = MemVT.getSizeInBits();
14945 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14947 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14948 // The only way in which we have a legal 256-bit vector result but not the
14949 // integer 256-bit operations needed to directly lower a sextload is if we
14950 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14951 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14952 // correctly legalized. We do this late to allow the canonical form of
14953 // sextload to persist throughout the rest of the DAG combiner -- it wants
14954 // to fold together any extensions it can, and so will fuse a sign_extend
14955 // of an sextload into a sextload targeting a wider value.
14957 if (MemSz == 128) {
14958 // Just switch this to a normal load.
14959 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14960 "it must be a legal 128-bit vector "
14962 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14963 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14964 Ld->isInvariant(), Ld->getAlignment());
14966 assert(MemSz < 128 &&
14967 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14968 // Do an sext load to a 128-bit vector type. We want to use the same
14969 // number of elements, but elements half as wide. This will end up being
14970 // recursively lowered by this routine, but will succeed as we definitely
14971 // have all the necessary features if we're using AVX1.
14973 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14974 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14976 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14977 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14978 Ld->isNonTemporal(), Ld->isInvariant(),
14979 Ld->getAlignment());
14982 // Replace chain users with the new chain.
14983 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14984 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14986 // Finally, do a normal sign-extend to the desired register.
14987 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14990 // All sizes must be a power of two.
14991 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14992 "Non-power-of-two elements are not custom lowered!");
14994 // Attempt to load the original value using scalar loads.
14995 // Find the largest scalar type that divides the total loaded size.
14996 MVT SclrLoadTy = MVT::i8;
14997 for (MVT Tp : MVT::integer_valuetypes()) {
14998 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15003 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15004 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15006 SclrLoadTy = MVT::f64;
15008 // Calculate the number of scalar loads that we need to perform
15009 // in order to load our vector from memory.
15010 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15012 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15013 "Can only lower sext loads with a single scalar load!");
15015 unsigned loadRegZize = RegSz;
15016 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15019 // Represent our vector as a sequence of elements which are the
15020 // largest scalar that we can load.
15021 EVT LoadUnitVecVT = EVT::getVectorVT(
15022 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15024 // Represent the data using the same element type that is stored in
15025 // memory. In practice, we ''widen'' MemVT.
15027 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15028 loadRegZize / MemVT.getScalarType().getSizeInBits());
15030 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15031 "Invalid vector type");
15033 // We can't shuffle using an illegal type.
15034 assert(TLI.isTypeLegal(WideVecVT) &&
15035 "We only lower types that form legal widened vector types");
15037 SmallVector<SDValue, 8> Chains;
15038 SDValue Ptr = Ld->getBasePtr();
15039 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15040 TLI.getPointerTy(DAG.getDataLayout()));
15041 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15043 for (unsigned i = 0; i < NumLoads; ++i) {
15044 // Perform a single load.
15045 SDValue ScalarLoad =
15046 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15047 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15048 Ld->getAlignment());
15049 Chains.push_back(ScalarLoad.getValue(1));
15050 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15051 // another round of DAGCombining.
15053 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15055 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15056 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15058 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15061 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15063 // Bitcast the loaded value to a vector of the original element type, in
15064 // the size of the target vector type.
15065 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15066 unsigned SizeRatio = RegSz / MemSz;
15068 if (Ext == ISD::SEXTLOAD) {
15069 // If we have SSE4.1, we can directly emit a VSEXT node.
15070 if (Subtarget->hasSSE41()) {
15071 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15072 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15076 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15078 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15079 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15081 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15082 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15086 // Redistribute the loaded elements into the different locations.
15087 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15088 for (unsigned i = 0; i != NumElems; ++i)
15089 ShuffleVec[i * SizeRatio] = i;
15091 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15092 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15094 // Bitcast to the requested type.
15095 Shuff = DAG.getBitcast(RegVT, Shuff);
15096 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15100 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15101 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15102 // from the AND / OR.
15103 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15104 Opc = Op.getOpcode();
15105 if (Opc != ISD::OR && Opc != ISD::AND)
15107 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15108 Op.getOperand(0).hasOneUse() &&
15109 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15110 Op.getOperand(1).hasOneUse());
15113 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15114 // 1 and that the SETCC node has a single use.
15115 static bool isXor1OfSetCC(SDValue Op) {
15116 if (Op.getOpcode() != ISD::XOR)
15118 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15119 if (N1C && N1C->getAPIntValue() == 1) {
15120 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15121 Op.getOperand(0).hasOneUse();
15126 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15127 bool addTest = true;
15128 SDValue Chain = Op.getOperand(0);
15129 SDValue Cond = Op.getOperand(1);
15130 SDValue Dest = Op.getOperand(2);
15133 bool Inverted = false;
15135 if (Cond.getOpcode() == ISD::SETCC) {
15136 // Check for setcc([su]{add,sub,mul}o == 0).
15137 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15138 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15139 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15140 Cond.getOperand(0).getResNo() == 1 &&
15141 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15142 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15143 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15144 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15145 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15146 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15148 Cond = Cond.getOperand(0);
15150 SDValue NewCond = LowerSETCC(Cond, DAG);
15151 if (NewCond.getNode())
15156 // FIXME: LowerXALUO doesn't handle these!!
15157 else if (Cond.getOpcode() == X86ISD::ADD ||
15158 Cond.getOpcode() == X86ISD::SUB ||
15159 Cond.getOpcode() == X86ISD::SMUL ||
15160 Cond.getOpcode() == X86ISD::UMUL)
15161 Cond = LowerXALUO(Cond, DAG);
15164 // Look pass (and (setcc_carry (cmp ...)), 1).
15165 if (Cond.getOpcode() == ISD::AND &&
15166 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15167 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15168 if (C && C->getAPIntValue() == 1)
15169 Cond = Cond.getOperand(0);
15172 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15173 // setting operand in place of the X86ISD::SETCC.
15174 unsigned CondOpcode = Cond.getOpcode();
15175 if (CondOpcode == X86ISD::SETCC ||
15176 CondOpcode == X86ISD::SETCC_CARRY) {
15177 CC = Cond.getOperand(0);
15179 SDValue Cmp = Cond.getOperand(1);
15180 unsigned Opc = Cmp.getOpcode();
15181 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15182 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15186 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15190 // These can only come from an arithmetic instruction with overflow,
15191 // e.g. SADDO, UADDO.
15192 Cond = Cond.getNode()->getOperand(1);
15198 CondOpcode = Cond.getOpcode();
15199 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15200 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15201 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15202 Cond.getOperand(0).getValueType() != MVT::i8)) {
15203 SDValue LHS = Cond.getOperand(0);
15204 SDValue RHS = Cond.getOperand(1);
15205 unsigned X86Opcode;
15208 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15209 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15211 switch (CondOpcode) {
15212 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15214 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15216 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15219 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15220 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15222 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15224 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15227 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15228 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15229 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15230 default: llvm_unreachable("unexpected overflowing operator");
15233 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15234 if (CondOpcode == ISD::UMULO)
15235 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15238 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15240 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15242 if (CondOpcode == ISD::UMULO)
15243 Cond = X86Op.getValue(2);
15245 Cond = X86Op.getValue(1);
15247 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15251 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15252 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15253 if (CondOpc == ISD::OR) {
15254 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15255 // two branches instead of an explicit OR instruction with a
15257 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15258 isX86LogicalCmp(Cmp)) {
15259 CC = Cond.getOperand(0).getOperand(0);
15260 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15261 Chain, Dest, CC, Cmp);
15262 CC = Cond.getOperand(1).getOperand(0);
15266 } else { // ISD::AND
15267 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15268 // two branches instead of an explicit AND instruction with a
15269 // separate test. However, we only do this if this block doesn't
15270 // have a fall-through edge, because this requires an explicit
15271 // jmp when the condition is false.
15272 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15273 isX86LogicalCmp(Cmp) &&
15274 Op.getNode()->hasOneUse()) {
15275 X86::CondCode CCode =
15276 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15277 CCode = X86::GetOppositeBranchCondition(CCode);
15278 CC = DAG.getConstant(CCode, dl, MVT::i8);
15279 SDNode *User = *Op.getNode()->use_begin();
15280 // Look for an unconditional branch following this conditional branch.
15281 // We need this because we need to reverse the successors in order
15282 // to implement FCMP_OEQ.
15283 if (User->getOpcode() == ISD::BR) {
15284 SDValue FalseBB = User->getOperand(1);
15286 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15287 assert(NewBR == User);
15291 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15292 Chain, Dest, CC, Cmp);
15293 X86::CondCode CCode =
15294 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15295 CCode = X86::GetOppositeBranchCondition(CCode);
15296 CC = DAG.getConstant(CCode, dl, MVT::i8);
15302 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15303 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15304 // It should be transformed during dag combiner except when the condition
15305 // is set by a arithmetics with overflow node.
15306 X86::CondCode CCode =
15307 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15308 CCode = X86::GetOppositeBranchCondition(CCode);
15309 CC = DAG.getConstant(CCode, dl, MVT::i8);
15310 Cond = Cond.getOperand(0).getOperand(1);
15312 } else if (Cond.getOpcode() == ISD::SETCC &&
15313 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15314 // For FCMP_OEQ, we can emit
15315 // two branches instead of an explicit AND instruction with a
15316 // separate test. However, we only do this if this block doesn't
15317 // have a fall-through edge, because this requires an explicit
15318 // jmp when the condition is false.
15319 if (Op.getNode()->hasOneUse()) {
15320 SDNode *User = *Op.getNode()->use_begin();
15321 // Look for an unconditional branch following this conditional branch.
15322 // We need this because we need to reverse the successors in order
15323 // to implement FCMP_OEQ.
15324 if (User->getOpcode() == ISD::BR) {
15325 SDValue FalseBB = User->getOperand(1);
15327 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15328 assert(NewBR == User);
15332 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15333 Cond.getOperand(0), Cond.getOperand(1));
15334 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15335 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15336 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15337 Chain, Dest, CC, Cmp);
15338 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15343 } else if (Cond.getOpcode() == ISD::SETCC &&
15344 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15345 // For FCMP_UNE, we can emit
15346 // two branches instead of an explicit AND instruction with a
15347 // separate test. However, we only do this if this block doesn't
15348 // have a fall-through edge, because this requires an explicit
15349 // jmp when the condition is false.
15350 if (Op.getNode()->hasOneUse()) {
15351 SDNode *User = *Op.getNode()->use_begin();
15352 // Look for an unconditional branch following this conditional branch.
15353 // We need this because we need to reverse the successors in order
15354 // to implement FCMP_UNE.
15355 if (User->getOpcode() == ISD::BR) {
15356 SDValue FalseBB = User->getOperand(1);
15358 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15359 assert(NewBR == User);
15362 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15363 Cond.getOperand(0), Cond.getOperand(1));
15364 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15365 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15366 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15367 Chain, Dest, CC, Cmp);
15368 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15378 // Look pass the truncate if the high bits are known zero.
15379 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15380 Cond = Cond.getOperand(0);
15382 // We know the result of AND is compared against zero. Try to match
15384 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15385 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15386 if (NewSetCC.getNode()) {
15387 CC = NewSetCC.getOperand(0);
15388 Cond = NewSetCC.getOperand(1);
15395 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15396 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15397 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15399 Cond = ConvertCmpIfNecessary(Cond, DAG);
15400 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15401 Chain, Dest, CC, Cond);
15404 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15405 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15406 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15407 // that the guard pages used by the OS virtual memory manager are allocated in
15408 // correct sequence.
15410 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15411 SelectionDAG &DAG) const {
15412 MachineFunction &MF = DAG.getMachineFunction();
15413 bool SplitStack = MF.shouldSplitStack();
15414 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15419 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15420 SDNode* Node = Op.getNode();
15422 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15423 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15424 " not tell us which reg is the stack pointer!");
15425 EVT VT = Node->getValueType(0);
15426 SDValue Tmp1 = SDValue(Node, 0);
15427 SDValue Tmp2 = SDValue(Node, 1);
15428 SDValue Tmp3 = Node->getOperand(2);
15429 SDValue Chain = Tmp1.getOperand(0);
15431 // Chain the dynamic stack allocation so that it doesn't modify the stack
15432 // pointer when other instructions are using the stack.
15433 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15436 SDValue Size = Tmp2.getOperand(1);
15437 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15438 Chain = SP.getValue(1);
15439 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15440 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15441 unsigned StackAlign = TFI.getStackAlignment();
15442 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15443 if (Align > StackAlign)
15444 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15445 DAG.getConstant(-(uint64_t)Align, dl, VT));
15446 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15448 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15449 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15452 SDValue Ops[2] = { Tmp1, Tmp2 };
15453 return DAG.getMergeValues(Ops, dl);
15457 SDValue Chain = Op.getOperand(0);
15458 SDValue Size = Op.getOperand(1);
15459 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15460 EVT VT = Op.getNode()->getValueType(0);
15462 bool Is64Bit = Subtarget->is64Bit();
15463 MVT SPTy = getPointerTy(DAG.getDataLayout());
15466 MachineRegisterInfo &MRI = MF.getRegInfo();
15469 // The 64 bit implementation of segmented stacks needs to clobber both r10
15470 // r11. This makes it impossible to use it along with nested parameters.
15471 const Function *F = MF.getFunction();
15473 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15475 if (I->hasNestAttr())
15476 report_fatal_error("Cannot use segmented stacks with functions that "
15477 "have nested arguments.");
15480 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15481 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15482 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15483 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15484 DAG.getRegister(Vreg, SPTy));
15485 SDValue Ops1[2] = { Value, Chain };
15486 return DAG.getMergeValues(Ops1, dl);
15489 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15491 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15492 Flag = Chain.getValue(1);
15493 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15495 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15497 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15498 unsigned SPReg = RegInfo->getStackRegister();
15499 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15500 Chain = SP.getValue(1);
15503 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15504 DAG.getConstant(-(uint64_t)Align, dl, VT));
15505 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15508 SDValue Ops1[2] = { SP, Chain };
15509 return DAG.getMergeValues(Ops1, dl);
15513 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15514 MachineFunction &MF = DAG.getMachineFunction();
15515 auto PtrVT = getPointerTy(MF.getDataLayout());
15516 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15518 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15521 if (!Subtarget->is64Bit() ||
15522 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15523 // vastart just stores the address of the VarArgsFrameIndex slot into the
15524 // memory location argument.
15525 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15526 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15527 MachinePointerInfo(SV), false, false, 0);
15531 // gp_offset (0 - 6 * 8)
15532 // fp_offset (48 - 48 + 8 * 16)
15533 // overflow_arg_area (point to parameters coming in memory).
15535 SmallVector<SDValue, 8> MemOps;
15536 SDValue FIN = Op.getOperand(1);
15538 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15539 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15541 FIN, MachinePointerInfo(SV), false, false, 0);
15542 MemOps.push_back(Store);
15545 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15546 Store = DAG.getStore(Op.getOperand(0), DL,
15547 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15549 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15550 MemOps.push_back(Store);
15552 // Store ptr to overflow_arg_area
15553 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15554 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15555 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15556 MachinePointerInfo(SV, 8),
15558 MemOps.push_back(Store);
15560 // Store ptr to reg_save_area.
15561 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15562 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15563 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15564 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15565 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15566 MemOps.push_back(Store);
15567 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15570 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15571 assert(Subtarget->is64Bit() &&
15572 "LowerVAARG only handles 64-bit va_arg!");
15573 assert(Op.getNode()->getNumOperands() == 4);
15575 MachineFunction &MF = DAG.getMachineFunction();
15576 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15577 // The Win64 ABI uses char* instead of a structure.
15578 return DAG.expandVAArg(Op.getNode());
15580 SDValue Chain = Op.getOperand(0);
15581 SDValue SrcPtr = Op.getOperand(1);
15582 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15583 unsigned Align = Op.getConstantOperandVal(3);
15586 EVT ArgVT = Op.getNode()->getValueType(0);
15587 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15588 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15591 // Decide which area this value should be read from.
15592 // TODO: Implement the AMD64 ABI in its entirety. This simple
15593 // selection mechanism works only for the basic types.
15594 if (ArgVT == MVT::f80) {
15595 llvm_unreachable("va_arg for f80 not yet implemented");
15596 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15597 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15598 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15599 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15601 llvm_unreachable("Unhandled argument type in LowerVAARG");
15604 if (ArgMode == 2) {
15605 // Sanity Check: Make sure using fp_offset makes sense.
15606 assert(!Subtarget->useSoftFloat() &&
15607 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15608 Subtarget->hasSSE1());
15611 // Insert VAARG_64 node into the DAG
15612 // VAARG_64 returns two values: Variable Argument Address, Chain
15613 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15614 DAG.getConstant(ArgMode, dl, MVT::i8),
15615 DAG.getConstant(Align, dl, MVT::i32)};
15616 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15617 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15618 VTs, InstOps, MVT::i64,
15619 MachinePointerInfo(SV),
15621 /*Volatile=*/false,
15623 /*WriteMem=*/true);
15624 Chain = VAARG.getValue(1);
15626 // Load the next argument and return it
15627 return DAG.getLoad(ArgVT, dl,
15630 MachinePointerInfo(),
15631 false, false, false, 0);
15634 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15635 SelectionDAG &DAG) {
15636 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15637 // where a va_list is still an i8*.
15638 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15639 if (Subtarget->isCallingConvWin64(
15640 DAG.getMachineFunction().getFunction()->getCallingConv()))
15641 // Probably a Win64 va_copy.
15642 return DAG.expandVACopy(Op.getNode());
15644 SDValue Chain = Op.getOperand(0);
15645 SDValue DstPtr = Op.getOperand(1);
15646 SDValue SrcPtr = Op.getOperand(2);
15647 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15648 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15651 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15652 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15654 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15657 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15658 // amount is a constant. Takes immediate version of shift as input.
15659 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15660 SDValue SrcOp, uint64_t ShiftAmt,
15661 SelectionDAG &DAG) {
15662 MVT ElementType = VT.getVectorElementType();
15664 // Fold this packed shift into its first operand if ShiftAmt is 0.
15668 // Check for ShiftAmt >= element width
15669 if (ShiftAmt >= ElementType.getSizeInBits()) {
15670 if (Opc == X86ISD::VSRAI)
15671 ShiftAmt = ElementType.getSizeInBits() - 1;
15673 return DAG.getConstant(0, dl, VT);
15676 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15677 && "Unknown target vector shift-by-constant node");
15679 // Fold this packed vector shift into a build vector if SrcOp is a
15680 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15681 if (VT == SrcOp.getSimpleValueType() &&
15682 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15683 SmallVector<SDValue, 8> Elts;
15684 unsigned NumElts = SrcOp->getNumOperands();
15685 ConstantSDNode *ND;
15688 default: llvm_unreachable(nullptr);
15689 case X86ISD::VSHLI:
15690 for (unsigned i=0; i!=NumElts; ++i) {
15691 SDValue CurrentOp = SrcOp->getOperand(i);
15692 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15693 Elts.push_back(CurrentOp);
15696 ND = cast<ConstantSDNode>(CurrentOp);
15697 const APInt &C = ND->getAPIntValue();
15698 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15701 case X86ISD::VSRLI:
15702 for (unsigned i=0; i!=NumElts; ++i) {
15703 SDValue CurrentOp = SrcOp->getOperand(i);
15704 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15705 Elts.push_back(CurrentOp);
15708 ND = cast<ConstantSDNode>(CurrentOp);
15709 const APInt &C = ND->getAPIntValue();
15710 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15713 case X86ISD::VSRAI:
15714 for (unsigned i=0; i!=NumElts; ++i) {
15715 SDValue CurrentOp = SrcOp->getOperand(i);
15716 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15717 Elts.push_back(CurrentOp);
15720 ND = cast<ConstantSDNode>(CurrentOp);
15721 const APInt &C = ND->getAPIntValue();
15722 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15727 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15730 return DAG.getNode(Opc, dl, VT, SrcOp,
15731 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15734 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15735 // may or may not be a constant. Takes immediate version of shift as input.
15736 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15737 SDValue SrcOp, SDValue ShAmt,
15738 SelectionDAG &DAG) {
15739 MVT SVT = ShAmt.getSimpleValueType();
15740 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15742 // Catch shift-by-constant.
15743 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15744 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15745 CShAmt->getZExtValue(), DAG);
15747 // Change opcode to non-immediate version
15749 default: llvm_unreachable("Unknown target vector shift node");
15750 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15751 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15752 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15755 const X86Subtarget &Subtarget =
15756 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15757 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15758 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15759 // Let the shuffle legalizer expand this shift amount node.
15760 SDValue Op0 = ShAmt.getOperand(0);
15761 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15762 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15764 // Need to build a vector containing shift amount.
15765 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15766 SmallVector<SDValue, 4> ShOps;
15767 ShOps.push_back(ShAmt);
15768 if (SVT == MVT::i32) {
15769 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15770 ShOps.push_back(DAG.getUNDEF(SVT));
15772 ShOps.push_back(DAG.getUNDEF(SVT));
15774 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15775 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15778 // The return type has to be a 128-bit type with the same element
15779 // type as the input type.
15780 MVT EltVT = VT.getVectorElementType();
15781 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15783 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15784 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15787 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15788 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15789 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15790 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15791 SDValue PreservedSrc,
15792 const X86Subtarget *Subtarget,
15793 SelectionDAG &DAG) {
15794 EVT VT = Op.getValueType();
15795 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15796 MVT::i1, VT.getVectorNumElements());
15797 SDValue VMask = SDValue();
15798 unsigned OpcodeSelect = ISD::VSELECT;
15801 assert(MaskVT.isSimple() && "invalid mask type");
15803 if (isAllOnes(Mask))
15806 if (MaskVT.bitsGT(Mask.getValueType())) {
15807 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15808 MaskVT.getSizeInBits());
15809 VMask = DAG.getBitcast(MaskVT,
15810 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15812 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15813 Mask.getValueType().getSizeInBits());
15814 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15815 // are extracted by EXTRACT_SUBVECTOR.
15816 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15817 DAG.getBitcast(BitcastVT, Mask),
15818 DAG.getIntPtrConstant(0, dl));
15821 switch (Op.getOpcode()) {
15823 case X86ISD::PCMPEQM:
15824 case X86ISD::PCMPGTM:
15826 case X86ISD::CMPMU:
15827 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15828 case X86ISD::VFPCLASS:
15829 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15830 case X86ISD::VTRUNC:
15831 case X86ISD::VTRUNCS:
15832 case X86ISD::VTRUNCUS:
15833 // We can't use ISD::VSELECT here because it is not always "Legal"
15834 // for the destination type. For example vpmovqb require only AVX512
15835 // and vselect that can operate on byte element type require BWI
15836 OpcodeSelect = X86ISD::SELECT;
15839 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15840 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15841 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15844 /// \brief Creates an SDNode for a predicated scalar operation.
15845 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15846 /// The mask is coming as MVT::i8 and it should be truncated
15847 /// to MVT::i1 while lowering masking intrinsics.
15848 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15849 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15850 /// for a scalar instruction.
15851 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15852 SDValue PreservedSrc,
15853 const X86Subtarget *Subtarget,
15854 SelectionDAG &DAG) {
15855 if (isAllOnes(Mask))
15858 EVT VT = Op.getValueType();
15860 // The mask should be of type MVT::i1
15861 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15863 if (Op.getOpcode() == X86ISD::FSETCC)
15864 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15866 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15867 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15868 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15871 static int getSEHRegistrationNodeSize(const Function *Fn) {
15872 if (!Fn->hasPersonalityFn())
15873 report_fatal_error(
15874 "querying registration node size for function without personality");
15875 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15876 // WinEHStatePass for the full struct definition.
15877 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15878 case EHPersonality::MSVC_X86SEH: return 24;
15879 case EHPersonality::MSVC_CXX: return 16;
15882 report_fatal_error("can only recover FP for MSVC EH personality functions");
15885 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15886 /// function or when returning to a parent frame after catching an exception, we
15887 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15888 /// Here's the math:
15889 /// RegNodeBase = EntryEBP - RegNodeSize
15890 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15891 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15892 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15893 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15894 SDValue EntryEBP) {
15895 MachineFunction &MF = DAG.getMachineFunction();
15898 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15899 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15901 // It's possible that the parent function no longer has a personality function
15902 // if the exceptional code was optimized away, in which case we just return
15903 // the incoming EBP.
15904 if (!Fn->hasPersonalityFn())
15907 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15909 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15911 MCSymbol *OffsetSym =
15912 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15913 GlobalValue::getRealLinkageName(Fn->getName()));
15914 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15915 SDValue RegNodeFrameOffset =
15916 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15918 // RegNodeBase = EntryEBP - RegNodeSize
15919 // ParentFP = RegNodeBase - RegNodeFrameOffset
15920 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15921 DAG.getConstant(RegNodeSize, dl, PtrVT));
15922 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15925 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15926 SelectionDAG &DAG) {
15928 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15929 EVT VT = Op.getValueType();
15930 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15932 switch(IntrData->Type) {
15933 case INTR_TYPE_1OP:
15934 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15935 case INTR_TYPE_2OP:
15936 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15938 case INTR_TYPE_2OP_IMM8:
15939 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15940 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
15941 case INTR_TYPE_3OP:
15942 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15943 Op.getOperand(2), Op.getOperand(3));
15944 case INTR_TYPE_4OP:
15945 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15946 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15947 case INTR_TYPE_1OP_MASK_RM: {
15948 SDValue Src = Op.getOperand(1);
15949 SDValue PassThru = Op.getOperand(2);
15950 SDValue Mask = Op.getOperand(3);
15951 SDValue RoundingMode;
15952 // We allways add rounding mode to the Node.
15953 // If the rounding mode is not specified, we add the
15954 // "current direction" mode.
15955 if (Op.getNumOperands() == 4)
15957 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15959 RoundingMode = Op.getOperand(4);
15960 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15961 if (IntrWithRoundingModeOpcode != 0)
15962 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
15963 X86::STATIC_ROUNDING::CUR_DIRECTION)
15964 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15965 dl, Op.getValueType(), Src, RoundingMode),
15966 Mask, PassThru, Subtarget, DAG);
15967 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15969 Mask, PassThru, Subtarget, DAG);
15971 case INTR_TYPE_1OP_MASK: {
15972 SDValue Src = Op.getOperand(1);
15973 SDValue PassThru = Op.getOperand(2);
15974 SDValue Mask = Op.getOperand(3);
15975 // We add rounding mode to the Node when
15976 // - RM Opcode is specified and
15977 // - RM is not "current direction".
15978 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15979 if (IntrWithRoundingModeOpcode != 0) {
15980 SDValue Rnd = Op.getOperand(4);
15981 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15982 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15983 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15984 dl, Op.getValueType(),
15986 Mask, PassThru, Subtarget, DAG);
15989 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15990 Mask, PassThru, Subtarget, DAG);
15992 case INTR_TYPE_SCALAR_MASK: {
15993 SDValue Src1 = Op.getOperand(1);
15994 SDValue Src2 = Op.getOperand(2);
15995 SDValue passThru = Op.getOperand(3);
15996 SDValue Mask = Op.getOperand(4);
15997 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
15998 Mask, passThru, Subtarget, DAG);
16000 case INTR_TYPE_SCALAR_MASK_RM: {
16001 SDValue Src1 = Op.getOperand(1);
16002 SDValue Src2 = Op.getOperand(2);
16003 SDValue Src0 = Op.getOperand(3);
16004 SDValue Mask = Op.getOperand(4);
16005 // There are 2 kinds of intrinsics in this group:
16006 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16007 // (2) With rounding mode and sae - 7 operands.
16008 if (Op.getNumOperands() == 6) {
16009 SDValue Sae = Op.getOperand(5);
16010 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16011 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16013 Mask, Src0, Subtarget, DAG);
16015 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16016 SDValue RoundingMode = Op.getOperand(5);
16017 SDValue Sae = Op.getOperand(6);
16018 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16019 RoundingMode, Sae),
16020 Mask, Src0, Subtarget, DAG);
16022 case INTR_TYPE_2OP_MASK:
16023 case INTR_TYPE_2OP_IMM8_MASK: {
16024 SDValue Src1 = Op.getOperand(1);
16025 SDValue Src2 = Op.getOperand(2);
16026 SDValue PassThru = Op.getOperand(3);
16027 SDValue Mask = Op.getOperand(4);
16029 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16030 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16032 // We specify 2 possible opcodes for intrinsics with rounding modes.
16033 // First, we check if the intrinsic may have non-default rounding mode,
16034 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16035 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16036 if (IntrWithRoundingModeOpcode != 0) {
16037 SDValue Rnd = Op.getOperand(5);
16038 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16039 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16040 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16041 dl, Op.getValueType(),
16043 Mask, PassThru, Subtarget, DAG);
16046 // TODO: Intrinsics should have fast-math-flags to propagate.
16047 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16048 Mask, PassThru, Subtarget, DAG);
16050 case INTR_TYPE_2OP_MASK_RM: {
16051 SDValue Src1 = Op.getOperand(1);
16052 SDValue Src2 = Op.getOperand(2);
16053 SDValue PassThru = Op.getOperand(3);
16054 SDValue Mask = Op.getOperand(4);
16055 // We specify 2 possible modes for intrinsics, with/without rounding
16057 // First, we check if the intrinsic have rounding mode (6 operands),
16058 // if not, we set rounding mode to "current".
16060 if (Op.getNumOperands() == 6)
16061 Rnd = Op.getOperand(5);
16063 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16064 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16066 Mask, PassThru, Subtarget, DAG);
16068 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16069 SDValue Src1 = Op.getOperand(1);
16070 SDValue Src2 = Op.getOperand(2);
16071 SDValue Src3 = Op.getOperand(3);
16072 SDValue PassThru = Op.getOperand(4);
16073 SDValue Mask = Op.getOperand(5);
16074 SDValue Sae = Op.getOperand(6);
16076 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16078 Mask, PassThru, Subtarget, DAG);
16080 case INTR_TYPE_3OP_MASK_RM: {
16081 SDValue Src1 = Op.getOperand(1);
16082 SDValue Src2 = Op.getOperand(2);
16083 SDValue Imm = Op.getOperand(3);
16084 SDValue PassThru = Op.getOperand(4);
16085 SDValue Mask = Op.getOperand(5);
16086 // We specify 2 possible modes for intrinsics, with/without rounding
16088 // First, we check if the intrinsic have rounding mode (7 operands),
16089 // if not, we set rounding mode to "current".
16091 if (Op.getNumOperands() == 7)
16092 Rnd = Op.getOperand(6);
16094 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16095 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16096 Src1, Src2, Imm, Rnd),
16097 Mask, PassThru, Subtarget, DAG);
16099 case INTR_TYPE_3OP_IMM8_MASK:
16100 case INTR_TYPE_3OP_MASK:
16101 case INSERT_SUBVEC: {
16102 SDValue Src1 = Op.getOperand(1);
16103 SDValue Src2 = Op.getOperand(2);
16104 SDValue Src3 = Op.getOperand(3);
16105 SDValue PassThru = Op.getOperand(4);
16106 SDValue Mask = Op.getOperand(5);
16108 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16109 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16110 else if (IntrData->Type == INSERT_SUBVEC) {
16111 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16112 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16113 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16114 Imm *= Src2.getValueType().getVectorNumElements();
16115 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16118 // We specify 2 possible opcodes for intrinsics with rounding modes.
16119 // First, we check if the intrinsic may have non-default rounding mode,
16120 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16121 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16122 if (IntrWithRoundingModeOpcode != 0) {
16123 SDValue Rnd = Op.getOperand(6);
16124 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16125 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16126 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16127 dl, Op.getValueType(),
16128 Src1, Src2, Src3, Rnd),
16129 Mask, PassThru, Subtarget, DAG);
16132 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16134 Mask, PassThru, Subtarget, DAG);
16136 case VPERM_3OP_MASKZ:
16137 case VPERM_3OP_MASK:
16140 case FMA_OP_MASK: {
16141 SDValue Src1 = Op.getOperand(1);
16142 SDValue Src2 = Op.getOperand(2);
16143 SDValue Src3 = Op.getOperand(3);
16144 SDValue Mask = Op.getOperand(4);
16145 EVT VT = Op.getValueType();
16146 SDValue PassThru = SDValue();
16148 // set PassThru element
16149 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16150 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16151 else if (IntrData->Type == FMA_OP_MASK3)
16156 // We specify 2 possible opcodes for intrinsics with rounding modes.
16157 // First, we check if the intrinsic may have non-default rounding mode,
16158 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16159 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16160 if (IntrWithRoundingModeOpcode != 0) {
16161 SDValue Rnd = Op.getOperand(5);
16162 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16163 X86::STATIC_ROUNDING::CUR_DIRECTION)
16164 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16165 dl, Op.getValueType(),
16166 Src1, Src2, Src3, Rnd),
16167 Mask, PassThru, Subtarget, DAG);
16169 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16170 dl, Op.getValueType(),
16172 Mask, PassThru, Subtarget, DAG);
16175 // FPclass intrinsics with mask
16176 SDValue Src1 = Op.getOperand(1);
16177 EVT VT = Src1.getValueType();
16178 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16179 VT.getVectorNumElements());
16180 SDValue Imm = Op.getOperand(2);
16181 SDValue Mask = Op.getOperand(3);
16182 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16183 Mask.getValueType().getSizeInBits());
16184 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16185 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16186 DAG.getTargetConstant(0, dl, MaskVT),
16188 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16189 DAG.getUNDEF(BitcastVT), FPclassMask,
16190 DAG.getIntPtrConstant(0, dl));
16191 return DAG.getBitcast(Op.getValueType(), Res);
16194 case CMP_MASK_CC: {
16195 // Comparison intrinsics with masks.
16196 // Example of transformation:
16197 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16198 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16200 // (v8i1 (insert_subvector undef,
16201 // (v2i1 (and (PCMPEQM %a, %b),
16202 // (extract_subvector
16203 // (v8i1 (bitcast %mask)), 0))), 0))))
16204 EVT VT = Op.getOperand(1).getValueType();
16205 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16206 VT.getVectorNumElements());
16207 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16208 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16209 Mask.getValueType().getSizeInBits());
16211 if (IntrData->Type == CMP_MASK_CC) {
16212 SDValue CC = Op.getOperand(3);
16213 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16214 // We specify 2 possible opcodes for intrinsics with rounding modes.
16215 // First, we check if the intrinsic may have non-default rounding mode,
16216 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16217 if (IntrData->Opc1 != 0) {
16218 SDValue Rnd = Op.getOperand(5);
16219 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16220 X86::STATIC_ROUNDING::CUR_DIRECTION)
16221 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16222 Op.getOperand(2), CC, Rnd);
16224 //default rounding mode
16226 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16227 Op.getOperand(2), CC);
16230 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16231 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16234 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16235 DAG.getTargetConstant(0, dl,
16238 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16239 DAG.getUNDEF(BitcastVT), CmpMask,
16240 DAG.getIntPtrConstant(0, dl));
16241 return DAG.getBitcast(Op.getValueType(), Res);
16243 case CMP_MASK_SCALAR_CC: {
16244 SDValue Src1 = Op.getOperand(1);
16245 SDValue Src2 = Op.getOperand(2);
16246 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16247 SDValue Mask = Op.getOperand(4);
16250 if (IntrData->Opc1 != 0) {
16251 SDValue Rnd = Op.getOperand(5);
16252 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16253 X86::STATIC_ROUNDING::CUR_DIRECTION)
16254 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16256 //default rounding mode
16258 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16260 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16261 DAG.getTargetConstant(0, dl,
16265 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16266 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16267 DAG.getValueType(MVT::i1));
16269 case COMI: { // Comparison intrinsics
16270 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16271 SDValue LHS = Op.getOperand(1);
16272 SDValue RHS = Op.getOperand(2);
16273 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16274 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16275 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16276 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16277 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16278 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16281 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16282 Op.getOperand(1), Op.getOperand(2), DAG);
16284 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16285 Op.getSimpleValueType(),
16287 Op.getOperand(2), DAG),
16288 Op.getOperand(4), Op.getOperand(3), Subtarget,
16290 case COMPRESS_EXPAND_IN_REG: {
16291 SDValue Mask = Op.getOperand(3);
16292 SDValue DataToCompress = Op.getOperand(1);
16293 SDValue PassThru = Op.getOperand(2);
16294 if (isAllOnes(Mask)) // return data as is
16295 return Op.getOperand(1);
16297 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16299 Mask, PassThru, Subtarget, DAG);
16302 SDValue Mask = Op.getOperand(3);
16303 EVT VT = Op.getValueType();
16304 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16305 VT.getVectorNumElements());
16306 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16307 Mask.getValueType().getSizeInBits());
16309 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16310 DAG.getBitcast(BitcastVT, Mask),
16311 DAG.getIntPtrConstant(0, dl));
16312 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16321 default: return SDValue(); // Don't custom lower most intrinsics.
16323 case Intrinsic::x86_avx2_permd:
16324 case Intrinsic::x86_avx2_permps:
16325 // Operands intentionally swapped. Mask is last operand to intrinsic,
16326 // but second operand for node/instruction.
16327 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16328 Op.getOperand(2), Op.getOperand(1));
16330 // ptest and testp intrinsics. The intrinsic these come from are designed to
16331 // return an integer value, not just an instruction so lower it to the ptest
16332 // or testp pattern and a setcc for the result.
16333 case Intrinsic::x86_sse41_ptestz:
16334 case Intrinsic::x86_sse41_ptestc:
16335 case Intrinsic::x86_sse41_ptestnzc:
16336 case Intrinsic::x86_avx_ptestz_256:
16337 case Intrinsic::x86_avx_ptestc_256:
16338 case Intrinsic::x86_avx_ptestnzc_256:
16339 case Intrinsic::x86_avx_vtestz_ps:
16340 case Intrinsic::x86_avx_vtestc_ps:
16341 case Intrinsic::x86_avx_vtestnzc_ps:
16342 case Intrinsic::x86_avx_vtestz_pd:
16343 case Intrinsic::x86_avx_vtestc_pd:
16344 case Intrinsic::x86_avx_vtestnzc_pd:
16345 case Intrinsic::x86_avx_vtestz_ps_256:
16346 case Intrinsic::x86_avx_vtestc_ps_256:
16347 case Intrinsic::x86_avx_vtestnzc_ps_256:
16348 case Intrinsic::x86_avx_vtestz_pd_256:
16349 case Intrinsic::x86_avx_vtestc_pd_256:
16350 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16351 bool IsTestPacked = false;
16354 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16355 case Intrinsic::x86_avx_vtestz_ps:
16356 case Intrinsic::x86_avx_vtestz_pd:
16357 case Intrinsic::x86_avx_vtestz_ps_256:
16358 case Intrinsic::x86_avx_vtestz_pd_256:
16359 IsTestPacked = true; // Fallthrough
16360 case Intrinsic::x86_sse41_ptestz:
16361 case Intrinsic::x86_avx_ptestz_256:
16363 X86CC = X86::COND_E;
16365 case Intrinsic::x86_avx_vtestc_ps:
16366 case Intrinsic::x86_avx_vtestc_pd:
16367 case Intrinsic::x86_avx_vtestc_ps_256:
16368 case Intrinsic::x86_avx_vtestc_pd_256:
16369 IsTestPacked = true; // Fallthrough
16370 case Intrinsic::x86_sse41_ptestc:
16371 case Intrinsic::x86_avx_ptestc_256:
16373 X86CC = X86::COND_B;
16375 case Intrinsic::x86_avx_vtestnzc_ps:
16376 case Intrinsic::x86_avx_vtestnzc_pd:
16377 case Intrinsic::x86_avx_vtestnzc_ps_256:
16378 case Intrinsic::x86_avx_vtestnzc_pd_256:
16379 IsTestPacked = true; // Fallthrough
16380 case Intrinsic::x86_sse41_ptestnzc:
16381 case Intrinsic::x86_avx_ptestnzc_256:
16383 X86CC = X86::COND_A;
16387 SDValue LHS = Op.getOperand(1);
16388 SDValue RHS = Op.getOperand(2);
16389 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16390 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16391 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16392 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16393 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16395 case Intrinsic::x86_avx512_kortestz_w:
16396 case Intrinsic::x86_avx512_kortestc_w: {
16397 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16398 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16399 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16400 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16401 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16402 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16403 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16406 case Intrinsic::x86_sse42_pcmpistria128:
16407 case Intrinsic::x86_sse42_pcmpestria128:
16408 case Intrinsic::x86_sse42_pcmpistric128:
16409 case Intrinsic::x86_sse42_pcmpestric128:
16410 case Intrinsic::x86_sse42_pcmpistrio128:
16411 case Intrinsic::x86_sse42_pcmpestrio128:
16412 case Intrinsic::x86_sse42_pcmpistris128:
16413 case Intrinsic::x86_sse42_pcmpestris128:
16414 case Intrinsic::x86_sse42_pcmpistriz128:
16415 case Intrinsic::x86_sse42_pcmpestriz128: {
16419 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16420 case Intrinsic::x86_sse42_pcmpistria128:
16421 Opcode = X86ISD::PCMPISTRI;
16422 X86CC = X86::COND_A;
16424 case Intrinsic::x86_sse42_pcmpestria128:
16425 Opcode = X86ISD::PCMPESTRI;
16426 X86CC = X86::COND_A;
16428 case Intrinsic::x86_sse42_pcmpistric128:
16429 Opcode = X86ISD::PCMPISTRI;
16430 X86CC = X86::COND_B;
16432 case Intrinsic::x86_sse42_pcmpestric128:
16433 Opcode = X86ISD::PCMPESTRI;
16434 X86CC = X86::COND_B;
16436 case Intrinsic::x86_sse42_pcmpistrio128:
16437 Opcode = X86ISD::PCMPISTRI;
16438 X86CC = X86::COND_O;
16440 case Intrinsic::x86_sse42_pcmpestrio128:
16441 Opcode = X86ISD::PCMPESTRI;
16442 X86CC = X86::COND_O;
16444 case Intrinsic::x86_sse42_pcmpistris128:
16445 Opcode = X86ISD::PCMPISTRI;
16446 X86CC = X86::COND_S;
16448 case Intrinsic::x86_sse42_pcmpestris128:
16449 Opcode = X86ISD::PCMPESTRI;
16450 X86CC = X86::COND_S;
16452 case Intrinsic::x86_sse42_pcmpistriz128:
16453 Opcode = X86ISD::PCMPISTRI;
16454 X86CC = X86::COND_E;
16456 case Intrinsic::x86_sse42_pcmpestriz128:
16457 Opcode = X86ISD::PCMPESTRI;
16458 X86CC = X86::COND_E;
16461 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16462 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16463 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16464 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16465 DAG.getConstant(X86CC, dl, MVT::i8),
16466 SDValue(PCMP.getNode(), 1));
16467 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16470 case Intrinsic::x86_sse42_pcmpistri128:
16471 case Intrinsic::x86_sse42_pcmpestri128: {
16473 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16474 Opcode = X86ISD::PCMPISTRI;
16476 Opcode = X86ISD::PCMPESTRI;
16478 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16479 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16480 return DAG.getNode(Opcode, dl, VTs, NewOps);
16483 case Intrinsic::x86_seh_lsda: {
16484 // Compute the symbol for the LSDA. We know it'll get emitted later.
16485 MachineFunction &MF = DAG.getMachineFunction();
16486 SDValue Op1 = Op.getOperand(1);
16487 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16488 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16489 GlobalValue::getRealLinkageName(Fn->getName()));
16491 // Generate a simple absolute symbol reference. This intrinsic is only
16492 // supported on 32-bit Windows, which isn't PIC.
16493 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16494 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16497 case Intrinsic::x86_seh_recoverfp: {
16498 SDValue FnOp = Op.getOperand(1);
16499 SDValue IncomingFPOp = Op.getOperand(2);
16500 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16501 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16503 report_fatal_error(
16504 "llvm.x86.seh.recoverfp must take a function as the first argument");
16505 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16508 case Intrinsic::localaddress: {
16509 // Returns one of the stack, base, or frame pointer registers, depending on
16510 // which is used to reference local variables.
16511 MachineFunction &MF = DAG.getMachineFunction();
16512 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16514 if (RegInfo->hasBasePointer(MF))
16515 Reg = RegInfo->getBaseRegister();
16516 else // This function handles the SP or FP case.
16517 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16518 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16523 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16524 SDValue Src, SDValue Mask, SDValue Base,
16525 SDValue Index, SDValue ScaleOp, SDValue Chain,
16526 const X86Subtarget * Subtarget) {
16528 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16530 llvm_unreachable("Invalid scale type");
16531 unsigned ScaleVal = C->getZExtValue();
16532 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16533 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16535 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16536 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16537 Index.getSimpleValueType().getVectorNumElements());
16539 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16541 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16543 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16544 Mask.getValueType().getSizeInBits());
16546 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16547 // are extracted by EXTRACT_SUBVECTOR.
16548 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16549 DAG.getBitcast(BitcastVT, Mask),
16550 DAG.getIntPtrConstant(0, dl));
16552 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16553 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16554 SDValue Segment = DAG.getRegister(0, MVT::i32);
16555 if (Src.getOpcode() == ISD::UNDEF)
16556 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16557 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16558 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16559 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16560 return DAG.getMergeValues(RetOps, dl);
16563 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16564 SDValue Src, SDValue Mask, SDValue Base,
16565 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16567 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16569 llvm_unreachable("Invalid scale type");
16570 unsigned ScaleVal = C->getZExtValue();
16571 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16572 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16574 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16575 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16576 SDValue Segment = DAG.getRegister(0, MVT::i32);
16577 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16578 Index.getSimpleValueType().getVectorNumElements());
16580 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16582 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16584 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16585 Mask.getValueType().getSizeInBits());
16587 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16588 // are extracted by EXTRACT_SUBVECTOR.
16589 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16590 DAG.getBitcast(BitcastVT, Mask),
16591 DAG.getIntPtrConstant(0, dl));
16593 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16594 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16595 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16596 return SDValue(Res, 1);
16599 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16600 SDValue Mask, SDValue Base, SDValue Index,
16601 SDValue ScaleOp, SDValue Chain) {
16603 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16604 assert(C && "Invalid scale type");
16605 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16606 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16607 SDValue Segment = DAG.getRegister(0, MVT::i32);
16609 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16611 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16613 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16615 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16616 //SDVTList VTs = DAG.getVTList(MVT::Other);
16617 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16618 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16619 return SDValue(Res, 0);
16622 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16623 // read performance monitor counters (x86_rdpmc).
16624 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16625 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16626 SmallVectorImpl<SDValue> &Results) {
16627 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16628 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16631 // The ECX register is used to select the index of the performance counter
16633 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16635 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16637 // Reads the content of a 64-bit performance counter and returns it in the
16638 // registers EDX:EAX.
16639 if (Subtarget->is64Bit()) {
16640 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16641 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16644 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16645 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16648 Chain = HI.getValue(1);
16650 if (Subtarget->is64Bit()) {
16651 // The EAX register is loaded with the low-order 32 bits. The EDX register
16652 // is loaded with the supported high-order bits of the counter.
16653 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16654 DAG.getConstant(32, DL, MVT::i8));
16655 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16656 Results.push_back(Chain);
16660 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16661 SDValue Ops[] = { LO, HI };
16662 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16663 Results.push_back(Pair);
16664 Results.push_back(Chain);
16667 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16668 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16669 // also used to custom lower READCYCLECOUNTER nodes.
16670 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16671 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16672 SmallVectorImpl<SDValue> &Results) {
16673 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16674 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16677 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16678 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16679 // and the EAX register is loaded with the low-order 32 bits.
16680 if (Subtarget->is64Bit()) {
16681 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16682 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16685 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16686 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16689 SDValue Chain = HI.getValue(1);
16691 if (Opcode == X86ISD::RDTSCP_DAG) {
16692 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16694 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16695 // the ECX register. Add 'ecx' explicitly to the chain.
16696 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16698 // Explicitly store the content of ECX at the location passed in input
16699 // to the 'rdtscp' intrinsic.
16700 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16701 MachinePointerInfo(), false, false, 0);
16704 if (Subtarget->is64Bit()) {
16705 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16706 // the EAX register is loaded with the low-order 32 bits.
16707 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16708 DAG.getConstant(32, DL, MVT::i8));
16709 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16710 Results.push_back(Chain);
16714 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16715 SDValue Ops[] = { LO, HI };
16716 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16717 Results.push_back(Pair);
16718 Results.push_back(Chain);
16721 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16722 SelectionDAG &DAG) {
16723 SmallVector<SDValue, 2> Results;
16725 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16727 return DAG.getMergeValues(Results, DL);
16730 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16731 SelectionDAG &DAG) {
16732 MachineFunction &MF = DAG.getMachineFunction();
16733 const Function *Fn = MF.getFunction();
16735 SDValue Chain = Op.getOperand(0);
16737 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16738 "using llvm.x86.seh.restoreframe requires a frame pointer");
16740 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16741 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16743 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16744 unsigned FrameReg =
16745 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16746 unsigned SPReg = RegInfo->getStackRegister();
16747 unsigned SlotSize = RegInfo->getSlotSize();
16749 // Get incoming EBP.
16750 SDValue IncomingEBP =
16751 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16753 // SP is saved in the first field of every registration node, so load
16754 // [EBP-RegNodeSize] into SP.
16755 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16756 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16757 DAG.getConstant(-RegNodeSize, dl, VT));
16759 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16760 false, VT.getScalarSizeInBits() / 8);
16761 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16763 if (!RegInfo->needsStackRealignment(MF)) {
16764 // Adjust EBP to point back to the original frame position.
16765 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16766 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16768 assert(RegInfo->hasBasePointer(MF) &&
16769 "functions with Win32 EH must use frame or base pointer register");
16771 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16772 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16773 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16775 // Reload the spilled EBP value, now that the stack and base pointers are
16777 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16778 X86FI->setHasSEHFramePtrSave(true);
16779 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16780 X86FI->setSEHFramePtrSaveIndex(FI);
16781 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16782 MachinePointerInfo(), false, false, false,
16783 VT.getScalarSizeInBits() / 8);
16784 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16790 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16791 /// return truncate Store/MaskedStore Node
16792 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16796 SDValue Mask = Op.getOperand(4);
16797 SDValue DataToTruncate = Op.getOperand(3);
16798 SDValue Addr = Op.getOperand(2);
16799 SDValue Chain = Op.getOperand(0);
16801 EVT VT = DataToTruncate.getValueType();
16802 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16803 ElementType, VT.getVectorNumElements());
16805 if (isAllOnes(Mask)) // return just a truncate store
16806 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16807 MachinePointerInfo(), SVT, false, false,
16808 SVT.getScalarSizeInBits()/8);
16810 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16811 MVT::i1, VT.getVectorNumElements());
16812 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16813 Mask.getValueType().getSizeInBits());
16814 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16815 // are extracted by EXTRACT_SUBVECTOR.
16816 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16817 DAG.getBitcast(BitcastVT, Mask),
16818 DAG.getIntPtrConstant(0, dl));
16820 MachineMemOperand *MMO = DAG.getMachineFunction().
16821 getMachineMemOperand(MachinePointerInfo(),
16822 MachineMemOperand::MOStore, SVT.getStoreSize(),
16823 SVT.getScalarSizeInBits()/8);
16825 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16826 VMask, SVT, MMO, true);
16829 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16830 SelectionDAG &DAG) {
16831 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16833 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16835 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16836 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16841 switch(IntrData->Type) {
16843 llvm_unreachable("Unknown Intrinsic Type");
16847 // Emit the node with the right value type.
16848 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16849 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16851 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16852 // Otherwise return the value from Rand, which is always 0, casted to i32.
16853 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16854 DAG.getConstant(1, dl, Op->getValueType(1)),
16855 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16856 SDValue(Result.getNode(), 1) };
16857 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16858 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16861 // Return { result, isValid, chain }.
16862 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16863 SDValue(Result.getNode(), 2));
16866 //gather(v1, mask, index, base, scale);
16867 SDValue Chain = Op.getOperand(0);
16868 SDValue Src = Op.getOperand(2);
16869 SDValue Base = Op.getOperand(3);
16870 SDValue Index = Op.getOperand(4);
16871 SDValue Mask = Op.getOperand(5);
16872 SDValue Scale = Op.getOperand(6);
16873 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16877 //scatter(base, mask, index, v1, scale);
16878 SDValue Chain = Op.getOperand(0);
16879 SDValue Base = Op.getOperand(2);
16880 SDValue Mask = Op.getOperand(3);
16881 SDValue Index = Op.getOperand(4);
16882 SDValue Src = Op.getOperand(5);
16883 SDValue Scale = Op.getOperand(6);
16884 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16888 SDValue Hint = Op.getOperand(6);
16889 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16890 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16891 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16892 SDValue Chain = Op.getOperand(0);
16893 SDValue Mask = Op.getOperand(2);
16894 SDValue Index = Op.getOperand(3);
16895 SDValue Base = Op.getOperand(4);
16896 SDValue Scale = Op.getOperand(5);
16897 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16899 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16901 SmallVector<SDValue, 2> Results;
16902 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16904 return DAG.getMergeValues(Results, dl);
16906 // Read Performance Monitoring Counters.
16908 SmallVector<SDValue, 2> Results;
16909 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16910 return DAG.getMergeValues(Results, dl);
16912 // XTEST intrinsics.
16914 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16915 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16916 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16917 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16919 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16920 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16921 Ret, SDValue(InTrans.getNode(), 1));
16925 SmallVector<SDValue, 2> Results;
16926 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16927 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16928 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16929 DAG.getConstant(-1, dl, MVT::i8));
16930 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16931 Op.getOperand(4), GenCF.getValue(1));
16932 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16933 Op.getOperand(5), MachinePointerInfo(),
16935 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16936 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16938 Results.push_back(SetCC);
16939 Results.push_back(Store);
16940 return DAG.getMergeValues(Results, dl);
16942 case COMPRESS_TO_MEM: {
16944 SDValue Mask = Op.getOperand(4);
16945 SDValue DataToCompress = Op.getOperand(3);
16946 SDValue Addr = Op.getOperand(2);
16947 SDValue Chain = Op.getOperand(0);
16949 EVT VT = DataToCompress.getValueType();
16950 if (isAllOnes(Mask)) // return just a store
16951 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16952 MachinePointerInfo(), false, false,
16953 VT.getScalarSizeInBits()/8);
16955 SDValue Compressed =
16956 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16957 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16958 return DAG.getStore(Chain, dl, Compressed, Addr,
16959 MachinePointerInfo(), false, false,
16960 VT.getScalarSizeInBits()/8);
16962 case TRUNCATE_TO_MEM_VI8:
16963 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
16964 case TRUNCATE_TO_MEM_VI16:
16965 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
16966 case TRUNCATE_TO_MEM_VI32:
16967 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
16968 case EXPAND_FROM_MEM: {
16970 SDValue Mask = Op.getOperand(4);
16971 SDValue PassThru = Op.getOperand(3);
16972 SDValue Addr = Op.getOperand(2);
16973 SDValue Chain = Op.getOperand(0);
16974 EVT VT = Op.getValueType();
16976 if (isAllOnes(Mask)) // return just a load
16977 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16978 false, VT.getScalarSizeInBits()/8);
16980 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16981 false, false, false,
16982 VT.getScalarSizeInBits()/8);
16984 SDValue Results[] = {
16985 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16986 Mask, PassThru, Subtarget, DAG), Chain};
16987 return DAG.getMergeValues(Results, dl);
16992 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16993 SelectionDAG &DAG) const {
16994 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16995 MFI->setReturnAddressIsTaken(true);
16997 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17000 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17002 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17005 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17006 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17007 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17008 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17009 DAG.getNode(ISD::ADD, dl, PtrVT,
17010 FrameAddr, Offset),
17011 MachinePointerInfo(), false, false, false, 0);
17014 // Just load the return address.
17015 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17016 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17017 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17020 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17021 MachineFunction &MF = DAG.getMachineFunction();
17022 MachineFrameInfo *MFI = MF.getFrameInfo();
17023 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17024 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17025 EVT VT = Op.getValueType();
17027 MFI->setFrameAddressIsTaken(true);
17029 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17030 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17031 // is not possible to crawl up the stack without looking at the unwind codes
17033 int FrameAddrIndex = FuncInfo->getFAIndex();
17034 if (!FrameAddrIndex) {
17035 // Set up a frame object for the return address.
17036 unsigned SlotSize = RegInfo->getSlotSize();
17037 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17038 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17039 FuncInfo->setFAIndex(FrameAddrIndex);
17041 return DAG.getFrameIndex(FrameAddrIndex, VT);
17044 unsigned FrameReg =
17045 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17046 SDLoc dl(Op); // FIXME probably not meaningful
17047 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17048 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17049 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17050 "Invalid Frame Register!");
17051 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17053 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17054 MachinePointerInfo(),
17055 false, false, false, 0);
17059 // FIXME? Maybe this could be a TableGen attribute on some registers and
17060 // this table could be generated automatically from RegInfo.
17061 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17062 SelectionDAG &DAG) const {
17063 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17064 const MachineFunction &MF = DAG.getMachineFunction();
17066 unsigned Reg = StringSwitch<unsigned>(RegName)
17067 .Case("esp", X86::ESP)
17068 .Case("rsp", X86::RSP)
17069 .Case("ebp", X86::EBP)
17070 .Case("rbp", X86::RBP)
17073 if (Reg == X86::EBP || Reg == X86::RBP) {
17074 if (!TFI.hasFP(MF))
17075 report_fatal_error("register " + StringRef(RegName) +
17076 " is allocatable: function has no frame pointer");
17079 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17080 unsigned FrameReg =
17081 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17082 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17083 "Invalid Frame Register!");
17091 report_fatal_error("Invalid register name global variable");
17094 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17095 SelectionDAG &DAG) const {
17096 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17097 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17100 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17101 SDValue Chain = Op.getOperand(0);
17102 SDValue Offset = Op.getOperand(1);
17103 SDValue Handler = Op.getOperand(2);
17106 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17107 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17108 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17109 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17110 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17111 "Invalid Frame Register!");
17112 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17113 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17115 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17116 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17118 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17119 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17121 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17123 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17124 DAG.getRegister(StoreAddrReg, PtrVT));
17127 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17128 SelectionDAG &DAG) const {
17130 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17131 DAG.getVTList(MVT::i32, MVT::Other),
17132 Op.getOperand(0), Op.getOperand(1));
17135 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17136 SelectionDAG &DAG) const {
17138 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17139 Op.getOperand(0), Op.getOperand(1));
17142 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17143 return Op.getOperand(0);
17146 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17147 SelectionDAG &DAG) const {
17148 SDValue Root = Op.getOperand(0);
17149 SDValue Trmp = Op.getOperand(1); // trampoline
17150 SDValue FPtr = Op.getOperand(2); // nested function
17151 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17154 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17155 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17157 if (Subtarget->is64Bit()) {
17158 SDValue OutChains[6];
17160 // Large code-model.
17161 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17162 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17164 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17165 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17167 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17169 // Load the pointer to the nested function into R11.
17170 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17171 SDValue Addr = Trmp;
17172 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17173 Addr, MachinePointerInfo(TrmpAddr),
17176 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17177 DAG.getConstant(2, dl, MVT::i64));
17178 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17179 MachinePointerInfo(TrmpAddr, 2),
17182 // Load the 'nest' parameter value into R10.
17183 // R10 is specified in X86CallingConv.td
17184 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17185 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17186 DAG.getConstant(10, dl, MVT::i64));
17187 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17188 Addr, MachinePointerInfo(TrmpAddr, 10),
17191 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17192 DAG.getConstant(12, dl, MVT::i64));
17193 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17194 MachinePointerInfo(TrmpAddr, 12),
17197 // Jump to the nested function.
17198 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17199 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17200 DAG.getConstant(20, dl, MVT::i64));
17201 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17202 Addr, MachinePointerInfo(TrmpAddr, 20),
17205 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17206 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17207 DAG.getConstant(22, dl, MVT::i64));
17208 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17209 Addr, MachinePointerInfo(TrmpAddr, 22),
17212 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17214 const Function *Func =
17215 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17216 CallingConv::ID CC = Func->getCallingConv();
17221 llvm_unreachable("Unsupported calling convention");
17222 case CallingConv::C:
17223 case CallingConv::X86_StdCall: {
17224 // Pass 'nest' parameter in ECX.
17225 // Must be kept in sync with X86CallingConv.td
17226 NestReg = X86::ECX;
17228 // Check that ECX wasn't needed by an 'inreg' parameter.
17229 FunctionType *FTy = Func->getFunctionType();
17230 const AttributeSet &Attrs = Func->getAttributes();
17232 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17233 unsigned InRegCount = 0;
17236 for (FunctionType::param_iterator I = FTy->param_begin(),
17237 E = FTy->param_end(); I != E; ++I, ++Idx)
17238 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17239 auto &DL = DAG.getDataLayout();
17240 // FIXME: should only count parameters that are lowered to integers.
17241 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17244 if (InRegCount > 2) {
17245 report_fatal_error("Nest register in use - reduce number of inreg"
17251 case CallingConv::X86_FastCall:
17252 case CallingConv::X86_ThisCall:
17253 case CallingConv::Fast:
17254 // Pass 'nest' parameter in EAX.
17255 // Must be kept in sync with X86CallingConv.td
17256 NestReg = X86::EAX;
17260 SDValue OutChains[4];
17261 SDValue Addr, Disp;
17263 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17264 DAG.getConstant(10, dl, MVT::i32));
17265 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17267 // This is storing the opcode for MOV32ri.
17268 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17269 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17270 OutChains[0] = DAG.getStore(Root, dl,
17271 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17272 Trmp, MachinePointerInfo(TrmpAddr),
17275 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17276 DAG.getConstant(1, dl, MVT::i32));
17277 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17278 MachinePointerInfo(TrmpAddr, 1),
17281 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17282 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17283 DAG.getConstant(5, dl, MVT::i32));
17284 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17285 Addr, MachinePointerInfo(TrmpAddr, 5),
17288 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17289 DAG.getConstant(6, dl, MVT::i32));
17290 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17291 MachinePointerInfo(TrmpAddr, 6),
17294 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17298 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17299 SelectionDAG &DAG) const {
17301 The rounding mode is in bits 11:10 of FPSR, and has the following
17303 00 Round to nearest
17308 FLT_ROUNDS, on the other hand, expects the following:
17315 To perform the conversion, we do:
17316 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17319 MachineFunction &MF = DAG.getMachineFunction();
17320 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17321 unsigned StackAlignment = TFI.getStackAlignment();
17322 MVT VT = Op.getSimpleValueType();
17325 // Save FP Control Word to stack slot
17326 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17327 SDValue StackSlot =
17328 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17330 MachineMemOperand *MMO =
17331 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17332 MachineMemOperand::MOStore, 2, 2);
17334 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17335 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17336 DAG.getVTList(MVT::Other),
17337 Ops, MVT::i16, MMO);
17339 // Load FP Control Word from stack slot
17340 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17341 MachinePointerInfo(), false, false, false, 0);
17343 // Transform as necessary
17345 DAG.getNode(ISD::SRL, DL, MVT::i16,
17346 DAG.getNode(ISD::AND, DL, MVT::i16,
17347 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17348 DAG.getConstant(11, DL, MVT::i8));
17350 DAG.getNode(ISD::SRL, DL, MVT::i16,
17351 DAG.getNode(ISD::AND, DL, MVT::i16,
17352 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17353 DAG.getConstant(9, DL, MVT::i8));
17356 DAG.getNode(ISD::AND, DL, MVT::i16,
17357 DAG.getNode(ISD::ADD, DL, MVT::i16,
17358 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17359 DAG.getConstant(1, DL, MVT::i16)),
17360 DAG.getConstant(3, DL, MVT::i16));
17362 return DAG.getNode((VT.getSizeInBits() < 16 ?
17363 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17366 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17367 MVT VT = Op.getSimpleValueType();
17369 unsigned NumBits = VT.getSizeInBits();
17372 Op = Op.getOperand(0);
17373 if (VT == MVT::i8) {
17374 // Zero extend to i32 since there is not an i8 bsr.
17376 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17379 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17380 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17381 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17383 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17386 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17387 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17390 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17392 // Finally xor with NumBits-1.
17393 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17394 DAG.getConstant(NumBits - 1, dl, OpVT));
17397 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17401 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17402 MVT VT = Op.getSimpleValueType();
17404 unsigned NumBits = VT.getSizeInBits();
17407 Op = Op.getOperand(0);
17408 if (VT == MVT::i8) {
17409 // Zero extend to i32 since there is not an i8 bsr.
17411 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17414 // Issue a bsr (scan bits in reverse).
17415 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17416 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17418 // And xor with NumBits-1.
17419 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17420 DAG.getConstant(NumBits - 1, dl, OpVT));
17423 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17427 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17428 MVT VT = Op.getSimpleValueType();
17429 unsigned NumBits = VT.getScalarSizeInBits();
17432 if (VT.isVector()) {
17433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17435 SDValue N0 = Op.getOperand(0);
17436 SDValue Zero = DAG.getConstant(0, dl, VT);
17438 // lsb(x) = (x & -x)
17439 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17440 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17442 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17443 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17444 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17445 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17446 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17447 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17450 // cttz(x) = ctpop(lsb - 1)
17451 SDValue One = DAG.getConstant(1, dl, VT);
17452 return DAG.getNode(ISD::CTPOP, dl, VT,
17453 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17456 assert(Op.getOpcode() == ISD::CTTZ &&
17457 "Only scalar CTTZ requires custom lowering");
17459 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17460 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17461 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17463 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17466 DAG.getConstant(NumBits, dl, VT),
17467 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17470 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17473 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17474 // ones, and then concatenate the result back.
17475 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17476 MVT VT = Op.getSimpleValueType();
17478 assert(VT.is256BitVector() && VT.isInteger() &&
17479 "Unsupported value type for operation");
17481 unsigned NumElems = VT.getVectorNumElements();
17484 // Extract the LHS vectors
17485 SDValue LHS = Op.getOperand(0);
17486 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17487 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17489 // Extract the RHS vectors
17490 SDValue RHS = Op.getOperand(1);
17491 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17492 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17494 MVT EltVT = VT.getVectorElementType();
17495 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17497 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17498 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17499 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17502 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17503 if (Op.getValueType() == MVT::i1)
17504 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17505 Op.getOperand(0), Op.getOperand(1));
17506 assert(Op.getSimpleValueType().is256BitVector() &&
17507 Op.getSimpleValueType().isInteger() &&
17508 "Only handle AVX 256-bit vector integer operation");
17509 return Lower256IntArith(Op, DAG);
17512 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17513 if (Op.getValueType() == MVT::i1)
17514 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17515 Op.getOperand(0), Op.getOperand(1));
17516 assert(Op.getSimpleValueType().is256BitVector() &&
17517 Op.getSimpleValueType().isInteger() &&
17518 "Only handle AVX 256-bit vector integer operation");
17519 return Lower256IntArith(Op, DAG);
17522 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17523 assert(Op.getSimpleValueType().is256BitVector() &&
17524 Op.getSimpleValueType().isInteger() &&
17525 "Only handle AVX 256-bit vector integer operation");
17526 return Lower256IntArith(Op, DAG);
17529 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17530 SelectionDAG &DAG) {
17532 MVT VT = Op.getSimpleValueType();
17535 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17537 // Decompose 256-bit ops into smaller 128-bit ops.
17538 if (VT.is256BitVector() && !Subtarget->hasInt256())
17539 return Lower256IntArith(Op, DAG);
17541 SDValue A = Op.getOperand(0);
17542 SDValue B = Op.getOperand(1);
17544 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17545 // pairs, multiply and truncate.
17546 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17547 if (Subtarget->hasInt256()) {
17548 if (VT == MVT::v32i8) {
17549 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17550 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17551 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17552 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17553 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17554 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17555 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17556 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17557 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17558 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17561 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17562 return DAG.getNode(
17563 ISD::TRUNCATE, dl, VT,
17564 DAG.getNode(ISD::MUL, dl, ExVT,
17565 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17566 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17569 assert(VT == MVT::v16i8 &&
17570 "Pre-AVX2 support only supports v16i8 multiplication");
17571 MVT ExVT = MVT::v8i16;
17573 // Extract the lo parts and sign extend to i16
17575 if (Subtarget->hasSSE41()) {
17576 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17577 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17579 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17580 -1, 4, -1, 5, -1, 6, -1, 7};
17581 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17582 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17583 ALo = DAG.getBitcast(ExVT, ALo);
17584 BLo = DAG.getBitcast(ExVT, BLo);
17585 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17586 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17589 // Extract the hi parts and sign extend to i16
17591 if (Subtarget->hasSSE41()) {
17592 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17593 -1, -1, -1, -1, -1, -1, -1, -1};
17594 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17595 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17596 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17597 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17599 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17600 -1, 12, -1, 13, -1, 14, -1, 15};
17601 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17602 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17603 AHi = DAG.getBitcast(ExVT, AHi);
17604 BHi = DAG.getBitcast(ExVT, BHi);
17605 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17606 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17609 // Multiply, mask the lower 8bits of the lo/hi results and pack
17610 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17611 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17612 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17613 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17614 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17617 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17618 if (VT == MVT::v4i32) {
17619 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17620 "Should not custom lower when pmuldq is available!");
17622 // Extract the odd parts.
17623 static const int UnpackMask[] = { 1, -1, 3, -1 };
17624 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17625 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17627 // Multiply the even parts.
17628 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17629 // Now multiply odd parts.
17630 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17632 Evens = DAG.getBitcast(VT, Evens);
17633 Odds = DAG.getBitcast(VT, Odds);
17635 // Merge the two vectors back together with a shuffle. This expands into 2
17637 static const int ShufMask[] = { 0, 4, 2, 6 };
17638 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17641 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17642 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17644 // Ahi = psrlqi(a, 32);
17645 // Bhi = psrlqi(b, 32);
17647 // AloBlo = pmuludq(a, b);
17648 // AloBhi = pmuludq(a, Bhi);
17649 // AhiBlo = pmuludq(Ahi, b);
17651 // AloBhi = psllqi(AloBhi, 32);
17652 // AhiBlo = psllqi(AhiBlo, 32);
17653 // return AloBlo + AloBhi + AhiBlo;
17655 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17656 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17658 SDValue AhiBlo = Ahi;
17659 SDValue AloBhi = Bhi;
17660 // Bit cast to 32-bit vectors for MULUDQ
17661 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17662 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17663 A = DAG.getBitcast(MulVT, A);
17664 B = DAG.getBitcast(MulVT, B);
17665 Ahi = DAG.getBitcast(MulVT, Ahi);
17666 Bhi = DAG.getBitcast(MulVT, Bhi);
17668 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17669 // After shifting right const values the result may be all-zero.
17670 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17671 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17672 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17674 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17675 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17676 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17679 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17680 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17683 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17684 assert(Subtarget->isTargetWin64() && "Unexpected target");
17685 EVT VT = Op.getValueType();
17686 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17687 "Unexpected return type for lowering");
17691 switch (Op->getOpcode()) {
17692 default: llvm_unreachable("Unexpected request for libcall!");
17693 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17694 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17695 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17696 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17697 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17698 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17702 SDValue InChain = DAG.getEntryNode();
17704 TargetLowering::ArgListTy Args;
17705 TargetLowering::ArgListEntry Entry;
17706 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17707 EVT ArgVT = Op->getOperand(i).getValueType();
17708 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17709 "Unexpected argument type for lowering");
17710 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17711 Entry.Node = StackPtr;
17712 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17714 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17715 Entry.Ty = PointerType::get(ArgTy,0);
17716 Entry.isSExt = false;
17717 Entry.isZExt = false;
17718 Args.push_back(Entry);
17721 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17722 getPointerTy(DAG.getDataLayout()));
17724 TargetLowering::CallLoweringInfo CLI(DAG);
17725 CLI.setDebugLoc(dl).setChain(InChain)
17726 .setCallee(getLibcallCallingConv(LC),
17727 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17728 Callee, std::move(Args), 0)
17729 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17731 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17732 return DAG.getBitcast(VT, CallInfo.first);
17735 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17736 SelectionDAG &DAG) {
17737 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17738 EVT VT = Op0.getValueType();
17741 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17742 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17744 // PMULxD operations multiply each even value (starting at 0) of LHS with
17745 // the related value of RHS and produce a widen result.
17746 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17747 // => <2 x i64> <ae|cg>
17749 // In other word, to have all the results, we need to perform two PMULxD:
17750 // 1. one with the even values.
17751 // 2. one with the odd values.
17752 // To achieve #2, with need to place the odd values at an even position.
17754 // Place the odd value at an even position (basically, shift all values 1
17755 // step to the left):
17756 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17757 // <a|b|c|d> => <b|undef|d|undef>
17758 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17759 // <e|f|g|h> => <f|undef|h|undef>
17760 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17762 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17764 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17765 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17767 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17768 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17769 // => <2 x i64> <ae|cg>
17770 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17771 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17772 // => <2 x i64> <bf|dh>
17773 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17775 // Shuffle it back into the right order.
17776 SDValue Highs, Lows;
17777 if (VT == MVT::v8i32) {
17778 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17779 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17780 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17781 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17783 const int HighMask[] = {1, 5, 3, 7};
17784 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17785 const int LowMask[] = {0, 4, 2, 6};
17786 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17789 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17790 // unsigned multiply.
17791 if (IsSigned && !Subtarget->hasSSE41()) {
17792 SDValue ShAmt = DAG.getConstant(
17794 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17795 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17796 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17797 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17798 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17800 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17801 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17804 // The first result of MUL_LOHI is actually the low value, followed by the
17806 SDValue Ops[] = {Lows, Highs};
17807 return DAG.getMergeValues(Ops, dl);
17810 // Return true if the required (according to Opcode) shift-imm form is natively
17811 // supported by the Subtarget
17812 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17814 if (VT.getScalarSizeInBits() < 16)
17817 if (VT.is512BitVector() &&
17818 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17821 bool LShift = VT.is128BitVector() ||
17822 (VT.is256BitVector() && Subtarget->hasInt256());
17824 bool AShift = LShift && (Subtarget->hasVLX() ||
17825 (VT != MVT::v2i64 && VT != MVT::v4i64));
17826 return (Opcode == ISD::SRA) ? AShift : LShift;
17829 // The shift amount is a variable, but it is the same for all vector lanes.
17830 // These instructions are defined together with shift-immediate.
17832 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17834 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17837 // Return true if the required (according to Opcode) variable-shift form is
17838 // natively supported by the Subtarget
17839 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17842 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17845 // vXi16 supported only on AVX-512, BWI
17846 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17849 if (VT.is512BitVector() || Subtarget->hasVLX())
17852 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17853 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17854 return (Opcode == ISD::SRA) ? AShift : LShift;
17857 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17858 const X86Subtarget *Subtarget) {
17859 MVT VT = Op.getSimpleValueType();
17861 SDValue R = Op.getOperand(0);
17862 SDValue Amt = Op.getOperand(1);
17864 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17865 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17867 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17868 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17869 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17870 SDValue Ex = DAG.getBitcast(ExVT, R);
17872 if (ShiftAmt >= 32) {
17873 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17875 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17876 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17877 ShiftAmt - 32, DAG);
17878 if (VT == MVT::v2i64)
17879 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17880 if (VT == MVT::v4i64)
17881 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17882 {9, 1, 11, 3, 13, 5, 15, 7});
17884 // SRA upper i32, SHL whole i64 and select lower i32.
17885 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17888 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17889 Lower = DAG.getBitcast(ExVT, Lower);
17890 if (VT == MVT::v2i64)
17891 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17892 if (VT == MVT::v4i64)
17893 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17894 {8, 1, 10, 3, 12, 5, 14, 7});
17896 return DAG.getBitcast(VT, Ex);
17899 // Optimize shl/srl/sra with constant shift amount.
17900 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17901 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17902 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17904 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17905 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17907 // i64 SRA needs to be performed as partial shifts.
17908 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17909 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
17910 return ArithmeticShiftRight64(ShiftAmt);
17912 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17913 unsigned NumElts = VT.getVectorNumElements();
17914 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17916 // Simple i8 add case
17917 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
17918 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17920 // ashr(R, 7) === cmp_slt(R, 0)
17921 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
17922 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17923 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17926 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
17927 if (VT == MVT::v16i8 && Subtarget->hasXOP())
17930 if (Op.getOpcode() == ISD::SHL) {
17931 // Make a large shift.
17932 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17934 SHL = DAG.getBitcast(VT, SHL);
17935 // Zero out the rightmost bits.
17936 SmallVector<SDValue, 32> V(
17937 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17938 return DAG.getNode(ISD::AND, dl, VT, SHL,
17939 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17941 if (Op.getOpcode() == ISD::SRL) {
17942 // Make a large shift.
17943 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17945 SRL = DAG.getBitcast(VT, SRL);
17946 // Zero out the leftmost bits.
17947 SmallVector<SDValue, 32> V(
17948 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17949 return DAG.getNode(ISD::AND, dl, VT, SRL,
17950 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17952 if (Op.getOpcode() == ISD::SRA) {
17953 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
17954 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17955 SmallVector<SDValue, 32> V(NumElts,
17956 DAG.getConstant(128 >> ShiftAmt, dl,
17958 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17959 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17960 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17963 llvm_unreachable("Unknown shift opcode.");
17968 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17969 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
17970 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
17972 // Peek through any splat that was introduced for i64 shift vectorization.
17973 int SplatIndex = -1;
17974 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
17975 if (SVN->isSplat()) {
17976 SplatIndex = SVN->getSplatIndex();
17977 Amt = Amt.getOperand(0);
17978 assert(SplatIndex < (int)VT.getVectorNumElements() &&
17979 "Splat shuffle referencing second operand");
17982 if (Amt.getOpcode() != ISD::BITCAST ||
17983 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
17986 Amt = Amt.getOperand(0);
17987 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17988 VT.getVectorNumElements();
17989 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17990 uint64_t ShiftAmt = 0;
17991 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
17992 for (unsigned i = 0; i != Ratio; ++i) {
17993 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
17997 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18000 // Check remaining shift amounts (if not a splat).
18001 if (SplatIndex < 0) {
18002 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18003 uint64_t ShAmt = 0;
18004 for (unsigned j = 0; j != Ratio; ++j) {
18005 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18009 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18011 if (ShAmt != ShiftAmt)
18016 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18017 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18019 if (Op.getOpcode() == ISD::SRA)
18020 return ArithmeticShiftRight64(ShiftAmt);
18026 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18027 const X86Subtarget* Subtarget) {
18028 MVT VT = Op.getSimpleValueType();
18030 SDValue R = Op.getOperand(0);
18031 SDValue Amt = Op.getOperand(1);
18033 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18034 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18036 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18037 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18039 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18041 EVT EltVT = VT.getVectorElementType();
18043 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18044 // Check if this build_vector node is doing a splat.
18045 // If so, then set BaseShAmt equal to the splat value.
18046 BaseShAmt = BV->getSplatValue();
18047 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18048 BaseShAmt = SDValue();
18050 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18051 Amt = Amt.getOperand(0);
18053 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18054 if (SVN && SVN->isSplat()) {
18055 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18056 SDValue InVec = Amt.getOperand(0);
18057 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18058 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18059 "Unexpected shuffle index found!");
18060 BaseShAmt = InVec.getOperand(SplatIdx);
18061 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18062 if (ConstantSDNode *C =
18063 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18064 if (C->getZExtValue() == SplatIdx)
18065 BaseShAmt = InVec.getOperand(1);
18070 // Avoid introducing an extract element from a shuffle.
18071 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18072 DAG.getIntPtrConstant(SplatIdx, dl));
18076 if (BaseShAmt.getNode()) {
18077 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18078 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18079 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18080 else if (EltVT.bitsLT(MVT::i32))
18081 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18083 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18087 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18088 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18089 Amt.getOpcode() == ISD::BITCAST &&
18090 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18091 Amt = Amt.getOperand(0);
18092 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18093 VT.getVectorNumElements();
18094 std::vector<SDValue> Vals(Ratio);
18095 for (unsigned i = 0; i != Ratio; ++i)
18096 Vals[i] = Amt.getOperand(i);
18097 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18098 for (unsigned j = 0; j != Ratio; ++j)
18099 if (Vals[j] != Amt.getOperand(i + j))
18103 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18104 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18109 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18110 SelectionDAG &DAG) {
18111 MVT VT = Op.getSimpleValueType();
18113 SDValue R = Op.getOperand(0);
18114 SDValue Amt = Op.getOperand(1);
18116 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18117 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18119 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18122 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18125 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18128 // XOP has 128-bit variable logical/arithmetic shifts.
18129 // +ve/-ve Amt = shift left/right.
18130 if (Subtarget->hasXOP() &&
18131 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18132 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18133 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18134 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18135 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18137 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18138 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18139 if (Op.getOpcode() == ISD::SRA)
18140 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18143 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18144 // shifts per-lane and then shuffle the partial results back together.
18145 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18146 // Splat the shift amounts so the scalar shifts above will catch it.
18147 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18148 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18149 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18150 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18151 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18154 // i64 vector arithmetic shift can be emulated with the transform:
18155 // M = lshr(SIGN_BIT, Amt)
18156 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18157 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18158 Op.getOpcode() == ISD::SRA) {
18159 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18160 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18161 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18162 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18163 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18167 // If possible, lower this packed shift into a vector multiply instead of
18168 // expanding it into a sequence of scalar shifts.
18169 // Do this only if the vector shift count is a constant build_vector.
18170 if (Op.getOpcode() == ISD::SHL &&
18171 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18172 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18173 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18174 SmallVector<SDValue, 8> Elts;
18175 EVT SVT = VT.getScalarType();
18176 unsigned SVTBits = SVT.getSizeInBits();
18177 const APInt &One = APInt(SVTBits, 1);
18178 unsigned NumElems = VT.getVectorNumElements();
18180 for (unsigned i=0; i !=NumElems; ++i) {
18181 SDValue Op = Amt->getOperand(i);
18182 if (Op->getOpcode() == ISD::UNDEF) {
18183 Elts.push_back(Op);
18187 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18188 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18189 uint64_t ShAmt = C.getZExtValue();
18190 if (ShAmt >= SVTBits) {
18191 Elts.push_back(DAG.getUNDEF(SVT));
18194 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18196 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18197 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18200 // Lower SHL with variable shift amount.
18201 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18202 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18204 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18205 DAG.getConstant(0x3f800000U, dl, VT));
18206 Op = DAG.getBitcast(MVT::v4f32, Op);
18207 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18208 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18211 // If possible, lower this shift as a sequence of two shifts by
18212 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18214 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18216 // Could be rewritten as:
18217 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18219 // The advantage is that the two shifts from the example would be
18220 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18221 // the vector shift into four scalar shifts plus four pairs of vector
18223 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18224 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18225 unsigned TargetOpcode = X86ISD::MOVSS;
18226 bool CanBeSimplified;
18227 // The splat value for the first packed shift (the 'X' from the example).
18228 SDValue Amt1 = Amt->getOperand(0);
18229 // The splat value for the second packed shift (the 'Y' from the example).
18230 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18231 Amt->getOperand(2);
18233 // See if it is possible to replace this node with a sequence of
18234 // two shifts followed by a MOVSS/MOVSD
18235 if (VT == MVT::v4i32) {
18236 // Check if it is legal to use a MOVSS.
18237 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18238 Amt2 == Amt->getOperand(3);
18239 if (!CanBeSimplified) {
18240 // Otherwise, check if we can still simplify this node using a MOVSD.
18241 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18242 Amt->getOperand(2) == Amt->getOperand(3);
18243 TargetOpcode = X86ISD::MOVSD;
18244 Amt2 = Amt->getOperand(2);
18247 // Do similar checks for the case where the machine value type
18249 CanBeSimplified = Amt1 == Amt->getOperand(1);
18250 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18251 CanBeSimplified = Amt2 == Amt->getOperand(i);
18253 if (!CanBeSimplified) {
18254 TargetOpcode = X86ISD::MOVSD;
18255 CanBeSimplified = true;
18256 Amt2 = Amt->getOperand(4);
18257 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18258 CanBeSimplified = Amt1 == Amt->getOperand(i);
18259 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18260 CanBeSimplified = Amt2 == Amt->getOperand(j);
18264 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18265 isa<ConstantSDNode>(Amt2)) {
18266 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18267 EVT CastVT = MVT::v4i32;
18269 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18270 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18272 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18273 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18274 if (TargetOpcode == X86ISD::MOVSD)
18275 CastVT = MVT::v2i64;
18276 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18277 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18278 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18280 return DAG.getBitcast(VT, Result);
18284 // v4i32 Non Uniform Shifts.
18285 // If the shift amount is constant we can shift each lane using the SSE2
18286 // immediate shifts, else we need to zero-extend each lane to the lower i64
18287 // and shift using the SSE2 variable shifts.
18288 // The separate results can then be blended together.
18289 if (VT == MVT::v4i32) {
18290 unsigned Opc = Op.getOpcode();
18291 SDValue Amt0, Amt1, Amt2, Amt3;
18292 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18293 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18294 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18295 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18296 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18298 // ISD::SHL is handled above but we include it here for completeness.
18301 llvm_unreachable("Unknown target vector shift node");
18303 Opc = X86ISD::VSHL;
18306 Opc = X86ISD::VSRL;
18309 Opc = X86ISD::VSRA;
18312 // The SSE2 shifts use the lower i64 as the same shift amount for
18313 // all lanes and the upper i64 is ignored. These shuffle masks
18314 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18315 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18316 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18317 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18318 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18319 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18322 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18323 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18324 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18325 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18326 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18327 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18328 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18331 if (VT == MVT::v16i8 ||
18332 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18333 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18334 unsigned ShiftOpcode = Op->getOpcode();
18336 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18337 // On SSE41 targets we make use of the fact that VSELECT lowers
18338 // to PBLENDVB which selects bytes based just on the sign bit.
18339 if (Subtarget->hasSSE41()) {
18340 V0 = DAG.getBitcast(VT, V0);
18341 V1 = DAG.getBitcast(VT, V1);
18342 Sel = DAG.getBitcast(VT, Sel);
18343 return DAG.getBitcast(SelVT,
18344 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18346 // On pre-SSE41 targets we test for the sign bit by comparing to
18347 // zero - a negative value will set all bits of the lanes to true
18348 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18349 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18350 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18351 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18354 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18355 // We can safely do this using i16 shifts as we're only interested in
18356 // the 3 lower bits of each byte.
18357 Amt = DAG.getBitcast(ExtVT, Amt);
18358 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18359 Amt = DAG.getBitcast(VT, Amt);
18361 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18362 // r = VSELECT(r, shift(r, 4), a);
18364 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18365 R = SignBitSelect(VT, Amt, M, R);
18368 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18370 // r = VSELECT(r, shift(r, 2), a);
18371 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18372 R = SignBitSelect(VT, Amt, M, R);
18375 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18377 // return VSELECT(r, shift(r, 1), a);
18378 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18379 R = SignBitSelect(VT, Amt, M, R);
18383 if (Op->getOpcode() == ISD::SRA) {
18384 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18385 // so we can correctly sign extend. We don't care what happens to the
18387 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18388 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18389 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18390 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18391 ALo = DAG.getBitcast(ExtVT, ALo);
18392 AHi = DAG.getBitcast(ExtVT, AHi);
18393 RLo = DAG.getBitcast(ExtVT, RLo);
18394 RHi = DAG.getBitcast(ExtVT, RHi);
18396 // r = VSELECT(r, shift(r, 4), a);
18397 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18398 DAG.getConstant(4, dl, ExtVT));
18399 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18400 DAG.getConstant(4, dl, ExtVT));
18401 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18402 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18405 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18406 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18408 // r = VSELECT(r, shift(r, 2), a);
18409 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18410 DAG.getConstant(2, dl, ExtVT));
18411 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18412 DAG.getConstant(2, dl, ExtVT));
18413 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18414 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18417 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18418 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18420 // r = VSELECT(r, shift(r, 1), a);
18421 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18422 DAG.getConstant(1, dl, ExtVT));
18423 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18424 DAG.getConstant(1, dl, ExtVT));
18425 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18426 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18428 // Logical shift the result back to the lower byte, leaving a zero upper
18430 // meaning that we can safely pack with PACKUSWB.
18432 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18434 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18435 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18439 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18440 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18441 // solution better.
18442 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18443 MVT ExtVT = MVT::v8i32;
18445 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18446 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18447 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18448 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18449 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18452 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18453 MVT ExtVT = MVT::v8i32;
18454 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18455 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18456 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18457 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18458 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18459 ALo = DAG.getBitcast(ExtVT, ALo);
18460 AHi = DAG.getBitcast(ExtVT, AHi);
18461 RLo = DAG.getBitcast(ExtVT, RLo);
18462 RHi = DAG.getBitcast(ExtVT, RHi);
18463 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18464 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18465 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18466 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18467 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18470 if (VT == MVT::v8i16) {
18471 unsigned ShiftOpcode = Op->getOpcode();
18473 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18474 // On SSE41 targets we make use of the fact that VSELECT lowers
18475 // to PBLENDVB which selects bytes based just on the sign bit.
18476 if (Subtarget->hasSSE41()) {
18477 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18478 V0 = DAG.getBitcast(ExtVT, V0);
18479 V1 = DAG.getBitcast(ExtVT, V1);
18480 Sel = DAG.getBitcast(ExtVT, Sel);
18481 return DAG.getBitcast(
18482 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18484 // On pre-SSE41 targets we splat the sign bit - a negative value will
18485 // set all bits of the lanes to true and VSELECT uses that in
18486 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18488 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18489 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18492 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18493 if (Subtarget->hasSSE41()) {
18494 // On SSE41 targets we need to replicate the shift mask in both
18495 // bytes for PBLENDVB.
18498 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18499 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18501 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18504 // r = VSELECT(r, shift(r, 8), a);
18505 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18506 R = SignBitSelect(Amt, M, R);
18509 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18511 // r = VSELECT(r, shift(r, 4), a);
18512 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18513 R = SignBitSelect(Amt, M, R);
18516 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18518 // r = VSELECT(r, shift(r, 2), a);
18519 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18520 R = SignBitSelect(Amt, M, R);
18523 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18525 // return VSELECT(r, shift(r, 1), a);
18526 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18527 R = SignBitSelect(Amt, M, R);
18531 // Decompose 256-bit shifts into smaller 128-bit shifts.
18532 if (VT.is256BitVector()) {
18533 unsigned NumElems = VT.getVectorNumElements();
18534 MVT EltVT = VT.getVectorElementType();
18535 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18537 // Extract the two vectors
18538 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18539 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18541 // Recreate the shift amount vectors
18542 SDValue Amt1, Amt2;
18543 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18544 // Constant shift amount
18545 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18546 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18547 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18549 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18550 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18552 // Variable shift amount
18553 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18554 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18557 // Issue new vector shifts for the smaller types
18558 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18559 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18561 // Concatenate the result back
18562 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18568 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18569 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18570 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18571 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18572 // has only one use.
18573 SDNode *N = Op.getNode();
18574 SDValue LHS = N->getOperand(0);
18575 SDValue RHS = N->getOperand(1);
18576 unsigned BaseOp = 0;
18579 switch (Op.getOpcode()) {
18580 default: llvm_unreachable("Unknown ovf instruction!");
18582 // A subtract of one will be selected as a INC. Note that INC doesn't
18583 // set CF, so we can't do this for UADDO.
18584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18586 BaseOp = X86ISD::INC;
18587 Cond = X86::COND_O;
18590 BaseOp = X86ISD::ADD;
18591 Cond = X86::COND_O;
18594 BaseOp = X86ISD::ADD;
18595 Cond = X86::COND_B;
18598 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18599 // set CF, so we can't do this for USUBO.
18600 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18602 BaseOp = X86ISD::DEC;
18603 Cond = X86::COND_O;
18606 BaseOp = X86ISD::SUB;
18607 Cond = X86::COND_O;
18610 BaseOp = X86ISD::SUB;
18611 Cond = X86::COND_B;
18614 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18615 Cond = X86::COND_O;
18617 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18618 if (N->getValueType(0) == MVT::i8) {
18619 BaseOp = X86ISD::UMUL8;
18620 Cond = X86::COND_O;
18623 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18625 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18628 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18629 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18630 SDValue(Sum.getNode(), 2));
18632 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18636 // Also sets EFLAGS.
18637 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18638 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18641 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18642 DAG.getConstant(Cond, DL, MVT::i32),
18643 SDValue(Sum.getNode(), 1));
18645 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18648 /// Returns true if the operand type is exactly twice the native width, and
18649 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18650 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18651 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18652 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18653 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18656 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18657 else if (OpWidth == 128)
18658 return Subtarget->hasCmpxchg16b();
18663 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18664 return needsCmpXchgNb(SI->getValueOperand()->getType());
18667 // Note: this turns large loads into lock cmpxchg8b/16b.
18668 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18669 TargetLowering::AtomicExpansionKind
18670 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18671 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18672 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18673 : AtomicExpansionKind::None;
18676 TargetLowering::AtomicExpansionKind
18677 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18678 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18679 Type *MemType = AI->getType();
18681 // If the operand is too big, we must see if cmpxchg8/16b is available
18682 // and default to library calls otherwise.
18683 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18684 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18685 : AtomicExpansionKind::None;
18688 AtomicRMWInst::BinOp Op = AI->getOperation();
18691 llvm_unreachable("Unknown atomic operation");
18692 case AtomicRMWInst::Xchg:
18693 case AtomicRMWInst::Add:
18694 case AtomicRMWInst::Sub:
18695 // It's better to use xadd, xsub or xchg for these in all cases.
18696 return AtomicExpansionKind::None;
18697 case AtomicRMWInst::Or:
18698 case AtomicRMWInst::And:
18699 case AtomicRMWInst::Xor:
18700 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18701 // prefix to a normal instruction for these operations.
18702 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18703 : AtomicExpansionKind::None;
18704 case AtomicRMWInst::Nand:
18705 case AtomicRMWInst::Max:
18706 case AtomicRMWInst::Min:
18707 case AtomicRMWInst::UMax:
18708 case AtomicRMWInst::UMin:
18709 // These always require a non-trivial set of data operations on x86. We must
18710 // use a cmpxchg loop.
18711 return AtomicExpansionKind::CmpXChg;
18715 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18716 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18717 // no-sse2). There isn't any reason to disable it if the target processor
18719 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18723 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18724 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18725 Type *MemType = AI->getType();
18726 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18727 // there is no benefit in turning such RMWs into loads, and it is actually
18728 // harmful as it introduces a mfence.
18729 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18732 auto Builder = IRBuilder<>(AI);
18733 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18734 auto SynchScope = AI->getSynchScope();
18735 // We must restrict the ordering to avoid generating loads with Release or
18736 // ReleaseAcquire orderings.
18737 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18738 auto Ptr = AI->getPointerOperand();
18740 // Before the load we need a fence. Here is an example lifted from
18741 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18744 // x.store(1, relaxed);
18745 // r1 = y.fetch_add(0, release);
18747 // y.fetch_add(42, acquire);
18748 // r2 = x.load(relaxed);
18749 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18750 // lowered to just a load without a fence. A mfence flushes the store buffer,
18751 // making the optimization clearly correct.
18752 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18753 // otherwise, we might be able to be more aggressive on relaxed idempotent
18754 // rmw. In practice, they do not look useful, so we don't try to be
18755 // especially clever.
18756 if (SynchScope == SingleThread)
18757 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18758 // the IR level, so we must wrap it in an intrinsic.
18761 if (!hasMFENCE(*Subtarget))
18762 // FIXME: it might make sense to use a locked operation here but on a
18763 // different cache-line to prevent cache-line bouncing. In practice it
18764 // is probably a small win, and x86 processors without mfence are rare
18765 // enough that we do not bother.
18769 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18770 Builder.CreateCall(MFence, {});
18772 // Finally we can emit the atomic load.
18773 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18774 AI->getType()->getPrimitiveSizeInBits());
18775 Loaded->setAtomic(Order, SynchScope);
18776 AI->replaceAllUsesWith(Loaded);
18777 AI->eraseFromParent();
18781 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18782 SelectionDAG &DAG) {
18784 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18785 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18786 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18787 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18789 // The only fence that needs an instruction is a sequentially-consistent
18790 // cross-thread fence.
18791 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18792 if (hasMFENCE(*Subtarget))
18793 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18795 SDValue Chain = Op.getOperand(0);
18796 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18798 DAG.getRegister(X86::ESP, MVT::i32), // Base
18799 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18800 DAG.getRegister(0, MVT::i32), // Index
18801 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18802 DAG.getRegister(0, MVT::i32), // Segment.
18806 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18807 return SDValue(Res, 0);
18810 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18811 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18814 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18815 SelectionDAG &DAG) {
18816 MVT T = Op.getSimpleValueType();
18820 switch(T.SimpleTy) {
18821 default: llvm_unreachable("Invalid value type!");
18822 case MVT::i8: Reg = X86::AL; size = 1; break;
18823 case MVT::i16: Reg = X86::AX; size = 2; break;
18824 case MVT::i32: Reg = X86::EAX; size = 4; break;
18826 assert(Subtarget->is64Bit() && "Node not type legal!");
18827 Reg = X86::RAX; size = 8;
18830 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18831 Op.getOperand(2), SDValue());
18832 SDValue Ops[] = { cpIn.getValue(0),
18835 DAG.getTargetConstant(size, DL, MVT::i8),
18836 cpIn.getValue(1) };
18837 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18838 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18839 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18843 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18844 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18845 MVT::i32, cpOut.getValue(2));
18846 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18847 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18850 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18851 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18852 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18856 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18857 SelectionDAG &DAG) {
18858 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18859 MVT DstVT = Op.getSimpleValueType();
18861 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18862 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18863 if (DstVT != MVT::f64)
18864 // This conversion needs to be expanded.
18867 SDValue InVec = Op->getOperand(0);
18869 unsigned NumElts = SrcVT.getVectorNumElements();
18870 EVT SVT = SrcVT.getVectorElementType();
18872 // Widen the vector in input in the case of MVT::v2i32.
18873 // Example: from MVT::v2i32 to MVT::v4i32.
18874 SmallVector<SDValue, 16> Elts;
18875 for (unsigned i = 0, e = NumElts; i != e; ++i)
18876 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18877 DAG.getIntPtrConstant(i, dl)));
18879 // Explicitly mark the extra elements as Undef.
18880 Elts.append(NumElts, DAG.getUNDEF(SVT));
18882 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18883 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18884 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18885 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18886 DAG.getIntPtrConstant(0, dl));
18889 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18890 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18891 assert((DstVT == MVT::i64 ||
18892 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18893 "Unexpected custom BITCAST");
18894 // i64 <=> MMX conversions are Legal.
18895 if (SrcVT==MVT::i64 && DstVT.isVector())
18897 if (DstVT==MVT::i64 && SrcVT.isVector())
18899 // MMX <=> MMX conversions are Legal.
18900 if (SrcVT.isVector() && DstVT.isVector())
18902 // All other conversions need to be expanded.
18906 /// Compute the horizontal sum of bytes in V for the elements of VT.
18908 /// Requires V to be a byte vector and VT to be an integer vector type with
18909 /// wider elements than V's type. The width of the elements of VT determines
18910 /// how many bytes of V are summed horizontally to produce each element of the
18912 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18913 const X86Subtarget *Subtarget,
18914 SelectionDAG &DAG) {
18916 MVT ByteVecVT = V.getSimpleValueType();
18917 MVT EltVT = VT.getVectorElementType();
18918 int NumElts = VT.getVectorNumElements();
18919 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18920 "Expected value to have byte element type.");
18921 assert(EltVT != MVT::i8 &&
18922 "Horizontal byte sum only makes sense for wider elements!");
18923 unsigned VecSize = VT.getSizeInBits();
18924 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18926 // PSADBW instruction horizontally add all bytes and leave the result in i64
18927 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18928 if (EltVT == MVT::i64) {
18929 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18930 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18931 return DAG.getBitcast(VT, V);
18934 if (EltVT == MVT::i32) {
18935 // We unpack the low half and high half into i32s interleaved with zeros so
18936 // that we can use PSADBW to horizontally sum them. The most useful part of
18937 // this is that it lines up the results of two PSADBW instructions to be
18938 // two v2i64 vectors which concatenated are the 4 population counts. We can
18939 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18940 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18941 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18942 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18944 // Do the horizontal sums into two v2i64s.
18945 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18946 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18947 DAG.getBitcast(ByteVecVT, Low), Zeros);
18948 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18949 DAG.getBitcast(ByteVecVT, High), Zeros);
18951 // Merge them together.
18952 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18953 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18954 DAG.getBitcast(ShortVecVT, Low),
18955 DAG.getBitcast(ShortVecVT, High));
18957 return DAG.getBitcast(VT, V);
18960 // The only element type left is i16.
18961 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18963 // To obtain pop count for each i16 element starting from the pop count for
18964 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18965 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18966 // directly supported.
18967 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18968 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18969 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18970 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18971 DAG.getBitcast(ByteVecVT, V));
18972 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18975 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18976 const X86Subtarget *Subtarget,
18977 SelectionDAG &DAG) {
18978 MVT VT = Op.getSimpleValueType();
18979 MVT EltVT = VT.getVectorElementType();
18980 unsigned VecSize = VT.getSizeInBits();
18982 // Implement a lookup table in register by using an algorithm based on:
18983 // http://wm.ite.pl/articles/sse-popcount.html
18985 // The general idea is that every lower byte nibble in the input vector is an
18986 // index into a in-register pre-computed pop count table. We then split up the
18987 // input vector in two new ones: (1) a vector with only the shifted-right
18988 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18989 // masked out higher ones) for each byte. PSHUB is used separately with both
18990 // to index the in-register table. Next, both are added and the result is a
18991 // i8 vector where each element contains the pop count for input byte.
18993 // To obtain the pop count for elements != i8, we follow up with the same
18994 // approach and use additional tricks as described below.
18996 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18997 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18998 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18999 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19001 int NumByteElts = VecSize / 8;
19002 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19003 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19004 SmallVector<SDValue, 16> LUTVec;
19005 for (int i = 0; i < NumByteElts; ++i)
19006 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19007 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19008 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19009 DAG.getConstant(0x0F, DL, MVT::i8));
19010 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19013 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19014 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19015 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19018 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19020 // The input vector is used as the shuffle mask that index elements into the
19021 // LUT. After counting low and high nibbles, add the vector to obtain the
19022 // final pop count per i8 element.
19023 SDValue HighPopCnt =
19024 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19025 SDValue LowPopCnt =
19026 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19027 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19029 if (EltVT == MVT::i8)
19032 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19035 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19036 const X86Subtarget *Subtarget,
19037 SelectionDAG &DAG) {
19038 MVT VT = Op.getSimpleValueType();
19039 assert(VT.is128BitVector() &&
19040 "Only 128-bit vector bitmath lowering supported.");
19042 int VecSize = VT.getSizeInBits();
19043 MVT EltVT = VT.getVectorElementType();
19044 int Len = EltVT.getSizeInBits();
19046 // This is the vectorized version of the "best" algorithm from
19047 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19048 // with a minor tweak to use a series of adds + shifts instead of vector
19049 // multiplications. Implemented for all integer vector types. We only use
19050 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19051 // much faster, even faster than using native popcnt instructions.
19053 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19054 MVT VT = V.getSimpleValueType();
19055 SmallVector<SDValue, 32> Shifters(
19056 VT.getVectorNumElements(),
19057 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19058 return DAG.getNode(OpCode, DL, VT, V,
19059 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19061 auto GetMask = [&](SDValue V, APInt Mask) {
19062 MVT VT = V.getSimpleValueType();
19063 SmallVector<SDValue, 32> Masks(
19064 VT.getVectorNumElements(),
19065 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19066 return DAG.getNode(ISD::AND, DL, VT, V,
19067 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19070 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19071 // x86, so set the SRL type to have elements at least i16 wide. This is
19072 // correct because all of our SRLs are followed immediately by a mask anyways
19073 // that handles any bits that sneak into the high bits of the byte elements.
19074 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19078 // v = v - ((v >> 1) & 0x55555555...)
19080 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19081 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19082 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19084 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19085 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19086 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19087 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19088 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19090 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19091 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19092 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19093 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19095 // At this point, V contains the byte-wise population count, and we are
19096 // merely doing a horizontal sum if necessary to get the wider element
19098 if (EltVT == MVT::i8)
19101 return LowerHorizontalByteSum(
19102 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19106 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19107 SelectionDAG &DAG) {
19108 MVT VT = Op.getSimpleValueType();
19109 // FIXME: Need to add AVX-512 support here!
19110 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19111 "Unknown CTPOP type to handle");
19112 SDLoc DL(Op.getNode());
19113 SDValue Op0 = Op.getOperand(0);
19115 if (!Subtarget->hasSSSE3()) {
19116 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19117 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19118 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19121 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19122 unsigned NumElems = VT.getVectorNumElements();
19124 // Extract each 128-bit vector, compute pop count and concat the result.
19125 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19126 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19128 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19129 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19130 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19133 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19136 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19137 SelectionDAG &DAG) {
19138 assert(Op.getValueType().isVector() &&
19139 "We only do custom lowering for vector population count.");
19140 return LowerVectorCTPOP(Op, Subtarget, DAG);
19143 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19144 SDNode *Node = Op.getNode();
19146 EVT T = Node->getValueType(0);
19147 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19148 DAG.getConstant(0, dl, T), Node->getOperand(2));
19149 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19150 cast<AtomicSDNode>(Node)->getMemoryVT(),
19151 Node->getOperand(0),
19152 Node->getOperand(1), negOp,
19153 cast<AtomicSDNode>(Node)->getMemOperand(),
19154 cast<AtomicSDNode>(Node)->getOrdering(),
19155 cast<AtomicSDNode>(Node)->getSynchScope());
19158 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19159 SDNode *Node = Op.getNode();
19161 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19163 // Convert seq_cst store -> xchg
19164 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19165 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19166 // (The only way to get a 16-byte store is cmpxchg16b)
19167 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19168 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19169 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19170 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19171 cast<AtomicSDNode>(Node)->getMemoryVT(),
19172 Node->getOperand(0),
19173 Node->getOperand(1), Node->getOperand(2),
19174 cast<AtomicSDNode>(Node)->getMemOperand(),
19175 cast<AtomicSDNode>(Node)->getOrdering(),
19176 cast<AtomicSDNode>(Node)->getSynchScope());
19177 return Swap.getValue(1);
19179 // Other atomic stores have a simple pattern.
19183 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19184 EVT VT = Op.getNode()->getSimpleValueType(0);
19186 // Let legalize expand this if it isn't a legal type yet.
19187 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19190 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19193 bool ExtraOp = false;
19194 switch (Op.getOpcode()) {
19195 default: llvm_unreachable("Invalid code");
19196 case ISD::ADDC: Opc = X86ISD::ADD; break;
19197 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19198 case ISD::SUBC: Opc = X86ISD::SUB; break;
19199 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19203 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19205 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19206 Op.getOperand(1), Op.getOperand(2));
19209 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19210 SelectionDAG &DAG) {
19211 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19213 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19214 // which returns the values as { float, float } (in XMM0) or
19215 // { double, double } (which is returned in XMM0, XMM1).
19217 SDValue Arg = Op.getOperand(0);
19218 EVT ArgVT = Arg.getValueType();
19219 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19221 TargetLowering::ArgListTy Args;
19222 TargetLowering::ArgListEntry Entry;
19226 Entry.isSExt = false;
19227 Entry.isZExt = false;
19228 Args.push_back(Entry);
19230 bool isF64 = ArgVT == MVT::f64;
19231 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19232 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19233 // the results are returned via SRet in memory.
19234 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19235 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19237 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19239 Type *RetTy = isF64
19240 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19241 : (Type*)VectorType::get(ArgTy, 4);
19243 TargetLowering::CallLoweringInfo CLI(DAG);
19244 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19245 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19247 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19250 // Returned in xmm0 and xmm1.
19251 return CallResult.first;
19253 // Returned in bits 0:31 and 32:64 xmm0.
19254 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19255 CallResult.first, DAG.getIntPtrConstant(0, dl));
19256 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19257 CallResult.first, DAG.getIntPtrConstant(1, dl));
19258 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19259 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19262 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19263 SelectionDAG &DAG) {
19264 assert(Subtarget->hasAVX512() &&
19265 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19267 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19268 EVT VT = N->getValue().getValueType();
19269 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19272 // X86 scatter kills mask register, so its type should be added to
19273 // the list of return values
19274 if (N->getNumValues() == 1) {
19275 SDValue Index = N->getIndex();
19276 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19277 !Index.getValueType().is512BitVector())
19278 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19280 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19281 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19282 N->getOperand(3), Index };
19284 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19285 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19286 return SDValue(NewScatter.getNode(), 0);
19291 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19292 SelectionDAG &DAG) {
19293 assert(Subtarget->hasAVX512() &&
19294 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19296 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19297 EVT VT = Op.getValueType();
19298 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19301 SDValue Index = N->getIndex();
19302 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19303 !Index.getValueType().is512BitVector()) {
19304 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19305 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19306 N->getOperand(3), Index };
19307 DAG.UpdateNodeOperands(N, Ops);
19312 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19313 SelectionDAG &DAG) const {
19314 // TODO: Eventually, the lowering of these nodes should be informed by or
19315 // deferred to the GC strategy for the function in which they appear. For
19316 // now, however, they must be lowered to something. Since they are logically
19317 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19318 // require special handling for these nodes), lower them as literal NOOPs for
19320 SmallVector<SDValue, 2> Ops;
19322 Ops.push_back(Op.getOperand(0));
19323 if (Op->getGluedNode())
19324 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19327 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19328 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19333 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19334 SelectionDAG &DAG) const {
19335 // TODO: Eventually, the lowering of these nodes should be informed by or
19336 // deferred to the GC strategy for the function in which they appear. For
19337 // now, however, they must be lowered to something. Since they are logically
19338 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19339 // require special handling for these nodes), lower them as literal NOOPs for
19341 SmallVector<SDValue, 2> Ops;
19343 Ops.push_back(Op.getOperand(0));
19344 if (Op->getGluedNode())
19345 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19348 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19349 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19354 /// LowerOperation - Provide custom lowering hooks for some operations.
19356 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19357 switch (Op.getOpcode()) {
19358 default: llvm_unreachable("Should not custom lower this!");
19359 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19360 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19361 return LowerCMP_SWAP(Op, Subtarget, DAG);
19362 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19363 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19364 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19365 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19366 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19367 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19368 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19369 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19370 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19371 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19372 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19373 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19374 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19375 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19376 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19377 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19378 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19379 case ISD::SHL_PARTS:
19380 case ISD::SRA_PARTS:
19381 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19382 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19383 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19384 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19385 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19386 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19387 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19388 case ISD::SIGN_EXTEND_VECTOR_INREG:
19389 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19390 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19391 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19392 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19393 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19395 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19396 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19397 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19398 case ISD::SETCC: return LowerSETCC(Op, DAG);
19399 case ISD::SELECT: return LowerSELECT(Op, DAG);
19400 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19401 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19402 case ISD::VASTART: return LowerVASTART(Op, DAG);
19403 case ISD::VAARG: return LowerVAARG(Op, DAG);
19404 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19405 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19406 case ISD::INTRINSIC_VOID:
19407 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19408 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19409 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19410 case ISD::FRAME_TO_ARGS_OFFSET:
19411 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19412 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19413 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19414 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19415 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19416 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19417 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19418 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19419 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19420 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19422 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19423 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19424 case ISD::UMUL_LOHI:
19425 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19428 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19434 case ISD::UMULO: return LowerXALUO(Op, DAG);
19435 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19436 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19440 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19441 case ISD::ADD: return LowerADD(Op, DAG);
19442 case ISD::SUB: return LowerSUB(Op, DAG);
19446 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19447 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19448 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19449 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19450 case ISD::GC_TRANSITION_START:
19451 return LowerGC_TRANSITION_START(Op, DAG);
19452 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19456 /// ReplaceNodeResults - Replace a node with an illegal result type
19457 /// with a new node built out of custom code.
19458 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19459 SmallVectorImpl<SDValue>&Results,
19460 SelectionDAG &DAG) const {
19462 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19463 switch (N->getOpcode()) {
19465 llvm_unreachable("Do not know how to custom type legalize this operation!");
19466 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19467 case X86ISD::FMINC:
19469 case X86ISD::FMAXC:
19470 case X86ISD::FMAX: {
19471 EVT VT = N->getValueType(0);
19472 if (VT != MVT::v2f32)
19473 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19474 SDValue UNDEF = DAG.getUNDEF(VT);
19475 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19476 N->getOperand(0), UNDEF);
19477 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19478 N->getOperand(1), UNDEF);
19479 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19482 case ISD::SIGN_EXTEND_INREG:
19487 // We don't want to expand or promote these.
19494 case ISD::UDIVREM: {
19495 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19496 Results.push_back(V);
19499 case ISD::FP_TO_SINT:
19500 case ISD::FP_TO_UINT: {
19501 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19503 std::pair<SDValue,SDValue> Vals =
19504 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19505 SDValue FIST = Vals.first, StackSlot = Vals.second;
19506 if (FIST.getNode()) {
19507 EVT VT = N->getValueType(0);
19508 // Return a load from the stack slot.
19509 if (StackSlot.getNode())
19510 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19511 MachinePointerInfo(),
19512 false, false, false, 0));
19514 Results.push_back(FIST);
19518 case ISD::UINT_TO_FP: {
19519 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19520 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19521 N->getValueType(0) != MVT::v2f32)
19523 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19525 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19527 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19528 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19529 DAG.getBitcast(MVT::v2i64, VBias));
19530 Or = DAG.getBitcast(MVT::v2f64, Or);
19531 // TODO: Are there any fast-math-flags to propagate here?
19532 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19533 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19536 case ISD::FP_ROUND: {
19537 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19539 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19540 Results.push_back(V);
19543 case ISD::FP_EXTEND: {
19544 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19545 // No other ValueType for FP_EXTEND should reach this point.
19546 assert(N->getValueType(0) == MVT::v2f32 &&
19547 "Do not know how to legalize this Node");
19550 case ISD::INTRINSIC_W_CHAIN: {
19551 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19553 default : llvm_unreachable("Do not know how to custom type "
19554 "legalize this intrinsic operation!");
19555 case Intrinsic::x86_rdtsc:
19556 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19558 case Intrinsic::x86_rdtscp:
19559 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19561 case Intrinsic::x86_rdpmc:
19562 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19565 case ISD::READCYCLECOUNTER: {
19566 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19569 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19570 EVT T = N->getValueType(0);
19571 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19572 bool Regs64bit = T == MVT::i128;
19573 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19574 SDValue cpInL, cpInH;
19575 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19576 DAG.getConstant(0, dl, HalfT));
19577 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19578 DAG.getConstant(1, dl, HalfT));
19579 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19580 Regs64bit ? X86::RAX : X86::EAX,
19582 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19583 Regs64bit ? X86::RDX : X86::EDX,
19584 cpInH, cpInL.getValue(1));
19585 SDValue swapInL, swapInH;
19586 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19587 DAG.getConstant(0, dl, HalfT));
19588 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19589 DAG.getConstant(1, dl, HalfT));
19590 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19591 Regs64bit ? X86::RBX : X86::EBX,
19592 swapInL, cpInH.getValue(1));
19593 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19594 Regs64bit ? X86::RCX : X86::ECX,
19595 swapInH, swapInL.getValue(1));
19596 SDValue Ops[] = { swapInH.getValue(0),
19598 swapInH.getValue(1) };
19599 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19600 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19601 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19602 X86ISD::LCMPXCHG8_DAG;
19603 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19604 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19605 Regs64bit ? X86::RAX : X86::EAX,
19606 HalfT, Result.getValue(1));
19607 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19608 Regs64bit ? X86::RDX : X86::EDX,
19609 HalfT, cpOutL.getValue(2));
19610 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19612 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19613 MVT::i32, cpOutH.getValue(2));
19615 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19616 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19617 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19619 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19620 Results.push_back(Success);
19621 Results.push_back(EFLAGS.getValue(1));
19624 case ISD::ATOMIC_SWAP:
19625 case ISD::ATOMIC_LOAD_ADD:
19626 case ISD::ATOMIC_LOAD_SUB:
19627 case ISD::ATOMIC_LOAD_AND:
19628 case ISD::ATOMIC_LOAD_OR:
19629 case ISD::ATOMIC_LOAD_XOR:
19630 case ISD::ATOMIC_LOAD_NAND:
19631 case ISD::ATOMIC_LOAD_MIN:
19632 case ISD::ATOMIC_LOAD_MAX:
19633 case ISD::ATOMIC_LOAD_UMIN:
19634 case ISD::ATOMIC_LOAD_UMAX:
19635 case ISD::ATOMIC_LOAD: {
19636 // Delegate to generic TypeLegalization. Situations we can really handle
19637 // should have already been dealt with by AtomicExpandPass.cpp.
19640 case ISD::BITCAST: {
19641 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19642 EVT DstVT = N->getValueType(0);
19643 EVT SrcVT = N->getOperand(0)->getValueType(0);
19645 if (SrcVT != MVT::f64 ||
19646 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19649 unsigned NumElts = DstVT.getVectorNumElements();
19650 EVT SVT = DstVT.getVectorElementType();
19651 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19652 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19653 MVT::v2f64, N->getOperand(0));
19654 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19656 if (ExperimentalVectorWideningLegalization) {
19657 // If we are legalizing vectors by widening, we already have the desired
19658 // legal vector type, just return it.
19659 Results.push_back(ToVecInt);
19663 SmallVector<SDValue, 8> Elts;
19664 for (unsigned i = 0, e = NumElts; i != e; ++i)
19665 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19666 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19668 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19673 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19674 switch ((X86ISD::NodeType)Opcode) {
19675 case X86ISD::FIRST_NUMBER: break;
19676 case X86ISD::BSF: return "X86ISD::BSF";
19677 case X86ISD::BSR: return "X86ISD::BSR";
19678 case X86ISD::SHLD: return "X86ISD::SHLD";
19679 case X86ISD::SHRD: return "X86ISD::SHRD";
19680 case X86ISD::FAND: return "X86ISD::FAND";
19681 case X86ISD::FANDN: return "X86ISD::FANDN";
19682 case X86ISD::FOR: return "X86ISD::FOR";
19683 case X86ISD::FXOR: return "X86ISD::FXOR";
19684 case X86ISD::FILD: return "X86ISD::FILD";
19685 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19686 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19687 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19688 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19689 case X86ISD::FLD: return "X86ISD::FLD";
19690 case X86ISD::FST: return "X86ISD::FST";
19691 case X86ISD::CALL: return "X86ISD::CALL";
19692 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19693 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19694 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19695 case X86ISD::BT: return "X86ISD::BT";
19696 case X86ISD::CMP: return "X86ISD::CMP";
19697 case X86ISD::COMI: return "X86ISD::COMI";
19698 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19699 case X86ISD::CMPM: return "X86ISD::CMPM";
19700 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19701 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19702 case X86ISD::SETCC: return "X86ISD::SETCC";
19703 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19704 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19705 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19706 case X86ISD::CMOV: return "X86ISD::CMOV";
19707 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19708 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19709 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19710 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19711 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19712 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19713 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19714 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19715 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19716 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19717 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19718 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19719 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19720 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19721 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19722 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19723 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19724 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19725 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19726 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19727 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19728 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19729 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19730 case X86ISD::HADD: return "X86ISD::HADD";
19731 case X86ISD::HSUB: return "X86ISD::HSUB";
19732 case X86ISD::FHADD: return "X86ISD::FHADD";
19733 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19734 case X86ISD::ABS: return "X86ISD::ABS";
19735 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19736 case X86ISD::FMAX: return "X86ISD::FMAX";
19737 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19738 case X86ISD::FMIN: return "X86ISD::FMIN";
19739 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19740 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19741 case X86ISD::FMINC: return "X86ISD::FMINC";
19742 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19743 case X86ISD::FRCP: return "X86ISD::FRCP";
19744 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19745 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19746 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19747 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19748 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19749 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19750 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19751 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19752 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19753 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19754 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19755 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19756 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19757 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19758 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19759 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19760 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19761 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19762 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19763 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19764 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19765 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19766 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19767 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19768 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19769 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19770 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19771 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19772 case X86ISD::VSHL: return "X86ISD::VSHL";
19773 case X86ISD::VSRL: return "X86ISD::VSRL";
19774 case X86ISD::VSRA: return "X86ISD::VSRA";
19775 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19776 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19777 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19778 case X86ISD::CMPP: return "X86ISD::CMPP";
19779 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19780 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19781 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19782 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19783 case X86ISD::ADD: return "X86ISD::ADD";
19784 case X86ISD::SUB: return "X86ISD::SUB";
19785 case X86ISD::ADC: return "X86ISD::ADC";
19786 case X86ISD::SBB: return "X86ISD::SBB";
19787 case X86ISD::SMUL: return "X86ISD::SMUL";
19788 case X86ISD::UMUL: return "X86ISD::UMUL";
19789 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19790 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19791 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19792 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19793 case X86ISD::INC: return "X86ISD::INC";
19794 case X86ISD::DEC: return "X86ISD::DEC";
19795 case X86ISD::OR: return "X86ISD::OR";
19796 case X86ISD::XOR: return "X86ISD::XOR";
19797 case X86ISD::AND: return "X86ISD::AND";
19798 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19799 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19800 case X86ISD::PTEST: return "X86ISD::PTEST";
19801 case X86ISD::TESTP: return "X86ISD::TESTP";
19802 case X86ISD::TESTM: return "X86ISD::TESTM";
19803 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19804 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19805 case X86ISD::KTEST: return "X86ISD::KTEST";
19806 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19807 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19808 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19809 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19810 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19811 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19812 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19813 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19814 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19815 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19816 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19817 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19818 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19819 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19820 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19821 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19822 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19823 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19824 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19825 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19826 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19827 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19828 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19829 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19830 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19831 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19832 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19833 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19834 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19835 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19836 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19837 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19838 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19839 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19840 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19841 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19842 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19843 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19844 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19845 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19846 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19847 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19848 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19849 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19850 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19851 case X86ISD::SAHF: return "X86ISD::SAHF";
19852 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19853 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19854 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19855 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19856 case X86ISD::VPSHA: return "X86ISD::VPSHA";
19857 case X86ISD::VPSHL: return "X86ISD::VPSHL";
19858 case X86ISD::FMADD: return "X86ISD::FMADD";
19859 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19860 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19861 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19862 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19863 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19864 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19865 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19866 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19867 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19868 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19869 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19870 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19871 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19872 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19873 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19874 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19875 case X86ISD::XTEST: return "X86ISD::XTEST";
19876 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19877 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19878 case X86ISD::SELECT: return "X86ISD::SELECT";
19879 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19880 case X86ISD::RCP28: return "X86ISD::RCP28";
19881 case X86ISD::EXP2: return "X86ISD::EXP2";
19882 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19883 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19884 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19885 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19886 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19887 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19888 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19889 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19890 case X86ISD::ADDS: return "X86ISD::ADDS";
19891 case X86ISD::SUBS: return "X86ISD::SUBS";
19892 case X86ISD::AVG: return "X86ISD::AVG";
19893 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19894 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19895 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19896 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19897 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19898 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
19903 // isLegalAddressingMode - Return true if the addressing mode represented
19904 // by AM is legal for this target, for a load/store of the specified type.
19905 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19906 const AddrMode &AM, Type *Ty,
19907 unsigned AS) const {
19908 // X86 supports extremely general addressing modes.
19909 CodeModel::Model M = getTargetMachine().getCodeModel();
19910 Reloc::Model R = getTargetMachine().getRelocationModel();
19912 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19913 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19918 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19920 // If a reference to this global requires an extra load, we can't fold it.
19921 if (isGlobalStubReference(GVFlags))
19924 // If BaseGV requires a register for the PIC base, we cannot also have a
19925 // BaseReg specified.
19926 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19929 // If lower 4G is not available, then we must use rip-relative addressing.
19930 if ((M != CodeModel::Small || R != Reloc::Static) &&
19931 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19935 switch (AM.Scale) {
19941 // These scales always work.
19946 // These scales are formed with basereg+scalereg. Only accept if there is
19951 default: // Other stuff never works.
19958 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19959 unsigned Bits = Ty->getScalarSizeInBits();
19961 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19962 // particularly cheaper than those without.
19966 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19967 // variable shifts just as cheap as scalar ones.
19968 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19971 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19972 // fully general vector.
19976 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19977 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19979 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19980 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19981 return NumBits1 > NumBits2;
19984 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19985 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19988 if (!isTypeLegal(EVT::getEVT(Ty1)))
19991 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19993 // Assuming the caller doesn't have a zeroext or signext return parameter,
19994 // truncation all the way down to i1 is valid.
19998 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19999 return isInt<32>(Imm);
20002 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20003 // Can also use sub to handle negated immediates.
20004 return isInt<32>(Imm);
20007 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20008 if (!VT1.isInteger() || !VT2.isInteger())
20010 unsigned NumBits1 = VT1.getSizeInBits();
20011 unsigned NumBits2 = VT2.getSizeInBits();
20012 return NumBits1 > NumBits2;
20015 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20016 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20017 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20020 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20021 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20022 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20025 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20026 EVT VT1 = Val.getValueType();
20027 if (isZExtFree(VT1, VT2))
20030 if (Val.getOpcode() != ISD::LOAD)
20033 if (!VT1.isSimple() || !VT1.isInteger() ||
20034 !VT2.isSimple() || !VT2.isInteger())
20037 switch (VT1.getSimpleVT().SimpleTy) {
20042 // X86 has 8, 16, and 32-bit zero-extending loads.
20049 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20052 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20053 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20056 VT = VT.getScalarType();
20058 if (!VT.isSimple())
20061 switch (VT.getSimpleVT().SimpleTy) {
20072 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20073 // i16 instructions are longer (0x66 prefix) and potentially slower.
20074 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20077 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20078 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20079 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20080 /// are assumed to be legal.
20082 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20084 if (!VT.isSimple())
20087 // Not for i1 vectors
20088 if (VT.getScalarType() == MVT::i1)
20091 // Very little shuffling can be done for 64-bit vectors right now.
20092 if (VT.getSizeInBits() == 64)
20095 // We only care that the types being shuffled are legal. The lowering can
20096 // handle any possible shuffle mask that results.
20097 return isTypeLegal(VT.getSimpleVT());
20101 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20103 // Just delegate to the generic legality, clear masks aren't special.
20104 return isShuffleMaskLegal(Mask, VT);
20107 //===----------------------------------------------------------------------===//
20108 // X86 Scheduler Hooks
20109 //===----------------------------------------------------------------------===//
20111 /// Utility function to emit xbegin specifying the start of an RTM region.
20112 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20113 const TargetInstrInfo *TII) {
20114 DebugLoc DL = MI->getDebugLoc();
20116 const BasicBlock *BB = MBB->getBasicBlock();
20117 MachineFunction::iterator I = MBB;
20120 // For the v = xbegin(), we generate
20131 MachineBasicBlock *thisMBB = MBB;
20132 MachineFunction *MF = MBB->getParent();
20133 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20134 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20135 MF->insert(I, mainMBB);
20136 MF->insert(I, sinkMBB);
20138 // Transfer the remainder of BB and its successor edges to sinkMBB.
20139 sinkMBB->splice(sinkMBB->begin(), MBB,
20140 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20141 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20145 // # fallthrough to mainMBB
20146 // # abortion to sinkMBB
20147 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20148 thisMBB->addSuccessor(mainMBB);
20149 thisMBB->addSuccessor(sinkMBB);
20153 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20154 mainMBB->addSuccessor(sinkMBB);
20157 // EAX is live into the sinkMBB
20158 sinkMBB->addLiveIn(X86::EAX);
20159 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20160 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20163 MI->eraseFromParent();
20167 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20168 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20169 // in the .td file.
20170 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20171 const TargetInstrInfo *TII) {
20173 switch (MI->getOpcode()) {
20174 default: llvm_unreachable("illegal opcode!");
20175 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20176 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20177 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20178 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20179 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20180 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20181 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20182 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20185 DebugLoc dl = MI->getDebugLoc();
20186 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20188 unsigned NumArgs = MI->getNumOperands();
20189 for (unsigned i = 1; i < NumArgs; ++i) {
20190 MachineOperand &Op = MI->getOperand(i);
20191 if (!(Op.isReg() && Op.isImplicit()))
20192 MIB.addOperand(Op);
20194 if (MI->hasOneMemOperand())
20195 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20197 BuildMI(*BB, MI, dl,
20198 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20199 .addReg(X86::XMM0);
20201 MI->eraseFromParent();
20205 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20206 // defs in an instruction pattern
20207 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20208 const TargetInstrInfo *TII) {
20210 switch (MI->getOpcode()) {
20211 default: llvm_unreachable("illegal opcode!");
20212 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20213 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20214 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20215 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20216 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20217 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20218 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20219 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20222 DebugLoc dl = MI->getDebugLoc();
20223 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20225 unsigned NumArgs = MI->getNumOperands(); // remove the results
20226 for (unsigned i = 1; i < NumArgs; ++i) {
20227 MachineOperand &Op = MI->getOperand(i);
20228 if (!(Op.isReg() && Op.isImplicit()))
20229 MIB.addOperand(Op);
20231 if (MI->hasOneMemOperand())
20232 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20234 BuildMI(*BB, MI, dl,
20235 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20238 MI->eraseFromParent();
20242 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20243 const X86Subtarget *Subtarget) {
20244 DebugLoc dl = MI->getDebugLoc();
20245 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20246 // Address into RAX/EAX, other two args into ECX, EDX.
20247 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20248 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20249 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20250 for (int i = 0; i < X86::AddrNumOperands; ++i)
20251 MIB.addOperand(MI->getOperand(i));
20253 unsigned ValOps = X86::AddrNumOperands;
20254 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20255 .addReg(MI->getOperand(ValOps).getReg());
20256 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20257 .addReg(MI->getOperand(ValOps+1).getReg());
20259 // The instruction doesn't actually take any operands though.
20260 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20262 MI->eraseFromParent(); // The pseudo is gone now.
20266 MachineBasicBlock *
20267 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20268 MachineBasicBlock *MBB) const {
20269 // Emit va_arg instruction on X86-64.
20271 // Operands to this pseudo-instruction:
20272 // 0 ) Output : destination address (reg)
20273 // 1-5) Input : va_list address (addr, i64mem)
20274 // 6 ) ArgSize : Size (in bytes) of vararg type
20275 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20276 // 8 ) Align : Alignment of type
20277 // 9 ) EFLAGS (implicit-def)
20279 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20280 static_assert(X86::AddrNumOperands == 5,
20281 "VAARG_64 assumes 5 address operands");
20283 unsigned DestReg = MI->getOperand(0).getReg();
20284 MachineOperand &Base = MI->getOperand(1);
20285 MachineOperand &Scale = MI->getOperand(2);
20286 MachineOperand &Index = MI->getOperand(3);
20287 MachineOperand &Disp = MI->getOperand(4);
20288 MachineOperand &Segment = MI->getOperand(5);
20289 unsigned ArgSize = MI->getOperand(6).getImm();
20290 unsigned ArgMode = MI->getOperand(7).getImm();
20291 unsigned Align = MI->getOperand(8).getImm();
20293 // Memory Reference
20294 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20295 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20296 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20298 // Machine Information
20299 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20300 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20301 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20302 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20303 DebugLoc DL = MI->getDebugLoc();
20305 // struct va_list {
20308 // i64 overflow_area (address)
20309 // i64 reg_save_area (address)
20311 // sizeof(va_list) = 24
20312 // alignment(va_list) = 8
20314 unsigned TotalNumIntRegs = 6;
20315 unsigned TotalNumXMMRegs = 8;
20316 bool UseGPOffset = (ArgMode == 1);
20317 bool UseFPOffset = (ArgMode == 2);
20318 unsigned MaxOffset = TotalNumIntRegs * 8 +
20319 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20321 /* Align ArgSize to a multiple of 8 */
20322 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20323 bool NeedsAlign = (Align > 8);
20325 MachineBasicBlock *thisMBB = MBB;
20326 MachineBasicBlock *overflowMBB;
20327 MachineBasicBlock *offsetMBB;
20328 MachineBasicBlock *endMBB;
20330 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20331 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20332 unsigned OffsetReg = 0;
20334 if (!UseGPOffset && !UseFPOffset) {
20335 // If we only pull from the overflow region, we don't create a branch.
20336 // We don't need to alter control flow.
20337 OffsetDestReg = 0; // unused
20338 OverflowDestReg = DestReg;
20340 offsetMBB = nullptr;
20341 overflowMBB = thisMBB;
20344 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20345 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20346 // If not, pull from overflow_area. (branch to overflowMBB)
20351 // offsetMBB overflowMBB
20356 // Registers for the PHI in endMBB
20357 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20358 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20360 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20361 MachineFunction *MF = MBB->getParent();
20362 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20363 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20364 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20366 MachineFunction::iterator MBBIter = MBB;
20369 // Insert the new basic blocks
20370 MF->insert(MBBIter, offsetMBB);
20371 MF->insert(MBBIter, overflowMBB);
20372 MF->insert(MBBIter, endMBB);
20374 // Transfer the remainder of MBB and its successor edges to endMBB.
20375 endMBB->splice(endMBB->begin(), thisMBB,
20376 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20377 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20379 // Make offsetMBB and overflowMBB successors of thisMBB
20380 thisMBB->addSuccessor(offsetMBB);
20381 thisMBB->addSuccessor(overflowMBB);
20383 // endMBB is a successor of both offsetMBB and overflowMBB
20384 offsetMBB->addSuccessor(endMBB);
20385 overflowMBB->addSuccessor(endMBB);
20387 // Load the offset value into a register
20388 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20389 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20393 .addDisp(Disp, UseFPOffset ? 4 : 0)
20394 .addOperand(Segment)
20395 .setMemRefs(MMOBegin, MMOEnd);
20397 // Check if there is enough room left to pull this argument.
20398 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20400 .addImm(MaxOffset + 8 - ArgSizeA8);
20402 // Branch to "overflowMBB" if offset >= max
20403 // Fall through to "offsetMBB" otherwise
20404 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20405 .addMBB(overflowMBB);
20408 // In offsetMBB, emit code to use the reg_save_area.
20410 assert(OffsetReg != 0);
20412 // Read the reg_save_area address.
20413 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20414 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20419 .addOperand(Segment)
20420 .setMemRefs(MMOBegin, MMOEnd);
20422 // Zero-extend the offset
20423 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20424 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20427 .addImm(X86::sub_32bit);
20429 // Add the offset to the reg_save_area to get the final address.
20430 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20431 .addReg(OffsetReg64)
20432 .addReg(RegSaveReg);
20434 // Compute the offset for the next argument
20435 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20436 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20438 .addImm(UseFPOffset ? 16 : 8);
20440 // Store it back into the va_list.
20441 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20445 .addDisp(Disp, UseFPOffset ? 4 : 0)
20446 .addOperand(Segment)
20447 .addReg(NextOffsetReg)
20448 .setMemRefs(MMOBegin, MMOEnd);
20451 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20456 // Emit code to use overflow area
20459 // Load the overflow_area address into a register.
20460 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20461 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20466 .addOperand(Segment)
20467 .setMemRefs(MMOBegin, MMOEnd);
20469 // If we need to align it, do so. Otherwise, just copy the address
20470 // to OverflowDestReg.
20472 // Align the overflow address
20473 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20474 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20476 // aligned_addr = (addr + (align-1)) & ~(align-1)
20477 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20478 .addReg(OverflowAddrReg)
20481 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20483 .addImm(~(uint64_t)(Align-1));
20485 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20486 .addReg(OverflowAddrReg);
20489 // Compute the next overflow address after this argument.
20490 // (the overflow address should be kept 8-byte aligned)
20491 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20492 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20493 .addReg(OverflowDestReg)
20494 .addImm(ArgSizeA8);
20496 // Store the new overflow address.
20497 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20502 .addOperand(Segment)
20503 .addReg(NextAddrReg)
20504 .setMemRefs(MMOBegin, MMOEnd);
20506 // If we branched, emit the PHI to the front of endMBB.
20508 BuildMI(*endMBB, endMBB->begin(), DL,
20509 TII->get(X86::PHI), DestReg)
20510 .addReg(OffsetDestReg).addMBB(offsetMBB)
20511 .addReg(OverflowDestReg).addMBB(overflowMBB);
20514 // Erase the pseudo instruction
20515 MI->eraseFromParent();
20520 MachineBasicBlock *
20521 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20523 MachineBasicBlock *MBB) const {
20524 // Emit code to save XMM registers to the stack. The ABI says that the
20525 // number of registers to save is given in %al, so it's theoretically
20526 // possible to do an indirect jump trick to avoid saving all of them,
20527 // however this code takes a simpler approach and just executes all
20528 // of the stores if %al is non-zero. It's less code, and it's probably
20529 // easier on the hardware branch predictor, and stores aren't all that
20530 // expensive anyway.
20532 // Create the new basic blocks. One block contains all the XMM stores,
20533 // and one block is the final destination regardless of whether any
20534 // stores were performed.
20535 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20536 MachineFunction *F = MBB->getParent();
20537 MachineFunction::iterator MBBIter = MBB;
20539 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20540 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20541 F->insert(MBBIter, XMMSaveMBB);
20542 F->insert(MBBIter, EndMBB);
20544 // Transfer the remainder of MBB and its successor edges to EndMBB.
20545 EndMBB->splice(EndMBB->begin(), MBB,
20546 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20547 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20549 // The original block will now fall through to the XMM save block.
20550 MBB->addSuccessor(XMMSaveMBB);
20551 // The XMMSaveMBB will fall through to the end block.
20552 XMMSaveMBB->addSuccessor(EndMBB);
20554 // Now add the instructions.
20555 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20556 DebugLoc DL = MI->getDebugLoc();
20558 unsigned CountReg = MI->getOperand(0).getReg();
20559 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20560 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20562 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20563 // If %al is 0, branch around the XMM save block.
20564 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20565 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20566 MBB->addSuccessor(EndMBB);
20569 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20570 // that was just emitted, but clearly shouldn't be "saved".
20571 assert((MI->getNumOperands() <= 3 ||
20572 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20573 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20574 && "Expected last argument to be EFLAGS");
20575 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20576 // In the XMM save block, save all the XMM argument registers.
20577 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20578 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20579 MachineMemOperand *MMO = F->getMachineMemOperand(
20580 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20581 MachineMemOperand::MOStore,
20582 /*Size=*/16, /*Align=*/16);
20583 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20584 .addFrameIndex(RegSaveFrameIndex)
20585 .addImm(/*Scale=*/1)
20586 .addReg(/*IndexReg=*/0)
20587 .addImm(/*Disp=*/Offset)
20588 .addReg(/*Segment=*/0)
20589 .addReg(MI->getOperand(i).getReg())
20590 .addMemOperand(MMO);
20593 MI->eraseFromParent(); // The pseudo instruction is gone now.
20598 // The EFLAGS operand of SelectItr might be missing a kill marker
20599 // because there were multiple uses of EFLAGS, and ISel didn't know
20600 // which to mark. Figure out whether SelectItr should have had a
20601 // kill marker, and set it if it should. Returns the correct kill
20603 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20604 MachineBasicBlock* BB,
20605 const TargetRegisterInfo* TRI) {
20606 // Scan forward through BB for a use/def of EFLAGS.
20607 MachineBasicBlock::iterator miI(std::next(SelectItr));
20608 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20609 const MachineInstr& mi = *miI;
20610 if (mi.readsRegister(X86::EFLAGS))
20612 if (mi.definesRegister(X86::EFLAGS))
20613 break; // Should have kill-flag - update below.
20616 // If we hit the end of the block, check whether EFLAGS is live into a
20618 if (miI == BB->end()) {
20619 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20620 sEnd = BB->succ_end();
20621 sItr != sEnd; ++sItr) {
20622 MachineBasicBlock* succ = *sItr;
20623 if (succ->isLiveIn(X86::EFLAGS))
20628 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20629 // out. SelectMI should have a kill flag on EFLAGS.
20630 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20634 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20635 // together with other CMOV pseudo-opcodes into a single basic-block with
20636 // conditional jump around it.
20637 static bool isCMOVPseudo(MachineInstr *MI) {
20638 switch (MI->getOpcode()) {
20639 case X86::CMOV_FR32:
20640 case X86::CMOV_FR64:
20641 case X86::CMOV_GR8:
20642 case X86::CMOV_GR16:
20643 case X86::CMOV_GR32:
20644 case X86::CMOV_RFP32:
20645 case X86::CMOV_RFP64:
20646 case X86::CMOV_RFP80:
20647 case X86::CMOV_V2F64:
20648 case X86::CMOV_V2I64:
20649 case X86::CMOV_V4F32:
20650 case X86::CMOV_V4F64:
20651 case X86::CMOV_V4I64:
20652 case X86::CMOV_V16F32:
20653 case X86::CMOV_V8F32:
20654 case X86::CMOV_V8F64:
20655 case X86::CMOV_V8I64:
20656 case X86::CMOV_V8I1:
20657 case X86::CMOV_V16I1:
20658 case X86::CMOV_V32I1:
20659 case X86::CMOV_V64I1:
20667 MachineBasicBlock *
20668 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20669 MachineBasicBlock *BB) const {
20670 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20671 DebugLoc DL = MI->getDebugLoc();
20673 // To "insert" a SELECT_CC instruction, we actually have to insert the
20674 // diamond control-flow pattern. The incoming instruction knows the
20675 // destination vreg to set, the condition code register to branch on, the
20676 // true/false values to select between, and a branch opcode to use.
20677 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20678 MachineFunction::iterator It = BB;
20684 // cmpTY ccX, r1, r2
20686 // fallthrough --> copy0MBB
20687 MachineBasicBlock *thisMBB = BB;
20688 MachineFunction *F = BB->getParent();
20690 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20691 // as described above, by inserting a BB, and then making a PHI at the join
20692 // point to select the true and false operands of the CMOV in the PHI.
20694 // The code also handles two different cases of multiple CMOV opcodes
20698 // In this case, there are multiple CMOVs in a row, all which are based on
20699 // the same condition setting (or the exact opposite condition setting).
20700 // In this case we can lower all the CMOVs using a single inserted BB, and
20701 // then make a number of PHIs at the join point to model the CMOVs. The only
20702 // trickiness here, is that in a case like:
20704 // t2 = CMOV cond1 t1, f1
20705 // t3 = CMOV cond1 t2, f2
20707 // when rewriting this into PHIs, we have to perform some renaming on the
20708 // temps since you cannot have a PHI operand refer to a PHI result earlier
20709 // in the same block. The "simple" but wrong lowering would be:
20711 // t2 = PHI t1(BB1), f1(BB2)
20712 // t3 = PHI t2(BB1), f2(BB2)
20714 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20715 // renaming is to note that on the path through BB1, t2 is really just a
20716 // copy of t1, and do that renaming, properly generating:
20718 // t2 = PHI t1(BB1), f1(BB2)
20719 // t3 = PHI t1(BB1), f2(BB2)
20721 // Case 2, we lower cascaded CMOVs such as
20723 // (CMOV (CMOV F, T, cc1), T, cc2)
20725 // to two successives branches. For that, we look for another CMOV as the
20726 // following instruction.
20728 // Without this, we would add a PHI between the two jumps, which ends up
20729 // creating a few copies all around. For instance, for
20731 // (sitofp (zext (fcmp une)))
20733 // we would generate:
20735 // ucomiss %xmm1, %xmm0
20736 // movss <1.0f>, %xmm0
20737 // movaps %xmm0, %xmm1
20739 // xorps %xmm1, %xmm1
20742 // movaps %xmm1, %xmm0
20746 // because this custom-inserter would have generated:
20758 // A: X = ...; Y = ...
20760 // C: Z = PHI [X, A], [Y, B]
20762 // E: PHI [X, C], [Z, D]
20764 // If we lower both CMOVs in a single step, we can instead generate:
20776 // A: X = ...; Y = ...
20778 // E: PHI [X, A], [X, C], [Y, D]
20780 // Which, in our sitofp/fcmp example, gives us something like:
20782 // ucomiss %xmm1, %xmm0
20783 // movss <1.0f>, %xmm0
20786 // xorps %xmm0, %xmm0
20790 MachineInstr *CascadedCMOV = nullptr;
20791 MachineInstr *LastCMOV = MI;
20792 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20793 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20794 MachineBasicBlock::iterator NextMIIt =
20795 std::next(MachineBasicBlock::iterator(MI));
20797 // Check for case 1, where there are multiple CMOVs with the same condition
20798 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20799 // number of jumps the most.
20801 if (isCMOVPseudo(MI)) {
20802 // See if we have a string of CMOVS with the same condition.
20803 while (NextMIIt != BB->end() &&
20804 isCMOVPseudo(NextMIIt) &&
20805 (NextMIIt->getOperand(3).getImm() == CC ||
20806 NextMIIt->getOperand(3).getImm() == OppCC)) {
20807 LastCMOV = &*NextMIIt;
20812 // This checks for case 2, but only do this if we didn't already find
20813 // case 1, as indicated by LastCMOV == MI.
20814 if (LastCMOV == MI &&
20815 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20816 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20817 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20818 CascadedCMOV = &*NextMIIt;
20821 MachineBasicBlock *jcc1MBB = nullptr;
20823 // If we have a cascaded CMOV, we lower it to two successive branches to
20824 // the same block. EFLAGS is used by both, so mark it as live in the second.
20825 if (CascadedCMOV) {
20826 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20827 F->insert(It, jcc1MBB);
20828 jcc1MBB->addLiveIn(X86::EFLAGS);
20831 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20832 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20833 F->insert(It, copy0MBB);
20834 F->insert(It, sinkMBB);
20836 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20837 // live into the sink and copy blocks.
20838 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20840 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20841 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20842 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20843 copy0MBB->addLiveIn(X86::EFLAGS);
20844 sinkMBB->addLiveIn(X86::EFLAGS);
20847 // Transfer the remainder of BB and its successor edges to sinkMBB.
20848 sinkMBB->splice(sinkMBB->begin(), BB,
20849 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20850 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20852 // Add the true and fallthrough blocks as its successors.
20853 if (CascadedCMOV) {
20854 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20855 BB->addSuccessor(jcc1MBB);
20857 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20858 // jump to the sinkMBB.
20859 jcc1MBB->addSuccessor(copy0MBB);
20860 jcc1MBB->addSuccessor(sinkMBB);
20862 BB->addSuccessor(copy0MBB);
20865 // The true block target of the first (or only) branch is always sinkMBB.
20866 BB->addSuccessor(sinkMBB);
20868 // Create the conditional branch instruction.
20869 unsigned Opc = X86::GetCondBranchFromCond(CC);
20870 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20872 if (CascadedCMOV) {
20873 unsigned Opc2 = X86::GetCondBranchFromCond(
20874 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20875 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20879 // %FalseValue = ...
20880 // # fallthrough to sinkMBB
20881 copy0MBB->addSuccessor(sinkMBB);
20884 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20886 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20887 MachineBasicBlock::iterator MIItEnd =
20888 std::next(MachineBasicBlock::iterator(LastCMOV));
20889 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20890 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20891 MachineInstrBuilder MIB;
20893 // As we are creating the PHIs, we have to be careful if there is more than
20894 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20895 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20896 // That also means that PHI construction must work forward from earlier to
20897 // later, and that the code must maintain a mapping from earlier PHI's
20898 // destination registers, and the registers that went into the PHI.
20900 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20901 unsigned DestReg = MIIt->getOperand(0).getReg();
20902 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20903 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20905 // If this CMOV we are generating is the opposite condition from
20906 // the jump we generated, then we have to swap the operands for the
20907 // PHI that is going to be generated.
20908 if (MIIt->getOperand(3).getImm() == OppCC)
20909 std::swap(Op1Reg, Op2Reg);
20911 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20912 Op1Reg = RegRewriteTable[Op1Reg].first;
20914 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20915 Op2Reg = RegRewriteTable[Op2Reg].second;
20917 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20918 TII->get(X86::PHI), DestReg)
20919 .addReg(Op1Reg).addMBB(copy0MBB)
20920 .addReg(Op2Reg).addMBB(thisMBB);
20922 // Add this PHI to the rewrite table.
20923 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20926 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20927 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20928 if (CascadedCMOV) {
20929 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20930 // Copy the PHI result to the register defined by the second CMOV.
20931 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20932 DL, TII->get(TargetOpcode::COPY),
20933 CascadedCMOV->getOperand(0).getReg())
20934 .addReg(MI->getOperand(0).getReg());
20935 CascadedCMOV->eraseFromParent();
20938 // Now remove the CMOV(s).
20939 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20940 (MIIt++)->eraseFromParent();
20945 MachineBasicBlock *
20946 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
20947 MachineBasicBlock *BB) const {
20948 // Combine the following atomic floating-point modification pattern:
20949 // a.store(reg OP a.load(acquire), release)
20950 // Transform them into:
20951 // OPss (%gpr), %xmm
20952 // movss %xmm, (%gpr)
20953 // Or sd equivalent for 64-bit operations.
20955 switch (MI->getOpcode()) {
20956 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
20957 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
20958 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
20960 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20961 DebugLoc DL = MI->getDebugLoc();
20962 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
20963 unsigned MSrc = MI->getOperand(0).getReg();
20964 unsigned VSrc = MI->getOperand(5).getReg();
20965 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
20966 .addReg(/*Base=*/MSrc)
20967 .addImm(/*Scale=*/1)
20968 .addReg(/*Index=*/0)
20971 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
20972 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
20974 .addReg(/*Base=*/MSrc)
20975 .addImm(/*Scale=*/1)
20976 .addReg(/*Index=*/0)
20977 .addImm(/*Disp=*/0)
20978 .addReg(/*Segment=*/0);
20979 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
20980 MI->eraseFromParent(); // The pseudo instruction is gone now.
20984 MachineBasicBlock *
20985 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20986 MachineBasicBlock *BB) const {
20987 MachineFunction *MF = BB->getParent();
20988 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20989 DebugLoc DL = MI->getDebugLoc();
20990 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20992 assert(MF->shouldSplitStack());
20994 const bool Is64Bit = Subtarget->is64Bit();
20995 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20997 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20998 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21001 // ... [Till the alloca]
21002 // If stacklet is not large enough, jump to mallocMBB
21005 // Allocate by subtracting from RSP
21006 // Jump to continueMBB
21009 // Allocate by call to runtime
21013 // [rest of original BB]
21016 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21017 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21018 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21020 MachineRegisterInfo &MRI = MF->getRegInfo();
21021 const TargetRegisterClass *AddrRegClass =
21022 getRegClassFor(getPointerTy(MF->getDataLayout()));
21024 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21025 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21026 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21027 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21028 sizeVReg = MI->getOperand(1).getReg(),
21029 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21031 MachineFunction::iterator MBBIter = BB;
21034 MF->insert(MBBIter, bumpMBB);
21035 MF->insert(MBBIter, mallocMBB);
21036 MF->insert(MBBIter, continueMBB);
21038 continueMBB->splice(continueMBB->begin(), BB,
21039 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21040 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21042 // Add code to the main basic block to check if the stack limit has been hit,
21043 // and if so, jump to mallocMBB otherwise to bumpMBB.
21044 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21045 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21046 .addReg(tmpSPVReg).addReg(sizeVReg);
21047 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21048 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21049 .addReg(SPLimitVReg);
21050 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21052 // bumpMBB simply decreases the stack pointer, since we know the current
21053 // stacklet has enough space.
21054 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21055 .addReg(SPLimitVReg);
21056 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21057 .addReg(SPLimitVReg);
21058 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21060 // Calls into a routine in libgcc to allocate more space from the heap.
21061 const uint32_t *RegMask =
21062 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21064 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21066 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21067 .addExternalSymbol("__morestack_allocate_stack_space")
21068 .addRegMask(RegMask)
21069 .addReg(X86::RDI, RegState::Implicit)
21070 .addReg(X86::RAX, RegState::ImplicitDefine);
21071 } else if (Is64Bit) {
21072 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21074 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21075 .addExternalSymbol("__morestack_allocate_stack_space")
21076 .addRegMask(RegMask)
21077 .addReg(X86::EDI, RegState::Implicit)
21078 .addReg(X86::EAX, RegState::ImplicitDefine);
21080 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21082 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21083 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21084 .addExternalSymbol("__morestack_allocate_stack_space")
21085 .addRegMask(RegMask)
21086 .addReg(X86::EAX, RegState::ImplicitDefine);
21090 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21093 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21094 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21095 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21097 // Set up the CFG correctly.
21098 BB->addSuccessor(bumpMBB);
21099 BB->addSuccessor(mallocMBB);
21100 mallocMBB->addSuccessor(continueMBB);
21101 bumpMBB->addSuccessor(continueMBB);
21103 // Take care of the PHI nodes.
21104 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21105 MI->getOperand(0).getReg())
21106 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21107 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21109 // Delete the original pseudo instruction.
21110 MI->eraseFromParent();
21113 return continueMBB;
21116 MachineBasicBlock *
21117 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21118 MachineBasicBlock *BB) const {
21119 DebugLoc DL = MI->getDebugLoc();
21121 assert(!Subtarget->isTargetMachO());
21123 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21126 MI->eraseFromParent(); // The pseudo instruction is gone now.
21130 MachineBasicBlock *
21131 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21132 MachineBasicBlock *BB) const {
21133 // This is pretty easy. We're taking the value that we received from
21134 // our load from the relocation, sticking it in either RDI (x86-64)
21135 // or EAX and doing an indirect call. The return value will then
21136 // be in the normal return register.
21137 MachineFunction *F = BB->getParent();
21138 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21139 DebugLoc DL = MI->getDebugLoc();
21141 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21142 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21144 // Get a register mask for the lowered call.
21145 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21146 // proper register mask.
21147 const uint32_t *RegMask =
21148 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21149 if (Subtarget->is64Bit()) {
21150 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21151 TII->get(X86::MOV64rm), X86::RDI)
21153 .addImm(0).addReg(0)
21154 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21155 MI->getOperand(3).getTargetFlags())
21157 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21158 addDirectMem(MIB, X86::RDI);
21159 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21160 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21161 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21162 TII->get(X86::MOV32rm), X86::EAX)
21164 .addImm(0).addReg(0)
21165 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21166 MI->getOperand(3).getTargetFlags())
21168 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21169 addDirectMem(MIB, X86::EAX);
21170 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21172 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21173 TII->get(X86::MOV32rm), X86::EAX)
21174 .addReg(TII->getGlobalBaseReg(F))
21175 .addImm(0).addReg(0)
21176 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21177 MI->getOperand(3).getTargetFlags())
21179 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21180 addDirectMem(MIB, X86::EAX);
21181 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21184 MI->eraseFromParent(); // The pseudo instruction is gone now.
21188 MachineBasicBlock *
21189 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21190 MachineBasicBlock *MBB) const {
21191 DebugLoc DL = MI->getDebugLoc();
21192 MachineFunction *MF = MBB->getParent();
21193 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21194 MachineRegisterInfo &MRI = MF->getRegInfo();
21196 const BasicBlock *BB = MBB->getBasicBlock();
21197 MachineFunction::iterator I = MBB;
21200 // Memory Reference
21201 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21202 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21205 unsigned MemOpndSlot = 0;
21207 unsigned CurOp = 0;
21209 DstReg = MI->getOperand(CurOp++).getReg();
21210 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21211 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21212 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21213 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21215 MemOpndSlot = CurOp;
21217 MVT PVT = getPointerTy(MF->getDataLayout());
21218 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21219 "Invalid Pointer Size!");
21221 // For v = setjmp(buf), we generate
21224 // buf[LabelOffset] = restoreMBB
21225 // SjLjSetup restoreMBB
21231 // v = phi(main, restore)
21234 // if base pointer being used, load it from frame
21237 MachineBasicBlock *thisMBB = MBB;
21238 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21239 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21240 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21241 MF->insert(I, mainMBB);
21242 MF->insert(I, sinkMBB);
21243 MF->push_back(restoreMBB);
21245 MachineInstrBuilder MIB;
21247 // Transfer the remainder of BB and its successor edges to sinkMBB.
21248 sinkMBB->splice(sinkMBB->begin(), MBB,
21249 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21250 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21253 unsigned PtrStoreOpc = 0;
21254 unsigned LabelReg = 0;
21255 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21256 Reloc::Model RM = MF->getTarget().getRelocationModel();
21257 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21258 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21260 // Prepare IP either in reg or imm.
21261 if (!UseImmLabel) {
21262 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21263 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21264 LabelReg = MRI.createVirtualRegister(PtrRC);
21265 if (Subtarget->is64Bit()) {
21266 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21270 .addMBB(restoreMBB)
21273 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21274 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21275 .addReg(XII->getGlobalBaseReg(MF))
21278 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21282 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21284 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21285 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21286 if (i == X86::AddrDisp)
21287 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21289 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21292 MIB.addReg(LabelReg);
21294 MIB.addMBB(restoreMBB);
21295 MIB.setMemRefs(MMOBegin, MMOEnd);
21297 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21298 .addMBB(restoreMBB);
21300 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21301 MIB.addRegMask(RegInfo->getNoPreservedMask());
21302 thisMBB->addSuccessor(mainMBB);
21303 thisMBB->addSuccessor(restoreMBB);
21307 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21308 mainMBB->addSuccessor(sinkMBB);
21311 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21312 TII->get(X86::PHI), DstReg)
21313 .addReg(mainDstReg).addMBB(mainMBB)
21314 .addReg(restoreDstReg).addMBB(restoreMBB);
21317 if (RegInfo->hasBasePointer(*MF)) {
21318 const bool Uses64BitFramePtr =
21319 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21320 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21321 X86FI->setRestoreBasePointer(MF);
21322 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21323 unsigned BasePtr = RegInfo->getBaseRegister();
21324 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21325 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21326 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21327 .setMIFlag(MachineInstr::FrameSetup);
21329 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21330 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21331 restoreMBB->addSuccessor(sinkMBB);
21333 MI->eraseFromParent();
21337 MachineBasicBlock *
21338 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21339 MachineBasicBlock *MBB) const {
21340 DebugLoc DL = MI->getDebugLoc();
21341 MachineFunction *MF = MBB->getParent();
21342 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21343 MachineRegisterInfo &MRI = MF->getRegInfo();
21345 // Memory Reference
21346 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21347 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21349 MVT PVT = getPointerTy(MF->getDataLayout());
21350 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21351 "Invalid Pointer Size!");
21353 const TargetRegisterClass *RC =
21354 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21355 unsigned Tmp = MRI.createVirtualRegister(RC);
21356 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21357 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21358 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21359 unsigned SP = RegInfo->getStackRegister();
21361 MachineInstrBuilder MIB;
21363 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21364 const int64_t SPOffset = 2 * PVT.getStoreSize();
21366 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21367 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21370 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21371 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21372 MIB.addOperand(MI->getOperand(i));
21373 MIB.setMemRefs(MMOBegin, MMOEnd);
21375 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21376 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21377 if (i == X86::AddrDisp)
21378 MIB.addDisp(MI->getOperand(i), LabelOffset);
21380 MIB.addOperand(MI->getOperand(i));
21382 MIB.setMemRefs(MMOBegin, MMOEnd);
21384 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21385 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21386 if (i == X86::AddrDisp)
21387 MIB.addDisp(MI->getOperand(i), SPOffset);
21389 MIB.addOperand(MI->getOperand(i));
21391 MIB.setMemRefs(MMOBegin, MMOEnd);
21393 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21395 MI->eraseFromParent();
21399 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21400 // accumulator loops. Writing back to the accumulator allows the coalescer
21401 // to remove extra copies in the loop.
21402 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21403 MachineBasicBlock *
21404 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21405 MachineBasicBlock *MBB) const {
21406 MachineOperand &AddendOp = MI->getOperand(3);
21408 // Bail out early if the addend isn't a register - we can't switch these.
21409 if (!AddendOp.isReg())
21412 MachineFunction &MF = *MBB->getParent();
21413 MachineRegisterInfo &MRI = MF.getRegInfo();
21415 // Check whether the addend is defined by a PHI:
21416 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21417 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21418 if (!AddendDef.isPHI())
21421 // Look for the following pattern:
21423 // %addend = phi [%entry, 0], [%loop, %result]
21425 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21429 // %addend = phi [%entry, 0], [%loop, %result]
21431 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21433 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21434 assert(AddendDef.getOperand(i).isReg());
21435 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21436 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21437 if (&PHISrcInst == MI) {
21438 // Found a matching instruction.
21439 unsigned NewFMAOpc = 0;
21440 switch (MI->getOpcode()) {
21441 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21442 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21443 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21444 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21445 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21446 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21447 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21448 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21449 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21450 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21451 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21452 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21453 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21454 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21455 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21456 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21457 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21458 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21459 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21460 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21462 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21463 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21464 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21465 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21466 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21467 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21468 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21469 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21470 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21471 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21472 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21473 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21474 default: llvm_unreachable("Unrecognized FMA variant.");
21477 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21478 MachineInstrBuilder MIB =
21479 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21480 .addOperand(MI->getOperand(0))
21481 .addOperand(MI->getOperand(3))
21482 .addOperand(MI->getOperand(2))
21483 .addOperand(MI->getOperand(1));
21484 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21485 MI->eraseFromParent();
21492 MachineBasicBlock *
21493 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21494 MachineBasicBlock *BB) const {
21495 switch (MI->getOpcode()) {
21496 default: llvm_unreachable("Unexpected instr type to insert");
21497 case X86::TAILJMPd64:
21498 case X86::TAILJMPr64:
21499 case X86::TAILJMPm64:
21500 case X86::TAILJMPd64_REX:
21501 case X86::TAILJMPr64_REX:
21502 case X86::TAILJMPm64_REX:
21503 llvm_unreachable("TAILJMP64 would not be touched here.");
21504 case X86::TCRETURNdi64:
21505 case X86::TCRETURNri64:
21506 case X86::TCRETURNmi64:
21508 case X86::WIN_ALLOCA:
21509 return EmitLoweredWinAlloca(MI, BB);
21510 case X86::SEG_ALLOCA_32:
21511 case X86::SEG_ALLOCA_64:
21512 return EmitLoweredSegAlloca(MI, BB);
21513 case X86::TLSCall_32:
21514 case X86::TLSCall_64:
21515 return EmitLoweredTLSCall(MI, BB);
21516 case X86::CMOV_FR32:
21517 case X86::CMOV_FR64:
21518 case X86::CMOV_GR8:
21519 case X86::CMOV_GR16:
21520 case X86::CMOV_GR32:
21521 case X86::CMOV_RFP32:
21522 case X86::CMOV_RFP64:
21523 case X86::CMOV_RFP80:
21524 case X86::CMOV_V2F64:
21525 case X86::CMOV_V2I64:
21526 case X86::CMOV_V4F32:
21527 case X86::CMOV_V4F64:
21528 case X86::CMOV_V4I64:
21529 case X86::CMOV_V16F32:
21530 case X86::CMOV_V8F32:
21531 case X86::CMOV_V8F64:
21532 case X86::CMOV_V8I64:
21533 case X86::CMOV_V8I1:
21534 case X86::CMOV_V16I1:
21535 case X86::CMOV_V32I1:
21536 case X86::CMOV_V64I1:
21537 return EmitLoweredSelect(MI, BB);
21539 case X86::RELEASE_FADD32mr:
21540 case X86::RELEASE_FADD64mr:
21541 return EmitLoweredAtomicFP(MI, BB);
21543 case X86::FP32_TO_INT16_IN_MEM:
21544 case X86::FP32_TO_INT32_IN_MEM:
21545 case X86::FP32_TO_INT64_IN_MEM:
21546 case X86::FP64_TO_INT16_IN_MEM:
21547 case X86::FP64_TO_INT32_IN_MEM:
21548 case X86::FP64_TO_INT64_IN_MEM:
21549 case X86::FP80_TO_INT16_IN_MEM:
21550 case X86::FP80_TO_INT32_IN_MEM:
21551 case X86::FP80_TO_INT64_IN_MEM: {
21552 MachineFunction *F = BB->getParent();
21553 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21554 DebugLoc DL = MI->getDebugLoc();
21556 // Change the floating point control register to use "round towards zero"
21557 // mode when truncating to an integer value.
21558 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21559 addFrameReference(BuildMI(*BB, MI, DL,
21560 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21562 // Load the old value of the high byte of the control word...
21564 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21565 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21568 // Set the high part to be round to zero...
21569 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21572 // Reload the modified control word now...
21573 addFrameReference(BuildMI(*BB, MI, DL,
21574 TII->get(X86::FLDCW16m)), CWFrameIdx);
21576 // Restore the memory image of control word to original value
21577 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21580 // Get the X86 opcode to use.
21582 switch (MI->getOpcode()) {
21583 default: llvm_unreachable("illegal opcode!");
21584 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21585 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21586 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21587 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21588 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21589 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21590 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21591 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21592 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21596 MachineOperand &Op = MI->getOperand(0);
21598 AM.BaseType = X86AddressMode::RegBase;
21599 AM.Base.Reg = Op.getReg();
21601 AM.BaseType = X86AddressMode::FrameIndexBase;
21602 AM.Base.FrameIndex = Op.getIndex();
21604 Op = MI->getOperand(1);
21606 AM.Scale = Op.getImm();
21607 Op = MI->getOperand(2);
21609 AM.IndexReg = Op.getImm();
21610 Op = MI->getOperand(3);
21611 if (Op.isGlobal()) {
21612 AM.GV = Op.getGlobal();
21614 AM.Disp = Op.getImm();
21616 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21617 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21619 // Reload the original control word now.
21620 addFrameReference(BuildMI(*BB, MI, DL,
21621 TII->get(X86::FLDCW16m)), CWFrameIdx);
21623 MI->eraseFromParent(); // The pseudo instruction is gone now.
21626 // String/text processing lowering.
21627 case X86::PCMPISTRM128REG:
21628 case X86::VPCMPISTRM128REG:
21629 case X86::PCMPISTRM128MEM:
21630 case X86::VPCMPISTRM128MEM:
21631 case X86::PCMPESTRM128REG:
21632 case X86::VPCMPESTRM128REG:
21633 case X86::PCMPESTRM128MEM:
21634 case X86::VPCMPESTRM128MEM:
21635 assert(Subtarget->hasSSE42() &&
21636 "Target must have SSE4.2 or AVX features enabled");
21637 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21639 // String/text processing lowering.
21640 case X86::PCMPISTRIREG:
21641 case X86::VPCMPISTRIREG:
21642 case X86::PCMPISTRIMEM:
21643 case X86::VPCMPISTRIMEM:
21644 case X86::PCMPESTRIREG:
21645 case X86::VPCMPESTRIREG:
21646 case X86::PCMPESTRIMEM:
21647 case X86::VPCMPESTRIMEM:
21648 assert(Subtarget->hasSSE42() &&
21649 "Target must have SSE4.2 or AVX features enabled");
21650 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21652 // Thread synchronization.
21654 return EmitMonitor(MI, BB, Subtarget);
21658 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21660 case X86::VASTART_SAVE_XMM_REGS:
21661 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21663 case X86::VAARG_64:
21664 return EmitVAARG64WithCustomInserter(MI, BB);
21666 case X86::EH_SjLj_SetJmp32:
21667 case X86::EH_SjLj_SetJmp64:
21668 return emitEHSjLjSetJmp(MI, BB);
21670 case X86::EH_SjLj_LongJmp32:
21671 case X86::EH_SjLj_LongJmp64:
21672 return emitEHSjLjLongJmp(MI, BB);
21674 case TargetOpcode::STATEPOINT:
21675 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21676 // this point in the process. We diverge later.
21677 return emitPatchPoint(MI, BB);
21679 case TargetOpcode::STACKMAP:
21680 case TargetOpcode::PATCHPOINT:
21681 return emitPatchPoint(MI, BB);
21683 case X86::VFMADDPDr213r:
21684 case X86::VFMADDPSr213r:
21685 case X86::VFMADDSDr213r:
21686 case X86::VFMADDSSr213r:
21687 case X86::VFMSUBPDr213r:
21688 case X86::VFMSUBPSr213r:
21689 case X86::VFMSUBSDr213r:
21690 case X86::VFMSUBSSr213r:
21691 case X86::VFNMADDPDr213r:
21692 case X86::VFNMADDPSr213r:
21693 case X86::VFNMADDSDr213r:
21694 case X86::VFNMADDSSr213r:
21695 case X86::VFNMSUBPDr213r:
21696 case X86::VFNMSUBPSr213r:
21697 case X86::VFNMSUBSDr213r:
21698 case X86::VFNMSUBSSr213r:
21699 case X86::VFMADDSUBPDr213r:
21700 case X86::VFMADDSUBPSr213r:
21701 case X86::VFMSUBADDPDr213r:
21702 case X86::VFMSUBADDPSr213r:
21703 case X86::VFMADDPDr213rY:
21704 case X86::VFMADDPSr213rY:
21705 case X86::VFMSUBPDr213rY:
21706 case X86::VFMSUBPSr213rY:
21707 case X86::VFNMADDPDr213rY:
21708 case X86::VFNMADDPSr213rY:
21709 case X86::VFNMSUBPDr213rY:
21710 case X86::VFNMSUBPSr213rY:
21711 case X86::VFMADDSUBPDr213rY:
21712 case X86::VFMADDSUBPSr213rY:
21713 case X86::VFMSUBADDPDr213rY:
21714 case X86::VFMSUBADDPSr213rY:
21715 return emitFMA3Instr(MI, BB);
21719 //===----------------------------------------------------------------------===//
21720 // X86 Optimization Hooks
21721 //===----------------------------------------------------------------------===//
21723 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21726 const SelectionDAG &DAG,
21727 unsigned Depth) const {
21728 unsigned BitWidth = KnownZero.getBitWidth();
21729 unsigned Opc = Op.getOpcode();
21730 assert((Opc >= ISD::BUILTIN_OP_END ||
21731 Opc == ISD::INTRINSIC_WO_CHAIN ||
21732 Opc == ISD::INTRINSIC_W_CHAIN ||
21733 Opc == ISD::INTRINSIC_VOID) &&
21734 "Should use MaskedValueIsZero if you don't know whether Op"
21735 " is a target node!");
21737 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21751 // These nodes' second result is a boolean.
21752 if (Op.getResNo() == 0)
21755 case X86ISD::SETCC:
21756 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21758 case ISD::INTRINSIC_WO_CHAIN: {
21759 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21760 unsigned NumLoBits = 0;
21763 case Intrinsic::x86_sse_movmsk_ps:
21764 case Intrinsic::x86_avx_movmsk_ps_256:
21765 case Intrinsic::x86_sse2_movmsk_pd:
21766 case Intrinsic::x86_avx_movmsk_pd_256:
21767 case Intrinsic::x86_mmx_pmovmskb:
21768 case Intrinsic::x86_sse2_pmovmskb_128:
21769 case Intrinsic::x86_avx2_pmovmskb: {
21770 // High bits of movmskp{s|d}, pmovmskb are known zero.
21772 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21773 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21774 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21775 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21776 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21777 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21778 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21779 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21781 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21790 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21792 const SelectionDAG &,
21793 unsigned Depth) const {
21794 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21795 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21796 return Op.getValueType().getScalarType().getSizeInBits();
21802 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21803 /// node is a GlobalAddress + offset.
21804 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21805 const GlobalValue* &GA,
21806 int64_t &Offset) const {
21807 if (N->getOpcode() == X86ISD::Wrapper) {
21808 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21809 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21810 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21814 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21817 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21818 /// same as extracting the high 128-bit part of 256-bit vector and then
21819 /// inserting the result into the low part of a new 256-bit vector
21820 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21821 EVT VT = SVOp->getValueType(0);
21822 unsigned NumElems = VT.getVectorNumElements();
21824 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21825 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21826 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21827 SVOp->getMaskElt(j) >= 0)
21833 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21834 /// same as extracting the low 128-bit part of 256-bit vector and then
21835 /// inserting the result into the high part of a new 256-bit vector
21836 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21837 EVT VT = SVOp->getValueType(0);
21838 unsigned NumElems = VT.getVectorNumElements();
21840 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21841 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21842 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21843 SVOp->getMaskElt(j) >= 0)
21849 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21850 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21851 TargetLowering::DAGCombinerInfo &DCI,
21852 const X86Subtarget* Subtarget) {
21854 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21855 SDValue V1 = SVOp->getOperand(0);
21856 SDValue V2 = SVOp->getOperand(1);
21857 EVT VT = SVOp->getValueType(0);
21858 unsigned NumElems = VT.getVectorNumElements();
21860 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21861 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21865 // V UNDEF BUILD_VECTOR UNDEF
21867 // CONCAT_VECTOR CONCAT_VECTOR
21870 // RESULT: V + zero extended
21872 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21873 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21874 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21877 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21880 // To match the shuffle mask, the first half of the mask should
21881 // be exactly the first vector, and all the rest a splat with the
21882 // first element of the second one.
21883 for (unsigned i = 0; i != NumElems/2; ++i)
21884 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21885 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21888 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21889 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21890 if (Ld->hasNUsesOfValue(1, 0)) {
21891 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21892 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21894 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21896 Ld->getPointerInfo(),
21897 Ld->getAlignment(),
21898 false/*isVolatile*/, true/*ReadMem*/,
21899 false/*WriteMem*/);
21901 // Make sure the newly-created LOAD is in the same position as Ld in
21902 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21903 // and update uses of Ld's output chain to use the TokenFactor.
21904 if (Ld->hasAnyUseOfValue(1)) {
21905 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21906 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21907 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21908 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21909 SDValue(ResNode.getNode(), 1));
21912 return DAG.getBitcast(VT, ResNode);
21916 // Emit a zeroed vector and insert the desired subvector on its
21918 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21919 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21920 return DCI.CombineTo(N, InsV);
21923 //===--------------------------------------------------------------------===//
21924 // Combine some shuffles into subvector extracts and inserts:
21927 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21928 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21929 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21930 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21931 return DCI.CombineTo(N, InsV);
21934 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21935 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21936 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21937 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21938 return DCI.CombineTo(N, InsV);
21944 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21947 /// This is the leaf of the recursive combinine below. When we have found some
21948 /// chain of single-use x86 shuffle instructions and accumulated the combined
21949 /// shuffle mask represented by them, this will try to pattern match that mask
21950 /// into either a single instruction if there is a special purpose instruction
21951 /// for this operation, or into a PSHUFB instruction which is a fully general
21952 /// instruction but should only be used to replace chains over a certain depth.
21953 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21954 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21955 TargetLowering::DAGCombinerInfo &DCI,
21956 const X86Subtarget *Subtarget) {
21957 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21959 // Find the operand that enters the chain. Note that multiple uses are OK
21960 // here, we're not going to remove the operand we find.
21961 SDValue Input = Op.getOperand(0);
21962 while (Input.getOpcode() == ISD::BITCAST)
21963 Input = Input.getOperand(0);
21965 MVT VT = Input.getSimpleValueType();
21966 MVT RootVT = Root.getSimpleValueType();
21969 // Just remove no-op shuffle masks.
21970 if (Mask.size() == 1) {
21971 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
21976 // Use the float domain if the operand type is a floating point type.
21977 bool FloatDomain = VT.isFloatingPoint();
21979 // For floating point shuffles, we don't have free copies in the shuffle
21980 // instructions or the ability to load as part of the instruction, so
21981 // canonicalize their shuffles to UNPCK or MOV variants.
21983 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21984 // vectors because it can have a load folded into it that UNPCK cannot. This
21985 // doesn't preclude something switching to the shorter encoding post-RA.
21987 // FIXME: Should teach these routines about AVX vector widths.
21988 if (FloatDomain && VT.getSizeInBits() == 128) {
21989 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
21990 bool Lo = Mask.equals({0, 0});
21993 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21994 // is no slower than UNPCKLPD but has the option to fold the input operand
21995 // into even an unaligned memory load.
21996 if (Lo && Subtarget->hasSSE3()) {
21997 Shuffle = X86ISD::MOVDDUP;
21998 ShuffleVT = MVT::v2f64;
22000 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22001 // than the UNPCK variants.
22002 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22003 ShuffleVT = MVT::v4f32;
22005 if (Depth == 1 && Root->getOpcode() == Shuffle)
22006 return false; // Nothing to do!
22007 Op = DAG.getBitcast(ShuffleVT, Input);
22008 DCI.AddToWorklist(Op.getNode());
22009 if (Shuffle == X86ISD::MOVDDUP)
22010 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22012 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22013 DCI.AddToWorklist(Op.getNode());
22014 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22018 if (Subtarget->hasSSE3() &&
22019 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22020 bool Lo = Mask.equals({0, 0, 2, 2});
22021 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22022 MVT ShuffleVT = MVT::v4f32;
22023 if (Depth == 1 && Root->getOpcode() == Shuffle)
22024 return false; // Nothing to do!
22025 Op = DAG.getBitcast(ShuffleVT, Input);
22026 DCI.AddToWorklist(Op.getNode());
22027 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22028 DCI.AddToWorklist(Op.getNode());
22029 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22033 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22034 bool Lo = Mask.equals({0, 0, 1, 1});
22035 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22036 MVT ShuffleVT = MVT::v4f32;
22037 if (Depth == 1 && Root->getOpcode() == Shuffle)
22038 return false; // Nothing to do!
22039 Op = DAG.getBitcast(ShuffleVT, Input);
22040 DCI.AddToWorklist(Op.getNode());
22041 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22042 DCI.AddToWorklist(Op.getNode());
22043 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22049 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22050 // variants as none of these have single-instruction variants that are
22051 // superior to the UNPCK formulation.
22052 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22053 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22054 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22055 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22057 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22058 bool Lo = Mask[0] == 0;
22059 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22060 if (Depth == 1 && Root->getOpcode() == Shuffle)
22061 return false; // Nothing to do!
22063 switch (Mask.size()) {
22065 ShuffleVT = MVT::v8i16;
22068 ShuffleVT = MVT::v16i8;
22071 llvm_unreachable("Impossible mask size!");
22073 Op = DAG.getBitcast(ShuffleVT, Input);
22074 DCI.AddToWorklist(Op.getNode());
22075 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22076 DCI.AddToWorklist(Op.getNode());
22077 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22082 // Don't try to re-form single instruction chains under any circumstances now
22083 // that we've done encoding canonicalization for them.
22087 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22088 // can replace them with a single PSHUFB instruction profitably. Intel's
22089 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22090 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22091 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22092 SmallVector<SDValue, 16> PSHUFBMask;
22093 int NumBytes = VT.getSizeInBits() / 8;
22094 int Ratio = NumBytes / Mask.size();
22095 for (int i = 0; i < NumBytes; ++i) {
22096 if (Mask[i / Ratio] == SM_SentinelUndef) {
22097 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22100 int M = Mask[i / Ratio] != SM_SentinelZero
22101 ? Ratio * Mask[i / Ratio] + i % Ratio
22103 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22105 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22106 Op = DAG.getBitcast(ByteVT, Input);
22107 DCI.AddToWorklist(Op.getNode());
22108 SDValue PSHUFBMaskOp =
22109 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22110 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22111 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22112 DCI.AddToWorklist(Op.getNode());
22113 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22118 // Failed to find any combines.
22122 /// \brief Fully generic combining of x86 shuffle instructions.
22124 /// This should be the last combine run over the x86 shuffle instructions. Once
22125 /// they have been fully optimized, this will recursively consider all chains
22126 /// of single-use shuffle instructions, build a generic model of the cumulative
22127 /// shuffle operation, and check for simpler instructions which implement this
22128 /// operation. We use this primarily for two purposes:
22130 /// 1) Collapse generic shuffles to specialized single instructions when
22131 /// equivalent. In most cases, this is just an encoding size win, but
22132 /// sometimes we will collapse multiple generic shuffles into a single
22133 /// special-purpose shuffle.
22134 /// 2) Look for sequences of shuffle instructions with 3 or more total
22135 /// instructions, and replace them with the slightly more expensive SSSE3
22136 /// PSHUFB instruction if available. We do this as the last combining step
22137 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22138 /// a suitable short sequence of other instructions. The PHUFB will either
22139 /// use a register or have to read from memory and so is slightly (but only
22140 /// slightly) more expensive than the other shuffle instructions.
22142 /// Because this is inherently a quadratic operation (for each shuffle in
22143 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22144 /// This should never be an issue in practice as the shuffle lowering doesn't
22145 /// produce sequences of more than 8 instructions.
22147 /// FIXME: We will currently miss some cases where the redundant shuffling
22148 /// would simplify under the threshold for PSHUFB formation because of
22149 /// combine-ordering. To fix this, we should do the redundant instruction
22150 /// combining in this recursive walk.
22151 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22152 ArrayRef<int> RootMask,
22153 int Depth, bool HasPSHUFB,
22155 TargetLowering::DAGCombinerInfo &DCI,
22156 const X86Subtarget *Subtarget) {
22157 // Bound the depth of our recursive combine because this is ultimately
22158 // quadratic in nature.
22162 // Directly rip through bitcasts to find the underlying operand.
22163 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22164 Op = Op.getOperand(0);
22166 MVT VT = Op.getSimpleValueType();
22167 if (!VT.isVector())
22168 return false; // Bail if we hit a non-vector.
22170 assert(Root.getSimpleValueType().isVector() &&
22171 "Shuffles operate on vector types!");
22172 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22173 "Can only combine shuffles of the same vector register size.");
22175 if (!isTargetShuffle(Op.getOpcode()))
22177 SmallVector<int, 16> OpMask;
22179 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22180 // We only can combine unary shuffles which we can decode the mask for.
22181 if (!HaveMask || !IsUnary)
22184 assert(VT.getVectorNumElements() == OpMask.size() &&
22185 "Different mask size from vector size!");
22186 assert(((RootMask.size() > OpMask.size() &&
22187 RootMask.size() % OpMask.size() == 0) ||
22188 (OpMask.size() > RootMask.size() &&
22189 OpMask.size() % RootMask.size() == 0) ||
22190 OpMask.size() == RootMask.size()) &&
22191 "The smaller number of elements must divide the larger.");
22192 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22193 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22194 assert(((RootRatio == 1 && OpRatio == 1) ||
22195 (RootRatio == 1) != (OpRatio == 1)) &&
22196 "Must not have a ratio for both incoming and op masks!");
22198 SmallVector<int, 16> Mask;
22199 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22201 // Merge this shuffle operation's mask into our accumulated mask. Note that
22202 // this shuffle's mask will be the first applied to the input, followed by the
22203 // root mask to get us all the way to the root value arrangement. The reason
22204 // for this order is that we are recursing up the operation chain.
22205 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22206 int RootIdx = i / RootRatio;
22207 if (RootMask[RootIdx] < 0) {
22208 // This is a zero or undef lane, we're done.
22209 Mask.push_back(RootMask[RootIdx]);
22213 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22214 int OpIdx = RootMaskedIdx / OpRatio;
22215 if (OpMask[OpIdx] < 0) {
22216 // The incoming lanes are zero or undef, it doesn't matter which ones we
22218 Mask.push_back(OpMask[OpIdx]);
22222 // Ok, we have non-zero lanes, map them through.
22223 Mask.push_back(OpMask[OpIdx] * OpRatio +
22224 RootMaskedIdx % OpRatio);
22227 // See if we can recurse into the operand to combine more things.
22228 switch (Op.getOpcode()) {
22229 case X86ISD::PSHUFB:
22231 case X86ISD::PSHUFD:
22232 case X86ISD::PSHUFHW:
22233 case X86ISD::PSHUFLW:
22234 if (Op.getOperand(0).hasOneUse() &&
22235 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22236 HasPSHUFB, DAG, DCI, Subtarget))
22240 case X86ISD::UNPCKL:
22241 case X86ISD::UNPCKH:
22242 assert(Op.getOperand(0) == Op.getOperand(1) &&
22243 "We only combine unary shuffles!");
22244 // We can't check for single use, we have to check that this shuffle is the
22246 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22247 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22248 HasPSHUFB, DAG, DCI, Subtarget))
22253 // Minor canonicalization of the accumulated shuffle mask to make it easier
22254 // to match below. All this does is detect masks with squential pairs of
22255 // elements, and shrink them to the half-width mask. It does this in a loop
22256 // so it will reduce the size of the mask to the minimal width mask which
22257 // performs an equivalent shuffle.
22258 SmallVector<int, 16> WidenedMask;
22259 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22260 Mask = std::move(WidenedMask);
22261 WidenedMask.clear();
22264 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22268 /// \brief Get the PSHUF-style mask from PSHUF node.
22270 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22271 /// PSHUF-style masks that can be reused with such instructions.
22272 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22273 MVT VT = N.getSimpleValueType();
22274 SmallVector<int, 4> Mask;
22276 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22280 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22281 // matter. Check that the upper masks are repeats and remove them.
22282 if (VT.getSizeInBits() > 128) {
22283 int LaneElts = 128 / VT.getScalarSizeInBits();
22285 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22286 for (int j = 0; j < LaneElts; ++j)
22287 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22288 "Mask doesn't repeat in high 128-bit lanes!");
22290 Mask.resize(LaneElts);
22293 switch (N.getOpcode()) {
22294 case X86ISD::PSHUFD:
22296 case X86ISD::PSHUFLW:
22299 case X86ISD::PSHUFHW:
22300 Mask.erase(Mask.begin(), Mask.begin() + 4);
22301 for (int &M : Mask)
22305 llvm_unreachable("No valid shuffle instruction found!");
22309 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22311 /// We walk up the chain and look for a combinable shuffle, skipping over
22312 /// shuffles that we could hoist this shuffle's transformation past without
22313 /// altering anything.
22315 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22317 TargetLowering::DAGCombinerInfo &DCI) {
22318 assert(N.getOpcode() == X86ISD::PSHUFD &&
22319 "Called with something other than an x86 128-bit half shuffle!");
22322 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22323 // of the shuffles in the chain so that we can form a fresh chain to replace
22325 SmallVector<SDValue, 8> Chain;
22326 SDValue V = N.getOperand(0);
22327 for (; V.hasOneUse(); V = V.getOperand(0)) {
22328 switch (V.getOpcode()) {
22330 return SDValue(); // Nothing combined!
22333 // Skip bitcasts as we always know the type for the target specific
22337 case X86ISD::PSHUFD:
22338 // Found another dword shuffle.
22341 case X86ISD::PSHUFLW:
22342 // Check that the low words (being shuffled) are the identity in the
22343 // dword shuffle, and the high words are self-contained.
22344 if (Mask[0] != 0 || Mask[1] != 1 ||
22345 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22348 Chain.push_back(V);
22351 case X86ISD::PSHUFHW:
22352 // Check that the high words (being shuffled) are the identity in the
22353 // dword shuffle, and the low words are self-contained.
22354 if (Mask[2] != 2 || Mask[3] != 3 ||
22355 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22358 Chain.push_back(V);
22361 case X86ISD::UNPCKL:
22362 case X86ISD::UNPCKH:
22363 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22364 // shuffle into a preceding word shuffle.
22365 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22366 V.getSimpleValueType().getScalarType() != MVT::i16)
22369 // Search for a half-shuffle which we can combine with.
22370 unsigned CombineOp =
22371 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22372 if (V.getOperand(0) != V.getOperand(1) ||
22373 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22375 Chain.push_back(V);
22376 V = V.getOperand(0);
22378 switch (V.getOpcode()) {
22380 return SDValue(); // Nothing to combine.
22382 case X86ISD::PSHUFLW:
22383 case X86ISD::PSHUFHW:
22384 if (V.getOpcode() == CombineOp)
22387 Chain.push_back(V);
22391 V = V.getOperand(0);
22395 } while (V.hasOneUse());
22398 // Break out of the loop if we break out of the switch.
22402 if (!V.hasOneUse())
22403 // We fell out of the loop without finding a viable combining instruction.
22406 // Merge this node's mask and our incoming mask.
22407 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22408 for (int &M : Mask)
22410 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22411 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22413 // Rebuild the chain around this new shuffle.
22414 while (!Chain.empty()) {
22415 SDValue W = Chain.pop_back_val();
22417 if (V.getValueType() != W.getOperand(0).getValueType())
22418 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22420 switch (W.getOpcode()) {
22422 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22424 case X86ISD::UNPCKL:
22425 case X86ISD::UNPCKH:
22426 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22429 case X86ISD::PSHUFD:
22430 case X86ISD::PSHUFLW:
22431 case X86ISD::PSHUFHW:
22432 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22436 if (V.getValueType() != N.getValueType())
22437 V = DAG.getBitcast(N.getValueType(), V);
22439 // Return the new chain to replace N.
22443 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22446 /// We walk up the chain, skipping shuffles of the other half and looking
22447 /// through shuffles which switch halves trying to find a shuffle of the same
22448 /// pair of dwords.
22449 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22451 TargetLowering::DAGCombinerInfo &DCI) {
22453 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22454 "Called with something other than an x86 128-bit half shuffle!");
22456 unsigned CombineOpcode = N.getOpcode();
22458 // Walk up a single-use chain looking for a combinable shuffle.
22459 SDValue V = N.getOperand(0);
22460 for (; V.hasOneUse(); V = V.getOperand(0)) {
22461 switch (V.getOpcode()) {
22463 return false; // Nothing combined!
22466 // Skip bitcasts as we always know the type for the target specific
22470 case X86ISD::PSHUFLW:
22471 case X86ISD::PSHUFHW:
22472 if (V.getOpcode() == CombineOpcode)
22475 // Other-half shuffles are no-ops.
22478 // Break out of the loop if we break out of the switch.
22482 if (!V.hasOneUse())
22483 // We fell out of the loop without finding a viable combining instruction.
22486 // Combine away the bottom node as its shuffle will be accumulated into
22487 // a preceding shuffle.
22488 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22490 // Record the old value.
22493 // Merge this node's mask and our incoming mask (adjusted to account for all
22494 // the pshufd instructions encountered).
22495 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22496 for (int &M : Mask)
22498 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22499 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22501 // Check that the shuffles didn't cancel each other out. If not, we need to
22502 // combine to the new one.
22504 // Replace the combinable shuffle with the combined one, updating all users
22505 // so that we re-evaluate the chain here.
22506 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22511 /// \brief Try to combine x86 target specific shuffles.
22512 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22513 TargetLowering::DAGCombinerInfo &DCI,
22514 const X86Subtarget *Subtarget) {
22516 MVT VT = N.getSimpleValueType();
22517 SmallVector<int, 4> Mask;
22519 switch (N.getOpcode()) {
22520 case X86ISD::PSHUFD:
22521 case X86ISD::PSHUFLW:
22522 case X86ISD::PSHUFHW:
22523 Mask = getPSHUFShuffleMask(N);
22524 assert(Mask.size() == 4);
22530 // Nuke no-op shuffles that show up after combining.
22531 if (isNoopShuffleMask(Mask))
22532 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22534 // Look for simplifications involving one or two shuffle instructions.
22535 SDValue V = N.getOperand(0);
22536 switch (N.getOpcode()) {
22539 case X86ISD::PSHUFLW:
22540 case X86ISD::PSHUFHW:
22541 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22543 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22544 return SDValue(); // We combined away this shuffle, so we're done.
22546 // See if this reduces to a PSHUFD which is no more expensive and can
22547 // combine with more operations. Note that it has to at least flip the
22548 // dwords as otherwise it would have been removed as a no-op.
22549 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22550 int DMask[] = {0, 1, 2, 3};
22551 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22552 DMask[DOffset + 0] = DOffset + 1;
22553 DMask[DOffset + 1] = DOffset + 0;
22554 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22555 V = DAG.getBitcast(DVT, V);
22556 DCI.AddToWorklist(V.getNode());
22557 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22558 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22559 DCI.AddToWorklist(V.getNode());
22560 return DAG.getBitcast(VT, V);
22563 // Look for shuffle patterns which can be implemented as a single unpack.
22564 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22565 // only works when we have a PSHUFD followed by two half-shuffles.
22566 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22567 (V.getOpcode() == X86ISD::PSHUFLW ||
22568 V.getOpcode() == X86ISD::PSHUFHW) &&
22569 V.getOpcode() != N.getOpcode() &&
22571 SDValue D = V.getOperand(0);
22572 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22573 D = D.getOperand(0);
22574 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22575 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22576 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22577 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22578 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22580 for (int i = 0; i < 4; ++i) {
22581 WordMask[i + NOffset] = Mask[i] + NOffset;
22582 WordMask[i + VOffset] = VMask[i] + VOffset;
22584 // Map the word mask through the DWord mask.
22586 for (int i = 0; i < 8; ++i)
22587 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22588 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22589 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22590 // We can replace all three shuffles with an unpack.
22591 V = DAG.getBitcast(VT, D.getOperand(0));
22592 DCI.AddToWorklist(V.getNode());
22593 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22602 case X86ISD::PSHUFD:
22603 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22612 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22614 /// We combine this directly on the abstract vector shuffle nodes so it is
22615 /// easier to generically match. We also insert dummy vector shuffle nodes for
22616 /// the operands which explicitly discard the lanes which are unused by this
22617 /// operation to try to flow through the rest of the combiner the fact that
22618 /// they're unused.
22619 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22621 EVT VT = N->getValueType(0);
22623 // We only handle target-independent shuffles.
22624 // FIXME: It would be easy and harmless to use the target shuffle mask
22625 // extraction tool to support more.
22626 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22629 auto *SVN = cast<ShuffleVectorSDNode>(N);
22630 ArrayRef<int> Mask = SVN->getMask();
22631 SDValue V1 = N->getOperand(0);
22632 SDValue V2 = N->getOperand(1);
22634 // We require the first shuffle operand to be the SUB node, and the second to
22635 // be the ADD node.
22636 // FIXME: We should support the commuted patterns.
22637 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22640 // If there are other uses of these operations we can't fold them.
22641 if (!V1->hasOneUse() || !V2->hasOneUse())
22644 // Ensure that both operations have the same operands. Note that we can
22645 // commute the FADD operands.
22646 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22647 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22648 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22651 // We're looking for blends between FADD and FSUB nodes. We insist on these
22652 // nodes being lined up in a specific expected pattern.
22653 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22654 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22655 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22658 // Only specific types are legal at this point, assert so we notice if and
22659 // when these change.
22660 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22661 VT == MVT::v4f64) &&
22662 "Unknown vector type encountered!");
22664 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22667 /// PerformShuffleCombine - Performs several different shuffle combines.
22668 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22669 TargetLowering::DAGCombinerInfo &DCI,
22670 const X86Subtarget *Subtarget) {
22672 SDValue N0 = N->getOperand(0);
22673 SDValue N1 = N->getOperand(1);
22674 EVT VT = N->getValueType(0);
22676 // Don't create instructions with illegal types after legalize types has run.
22677 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22678 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22681 // If we have legalized the vector types, look for blends of FADD and FSUB
22682 // nodes that we can fuse into an ADDSUB node.
22683 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22684 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22687 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22688 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22689 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22690 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22692 // During Type Legalization, when promoting illegal vector types,
22693 // the backend might introduce new shuffle dag nodes and bitcasts.
22695 // This code performs the following transformation:
22696 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22697 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22699 // We do this only if both the bitcast and the BINOP dag nodes have
22700 // one use. Also, perform this transformation only if the new binary
22701 // operation is legal. This is to avoid introducing dag nodes that
22702 // potentially need to be further expanded (or custom lowered) into a
22703 // less optimal sequence of dag nodes.
22704 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22705 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22706 N0.getOpcode() == ISD::BITCAST) {
22707 SDValue BC0 = N0.getOperand(0);
22708 EVT SVT = BC0.getValueType();
22709 unsigned Opcode = BC0.getOpcode();
22710 unsigned NumElts = VT.getVectorNumElements();
22712 if (BC0.hasOneUse() && SVT.isVector() &&
22713 SVT.getVectorNumElements() * 2 == NumElts &&
22714 TLI.isOperationLegal(Opcode, VT)) {
22715 bool CanFold = false;
22727 unsigned SVTNumElts = SVT.getVectorNumElements();
22728 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22729 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22730 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22731 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22732 CanFold = SVOp->getMaskElt(i) < 0;
22735 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22736 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22737 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22738 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22743 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22744 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22745 // consecutive, non-overlapping, and in the right order.
22746 SmallVector<SDValue, 16> Elts;
22747 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22748 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22750 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22753 if (isTargetShuffle(N->getOpcode())) {
22755 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22756 if (Shuffle.getNode())
22759 // Try recursively combining arbitrary sequences of x86 shuffle
22760 // instructions into higher-order shuffles. We do this after combining
22761 // specific PSHUF instruction sequences into their minimal form so that we
22762 // can evaluate how many specialized shuffle instructions are involved in
22763 // a particular chain.
22764 SmallVector<int, 1> NonceMask; // Just a placeholder.
22765 NonceMask.push_back(0);
22766 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22767 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22769 return SDValue(); // This routine will use CombineTo to replace N.
22775 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22776 /// specific shuffle of a load can be folded into a single element load.
22777 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22778 /// shuffles have been custom lowered so we need to handle those here.
22779 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22780 TargetLowering::DAGCombinerInfo &DCI) {
22781 if (DCI.isBeforeLegalizeOps())
22784 SDValue InVec = N->getOperand(0);
22785 SDValue EltNo = N->getOperand(1);
22787 if (!isa<ConstantSDNode>(EltNo))
22790 EVT OriginalVT = InVec.getValueType();
22792 if (InVec.getOpcode() == ISD::BITCAST) {
22793 // Don't duplicate a load with other uses.
22794 if (!InVec.hasOneUse())
22796 EVT BCVT = InVec.getOperand(0).getValueType();
22797 if (!BCVT.isVector() ||
22798 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22800 InVec = InVec.getOperand(0);
22803 EVT CurrentVT = InVec.getValueType();
22805 if (!isTargetShuffle(InVec.getOpcode()))
22808 // Don't duplicate a load with other uses.
22809 if (!InVec.hasOneUse())
22812 SmallVector<int, 16> ShuffleMask;
22814 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22815 ShuffleMask, UnaryShuffle))
22818 // Select the input vector, guarding against out of range extract vector.
22819 unsigned NumElems = CurrentVT.getVectorNumElements();
22820 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22821 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22822 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22823 : InVec.getOperand(1);
22825 // If inputs to shuffle are the same for both ops, then allow 2 uses
22826 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22827 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22829 if (LdNode.getOpcode() == ISD::BITCAST) {
22830 // Don't duplicate a load with other uses.
22831 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22834 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22835 LdNode = LdNode.getOperand(0);
22838 if (!ISD::isNormalLoad(LdNode.getNode()))
22841 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22843 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22846 EVT EltVT = N->getValueType(0);
22847 // If there's a bitcast before the shuffle, check if the load type and
22848 // alignment is valid.
22849 unsigned Align = LN0->getAlignment();
22850 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22851 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22852 EltVT.getTypeForEVT(*DAG.getContext()));
22854 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22857 // All checks match so transform back to vector_shuffle so that DAG combiner
22858 // can finish the job
22861 // Create shuffle node taking into account the case that its a unary shuffle
22862 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22863 : InVec.getOperand(1);
22864 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22865 InVec.getOperand(0), Shuffle,
22867 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22868 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22872 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22873 /// special and don't usually play with other vector types, it's better to
22874 /// handle them early to be sure we emit efficient code by avoiding
22875 /// store-load conversions.
22876 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22877 if (N->getValueType(0) != MVT::x86mmx ||
22878 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22879 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22882 SDValue V = N->getOperand(0);
22883 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22884 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22885 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22886 N->getValueType(0), V.getOperand(0));
22891 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22892 /// generation and convert it from being a bunch of shuffles and extracts
22893 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22894 /// storing the value and loading scalars back, while for x64 we should
22895 /// use 64-bit extracts and shifts.
22896 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22897 TargetLowering::DAGCombinerInfo &DCI) {
22898 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22901 SDValue InputVector = N->getOperand(0);
22902 SDLoc dl(InputVector);
22903 // Detect mmx to i32 conversion through a v2i32 elt extract.
22904 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22905 N->getValueType(0) == MVT::i32 &&
22906 InputVector.getValueType() == MVT::v2i32) {
22908 // The bitcast source is a direct mmx result.
22909 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22910 if (MMXSrc.getValueType() == MVT::x86mmx)
22911 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22912 N->getValueType(0),
22913 InputVector.getNode()->getOperand(0));
22915 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22916 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22917 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22918 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
22919 MMXSrcOp.getOpcode() == ISD::BITCAST &&
22920 MMXSrcOp.getValueType() == MVT::v1i64 &&
22921 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22922 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22923 N->getValueType(0),
22924 MMXSrcOp.getOperand(0));
22927 EVT VT = N->getValueType(0);
22929 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22930 InputVector.getOpcode() == ISD::BITCAST &&
22931 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22932 uint64_t ExtractedElt =
22933 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
22934 uint64_t InputValue =
22935 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
22936 uint64_t Res = (InputValue >> ExtractedElt) & 1;
22937 return DAG.getConstant(Res, dl, MVT::i1);
22939 // Only operate on vectors of 4 elements, where the alternative shuffling
22940 // gets to be more expensive.
22941 if (InputVector.getValueType() != MVT::v4i32)
22944 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22945 // single use which is a sign-extend or zero-extend, and all elements are
22947 SmallVector<SDNode *, 4> Uses;
22948 unsigned ExtractedElements = 0;
22949 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22950 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22951 if (UI.getUse().getResNo() != InputVector.getResNo())
22954 SDNode *Extract = *UI;
22955 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22958 if (Extract->getValueType(0) != MVT::i32)
22960 if (!Extract->hasOneUse())
22962 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22963 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22965 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22968 // Record which element was extracted.
22969 ExtractedElements |=
22970 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22972 Uses.push_back(Extract);
22975 // If not all the elements were used, this may not be worthwhile.
22976 if (ExtractedElements != 15)
22979 // Ok, we've now decided to do the transformation.
22980 // If 64-bit shifts are legal, use the extract-shift sequence,
22981 // otherwise bounce the vector off the cache.
22982 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22985 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22986 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
22987 auto &DL = DAG.getDataLayout();
22988 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
22989 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22990 DAG.getConstant(0, dl, VecIdxTy));
22991 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22992 DAG.getConstant(1, dl, VecIdxTy));
22994 SDValue ShAmt = DAG.getConstant(
22995 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
22996 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22997 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22998 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22999 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23000 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23001 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23003 // Store the value to a temporary stack slot.
23004 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23005 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23006 MachinePointerInfo(), false, false, 0);
23008 EVT ElementType = InputVector.getValueType().getVectorElementType();
23009 unsigned EltSize = ElementType.getSizeInBits() / 8;
23011 // Replace each use (extract) with a load of the appropriate element.
23012 for (unsigned i = 0; i < 4; ++i) {
23013 uint64_t Offset = EltSize * i;
23014 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23015 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23017 SDValue ScalarAddr =
23018 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23020 // Load the scalar.
23021 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23022 ScalarAddr, MachinePointerInfo(),
23023 false, false, false, 0);
23028 // Replace the extracts
23029 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23030 UE = Uses.end(); UI != UE; ++UI) {
23031 SDNode *Extract = *UI;
23033 SDValue Idx = Extract->getOperand(1);
23034 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23035 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23038 // The replacement was made in place; don't return anything.
23043 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23044 const X86Subtarget *Subtarget) {
23046 SDValue Cond = N->getOperand(0);
23047 SDValue LHS = N->getOperand(1);
23048 SDValue RHS = N->getOperand(2);
23050 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23051 SDValue CondSrc = Cond->getOperand(0);
23052 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23053 Cond = CondSrc->getOperand(0);
23056 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23059 // A vselect where all conditions and data are constants can be optimized into
23060 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23061 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23062 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23065 unsigned MaskValue = 0;
23066 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23069 MVT VT = N->getSimpleValueType(0);
23070 unsigned NumElems = VT.getVectorNumElements();
23071 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23072 for (unsigned i = 0; i < NumElems; ++i) {
23073 // Be sure we emit undef where we can.
23074 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23075 ShuffleMask[i] = -1;
23077 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23080 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23081 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23083 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23086 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23088 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23089 TargetLowering::DAGCombinerInfo &DCI,
23090 const X86Subtarget *Subtarget) {
23092 SDValue Cond = N->getOperand(0);
23093 // Get the LHS/RHS of the select.
23094 SDValue LHS = N->getOperand(1);
23095 SDValue RHS = N->getOperand(2);
23096 EVT VT = LHS.getValueType();
23097 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23099 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23100 // instructions match the semantics of the common C idiom x<y?x:y but not
23101 // x<=y?x:y, because of how they handle negative zero (which can be
23102 // ignored in unsafe-math mode).
23103 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23104 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23105 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23106 (Subtarget->hasSSE2() ||
23107 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23108 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23110 unsigned Opcode = 0;
23111 // Check for x CC y ? x : y.
23112 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23113 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23117 // Converting this to a min would handle NaNs incorrectly, and swapping
23118 // the operands would cause it to handle comparisons between positive
23119 // and negative zero incorrectly.
23120 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23121 if (!DAG.getTarget().Options.UnsafeFPMath &&
23122 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23124 std::swap(LHS, RHS);
23126 Opcode = X86ISD::FMIN;
23129 // Converting this to a min would handle comparisons between positive
23130 // and negative zero incorrectly.
23131 if (!DAG.getTarget().Options.UnsafeFPMath &&
23132 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23134 Opcode = X86ISD::FMIN;
23137 // Converting this to a min would handle both negative zeros and NaNs
23138 // incorrectly, but we can swap the operands to fix both.
23139 std::swap(LHS, RHS);
23143 Opcode = X86ISD::FMIN;
23147 // Converting this to a max would handle comparisons between positive
23148 // and negative zero incorrectly.
23149 if (!DAG.getTarget().Options.UnsafeFPMath &&
23150 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23152 Opcode = X86ISD::FMAX;
23155 // Converting this to a max would handle NaNs incorrectly, and swapping
23156 // the operands would cause it to handle comparisons between positive
23157 // and negative zero incorrectly.
23158 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23159 if (!DAG.getTarget().Options.UnsafeFPMath &&
23160 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23162 std::swap(LHS, RHS);
23164 Opcode = X86ISD::FMAX;
23167 // Converting this to a max would handle both negative zeros and NaNs
23168 // incorrectly, but we can swap the operands to fix both.
23169 std::swap(LHS, RHS);
23173 Opcode = X86ISD::FMAX;
23176 // Check for x CC y ? y : x -- a min/max with reversed arms.
23177 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23178 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23182 // Converting this to a min would handle comparisons between positive
23183 // and negative zero incorrectly, and swapping the operands would
23184 // cause it to handle NaNs incorrectly.
23185 if (!DAG.getTarget().Options.UnsafeFPMath &&
23186 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23187 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23189 std::swap(LHS, RHS);
23191 Opcode = X86ISD::FMIN;
23194 // Converting this to a min would handle NaNs incorrectly.
23195 if (!DAG.getTarget().Options.UnsafeFPMath &&
23196 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23198 Opcode = X86ISD::FMIN;
23201 // Converting this to a min would handle both negative zeros and NaNs
23202 // incorrectly, but we can swap the operands to fix both.
23203 std::swap(LHS, RHS);
23207 Opcode = X86ISD::FMIN;
23211 // Converting this to a max would handle NaNs incorrectly.
23212 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23214 Opcode = X86ISD::FMAX;
23217 // Converting this to a max would handle comparisons between positive
23218 // and negative zero incorrectly, and swapping the operands would
23219 // cause it to handle NaNs incorrectly.
23220 if (!DAG.getTarget().Options.UnsafeFPMath &&
23221 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23222 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23224 std::swap(LHS, RHS);
23226 Opcode = X86ISD::FMAX;
23229 // Converting this to a max would handle both negative zeros and NaNs
23230 // incorrectly, but we can swap the operands to fix both.
23231 std::swap(LHS, RHS);
23235 Opcode = X86ISD::FMAX;
23241 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23244 EVT CondVT = Cond.getValueType();
23245 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23246 CondVT.getVectorElementType() == MVT::i1) {
23247 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23248 // lowering on KNL. In this case we convert it to
23249 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23250 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23251 // Since SKX these selects have a proper lowering.
23252 EVT OpVT = LHS.getValueType();
23253 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23254 (OpVT.getVectorElementType() == MVT::i8 ||
23255 OpVT.getVectorElementType() == MVT::i16) &&
23256 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23257 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23258 DCI.AddToWorklist(Cond.getNode());
23259 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23262 // If this is a select between two integer constants, try to do some
23264 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23265 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23266 // Don't do this for crazy integer types.
23267 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23268 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23269 // so that TrueC (the true value) is larger than FalseC.
23270 bool NeedsCondInvert = false;
23272 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23273 // Efficiently invertible.
23274 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23275 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23276 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23277 NeedsCondInvert = true;
23278 std::swap(TrueC, FalseC);
23281 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23282 if (FalseC->getAPIntValue() == 0 &&
23283 TrueC->getAPIntValue().isPowerOf2()) {
23284 if (NeedsCondInvert) // Invert the condition if needed.
23285 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23286 DAG.getConstant(1, DL, Cond.getValueType()));
23288 // Zero extend the condition if needed.
23289 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23291 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23292 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23293 DAG.getConstant(ShAmt, DL, MVT::i8));
23296 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23297 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23298 if (NeedsCondInvert) // Invert the condition if needed.
23299 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23300 DAG.getConstant(1, DL, Cond.getValueType()));
23302 // Zero extend the condition if needed.
23303 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23304 FalseC->getValueType(0), Cond);
23305 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23306 SDValue(FalseC, 0));
23309 // Optimize cases that will turn into an LEA instruction. This requires
23310 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23311 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23312 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23313 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23315 bool isFastMultiplier = false;
23317 switch ((unsigned char)Diff) {
23319 case 1: // result = add base, cond
23320 case 2: // result = lea base( , cond*2)
23321 case 3: // result = lea base(cond, cond*2)
23322 case 4: // result = lea base( , cond*4)
23323 case 5: // result = lea base(cond, cond*4)
23324 case 8: // result = lea base( , cond*8)
23325 case 9: // result = lea base(cond, cond*8)
23326 isFastMultiplier = true;
23331 if (isFastMultiplier) {
23332 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23333 if (NeedsCondInvert) // Invert the condition if needed.
23334 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23335 DAG.getConstant(1, DL, Cond.getValueType()));
23337 // Zero extend the condition if needed.
23338 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23340 // Scale the condition by the difference.
23342 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23343 DAG.getConstant(Diff, DL,
23344 Cond.getValueType()));
23346 // Add the base if non-zero.
23347 if (FalseC->getAPIntValue() != 0)
23348 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23349 SDValue(FalseC, 0));
23356 // Canonicalize max and min:
23357 // (x > y) ? x : y -> (x >= y) ? x : y
23358 // (x < y) ? x : y -> (x <= y) ? x : y
23359 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23360 // the need for an extra compare
23361 // against zero. e.g.
23362 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23364 // testl %edi, %edi
23366 // cmovgl %edi, %eax
23370 // cmovsl %eax, %edi
23371 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23372 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23373 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23374 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23379 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23380 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23381 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23382 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23387 // Early exit check
23388 if (!TLI.isTypeLegal(VT))
23391 // Match VSELECTs into subs with unsigned saturation.
23392 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23393 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23394 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23395 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23396 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23398 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23399 // left side invert the predicate to simplify logic below.
23401 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23403 CC = ISD::getSetCCInverse(CC, true);
23404 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23408 if (Other.getNode() && Other->getNumOperands() == 2 &&
23409 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23410 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23411 SDValue CondRHS = Cond->getOperand(1);
23413 // Look for a general sub with unsigned saturation first.
23414 // x >= y ? x-y : 0 --> subus x, y
23415 // x > y ? x-y : 0 --> subus x, y
23416 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23417 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23418 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23420 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23421 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23422 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23423 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23424 // If the RHS is a constant we have to reverse the const
23425 // canonicalization.
23426 // x > C-1 ? x+-C : 0 --> subus x, C
23427 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23428 CondRHSConst->getAPIntValue() ==
23429 (-OpRHSConst->getAPIntValue() - 1))
23430 return DAG.getNode(
23431 X86ISD::SUBUS, DL, VT, OpLHS,
23432 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23434 // Another special case: If C was a sign bit, the sub has been
23435 // canonicalized into a xor.
23436 // FIXME: Would it be better to use computeKnownBits to determine
23437 // whether it's safe to decanonicalize the xor?
23438 // x s< 0 ? x^C : 0 --> subus x, C
23439 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23440 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23441 OpRHSConst->getAPIntValue().isSignBit())
23442 // Note that we have to rebuild the RHS constant here to ensure we
23443 // don't rely on particular values of undef lanes.
23444 return DAG.getNode(
23445 X86ISD::SUBUS, DL, VT, OpLHS,
23446 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23451 // Simplify vector selection if condition value type matches vselect
23453 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23454 assert(Cond.getValueType().isVector() &&
23455 "vector select expects a vector selector!");
23457 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23458 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23460 // Try invert the condition if true value is not all 1s and false value
23462 if (!TValIsAllOnes && !FValIsAllZeros &&
23463 // Check if the selector will be produced by CMPP*/PCMP*
23464 Cond.getOpcode() == ISD::SETCC &&
23465 // Check if SETCC has already been promoted
23466 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23468 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23469 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23471 if (TValIsAllZeros || FValIsAllOnes) {
23472 SDValue CC = Cond.getOperand(2);
23473 ISD::CondCode NewCC =
23474 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23475 Cond.getOperand(0).getValueType().isInteger());
23476 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23477 std::swap(LHS, RHS);
23478 TValIsAllOnes = FValIsAllOnes;
23479 FValIsAllZeros = TValIsAllZeros;
23483 if (TValIsAllOnes || FValIsAllZeros) {
23486 if (TValIsAllOnes && FValIsAllZeros)
23488 else if (TValIsAllOnes)
23490 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23491 else if (FValIsAllZeros)
23492 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23493 DAG.getBitcast(CondVT, LHS));
23495 return DAG.getBitcast(VT, Ret);
23499 // We should generate an X86ISD::BLENDI from a vselect if its argument
23500 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23501 // constants. This specific pattern gets generated when we split a
23502 // selector for a 512 bit vector in a machine without AVX512 (but with
23503 // 256-bit vectors), during legalization:
23505 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23507 // Iff we find this pattern and the build_vectors are built from
23508 // constants, we translate the vselect into a shuffle_vector that we
23509 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23510 if ((N->getOpcode() == ISD::VSELECT ||
23511 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23512 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23513 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23514 if (Shuffle.getNode())
23518 // If this is a *dynamic* select (non-constant condition) and we can match
23519 // this node with one of the variable blend instructions, restructure the
23520 // condition so that the blends can use the high bit of each element and use
23521 // SimplifyDemandedBits to simplify the condition operand.
23522 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23523 !DCI.isBeforeLegalize() &&
23524 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23525 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23527 // Don't optimize vector selects that map to mask-registers.
23531 // We can only handle the cases where VSELECT is directly legal on the
23532 // subtarget. We custom lower VSELECT nodes with constant conditions and
23533 // this makes it hard to see whether a dynamic VSELECT will correctly
23534 // lower, so we both check the operation's status and explicitly handle the
23535 // cases where a *dynamic* blend will fail even though a constant-condition
23536 // blend could be custom lowered.
23537 // FIXME: We should find a better way to handle this class of problems.
23538 // Potentially, we should combine constant-condition vselect nodes
23539 // pre-legalization into shuffles and not mark as many types as custom
23541 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23543 // FIXME: We don't support i16-element blends currently. We could and
23544 // should support them by making *all* the bits in the condition be set
23545 // rather than just the high bit and using an i8-element blend.
23546 if (VT.getScalarType() == MVT::i16)
23548 // Dynamic blending was only available from SSE4.1 onward.
23549 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23551 // Byte blends are only available in AVX2
23552 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23553 !Subtarget->hasAVX2())
23556 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23557 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23559 APInt KnownZero, KnownOne;
23560 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23561 DCI.isBeforeLegalizeOps());
23562 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23563 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23565 // If we changed the computation somewhere in the DAG, this change
23566 // will affect all users of Cond.
23567 // Make sure it is fine and update all the nodes so that we do not
23568 // use the generic VSELECT anymore. Otherwise, we may perform
23569 // wrong optimizations as we messed up with the actual expectation
23570 // for the vector boolean values.
23571 if (Cond != TLO.Old) {
23572 // Check all uses of that condition operand to check whether it will be
23573 // consumed by non-BLEND instructions, which may depend on all bits are
23575 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23577 if (I->getOpcode() != ISD::VSELECT)
23578 // TODO: Add other opcodes eventually lowered into BLEND.
23581 // Update all the users of the condition, before committing the change,
23582 // so that the VSELECT optimizations that expect the correct vector
23583 // boolean value will not be triggered.
23584 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23586 DAG.ReplaceAllUsesOfValueWith(
23588 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23589 Cond, I->getOperand(1), I->getOperand(2)));
23590 DCI.CommitTargetLoweringOpt(TLO);
23593 // At this point, only Cond is changed. Change the condition
23594 // just for N to keep the opportunity to optimize all other
23595 // users their own way.
23596 DAG.ReplaceAllUsesOfValueWith(
23598 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23599 TLO.New, N->getOperand(1), N->getOperand(2)));
23607 // Check whether a boolean test is testing a boolean value generated by
23608 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23611 // Simplify the following patterns:
23612 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23613 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23614 // to (Op EFLAGS Cond)
23616 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23617 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23618 // to (Op EFLAGS !Cond)
23620 // where Op could be BRCOND or CMOV.
23622 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23623 // Quit if not CMP and SUB with its value result used.
23624 if (Cmp.getOpcode() != X86ISD::CMP &&
23625 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23628 // Quit if not used as a boolean value.
23629 if (CC != X86::COND_E && CC != X86::COND_NE)
23632 // Check CMP operands. One of them should be 0 or 1 and the other should be
23633 // an SetCC or extended from it.
23634 SDValue Op1 = Cmp.getOperand(0);
23635 SDValue Op2 = Cmp.getOperand(1);
23638 const ConstantSDNode* C = nullptr;
23639 bool needOppositeCond = (CC == X86::COND_E);
23640 bool checkAgainstTrue = false; // Is it a comparison against 1?
23642 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23644 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23646 else // Quit if all operands are not constants.
23649 if (C->getZExtValue() == 1) {
23650 needOppositeCond = !needOppositeCond;
23651 checkAgainstTrue = true;
23652 } else if (C->getZExtValue() != 0)
23653 // Quit if the constant is neither 0 or 1.
23656 bool truncatedToBoolWithAnd = false;
23657 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23658 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23659 SetCC.getOpcode() == ISD::TRUNCATE ||
23660 SetCC.getOpcode() == ISD::AND) {
23661 if (SetCC.getOpcode() == ISD::AND) {
23663 ConstantSDNode *CS;
23664 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23665 CS->getZExtValue() == 1)
23667 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23668 CS->getZExtValue() == 1)
23672 SetCC = SetCC.getOperand(OpIdx);
23673 truncatedToBoolWithAnd = true;
23675 SetCC = SetCC.getOperand(0);
23678 switch (SetCC.getOpcode()) {
23679 case X86ISD::SETCC_CARRY:
23680 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23681 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23682 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23683 // truncated to i1 using 'and'.
23684 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23686 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23687 "Invalid use of SETCC_CARRY!");
23689 case X86ISD::SETCC:
23690 // Set the condition code or opposite one if necessary.
23691 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23692 if (needOppositeCond)
23693 CC = X86::GetOppositeBranchCondition(CC);
23694 return SetCC.getOperand(1);
23695 case X86ISD::CMOV: {
23696 // Check whether false/true value has canonical one, i.e. 0 or 1.
23697 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23698 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23699 // Quit if true value is not a constant.
23702 // Quit if false value is not a constant.
23704 SDValue Op = SetCC.getOperand(0);
23705 // Skip 'zext' or 'trunc' node.
23706 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23707 Op.getOpcode() == ISD::TRUNCATE)
23708 Op = Op.getOperand(0);
23709 // A special case for rdrand/rdseed, where 0 is set if false cond is
23711 if ((Op.getOpcode() != X86ISD::RDRAND &&
23712 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23715 // Quit if false value is not the constant 0 or 1.
23716 bool FValIsFalse = true;
23717 if (FVal && FVal->getZExtValue() != 0) {
23718 if (FVal->getZExtValue() != 1)
23720 // If FVal is 1, opposite cond is needed.
23721 needOppositeCond = !needOppositeCond;
23722 FValIsFalse = false;
23724 // Quit if TVal is not the constant opposite of FVal.
23725 if (FValIsFalse && TVal->getZExtValue() != 1)
23727 if (!FValIsFalse && TVal->getZExtValue() != 0)
23729 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23730 if (needOppositeCond)
23731 CC = X86::GetOppositeBranchCondition(CC);
23732 return SetCC.getOperand(3);
23739 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23741 /// (X86or (X86setcc) (X86setcc))
23742 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23743 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23744 X86::CondCode &CC1, SDValue &Flags,
23746 if (Cond->getOpcode() == X86ISD::CMP) {
23747 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23748 if (!CondOp1C || !CondOp1C->isNullValue())
23751 Cond = Cond->getOperand(0);
23756 SDValue SetCC0, SetCC1;
23757 switch (Cond->getOpcode()) {
23758 default: return false;
23765 SetCC0 = Cond->getOperand(0);
23766 SetCC1 = Cond->getOperand(1);
23770 // Make sure we have SETCC nodes, using the same flags value.
23771 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23772 SetCC1.getOpcode() != X86ISD::SETCC ||
23773 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23776 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23777 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23778 Flags = SetCC0->getOperand(1);
23782 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23783 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23784 TargetLowering::DAGCombinerInfo &DCI,
23785 const X86Subtarget *Subtarget) {
23788 // If the flag operand isn't dead, don't touch this CMOV.
23789 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23792 SDValue FalseOp = N->getOperand(0);
23793 SDValue TrueOp = N->getOperand(1);
23794 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23795 SDValue Cond = N->getOperand(3);
23797 if (CC == X86::COND_E || CC == X86::COND_NE) {
23798 switch (Cond.getOpcode()) {
23802 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23803 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23804 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23810 Flags = checkBoolTestSetCCCombine(Cond, CC);
23811 if (Flags.getNode() &&
23812 // Extra check as FCMOV only supports a subset of X86 cond.
23813 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23814 SDValue Ops[] = { FalseOp, TrueOp,
23815 DAG.getConstant(CC, DL, MVT::i8), Flags };
23816 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23819 // If this is a select between two integer constants, try to do some
23820 // optimizations. Note that the operands are ordered the opposite of SELECT
23822 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23823 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23824 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23825 // larger than FalseC (the false value).
23826 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23827 CC = X86::GetOppositeBranchCondition(CC);
23828 std::swap(TrueC, FalseC);
23829 std::swap(TrueOp, FalseOp);
23832 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23833 // This is efficient for any integer data type (including i8/i16) and
23835 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23836 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23837 DAG.getConstant(CC, DL, MVT::i8), Cond);
23839 // Zero extend the condition if needed.
23840 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23842 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23843 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23844 DAG.getConstant(ShAmt, DL, MVT::i8));
23845 if (N->getNumValues() == 2) // Dead flag value?
23846 return DCI.CombineTo(N, Cond, SDValue());
23850 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23851 // for any integer data type, including i8/i16.
23852 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23853 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23854 DAG.getConstant(CC, DL, MVT::i8), Cond);
23856 // Zero extend the condition if needed.
23857 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23858 FalseC->getValueType(0), Cond);
23859 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23860 SDValue(FalseC, 0));
23862 if (N->getNumValues() == 2) // Dead flag value?
23863 return DCI.CombineTo(N, Cond, SDValue());
23867 // Optimize cases that will turn into an LEA instruction. This requires
23868 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23869 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23870 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23871 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23873 bool isFastMultiplier = false;
23875 switch ((unsigned char)Diff) {
23877 case 1: // result = add base, cond
23878 case 2: // result = lea base( , cond*2)
23879 case 3: // result = lea base(cond, cond*2)
23880 case 4: // result = lea base( , cond*4)
23881 case 5: // result = lea base(cond, cond*4)
23882 case 8: // result = lea base( , cond*8)
23883 case 9: // result = lea base(cond, cond*8)
23884 isFastMultiplier = true;
23889 if (isFastMultiplier) {
23890 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23891 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23892 DAG.getConstant(CC, DL, MVT::i8), Cond);
23893 // Zero extend the condition if needed.
23894 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23896 // Scale the condition by the difference.
23898 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23899 DAG.getConstant(Diff, DL, Cond.getValueType()));
23901 // Add the base if non-zero.
23902 if (FalseC->getAPIntValue() != 0)
23903 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23904 SDValue(FalseC, 0));
23905 if (N->getNumValues() == 2) // Dead flag value?
23906 return DCI.CombineTo(N, Cond, SDValue());
23913 // Handle these cases:
23914 // (select (x != c), e, c) -> select (x != c), e, x),
23915 // (select (x == c), c, e) -> select (x == c), x, e)
23916 // where the c is an integer constant, and the "select" is the combination
23917 // of CMOV and CMP.
23919 // The rationale for this change is that the conditional-move from a constant
23920 // needs two instructions, however, conditional-move from a register needs
23921 // only one instruction.
23923 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23924 // some instruction-combining opportunities. This opt needs to be
23925 // postponed as late as possible.
23927 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23928 // the DCI.xxxx conditions are provided to postpone the optimization as
23929 // late as possible.
23931 ConstantSDNode *CmpAgainst = nullptr;
23932 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23933 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23934 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23936 if (CC == X86::COND_NE &&
23937 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23938 CC = X86::GetOppositeBranchCondition(CC);
23939 std::swap(TrueOp, FalseOp);
23942 if (CC == X86::COND_E &&
23943 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23944 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23945 DAG.getConstant(CC, DL, MVT::i8), Cond };
23946 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23951 // Fold and/or of setcc's to double CMOV:
23952 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
23953 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
23955 // This combine lets us generate:
23956 // cmovcc1 (jcc1 if we don't have CMOV)
23962 // cmovne (jne if we don't have CMOV)
23963 // When we can't use the CMOV instruction, it might increase branch
23965 // When we can use CMOV, or when there is no mispredict, this improves
23966 // throughput and reduces register pressure.
23968 if (CC == X86::COND_NE) {
23970 X86::CondCode CC0, CC1;
23972 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
23974 std::swap(FalseOp, TrueOp);
23975 CC0 = X86::GetOppositeBranchCondition(CC0);
23976 CC1 = X86::GetOppositeBranchCondition(CC1);
23979 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
23981 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
23982 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
23983 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23984 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
23992 /// PerformMulCombine - Optimize a single multiply with constant into two
23993 /// in order to implement it with two cheaper instructions, e.g.
23994 /// LEA + SHL, LEA + LEA.
23995 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23996 TargetLowering::DAGCombinerInfo &DCI) {
23997 // An imul is usually smaller than the alternative sequence.
23998 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24001 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24004 EVT VT = N->getValueType(0);
24005 if (VT != MVT::i64 && VT != MVT::i32)
24008 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24011 uint64_t MulAmt = C->getZExtValue();
24012 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24015 uint64_t MulAmt1 = 0;
24016 uint64_t MulAmt2 = 0;
24017 if ((MulAmt % 9) == 0) {
24019 MulAmt2 = MulAmt / 9;
24020 } else if ((MulAmt % 5) == 0) {
24022 MulAmt2 = MulAmt / 5;
24023 } else if ((MulAmt % 3) == 0) {
24025 MulAmt2 = MulAmt / 3;
24028 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24031 if (isPowerOf2_64(MulAmt2) &&
24032 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24033 // If second multiplifer is pow2, issue it first. We want the multiply by
24034 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24036 std::swap(MulAmt1, MulAmt2);
24039 if (isPowerOf2_64(MulAmt1))
24040 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24041 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24043 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24044 DAG.getConstant(MulAmt1, DL, VT));
24046 if (isPowerOf2_64(MulAmt2))
24047 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24048 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24050 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24051 DAG.getConstant(MulAmt2, DL, VT));
24053 // Do not add new nodes to DAG combiner worklist.
24054 DCI.CombineTo(N, NewMul, false);
24059 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24060 SDValue N0 = N->getOperand(0);
24061 SDValue N1 = N->getOperand(1);
24062 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24063 EVT VT = N0.getValueType();
24065 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24066 // since the result of setcc_c is all zero's or all ones.
24067 if (VT.isInteger() && !VT.isVector() &&
24068 N1C && N0.getOpcode() == ISD::AND &&
24069 N0.getOperand(1).getOpcode() == ISD::Constant) {
24070 SDValue N00 = N0.getOperand(0);
24071 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24072 APInt ShAmt = N1C->getAPIntValue();
24073 Mask = Mask.shl(ShAmt);
24074 bool MaskOK = false;
24075 // We can handle cases concerning bit-widening nodes containing setcc_c if
24076 // we carefully interrogate the mask to make sure we are semantics
24078 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24079 // of the underlying setcc_c operation if the setcc_c was zero extended.
24080 // Consider the following example:
24081 // zext(setcc_c) -> i32 0x0000FFFF
24082 // c1 -> i32 0x0000FFFF
24083 // c2 -> i32 0x00000001
24084 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24085 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24086 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24088 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24089 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24091 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24092 N00.getOpcode() == ISD::ANY_EXTEND) &&
24093 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24094 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24096 if (MaskOK && Mask != 0) {
24098 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24102 // Hardware support for vector shifts is sparse which makes us scalarize the
24103 // vector operations in many cases. Also, on sandybridge ADD is faster than
24105 // (shl V, 1) -> add V,V
24106 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24107 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24108 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24109 // We shift all of the values by one. In many cases we do not have
24110 // hardware support for this operation. This is better expressed as an ADD
24112 if (N1SplatC->getAPIntValue() == 1)
24113 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24119 /// \brief Returns a vector of 0s if the node in input is a vector logical
24120 /// shift by a constant amount which is known to be bigger than or equal
24121 /// to the vector element size in bits.
24122 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24123 const X86Subtarget *Subtarget) {
24124 EVT VT = N->getValueType(0);
24126 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24127 (!Subtarget->hasInt256() ||
24128 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24131 SDValue Amt = N->getOperand(1);
24133 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24134 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24135 APInt ShiftAmt = AmtSplat->getAPIntValue();
24136 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24138 // SSE2/AVX2 logical shifts always return a vector of 0s
24139 // if the shift amount is bigger than or equal to
24140 // the element size. The constant shift amount will be
24141 // encoded as a 8-bit immediate.
24142 if (ShiftAmt.trunc(8).uge(MaxAmount))
24143 return getZeroVector(VT, Subtarget, DAG, DL);
24149 /// PerformShiftCombine - Combine shifts.
24150 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24151 TargetLowering::DAGCombinerInfo &DCI,
24152 const X86Subtarget *Subtarget) {
24153 if (N->getOpcode() == ISD::SHL)
24154 if (SDValue V = PerformSHLCombine(N, DAG))
24157 // Try to fold this logical shift into a zero vector.
24158 if (N->getOpcode() != ISD::SRA)
24159 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24165 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24166 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24167 // and friends. Likewise for OR -> CMPNEQSS.
24168 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24169 TargetLowering::DAGCombinerInfo &DCI,
24170 const X86Subtarget *Subtarget) {
24173 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24174 // we're requiring SSE2 for both.
24175 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24176 SDValue N0 = N->getOperand(0);
24177 SDValue N1 = N->getOperand(1);
24178 SDValue CMP0 = N0->getOperand(1);
24179 SDValue CMP1 = N1->getOperand(1);
24182 // The SETCCs should both refer to the same CMP.
24183 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24186 SDValue CMP00 = CMP0->getOperand(0);
24187 SDValue CMP01 = CMP0->getOperand(1);
24188 EVT VT = CMP00.getValueType();
24190 if (VT == MVT::f32 || VT == MVT::f64) {
24191 bool ExpectingFlags = false;
24192 // Check for any users that want flags:
24193 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24194 !ExpectingFlags && UI != UE; ++UI)
24195 switch (UI->getOpcode()) {
24200 ExpectingFlags = true;
24202 case ISD::CopyToReg:
24203 case ISD::SIGN_EXTEND:
24204 case ISD::ZERO_EXTEND:
24205 case ISD::ANY_EXTEND:
24209 if (!ExpectingFlags) {
24210 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24211 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24213 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24214 X86::CondCode tmp = cc0;
24219 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24220 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24221 // FIXME: need symbolic constants for these magic numbers.
24222 // See X86ATTInstPrinter.cpp:printSSECC().
24223 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24224 if (Subtarget->hasAVX512()) {
24225 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24227 DAG.getConstant(x86cc, DL, MVT::i8));
24228 if (N->getValueType(0) != MVT::i1)
24229 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24233 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24234 CMP00.getValueType(), CMP00, CMP01,
24235 DAG.getConstant(x86cc, DL,
24238 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24239 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24241 if (is64BitFP && !Subtarget->is64Bit()) {
24242 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24243 // 64-bit integer, since that's not a legal type. Since
24244 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24245 // bits, but can do this little dance to extract the lowest 32 bits
24246 // and work with those going forward.
24247 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24249 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24250 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24251 Vector32, DAG.getIntPtrConstant(0, DL));
24255 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24256 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24257 DAG.getConstant(1, DL, IntVT));
24258 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24260 return OneBitOfTruth;
24268 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24269 /// so it can be folded inside ANDNP.
24270 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24271 EVT VT = N->getValueType(0);
24273 // Match direct AllOnes for 128 and 256-bit vectors
24274 if (ISD::isBuildVectorAllOnes(N))
24277 // Look through a bit convert.
24278 if (N->getOpcode() == ISD::BITCAST)
24279 N = N->getOperand(0).getNode();
24281 // Sometimes the operand may come from a insert_subvector building a 256-bit
24283 if (VT.is256BitVector() &&
24284 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24285 SDValue V1 = N->getOperand(0);
24286 SDValue V2 = N->getOperand(1);
24288 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24289 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24290 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24291 ISD::isBuildVectorAllOnes(V2.getNode()))
24298 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24299 // register. In most cases we actually compare or select YMM-sized registers
24300 // and mixing the two types creates horrible code. This method optimizes
24301 // some of the transition sequences.
24302 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24303 TargetLowering::DAGCombinerInfo &DCI,
24304 const X86Subtarget *Subtarget) {
24305 EVT VT = N->getValueType(0);
24306 if (!VT.is256BitVector())
24309 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24310 N->getOpcode() == ISD::ZERO_EXTEND ||
24311 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24313 SDValue Narrow = N->getOperand(0);
24314 EVT NarrowVT = Narrow->getValueType(0);
24315 if (!NarrowVT.is128BitVector())
24318 if (Narrow->getOpcode() != ISD::XOR &&
24319 Narrow->getOpcode() != ISD::AND &&
24320 Narrow->getOpcode() != ISD::OR)
24323 SDValue N0 = Narrow->getOperand(0);
24324 SDValue N1 = Narrow->getOperand(1);
24327 // The Left side has to be a trunc.
24328 if (N0.getOpcode() != ISD::TRUNCATE)
24331 // The type of the truncated inputs.
24332 EVT WideVT = N0->getOperand(0)->getValueType(0);
24336 // The right side has to be a 'trunc' or a constant vector.
24337 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24338 ConstantSDNode *RHSConstSplat = nullptr;
24339 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24340 RHSConstSplat = RHSBV->getConstantSplatNode();
24341 if (!RHSTrunc && !RHSConstSplat)
24344 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24346 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24349 // Set N0 and N1 to hold the inputs to the new wide operation.
24350 N0 = N0->getOperand(0);
24351 if (RHSConstSplat) {
24352 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24353 SDValue(RHSConstSplat, 0));
24354 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24355 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24356 } else if (RHSTrunc) {
24357 N1 = N1->getOperand(0);
24360 // Generate the wide operation.
24361 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24362 unsigned Opcode = N->getOpcode();
24364 case ISD::ANY_EXTEND:
24366 case ISD::ZERO_EXTEND: {
24367 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24368 APInt Mask = APInt::getAllOnesValue(InBits);
24369 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24370 return DAG.getNode(ISD::AND, DL, VT,
24371 Op, DAG.getConstant(Mask, DL, VT));
24373 case ISD::SIGN_EXTEND:
24374 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24375 Op, DAG.getValueType(NarrowVT));
24377 llvm_unreachable("Unexpected opcode");
24381 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24382 TargetLowering::DAGCombinerInfo &DCI,
24383 const X86Subtarget *Subtarget) {
24384 SDValue N0 = N->getOperand(0);
24385 SDValue N1 = N->getOperand(1);
24388 // A vector zext_in_reg may be represented as a shuffle,
24389 // feeding into a bitcast (this represents anyext) feeding into
24390 // an and with a mask.
24391 // We'd like to try to combine that into a shuffle with zero
24392 // plus a bitcast, removing the and.
24393 if (N0.getOpcode() != ISD::BITCAST ||
24394 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24397 // The other side of the AND should be a splat of 2^C, where C
24398 // is the number of bits in the source type.
24399 if (N1.getOpcode() == ISD::BITCAST)
24400 N1 = N1.getOperand(0);
24401 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24403 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24405 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24406 EVT SrcType = Shuffle->getValueType(0);
24408 // We expect a single-source shuffle
24409 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24412 unsigned SrcSize = SrcType.getScalarSizeInBits();
24414 APInt SplatValue, SplatUndef;
24415 unsigned SplatBitSize;
24417 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24418 SplatBitSize, HasAnyUndefs))
24421 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24422 // Make sure the splat matches the mask we expect
24423 if (SplatBitSize > ResSize ||
24424 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24427 // Make sure the input and output size make sense
24428 if (SrcSize >= ResSize || ResSize % SrcSize)
24431 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24432 // The number of u's between each two values depends on the ratio between
24433 // the source and dest type.
24434 unsigned ZextRatio = ResSize / SrcSize;
24435 bool IsZext = true;
24436 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24437 if (i % ZextRatio) {
24438 if (Shuffle->getMaskElt(i) > 0) {
24444 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24445 // Expected element number
24455 // Ok, perform the transformation - replace the shuffle with
24456 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24457 // (instead of undef) where the k elements come from the zero vector.
24458 SmallVector<int, 8> Mask;
24459 unsigned NumElems = SrcType.getVectorNumElements();
24460 for (unsigned i = 0; i < NumElems; ++i)
24462 Mask.push_back(NumElems);
24464 Mask.push_back(i / ZextRatio);
24466 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24467 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24468 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24471 /// If both input operands of a logic op are being cast from floating point
24472 /// types, try to convert this into a floating point logic node to avoid
24473 /// unnecessary moves from SSE to integer registers.
24474 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24475 const X86Subtarget *Subtarget) {
24476 unsigned FPOpcode = ISD::DELETED_NODE;
24477 if (N->getOpcode() == ISD::AND)
24478 FPOpcode = X86ISD::FAND;
24479 else if (N->getOpcode() == ISD::OR)
24480 FPOpcode = X86ISD::FOR;
24481 else if (N->getOpcode() == ISD::XOR)
24482 FPOpcode = X86ISD::FXOR;
24484 assert(FPOpcode != ISD::DELETED_NODE &&
24485 "Unexpected input node for FP logic conversion");
24487 EVT VT = N->getValueType(0);
24488 SDValue N0 = N->getOperand(0);
24489 SDValue N1 = N->getOperand(1);
24491 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24492 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24493 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24494 SDValue N00 = N0.getOperand(0);
24495 SDValue N10 = N1.getOperand(0);
24496 EVT N00Type = N00.getValueType();
24497 EVT N10Type = N10.getValueType();
24498 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24499 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24500 return DAG.getBitcast(VT, FPLogic);
24506 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24507 TargetLowering::DAGCombinerInfo &DCI,
24508 const X86Subtarget *Subtarget) {
24509 if (DCI.isBeforeLegalizeOps())
24512 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24515 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24518 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24521 EVT VT = N->getValueType(0);
24522 SDValue N0 = N->getOperand(0);
24523 SDValue N1 = N->getOperand(1);
24526 // Create BEXTR instructions
24527 // BEXTR is ((X >> imm) & (2**size-1))
24528 if (VT == MVT::i32 || VT == MVT::i64) {
24529 // Check for BEXTR.
24530 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24531 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24532 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24533 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24534 if (MaskNode && ShiftNode) {
24535 uint64_t Mask = MaskNode->getZExtValue();
24536 uint64_t Shift = ShiftNode->getZExtValue();
24537 if (isMask_64(Mask)) {
24538 uint64_t MaskSize = countPopulation(Mask);
24539 if (Shift + MaskSize <= VT.getSizeInBits())
24540 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24541 DAG.getConstant(Shift | (MaskSize << 8), DL,
24550 // Want to form ANDNP nodes:
24551 // 1) In the hopes of then easily combining them with OR and AND nodes
24552 // to form PBLEND/PSIGN.
24553 // 2) To match ANDN packed intrinsics
24554 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24557 // Check LHS for vnot
24558 if (N0.getOpcode() == ISD::XOR &&
24559 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24560 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24561 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24563 // Check RHS for vnot
24564 if (N1.getOpcode() == ISD::XOR &&
24565 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24566 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24567 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24572 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24573 TargetLowering::DAGCombinerInfo &DCI,
24574 const X86Subtarget *Subtarget) {
24575 if (DCI.isBeforeLegalizeOps())
24578 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24581 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24584 SDValue N0 = N->getOperand(0);
24585 SDValue N1 = N->getOperand(1);
24586 EVT VT = N->getValueType(0);
24588 // look for psign/blend
24589 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24590 if (!Subtarget->hasSSSE3() ||
24591 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24594 // Canonicalize pandn to RHS
24595 if (N0.getOpcode() == X86ISD::ANDNP)
24597 // or (and (m, y), (pandn m, x))
24598 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24599 SDValue Mask = N1.getOperand(0);
24600 SDValue X = N1.getOperand(1);
24602 if (N0.getOperand(0) == Mask)
24603 Y = N0.getOperand(1);
24604 if (N0.getOperand(1) == Mask)
24605 Y = N0.getOperand(0);
24607 // Check to see if the mask appeared in both the AND and ANDNP and
24611 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24612 // Look through mask bitcast.
24613 if (Mask.getOpcode() == ISD::BITCAST)
24614 Mask = Mask.getOperand(0);
24615 if (X.getOpcode() == ISD::BITCAST)
24616 X = X.getOperand(0);
24617 if (Y.getOpcode() == ISD::BITCAST)
24618 Y = Y.getOperand(0);
24620 EVT MaskVT = Mask.getValueType();
24622 // Validate that the Mask operand is a vector sra node.
24623 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24624 // there is no psrai.b
24625 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24626 unsigned SraAmt = ~0;
24627 if (Mask.getOpcode() == ISD::SRA) {
24628 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24629 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24630 SraAmt = AmtConst->getZExtValue();
24631 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24632 SDValue SraC = Mask.getOperand(1);
24633 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24635 if ((SraAmt + 1) != EltBits)
24640 // Now we know we at least have a plendvb with the mask val. See if
24641 // we can form a psignb/w/d.
24642 // psign = x.type == y.type == mask.type && y = sub(0, x);
24643 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24644 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24645 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24646 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24647 "Unsupported VT for PSIGN");
24648 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24649 return DAG.getBitcast(VT, Mask);
24651 // PBLENDVB only available on SSE 4.1
24652 if (!Subtarget->hasSSE41())
24655 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24657 X = DAG.getBitcast(BlendVT, X);
24658 Y = DAG.getBitcast(BlendVT, Y);
24659 Mask = DAG.getBitcast(BlendVT, Mask);
24660 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24661 return DAG.getBitcast(VT, Mask);
24665 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24668 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24669 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24671 // SHLD/SHRD instructions have lower register pressure, but on some
24672 // platforms they have higher latency than the equivalent
24673 // series of shifts/or that would otherwise be generated.
24674 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24675 // have higher latencies and we are not optimizing for size.
24676 if (!OptForSize && Subtarget->isSHLDSlow())
24679 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24681 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24683 if (!N0.hasOneUse() || !N1.hasOneUse())
24686 SDValue ShAmt0 = N0.getOperand(1);
24687 if (ShAmt0.getValueType() != MVT::i8)
24689 SDValue ShAmt1 = N1.getOperand(1);
24690 if (ShAmt1.getValueType() != MVT::i8)
24692 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24693 ShAmt0 = ShAmt0.getOperand(0);
24694 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24695 ShAmt1 = ShAmt1.getOperand(0);
24698 unsigned Opc = X86ISD::SHLD;
24699 SDValue Op0 = N0.getOperand(0);
24700 SDValue Op1 = N1.getOperand(0);
24701 if (ShAmt0.getOpcode() == ISD::SUB) {
24702 Opc = X86ISD::SHRD;
24703 std::swap(Op0, Op1);
24704 std::swap(ShAmt0, ShAmt1);
24707 unsigned Bits = VT.getSizeInBits();
24708 if (ShAmt1.getOpcode() == ISD::SUB) {
24709 SDValue Sum = ShAmt1.getOperand(0);
24710 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24711 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24712 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24713 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24714 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24715 return DAG.getNode(Opc, DL, VT,
24717 DAG.getNode(ISD::TRUNCATE, DL,
24720 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24721 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24723 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24724 return DAG.getNode(Opc, DL, VT,
24725 N0.getOperand(0), N1.getOperand(0),
24726 DAG.getNode(ISD::TRUNCATE, DL,
24733 // Generate NEG and CMOV for integer abs.
24734 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24735 EVT VT = N->getValueType(0);
24737 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24738 // 8-bit integer abs to NEG and CMOV.
24739 if (VT.isInteger() && VT.getSizeInBits() == 8)
24742 SDValue N0 = N->getOperand(0);
24743 SDValue N1 = N->getOperand(1);
24746 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24747 // and change it to SUB and CMOV.
24748 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24749 N0.getOpcode() == ISD::ADD &&
24750 N0.getOperand(1) == N1 &&
24751 N1.getOpcode() == ISD::SRA &&
24752 N1.getOperand(0) == N0.getOperand(0))
24753 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24754 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24755 // Generate SUB & CMOV.
24756 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24757 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24759 SDValue Ops[] = { N0.getOperand(0), Neg,
24760 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24761 SDValue(Neg.getNode(), 1) };
24762 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24767 // Try to turn tests against the signbit in the form of:
24768 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24771 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24772 // This is only worth doing if the output type is i8.
24773 if (N->getValueType(0) != MVT::i8)
24776 SDValue N0 = N->getOperand(0);
24777 SDValue N1 = N->getOperand(1);
24779 // We should be performing an xor against a truncated shift.
24780 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24783 // Make sure we are performing an xor against one.
24784 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24787 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24788 SDValue Shift = N0.getOperand(0);
24789 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24792 // Make sure we are truncating from one of i16, i32 or i64.
24793 EVT ShiftTy = Shift.getValueType();
24794 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24797 // Make sure the shift amount extracts the sign bit.
24798 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24799 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24802 // Create a greater-than comparison against -1.
24803 // N.B. Using SETGE against 0 works but we want a canonical looking
24804 // comparison, using SETGT matches up with what TranslateX86CC.
24806 SDValue ShiftOp = Shift.getOperand(0);
24807 EVT ShiftOpTy = ShiftOp.getValueType();
24808 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24809 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24813 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24814 TargetLowering::DAGCombinerInfo &DCI,
24815 const X86Subtarget *Subtarget) {
24816 if (DCI.isBeforeLegalizeOps())
24819 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24822 if (Subtarget->hasCMov())
24823 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24826 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24832 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24833 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24834 TargetLowering::DAGCombinerInfo &DCI,
24835 const X86Subtarget *Subtarget) {
24836 LoadSDNode *Ld = cast<LoadSDNode>(N);
24837 EVT RegVT = Ld->getValueType(0);
24838 EVT MemVT = Ld->getMemoryVT();
24840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24842 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24843 // into two 16-byte operations.
24844 ISD::LoadExtType Ext = Ld->getExtensionType();
24846 unsigned AddressSpace = Ld->getAddressSpace();
24847 unsigned Alignment = Ld->getAlignment();
24848 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24849 Ext == ISD::NON_EXTLOAD &&
24850 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24851 AddressSpace, Alignment, &Fast) && !Fast) {
24852 unsigned NumElems = RegVT.getVectorNumElements();
24856 SDValue Ptr = Ld->getBasePtr();
24857 SDValue Increment =
24858 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24860 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24862 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24863 Ld->getPointerInfo(), Ld->isVolatile(),
24864 Ld->isNonTemporal(), Ld->isInvariant(),
24866 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24867 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24868 Ld->getPointerInfo(), Ld->isVolatile(),
24869 Ld->isNonTemporal(), Ld->isInvariant(),
24870 std::min(16U, Alignment));
24871 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24873 Load2.getValue(1));
24875 SDValue NewVec = DAG.getUNDEF(RegVT);
24876 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24877 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24878 return DCI.CombineTo(N, NewVec, TF, true);
24884 /// PerformMLOADCombine - Resolve extending loads
24885 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24886 TargetLowering::DAGCombinerInfo &DCI,
24887 const X86Subtarget *Subtarget) {
24888 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24889 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24892 EVT VT = Mld->getValueType(0);
24893 unsigned NumElems = VT.getVectorNumElements();
24894 EVT LdVT = Mld->getMemoryVT();
24897 assert(LdVT != VT && "Cannot extend to the same type");
24898 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24899 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24900 // From, To sizes and ElemCount must be pow of two
24901 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24902 "Unexpected size for extending masked load");
24904 unsigned SizeRatio = ToSz / FromSz;
24905 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24907 // Create a type on which we perform the shuffle
24908 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24909 LdVT.getScalarType(), NumElems*SizeRatio);
24910 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24912 // Convert Src0 value
24913 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24914 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24915 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24916 for (unsigned i = 0; i != NumElems; ++i)
24917 ShuffleVec[i] = i * SizeRatio;
24919 // Can't shuffle using an illegal type.
24920 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24921 "WideVecVT should be legal");
24922 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24923 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24925 // Prepare the new mask
24927 SDValue Mask = Mld->getMask();
24928 if (Mask.getValueType() == VT) {
24929 // Mask and original value have the same type
24930 NewMask = DAG.getBitcast(WideVecVT, Mask);
24931 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24932 for (unsigned i = 0; i != NumElems; ++i)
24933 ShuffleVec[i] = i * SizeRatio;
24934 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24935 ShuffleVec[i] = NumElems*SizeRatio;
24936 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24937 DAG.getConstant(0, dl, WideVecVT),
24941 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24942 unsigned WidenNumElts = NumElems*SizeRatio;
24943 unsigned MaskNumElts = VT.getVectorNumElements();
24944 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24947 unsigned NumConcat = WidenNumElts / MaskNumElts;
24948 SmallVector<SDValue, 16> Ops(NumConcat);
24949 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24951 for (unsigned i = 1; i != NumConcat; ++i)
24954 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24957 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24958 Mld->getBasePtr(), NewMask, WideSrc0,
24959 Mld->getMemoryVT(), Mld->getMemOperand(),
24961 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24962 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24964 /// PerformMSTORECombine - Resolve truncating stores
24965 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24966 const X86Subtarget *Subtarget) {
24967 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24968 if (!Mst->isTruncatingStore())
24971 EVT VT = Mst->getValue().getValueType();
24972 unsigned NumElems = VT.getVectorNumElements();
24973 EVT StVT = Mst->getMemoryVT();
24976 assert(StVT != VT && "Cannot truncate to the same type");
24977 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24978 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24980 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24982 // The truncating store is legal in some cases. For example
24983 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24984 // are designated for truncate store.
24985 // In this case we don't need any further transformations.
24986 if (TLI.isTruncStoreLegal(VT, StVT))
24989 // From, To sizes and ElemCount must be pow of two
24990 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24991 "Unexpected size for truncating masked store");
24992 // We are going to use the original vector elt for storing.
24993 // Accumulated smaller vector elements must be a multiple of the store size.
24994 assert (((NumElems * FromSz) % ToSz) == 0 &&
24995 "Unexpected ratio for truncating masked store");
24997 unsigned SizeRatio = FromSz / ToSz;
24998 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25000 // Create a type on which we perform the shuffle
25001 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25002 StVT.getScalarType(), NumElems*SizeRatio);
25004 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25006 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25007 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25008 for (unsigned i = 0; i != NumElems; ++i)
25009 ShuffleVec[i] = i * SizeRatio;
25011 // Can't shuffle using an illegal type.
25012 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25013 "WideVecVT should be legal");
25015 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25016 DAG.getUNDEF(WideVecVT),
25020 SDValue Mask = Mst->getMask();
25021 if (Mask.getValueType() == VT) {
25022 // Mask and original value have the same type
25023 NewMask = DAG.getBitcast(WideVecVT, Mask);
25024 for (unsigned i = 0; i != NumElems; ++i)
25025 ShuffleVec[i] = i * SizeRatio;
25026 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25027 ShuffleVec[i] = NumElems*SizeRatio;
25028 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25029 DAG.getConstant(0, dl, WideVecVT),
25033 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25034 unsigned WidenNumElts = NumElems*SizeRatio;
25035 unsigned MaskNumElts = VT.getVectorNumElements();
25036 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25039 unsigned NumConcat = WidenNumElts / MaskNumElts;
25040 SmallVector<SDValue, 16> Ops(NumConcat);
25041 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25043 for (unsigned i = 1; i != NumConcat; ++i)
25046 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25049 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25050 NewMask, StVT, Mst->getMemOperand(), false);
25052 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25053 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25054 const X86Subtarget *Subtarget) {
25055 StoreSDNode *St = cast<StoreSDNode>(N);
25056 EVT VT = St->getValue().getValueType();
25057 EVT StVT = St->getMemoryVT();
25059 SDValue StoredVal = St->getOperand(1);
25060 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25062 // If we are saving a concatenation of two XMM registers and 32-byte stores
25063 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25065 unsigned AddressSpace = St->getAddressSpace();
25066 unsigned Alignment = St->getAlignment();
25067 if (VT.is256BitVector() && StVT == VT &&
25068 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25069 AddressSpace, Alignment, &Fast) && !Fast) {
25070 unsigned NumElems = VT.getVectorNumElements();
25074 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25075 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25078 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25079 SDValue Ptr0 = St->getBasePtr();
25080 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25082 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25083 St->getPointerInfo(), St->isVolatile(),
25084 St->isNonTemporal(), Alignment);
25085 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25086 St->getPointerInfo(), St->isVolatile(),
25087 St->isNonTemporal(),
25088 std::min(16U, Alignment));
25089 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25092 // Optimize trunc store (of multiple scalars) to shuffle and store.
25093 // First, pack all of the elements in one place. Next, store to memory
25094 // in fewer chunks.
25095 if (St->isTruncatingStore() && VT.isVector()) {
25096 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25097 unsigned NumElems = VT.getVectorNumElements();
25098 assert(StVT != VT && "Cannot truncate to the same type");
25099 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25100 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25102 // The truncating store is legal in some cases. For example
25103 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25104 // are designated for truncate store.
25105 // In this case we don't need any further transformations.
25106 if (TLI.isTruncStoreLegal(VT, StVT))
25109 // From, To sizes and ElemCount must be pow of two
25110 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25111 // We are going to use the original vector elt for storing.
25112 // Accumulated smaller vector elements must be a multiple of the store size.
25113 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25115 unsigned SizeRatio = FromSz / ToSz;
25117 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25119 // Create a type on which we perform the shuffle
25120 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25121 StVT.getScalarType(), NumElems*SizeRatio);
25123 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25125 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25126 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25127 for (unsigned i = 0; i != NumElems; ++i)
25128 ShuffleVec[i] = i * SizeRatio;
25130 // Can't shuffle using an illegal type.
25131 if (!TLI.isTypeLegal(WideVecVT))
25134 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25135 DAG.getUNDEF(WideVecVT),
25137 // At this point all of the data is stored at the bottom of the
25138 // register. We now need to save it to mem.
25140 // Find the largest store unit
25141 MVT StoreType = MVT::i8;
25142 for (MVT Tp : MVT::integer_valuetypes()) {
25143 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25147 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25148 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25149 (64 <= NumElems * ToSz))
25150 StoreType = MVT::f64;
25152 // Bitcast the original vector into a vector of store-size units
25153 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25154 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25155 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25156 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25157 SmallVector<SDValue, 8> Chains;
25158 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25159 TLI.getPointerTy(DAG.getDataLayout()));
25160 SDValue Ptr = St->getBasePtr();
25162 // Perform one or more big stores into memory.
25163 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25164 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25165 StoreType, ShuffWide,
25166 DAG.getIntPtrConstant(i, dl));
25167 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25168 St->getPointerInfo(), St->isVolatile(),
25169 St->isNonTemporal(), St->getAlignment());
25170 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25171 Chains.push_back(Ch);
25174 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25177 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25178 // the FP state in cases where an emms may be missing.
25179 // A preferable solution to the general problem is to figure out the right
25180 // places to insert EMMS. This qualifies as a quick hack.
25182 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25183 if (VT.getSizeInBits() != 64)
25186 const Function *F = DAG.getMachineFunction().getFunction();
25187 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25189 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25190 if ((VT.isVector() ||
25191 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25192 isa<LoadSDNode>(St->getValue()) &&
25193 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25194 St->getChain().hasOneUse() && !St->isVolatile()) {
25195 SDNode* LdVal = St->getValue().getNode();
25196 LoadSDNode *Ld = nullptr;
25197 int TokenFactorIndex = -1;
25198 SmallVector<SDValue, 8> Ops;
25199 SDNode* ChainVal = St->getChain().getNode();
25200 // Must be a store of a load. We currently handle two cases: the load
25201 // is a direct child, and it's under an intervening TokenFactor. It is
25202 // possible to dig deeper under nested TokenFactors.
25203 if (ChainVal == LdVal)
25204 Ld = cast<LoadSDNode>(St->getChain());
25205 else if (St->getValue().hasOneUse() &&
25206 ChainVal->getOpcode() == ISD::TokenFactor) {
25207 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25208 if (ChainVal->getOperand(i).getNode() == LdVal) {
25209 TokenFactorIndex = i;
25210 Ld = cast<LoadSDNode>(St->getValue());
25212 Ops.push_back(ChainVal->getOperand(i));
25216 if (!Ld || !ISD::isNormalLoad(Ld))
25219 // If this is not the MMX case, i.e. we are just turning i64 load/store
25220 // into f64 load/store, avoid the transformation if there are multiple
25221 // uses of the loaded value.
25222 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25227 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25228 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25230 if (Subtarget->is64Bit() || F64IsLegal) {
25231 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25232 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25233 Ld->getPointerInfo(), Ld->isVolatile(),
25234 Ld->isNonTemporal(), Ld->isInvariant(),
25235 Ld->getAlignment());
25236 SDValue NewChain = NewLd.getValue(1);
25237 if (TokenFactorIndex != -1) {
25238 Ops.push_back(NewChain);
25239 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25241 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25242 St->getPointerInfo(),
25243 St->isVolatile(), St->isNonTemporal(),
25244 St->getAlignment());
25247 // Otherwise, lower to two pairs of 32-bit loads / stores.
25248 SDValue LoAddr = Ld->getBasePtr();
25249 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25250 DAG.getConstant(4, LdDL, MVT::i32));
25252 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25253 Ld->getPointerInfo(),
25254 Ld->isVolatile(), Ld->isNonTemporal(),
25255 Ld->isInvariant(), Ld->getAlignment());
25256 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25257 Ld->getPointerInfo().getWithOffset(4),
25258 Ld->isVolatile(), Ld->isNonTemporal(),
25260 MinAlign(Ld->getAlignment(), 4));
25262 SDValue NewChain = LoLd.getValue(1);
25263 if (TokenFactorIndex != -1) {
25264 Ops.push_back(LoLd);
25265 Ops.push_back(HiLd);
25266 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25269 LoAddr = St->getBasePtr();
25270 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25271 DAG.getConstant(4, StDL, MVT::i32));
25273 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25274 St->getPointerInfo(),
25275 St->isVolatile(), St->isNonTemporal(),
25276 St->getAlignment());
25277 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25278 St->getPointerInfo().getWithOffset(4),
25280 St->isNonTemporal(),
25281 MinAlign(St->getAlignment(), 4));
25282 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25285 // This is similar to the above case, but here we handle a scalar 64-bit
25286 // integer store that is extracted from a vector on a 32-bit target.
25287 // If we have SSE2, then we can treat it like a floating-point double
25288 // to get past legalization. The execution dependencies fixup pass will
25289 // choose the optimal machine instruction for the store if this really is
25290 // an integer or v2f32 rather than an f64.
25291 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25292 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25293 SDValue OldExtract = St->getOperand(1);
25294 SDValue ExtOp0 = OldExtract.getOperand(0);
25295 unsigned VecSize = ExtOp0.getValueSizeInBits();
25296 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25297 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25298 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25299 BitCast, OldExtract.getOperand(1));
25300 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25301 St->getPointerInfo(), St->isVolatile(),
25302 St->isNonTemporal(), St->getAlignment());
25308 /// Return 'true' if this vector operation is "horizontal"
25309 /// and return the operands for the horizontal operation in LHS and RHS. A
25310 /// horizontal operation performs the binary operation on successive elements
25311 /// of its first operand, then on successive elements of its second operand,
25312 /// returning the resulting values in a vector. For example, if
25313 /// A = < float a0, float a1, float a2, float a3 >
25315 /// B = < float b0, float b1, float b2, float b3 >
25316 /// then the result of doing a horizontal operation on A and B is
25317 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25318 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25319 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25320 /// set to A, RHS to B, and the routine returns 'true'.
25321 /// Note that the binary operation should have the property that if one of the
25322 /// operands is UNDEF then the result is UNDEF.
25323 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25324 // Look for the following pattern: if
25325 // A = < float a0, float a1, float a2, float a3 >
25326 // B = < float b0, float b1, float b2, float b3 >
25328 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25329 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25330 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25331 // which is A horizontal-op B.
25333 // At least one of the operands should be a vector shuffle.
25334 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25335 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25338 MVT VT = LHS.getSimpleValueType();
25340 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25341 "Unsupported vector type for horizontal add/sub");
25343 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25344 // operate independently on 128-bit lanes.
25345 unsigned NumElts = VT.getVectorNumElements();
25346 unsigned NumLanes = VT.getSizeInBits()/128;
25347 unsigned NumLaneElts = NumElts / NumLanes;
25348 assert((NumLaneElts % 2 == 0) &&
25349 "Vector type should have an even number of elements in each lane");
25350 unsigned HalfLaneElts = NumLaneElts/2;
25352 // View LHS in the form
25353 // LHS = VECTOR_SHUFFLE A, B, LMask
25354 // If LHS is not a shuffle then pretend it is the shuffle
25355 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25356 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25359 SmallVector<int, 16> LMask(NumElts);
25360 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25361 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25362 A = LHS.getOperand(0);
25363 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25364 B = LHS.getOperand(1);
25365 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25366 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25368 if (LHS.getOpcode() != ISD::UNDEF)
25370 for (unsigned i = 0; i != NumElts; ++i)
25374 // Likewise, view RHS in the form
25375 // RHS = VECTOR_SHUFFLE C, D, RMask
25377 SmallVector<int, 16> RMask(NumElts);
25378 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25379 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25380 C = RHS.getOperand(0);
25381 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25382 D = RHS.getOperand(1);
25383 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25384 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25386 if (RHS.getOpcode() != ISD::UNDEF)
25388 for (unsigned i = 0; i != NumElts; ++i)
25392 // Check that the shuffles are both shuffling the same vectors.
25393 if (!(A == C && B == D) && !(A == D && B == C))
25396 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25397 if (!A.getNode() && !B.getNode())
25400 // If A and B occur in reverse order in RHS, then "swap" them (which means
25401 // rewriting the mask).
25403 ShuffleVectorSDNode::commuteMask(RMask);
25405 // At this point LHS and RHS are equivalent to
25406 // LHS = VECTOR_SHUFFLE A, B, LMask
25407 // RHS = VECTOR_SHUFFLE A, B, RMask
25408 // Check that the masks correspond to performing a horizontal operation.
25409 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25410 for (unsigned i = 0; i != NumLaneElts; ++i) {
25411 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25413 // Ignore any UNDEF components.
25414 if (LIdx < 0 || RIdx < 0 ||
25415 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25416 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25419 // Check that successive elements are being operated on. If not, this is
25420 // not a horizontal operation.
25421 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25422 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25423 if (!(LIdx == Index && RIdx == Index + 1) &&
25424 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25429 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25430 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25434 /// Do target-specific dag combines on floating point adds.
25435 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25436 const X86Subtarget *Subtarget) {
25437 EVT VT = N->getValueType(0);
25438 SDValue LHS = N->getOperand(0);
25439 SDValue RHS = N->getOperand(1);
25441 // Try to synthesize horizontal adds from adds of shuffles.
25442 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25443 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25444 isHorizontalBinOp(LHS, RHS, true))
25445 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25449 /// Do target-specific dag combines on floating point subs.
25450 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25451 const X86Subtarget *Subtarget) {
25452 EVT VT = N->getValueType(0);
25453 SDValue LHS = N->getOperand(0);
25454 SDValue RHS = N->getOperand(1);
25456 // Try to synthesize horizontal subs from subs of shuffles.
25457 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25458 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25459 isHorizontalBinOp(LHS, RHS, false))
25460 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25464 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25465 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25466 const X86Subtarget *Subtarget) {
25467 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25469 // F[X]OR(0.0, x) -> x
25470 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25471 if (C->getValueAPF().isPosZero())
25472 return N->getOperand(1);
25474 // F[X]OR(x, 0.0) -> x
25475 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25476 if (C->getValueAPF().isPosZero())
25477 return N->getOperand(0);
25479 EVT VT = N->getValueType(0);
25480 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25482 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25483 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25485 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25486 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25487 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25488 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25489 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25494 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25495 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25496 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25498 // Only perform optimizations if UnsafeMath is used.
25499 if (!DAG.getTarget().Options.UnsafeFPMath)
25502 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25503 // into FMINC and FMAXC, which are Commutative operations.
25504 unsigned NewOp = 0;
25505 switch (N->getOpcode()) {
25506 default: llvm_unreachable("unknown opcode");
25507 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25508 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25511 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25512 N->getOperand(0), N->getOperand(1));
25515 /// Do target-specific dag combines on X86ISD::FAND nodes.
25516 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25517 // FAND(0.0, x) -> 0.0
25518 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25519 if (C->getValueAPF().isPosZero())
25520 return N->getOperand(0);
25522 // FAND(x, 0.0) -> 0.0
25523 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25524 if (C->getValueAPF().isPosZero())
25525 return N->getOperand(1);
25530 /// Do target-specific dag combines on X86ISD::FANDN nodes
25531 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25532 // FANDN(0.0, x) -> x
25533 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25534 if (C->getValueAPF().isPosZero())
25535 return N->getOperand(1);
25537 // FANDN(x, 0.0) -> 0.0
25538 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25539 if (C->getValueAPF().isPosZero())
25540 return N->getOperand(1);
25545 static SDValue PerformBTCombine(SDNode *N,
25547 TargetLowering::DAGCombinerInfo &DCI) {
25548 // BT ignores high bits in the bit index operand.
25549 SDValue Op1 = N->getOperand(1);
25550 if (Op1.hasOneUse()) {
25551 unsigned BitWidth = Op1.getValueSizeInBits();
25552 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25553 APInt KnownZero, KnownOne;
25554 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25555 !DCI.isBeforeLegalizeOps());
25556 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25557 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25558 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25559 DCI.CommitTargetLoweringOpt(TLO);
25564 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25565 SDValue Op = N->getOperand(0);
25566 if (Op.getOpcode() == ISD::BITCAST)
25567 Op = Op.getOperand(0);
25568 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25569 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25570 VT.getVectorElementType().getSizeInBits() ==
25571 OpVT.getVectorElementType().getSizeInBits()) {
25572 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25577 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25578 const X86Subtarget *Subtarget) {
25579 EVT VT = N->getValueType(0);
25580 if (!VT.isVector())
25583 SDValue N0 = N->getOperand(0);
25584 SDValue N1 = N->getOperand(1);
25585 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25588 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25589 // both SSE and AVX2 since there is no sign-extended shift right
25590 // operation on a vector with 64-bit elements.
25591 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25592 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25593 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25594 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25595 SDValue N00 = N0.getOperand(0);
25597 // EXTLOAD has a better solution on AVX2,
25598 // it may be replaced with X86ISD::VSEXT node.
25599 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25600 if (!ISD::isNormalLoad(N00.getNode()))
25603 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25604 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25606 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25612 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25613 TargetLowering::DAGCombinerInfo &DCI,
25614 const X86Subtarget *Subtarget) {
25615 SDValue N0 = N->getOperand(0);
25616 EVT VT = N->getValueType(0);
25617 EVT SVT = VT.getScalarType();
25618 EVT InVT = N0.getValueType();
25619 EVT InSVT = InVT.getScalarType();
25622 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25623 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25624 // This exposes the sext to the sdivrem lowering, so that it directly extends
25625 // from AH (which we otherwise need to do contortions to access).
25626 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25627 InVT == MVT::i8 && VT == MVT::i32) {
25628 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25629 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25630 N0.getOperand(0), N0.getOperand(1));
25631 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25632 return R.getValue(1);
25635 if (!DCI.isBeforeLegalizeOps()) {
25636 if (InVT == MVT::i1) {
25637 SDValue Zero = DAG.getConstant(0, DL, VT);
25639 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25640 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25645 if (VT.isVector() && Subtarget->hasSSE2()) {
25646 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25647 EVT InVT = N.getValueType();
25648 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25649 Size / InVT.getScalarSizeInBits());
25650 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25651 DAG.getUNDEF(InVT));
25653 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25656 // If target-size is less than 128-bits, extend to a type that would extend
25657 // to 128 bits, extend that and extract the original target vector.
25658 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25659 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25660 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25661 unsigned Scale = 128 / VT.getSizeInBits();
25663 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25664 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25665 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25666 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25667 DAG.getIntPtrConstant(0, DL));
25670 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25671 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25672 if (VT.getSizeInBits() == 128 &&
25673 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25674 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25675 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25676 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25679 // On pre-AVX2 targets, split into 128-bit nodes of
25680 // ISD::SIGN_EXTEND_VECTOR_INREG.
25681 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25682 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25683 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25684 unsigned NumVecs = VT.getSizeInBits() / 128;
25685 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25686 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25687 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25689 SmallVector<SDValue, 8> Opnds;
25690 for (unsigned i = 0, Offset = 0; i != NumVecs;
25691 ++i, Offset += NumSubElts) {
25692 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25693 DAG.getIntPtrConstant(Offset, DL));
25694 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25695 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25696 Opnds.push_back(SrcVec);
25698 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25702 if (!Subtarget->hasFp256())
25705 if (VT.isVector() && VT.getSizeInBits() == 256)
25706 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25712 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25713 const X86Subtarget* Subtarget) {
25715 EVT VT = N->getValueType(0);
25717 // Let legalize expand this if it isn't a legal type yet.
25718 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25721 EVT ScalarVT = VT.getScalarType();
25722 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25723 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25724 !Subtarget->hasAVX512()))
25727 SDValue A = N->getOperand(0);
25728 SDValue B = N->getOperand(1);
25729 SDValue C = N->getOperand(2);
25731 bool NegA = (A.getOpcode() == ISD::FNEG);
25732 bool NegB = (B.getOpcode() == ISD::FNEG);
25733 bool NegC = (C.getOpcode() == ISD::FNEG);
25735 // Negative multiplication when NegA xor NegB
25736 bool NegMul = (NegA != NegB);
25738 A = A.getOperand(0);
25740 B = B.getOperand(0);
25742 C = C.getOperand(0);
25746 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25748 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25750 return DAG.getNode(Opcode, dl, VT, A, B, C);
25753 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25754 TargetLowering::DAGCombinerInfo &DCI,
25755 const X86Subtarget *Subtarget) {
25756 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25757 // (and (i32 x86isd::setcc_carry), 1)
25758 // This eliminates the zext. This transformation is necessary because
25759 // ISD::SETCC is always legalized to i8.
25761 SDValue N0 = N->getOperand(0);
25762 EVT VT = N->getValueType(0);
25764 if (N0.getOpcode() == ISD::AND &&
25766 N0.getOperand(0).hasOneUse()) {
25767 SDValue N00 = N0.getOperand(0);
25768 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25769 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25770 if (!C || C->getZExtValue() != 1)
25772 return DAG.getNode(ISD::AND, dl, VT,
25773 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25774 N00.getOperand(0), N00.getOperand(1)),
25775 DAG.getConstant(1, dl, VT));
25779 if (N0.getOpcode() == ISD::TRUNCATE &&
25781 N0.getOperand(0).hasOneUse()) {
25782 SDValue N00 = N0.getOperand(0);
25783 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25784 return DAG.getNode(ISD::AND, dl, VT,
25785 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25786 N00.getOperand(0), N00.getOperand(1)),
25787 DAG.getConstant(1, dl, VT));
25791 if (VT.is256BitVector())
25792 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25795 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25796 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25797 // This exposes the zext to the udivrem lowering, so that it directly extends
25798 // from AH (which we otherwise need to do contortions to access).
25799 if (N0.getOpcode() == ISD::UDIVREM &&
25800 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25801 (VT == MVT::i32 || VT == MVT::i64)) {
25802 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25803 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25804 N0.getOperand(0), N0.getOperand(1));
25805 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25806 return R.getValue(1);
25812 // Optimize x == -y --> x+y == 0
25813 // x != -y --> x+y != 0
25814 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25815 const X86Subtarget* Subtarget) {
25816 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25817 SDValue LHS = N->getOperand(0);
25818 SDValue RHS = N->getOperand(1);
25819 EVT VT = N->getValueType(0);
25822 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25823 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25824 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25825 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25826 LHS.getOperand(1));
25827 return DAG.getSetCC(DL, N->getValueType(0), addV,
25828 DAG.getConstant(0, DL, addV.getValueType()), CC);
25830 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25832 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25833 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25834 RHS.getOperand(1));
25835 return DAG.getSetCC(DL, N->getValueType(0), addV,
25836 DAG.getConstant(0, DL, addV.getValueType()), CC);
25839 if (VT.getScalarType() == MVT::i1 &&
25840 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25842 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25843 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25844 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25846 if (!IsSEXT0 || !IsVZero1) {
25847 // Swap the operands and update the condition code.
25848 std::swap(LHS, RHS);
25849 CC = ISD::getSetCCSwappedOperands(CC);
25851 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25852 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25853 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25856 if (IsSEXT0 && IsVZero1) {
25857 assert(VT == LHS.getOperand(0).getValueType() &&
25858 "Uexpected operand type");
25859 if (CC == ISD::SETGT)
25860 return DAG.getConstant(0, DL, VT);
25861 if (CC == ISD::SETLE)
25862 return DAG.getConstant(1, DL, VT);
25863 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25864 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25866 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25867 "Unexpected condition code!");
25868 return LHS.getOperand(0);
25875 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25876 SelectionDAG &DAG) {
25878 MVT VT = Load->getSimpleValueType(0);
25879 MVT EVT = VT.getVectorElementType();
25880 SDValue Addr = Load->getOperand(1);
25881 SDValue NewAddr = DAG.getNode(
25882 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25883 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25884 Addr.getSimpleValueType()));
25887 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25888 DAG.getMachineFunction().getMachineMemOperand(
25889 Load->getMemOperand(), 0, EVT.getStoreSize()));
25893 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25894 const X86Subtarget *Subtarget) {
25896 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25897 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25898 "X86insertps is only defined for v4x32");
25900 SDValue Ld = N->getOperand(1);
25901 if (MayFoldLoad(Ld)) {
25902 // Extract the countS bits from the immediate so we can get the proper
25903 // address when narrowing the vector load to a specific element.
25904 // When the second source op is a memory address, insertps doesn't use
25905 // countS and just gets an f32 from that address.
25906 unsigned DestIndex =
25907 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25909 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25911 // Create this as a scalar to vector to match the instruction pattern.
25912 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25913 // countS bits are ignored when loading from memory on insertps, which
25914 // means we don't need to explicitly set them to 0.
25915 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25916 LoadScalarToVector, N->getOperand(2));
25921 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25922 SDValue V0 = N->getOperand(0);
25923 SDValue V1 = N->getOperand(1);
25925 EVT VT = N->getValueType(0);
25927 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25928 // operands and changing the mask to 1. This saves us a bunch of
25929 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25930 // x86InstrInfo knows how to commute this back after instruction selection
25931 // if it would help register allocation.
25933 // TODO: If optimizing for size or a processor that doesn't suffer from
25934 // partial register update stalls, this should be transformed into a MOVSD
25935 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
25937 if (VT == MVT::v2f64)
25938 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
25939 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
25940 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
25941 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
25947 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25948 // as "sbb reg,reg", since it can be extended without zext and produces
25949 // an all-ones bit which is more useful than 0/1 in some cases.
25950 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25953 return DAG.getNode(ISD::AND, DL, VT,
25954 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25955 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25957 DAG.getConstant(1, DL, VT));
25958 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25959 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25960 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25961 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25965 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25966 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25967 TargetLowering::DAGCombinerInfo &DCI,
25968 const X86Subtarget *Subtarget) {
25970 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25971 SDValue EFLAGS = N->getOperand(1);
25973 if (CC == X86::COND_A) {
25974 // Try to convert COND_A into COND_B in an attempt to facilitate
25975 // materializing "setb reg".
25977 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25978 // cannot take an immediate as its first operand.
25980 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25981 EFLAGS.getValueType().isInteger() &&
25982 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25983 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25984 EFLAGS.getNode()->getVTList(),
25985 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25986 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25987 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25991 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25992 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25994 if (CC == X86::COND_B)
25995 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25997 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25998 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25999 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26005 // Optimize branch condition evaluation.
26007 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26008 TargetLowering::DAGCombinerInfo &DCI,
26009 const X86Subtarget *Subtarget) {
26011 SDValue Chain = N->getOperand(0);
26012 SDValue Dest = N->getOperand(1);
26013 SDValue EFLAGS = N->getOperand(3);
26014 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26016 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26017 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26018 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26025 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26026 SelectionDAG &DAG) {
26027 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26028 // optimize away operation when it's from a constant.
26030 // The general transformation is:
26031 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26032 // AND(VECTOR_CMP(x,y), constant2)
26033 // constant2 = UNARYOP(constant)
26035 // Early exit if this isn't a vector operation, the operand of the
26036 // unary operation isn't a bitwise AND, or if the sizes of the operations
26037 // aren't the same.
26038 EVT VT = N->getValueType(0);
26039 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26040 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26041 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26044 // Now check that the other operand of the AND is a constant. We could
26045 // make the transformation for non-constant splats as well, but it's unclear
26046 // that would be a benefit as it would not eliminate any operations, just
26047 // perform one more step in scalar code before moving to the vector unit.
26048 if (BuildVectorSDNode *BV =
26049 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26050 // Bail out if the vector isn't a constant.
26051 if (!BV->isConstant())
26054 // Everything checks out. Build up the new and improved node.
26056 EVT IntVT = BV->getValueType(0);
26057 // Create a new constant of the appropriate type for the transformed
26059 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26060 // The AND node needs bitcasts to/from an integer vector type around it.
26061 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26062 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26063 N->getOperand(0)->getOperand(0), MaskConst);
26064 SDValue Res = DAG.getBitcast(VT, NewAnd);
26071 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26072 const X86Subtarget *Subtarget) {
26073 SDValue Op0 = N->getOperand(0);
26074 EVT VT = N->getValueType(0);
26075 EVT InVT = Op0.getValueType();
26076 EVT InSVT = InVT.getScalarType();
26077 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26079 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26080 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26081 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26083 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26084 InVT.getVectorNumElements());
26085 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26087 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26088 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26090 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26096 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26097 const X86Subtarget *Subtarget) {
26098 // First try to optimize away the conversion entirely when it's
26099 // conditionally from a constant. Vectors only.
26100 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26103 // Now move on to more general possibilities.
26104 SDValue Op0 = N->getOperand(0);
26105 EVT VT = N->getValueType(0);
26106 EVT InVT = Op0.getValueType();
26107 EVT InSVT = InVT.getScalarType();
26109 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26110 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26111 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26113 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26114 InVT.getVectorNumElements());
26115 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26116 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26119 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26120 // a 32-bit target where SSE doesn't support i64->FP operations.
26121 if (Op0.getOpcode() == ISD::LOAD) {
26122 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26123 EVT LdVT = Ld->getValueType(0);
26125 // This transformation is not supported if the result type is f16
26126 if (VT == MVT::f16)
26129 if (!Ld->isVolatile() && !VT.isVector() &&
26130 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26131 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26132 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26133 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26134 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26141 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26142 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26143 X86TargetLowering::DAGCombinerInfo &DCI) {
26144 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26145 // the result is either zero or one (depending on the input carry bit).
26146 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26147 if (X86::isZeroNode(N->getOperand(0)) &&
26148 X86::isZeroNode(N->getOperand(1)) &&
26149 // We don't have a good way to replace an EFLAGS use, so only do this when
26151 SDValue(N, 1).use_empty()) {
26153 EVT VT = N->getValueType(0);
26154 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26155 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26156 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26157 DAG.getConstant(X86::COND_B, DL,
26160 DAG.getConstant(1, DL, VT));
26161 return DCI.CombineTo(N, Res1, CarryOut);
26167 // fold (add Y, (sete X, 0)) -> adc 0, Y
26168 // (add Y, (setne X, 0)) -> sbb -1, Y
26169 // (sub (sete X, 0), Y) -> sbb 0, Y
26170 // (sub (setne X, 0), Y) -> adc -1, Y
26171 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26174 // Look through ZExts.
26175 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26176 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26179 SDValue SetCC = Ext.getOperand(0);
26180 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26183 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26184 if (CC != X86::COND_E && CC != X86::COND_NE)
26187 SDValue Cmp = SetCC.getOperand(1);
26188 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26189 !X86::isZeroNode(Cmp.getOperand(1)) ||
26190 !Cmp.getOperand(0).getValueType().isInteger())
26193 SDValue CmpOp0 = Cmp.getOperand(0);
26194 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26195 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26197 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26198 if (CC == X86::COND_NE)
26199 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26200 DL, OtherVal.getValueType(), OtherVal,
26201 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26203 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26204 DL, OtherVal.getValueType(), OtherVal,
26205 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26208 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26209 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26210 const X86Subtarget *Subtarget) {
26211 EVT VT = N->getValueType(0);
26212 SDValue Op0 = N->getOperand(0);
26213 SDValue Op1 = N->getOperand(1);
26215 // Try to synthesize horizontal adds from adds of shuffles.
26216 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26217 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26218 isHorizontalBinOp(Op0, Op1, true))
26219 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26221 return OptimizeConditionalInDecrement(N, DAG);
26224 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26225 const X86Subtarget *Subtarget) {
26226 SDValue Op0 = N->getOperand(0);
26227 SDValue Op1 = N->getOperand(1);
26229 // X86 can't encode an immediate LHS of a sub. See if we can push the
26230 // negation into a preceding instruction.
26231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26232 // If the RHS of the sub is a XOR with one use and a constant, invert the
26233 // immediate. Then add one to the LHS of the sub so we can turn
26234 // X-Y -> X+~Y+1, saving one register.
26235 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26236 isa<ConstantSDNode>(Op1.getOperand(1))) {
26237 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26238 EVT VT = Op0.getValueType();
26239 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26241 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26242 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26243 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26247 // Try to synthesize horizontal adds from adds of shuffles.
26248 EVT VT = N->getValueType(0);
26249 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26250 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26251 isHorizontalBinOp(Op0, Op1, true))
26252 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26254 return OptimizeConditionalInDecrement(N, DAG);
26257 /// performVZEXTCombine - Performs build vector combines
26258 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26259 TargetLowering::DAGCombinerInfo &DCI,
26260 const X86Subtarget *Subtarget) {
26262 MVT VT = N->getSimpleValueType(0);
26263 SDValue Op = N->getOperand(0);
26264 MVT OpVT = Op.getSimpleValueType();
26265 MVT OpEltVT = OpVT.getVectorElementType();
26266 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26268 // (vzext (bitcast (vzext (x)) -> (vzext x)
26270 while (V.getOpcode() == ISD::BITCAST)
26271 V = V.getOperand(0);
26273 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26274 MVT InnerVT = V.getSimpleValueType();
26275 MVT InnerEltVT = InnerVT.getVectorElementType();
26277 // If the element sizes match exactly, we can just do one larger vzext. This
26278 // is always an exact type match as vzext operates on integer types.
26279 if (OpEltVT == InnerEltVT) {
26280 assert(OpVT == InnerVT && "Types must match for vzext!");
26281 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26284 // The only other way we can combine them is if only a single element of the
26285 // inner vzext is used in the input to the outer vzext.
26286 if (InnerEltVT.getSizeInBits() < InputBits)
26289 // In this case, the inner vzext is completely dead because we're going to
26290 // only look at bits inside of the low element. Just do the outer vzext on
26291 // a bitcast of the input to the inner.
26292 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26295 // Check if we can bypass extracting and re-inserting an element of an input
26296 // vector. Essentially:
26297 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26298 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26299 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26300 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26301 SDValue ExtractedV = V.getOperand(0);
26302 SDValue OrigV = ExtractedV.getOperand(0);
26303 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26304 if (ExtractIdx->getZExtValue() == 0) {
26305 MVT OrigVT = OrigV.getSimpleValueType();
26306 // Extract a subvector if necessary...
26307 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26308 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26309 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26310 OrigVT.getVectorNumElements() / Ratio);
26311 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26312 DAG.getIntPtrConstant(0, DL));
26314 Op = DAG.getBitcast(OpVT, OrigV);
26315 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26322 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26323 DAGCombinerInfo &DCI) const {
26324 SelectionDAG &DAG = DCI.DAG;
26325 switch (N->getOpcode()) {
26327 case ISD::EXTRACT_VECTOR_ELT:
26328 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26331 case X86ISD::SHRUNKBLEND:
26332 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26333 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26334 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26335 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26336 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26337 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26338 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26341 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26342 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26343 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26344 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26345 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26346 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26347 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26348 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26349 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26350 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26351 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26352 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26354 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26356 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26357 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26358 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26359 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26360 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26361 case ISD::ANY_EXTEND:
26362 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26363 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26364 case ISD::SIGN_EXTEND_INREG:
26365 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26366 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26367 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26368 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26369 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26370 case X86ISD::SHUFP: // Handle all target specific shuffles
26371 case X86ISD::PALIGNR:
26372 case X86ISD::UNPCKH:
26373 case X86ISD::UNPCKL:
26374 case X86ISD::MOVHLPS:
26375 case X86ISD::MOVLHPS:
26376 case X86ISD::PSHUFB:
26377 case X86ISD::PSHUFD:
26378 case X86ISD::PSHUFHW:
26379 case X86ISD::PSHUFLW:
26380 case X86ISD::MOVSS:
26381 case X86ISD::MOVSD:
26382 case X86ISD::VPERMILPI:
26383 case X86ISD::VPERM2X128:
26384 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26385 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26386 case X86ISD::INSERTPS: {
26387 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26388 return PerformINSERTPSCombine(N, DAG, Subtarget);
26391 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26397 /// isTypeDesirableForOp - Return true if the target has native support for
26398 /// the specified value type and it is 'desirable' to use the type for the
26399 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26400 /// instruction encodings are longer and some i16 instructions are slow.
26401 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26402 if (!isTypeLegal(VT))
26404 if (VT != MVT::i16)
26411 case ISD::SIGN_EXTEND:
26412 case ISD::ZERO_EXTEND:
26413 case ISD::ANY_EXTEND:
26426 /// IsDesirableToPromoteOp - This method query the target whether it is
26427 /// beneficial for dag combiner to promote the specified node. If true, it
26428 /// should return the desired promotion type by reference.
26429 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26430 EVT VT = Op.getValueType();
26431 if (VT != MVT::i16)
26434 bool Promote = false;
26435 bool Commute = false;
26436 switch (Op.getOpcode()) {
26439 LoadSDNode *LD = cast<LoadSDNode>(Op);
26440 // If the non-extending load has a single use and it's not live out, then it
26441 // might be folded.
26442 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26443 Op.hasOneUse()*/) {
26444 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26445 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26446 // The only case where we'd want to promote LOAD (rather then it being
26447 // promoted as an operand is when it's only use is liveout.
26448 if (UI->getOpcode() != ISD::CopyToReg)
26455 case ISD::SIGN_EXTEND:
26456 case ISD::ZERO_EXTEND:
26457 case ISD::ANY_EXTEND:
26462 SDValue N0 = Op.getOperand(0);
26463 // Look out for (store (shl (load), x)).
26464 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26477 SDValue N0 = Op.getOperand(0);
26478 SDValue N1 = Op.getOperand(1);
26479 if (!Commute && MayFoldLoad(N1))
26481 // Avoid disabling potential load folding opportunities.
26482 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26484 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26494 //===----------------------------------------------------------------------===//
26495 // X86 Inline Assembly Support
26496 //===----------------------------------------------------------------------===//
26498 // Helper to match a string separated by whitespace.
26499 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26500 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26502 for (StringRef Piece : Pieces) {
26503 if (!S.startswith(Piece)) // Check if the piece matches.
26506 S = S.substr(Piece.size());
26507 StringRef::size_type Pos = S.find_first_not_of(" \t");
26508 if (Pos == 0) // We matched a prefix.
26517 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26519 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26520 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26521 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26522 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26524 if (AsmPieces.size() == 3)
26526 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26533 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26534 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26536 std::string AsmStr = IA->getAsmString();
26538 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26539 if (!Ty || Ty->getBitWidth() % 16 != 0)
26542 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26543 SmallVector<StringRef, 4> AsmPieces;
26544 SplitString(AsmStr, AsmPieces, ";\n");
26546 switch (AsmPieces.size()) {
26547 default: return false;
26549 // FIXME: this should verify that we are targeting a 486 or better. If not,
26550 // we will turn this bswap into something that will be lowered to logical
26551 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26552 // lower so don't worry about this.
26554 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26555 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26556 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26557 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26558 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26559 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26560 // No need to check constraints, nothing other than the equivalent of
26561 // "=r,0" would be valid here.
26562 return IntrinsicLowering::LowerToByteSwap(CI);
26565 // rorw $$8, ${0:w} --> llvm.bswap.i16
26566 if (CI->getType()->isIntegerTy(16) &&
26567 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26568 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26569 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26571 StringRef ConstraintsStr = IA->getConstraintString();
26572 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26573 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26574 if (clobbersFlagRegisters(AsmPieces))
26575 return IntrinsicLowering::LowerToByteSwap(CI);
26579 if (CI->getType()->isIntegerTy(32) &&
26580 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26581 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26582 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26583 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26585 StringRef ConstraintsStr = IA->getConstraintString();
26586 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26587 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26588 if (clobbersFlagRegisters(AsmPieces))
26589 return IntrinsicLowering::LowerToByteSwap(CI);
26592 if (CI->getType()->isIntegerTy(64)) {
26593 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26594 if (Constraints.size() >= 2 &&
26595 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26596 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26597 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26598 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26599 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26600 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26601 return IntrinsicLowering::LowerToByteSwap(CI);
26609 /// getConstraintType - Given a constraint letter, return the type of
26610 /// constraint it is for this target.
26611 X86TargetLowering::ConstraintType
26612 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26613 if (Constraint.size() == 1) {
26614 switch (Constraint[0]) {
26625 return C_RegisterClass;
26649 return TargetLowering::getConstraintType(Constraint);
26652 /// Examine constraint type and operand type and determine a weight value.
26653 /// This object must already have been set up with the operand type
26654 /// and the current alternative constraint selected.
26655 TargetLowering::ConstraintWeight
26656 X86TargetLowering::getSingleConstraintMatchWeight(
26657 AsmOperandInfo &info, const char *constraint) const {
26658 ConstraintWeight weight = CW_Invalid;
26659 Value *CallOperandVal = info.CallOperandVal;
26660 // If we don't have a value, we can't do a match,
26661 // but allow it at the lowest weight.
26662 if (!CallOperandVal)
26664 Type *type = CallOperandVal->getType();
26665 // Look at the constraint type.
26666 switch (*constraint) {
26668 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26679 if (CallOperandVal->getType()->isIntegerTy())
26680 weight = CW_SpecificReg;
26685 if (type->isFloatingPointTy())
26686 weight = CW_SpecificReg;
26689 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26690 weight = CW_SpecificReg;
26694 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26695 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26696 weight = CW_Register;
26699 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26700 if (C->getZExtValue() <= 31)
26701 weight = CW_Constant;
26705 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26706 if (C->getZExtValue() <= 63)
26707 weight = CW_Constant;
26711 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26712 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26713 weight = CW_Constant;
26717 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26718 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26719 weight = CW_Constant;
26723 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26724 if (C->getZExtValue() <= 3)
26725 weight = CW_Constant;
26729 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26730 if (C->getZExtValue() <= 0xff)
26731 weight = CW_Constant;
26736 if (isa<ConstantFP>(CallOperandVal)) {
26737 weight = CW_Constant;
26741 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26742 if ((C->getSExtValue() >= -0x80000000LL) &&
26743 (C->getSExtValue() <= 0x7fffffffLL))
26744 weight = CW_Constant;
26748 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26749 if (C->getZExtValue() <= 0xffffffff)
26750 weight = CW_Constant;
26757 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26758 /// with another that has more specific requirements based on the type of the
26759 /// corresponding operand.
26760 const char *X86TargetLowering::
26761 LowerXConstraint(EVT ConstraintVT) const {
26762 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26763 // 'f' like normal targets.
26764 if (ConstraintVT.isFloatingPoint()) {
26765 if (Subtarget->hasSSE2())
26767 if (Subtarget->hasSSE1())
26771 return TargetLowering::LowerXConstraint(ConstraintVT);
26774 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26775 /// vector. If it is invalid, don't add anything to Ops.
26776 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26777 std::string &Constraint,
26778 std::vector<SDValue>&Ops,
26779 SelectionDAG &DAG) const {
26782 // Only support length 1 constraints for now.
26783 if (Constraint.length() > 1) return;
26785 char ConstraintLetter = Constraint[0];
26786 switch (ConstraintLetter) {
26789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26790 if (C->getZExtValue() <= 31) {
26791 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26792 Op.getValueType());
26798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26799 if (C->getZExtValue() <= 63) {
26800 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26801 Op.getValueType());
26807 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26808 if (isInt<8>(C->getSExtValue())) {
26809 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26810 Op.getValueType());
26816 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26817 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26818 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26819 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26820 Op.getValueType());
26826 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26827 if (C->getZExtValue() <= 3) {
26828 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26829 Op.getValueType());
26835 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26836 if (C->getZExtValue() <= 255) {
26837 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26838 Op.getValueType());
26844 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26845 if (C->getZExtValue() <= 127) {
26846 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26847 Op.getValueType());
26853 // 32-bit signed value
26854 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26855 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26856 C->getSExtValue())) {
26857 // Widen to 64 bits here to get it sign extended.
26858 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26861 // FIXME gcc accepts some relocatable values here too, but only in certain
26862 // memory models; it's complicated.
26867 // 32-bit unsigned value
26868 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26869 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26870 C->getZExtValue())) {
26871 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26872 Op.getValueType());
26876 // FIXME gcc accepts some relocatable values here too, but only in certain
26877 // memory models; it's complicated.
26881 // Literal immediates are always ok.
26882 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26883 // Widen to 64 bits here to get it sign extended.
26884 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26888 // In any sort of PIC mode addresses need to be computed at runtime by
26889 // adding in a register or some sort of table lookup. These can't
26890 // be used as immediates.
26891 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26894 // If we are in non-pic codegen mode, we allow the address of a global (with
26895 // an optional displacement) to be used with 'i'.
26896 GlobalAddressSDNode *GA = nullptr;
26897 int64_t Offset = 0;
26899 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26901 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26902 Offset += GA->getOffset();
26904 } else if (Op.getOpcode() == ISD::ADD) {
26905 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26906 Offset += C->getZExtValue();
26907 Op = Op.getOperand(0);
26910 } else if (Op.getOpcode() == ISD::SUB) {
26911 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26912 Offset += -C->getZExtValue();
26913 Op = Op.getOperand(0);
26918 // Otherwise, this isn't something we can handle, reject it.
26922 const GlobalValue *GV = GA->getGlobal();
26923 // If we require an extra load to get this address, as in PIC mode, we
26924 // can't accept it.
26925 if (isGlobalStubReference(
26926 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26929 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26930 GA->getValueType(0), Offset);
26935 if (Result.getNode()) {
26936 Ops.push_back(Result);
26939 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26942 std::pair<unsigned, const TargetRegisterClass *>
26943 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
26944 StringRef Constraint,
26946 // First, see if this is a constraint that directly corresponds to an LLVM
26948 if (Constraint.size() == 1) {
26949 // GCC Constraint Letters
26950 switch (Constraint[0]) {
26952 // TODO: Slight differences here in allocation order and leaving
26953 // RIP in the class. Do they matter any more here than they do
26954 // in the normal allocation?
26955 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26956 if (Subtarget->is64Bit()) {
26957 if (VT == MVT::i32 || VT == MVT::f32)
26958 return std::make_pair(0U, &X86::GR32RegClass);
26959 if (VT == MVT::i16)
26960 return std::make_pair(0U, &X86::GR16RegClass);
26961 if (VT == MVT::i8 || VT == MVT::i1)
26962 return std::make_pair(0U, &X86::GR8RegClass);
26963 if (VT == MVT::i64 || VT == MVT::f64)
26964 return std::make_pair(0U, &X86::GR64RegClass);
26967 // 32-bit fallthrough
26968 case 'Q': // Q_REGS
26969 if (VT == MVT::i32 || VT == MVT::f32)
26970 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26971 if (VT == MVT::i16)
26972 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26973 if (VT == MVT::i8 || VT == MVT::i1)
26974 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26975 if (VT == MVT::i64)
26976 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26978 case 'r': // GENERAL_REGS
26979 case 'l': // INDEX_REGS
26980 if (VT == MVT::i8 || VT == MVT::i1)
26981 return std::make_pair(0U, &X86::GR8RegClass);
26982 if (VT == MVT::i16)
26983 return std::make_pair(0U, &X86::GR16RegClass);
26984 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26985 return std::make_pair(0U, &X86::GR32RegClass);
26986 return std::make_pair(0U, &X86::GR64RegClass);
26987 case 'R': // LEGACY_REGS
26988 if (VT == MVT::i8 || VT == MVT::i1)
26989 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26990 if (VT == MVT::i16)
26991 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26992 if (VT == MVT::i32 || !Subtarget->is64Bit())
26993 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26994 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26995 case 'f': // FP Stack registers.
26996 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26997 // value to the correct fpstack register class.
26998 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26999 return std::make_pair(0U, &X86::RFP32RegClass);
27000 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27001 return std::make_pair(0U, &X86::RFP64RegClass);
27002 return std::make_pair(0U, &X86::RFP80RegClass);
27003 case 'y': // MMX_REGS if MMX allowed.
27004 if (!Subtarget->hasMMX()) break;
27005 return std::make_pair(0U, &X86::VR64RegClass);
27006 case 'Y': // SSE_REGS if SSE2 allowed
27007 if (!Subtarget->hasSSE2()) break;
27009 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27010 if (!Subtarget->hasSSE1()) break;
27012 switch (VT.SimpleTy) {
27014 // Scalar SSE types.
27017 return std::make_pair(0U, &X86::FR32RegClass);
27020 return std::make_pair(0U, &X86::FR64RegClass);
27028 return std::make_pair(0U, &X86::VR128RegClass);
27036 return std::make_pair(0U, &X86::VR256RegClass);
27041 return std::make_pair(0U, &X86::VR512RegClass);
27047 // Use the default implementation in TargetLowering to convert the register
27048 // constraint into a member of a register class.
27049 std::pair<unsigned, const TargetRegisterClass*> Res;
27050 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27052 // Not found as a standard register?
27054 // Map st(0) -> st(7) -> ST0
27055 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27056 tolower(Constraint[1]) == 's' &&
27057 tolower(Constraint[2]) == 't' &&
27058 Constraint[3] == '(' &&
27059 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27060 Constraint[5] == ')' &&
27061 Constraint[6] == '}') {
27063 Res.first = X86::FP0+Constraint[4]-'0';
27064 Res.second = &X86::RFP80RegClass;
27068 // GCC allows "st(0)" to be called just plain "st".
27069 if (StringRef("{st}").equals_lower(Constraint)) {
27070 Res.first = X86::FP0;
27071 Res.second = &X86::RFP80RegClass;
27076 if (StringRef("{flags}").equals_lower(Constraint)) {
27077 Res.first = X86::EFLAGS;
27078 Res.second = &X86::CCRRegClass;
27082 // 'A' means EAX + EDX.
27083 if (Constraint == "A") {
27084 Res.first = X86::EAX;
27085 Res.second = &X86::GR32_ADRegClass;
27091 // Otherwise, check to see if this is a register class of the wrong value
27092 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27093 // turn into {ax},{dx}.
27094 // MVT::Other is used to specify clobber names.
27095 if (Res.second->hasType(VT) || VT == MVT::Other)
27096 return Res; // Correct type already, nothing to do.
27098 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27099 // return "eax". This should even work for things like getting 64bit integer
27100 // registers when given an f64 type.
27101 const TargetRegisterClass *Class = Res.second;
27102 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27103 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27104 unsigned Size = VT.getSizeInBits();
27105 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27106 : Size == 16 ? MVT::i16
27107 : Size == 32 ? MVT::i32
27108 : Size == 64 ? MVT::i64
27110 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27112 Res.first = DestReg;
27113 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27114 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27115 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27116 : &X86::GR64RegClass;
27117 assert(Res.second->contains(Res.first) && "Register in register class");
27119 // No register found/type mismatch.
27121 Res.second = nullptr;
27123 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27124 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27125 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27126 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27127 Class == &X86::VR512RegClass) {
27128 // Handle references to XMM physical registers that got mapped into the
27129 // wrong class. This can happen with constraints like {xmm0} where the
27130 // target independent register mapper will just pick the first match it can
27131 // find, ignoring the required type.
27133 if (VT == MVT::f32 || VT == MVT::i32)
27134 Res.second = &X86::FR32RegClass;
27135 else if (VT == MVT::f64 || VT == MVT::i64)
27136 Res.second = &X86::FR64RegClass;
27137 else if (X86::VR128RegClass.hasType(VT))
27138 Res.second = &X86::VR128RegClass;
27139 else if (X86::VR256RegClass.hasType(VT))
27140 Res.second = &X86::VR256RegClass;
27141 else if (X86::VR512RegClass.hasType(VT))
27142 Res.second = &X86::VR512RegClass;
27144 // Type mismatch and not a clobber: Return an error;
27146 Res.second = nullptr;
27153 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27154 const AddrMode &AM, Type *Ty,
27155 unsigned AS) const {
27156 // Scaling factors are not free at all.
27157 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27158 // will take 2 allocations in the out of order engine instead of 1
27159 // for plain addressing mode, i.e. inst (reg1).
27161 // vaddps (%rsi,%drx), %ymm0, %ymm1
27162 // Requires two allocations (one for the load, one for the computation)
27164 // vaddps (%rsi), %ymm0, %ymm1
27165 // Requires just 1 allocation, i.e., freeing allocations for other operations
27166 // and having less micro operations to execute.
27168 // For some X86 architectures, this is even worse because for instance for
27169 // stores, the complex addressing mode forces the instruction to use the
27170 // "load" ports instead of the dedicated "store" port.
27171 // E.g., on Haswell:
27172 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27173 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27174 if (isLegalAddressingMode(DL, AM, Ty, AS))
27175 // Scale represents reg2 * scale, thus account for 1
27176 // as soon as we use a second register.
27177 return AM.Scale != 0;
27181 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27182 // Integer division on x86 is expensive. However, when aggressively optimizing
27183 // for code size, we prefer to use a div instruction, as it is usually smaller
27184 // than the alternative sequence.
27185 // The exception to this is vector division. Since x86 doesn't have vector
27186 // integer division, leaving the division as-is is a loss even in terms of
27187 // size, because it will have to be scalarized, while the alternative code
27188 // sequence can be performed in vector form.
27189 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27190 Attribute::MinSize);
27191 return OptSize && !VT.isVector();