1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Constants.h"
35 #include "llvm/DerivedTypes.h"
36 #include "llvm/Function.h"
37 #include "llvm/GlobalAlias.h"
38 #include "llvm/GlobalVariable.h"
39 #include "llvm/Instructions.h"
40 #include "llvm/Intrinsics.h"
41 #include "llvm/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
162 RegInfo = TM.getRegisterInfo();
163 TD = getDataLayout();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
184 // Bypass i32 with i8 on Atom when compiling with O2
185 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default)
186 addBypassSlowDiv(32, 8);
188 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
189 // Setup Windows compiler runtime calls.
190 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
191 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
192 setLibcallName(RTLIB::SREM_I64, "_allrem");
193 setLibcallName(RTLIB::UREM_I64, "_aullrem");
194 setLibcallName(RTLIB::MUL_I64, "_allmul");
195 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
197 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
198 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
199 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
201 // The _ftol2 runtime function has an unusual calling conv, which
202 // is modeled by a special pseudo-instruction.
203 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
204 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
205 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
206 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
209 if (Subtarget->isTargetDarwin()) {
210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
211 setUseUnderscoreSetJmp(false);
212 setUseUnderscoreLongJmp(false);
213 } else if (Subtarget->isTargetMingw()) {
214 // MS runtime is weird: it exports _setjmp, but longjmp!
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(false);
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(true);
222 // Set up the register classes.
223 addRegisterClass(MVT::i8, &X86::GR8RegClass);
224 addRegisterClass(MVT::i16, &X86::GR16RegClass);
225 addRegisterClass(MVT::i32, &X86::GR32RegClass);
226 if (Subtarget->is64Bit())
227 addRegisterClass(MVT::i64, &X86::GR64RegClass);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 // We don't accept any truncstore of integer registers.
232 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
233 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
235 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
237 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
239 // SETOEQ and SETUNE require checking two conditions.
240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 } else if (!TM.Options.UseSoftFloat) {
257 // We have an algorithm for SSE2->double, and we turn this into a
258 // 64-bit FILD followed by conditional FADD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
260 // We have an algorithm for SSE2, and we turn this into a 64-bit
261 // FILD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
270 if (!TM.Options.UseSoftFloat) {
271 // SSE has no i16 to fp conversion, only i32
272 if (X86ScalarSSEf32) {
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
274 // f32 and f64 cases are Legal, f80 case is not
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
286 // are Legal, f80 is custom lowered.
287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
295 if (X86ScalarSSEf32) {
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
297 // f32 and f64 cases are Legal, f80 case is not
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 // Handle FP_TO_UINT by promoting the destination to a larger signed
306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
310 if (Subtarget->is64Bit()) {
311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
313 } else if (!TM.Options.UseSoftFloat) {
314 // Since AVX is a superset of SSE3, only check for SSE here.
315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 if (isTargetFTOL()) {
327 // Use the _ftol2 runtime function, which has a pseudo-instruction
328 // to handle its weird calling convention.
329 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
332 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
333 if (!X86ScalarSSEf64) {
334 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
335 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
338 // Without SSE, i64->f64 goes through memory.
339 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
343 // Scalar integer divide and remainder are lowered to use operations that
344 // produce two results, to match the available instructions. This exposes
345 // the two-result form to trivial CSE, which is able to combine x/y and x%y
346 // into a single instruction.
348 // Scalar integer multiply-high is also lowered to use two-result
349 // operations, to match the available instructions. However, plain multiply
350 // (low) operations are left as Legal, as there are single-result
351 // instructions for this in x86. Using the two-result multiply instructions
352 // when both high and low results are needed must be arranged by dagcombine.
353 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
355 setOperationAction(ISD::MULHS, VT, Expand);
356 setOperationAction(ISD::MULHU, VT, Expand);
357 setOperationAction(ISD::SDIV, VT, Expand);
358 setOperationAction(ISD::UDIV, VT, Expand);
359 setOperationAction(ISD::SREM, VT, Expand);
360 setOperationAction(ISD::UREM, VT, Expand);
362 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
363 setOperationAction(ISD::ADDC, VT, Custom);
364 setOperationAction(ISD::ADDE, VT, Custom);
365 setOperationAction(ISD::SUBC, VT, Custom);
366 setOperationAction(ISD::SUBE, VT, Custom);
369 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
370 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
371 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
372 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
373 if (Subtarget->is64Bit())
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
378 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
379 setOperationAction(ISD::FREM , MVT::f32 , Expand);
380 setOperationAction(ISD::FREM , MVT::f64 , Expand);
381 setOperationAction(ISD::FREM , MVT::f80 , Expand);
382 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
384 // Promote the i8 variants and force them on up to i32 which has a shorter
386 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
387 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
389 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
390 if (Subtarget->hasBMI()) {
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
396 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
397 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
398 if (Subtarget->is64Bit())
399 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
402 if (Subtarget->hasLZCNT()) {
403 // When promoting the i8 variants, force them to i32 for a shorter
405 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
406 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
408 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
411 if (Subtarget->is64Bit())
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
414 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
422 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
426 if (Subtarget->hasPOPCNT()) {
427 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
429 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
430 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
431 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
436 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
437 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
439 // These should be promoted to a larger select which is supported.
440 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
441 // X86 wants to expand cmov itself.
442 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
443 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
444 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
445 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
446 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
447 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
448 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
449 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
451 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
454 if (Subtarget->is64Bit()) {
455 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
456 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
458 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
459 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intened to support
460 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
461 // support continuation, user-level threading, and etc.. As a result, no
462 // other SjLj exception interfaces are implemented and please don't build
463 // your own exception handling based on them.
464 // LLVM/Clang supports zero-cost DWARF exception handling.
465 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
466 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
469 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
470 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
471 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
472 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
475 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
476 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
479 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
480 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
481 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
482 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
484 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
485 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
486 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
487 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
488 if (Subtarget->is64Bit()) {
489 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
490 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
491 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
494 if (Subtarget->hasSSE1())
495 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
497 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
498 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
500 // On X86 and X86-64, atomic operations are lowered to locked instructions.
501 // Locked instructions, in turn, have implicit fence semantics (all memory
502 // operations are flushed before issuing the locked instruction, and they
503 // are not buffered), so we can fold away the common pattern of
504 // fence-atomic-fence.
505 setShouldFoldAtomicFences(true);
507 // Expand certain atomics
508 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
512 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
515 if (!Subtarget->is64Bit()) {
516 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
517 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
518 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
519 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
520 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
521 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
522 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
523 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
524 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
525 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
526 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
527 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
530 if (Subtarget->hasCmpxchg16b()) {
531 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
534 // FIXME - use subtarget debug flags
535 if (!Subtarget->isTargetDarwin() &&
536 !Subtarget->isTargetELF() &&
537 !Subtarget->isTargetCygMing()) {
538 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
541 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
542 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
543 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
544 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
545 if (Subtarget->is64Bit()) {
546 setExceptionPointerRegister(X86::RAX);
547 setExceptionSelectorRegister(X86::RDX);
549 setExceptionPointerRegister(X86::EAX);
550 setExceptionSelectorRegister(X86::EDX);
552 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
553 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
555 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
556 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
558 setOperationAction(ISD::TRAP, MVT::Other, Legal);
559 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
561 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
562 setOperationAction(ISD::VASTART , MVT::Other, Custom);
563 setOperationAction(ISD::VAEND , MVT::Other, Expand);
564 if (Subtarget->is64Bit()) {
565 setOperationAction(ISD::VAARG , MVT::Other, Custom);
566 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
568 setOperationAction(ISD::VAARG , MVT::Other, Expand);
569 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
572 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
573 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
575 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
576 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
577 MVT::i64 : MVT::i32, Custom);
578 else if (TM.Options.EnableSegmentedStacks)
579 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
580 MVT::i64 : MVT::i32, Custom);
582 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
583 MVT::i64 : MVT::i32, Expand);
585 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
586 // f32 and f64 use SSE.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f32, &X86::FR32RegClass);
589 addRegisterClass(MVT::f64, &X86::FR64RegClass);
591 // Use ANDPD to simulate FABS.
592 setOperationAction(ISD::FABS , MVT::f64, Custom);
593 setOperationAction(ISD::FABS , MVT::f32, Custom);
595 // Use XORP to simulate FNEG.
596 setOperationAction(ISD::FNEG , MVT::f64, Custom);
597 setOperationAction(ISD::FNEG , MVT::f32, Custom);
599 // Use ANDPD and ORPD to simulate FCOPYSIGN.
600 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
601 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
603 // Lower this to FGETSIGNx86 plus an AND.
604 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
605 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
607 // We don't support sin/cos/fmod
608 setOperationAction(ISD::FSIN , MVT::f64, Expand);
609 setOperationAction(ISD::FCOS , MVT::f64, Expand);
610 setOperationAction(ISD::FSIN , MVT::f32, Expand);
611 setOperationAction(ISD::FCOS , MVT::f32, Expand);
613 // Expand FP immediates into loads from the stack, except for the special
615 addLegalFPImmediate(APFloat(+0.0)); // xorpd
616 addLegalFPImmediate(APFloat(+0.0f)); // xorps
617 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
618 // Use SSE for f32, x87 for f64.
619 // Set up the FP register classes.
620 addRegisterClass(MVT::f32, &X86::FR32RegClass);
621 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
623 // Use ANDPS to simulate FABS.
624 setOperationAction(ISD::FABS , MVT::f32, Custom);
626 // Use XORP to simulate FNEG.
627 setOperationAction(ISD::FNEG , MVT::f32, Custom);
629 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
631 // Use ANDPS and ORPS to simulate FCOPYSIGN.
632 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
633 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
635 // We don't support sin/cos/fmod
636 setOperationAction(ISD::FSIN , MVT::f32, Expand);
637 setOperationAction(ISD::FCOS , MVT::f32, Expand);
639 // Special cases we handle for FP constants.
640 addLegalFPImmediate(APFloat(+0.0f)); // xorps
641 addLegalFPImmediate(APFloat(+0.0)); // FLD0
642 addLegalFPImmediate(APFloat(+1.0)); // FLD1
643 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
644 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
646 if (!TM.Options.UnsafeFPMath) {
647 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
648 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
650 } else if (!TM.Options.UseSoftFloat) {
651 // f32 and f64 in x87.
652 // Set up the FP register classes.
653 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
654 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
656 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
657 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
658 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
659 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
661 if (!TM.Options.UnsafeFPMath) {
662 setOperationAction(ISD::FSIN , MVT::f32 , Expand);
663 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
664 setOperationAction(ISD::FCOS , MVT::f32 , Expand);
665 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
667 addLegalFPImmediate(APFloat(+0.0)); // FLD0
668 addLegalFPImmediate(APFloat(+1.0)); // FLD1
669 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
670 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
671 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
672 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
673 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
674 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
677 // We don't support FMA.
678 setOperationAction(ISD::FMA, MVT::f64, Expand);
679 setOperationAction(ISD::FMA, MVT::f32, Expand);
681 // Long double always uses X87.
682 if (!TM.Options.UseSoftFloat) {
683 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
684 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
685 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
687 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
688 addLegalFPImmediate(TmpFlt); // FLD0
690 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
693 APFloat TmpFlt2(+1.0);
694 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
696 addLegalFPImmediate(TmpFlt2); // FLD1
697 TmpFlt2.changeSign();
698 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
701 if (!TM.Options.UnsafeFPMath) {
702 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
703 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
706 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
707 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
708 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
709 setOperationAction(ISD::FRINT, MVT::f80, Expand);
710 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
711 setOperationAction(ISD::FMA, MVT::f80, Expand);
714 // Always use a library call for pow.
715 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
716 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
717 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
719 setOperationAction(ISD::FLOG, MVT::f80, Expand);
720 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
721 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
722 setOperationAction(ISD::FEXP, MVT::f80, Expand);
723 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
725 // First set operation action for all vector types to either promote
726 // (for widening) or expand (for scalarization). Then we will selectively
727 // turn on ones that can be effectively codegen'd.
728 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
729 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
730 MVT VT = (MVT::SimpleValueType)i;
731 setOperationAction(ISD::ADD , VT, Expand);
732 setOperationAction(ISD::SUB , VT, Expand);
733 setOperationAction(ISD::FADD, VT, Expand);
734 setOperationAction(ISD::FNEG, VT, Expand);
735 setOperationAction(ISD::FSUB, VT, Expand);
736 setOperationAction(ISD::MUL , VT, Expand);
737 setOperationAction(ISD::FMUL, VT, Expand);
738 setOperationAction(ISD::SDIV, VT, Expand);
739 setOperationAction(ISD::UDIV, VT, Expand);
740 setOperationAction(ISD::FDIV, VT, Expand);
741 setOperationAction(ISD::SREM, VT, Expand);
742 setOperationAction(ISD::UREM, VT, Expand);
743 setOperationAction(ISD::LOAD, VT, Expand);
744 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
745 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
746 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
747 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
748 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
749 setOperationAction(ISD::FABS, VT, Expand);
750 setOperationAction(ISD::FSIN, VT, Expand);
751 setOperationAction(ISD::FCOS, VT, Expand);
752 setOperationAction(ISD::FREM, VT, Expand);
753 setOperationAction(ISD::FMA, VT, Expand);
754 setOperationAction(ISD::FPOWI, VT, Expand);
755 setOperationAction(ISD::FSQRT, VT, Expand);
756 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
757 setOperationAction(ISD::FFLOOR, VT, Expand);
758 setOperationAction(ISD::FCEIL, VT, Expand);
759 setOperationAction(ISD::FTRUNC, VT, Expand);
760 setOperationAction(ISD::FRINT, VT, Expand);
761 setOperationAction(ISD::FNEARBYINT, VT, Expand);
762 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
763 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
764 setOperationAction(ISD::SDIVREM, VT, Expand);
765 setOperationAction(ISD::UDIVREM, VT, Expand);
766 setOperationAction(ISD::FPOW, VT, Expand);
767 setOperationAction(ISD::CTPOP, VT, Expand);
768 setOperationAction(ISD::CTTZ, VT, Expand);
769 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
770 setOperationAction(ISD::CTLZ, VT, Expand);
771 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
772 setOperationAction(ISD::SHL, VT, Expand);
773 setOperationAction(ISD::SRA, VT, Expand);
774 setOperationAction(ISD::SRL, VT, Expand);
775 setOperationAction(ISD::ROTL, VT, Expand);
776 setOperationAction(ISD::ROTR, VT, Expand);
777 setOperationAction(ISD::BSWAP, VT, Expand);
778 setOperationAction(ISD::SETCC, VT, Expand);
779 setOperationAction(ISD::FLOG, VT, Expand);
780 setOperationAction(ISD::FLOG2, VT, Expand);
781 setOperationAction(ISD::FLOG10, VT, Expand);
782 setOperationAction(ISD::FEXP, VT, Expand);
783 setOperationAction(ISD::FEXP2, VT, Expand);
784 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
785 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
786 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
787 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
788 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
789 setOperationAction(ISD::TRUNCATE, VT, Expand);
790 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
791 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
792 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
793 setOperationAction(ISD::VSELECT, VT, Expand);
794 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
795 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
796 setTruncStoreAction(VT,
797 (MVT::SimpleValueType)InnerVT, Expand);
798 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
799 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
800 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
803 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
804 // with -msoft-float, disable use of MMX as well.
805 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
806 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
807 // No operations on x86mmx supported, everything uses intrinsics.
810 // MMX-sized vectors (other than x86mmx) are expected to be expanded
811 // into smaller operations.
812 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
813 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
814 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
815 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
816 setOperationAction(ISD::AND, MVT::v8i8, Expand);
817 setOperationAction(ISD::AND, MVT::v4i16, Expand);
818 setOperationAction(ISD::AND, MVT::v2i32, Expand);
819 setOperationAction(ISD::AND, MVT::v1i64, Expand);
820 setOperationAction(ISD::OR, MVT::v8i8, Expand);
821 setOperationAction(ISD::OR, MVT::v4i16, Expand);
822 setOperationAction(ISD::OR, MVT::v2i32, Expand);
823 setOperationAction(ISD::OR, MVT::v1i64, Expand);
824 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
825 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
826 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
827 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
828 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
831 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
833 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
834 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
835 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
836 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
837 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
838 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
839 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
840 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
842 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
843 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
845 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
846 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
847 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
848 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
849 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
850 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
851 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
852 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
853 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
856 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
859 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
860 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
862 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
863 // registers cannot be used even for integer operations.
864 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
865 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
866 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
867 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
869 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
870 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
871 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
872 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
873 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
874 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
875 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
876 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
877 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
878 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
879 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
880 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
881 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
882 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
883 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
884 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
885 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
887 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
888 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
889 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
890 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
892 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
893 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
895 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
898 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
899 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
900 MVT VT = (MVT::SimpleValueType)i;
901 // Do not attempt to custom lower non-power-of-2 vectors
902 if (!isPowerOf2_32(VT.getVectorNumElements()))
904 // Do not attempt to custom lower non-128-bit vectors
905 if (!VT.is128BitVector())
907 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
908 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
909 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
912 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
913 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
914 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
915 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
916 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
919 if (Subtarget->is64Bit()) {
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
924 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
925 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
926 MVT VT = (MVT::SimpleValueType)i;
928 // Do not attempt to promote non-128-bit vectors
929 if (!VT.is128BitVector())
932 setOperationAction(ISD::AND, VT, Promote);
933 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
934 setOperationAction(ISD::OR, VT, Promote);
935 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
936 setOperationAction(ISD::XOR, VT, Promote);
937 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
938 setOperationAction(ISD::LOAD, VT, Promote);
939 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
940 setOperationAction(ISD::SELECT, VT, Promote);
941 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
944 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
946 // Custom lower v2i64 and v2f64 selects.
947 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
948 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
949 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
950 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
952 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
953 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
955 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
956 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
957 // As there is no 64-bit GPR available, we need build a special custom
958 // sequence to convert from v2i32 to v2f32.
959 if (!Subtarget->is64Bit())
960 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
962 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
963 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
965 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
968 if (Subtarget->hasSSE41()) {
969 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
970 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
971 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
972 setOperationAction(ISD::FRINT, MVT::f32, Legal);
973 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
974 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
975 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
976 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
977 setOperationAction(ISD::FRINT, MVT::f64, Legal);
978 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
980 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
981 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
982 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
983 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
984 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
985 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
986 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
988 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
991 // FIXME: Do we need to handle scalar-to-vector here?
992 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
994 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
995 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
996 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
997 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
998 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1000 // i8 and i16 vectors are custom , because the source register and source
1001 // source memory operand types are not the same width. f32 vectors are
1002 // custom since the immediate controlling the insert encodes additional
1004 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1005 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1007 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1014 // FIXME: these should be Legal but thats only for the case where
1015 // the index is constant. For now custom expand to deal with that.
1016 if (Subtarget->is64Bit()) {
1017 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1018 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1022 if (Subtarget->hasSSE2()) {
1023 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1029 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1030 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1032 if (Subtarget->hasInt256()) {
1033 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1034 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1036 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1037 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1039 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1041 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1042 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1044 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1045 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1047 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1051 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1052 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1053 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1059 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1060 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1063 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1064 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1074 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1077 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1087 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1089 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1091 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1094 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1095 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1097 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1098 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1099 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1101 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1103 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1104 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1106 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1117 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1118 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1119 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1121 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1122 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1123 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1124 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1126 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1127 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1129 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1130 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1131 setOperationAction(ISD::FMA, MVT::f32, Legal);
1132 setOperationAction(ISD::FMA, MVT::f64, Legal);
1135 if (Subtarget->hasInt256()) {
1136 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1137 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1138 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1139 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1141 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1142 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1143 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1144 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1146 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1147 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1148 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1149 // Don't lower v32i8 because there is no 128-bit byte mul
1151 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1153 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1154 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1156 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1157 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1161 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1174 // Don't lower v32i8 because there is no 128-bit byte mul
1176 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1177 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1179 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1180 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1182 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1185 // Custom lower several nodes for 256-bit types.
1186 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1187 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1188 MVT VT = (MVT::SimpleValueType)i;
1190 // Extract subvector is special because the value type
1191 // (result) is 128-bit but the source is 256-bit wide.
1192 if (VT.is128BitVector())
1193 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1195 // Do not attempt to custom lower other non-256-bit vectors
1196 if (!VT.is256BitVector())
1199 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1200 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1201 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1202 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1203 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1204 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1205 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1208 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1209 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1210 MVT VT = (MVT::SimpleValueType)i;
1212 // Do not attempt to promote non-256-bit vectors
1213 if (!VT.is256BitVector())
1216 setOperationAction(ISD::AND, VT, Promote);
1217 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1218 setOperationAction(ISD::OR, VT, Promote);
1219 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1220 setOperationAction(ISD::XOR, VT, Promote);
1221 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1222 setOperationAction(ISD::LOAD, VT, Promote);
1223 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1224 setOperationAction(ISD::SELECT, VT, Promote);
1225 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1229 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1230 // of this type with custom code.
1231 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1232 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1233 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1237 // We want to custom lower some of our intrinsics.
1238 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1239 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1242 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1243 // handle type legalization for these operations here.
1245 // FIXME: We really should do custom legalization for addition and
1246 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1247 // than generic legalization for 64-bit multiplication-with-overflow, though.
1248 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1249 // Add/Sub/Mul with overflow operations are custom lowered.
1251 setOperationAction(ISD::SADDO, VT, Custom);
1252 setOperationAction(ISD::UADDO, VT, Custom);
1253 setOperationAction(ISD::SSUBO, VT, Custom);
1254 setOperationAction(ISD::USUBO, VT, Custom);
1255 setOperationAction(ISD::SMULO, VT, Custom);
1256 setOperationAction(ISD::UMULO, VT, Custom);
1259 // There are no 8-bit 3-address imul/mul instructions
1260 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1261 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1263 if (!Subtarget->is64Bit()) {
1264 // These libcalls are not available in 32-bit.
1265 setLibcallName(RTLIB::SHL_I128, 0);
1266 setLibcallName(RTLIB::SRL_I128, 0);
1267 setLibcallName(RTLIB::SRA_I128, 0);
1270 // We have target-specific dag combine patterns for the following nodes:
1271 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1272 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1273 setTargetDAGCombine(ISD::VSELECT);
1274 setTargetDAGCombine(ISD::SELECT);
1275 setTargetDAGCombine(ISD::SHL);
1276 setTargetDAGCombine(ISD::SRA);
1277 setTargetDAGCombine(ISD::SRL);
1278 setTargetDAGCombine(ISD::OR);
1279 setTargetDAGCombine(ISD::AND);
1280 setTargetDAGCombine(ISD::ADD);
1281 setTargetDAGCombine(ISD::FADD);
1282 setTargetDAGCombine(ISD::FSUB);
1283 setTargetDAGCombine(ISD::FMA);
1284 setTargetDAGCombine(ISD::SUB);
1285 setTargetDAGCombine(ISD::LOAD);
1286 setTargetDAGCombine(ISD::STORE);
1287 setTargetDAGCombine(ISD::ZERO_EXTEND);
1288 setTargetDAGCombine(ISD::ANY_EXTEND);
1289 setTargetDAGCombine(ISD::SIGN_EXTEND);
1290 setTargetDAGCombine(ISD::TRUNCATE);
1291 setTargetDAGCombine(ISD::SINT_TO_FP);
1292 setTargetDAGCombine(ISD::SETCC);
1293 if (Subtarget->is64Bit())
1294 setTargetDAGCombine(ISD::MUL);
1295 setTargetDAGCombine(ISD::XOR);
1297 computeRegisterProperties();
1299 // On Darwin, -Os means optimize for size without hurting performance,
1300 // do not reduce the limit.
1301 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1302 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1303 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1304 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1305 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1306 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1307 setPrefLoopAlignment(4); // 2^4 bytes.
1308 benefitFromCodePlacementOpt = true;
1310 // Predictable cmov don't hurt on atom because it's in-order.
1311 predictableSelectIsExpensive = !Subtarget->isAtom();
1313 setPrefFunctionAlignment(4); // 2^4 bytes.
1317 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1318 if (!VT.isVector()) return MVT::i8;
1319 return VT.changeVectorElementTypeToInteger();
1323 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1324 /// the desired ByVal argument alignment.
1325 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1328 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1329 if (VTy->getBitWidth() == 128)
1331 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1332 unsigned EltAlign = 0;
1333 getMaxByValAlign(ATy->getElementType(), EltAlign);
1334 if (EltAlign > MaxAlign)
1335 MaxAlign = EltAlign;
1336 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1337 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1338 unsigned EltAlign = 0;
1339 getMaxByValAlign(STy->getElementType(i), EltAlign);
1340 if (EltAlign > MaxAlign)
1341 MaxAlign = EltAlign;
1348 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1349 /// function arguments in the caller parameter area. For X86, aggregates
1350 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1351 /// are at 4-byte boundaries.
1352 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1353 if (Subtarget->is64Bit()) {
1354 // Max of 8 and alignment of type.
1355 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1362 if (Subtarget->hasSSE1())
1363 getMaxByValAlign(Ty, Align);
1367 /// getOptimalMemOpType - Returns the target specific optimal type for load
1368 /// and store operations as a result of memset, memcpy, and memmove
1369 /// lowering. If DstAlign is zero that means it's safe to destination
1370 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1371 /// means there isn't a need to check it against alignment requirement,
1372 /// probably because the source does not need to be loaded. If
1373 /// 'ZeroOrLdSrc' is true, that means it's safe to return a
1374 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1375 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1376 /// constant so it does not need to be loaded.
1377 /// It returns EVT::Other if the type should be determined using generic
1378 /// target-independent logic.
1380 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1381 unsigned DstAlign, unsigned SrcAlign,
1384 MachineFunction &MF) const {
1385 const Function *F = MF.getFunction();
1387 !F->getFnAttributes().hasAttribute(Attributes::NoImplicitFloat)) {
1389 (Subtarget->isUnalignedMemAccessFast() ||
1390 ((DstAlign == 0 || DstAlign >= 16) &&
1391 (SrcAlign == 0 || SrcAlign >= 16)))) {
1393 if (Subtarget->hasInt256())
1395 if (Subtarget->hasFp256())
1398 if (Subtarget->hasSSE2())
1400 if (Subtarget->hasSSE1())
1402 } else if (!MemcpyStrSrc && Size >= 8 &&
1403 !Subtarget->is64Bit() &&
1404 Subtarget->hasSSE2()) {
1405 // Do not use f64 to lower memcpy if source is string constant. It's
1406 // better to use i32 to avoid the loads.
1410 if (Subtarget->is64Bit() && Size >= 8)
1415 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1417 return X86ScalarSSEf32;
1418 else if (VT == MVT::f64)
1419 return X86ScalarSSEf64;
1424 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1426 *Fast = Subtarget->isUnalignedMemAccessFast();
1430 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1431 /// current function. The returned value is a member of the
1432 /// MachineJumpTableInfo::JTEntryKind enum.
1433 unsigned X86TargetLowering::getJumpTableEncoding() const {
1434 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1436 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1437 Subtarget->isPICStyleGOT())
1438 return MachineJumpTableInfo::EK_Custom32;
1440 // Otherwise, use the normal jump table encoding heuristics.
1441 return TargetLowering::getJumpTableEncoding();
1445 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1446 const MachineBasicBlock *MBB,
1447 unsigned uid,MCContext &Ctx) const{
1448 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1449 Subtarget->isPICStyleGOT());
1450 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1452 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1453 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1456 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1458 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1459 SelectionDAG &DAG) const {
1460 if (!Subtarget->is64Bit())
1461 // This doesn't have DebugLoc associated with it, but is not really the
1462 // same as a Register.
1463 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1467 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1468 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1470 const MCExpr *X86TargetLowering::
1471 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1472 MCContext &Ctx) const {
1473 // X86-64 uses RIP relative addressing based on the jump table label.
1474 if (Subtarget->isPICStyleRIPRel())
1475 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1477 // Otherwise, the reference is relative to the PIC base.
1478 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1481 // FIXME: Why this routine is here? Move to RegInfo!
1482 std::pair<const TargetRegisterClass*, uint8_t>
1483 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1484 const TargetRegisterClass *RRC = 0;
1486 switch (VT.getSimpleVT().SimpleTy) {
1488 return TargetLowering::findRepresentativeClass(VT);
1489 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1490 RRC = Subtarget->is64Bit() ?
1491 (const TargetRegisterClass*)&X86::GR64RegClass :
1492 (const TargetRegisterClass*)&X86::GR32RegClass;
1495 RRC = &X86::VR64RegClass;
1497 case MVT::f32: case MVT::f64:
1498 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1499 case MVT::v4f32: case MVT::v2f64:
1500 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1502 RRC = &X86::VR128RegClass;
1505 return std::make_pair(RRC, Cost);
1508 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1509 unsigned &Offset) const {
1510 if (!Subtarget->isTargetLinux())
1513 if (Subtarget->is64Bit()) {
1514 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1516 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1529 //===----------------------------------------------------------------------===//
1530 // Return Value Calling Convention Implementation
1531 //===----------------------------------------------------------------------===//
1533 #include "X86GenCallingConv.inc"
1536 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1537 MachineFunction &MF, bool isVarArg,
1538 const SmallVectorImpl<ISD::OutputArg> &Outs,
1539 LLVMContext &Context) const {
1540 SmallVector<CCValAssign, 16> RVLocs;
1541 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1543 return CCInfo.CheckReturn(Outs, RetCC_X86);
1547 X86TargetLowering::LowerReturn(SDValue Chain,
1548 CallingConv::ID CallConv, bool isVarArg,
1549 const SmallVectorImpl<ISD::OutputArg> &Outs,
1550 const SmallVectorImpl<SDValue> &OutVals,
1551 DebugLoc dl, SelectionDAG &DAG) const {
1552 MachineFunction &MF = DAG.getMachineFunction();
1553 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1555 SmallVector<CCValAssign, 16> RVLocs;
1556 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1557 RVLocs, *DAG.getContext());
1558 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1560 // Add the regs to the liveout set for the function.
1561 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1562 for (unsigned i = 0; i != RVLocs.size(); ++i)
1563 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1564 MRI.addLiveOut(RVLocs[i].getLocReg());
1568 SmallVector<SDValue, 6> RetOps;
1569 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1570 // Operand #1 = Bytes To Pop
1571 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1574 // Copy the result values into the output registers.
1575 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1576 CCValAssign &VA = RVLocs[i];
1577 assert(VA.isRegLoc() && "Can only return in registers!");
1578 SDValue ValToCopy = OutVals[i];
1579 EVT ValVT = ValToCopy.getValueType();
1581 // Promote values to the appropriate types
1582 if (VA.getLocInfo() == CCValAssign::SExt)
1583 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1584 else if (VA.getLocInfo() == CCValAssign::ZExt)
1585 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1586 else if (VA.getLocInfo() == CCValAssign::AExt)
1587 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1588 else if (VA.getLocInfo() == CCValAssign::BCvt)
1589 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1591 // If this is x86-64, and we disabled SSE, we can't return FP values,
1592 // or SSE or MMX vectors.
1593 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1594 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1595 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1596 report_fatal_error("SSE register return with SSE disabled");
1598 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1599 // llvm-gcc has never done it right and no one has noticed, so this
1600 // should be OK for now.
1601 if (ValVT == MVT::f64 &&
1602 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1603 report_fatal_error("SSE2 register return with SSE2 disabled");
1605 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1606 // the RET instruction and handled by the FP Stackifier.
1607 if (VA.getLocReg() == X86::ST0 ||
1608 VA.getLocReg() == X86::ST1) {
1609 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1610 // change the value to the FP stack register class.
1611 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1612 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1613 RetOps.push_back(ValToCopy);
1614 // Don't emit a copytoreg.
1618 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1619 // which is returned in RAX / RDX.
1620 if (Subtarget->is64Bit()) {
1621 if (ValVT == MVT::x86mmx) {
1622 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1623 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1624 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1626 // If we don't have SSE2 available, convert to v4f32 so the generated
1627 // register is legal.
1628 if (!Subtarget->hasSSE2())
1629 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1634 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1635 Flag = Chain.getValue(1);
1638 // The x86-64 ABI for returning structs by value requires that we copy
1639 // the sret argument into %rax for the return. We saved the argument into
1640 // a virtual register in the entry block, so now we copy the value out
1642 if (Subtarget->is64Bit() &&
1643 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1644 MachineFunction &MF = DAG.getMachineFunction();
1645 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1646 unsigned Reg = FuncInfo->getSRetReturnReg();
1648 "SRetReturnReg should have been set in LowerFormalArguments().");
1649 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1651 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1652 Flag = Chain.getValue(1);
1654 // RAX now acts like a return value.
1655 MRI.addLiveOut(X86::RAX);
1658 RetOps[0] = Chain; // Update chain.
1660 // Add the flag if we have it.
1662 RetOps.push_back(Flag);
1664 return DAG.getNode(X86ISD::RET_FLAG, dl,
1665 MVT::Other, &RetOps[0], RetOps.size());
1668 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1669 if (N->getNumValues() != 1)
1671 if (!N->hasNUsesOfValue(1, 0))
1674 SDValue TCChain = Chain;
1675 SDNode *Copy = *N->use_begin();
1676 if (Copy->getOpcode() == ISD::CopyToReg) {
1677 // If the copy has a glue operand, we conservatively assume it isn't safe to
1678 // perform a tail call.
1679 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1681 TCChain = Copy->getOperand(0);
1682 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1685 bool HasRet = false;
1686 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1688 if (UI->getOpcode() != X86ISD::RET_FLAG)
1701 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1702 ISD::NodeType ExtendKind) const {
1704 // TODO: Is this also valid on 32-bit?
1705 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1706 ReturnMVT = MVT::i8;
1708 ReturnMVT = MVT::i32;
1710 EVT MinVT = getRegisterType(Context, ReturnMVT);
1711 return VT.bitsLT(MinVT) ? MinVT : VT;
1714 /// LowerCallResult - Lower the result values of a call into the
1715 /// appropriate copies out of appropriate physical registers.
1718 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1719 CallingConv::ID CallConv, bool isVarArg,
1720 const SmallVectorImpl<ISD::InputArg> &Ins,
1721 DebugLoc dl, SelectionDAG &DAG,
1722 SmallVectorImpl<SDValue> &InVals) const {
1724 // Assign locations to each value returned by this call.
1725 SmallVector<CCValAssign, 16> RVLocs;
1726 bool Is64Bit = Subtarget->is64Bit();
1727 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1728 getTargetMachine(), RVLocs, *DAG.getContext());
1729 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1731 // Copy all of the result registers out of their specified physreg.
1732 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1733 CCValAssign &VA = RVLocs[i];
1734 EVT CopyVT = VA.getValVT();
1736 // If this is x86-64, and we disabled SSE, we can't return FP values
1737 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1738 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1739 report_fatal_error("SSE register return with SSE disabled");
1744 // If this is a call to a function that returns an fp value on the floating
1745 // point stack, we must guarantee the value is popped from the stack, so
1746 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1747 // if the return value is not used. We use the FpPOP_RETVAL instruction
1749 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1750 // If we prefer to use the value in xmm registers, copy it out as f80 and
1751 // use a truncate to move it from fp stack reg to xmm reg.
1752 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1753 SDValue Ops[] = { Chain, InFlag };
1754 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1755 MVT::Other, MVT::Glue, Ops, 2), 1);
1756 Val = Chain.getValue(0);
1758 // Round the f80 to the right size, which also moves it to the appropriate
1760 if (CopyVT != VA.getValVT())
1761 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1762 // This truncation won't change the value.
1763 DAG.getIntPtrConstant(1));
1765 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1766 CopyVT, InFlag).getValue(1);
1767 Val = Chain.getValue(0);
1769 InFlag = Chain.getValue(2);
1770 InVals.push_back(Val);
1777 //===----------------------------------------------------------------------===//
1778 // C & StdCall & Fast Calling Convention implementation
1779 //===----------------------------------------------------------------------===//
1780 // StdCall calling convention seems to be standard for many Windows' API
1781 // routines and around. It differs from C calling convention just a little:
1782 // callee should clean up the stack, not caller. Symbols should be also
1783 // decorated in some fancy way :) It doesn't support any vector arguments.
1784 // For info on fast calling convention see Fast Calling Convention (tail call)
1785 // implementation LowerX86_32FastCCCallTo.
1787 /// CallIsStructReturn - Determines whether a call uses struct return
1789 enum StructReturnType {
1794 static StructReturnType
1795 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1797 return NotStructReturn;
1799 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1800 if (!Flags.isSRet())
1801 return NotStructReturn;
1802 if (Flags.isInReg())
1803 return RegStructReturn;
1804 return StackStructReturn;
1807 /// ArgsAreStructReturn - Determines whether a function uses struct
1808 /// return semantics.
1809 static StructReturnType
1810 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1812 return NotStructReturn;
1814 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1815 if (!Flags.isSRet())
1816 return NotStructReturn;
1817 if (Flags.isInReg())
1818 return RegStructReturn;
1819 return StackStructReturn;
1822 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1823 /// by "Src" to address "Dst" with size and alignment information specified by
1824 /// the specific parameter attribute. The copy will be passed as a byval
1825 /// function parameter.
1827 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1828 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1830 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1832 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1833 /*isVolatile*/false, /*AlwaysInline=*/true,
1834 MachinePointerInfo(), MachinePointerInfo());
1837 /// IsTailCallConvention - Return true if the calling convention is one that
1838 /// supports tail call optimization.
1839 static bool IsTailCallConvention(CallingConv::ID CC) {
1840 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1841 CC == CallingConv::HiPE);
1844 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1845 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1849 CallingConv::ID CalleeCC = CS.getCallingConv();
1850 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1856 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1857 /// a tailcall target by changing its ABI.
1858 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1859 bool GuaranteedTailCallOpt) {
1860 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1864 X86TargetLowering::LowerMemArgument(SDValue Chain,
1865 CallingConv::ID CallConv,
1866 const SmallVectorImpl<ISD::InputArg> &Ins,
1867 DebugLoc dl, SelectionDAG &DAG,
1868 const CCValAssign &VA,
1869 MachineFrameInfo *MFI,
1871 // Create the nodes corresponding to a load from this parameter slot.
1872 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1873 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1874 getTargetMachine().Options.GuaranteedTailCallOpt);
1875 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1878 // If value is passed by pointer we have address passed instead of the value
1880 if (VA.getLocInfo() == CCValAssign::Indirect)
1881 ValVT = VA.getLocVT();
1883 ValVT = VA.getValVT();
1885 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1886 // changed with more analysis.
1887 // In case of tail call optimization mark all arguments mutable. Since they
1888 // could be overwritten by lowering of arguments in case of a tail call.
1889 if (Flags.isByVal()) {
1890 unsigned Bytes = Flags.getByValSize();
1891 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1892 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1893 return DAG.getFrameIndex(FI, getPointerTy());
1895 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1896 VA.getLocMemOffset(), isImmutable);
1897 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1898 return DAG.getLoad(ValVT, dl, Chain, FIN,
1899 MachinePointerInfo::getFixedStack(FI),
1900 false, false, false, 0);
1905 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1906 CallingConv::ID CallConv,
1908 const SmallVectorImpl<ISD::InputArg> &Ins,
1911 SmallVectorImpl<SDValue> &InVals)
1913 MachineFunction &MF = DAG.getMachineFunction();
1914 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1916 const Function* Fn = MF.getFunction();
1917 if (Fn->hasExternalLinkage() &&
1918 Subtarget->isTargetCygMing() &&
1919 Fn->getName() == "main")
1920 FuncInfo->setForceFramePointer(true);
1922 MachineFrameInfo *MFI = MF.getFrameInfo();
1923 bool Is64Bit = Subtarget->is64Bit();
1924 bool IsWindows = Subtarget->isTargetWindows();
1925 bool IsWin64 = Subtarget->isTargetWin64();
1927 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1928 "Var args not supported with calling convention fastcc, ghc or hipe");
1930 // Assign locations to all of the incoming arguments.
1931 SmallVector<CCValAssign, 16> ArgLocs;
1932 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1933 ArgLocs, *DAG.getContext());
1935 // Allocate shadow area for Win64
1937 CCInfo.AllocateStack(32, 8);
1940 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1942 unsigned LastVal = ~0U;
1944 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1945 CCValAssign &VA = ArgLocs[i];
1946 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1948 assert(VA.getValNo() != LastVal &&
1949 "Don't support value assigned to multiple locs yet");
1951 LastVal = VA.getValNo();
1953 if (VA.isRegLoc()) {
1954 EVT RegVT = VA.getLocVT();
1955 const TargetRegisterClass *RC;
1956 if (RegVT == MVT::i32)
1957 RC = &X86::GR32RegClass;
1958 else if (Is64Bit && RegVT == MVT::i64)
1959 RC = &X86::GR64RegClass;
1960 else if (RegVT == MVT::f32)
1961 RC = &X86::FR32RegClass;
1962 else if (RegVT == MVT::f64)
1963 RC = &X86::FR64RegClass;
1964 else if (RegVT.is256BitVector())
1965 RC = &X86::VR256RegClass;
1966 else if (RegVT.is128BitVector())
1967 RC = &X86::VR128RegClass;
1968 else if (RegVT == MVT::x86mmx)
1969 RC = &X86::VR64RegClass;
1971 llvm_unreachable("Unknown argument type!");
1973 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1974 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1976 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1977 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1979 if (VA.getLocInfo() == CCValAssign::SExt)
1980 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1981 DAG.getValueType(VA.getValVT()));
1982 else if (VA.getLocInfo() == CCValAssign::ZExt)
1983 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1984 DAG.getValueType(VA.getValVT()));
1985 else if (VA.getLocInfo() == CCValAssign::BCvt)
1986 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1988 if (VA.isExtInLoc()) {
1989 // Handle MMX values passed in XMM regs.
1990 if (RegVT.isVector()) {
1991 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1994 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1997 assert(VA.isMemLoc());
1998 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2001 // If value is passed via pointer - do a load.
2002 if (VA.getLocInfo() == CCValAssign::Indirect)
2003 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2004 MachinePointerInfo(), false, false, false, 0);
2006 InVals.push_back(ArgValue);
2009 // The x86-64 ABI for returning structs by value requires that we copy
2010 // the sret argument into %rax for the return. Save the argument into
2011 // a virtual register so that we can access it from the return points.
2012 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
2013 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2014 unsigned Reg = FuncInfo->getSRetReturnReg();
2016 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
2017 FuncInfo->setSRetReturnReg(Reg);
2019 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2020 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2023 unsigned StackSize = CCInfo.getNextStackOffset();
2024 // Align stack specially for tail calls.
2025 if (FuncIsMadeTailCallSafe(CallConv,
2026 MF.getTarget().Options.GuaranteedTailCallOpt))
2027 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2029 // If the function takes variable number of arguments, make a frame index for
2030 // the start of the first vararg value... for expansion of llvm.va_start.
2032 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2033 CallConv != CallingConv::X86_ThisCall)) {
2034 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2037 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2039 // FIXME: We should really autogenerate these arrays
2040 static const uint16_t GPR64ArgRegsWin64[] = {
2041 X86::RCX, X86::RDX, X86::R8, X86::R9
2043 static const uint16_t GPR64ArgRegs64Bit[] = {
2044 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2046 static const uint16_t XMMArgRegs64Bit[] = {
2047 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2048 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2050 const uint16_t *GPR64ArgRegs;
2051 unsigned NumXMMRegs = 0;
2054 // The XMM registers which might contain var arg parameters are shadowed
2055 // in their paired GPR. So we only need to save the GPR to their home
2057 TotalNumIntRegs = 4;
2058 GPR64ArgRegs = GPR64ArgRegsWin64;
2060 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2061 GPR64ArgRegs = GPR64ArgRegs64Bit;
2063 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2066 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2069 bool NoImplicitFloatOps = Fn->getFnAttributes().
2070 hasAttribute(Attributes::NoImplicitFloat);
2071 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2072 "SSE register cannot be used when SSE is disabled!");
2073 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2074 NoImplicitFloatOps) &&
2075 "SSE register cannot be used when SSE is disabled!");
2076 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2077 !Subtarget->hasSSE1())
2078 // Kernel mode asks for SSE to be disabled, so don't push them
2080 TotalNumXMMRegs = 0;
2083 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2084 // Get to the caller-allocated home save location. Add 8 to account
2085 // for the return address.
2086 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2087 FuncInfo->setRegSaveFrameIndex(
2088 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2089 // Fixup to set vararg frame on shadow area (4 x i64).
2091 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2093 // For X86-64, if there are vararg parameters that are passed via
2094 // registers, then we must store them to their spots on the stack so
2095 // they may be loaded by deferencing the result of va_next.
2096 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2097 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2098 FuncInfo->setRegSaveFrameIndex(
2099 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2103 // Store the integer parameter registers.
2104 SmallVector<SDValue, 8> MemOps;
2105 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2107 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2108 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2109 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2110 DAG.getIntPtrConstant(Offset));
2111 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2112 &X86::GR64RegClass);
2113 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2115 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2116 MachinePointerInfo::getFixedStack(
2117 FuncInfo->getRegSaveFrameIndex(), Offset),
2119 MemOps.push_back(Store);
2123 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2124 // Now store the XMM (fp + vector) parameter registers.
2125 SmallVector<SDValue, 11> SaveXMMOps;
2126 SaveXMMOps.push_back(Chain);
2128 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2129 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2130 SaveXMMOps.push_back(ALVal);
2132 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2133 FuncInfo->getRegSaveFrameIndex()));
2134 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2135 FuncInfo->getVarArgsFPOffset()));
2137 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2138 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2139 &X86::VR128RegClass);
2140 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2141 SaveXMMOps.push_back(Val);
2143 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2145 &SaveXMMOps[0], SaveXMMOps.size()));
2148 if (!MemOps.empty())
2149 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2150 &MemOps[0], MemOps.size());
2154 // Some CCs need callee pop.
2155 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2156 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2157 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2159 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2160 // If this is an sret function, the return should pop the hidden pointer.
2161 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2162 argsAreStructReturn(Ins) == StackStructReturn)
2163 FuncInfo->setBytesToPopOnReturn(4);
2167 // RegSaveFrameIndex is X86-64 only.
2168 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2169 if (CallConv == CallingConv::X86_FastCall ||
2170 CallConv == CallingConv::X86_ThisCall)
2171 // fastcc functions can't have varargs.
2172 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2175 FuncInfo->setArgumentStackSize(StackSize);
2181 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2182 SDValue StackPtr, SDValue Arg,
2183 DebugLoc dl, SelectionDAG &DAG,
2184 const CCValAssign &VA,
2185 ISD::ArgFlagsTy Flags) const {
2186 unsigned LocMemOffset = VA.getLocMemOffset();
2187 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2188 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2189 if (Flags.isByVal())
2190 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2192 return DAG.getStore(Chain, dl, Arg, PtrOff,
2193 MachinePointerInfo::getStack(LocMemOffset),
2197 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2198 /// optimization is performed and it is required.
2200 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2201 SDValue &OutRetAddr, SDValue Chain,
2202 bool IsTailCall, bool Is64Bit,
2203 int FPDiff, DebugLoc dl) const {
2204 // Adjust the Return address stack slot.
2205 EVT VT = getPointerTy();
2206 OutRetAddr = getReturnAddressFrameIndex(DAG);
2208 // Load the "old" Return address.
2209 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2210 false, false, false, 0);
2211 return SDValue(OutRetAddr.getNode(), 1);
2214 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2215 /// optimization is performed and it is required (FPDiff!=0).
2217 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2218 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2219 unsigned SlotSize, int FPDiff, DebugLoc dl) {
2220 // Store the return address to the appropriate stack slot.
2221 if (!FPDiff) return Chain;
2222 // Calculate the new stack slot for the return address.
2223 int NewReturnAddrFI =
2224 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2225 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2226 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2227 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2233 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2234 SmallVectorImpl<SDValue> &InVals) const {
2235 SelectionDAG &DAG = CLI.DAG;
2236 DebugLoc &dl = CLI.DL;
2237 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2238 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2239 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2240 SDValue Chain = CLI.Chain;
2241 SDValue Callee = CLI.Callee;
2242 CallingConv::ID CallConv = CLI.CallConv;
2243 bool &isTailCall = CLI.IsTailCall;
2244 bool isVarArg = CLI.IsVarArg;
2246 MachineFunction &MF = DAG.getMachineFunction();
2247 bool Is64Bit = Subtarget->is64Bit();
2248 bool IsWin64 = Subtarget->isTargetWin64();
2249 bool IsWindows = Subtarget->isTargetWindows();
2250 StructReturnType SR = callIsStructReturn(Outs);
2251 bool IsSibcall = false;
2253 if (MF.getTarget().Options.DisableTailCalls)
2257 // Check if it's really possible to do a tail call.
2258 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2259 isVarArg, SR != NotStructReturn,
2260 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2261 Outs, OutVals, Ins, DAG);
2263 // Sibcalls are automatically detected tailcalls which do not require
2265 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2272 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2273 "Var args not supported with calling convention fastcc, ghc or hipe");
2275 // Analyze operands of the call, assigning locations to each operand.
2276 SmallVector<CCValAssign, 16> ArgLocs;
2277 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2278 ArgLocs, *DAG.getContext());
2280 // Allocate shadow area for Win64
2282 CCInfo.AllocateStack(32, 8);
2285 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2287 // Get a count of how many bytes are to be pushed on the stack.
2288 unsigned NumBytes = CCInfo.getNextStackOffset();
2290 // This is a sibcall. The memory operands are available in caller's
2291 // own caller's stack.
2293 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2294 IsTailCallConvention(CallConv))
2295 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2298 if (isTailCall && !IsSibcall) {
2299 // Lower arguments at fp - stackoffset + fpdiff.
2300 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2301 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2303 FPDiff = NumBytesCallerPushed - NumBytes;
2305 // Set the delta of movement of the returnaddr stackslot.
2306 // But only set if delta is greater than previous delta.
2307 if (FPDiff < X86Info->getTCReturnAddrDelta())
2308 X86Info->setTCReturnAddrDelta(FPDiff);
2312 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2314 SDValue RetAddrFrIdx;
2315 // Load return address for tail calls.
2316 if (isTailCall && FPDiff)
2317 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2318 Is64Bit, FPDiff, dl);
2320 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2321 SmallVector<SDValue, 8> MemOpChains;
2324 // Walk the register/memloc assignments, inserting copies/loads. In the case
2325 // of tail call optimization arguments are handle later.
2326 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2327 CCValAssign &VA = ArgLocs[i];
2328 EVT RegVT = VA.getLocVT();
2329 SDValue Arg = OutVals[i];
2330 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2331 bool isByVal = Flags.isByVal();
2333 // Promote the value if needed.
2334 switch (VA.getLocInfo()) {
2335 default: llvm_unreachable("Unknown loc info!");
2336 case CCValAssign::Full: break;
2337 case CCValAssign::SExt:
2338 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2340 case CCValAssign::ZExt:
2341 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2343 case CCValAssign::AExt:
2344 if (RegVT.is128BitVector()) {
2345 // Special case: passing MMX values in XMM registers.
2346 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2347 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2348 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2350 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2352 case CCValAssign::BCvt:
2353 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2355 case CCValAssign::Indirect: {
2356 // Store the argument.
2357 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2358 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2359 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2360 MachinePointerInfo::getFixedStack(FI),
2367 if (VA.isRegLoc()) {
2368 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2369 if (isVarArg && IsWin64) {
2370 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2371 // shadow reg if callee is a varargs function.
2372 unsigned ShadowReg = 0;
2373 switch (VA.getLocReg()) {
2374 case X86::XMM0: ShadowReg = X86::RCX; break;
2375 case X86::XMM1: ShadowReg = X86::RDX; break;
2376 case X86::XMM2: ShadowReg = X86::R8; break;
2377 case X86::XMM3: ShadowReg = X86::R9; break;
2380 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2382 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2383 assert(VA.isMemLoc());
2384 if (StackPtr.getNode() == 0)
2385 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2387 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2388 dl, DAG, VA, Flags));
2392 if (!MemOpChains.empty())
2393 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2394 &MemOpChains[0], MemOpChains.size());
2396 if (Subtarget->isPICStyleGOT()) {
2397 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2400 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2401 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2403 // If we are tail calling and generating PIC/GOT style code load the
2404 // address of the callee into ECX. The value in ecx is used as target of
2405 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2406 // for tail calls on PIC/GOT architectures. Normally we would just put the
2407 // address of GOT into ebx and then call target@PLT. But for tail calls
2408 // ebx would be restored (since ebx is callee saved) before jumping to the
2411 // Note: The actual moving to ECX is done further down.
2412 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2413 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2414 !G->getGlobal()->hasProtectedVisibility())
2415 Callee = LowerGlobalAddress(Callee, DAG);
2416 else if (isa<ExternalSymbolSDNode>(Callee))
2417 Callee = LowerExternalSymbol(Callee, DAG);
2421 if (Is64Bit && isVarArg && !IsWin64) {
2422 // From AMD64 ABI document:
2423 // For calls that may call functions that use varargs or stdargs
2424 // (prototype-less calls or calls to functions containing ellipsis (...) in
2425 // the declaration) %al is used as hidden argument to specify the number
2426 // of SSE registers used. The contents of %al do not need to match exactly
2427 // the number of registers, but must be an ubound on the number of SSE
2428 // registers used and is in the range 0 - 8 inclusive.
2430 // Count the number of XMM registers allocated.
2431 static const uint16_t XMMArgRegs[] = {
2432 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2433 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2435 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2436 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2437 && "SSE registers cannot be used when SSE is disabled");
2439 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2440 DAG.getConstant(NumXMMRegs, MVT::i8)));
2443 // For tail calls lower the arguments to the 'real' stack slot.
2445 // Force all the incoming stack arguments to be loaded from the stack
2446 // before any new outgoing arguments are stored to the stack, because the
2447 // outgoing stack slots may alias the incoming argument stack slots, and
2448 // the alias isn't otherwise explicit. This is slightly more conservative
2449 // than necessary, because it means that each store effectively depends
2450 // on every argument instead of just those arguments it would clobber.
2451 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2453 SmallVector<SDValue, 8> MemOpChains2;
2456 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2457 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2458 CCValAssign &VA = ArgLocs[i];
2461 assert(VA.isMemLoc());
2462 SDValue Arg = OutVals[i];
2463 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2464 // Create frame index.
2465 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2466 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2467 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2468 FIN = DAG.getFrameIndex(FI, getPointerTy());
2470 if (Flags.isByVal()) {
2471 // Copy relative to framepointer.
2472 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2473 if (StackPtr.getNode() == 0)
2474 StackPtr = DAG.getCopyFromReg(Chain, dl,
2475 RegInfo->getStackRegister(),
2477 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2479 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2483 // Store relative to framepointer.
2484 MemOpChains2.push_back(
2485 DAG.getStore(ArgChain, dl, Arg, FIN,
2486 MachinePointerInfo::getFixedStack(FI),
2492 if (!MemOpChains2.empty())
2493 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2494 &MemOpChains2[0], MemOpChains2.size());
2496 // Store the return address to the appropriate stack slot.
2497 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2498 getPointerTy(), RegInfo->getSlotSize(),
2502 // Build a sequence of copy-to-reg nodes chained together with token chain
2503 // and flag operands which copy the outgoing args into registers.
2505 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2506 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2507 RegsToPass[i].second, InFlag);
2508 InFlag = Chain.getValue(1);
2511 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2512 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2513 // In the 64-bit large code model, we have to make all calls
2514 // through a register, since the call instruction's 32-bit
2515 // pc-relative offset may not be large enough to hold the whole
2517 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2518 // If the callee is a GlobalAddress node (quite common, every direct call
2519 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2522 // We should use extra load for direct calls to dllimported functions in
2524 const GlobalValue *GV = G->getGlobal();
2525 if (!GV->hasDLLImportLinkage()) {
2526 unsigned char OpFlags = 0;
2527 bool ExtraLoad = false;
2528 unsigned WrapperKind = ISD::DELETED_NODE;
2530 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2531 // external symbols most go through the PLT in PIC mode. If the symbol
2532 // has hidden or protected visibility, or if it is static or local, then
2533 // we don't need to use the PLT - we can directly call it.
2534 if (Subtarget->isTargetELF() &&
2535 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2536 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2537 OpFlags = X86II::MO_PLT;
2538 } else if (Subtarget->isPICStyleStubAny() &&
2539 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2540 (!Subtarget->getTargetTriple().isMacOSX() ||
2541 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2542 // PC-relative references to external symbols should go through $stub,
2543 // unless we're building with the leopard linker or later, which
2544 // automatically synthesizes these stubs.
2545 OpFlags = X86II::MO_DARWIN_STUB;
2546 } else if (Subtarget->isPICStyleRIPRel() &&
2547 isa<Function>(GV) &&
2548 cast<Function>(GV)->getFnAttributes().
2549 hasAttribute(Attributes::NonLazyBind)) {
2550 // If the function is marked as non-lazy, generate an indirect call
2551 // which loads from the GOT directly. This avoids runtime overhead
2552 // at the cost of eager binding (and one extra byte of encoding).
2553 OpFlags = X86II::MO_GOTPCREL;
2554 WrapperKind = X86ISD::WrapperRIP;
2558 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2559 G->getOffset(), OpFlags);
2561 // Add a wrapper if needed.
2562 if (WrapperKind != ISD::DELETED_NODE)
2563 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2564 // Add extra indirection if needed.
2566 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2567 MachinePointerInfo::getGOT(),
2568 false, false, false, 0);
2570 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2571 unsigned char OpFlags = 0;
2573 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2574 // external symbols should go through the PLT.
2575 if (Subtarget->isTargetELF() &&
2576 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2577 OpFlags = X86II::MO_PLT;
2578 } else if (Subtarget->isPICStyleStubAny() &&
2579 (!Subtarget->getTargetTriple().isMacOSX() ||
2580 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2581 // PC-relative references to external symbols should go through $stub,
2582 // unless we're building with the leopard linker or later, which
2583 // automatically synthesizes these stubs.
2584 OpFlags = X86II::MO_DARWIN_STUB;
2587 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2591 // Returns a chain & a flag for retval copy to use.
2592 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2593 SmallVector<SDValue, 8> Ops;
2595 if (!IsSibcall && isTailCall) {
2596 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2597 DAG.getIntPtrConstant(0, true), InFlag);
2598 InFlag = Chain.getValue(1);
2601 Ops.push_back(Chain);
2602 Ops.push_back(Callee);
2605 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2607 // Add argument registers to the end of the list so that they are known live
2609 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2610 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2611 RegsToPass[i].second.getValueType()));
2613 // Add a register mask operand representing the call-preserved registers.
2614 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2615 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2616 assert(Mask && "Missing call preserved mask for calling convention");
2617 Ops.push_back(DAG.getRegisterMask(Mask));
2619 if (InFlag.getNode())
2620 Ops.push_back(InFlag);
2624 //// If this is the first return lowered for this function, add the regs
2625 //// to the liveout set for the function.
2626 // This isn't right, although it's probably harmless on x86; liveouts
2627 // should be computed from returns not tail calls. Consider a void
2628 // function making a tail call to a function returning int.
2629 return DAG.getNode(X86ISD::TC_RETURN, dl,
2630 NodeTys, &Ops[0], Ops.size());
2633 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2634 InFlag = Chain.getValue(1);
2636 // Create the CALLSEQ_END node.
2637 unsigned NumBytesForCalleeToPush;
2638 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2639 getTargetMachine().Options.GuaranteedTailCallOpt))
2640 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2641 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2642 SR == StackStructReturn)
2643 // If this is a call to a struct-return function, the callee
2644 // pops the hidden struct pointer, so we have to push it back.
2645 // This is common for Darwin/X86, Linux & Mingw32 targets.
2646 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2647 NumBytesForCalleeToPush = 4;
2649 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2651 // Returns a flag for retval copy to use.
2653 Chain = DAG.getCALLSEQ_END(Chain,
2654 DAG.getIntPtrConstant(NumBytes, true),
2655 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2658 InFlag = Chain.getValue(1);
2661 // Handle result values, copying them out of physregs into vregs that we
2663 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2664 Ins, dl, DAG, InVals);
2668 //===----------------------------------------------------------------------===//
2669 // Fast Calling Convention (tail call) implementation
2670 //===----------------------------------------------------------------------===//
2672 // Like std call, callee cleans arguments, convention except that ECX is
2673 // reserved for storing the tail called function address. Only 2 registers are
2674 // free for argument passing (inreg). Tail call optimization is performed
2676 // * tailcallopt is enabled
2677 // * caller/callee are fastcc
2678 // On X86_64 architecture with GOT-style position independent code only local
2679 // (within module) calls are supported at the moment.
2680 // To keep the stack aligned according to platform abi the function
2681 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2682 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2683 // If a tail called function callee has more arguments than the caller the
2684 // caller needs to make sure that there is room to move the RETADDR to. This is
2685 // achieved by reserving an area the size of the argument delta right after the
2686 // original REtADDR, but before the saved framepointer or the spilled registers
2687 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2699 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2700 /// for a 16 byte align requirement.
2702 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2703 SelectionDAG& DAG) const {
2704 MachineFunction &MF = DAG.getMachineFunction();
2705 const TargetMachine &TM = MF.getTarget();
2706 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2707 unsigned StackAlignment = TFI.getStackAlignment();
2708 uint64_t AlignMask = StackAlignment - 1;
2709 int64_t Offset = StackSize;
2710 unsigned SlotSize = RegInfo->getSlotSize();
2711 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2712 // Number smaller than 12 so just add the difference.
2713 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2715 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2716 Offset = ((~AlignMask) & Offset) + StackAlignment +
2717 (StackAlignment-SlotSize);
2722 /// MatchingStackOffset - Return true if the given stack call argument is
2723 /// already available in the same position (relatively) of the caller's
2724 /// incoming argument stack.
2726 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2727 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2728 const X86InstrInfo *TII) {
2729 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2731 if (Arg.getOpcode() == ISD::CopyFromReg) {
2732 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2733 if (!TargetRegisterInfo::isVirtualRegister(VR))
2735 MachineInstr *Def = MRI->getVRegDef(VR);
2738 if (!Flags.isByVal()) {
2739 if (!TII->isLoadFromStackSlot(Def, FI))
2742 unsigned Opcode = Def->getOpcode();
2743 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2744 Def->getOperand(1).isFI()) {
2745 FI = Def->getOperand(1).getIndex();
2746 Bytes = Flags.getByValSize();
2750 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2751 if (Flags.isByVal())
2752 // ByVal argument is passed in as a pointer but it's now being
2753 // dereferenced. e.g.
2754 // define @foo(%struct.X* %A) {
2755 // tail call @bar(%struct.X* byval %A)
2758 SDValue Ptr = Ld->getBasePtr();
2759 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2762 FI = FINode->getIndex();
2763 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2764 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2765 FI = FINode->getIndex();
2766 Bytes = Flags.getByValSize();
2770 assert(FI != INT_MAX);
2771 if (!MFI->isFixedObjectIndex(FI))
2773 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2776 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2777 /// for tail call optimization. Targets which want to do tail call
2778 /// optimization should implement this function.
2780 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2781 CallingConv::ID CalleeCC,
2783 bool isCalleeStructRet,
2784 bool isCallerStructRet,
2786 const SmallVectorImpl<ISD::OutputArg> &Outs,
2787 const SmallVectorImpl<SDValue> &OutVals,
2788 const SmallVectorImpl<ISD::InputArg> &Ins,
2789 SelectionDAG& DAG) const {
2790 if (!IsTailCallConvention(CalleeCC) &&
2791 CalleeCC != CallingConv::C)
2794 // If -tailcallopt is specified, make fastcc functions tail-callable.
2795 const MachineFunction &MF = DAG.getMachineFunction();
2796 const Function *CallerF = DAG.getMachineFunction().getFunction();
2798 // If the function return type is x86_fp80 and the callee return type is not,
2799 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2800 // perform a tailcall optimization here.
2801 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
2804 CallingConv::ID CallerCC = CallerF->getCallingConv();
2805 bool CCMatch = CallerCC == CalleeCC;
2807 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2808 if (IsTailCallConvention(CalleeCC) && CCMatch)
2813 // Look for obvious safe cases to perform tail call optimization that do not
2814 // require ABI changes. This is what gcc calls sibcall.
2816 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2817 // emit a special epilogue.
2818 if (RegInfo->needsStackRealignment(MF))
2821 // Also avoid sibcall optimization if either caller or callee uses struct
2822 // return semantics.
2823 if (isCalleeStructRet || isCallerStructRet)
2826 // An stdcall caller is expected to clean up its arguments; the callee
2827 // isn't going to do that.
2828 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2831 // Do not sibcall optimize vararg calls unless all arguments are passed via
2833 if (isVarArg && !Outs.empty()) {
2835 // Optimizing for varargs on Win64 is unlikely to be safe without
2836 // additional testing.
2837 if (Subtarget->isTargetWin64())
2840 SmallVector<CCValAssign, 16> ArgLocs;
2841 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2842 getTargetMachine(), ArgLocs, *DAG.getContext());
2844 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2845 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2846 if (!ArgLocs[i].isRegLoc())
2850 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2851 // stack. Therefore, if it's not used by the call it is not safe to optimize
2852 // this into a sibcall.
2853 bool Unused = false;
2854 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2861 SmallVector<CCValAssign, 16> RVLocs;
2862 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2863 getTargetMachine(), RVLocs, *DAG.getContext());
2864 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2865 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2866 CCValAssign &VA = RVLocs[i];
2867 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2872 // If the calling conventions do not match, then we'd better make sure the
2873 // results are returned in the same way as what the caller expects.
2875 SmallVector<CCValAssign, 16> RVLocs1;
2876 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2877 getTargetMachine(), RVLocs1, *DAG.getContext());
2878 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2880 SmallVector<CCValAssign, 16> RVLocs2;
2881 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2882 getTargetMachine(), RVLocs2, *DAG.getContext());
2883 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2885 if (RVLocs1.size() != RVLocs2.size())
2887 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2888 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2890 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2892 if (RVLocs1[i].isRegLoc()) {
2893 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2896 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2902 // If the callee takes no arguments then go on to check the results of the
2904 if (!Outs.empty()) {
2905 // Check if stack adjustment is needed. For now, do not do this if any
2906 // argument is passed on the stack.
2907 SmallVector<CCValAssign, 16> ArgLocs;
2908 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2909 getTargetMachine(), ArgLocs, *DAG.getContext());
2911 // Allocate shadow area for Win64
2912 if (Subtarget->isTargetWin64()) {
2913 CCInfo.AllocateStack(32, 8);
2916 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2917 if (CCInfo.getNextStackOffset()) {
2918 MachineFunction &MF = DAG.getMachineFunction();
2919 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2922 // Check if the arguments are already laid out in the right way as
2923 // the caller's fixed stack objects.
2924 MachineFrameInfo *MFI = MF.getFrameInfo();
2925 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2926 const X86InstrInfo *TII =
2927 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
2928 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2929 CCValAssign &VA = ArgLocs[i];
2930 SDValue Arg = OutVals[i];
2931 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2932 if (VA.getLocInfo() == CCValAssign::Indirect)
2934 if (!VA.isRegLoc()) {
2935 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2942 // If the tailcall address may be in a register, then make sure it's
2943 // possible to register allocate for it. In 32-bit, the call address can
2944 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2945 // callee-saved registers are restored. These happen to be the same
2946 // registers used to pass 'inreg' arguments so watch out for those.
2947 if (!Subtarget->is64Bit() &&
2948 !isa<GlobalAddressSDNode>(Callee) &&
2949 !isa<ExternalSymbolSDNode>(Callee)) {
2950 unsigned NumInRegs = 0;
2951 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2952 CCValAssign &VA = ArgLocs[i];
2955 unsigned Reg = VA.getLocReg();
2958 case X86::EAX: case X86::EDX: case X86::ECX:
2959 if (++NumInRegs == 3)
2971 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
2972 const TargetLibraryInfo *libInfo) const {
2973 return X86::createFastISel(funcInfo, libInfo);
2977 //===----------------------------------------------------------------------===//
2978 // Other Lowering Hooks
2979 //===----------------------------------------------------------------------===//
2981 static bool MayFoldLoad(SDValue Op) {
2982 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2985 static bool MayFoldIntoStore(SDValue Op) {
2986 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2989 static bool isTargetShuffle(unsigned Opcode) {
2991 default: return false;
2992 case X86ISD::PSHUFD:
2993 case X86ISD::PSHUFHW:
2994 case X86ISD::PSHUFLW:
2996 case X86ISD::PALIGN:
2997 case X86ISD::MOVLHPS:
2998 case X86ISD::MOVLHPD:
2999 case X86ISD::MOVHLPS:
3000 case X86ISD::MOVLPS:
3001 case X86ISD::MOVLPD:
3002 case X86ISD::MOVSHDUP:
3003 case X86ISD::MOVSLDUP:
3004 case X86ISD::MOVDDUP:
3007 case X86ISD::UNPCKL:
3008 case X86ISD::UNPCKH:
3009 case X86ISD::VPERMILP:
3010 case X86ISD::VPERM2X128:
3011 case X86ISD::VPERMI:
3016 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3017 SDValue V1, SelectionDAG &DAG) {
3019 default: llvm_unreachable("Unknown x86 shuffle node");
3020 case X86ISD::MOVSHDUP:
3021 case X86ISD::MOVSLDUP:
3022 case X86ISD::MOVDDUP:
3023 return DAG.getNode(Opc, dl, VT, V1);
3027 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3028 SDValue V1, unsigned TargetMask,
3029 SelectionDAG &DAG) {
3031 default: llvm_unreachable("Unknown x86 shuffle node");
3032 case X86ISD::PSHUFD:
3033 case X86ISD::PSHUFHW:
3034 case X86ISD::PSHUFLW:
3035 case X86ISD::VPERMILP:
3036 case X86ISD::VPERMI:
3037 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3041 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3042 SDValue V1, SDValue V2, unsigned TargetMask,
3043 SelectionDAG &DAG) {
3045 default: llvm_unreachable("Unknown x86 shuffle node");
3046 case X86ISD::PALIGN:
3048 case X86ISD::VPERM2X128:
3049 return DAG.getNode(Opc, dl, VT, V1, V2,
3050 DAG.getConstant(TargetMask, MVT::i8));
3054 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3055 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3057 default: llvm_unreachable("Unknown x86 shuffle node");
3058 case X86ISD::MOVLHPS:
3059 case X86ISD::MOVLHPD:
3060 case X86ISD::MOVHLPS:
3061 case X86ISD::MOVLPS:
3062 case X86ISD::MOVLPD:
3065 case X86ISD::UNPCKL:
3066 case X86ISD::UNPCKH:
3067 return DAG.getNode(Opc, dl, VT, V1, V2);
3071 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3072 MachineFunction &MF = DAG.getMachineFunction();
3073 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3074 int ReturnAddrIndex = FuncInfo->getRAIndex();
3076 if (ReturnAddrIndex == 0) {
3077 // Set up a frame object for the return address.
3078 unsigned SlotSize = RegInfo->getSlotSize();
3079 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3081 FuncInfo->setRAIndex(ReturnAddrIndex);
3084 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3088 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3089 bool hasSymbolicDisplacement) {
3090 // Offset should fit into 32 bit immediate field.
3091 if (!isInt<32>(Offset))
3094 // If we don't have a symbolic displacement - we don't have any extra
3096 if (!hasSymbolicDisplacement)
3099 // FIXME: Some tweaks might be needed for medium code model.
3100 if (M != CodeModel::Small && M != CodeModel::Kernel)
3103 // For small code model we assume that latest object is 16MB before end of 31
3104 // bits boundary. We may also accept pretty large negative constants knowing
3105 // that all objects are in the positive half of address space.
3106 if (M == CodeModel::Small && Offset < 16*1024*1024)
3109 // For kernel code model we know that all object resist in the negative half
3110 // of 32bits address space. We may not accept negative offsets, since they may
3111 // be just off and we may accept pretty large positive ones.
3112 if (M == CodeModel::Kernel && Offset > 0)
3118 /// isCalleePop - Determines whether the callee is required to pop its
3119 /// own arguments. Callee pop is necessary to support tail calls.
3120 bool X86::isCalleePop(CallingConv::ID CallingConv,
3121 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3125 switch (CallingConv) {
3128 case CallingConv::X86_StdCall:
3130 case CallingConv::X86_FastCall:
3132 case CallingConv::X86_ThisCall:
3134 case CallingConv::Fast:
3136 case CallingConv::GHC:
3138 case CallingConv::HiPE:
3143 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3144 /// specific condition code, returning the condition code and the LHS/RHS of the
3145 /// comparison to make.
3146 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3147 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3149 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3150 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3151 // X > -1 -> X == 0, jump !sign.
3152 RHS = DAG.getConstant(0, RHS.getValueType());
3153 return X86::COND_NS;
3155 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3156 // X < 0 -> X == 0, jump on sign.
3159 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3161 RHS = DAG.getConstant(0, RHS.getValueType());
3162 return X86::COND_LE;
3166 switch (SetCCOpcode) {
3167 default: llvm_unreachable("Invalid integer condition!");
3168 case ISD::SETEQ: return X86::COND_E;
3169 case ISD::SETGT: return X86::COND_G;
3170 case ISD::SETGE: return X86::COND_GE;
3171 case ISD::SETLT: return X86::COND_L;
3172 case ISD::SETLE: return X86::COND_LE;
3173 case ISD::SETNE: return X86::COND_NE;
3174 case ISD::SETULT: return X86::COND_B;
3175 case ISD::SETUGT: return X86::COND_A;
3176 case ISD::SETULE: return X86::COND_BE;
3177 case ISD::SETUGE: return X86::COND_AE;
3181 // First determine if it is required or is profitable to flip the operands.
3183 // If LHS is a foldable load, but RHS is not, flip the condition.
3184 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3185 !ISD::isNON_EXTLoad(RHS.getNode())) {
3186 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3187 std::swap(LHS, RHS);
3190 switch (SetCCOpcode) {
3196 std::swap(LHS, RHS);
3200 // On a floating point condition, the flags are set as follows:
3202 // 0 | 0 | 0 | X > Y
3203 // 0 | 0 | 1 | X < Y
3204 // 1 | 0 | 0 | X == Y
3205 // 1 | 1 | 1 | unordered
3206 switch (SetCCOpcode) {
3207 default: llvm_unreachable("Condcode should be pre-legalized away");
3209 case ISD::SETEQ: return X86::COND_E;
3210 case ISD::SETOLT: // flipped
3212 case ISD::SETGT: return X86::COND_A;
3213 case ISD::SETOLE: // flipped
3215 case ISD::SETGE: return X86::COND_AE;
3216 case ISD::SETUGT: // flipped
3218 case ISD::SETLT: return X86::COND_B;
3219 case ISD::SETUGE: // flipped
3221 case ISD::SETLE: return X86::COND_BE;
3223 case ISD::SETNE: return X86::COND_NE;
3224 case ISD::SETUO: return X86::COND_P;
3225 case ISD::SETO: return X86::COND_NP;
3227 case ISD::SETUNE: return X86::COND_INVALID;
3231 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3232 /// code. Current x86 isa includes the following FP cmov instructions:
3233 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3234 static bool hasFPCMov(unsigned X86CC) {
3250 /// isFPImmLegal - Returns true if the target can instruction select the
3251 /// specified FP immediate natively. If false, the legalizer will
3252 /// materialize the FP immediate as a load from a constant pool.
3253 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3254 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3255 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3261 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3262 /// the specified range (L, H].
3263 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3264 return (Val < 0) || (Val >= Low && Val < Hi);
3267 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3268 /// specified value.
3269 static bool isUndefOrEqual(int Val, int CmpVal) {
3270 return (Val < 0 || Val == CmpVal);
3273 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3274 /// from position Pos and ending in Pos+Size, falls within the specified
3275 /// sequential range (L, L+Pos]. or is undef.
3276 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3277 unsigned Pos, unsigned Size, int Low) {
3278 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3279 if (!isUndefOrEqual(Mask[i], Low))
3284 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3285 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3286 /// the second operand.
3287 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3288 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3289 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3290 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3291 return (Mask[0] < 2 && Mask[1] < 2);
3295 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3296 /// is suitable for input to PSHUFHW.
3297 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3298 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3301 // Lower quadword copied in order or undef.
3302 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3305 // Upper quadword shuffled.
3306 for (unsigned i = 4; i != 8; ++i)
3307 if (!isUndefOrInRange(Mask[i], 4, 8))
3310 if (VT == MVT::v16i16) {
3311 // Lower quadword copied in order or undef.
3312 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3315 // Upper quadword shuffled.
3316 for (unsigned i = 12; i != 16; ++i)
3317 if (!isUndefOrInRange(Mask[i], 12, 16))
3324 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3325 /// is suitable for input to PSHUFLW.
3326 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3327 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3330 // Upper quadword copied in order.
3331 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3334 // Lower quadword shuffled.
3335 for (unsigned i = 0; i != 4; ++i)
3336 if (!isUndefOrInRange(Mask[i], 0, 4))
3339 if (VT == MVT::v16i16) {
3340 // Upper quadword copied in order.
3341 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3344 // Lower quadword shuffled.
3345 for (unsigned i = 8; i != 12; ++i)
3346 if (!isUndefOrInRange(Mask[i], 8, 12))
3353 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3354 /// is suitable for input to PALIGNR.
3355 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3356 const X86Subtarget *Subtarget) {
3357 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3358 (VT.getSizeInBits() == 256 && !Subtarget->hasInt256()))
3361 unsigned NumElts = VT.getVectorNumElements();
3362 unsigned NumLanes = VT.getSizeInBits()/128;
3363 unsigned NumLaneElts = NumElts/NumLanes;
3365 // Do not handle 64-bit element shuffles with palignr.
3366 if (NumLaneElts == 2)
3369 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3371 for (i = 0; i != NumLaneElts; ++i) {
3376 // Lane is all undef, go to next lane
3377 if (i == NumLaneElts)
3380 int Start = Mask[i+l];
3382 // Make sure its in this lane in one of the sources
3383 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3384 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3387 // If not lane 0, then we must match lane 0
3388 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3391 // Correct second source to be contiguous with first source
3392 if (Start >= (int)NumElts)
3393 Start -= NumElts - NumLaneElts;
3395 // Make sure we're shifting in the right direction.
3396 if (Start <= (int)(i+l))
3401 // Check the rest of the elements to see if they are consecutive.
3402 for (++i; i != NumLaneElts; ++i) {
3403 int Idx = Mask[i+l];
3405 // Make sure its in this lane
3406 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3407 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3410 // If not lane 0, then we must match lane 0
3411 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3414 if (Idx >= (int)NumElts)
3415 Idx -= NumElts - NumLaneElts;
3417 if (!isUndefOrEqual(Idx, Start+i))
3426 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3427 /// the two vector operands have swapped position.
3428 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3429 unsigned NumElems) {
3430 for (unsigned i = 0; i != NumElems; ++i) {
3434 else if (idx < (int)NumElems)
3435 Mask[i] = idx + NumElems;
3437 Mask[i] = idx - NumElems;
3441 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3442 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3443 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3444 /// reverse of what x86 shuffles want.
3445 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
3446 bool Commuted = false) {
3447 if (!HasFp256 && VT.getSizeInBits() == 256)
3450 unsigned NumElems = VT.getVectorNumElements();
3451 unsigned NumLanes = VT.getSizeInBits()/128;
3452 unsigned NumLaneElems = NumElems/NumLanes;
3454 if (NumLaneElems != 2 && NumLaneElems != 4)
3457 // VSHUFPSY divides the resulting vector into 4 chunks.
3458 // The sources are also splitted into 4 chunks, and each destination
3459 // chunk must come from a different source chunk.
3461 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3462 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3464 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3465 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3467 // VSHUFPDY divides the resulting vector into 4 chunks.
3468 // The sources are also splitted into 4 chunks, and each destination
3469 // chunk must come from a different source chunk.
3471 // SRC1 => X3 X2 X1 X0
3472 // SRC2 => Y3 Y2 Y1 Y0
3474 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3476 unsigned HalfLaneElems = NumLaneElems/2;
3477 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3478 for (unsigned i = 0; i != NumLaneElems; ++i) {
3479 int Idx = Mask[i+l];
3480 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3481 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3483 // For VSHUFPSY, the mask of the second half must be the same as the
3484 // first but with the appropriate offsets. This works in the same way as
3485 // VPERMILPS works with masks.
3486 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3488 if (!isUndefOrEqual(Idx, Mask[i]+l))
3496 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3497 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3498 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3499 if (!VT.is128BitVector())
3502 unsigned NumElems = VT.getVectorNumElements();
3507 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3508 return isUndefOrEqual(Mask[0], 6) &&
3509 isUndefOrEqual(Mask[1], 7) &&
3510 isUndefOrEqual(Mask[2], 2) &&
3511 isUndefOrEqual(Mask[3], 3);
3514 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3515 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3517 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3518 if (!VT.is128BitVector())
3521 unsigned NumElems = VT.getVectorNumElements();
3526 return isUndefOrEqual(Mask[0], 2) &&
3527 isUndefOrEqual(Mask[1], 3) &&
3528 isUndefOrEqual(Mask[2], 2) &&
3529 isUndefOrEqual(Mask[3], 3);
3532 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3533 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3534 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3535 if (!VT.is128BitVector())
3538 unsigned NumElems = VT.getVectorNumElements();
3540 if (NumElems != 2 && NumElems != 4)
3543 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3544 if (!isUndefOrEqual(Mask[i], i + NumElems))
3547 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3548 if (!isUndefOrEqual(Mask[i], i))
3554 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3555 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3556 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3557 if (!VT.is128BitVector())
3560 unsigned NumElems = VT.getVectorNumElements();
3562 if (NumElems != 2 && NumElems != 4)
3565 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3566 if (!isUndefOrEqual(Mask[i], i))
3569 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3570 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3577 // Some special combinations that can be optimized.
3580 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3581 SelectionDAG &DAG) {
3582 EVT VT = SVOp->getValueType(0);
3583 DebugLoc dl = SVOp->getDebugLoc();
3585 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3588 ArrayRef<int> Mask = SVOp->getMask();
3590 // These are the special masks that may be optimized.
3591 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3592 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3593 bool MatchEvenMask = true;
3594 bool MatchOddMask = true;
3595 for (int i=0; i<8; ++i) {
3596 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3597 MatchEvenMask = false;
3598 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3599 MatchOddMask = false;
3602 if (!MatchEvenMask && !MatchOddMask)
3605 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3607 SDValue Op0 = SVOp->getOperand(0);
3608 SDValue Op1 = SVOp->getOperand(1);
3610 if (MatchEvenMask) {
3611 // Shift the second operand right to 32 bits.
3612 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3613 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3615 // Shift the first operand left to 32 bits.
3616 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3617 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3619 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3620 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3623 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3624 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3625 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3626 bool HasInt256, bool V2IsSplat = false) {
3627 unsigned NumElts = VT.getVectorNumElements();
3629 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3630 "Unsupported vector type for unpckh");
3632 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3633 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3636 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3637 // independently on 128-bit lanes.
3638 unsigned NumLanes = VT.getSizeInBits()/128;
3639 unsigned NumLaneElts = NumElts/NumLanes;
3641 for (unsigned l = 0; l != NumLanes; ++l) {
3642 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3643 i != (l+1)*NumLaneElts;
3646 int BitI1 = Mask[i+1];
3647 if (!isUndefOrEqual(BitI, j))
3650 if (!isUndefOrEqual(BitI1, NumElts))
3653 if (!isUndefOrEqual(BitI1, j + NumElts))
3662 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3663 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3664 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3665 bool HasInt256, bool V2IsSplat = false) {
3666 unsigned NumElts = VT.getVectorNumElements();
3668 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3669 "Unsupported vector type for unpckh");
3671 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3672 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3675 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3676 // independently on 128-bit lanes.
3677 unsigned NumLanes = VT.getSizeInBits()/128;
3678 unsigned NumLaneElts = NumElts/NumLanes;
3680 for (unsigned l = 0; l != NumLanes; ++l) {
3681 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3682 i != (l+1)*NumLaneElts; i += 2, ++j) {
3684 int BitI1 = Mask[i+1];
3685 if (!isUndefOrEqual(BitI, j))
3688 if (isUndefOrEqual(BitI1, NumElts))
3691 if (!isUndefOrEqual(BitI1, j+NumElts))
3699 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3700 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3702 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3704 unsigned NumElts = VT.getVectorNumElements();
3706 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3707 "Unsupported vector type for unpckh");
3709 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3710 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3713 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3714 // FIXME: Need a better way to get rid of this, there's no latency difference
3715 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3716 // the former later. We should also remove the "_undef" special mask.
3717 if (NumElts == 4 && VT.getSizeInBits() == 256)
3720 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3721 // independently on 128-bit lanes.
3722 unsigned NumLanes = VT.getSizeInBits()/128;
3723 unsigned NumLaneElts = NumElts/NumLanes;
3725 for (unsigned l = 0; l != NumLanes; ++l) {
3726 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3727 i != (l+1)*NumLaneElts;
3730 int BitI1 = Mask[i+1];
3732 if (!isUndefOrEqual(BitI, j))
3734 if (!isUndefOrEqual(BitI1, j))
3742 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3743 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3745 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3746 unsigned NumElts = VT.getVectorNumElements();
3748 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3749 "Unsupported vector type for unpckh");
3751 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3752 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3755 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3756 // independently on 128-bit lanes.
3757 unsigned NumLanes = VT.getSizeInBits()/128;
3758 unsigned NumLaneElts = NumElts/NumLanes;
3760 for (unsigned l = 0; l != NumLanes; ++l) {
3761 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3762 i != (l+1)*NumLaneElts; i += 2, ++j) {
3764 int BitI1 = Mask[i+1];
3765 if (!isUndefOrEqual(BitI, j))
3767 if (!isUndefOrEqual(BitI1, j))
3774 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3775 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3776 /// MOVSD, and MOVD, i.e. setting the lowest element.
3777 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3778 if (VT.getVectorElementType().getSizeInBits() < 32)
3780 if (!VT.is128BitVector())
3783 unsigned NumElts = VT.getVectorNumElements();
3785 if (!isUndefOrEqual(Mask[0], NumElts))
3788 for (unsigned i = 1; i != NumElts; ++i)
3789 if (!isUndefOrEqual(Mask[i], i))
3795 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3796 /// as permutations between 128-bit chunks or halves. As an example: this
3798 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3799 /// The first half comes from the second half of V1 and the second half from the
3800 /// the second half of V2.
3801 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3802 if (!HasFp256 || !VT.is256BitVector())
3805 // The shuffle result is divided into half A and half B. In total the two
3806 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3807 // B must come from C, D, E or F.
3808 unsigned HalfSize = VT.getVectorNumElements()/2;
3809 bool MatchA = false, MatchB = false;
3811 // Check if A comes from one of C, D, E, F.
3812 for (unsigned Half = 0; Half != 4; ++Half) {
3813 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3819 // Check if B comes from one of C, D, E, F.
3820 for (unsigned Half = 0; Half != 4; ++Half) {
3821 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3827 return MatchA && MatchB;
3830 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3831 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3832 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3833 EVT VT = SVOp->getValueType(0);
3835 unsigned HalfSize = VT.getVectorNumElements()/2;
3837 unsigned FstHalf = 0, SndHalf = 0;
3838 for (unsigned i = 0; i < HalfSize; ++i) {
3839 if (SVOp->getMaskElt(i) > 0) {
3840 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3844 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3845 if (SVOp->getMaskElt(i) > 0) {
3846 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3851 return (FstHalf | (SndHalf << 4));
3854 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3855 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3856 /// Note that VPERMIL mask matching is different depending whether theunderlying
3857 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3858 /// to the same elements of the low, but to the higher half of the source.
3859 /// In VPERMILPD the two lanes could be shuffled independently of each other
3860 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3861 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3865 unsigned NumElts = VT.getVectorNumElements();
3866 // Only match 256-bit with 32/64-bit types
3867 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3870 unsigned NumLanes = VT.getSizeInBits()/128;
3871 unsigned LaneSize = NumElts/NumLanes;
3872 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3873 for (unsigned i = 0; i != LaneSize; ++i) {
3874 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3876 if (NumElts != 8 || l == 0)
3878 // VPERMILPS handling
3881 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3889 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3890 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3891 /// element of vector 2 and the other elements to come from vector 1 in order.
3892 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3893 bool V2IsSplat = false, bool V2IsUndef = false) {
3894 if (!VT.is128BitVector())
3897 unsigned NumOps = VT.getVectorNumElements();
3898 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3901 if (!isUndefOrEqual(Mask[0], 0))
3904 for (unsigned i = 1; i != NumOps; ++i)
3905 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3906 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3907 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3913 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3914 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3915 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3916 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3917 const X86Subtarget *Subtarget) {
3918 if (!Subtarget->hasSSE3())
3921 unsigned NumElems = VT.getVectorNumElements();
3923 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3924 (VT.getSizeInBits() == 256 && NumElems != 8))
3927 // "i+1" is the value the indexed mask element must have
3928 for (unsigned i = 0; i != NumElems; i += 2)
3929 if (!isUndefOrEqual(Mask[i], i+1) ||
3930 !isUndefOrEqual(Mask[i+1], i+1))
3936 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3937 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3938 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3939 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3940 const X86Subtarget *Subtarget) {
3941 if (!Subtarget->hasSSE3())
3944 unsigned NumElems = VT.getVectorNumElements();
3946 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3947 (VT.getSizeInBits() == 256 && NumElems != 8))
3950 // "i" is the value the indexed mask element must have
3951 for (unsigned i = 0; i != NumElems; i += 2)
3952 if (!isUndefOrEqual(Mask[i], i) ||
3953 !isUndefOrEqual(Mask[i+1], i))
3959 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3960 /// specifies a shuffle of elements that is suitable for input to 256-bit
3961 /// version of MOVDDUP.
3962 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3963 if (!HasFp256 || !VT.is256BitVector())
3966 unsigned NumElts = VT.getVectorNumElements();
3970 for (unsigned i = 0; i != NumElts/2; ++i)
3971 if (!isUndefOrEqual(Mask[i], 0))
3973 for (unsigned i = NumElts/2; i != NumElts; ++i)
3974 if (!isUndefOrEqual(Mask[i], NumElts/2))
3979 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3980 /// specifies a shuffle of elements that is suitable for input to 128-bit
3981 /// version of MOVDDUP.
3982 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3983 if (!VT.is128BitVector())
3986 unsigned e = VT.getVectorNumElements() / 2;
3987 for (unsigned i = 0; i != e; ++i)
3988 if (!isUndefOrEqual(Mask[i], i))
3990 for (unsigned i = 0; i != e; ++i)
3991 if (!isUndefOrEqual(Mask[e+i], i))
3996 /// isVEXTRACTF128Index - Return true if the specified
3997 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3998 /// suitable for input to VEXTRACTF128.
3999 bool X86::isVEXTRACTF128Index(SDNode *N) {
4000 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4003 // The index should be aligned on a 128-bit boundary.
4005 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4007 unsigned VL = N->getValueType(0).getVectorNumElements();
4008 unsigned VBits = N->getValueType(0).getSizeInBits();
4009 unsigned ElSize = VBits / VL;
4010 bool Result = (Index * ElSize) % 128 == 0;
4015 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4016 /// operand specifies a subvector insert that is suitable for input to
4018 bool X86::isVINSERTF128Index(SDNode *N) {
4019 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4022 // The index should be aligned on a 128-bit boundary.
4024 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4026 unsigned VL = N->getValueType(0).getVectorNumElements();
4027 unsigned VBits = N->getValueType(0).getSizeInBits();
4028 unsigned ElSize = VBits / VL;
4029 bool Result = (Index * ElSize) % 128 == 0;
4034 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4035 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4036 /// Handles 128-bit and 256-bit.
4037 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4038 EVT VT = N->getValueType(0);
4040 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4041 "Unsupported vector type for PSHUF/SHUFP");
4043 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4044 // independently on 128-bit lanes.
4045 unsigned NumElts = VT.getVectorNumElements();
4046 unsigned NumLanes = VT.getSizeInBits()/128;
4047 unsigned NumLaneElts = NumElts/NumLanes;
4049 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4050 "Only supports 2 or 4 elements per lane");
4052 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4054 for (unsigned i = 0; i != NumElts; ++i) {
4055 int Elt = N->getMaskElt(i);
4056 if (Elt < 0) continue;
4057 Elt &= NumLaneElts - 1;
4058 unsigned ShAmt = (i << Shift) % 8;
4059 Mask |= Elt << ShAmt;
4065 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4066 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4067 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4068 EVT VT = N->getValueType(0);
4070 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4071 "Unsupported vector type for PSHUFHW");
4073 unsigned NumElts = VT.getVectorNumElements();
4076 for (unsigned l = 0; l != NumElts; l += 8) {
4077 // 8 nodes per lane, but we only care about the last 4.
4078 for (unsigned i = 0; i < 4; ++i) {
4079 int Elt = N->getMaskElt(l+i+4);
4080 if (Elt < 0) continue;
4081 Elt &= 0x3; // only 2-bits.
4082 Mask |= Elt << (i * 2);
4089 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4090 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4091 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4092 EVT VT = N->getValueType(0);
4094 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4095 "Unsupported vector type for PSHUFHW");
4097 unsigned NumElts = VT.getVectorNumElements();
4100 for (unsigned l = 0; l != NumElts; l += 8) {
4101 // 8 nodes per lane, but we only care about the first 4.
4102 for (unsigned i = 0; i < 4; ++i) {
4103 int Elt = N->getMaskElt(l+i);
4104 if (Elt < 0) continue;
4105 Elt &= 0x3; // only 2-bits
4106 Mask |= Elt << (i * 2);
4113 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4114 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4115 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4116 EVT VT = SVOp->getValueType(0);
4117 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4119 unsigned NumElts = VT.getVectorNumElements();
4120 unsigned NumLanes = VT.getSizeInBits()/128;
4121 unsigned NumLaneElts = NumElts/NumLanes;
4125 for (i = 0; i != NumElts; ++i) {
4126 Val = SVOp->getMaskElt(i);
4130 if (Val >= (int)NumElts)
4131 Val -= NumElts - NumLaneElts;
4133 assert(Val - i > 0 && "PALIGNR imm should be positive");
4134 return (Val - i) * EltSize;
4137 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4138 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4140 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4141 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4142 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4145 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4147 EVT VecVT = N->getOperand(0).getValueType();
4148 EVT ElVT = VecVT.getVectorElementType();
4150 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4151 return Index / NumElemsPerChunk;
4154 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4155 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4157 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4158 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4159 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4162 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4164 EVT VecVT = N->getValueType(0);
4165 EVT ElVT = VecVT.getVectorElementType();
4167 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4168 return Index / NumElemsPerChunk;
4171 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4172 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4173 /// Handles 256-bit.
4174 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4175 EVT VT = N->getValueType(0);
4177 unsigned NumElts = VT.getVectorNumElements();
4179 assert((VT.is256BitVector() && NumElts == 4) &&
4180 "Unsupported vector type for VPERMQ/VPERMPD");
4183 for (unsigned i = 0; i != NumElts; ++i) {
4184 int Elt = N->getMaskElt(i);
4187 Mask |= Elt << (i*2);
4192 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4194 bool X86::isZeroNode(SDValue Elt) {
4195 return ((isa<ConstantSDNode>(Elt) &&
4196 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4197 (isa<ConstantFPSDNode>(Elt) &&
4198 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4201 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4202 /// their permute mask.
4203 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4204 SelectionDAG &DAG) {
4205 EVT VT = SVOp->getValueType(0);
4206 unsigned NumElems = VT.getVectorNumElements();
4207 SmallVector<int, 8> MaskVec;
4209 for (unsigned i = 0; i != NumElems; ++i) {
4210 int Idx = SVOp->getMaskElt(i);
4212 if (Idx < (int)NumElems)
4217 MaskVec.push_back(Idx);
4219 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4220 SVOp->getOperand(0), &MaskVec[0]);
4223 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4224 /// match movhlps. The lower half elements should come from upper half of
4225 /// V1 (and in order), and the upper half elements should come from the upper
4226 /// half of V2 (and in order).
4227 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4228 if (!VT.is128BitVector())
4230 if (VT.getVectorNumElements() != 4)
4232 for (unsigned i = 0, e = 2; i != e; ++i)
4233 if (!isUndefOrEqual(Mask[i], i+2))
4235 for (unsigned i = 2; i != 4; ++i)
4236 if (!isUndefOrEqual(Mask[i], i+4))
4241 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4242 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4244 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4245 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4247 N = N->getOperand(0).getNode();
4248 if (!ISD::isNON_EXTLoad(N))
4251 *LD = cast<LoadSDNode>(N);
4255 // Test whether the given value is a vector value which will be legalized
4257 static bool WillBeConstantPoolLoad(SDNode *N) {
4258 if (N->getOpcode() != ISD::BUILD_VECTOR)
4261 // Check for any non-constant elements.
4262 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4263 switch (N->getOperand(i).getNode()->getOpcode()) {
4265 case ISD::ConstantFP:
4272 // Vectors of all-zeros and all-ones are materialized with special
4273 // instructions rather than being loaded.
4274 return !ISD::isBuildVectorAllZeros(N) &&
4275 !ISD::isBuildVectorAllOnes(N);
4278 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4279 /// match movlp{s|d}. The lower half elements should come from lower half of
4280 /// V1 (and in order), and the upper half elements should come from the upper
4281 /// half of V2 (and in order). And since V1 will become the source of the
4282 /// MOVLP, it must be either a vector load or a scalar load to vector.
4283 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4284 ArrayRef<int> Mask, EVT VT) {
4285 if (!VT.is128BitVector())
4288 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4290 // Is V2 is a vector load, don't do this transformation. We will try to use
4291 // load folding shufps op.
4292 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4295 unsigned NumElems = VT.getVectorNumElements();
4297 if (NumElems != 2 && NumElems != 4)
4299 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4300 if (!isUndefOrEqual(Mask[i], i))
4302 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4303 if (!isUndefOrEqual(Mask[i], i+NumElems))
4308 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4310 static bool isSplatVector(SDNode *N) {
4311 if (N->getOpcode() != ISD::BUILD_VECTOR)
4314 SDValue SplatValue = N->getOperand(0);
4315 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4316 if (N->getOperand(i) != SplatValue)
4321 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4322 /// to an zero vector.
4323 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4324 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4325 SDValue V1 = N->getOperand(0);
4326 SDValue V2 = N->getOperand(1);
4327 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4328 for (unsigned i = 0; i != NumElems; ++i) {
4329 int Idx = N->getMaskElt(i);
4330 if (Idx >= (int)NumElems) {
4331 unsigned Opc = V2.getOpcode();
4332 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4334 if (Opc != ISD::BUILD_VECTOR ||
4335 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4337 } else if (Idx >= 0) {
4338 unsigned Opc = V1.getOpcode();
4339 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4341 if (Opc != ISD::BUILD_VECTOR ||
4342 !X86::isZeroNode(V1.getOperand(Idx)))
4349 /// getZeroVector - Returns a vector of specified type with all zero elements.
4351 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4352 SelectionDAG &DAG, DebugLoc dl) {
4353 assert(VT.isVector() && "Expected a vector type");
4354 unsigned Size = VT.getSizeInBits();
4356 // Always build SSE zero vectors as <4 x i32> bitcasted
4357 // to their dest type. This ensures they get CSE'd.
4359 if (Size == 128) { // SSE
4360 if (Subtarget->hasSSE2()) { // SSE2
4361 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4362 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4364 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4365 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4367 } else if (Size == 256) { // AVX
4368 if (Subtarget->hasInt256()) { // AVX2
4369 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4370 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4371 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4373 // 256-bit logic and arithmetic instructions in AVX are all
4374 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4375 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4376 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4377 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4380 llvm_unreachable("Unexpected vector type");
4382 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4385 /// getOnesVector - Returns a vector of specified type with all bits set.
4386 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4387 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4388 /// Then bitcast to their original type, ensuring they get CSE'd.
4389 static SDValue getOnesVector(EVT VT, bool HasInt256, SelectionDAG &DAG,
4391 assert(VT.isVector() && "Expected a vector type");
4392 unsigned Size = VT.getSizeInBits();
4394 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4397 if (HasInt256) { // AVX2
4398 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4399 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4401 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4402 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4404 } else if (Size == 128) {
4405 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4407 llvm_unreachable("Unexpected vector type");
4409 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4412 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4413 /// that point to V2 points to its first element.
4414 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4415 for (unsigned i = 0; i != NumElems; ++i) {
4416 if (Mask[i] > (int)NumElems) {
4422 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4423 /// operation of specified width.
4424 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4426 unsigned NumElems = VT.getVectorNumElements();
4427 SmallVector<int, 8> Mask;
4428 Mask.push_back(NumElems);
4429 for (unsigned i = 1; i != NumElems; ++i)
4431 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4434 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4435 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4437 unsigned NumElems = VT.getVectorNumElements();
4438 SmallVector<int, 8> Mask;
4439 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4441 Mask.push_back(i + NumElems);
4443 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4446 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4447 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4449 unsigned NumElems = VT.getVectorNumElements();
4450 SmallVector<int, 8> Mask;
4451 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4452 Mask.push_back(i + Half);
4453 Mask.push_back(i + NumElems + Half);
4455 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4458 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4459 // a generic shuffle instruction because the target has no such instructions.
4460 // Generate shuffles which repeat i16 and i8 several times until they can be
4461 // represented by v4f32 and then be manipulated by target suported shuffles.
4462 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4463 EVT VT = V.getValueType();
4464 int NumElems = VT.getVectorNumElements();
4465 DebugLoc dl = V.getDebugLoc();
4467 while (NumElems > 4) {
4468 if (EltNo < NumElems/2) {
4469 V = getUnpackl(DAG, dl, VT, V, V);
4471 V = getUnpackh(DAG, dl, VT, V, V);
4472 EltNo -= NumElems/2;
4479 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4480 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4481 EVT VT = V.getValueType();
4482 DebugLoc dl = V.getDebugLoc();
4483 unsigned Size = VT.getSizeInBits();
4486 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4487 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4488 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4490 } else if (Size == 256) {
4491 // To use VPERMILPS to splat scalars, the second half of indicies must
4492 // refer to the higher part, which is a duplication of the lower one,
4493 // because VPERMILPS can only handle in-lane permutations.
4494 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4495 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4497 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4498 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4501 llvm_unreachable("Vector size not supported");
4503 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4506 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4507 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4508 EVT SrcVT = SV->getValueType(0);
4509 SDValue V1 = SV->getOperand(0);
4510 DebugLoc dl = SV->getDebugLoc();
4512 int EltNo = SV->getSplatIndex();
4513 int NumElems = SrcVT.getVectorNumElements();
4514 unsigned Size = SrcVT.getSizeInBits();
4516 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4517 "Unknown how to promote splat for type");
4519 // Extract the 128-bit part containing the splat element and update
4520 // the splat element index when it refers to the higher register.
4522 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4523 if (EltNo >= NumElems/2)
4524 EltNo -= NumElems/2;
4527 // All i16 and i8 vector types can't be used directly by a generic shuffle
4528 // instruction because the target has no such instruction. Generate shuffles
4529 // which repeat i16 and i8 several times until they fit in i32, and then can
4530 // be manipulated by target suported shuffles.
4531 EVT EltVT = SrcVT.getVectorElementType();
4532 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4533 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4535 // Recreate the 256-bit vector and place the same 128-bit vector
4536 // into the low and high part. This is necessary because we want
4537 // to use VPERM* to shuffle the vectors
4539 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4542 return getLegalSplat(DAG, V1, EltNo);
4545 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4546 /// vector of zero or undef vector. This produces a shuffle where the low
4547 /// element of V2 is swizzled into the zero/undef vector, landing at element
4548 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4549 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4551 const X86Subtarget *Subtarget,
4552 SelectionDAG &DAG) {
4553 EVT VT = V2.getValueType();
4555 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4556 unsigned NumElems = VT.getVectorNumElements();
4557 SmallVector<int, 16> MaskVec;
4558 for (unsigned i = 0; i != NumElems; ++i)
4559 // If this is the insertion idx, put the low elt of V2 here.
4560 MaskVec.push_back(i == Idx ? NumElems : i);
4561 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4564 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4565 /// target specific opcode. Returns true if the Mask could be calculated.
4566 /// Sets IsUnary to true if only uses one source.
4567 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4568 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4569 unsigned NumElems = VT.getVectorNumElements();
4573 switch(N->getOpcode()) {
4575 ImmN = N->getOperand(N->getNumOperands()-1);
4576 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4578 case X86ISD::UNPCKH:
4579 DecodeUNPCKHMask(VT, Mask);
4581 case X86ISD::UNPCKL:
4582 DecodeUNPCKLMask(VT, Mask);
4584 case X86ISD::MOVHLPS:
4585 DecodeMOVHLPSMask(NumElems, Mask);
4587 case X86ISD::MOVLHPS:
4588 DecodeMOVLHPSMask(NumElems, Mask);
4590 case X86ISD::PSHUFD:
4591 case X86ISD::VPERMILP:
4592 ImmN = N->getOperand(N->getNumOperands()-1);
4593 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4596 case X86ISD::PSHUFHW:
4597 ImmN = N->getOperand(N->getNumOperands()-1);
4598 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4601 case X86ISD::PSHUFLW:
4602 ImmN = N->getOperand(N->getNumOperands()-1);
4603 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4606 case X86ISD::VPERMI:
4607 ImmN = N->getOperand(N->getNumOperands()-1);
4608 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4612 case X86ISD::MOVSD: {
4613 // The index 0 always comes from the first element of the second source,
4614 // this is why MOVSS and MOVSD are used in the first place. The other
4615 // elements come from the other positions of the first source vector
4616 Mask.push_back(NumElems);
4617 for (unsigned i = 1; i != NumElems; ++i) {
4622 case X86ISD::VPERM2X128:
4623 ImmN = N->getOperand(N->getNumOperands()-1);
4624 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4625 if (Mask.empty()) return false;
4627 case X86ISD::MOVDDUP:
4628 case X86ISD::MOVLHPD:
4629 case X86ISD::MOVLPD:
4630 case X86ISD::MOVLPS:
4631 case X86ISD::MOVSHDUP:
4632 case X86ISD::MOVSLDUP:
4633 case X86ISD::PALIGN:
4634 // Not yet implemented
4636 default: llvm_unreachable("unknown target shuffle node");
4642 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4643 /// element of the result of the vector shuffle.
4644 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4647 return SDValue(); // Limit search depth.
4649 SDValue V = SDValue(N, 0);
4650 EVT VT = V.getValueType();
4651 unsigned Opcode = V.getOpcode();
4653 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4654 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4655 int Elt = SV->getMaskElt(Index);
4658 return DAG.getUNDEF(VT.getVectorElementType());
4660 unsigned NumElems = VT.getVectorNumElements();
4661 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4662 : SV->getOperand(1);
4663 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4666 // Recurse into target specific vector shuffles to find scalars.
4667 if (isTargetShuffle(Opcode)) {
4668 MVT ShufVT = V.getValueType().getSimpleVT();
4669 unsigned NumElems = ShufVT.getVectorNumElements();
4670 SmallVector<int, 16> ShuffleMask;
4673 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4676 int Elt = ShuffleMask[Index];
4678 return DAG.getUNDEF(ShufVT.getVectorElementType());
4680 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4682 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4686 // Actual nodes that may contain scalar elements
4687 if (Opcode == ISD::BITCAST) {
4688 V = V.getOperand(0);
4689 EVT SrcVT = V.getValueType();
4690 unsigned NumElems = VT.getVectorNumElements();
4692 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4696 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4697 return (Index == 0) ? V.getOperand(0)
4698 : DAG.getUNDEF(VT.getVectorElementType());
4700 if (V.getOpcode() == ISD::BUILD_VECTOR)
4701 return V.getOperand(Index);
4706 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4707 /// shuffle operation which come from a consecutively from a zero. The
4708 /// search can start in two different directions, from left or right.
4710 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4711 bool ZerosFromLeft, SelectionDAG &DAG) {
4713 for (i = 0; i != NumElems; ++i) {
4714 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4715 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4716 if (!(Elt.getNode() &&
4717 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4724 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4725 /// correspond consecutively to elements from one of the vector operands,
4726 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4728 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4729 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4730 unsigned NumElems, unsigned &OpNum) {
4731 bool SeenV1 = false;
4732 bool SeenV2 = false;
4734 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4735 int Idx = SVOp->getMaskElt(i);
4736 // Ignore undef indicies
4740 if (Idx < (int)NumElems)
4745 // Only accept consecutive elements from the same vector
4746 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4750 OpNum = SeenV1 ? 0 : 1;
4754 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4755 /// logical left shift of a vector.
4756 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4757 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4758 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4759 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4760 false /* check zeros from right */, DAG);
4766 // Considering the elements in the mask that are not consecutive zeros,
4767 // check if they consecutively come from only one of the source vectors.
4769 // V1 = {X, A, B, C} 0
4771 // vector_shuffle V1, V2 <1, 2, 3, X>
4773 if (!isShuffleMaskConsecutive(SVOp,
4774 0, // Mask Start Index
4775 NumElems-NumZeros, // Mask End Index(exclusive)
4776 NumZeros, // Where to start looking in the src vector
4777 NumElems, // Number of elements in vector
4778 OpSrc)) // Which source operand ?
4783 ShVal = SVOp->getOperand(OpSrc);
4787 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4788 /// logical left shift of a vector.
4789 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4790 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4791 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4792 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4793 true /* check zeros from left */, DAG);
4799 // Considering the elements in the mask that are not consecutive zeros,
4800 // check if they consecutively come from only one of the source vectors.
4802 // 0 { A, B, X, X } = V2
4804 // vector_shuffle V1, V2 <X, X, 4, 5>
4806 if (!isShuffleMaskConsecutive(SVOp,
4807 NumZeros, // Mask Start Index
4808 NumElems, // Mask End Index(exclusive)
4809 0, // Where to start looking in the src vector
4810 NumElems, // Number of elements in vector
4811 OpSrc)) // Which source operand ?
4816 ShVal = SVOp->getOperand(OpSrc);
4820 /// isVectorShift - Returns true if the shuffle can be implemented as a
4821 /// logical left or right shift of a vector.
4822 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4823 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4824 // Although the logic below support any bitwidth size, there are no
4825 // shift instructions which handle more than 128-bit vectors.
4826 if (!SVOp->getValueType(0).is128BitVector())
4829 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4830 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4836 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4838 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4839 unsigned NumNonZero, unsigned NumZero,
4841 const X86Subtarget* Subtarget,
4842 const TargetLowering &TLI) {
4846 DebugLoc dl = Op.getDebugLoc();
4849 for (unsigned i = 0; i < 16; ++i) {
4850 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4851 if (ThisIsNonZero && First) {
4853 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4855 V = DAG.getUNDEF(MVT::v8i16);
4860 SDValue ThisElt(0, 0), LastElt(0, 0);
4861 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4862 if (LastIsNonZero) {
4863 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4864 MVT::i16, Op.getOperand(i-1));
4866 if (ThisIsNonZero) {
4867 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4868 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4869 ThisElt, DAG.getConstant(8, MVT::i8));
4871 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4875 if (ThisElt.getNode())
4876 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4877 DAG.getIntPtrConstant(i/2));
4881 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4884 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4886 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4887 unsigned NumNonZero, unsigned NumZero,
4889 const X86Subtarget* Subtarget,
4890 const TargetLowering &TLI) {
4894 DebugLoc dl = Op.getDebugLoc();
4897 for (unsigned i = 0; i < 8; ++i) {
4898 bool isNonZero = (NonZeros & (1 << i)) != 0;
4902 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4904 V = DAG.getUNDEF(MVT::v8i16);
4907 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4908 MVT::v8i16, V, Op.getOperand(i),
4909 DAG.getIntPtrConstant(i));
4916 /// getVShift - Return a vector logical shift node.
4918 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4919 unsigned NumBits, SelectionDAG &DAG,
4920 const TargetLowering &TLI, DebugLoc dl) {
4921 assert(VT.is128BitVector() && "Unknown type for VShift");
4922 EVT ShVT = MVT::v2i64;
4923 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4924 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4925 return DAG.getNode(ISD::BITCAST, dl, VT,
4926 DAG.getNode(Opc, dl, ShVT, SrcOp,
4927 DAG.getConstant(NumBits,
4928 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4932 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4933 SelectionDAG &DAG) const {
4935 // Check if the scalar load can be widened into a vector load. And if
4936 // the address is "base + cst" see if the cst can be "absorbed" into
4937 // the shuffle mask.
4938 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4939 SDValue Ptr = LD->getBasePtr();
4940 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4942 EVT PVT = LD->getValueType(0);
4943 if (PVT != MVT::i32 && PVT != MVT::f32)
4948 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4949 FI = FINode->getIndex();
4951 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4952 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4953 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4954 Offset = Ptr.getConstantOperandVal(1);
4955 Ptr = Ptr.getOperand(0);
4960 // FIXME: 256-bit vector instructions don't require a strict alignment,
4961 // improve this code to support it better.
4962 unsigned RequiredAlign = VT.getSizeInBits()/8;
4963 SDValue Chain = LD->getChain();
4964 // Make sure the stack object alignment is at least 16 or 32.
4965 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4966 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4967 if (MFI->isFixedObjectIndex(FI)) {
4968 // Can't change the alignment. FIXME: It's possible to compute
4969 // the exact stack offset and reference FI + adjust offset instead.
4970 // If someone *really* cares about this. That's the way to implement it.
4973 MFI->setObjectAlignment(FI, RequiredAlign);
4977 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4978 // Ptr + (Offset & ~15).
4981 if ((Offset % RequiredAlign) & 3)
4983 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4985 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4986 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4988 int EltNo = (Offset - StartOffset) >> 2;
4989 unsigned NumElems = VT.getVectorNumElements();
4991 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4992 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4993 LD->getPointerInfo().getWithOffset(StartOffset),
4994 false, false, false, 0);
4996 SmallVector<int, 8> Mask;
4997 for (unsigned i = 0; i != NumElems; ++i)
4998 Mask.push_back(EltNo);
5000 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5006 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5007 /// vector of type 'VT', see if the elements can be replaced by a single large
5008 /// load which has the same value as a build_vector whose operands are 'elts'.
5010 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5012 /// FIXME: we'd also like to handle the case where the last elements are zero
5013 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5014 /// There's even a handy isZeroNode for that purpose.
5015 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5016 DebugLoc &DL, SelectionDAG &DAG) {
5017 EVT EltVT = VT.getVectorElementType();
5018 unsigned NumElems = Elts.size();
5020 LoadSDNode *LDBase = NULL;
5021 unsigned LastLoadedElt = -1U;
5023 // For each element in the initializer, see if we've found a load or an undef.
5024 // If we don't find an initial load element, or later load elements are
5025 // non-consecutive, bail out.
5026 for (unsigned i = 0; i < NumElems; ++i) {
5027 SDValue Elt = Elts[i];
5029 if (!Elt.getNode() ||
5030 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5033 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5035 LDBase = cast<LoadSDNode>(Elt.getNode());
5039 if (Elt.getOpcode() == ISD::UNDEF)
5042 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5043 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5048 // If we have found an entire vector of loads and undefs, then return a large
5049 // load of the entire vector width starting at the base pointer. If we found
5050 // consecutive loads for the low half, generate a vzext_load node.
5051 if (LastLoadedElt == NumElems - 1) {
5052 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5053 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5054 LDBase->getPointerInfo(),
5055 LDBase->isVolatile(), LDBase->isNonTemporal(),
5056 LDBase->isInvariant(), 0);
5057 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5058 LDBase->getPointerInfo(),
5059 LDBase->isVolatile(), LDBase->isNonTemporal(),
5060 LDBase->isInvariant(), LDBase->getAlignment());
5062 if (NumElems == 4 && LastLoadedElt == 1 &&
5063 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5064 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5065 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5067 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5068 LDBase->getPointerInfo(),
5069 LDBase->getAlignment(),
5070 false/*isVolatile*/, true/*ReadMem*/,
5073 // Make sure the newly-created LOAD is in the same position as LDBase in
5074 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5075 // update uses of LDBase's output chain to use the TokenFactor.
5076 if (LDBase->hasAnyUseOfValue(1)) {
5077 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5078 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5079 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5080 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5081 SDValue(ResNode.getNode(), 1));
5084 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5089 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5090 /// to generate a splat value for the following cases:
5091 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5092 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5093 /// a scalar load, or a constant.
5094 /// The VBROADCAST node is returned when a pattern is found,
5095 /// or SDValue() otherwise.
5097 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5098 if (!Subtarget->hasFp256())
5101 EVT VT = Op.getValueType();
5102 DebugLoc dl = Op.getDebugLoc();
5104 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5105 "Unsupported vector type for broadcast.");
5110 switch (Op.getOpcode()) {
5112 // Unknown pattern found.
5115 case ISD::BUILD_VECTOR: {
5116 // The BUILD_VECTOR node must be a splat.
5117 if (!isSplatVector(Op.getNode()))
5120 Ld = Op.getOperand(0);
5121 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5122 Ld.getOpcode() == ISD::ConstantFP);
5124 // The suspected load node has several users. Make sure that all
5125 // of its users are from the BUILD_VECTOR node.
5126 // Constants may have multiple users.
5127 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5132 case ISD::VECTOR_SHUFFLE: {
5133 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5135 // Shuffles must have a splat mask where the first element is
5137 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5140 SDValue Sc = Op.getOperand(0);
5141 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5142 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5144 if (!Subtarget->hasInt256())
5147 // Use the register form of the broadcast instruction available on AVX2.
5148 if (VT.is256BitVector())
5149 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5150 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5153 Ld = Sc.getOperand(0);
5154 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5155 Ld.getOpcode() == ISD::ConstantFP);
5157 // The scalar_to_vector node and the suspected
5158 // load node must have exactly one user.
5159 // Constants may have multiple users.
5160 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5166 bool Is256 = VT.is256BitVector();
5168 // Handle the broadcasting a single constant scalar from the constant pool
5169 // into a vector. On Sandybridge it is still better to load a constant vector
5170 // from the constant pool and not to broadcast it from a scalar.
5171 if (ConstSplatVal && Subtarget->hasInt256()) {
5172 EVT CVT = Ld.getValueType();
5173 assert(!CVT.isVector() && "Must not broadcast a vector type");
5174 unsigned ScalarSize = CVT.getSizeInBits();
5176 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5177 const Constant *C = 0;
5178 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5179 C = CI->getConstantIntValue();
5180 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5181 C = CF->getConstantFPValue();
5183 assert(C && "Invalid constant type");
5185 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5186 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5187 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5188 MachinePointerInfo::getConstantPool(),
5189 false, false, false, Alignment);
5191 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5195 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5196 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5198 // Handle AVX2 in-register broadcasts.
5199 if (!IsLoad && Subtarget->hasInt256() &&
5200 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5201 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5203 // The scalar source must be a normal load.
5207 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5208 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5210 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5211 // double since there is no vbroadcastsd xmm
5212 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5213 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5214 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5217 // Unsupported broadcast.
5222 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5223 EVT VT = Op.getValueType();
5225 // Skip if insert_vec_elt is not supported.
5226 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5229 DebugLoc DL = Op.getDebugLoc();
5230 unsigned NumElems = Op.getNumOperands();
5234 SmallVector<unsigned, 4> InsertIndices;
5235 SmallVector<int, 8> Mask(NumElems, -1);
5237 for (unsigned i = 0; i != NumElems; ++i) {
5238 unsigned Opc = Op.getOperand(i).getOpcode();
5240 if (Opc == ISD::UNDEF)
5243 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5244 // Quit if more than 1 elements need inserting.
5245 if (InsertIndices.size() > 1)
5248 InsertIndices.push_back(i);
5252 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5253 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5255 // Quit if extracted from vector of different type.
5256 if (ExtractedFromVec.getValueType() != VT)
5259 // Quit if non-constant index.
5260 if (!isa<ConstantSDNode>(ExtIdx))
5263 if (VecIn1.getNode() == 0)
5264 VecIn1 = ExtractedFromVec;
5265 else if (VecIn1 != ExtractedFromVec) {
5266 if (VecIn2.getNode() == 0)
5267 VecIn2 = ExtractedFromVec;
5268 else if (VecIn2 != ExtractedFromVec)
5269 // Quit if more than 2 vectors to shuffle
5273 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5275 if (ExtractedFromVec == VecIn1)
5277 else if (ExtractedFromVec == VecIn2)
5278 Mask[i] = Idx + NumElems;
5281 if (VecIn1.getNode() == 0)
5284 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5285 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5286 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5287 unsigned Idx = InsertIndices[i];
5288 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5289 DAG.getIntPtrConstant(Idx));
5296 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5297 DebugLoc dl = Op.getDebugLoc();
5299 EVT VT = Op.getValueType();
5300 EVT ExtVT = VT.getVectorElementType();
5301 unsigned NumElems = Op.getNumOperands();
5303 // Vectors containing all zeros can be matched by pxor and xorps later
5304 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5305 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5306 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5307 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5310 return getZeroVector(VT, Subtarget, DAG, dl);
5313 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5314 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5315 // vpcmpeqd on 256-bit vectors.
5316 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5317 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5320 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5323 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5324 if (Broadcast.getNode())
5327 unsigned EVTBits = ExtVT.getSizeInBits();
5329 unsigned NumZero = 0;
5330 unsigned NumNonZero = 0;
5331 unsigned NonZeros = 0;
5332 bool IsAllConstants = true;
5333 SmallSet<SDValue, 8> Values;
5334 for (unsigned i = 0; i < NumElems; ++i) {
5335 SDValue Elt = Op.getOperand(i);
5336 if (Elt.getOpcode() == ISD::UNDEF)
5339 if (Elt.getOpcode() != ISD::Constant &&
5340 Elt.getOpcode() != ISD::ConstantFP)
5341 IsAllConstants = false;
5342 if (X86::isZeroNode(Elt))
5345 NonZeros |= (1 << i);
5350 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5351 if (NumNonZero == 0)
5352 return DAG.getUNDEF(VT);
5354 // Special case for single non-zero, non-undef, element.
5355 if (NumNonZero == 1) {
5356 unsigned Idx = CountTrailingZeros_32(NonZeros);
5357 SDValue Item = Op.getOperand(Idx);
5359 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5360 // the value are obviously zero, truncate the value to i32 and do the
5361 // insertion that way. Only do this if the value is non-constant or if the
5362 // value is a constant being inserted into element 0. It is cheaper to do
5363 // a constant pool load than it is to do a movd + shuffle.
5364 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5365 (!IsAllConstants || Idx == 0)) {
5366 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5368 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5369 EVT VecVT = MVT::v4i32;
5370 unsigned VecElts = 4;
5372 // Truncate the value (which may itself be a constant) to i32, and
5373 // convert it to a vector with movd (S2V+shuffle to zero extend).
5374 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5375 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5376 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5378 // Now we have our 32-bit value zero extended in the low element of
5379 // a vector. If Idx != 0, swizzle it into place.
5381 SmallVector<int, 4> Mask;
5382 Mask.push_back(Idx);
5383 for (unsigned i = 1; i != VecElts; ++i)
5385 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5388 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5392 // If we have a constant or non-constant insertion into the low element of
5393 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5394 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5395 // depending on what the source datatype is.
5398 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5400 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5401 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5402 if (VT.is256BitVector()) {
5403 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5404 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5405 Item, DAG.getIntPtrConstant(0));
5407 assert(VT.is128BitVector() && "Expected an SSE value type!");
5408 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5409 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5410 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5413 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5414 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5415 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5416 if (VT.is256BitVector()) {
5417 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5418 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5420 assert(VT.is128BitVector() && "Expected an SSE value type!");
5421 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5423 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5427 // Is it a vector logical left shift?
5428 if (NumElems == 2 && Idx == 1 &&
5429 X86::isZeroNode(Op.getOperand(0)) &&
5430 !X86::isZeroNode(Op.getOperand(1))) {
5431 unsigned NumBits = VT.getSizeInBits();
5432 return getVShift(true, VT,
5433 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5434 VT, Op.getOperand(1)),
5435 NumBits/2, DAG, *this, dl);
5438 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5441 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5442 // is a non-constant being inserted into an element other than the low one,
5443 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5444 // movd/movss) to move this into the low element, then shuffle it into
5446 if (EVTBits == 32) {
5447 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5449 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5450 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5451 SmallVector<int, 8> MaskVec;
5452 for (unsigned i = 0; i != NumElems; ++i)
5453 MaskVec.push_back(i == Idx ? 0 : 1);
5454 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5458 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5459 if (Values.size() == 1) {
5460 if (EVTBits == 32) {
5461 // Instead of a shuffle like this:
5462 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5463 // Check if it's possible to issue this instead.
5464 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5465 unsigned Idx = CountTrailingZeros_32(NonZeros);
5466 SDValue Item = Op.getOperand(Idx);
5467 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5468 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5473 // A vector full of immediates; various special cases are already
5474 // handled, so this is best done with a single constant-pool load.
5478 // For AVX-length vectors, build the individual 128-bit pieces and use
5479 // shuffles to put them in place.
5480 if (VT.is256BitVector()) {
5481 SmallVector<SDValue, 32> V;
5482 for (unsigned i = 0; i != NumElems; ++i)
5483 V.push_back(Op.getOperand(i));
5485 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5487 // Build both the lower and upper subvector.
5488 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5489 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5492 // Recreate the wider vector with the lower and upper part.
5493 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5496 // Let legalizer expand 2-wide build_vectors.
5497 if (EVTBits == 64) {
5498 if (NumNonZero == 1) {
5499 // One half is zero or undef.
5500 unsigned Idx = CountTrailingZeros_32(NonZeros);
5501 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5502 Op.getOperand(Idx));
5503 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5508 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5509 if (EVTBits == 8 && NumElems == 16) {
5510 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5512 if (V.getNode()) return V;
5515 if (EVTBits == 16 && NumElems == 8) {
5516 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5518 if (V.getNode()) return V;
5521 // If element VT is == 32 bits, turn it into a number of shuffles.
5522 SmallVector<SDValue, 8> V(NumElems);
5523 if (NumElems == 4 && NumZero > 0) {
5524 for (unsigned i = 0; i < 4; ++i) {
5525 bool isZero = !(NonZeros & (1 << i));
5527 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5529 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5532 for (unsigned i = 0; i < 2; ++i) {
5533 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5536 V[i] = V[i*2]; // Must be a zero vector.
5539 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5542 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5545 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5550 bool Reverse1 = (NonZeros & 0x3) == 2;
5551 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5555 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5556 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5558 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5561 if (Values.size() > 1 && VT.is128BitVector()) {
5562 // Check for a build vector of consecutive loads.
5563 for (unsigned i = 0; i < NumElems; ++i)
5564 V[i] = Op.getOperand(i);
5566 // Check for elements which are consecutive loads.
5567 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5571 // Check for a build vector from mostly shuffle plus few inserting.
5572 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5576 // For SSE 4.1, use insertps to put the high elements into the low element.
5577 if (getSubtarget()->hasSSE41()) {
5579 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5580 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5582 Result = DAG.getUNDEF(VT);
5584 for (unsigned i = 1; i < NumElems; ++i) {
5585 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5586 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5587 Op.getOperand(i), DAG.getIntPtrConstant(i));
5592 // Otherwise, expand into a number of unpckl*, start by extending each of
5593 // our (non-undef) elements to the full vector width with the element in the
5594 // bottom slot of the vector (which generates no code for SSE).
5595 for (unsigned i = 0; i < NumElems; ++i) {
5596 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5597 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5599 V[i] = DAG.getUNDEF(VT);
5602 // Next, we iteratively mix elements, e.g. for v4f32:
5603 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5604 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5605 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5606 unsigned EltStride = NumElems >> 1;
5607 while (EltStride != 0) {
5608 for (unsigned i = 0; i < EltStride; ++i) {
5609 // If V[i+EltStride] is undef and this is the first round of mixing,
5610 // then it is safe to just drop this shuffle: V[i] is already in the
5611 // right place, the one element (since it's the first round) being
5612 // inserted as undef can be dropped. This isn't safe for successive
5613 // rounds because they will permute elements within both vectors.
5614 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5615 EltStride == NumElems/2)
5618 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5627 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5628 // to create 256-bit vectors from two other 128-bit ones.
5629 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5630 DebugLoc dl = Op.getDebugLoc();
5631 EVT ResVT = Op.getValueType();
5633 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5635 SDValue V1 = Op.getOperand(0);
5636 SDValue V2 = Op.getOperand(1);
5637 unsigned NumElems = ResVT.getVectorNumElements();
5639 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5642 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5643 assert(Op.getNumOperands() == 2);
5645 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5646 // from two other 128-bit ones.
5647 return LowerAVXCONCAT_VECTORS(Op, DAG);
5650 // Try to lower a shuffle node into a simple blend instruction.
5652 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5653 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5654 SDValue V1 = SVOp->getOperand(0);
5655 SDValue V2 = SVOp->getOperand(1);
5656 DebugLoc dl = SVOp->getDebugLoc();
5657 EVT VT = SVOp->getValueType(0);
5658 EVT EltVT = VT.getVectorElementType();
5659 unsigned NumElems = VT.getVectorNumElements();
5661 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
5663 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
5666 // Check the mask for BLEND and build the value.
5667 unsigned MaskValue = 0;
5668 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
5669 unsigned NumLanes = (NumElems-1)/8 + 1;
5670 unsigned NumElemsInLane = NumElems / NumLanes;
5672 // Blend for v16i16 should be symetric for the both lanes.
5673 for (unsigned i = 0; i < NumElemsInLane; ++i) {
5675 int SndLaneEltIdx = (NumLanes == 2) ?
5676 SVOp->getMaskElt(i + NumElemsInLane) : -1;
5677 int EltIdx = SVOp->getMaskElt(i);
5679 if ((EltIdx == -1 || EltIdx == (int)i) &&
5680 (SndLaneEltIdx == -1 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
5683 if (((unsigned)EltIdx == (i + NumElems)) &&
5684 (SndLaneEltIdx == -1 ||
5685 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
5686 MaskValue |= (1<<i);
5691 // Convert i32 vectors to floating point if it is not AVX2.
5692 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
5694 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
5695 BlendVT = EVT::getVectorVT(*DAG.getContext(),
5696 EVT::getFloatingPointVT(EltVT.getSizeInBits()),
5698 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
5699 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
5702 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
5703 DAG.getConstant(MaskValue, MVT::i32));
5704 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5707 // v8i16 shuffles - Prefer shuffles in the following order:
5708 // 1. [all] pshuflw, pshufhw, optional move
5709 // 2. [ssse3] 1 x pshufb
5710 // 3. [ssse3] 2 x pshufb + 1 x por
5711 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5713 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
5714 SelectionDAG &DAG) {
5715 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5716 SDValue V1 = SVOp->getOperand(0);
5717 SDValue V2 = SVOp->getOperand(1);
5718 DebugLoc dl = SVOp->getDebugLoc();
5719 SmallVector<int, 8> MaskVals;
5721 // Determine if more than 1 of the words in each of the low and high quadwords
5722 // of the result come from the same quadword of one of the two inputs. Undef
5723 // mask values count as coming from any quadword, for better codegen.
5724 unsigned LoQuad[] = { 0, 0, 0, 0 };
5725 unsigned HiQuad[] = { 0, 0, 0, 0 };
5726 std::bitset<4> InputQuads;
5727 for (unsigned i = 0; i < 8; ++i) {
5728 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5729 int EltIdx = SVOp->getMaskElt(i);
5730 MaskVals.push_back(EltIdx);
5739 InputQuads.set(EltIdx / 4);
5742 int BestLoQuad = -1;
5743 unsigned MaxQuad = 1;
5744 for (unsigned i = 0; i < 4; ++i) {
5745 if (LoQuad[i] > MaxQuad) {
5747 MaxQuad = LoQuad[i];
5751 int BestHiQuad = -1;
5753 for (unsigned i = 0; i < 4; ++i) {
5754 if (HiQuad[i] > MaxQuad) {
5756 MaxQuad = HiQuad[i];
5760 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5761 // of the two input vectors, shuffle them into one input vector so only a
5762 // single pshufb instruction is necessary. If There are more than 2 input
5763 // quads, disable the next transformation since it does not help SSSE3.
5764 bool V1Used = InputQuads[0] || InputQuads[1];
5765 bool V2Used = InputQuads[2] || InputQuads[3];
5766 if (Subtarget->hasSSSE3()) {
5767 if (InputQuads.count() == 2 && V1Used && V2Used) {
5768 BestLoQuad = InputQuads[0] ? 0 : 1;
5769 BestHiQuad = InputQuads[2] ? 2 : 3;
5771 if (InputQuads.count() > 2) {
5777 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5778 // the shuffle mask. If a quad is scored as -1, that means that it contains
5779 // words from all 4 input quadwords.
5781 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5783 BestLoQuad < 0 ? 0 : BestLoQuad,
5784 BestHiQuad < 0 ? 1 : BestHiQuad
5786 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5787 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5788 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5789 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5791 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5792 // source words for the shuffle, to aid later transformations.
5793 bool AllWordsInNewV = true;
5794 bool InOrder[2] = { true, true };
5795 for (unsigned i = 0; i != 8; ++i) {
5796 int idx = MaskVals[i];
5798 InOrder[i/4] = false;
5799 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5801 AllWordsInNewV = false;
5805 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5806 if (AllWordsInNewV) {
5807 for (int i = 0; i != 8; ++i) {
5808 int idx = MaskVals[i];
5811 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5812 if ((idx != i) && idx < 4)
5814 if ((idx != i) && idx > 3)
5823 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5824 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5825 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5826 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5827 unsigned TargetMask = 0;
5828 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5829 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5830 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5831 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5832 getShufflePSHUFLWImmediate(SVOp);
5833 V1 = NewV.getOperand(0);
5834 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5838 // If we have SSSE3, and all words of the result are from 1 input vector,
5839 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5840 // is present, fall back to case 4.
5841 if (Subtarget->hasSSSE3()) {
5842 SmallVector<SDValue,16> pshufbMask;
5844 // If we have elements from both input vectors, set the high bit of the
5845 // shuffle mask element to zero out elements that come from V2 in the V1
5846 // mask, and elements that come from V1 in the V2 mask, so that the two
5847 // results can be OR'd together.
5848 bool TwoInputs = V1Used && V2Used;
5849 for (unsigned i = 0; i != 8; ++i) {
5850 int EltIdx = MaskVals[i] * 2;
5851 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5852 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5853 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5854 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5856 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5857 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5858 DAG.getNode(ISD::BUILD_VECTOR, dl,
5859 MVT::v16i8, &pshufbMask[0], 16));
5861 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5863 // Calculate the shuffle mask for the second input, shuffle it, and
5864 // OR it with the first shuffled input.
5866 for (unsigned i = 0; i != 8; ++i) {
5867 int EltIdx = MaskVals[i] * 2;
5868 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5869 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5870 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5871 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5873 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5874 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5875 DAG.getNode(ISD::BUILD_VECTOR, dl,
5876 MVT::v16i8, &pshufbMask[0], 16));
5877 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5878 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5881 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5882 // and update MaskVals with new element order.
5883 std::bitset<8> InOrder;
5884 if (BestLoQuad >= 0) {
5885 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5886 for (int i = 0; i != 4; ++i) {
5887 int idx = MaskVals[i];
5890 } else if ((idx / 4) == BestLoQuad) {
5895 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5898 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5899 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5900 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5902 getShufflePSHUFLWImmediate(SVOp), DAG);
5906 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5907 // and update MaskVals with the new element order.
5908 if (BestHiQuad >= 0) {
5909 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5910 for (unsigned i = 4; i != 8; ++i) {
5911 int idx = MaskVals[i];
5914 } else if ((idx / 4) == BestHiQuad) {
5915 MaskV[i] = (idx & 3) + 4;
5919 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5922 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5923 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5924 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5926 getShufflePSHUFHWImmediate(SVOp), DAG);
5930 // In case BestHi & BestLo were both -1, which means each quadword has a word
5931 // from each of the four input quadwords, calculate the InOrder bitvector now
5932 // before falling through to the insert/extract cleanup.
5933 if (BestLoQuad == -1 && BestHiQuad == -1) {
5935 for (int i = 0; i != 8; ++i)
5936 if (MaskVals[i] < 0 || MaskVals[i] == i)
5940 // The other elements are put in the right place using pextrw and pinsrw.
5941 for (unsigned i = 0; i != 8; ++i) {
5944 int EltIdx = MaskVals[i];
5947 SDValue ExtOp = (EltIdx < 8) ?
5948 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5949 DAG.getIntPtrConstant(EltIdx)) :
5950 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5951 DAG.getIntPtrConstant(EltIdx - 8));
5952 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5953 DAG.getIntPtrConstant(i));
5958 // v16i8 shuffles - Prefer shuffles in the following order:
5959 // 1. [ssse3] 1 x pshufb
5960 // 2. [ssse3] 2 x pshufb + 1 x por
5961 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5963 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5965 const X86TargetLowering &TLI) {
5966 SDValue V1 = SVOp->getOperand(0);
5967 SDValue V2 = SVOp->getOperand(1);
5968 DebugLoc dl = SVOp->getDebugLoc();
5969 ArrayRef<int> MaskVals = SVOp->getMask();
5971 // If we have SSSE3, case 1 is generated when all result bytes come from
5972 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5973 // present, fall back to case 3.
5975 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5976 if (TLI.getSubtarget()->hasSSSE3()) {
5977 SmallVector<SDValue,16> pshufbMask;
5979 // If all result elements are from one input vector, then only translate
5980 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5982 // Otherwise, we have elements from both input vectors, and must zero out
5983 // elements that come from V2 in the first mask, and V1 in the second mask
5984 // so that we can OR them together.
5985 for (unsigned i = 0; i != 16; ++i) {
5986 int EltIdx = MaskVals[i];
5987 if (EltIdx < 0 || EltIdx >= 16)
5989 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5991 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5992 DAG.getNode(ISD::BUILD_VECTOR, dl,
5993 MVT::v16i8, &pshufbMask[0], 16));
5995 // As PSHUFB will zero elements with negative indices, it's safe to ignore
5996 // the 2nd operand if it's undefined or zero.
5997 if (V2.getOpcode() == ISD::UNDEF ||
5998 ISD::isBuildVectorAllZeros(V2.getNode()))
6001 // Calculate the shuffle mask for the second input, shuffle it, and
6002 // OR it with the first shuffled input.
6004 for (unsigned i = 0; i != 16; ++i) {
6005 int EltIdx = MaskVals[i];
6006 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6007 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6009 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6010 DAG.getNode(ISD::BUILD_VECTOR, dl,
6011 MVT::v16i8, &pshufbMask[0], 16));
6012 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6015 // No SSSE3 - Calculate in place words and then fix all out of place words
6016 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6017 // the 16 different words that comprise the two doublequadword input vectors.
6018 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6019 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6021 for (int i = 0; i != 8; ++i) {
6022 int Elt0 = MaskVals[i*2];
6023 int Elt1 = MaskVals[i*2+1];
6025 // This word of the result is all undef, skip it.
6026 if (Elt0 < 0 && Elt1 < 0)
6029 // This word of the result is already in the correct place, skip it.
6030 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6033 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6034 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6037 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6038 // using a single extract together, load it and store it.
6039 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6040 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6041 DAG.getIntPtrConstant(Elt1 / 2));
6042 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6043 DAG.getIntPtrConstant(i));
6047 // If Elt1 is defined, extract it from the appropriate source. If the
6048 // source byte is not also odd, shift the extracted word left 8 bits
6049 // otherwise clear the bottom 8 bits if we need to do an or.
6051 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6052 DAG.getIntPtrConstant(Elt1 / 2));
6053 if ((Elt1 & 1) == 0)
6054 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6056 TLI.getShiftAmountTy(InsElt.getValueType())));
6058 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6059 DAG.getConstant(0xFF00, MVT::i16));
6061 // If Elt0 is defined, extract it from the appropriate source. If the
6062 // source byte is not also even, shift the extracted word right 8 bits. If
6063 // Elt1 was also defined, OR the extracted values together before
6064 // inserting them in the result.
6066 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6067 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6068 if ((Elt0 & 1) != 0)
6069 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6071 TLI.getShiftAmountTy(InsElt0.getValueType())));
6073 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6074 DAG.getConstant(0x00FF, MVT::i16));
6075 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6078 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6079 DAG.getIntPtrConstant(i));
6081 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6084 // v32i8 shuffles - Translate to VPSHUFB if possible.
6086 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6087 const X86Subtarget *Subtarget,
6088 SelectionDAG &DAG) {
6089 EVT VT = SVOp->getValueType(0);
6090 SDValue V1 = SVOp->getOperand(0);
6091 SDValue V2 = SVOp->getOperand(1);
6092 DebugLoc dl = SVOp->getDebugLoc();
6093 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6095 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6096 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6097 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6099 // VPSHUFB may be generated if
6100 // (1) one of input vector is undefined or zeroinitializer.
6101 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6102 // And (2) the mask indexes don't cross the 128-bit lane.
6103 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6104 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6107 if (V1IsAllZero && !V2IsAllZero) {
6108 CommuteVectorShuffleMask(MaskVals, 32);
6111 SmallVector<SDValue, 32> pshufbMask;
6112 for (unsigned i = 0; i != 32; i++) {
6113 int EltIdx = MaskVals[i];
6114 if (EltIdx < 0 || EltIdx >= 32)
6117 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6118 // Cross lane is not allowed.
6122 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6124 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6125 DAG.getNode(ISD::BUILD_VECTOR, dl,
6126 MVT::v32i8, &pshufbMask[0], 32));
6129 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6130 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6131 /// done when every pair / quad of shuffle mask elements point to elements in
6132 /// the right sequence. e.g.
6133 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6135 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6136 SelectionDAG &DAG, DebugLoc dl) {
6137 MVT VT = SVOp->getValueType(0).getSimpleVT();
6138 unsigned NumElems = VT.getVectorNumElements();
6141 switch (VT.SimpleTy) {
6142 default: llvm_unreachable("Unexpected!");
6143 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6144 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6145 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6146 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6147 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6148 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6151 SmallVector<int, 8> MaskVec;
6152 for (unsigned i = 0; i != NumElems; i += Scale) {
6154 for (unsigned j = 0; j != Scale; ++j) {
6155 int EltIdx = SVOp->getMaskElt(i+j);
6159 StartIdx = (EltIdx / Scale);
6160 if (EltIdx != (int)(StartIdx*Scale + j))
6163 MaskVec.push_back(StartIdx);
6166 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6167 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6168 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6171 /// getVZextMovL - Return a zero-extending vector move low node.
6173 static SDValue getVZextMovL(EVT VT, EVT OpVT,
6174 SDValue SrcOp, SelectionDAG &DAG,
6175 const X86Subtarget *Subtarget, DebugLoc dl) {
6176 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6177 LoadSDNode *LD = NULL;
6178 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6179 LD = dyn_cast<LoadSDNode>(SrcOp);
6181 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6183 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6184 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6185 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6186 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6187 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6189 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6190 return DAG.getNode(ISD::BITCAST, dl, VT,
6191 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6192 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6200 return DAG.getNode(ISD::BITCAST, dl, VT,
6201 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6202 DAG.getNode(ISD::BITCAST, dl,
6206 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6207 /// which could not be matched by any known target speficic shuffle
6209 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6211 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6212 if (NewOp.getNode())
6215 EVT VT = SVOp->getValueType(0);
6217 unsigned NumElems = VT.getVectorNumElements();
6218 unsigned NumLaneElems = NumElems / 2;
6220 DebugLoc dl = SVOp->getDebugLoc();
6221 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6222 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6225 SmallVector<int, 16> Mask;
6226 for (unsigned l = 0; l < 2; ++l) {
6227 // Build a shuffle mask for the output, discovering on the fly which
6228 // input vectors to use as shuffle operands (recorded in InputUsed).
6229 // If building a suitable shuffle vector proves too hard, then bail
6230 // out with UseBuildVector set.
6231 bool UseBuildVector = false;
6232 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6233 unsigned LaneStart = l * NumLaneElems;
6234 for (unsigned i = 0; i != NumLaneElems; ++i) {
6235 // The mask element. This indexes into the input.
6236 int Idx = SVOp->getMaskElt(i+LaneStart);
6238 // the mask element does not index into any input vector.
6243 // The input vector this mask element indexes into.
6244 int Input = Idx / NumLaneElems;
6246 // Turn the index into an offset from the start of the input vector.
6247 Idx -= Input * NumLaneElems;
6249 // Find or create a shuffle vector operand to hold this input.
6251 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6252 if (InputUsed[OpNo] == Input)
6253 // This input vector is already an operand.
6255 if (InputUsed[OpNo] < 0) {
6256 // Create a new operand for this input vector.
6257 InputUsed[OpNo] = Input;
6262 if (OpNo >= array_lengthof(InputUsed)) {
6263 // More than two input vectors used! Give up on trying to create a
6264 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6265 UseBuildVector = true;
6269 // Add the mask index for the new shuffle vector.
6270 Mask.push_back(Idx + OpNo * NumLaneElems);
6273 if (UseBuildVector) {
6274 SmallVector<SDValue, 16> SVOps;
6275 for (unsigned i = 0; i != NumLaneElems; ++i) {
6276 // The mask element. This indexes into the input.
6277 int Idx = SVOp->getMaskElt(i+LaneStart);
6279 SVOps.push_back(DAG.getUNDEF(EltVT));
6283 // The input vector this mask element indexes into.
6284 int Input = Idx / NumElems;
6286 // Turn the index into an offset from the start of the input vector.
6287 Idx -= Input * NumElems;
6289 // Extract the vector element by hand.
6290 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6291 SVOp->getOperand(Input),
6292 DAG.getIntPtrConstant(Idx)));
6295 // Construct the output using a BUILD_VECTOR.
6296 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6298 } else if (InputUsed[0] < 0) {
6299 // No input vectors were used! The result is undefined.
6300 Output[l] = DAG.getUNDEF(NVT);
6302 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6303 (InputUsed[0] % 2) * NumLaneElems,
6305 // If only one input was used, use an undefined vector for the other.
6306 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6307 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6308 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6309 // At least one input vector was used. Create a new shuffle vector.
6310 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6316 // Concatenate the result back
6317 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6320 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6321 /// 4 elements, and match them with several different shuffle types.
6323 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6324 SDValue V1 = SVOp->getOperand(0);
6325 SDValue V2 = SVOp->getOperand(1);
6326 DebugLoc dl = SVOp->getDebugLoc();
6327 EVT VT = SVOp->getValueType(0);
6329 assert(VT.is128BitVector() && "Unsupported vector size");
6331 std::pair<int, int> Locs[4];
6332 int Mask1[] = { -1, -1, -1, -1 };
6333 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6337 for (unsigned i = 0; i != 4; ++i) {
6338 int Idx = PermMask[i];
6340 Locs[i] = std::make_pair(-1, -1);
6342 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6344 Locs[i] = std::make_pair(0, NumLo);
6348 Locs[i] = std::make_pair(1, NumHi);
6350 Mask1[2+NumHi] = Idx;
6356 if (NumLo <= 2 && NumHi <= 2) {
6357 // If no more than two elements come from either vector. This can be
6358 // implemented with two shuffles. First shuffle gather the elements.
6359 // The second shuffle, which takes the first shuffle as both of its
6360 // vector operands, put the elements into the right order.
6361 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6363 int Mask2[] = { -1, -1, -1, -1 };
6365 for (unsigned i = 0; i != 4; ++i)
6366 if (Locs[i].first != -1) {
6367 unsigned Idx = (i < 2) ? 0 : 4;
6368 Idx += Locs[i].first * 2 + Locs[i].second;
6372 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6375 if (NumLo == 3 || NumHi == 3) {
6376 // Otherwise, we must have three elements from one vector, call it X, and
6377 // one element from the other, call it Y. First, use a shufps to build an
6378 // intermediate vector with the one element from Y and the element from X
6379 // that will be in the same half in the final destination (the indexes don't
6380 // matter). Then, use a shufps to build the final vector, taking the half
6381 // containing the element from Y from the intermediate, and the other half
6384 // Normalize it so the 3 elements come from V1.
6385 CommuteVectorShuffleMask(PermMask, 4);
6389 // Find the element from V2.
6391 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6392 int Val = PermMask[HiIndex];
6399 Mask1[0] = PermMask[HiIndex];
6401 Mask1[2] = PermMask[HiIndex^1];
6403 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6406 Mask1[0] = PermMask[0];
6407 Mask1[1] = PermMask[1];
6408 Mask1[2] = HiIndex & 1 ? 6 : 4;
6409 Mask1[3] = HiIndex & 1 ? 4 : 6;
6410 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6413 Mask1[0] = HiIndex & 1 ? 2 : 0;
6414 Mask1[1] = HiIndex & 1 ? 0 : 2;
6415 Mask1[2] = PermMask[2];
6416 Mask1[3] = PermMask[3];
6421 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6424 // Break it into (shuffle shuffle_hi, shuffle_lo).
6425 int LoMask[] = { -1, -1, -1, -1 };
6426 int HiMask[] = { -1, -1, -1, -1 };
6428 int *MaskPtr = LoMask;
6429 unsigned MaskIdx = 0;
6432 for (unsigned i = 0; i != 4; ++i) {
6439 int Idx = PermMask[i];
6441 Locs[i] = std::make_pair(-1, -1);
6442 } else if (Idx < 4) {
6443 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6444 MaskPtr[LoIdx] = Idx;
6447 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6448 MaskPtr[HiIdx] = Idx;
6453 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6454 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6455 int MaskOps[] = { -1, -1, -1, -1 };
6456 for (unsigned i = 0; i != 4; ++i)
6457 if (Locs[i].first != -1)
6458 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6459 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6462 static bool MayFoldVectorLoad(SDValue V) {
6463 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6464 V = V.getOperand(0);
6466 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6467 V = V.getOperand(0);
6468 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6469 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6470 // BUILD_VECTOR (load), undef
6471 V = V.getOperand(0);
6473 return MayFoldLoad(V);
6477 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6478 EVT VT = Op.getValueType();
6480 // Canonizalize to v2f64.
6481 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6482 return DAG.getNode(ISD::BITCAST, dl, VT,
6483 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6488 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6490 SDValue V1 = Op.getOperand(0);
6491 SDValue V2 = Op.getOperand(1);
6492 EVT VT = Op.getValueType();
6494 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6496 if (HasSSE2 && VT == MVT::v2f64)
6497 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6499 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6500 return DAG.getNode(ISD::BITCAST, dl, VT,
6501 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6502 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6503 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6507 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6508 SDValue V1 = Op.getOperand(0);
6509 SDValue V2 = Op.getOperand(1);
6510 EVT VT = Op.getValueType();
6512 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6513 "unsupported shuffle type");
6515 if (V2.getOpcode() == ISD::UNDEF)
6519 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6523 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6524 SDValue V1 = Op.getOperand(0);
6525 SDValue V2 = Op.getOperand(1);
6526 EVT VT = Op.getValueType();
6527 unsigned NumElems = VT.getVectorNumElements();
6529 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6530 // operand of these instructions is only memory, so check if there's a
6531 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6533 bool CanFoldLoad = false;
6535 // Trivial case, when V2 comes from a load.
6536 if (MayFoldVectorLoad(V2))
6539 // When V1 is a load, it can be folded later into a store in isel, example:
6540 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6542 // (MOVLPSmr addr:$src1, VR128:$src2)
6543 // So, recognize this potential and also use MOVLPS or MOVLPD
6544 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6547 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6549 if (HasSSE2 && NumElems == 2)
6550 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6553 // If we don't care about the second element, proceed to use movss.
6554 if (SVOp->getMaskElt(1) != -1)
6555 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6558 // movl and movlp will both match v2i64, but v2i64 is never matched by
6559 // movl earlier because we make it strict to avoid messing with the movlp load
6560 // folding logic (see the code above getMOVLP call). Match it here then,
6561 // this is horrible, but will stay like this until we move all shuffle
6562 // matching to x86 specific nodes. Note that for the 1st condition all
6563 // types are matched with movsd.
6565 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6566 // as to remove this logic from here, as much as possible
6567 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6568 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6569 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6572 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6574 // Invert the operand order and use SHUFPS to match it.
6575 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6576 getShuffleSHUFImmediate(SVOp), DAG);
6579 // Reduce a vector shuffle to zext.
6581 X86TargetLowering::lowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
6582 // PMOVZX is only available from SSE41.
6583 if (!Subtarget->hasSSE41())
6586 EVT VT = Op.getValueType();
6588 // Only AVX2 support 256-bit vector integer extending.
6589 if (!Subtarget->hasInt256() && VT.is256BitVector())
6592 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6593 DebugLoc DL = Op.getDebugLoc();
6594 SDValue V1 = Op.getOperand(0);
6595 SDValue V2 = Op.getOperand(1);
6596 unsigned NumElems = VT.getVectorNumElements();
6598 // Extending is an unary operation and the element type of the source vector
6599 // won't be equal to or larger than i64.
6600 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6601 VT.getVectorElementType() == MVT::i64)
6604 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
6605 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
6606 while ((1U << Shift) < NumElems) {
6607 if (SVOp->getMaskElt(1U << Shift) == 1)
6610 // The maximal ratio is 8, i.e. from i8 to i64.
6615 // Check the shuffle mask.
6616 unsigned Mask = (1U << Shift) - 1;
6617 for (unsigned i = 0; i != NumElems; ++i) {
6618 int EltIdx = SVOp->getMaskElt(i);
6619 if ((i & Mask) != 0 && EltIdx != -1)
6621 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
6625 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
6626 EVT NeVT = EVT::getIntegerVT(*DAG.getContext(), NBits);
6627 EVT NVT = EVT::getVectorVT(*DAG.getContext(), NeVT, NumElems >> Shift);
6629 if (!isTypeLegal(NVT))
6632 // Simplify the operand as it's prepared to be fed into shuffle.
6633 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
6634 if (V1.getOpcode() == ISD::BITCAST &&
6635 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6636 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6638 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
6639 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
6640 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
6641 ConstantSDNode *CIdx =
6642 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
6643 // If it's foldable, i.e. normal load with single use, we will let code
6644 // selection to fold it. Otherwise, we will short the conversion sequence.
6645 if (CIdx && CIdx->getZExtValue() == 0 &&
6646 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse()))
6647 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6650 return DAG.getNode(ISD::BITCAST, DL, VT,
6651 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
6655 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6656 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6657 EVT VT = Op.getValueType();
6658 DebugLoc dl = Op.getDebugLoc();
6659 SDValue V1 = Op.getOperand(0);
6660 SDValue V2 = Op.getOperand(1);
6662 if (isZeroShuffle(SVOp))
6663 return getZeroVector(VT, Subtarget, DAG, dl);
6665 // Handle splat operations
6666 if (SVOp->isSplat()) {
6667 unsigned NumElem = VT.getVectorNumElements();
6668 int Size = VT.getSizeInBits();
6670 // Use vbroadcast whenever the splat comes from a foldable load
6671 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6672 if (Broadcast.getNode())
6675 // Handle splats by matching through known shuffle masks
6676 if ((Size == 128 && NumElem <= 4) ||
6677 (Size == 256 && NumElem <= 8))
6680 // All remaning splats are promoted to target supported vector shuffles.
6681 return PromoteSplat(SVOp, DAG);
6684 // Check integer expanding shuffles.
6685 SDValue NewOp = lowerVectorIntExtend(Op, DAG);
6686 if (NewOp.getNode())
6689 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6691 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6692 VT == MVT::v16i16 || VT == MVT::v32i8) {
6693 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6694 if (NewOp.getNode())
6695 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6696 } else if ((VT == MVT::v4i32 ||
6697 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6698 // FIXME: Figure out a cleaner way to do this.
6699 // Try to make use of movq to zero out the top part.
6700 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6701 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6702 if (NewOp.getNode()) {
6703 EVT NewVT = NewOp.getValueType();
6704 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6705 NewVT, true, false))
6706 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6707 DAG, Subtarget, dl);
6709 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6710 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6711 if (NewOp.getNode()) {
6712 EVT NewVT = NewOp.getValueType();
6713 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6714 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6715 DAG, Subtarget, dl);
6723 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6724 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6725 SDValue V1 = Op.getOperand(0);
6726 SDValue V2 = Op.getOperand(1);
6727 EVT VT = Op.getValueType();
6728 DebugLoc dl = Op.getDebugLoc();
6729 unsigned NumElems = VT.getVectorNumElements();
6730 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6731 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6732 bool V1IsSplat = false;
6733 bool V2IsSplat = false;
6734 bool HasSSE2 = Subtarget->hasSSE2();
6735 bool HasFp256 = Subtarget->hasFp256();
6736 bool HasInt256 = Subtarget->hasInt256();
6737 MachineFunction &MF = DAG.getMachineFunction();
6738 bool OptForSize = MF.getFunction()->getFnAttributes().
6739 hasAttribute(Attributes::OptimizeForSize);
6741 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6743 if (V1IsUndef && V2IsUndef)
6744 return DAG.getUNDEF(VT);
6746 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6748 // Vector shuffle lowering takes 3 steps:
6750 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6751 // narrowing and commutation of operands should be handled.
6752 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6754 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6755 // so the shuffle can be broken into other shuffles and the legalizer can
6756 // try the lowering again.
6758 // The general idea is that no vector_shuffle operation should be left to
6759 // be matched during isel, all of them must be converted to a target specific
6762 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6763 // narrowing and commutation of operands should be handled. The actual code
6764 // doesn't include all of those, work in progress...
6765 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6766 if (NewOp.getNode())
6769 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6771 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6772 // unpckh_undef). Only use pshufd if speed is more important than size.
6773 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6774 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6775 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6776 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6778 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6779 V2IsUndef && MayFoldVectorLoad(V1))
6780 return getMOVDDup(Op, dl, V1, DAG);
6782 if (isMOVHLPS_v_undef_Mask(M, VT))
6783 return getMOVHighToLow(Op, dl, DAG);
6785 // Use to match splats
6786 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
6787 (VT == MVT::v2f64 || VT == MVT::v2i64))
6788 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6790 if (isPSHUFDMask(M, VT)) {
6791 // The actual implementation will match the mask in the if above and then
6792 // during isel it can match several different instructions, not only pshufd
6793 // as its name says, sad but true, emulate the behavior for now...
6794 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6795 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6797 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6799 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6800 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6802 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
6803 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
6806 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6810 // Check if this can be converted into a logical shift.
6811 bool isLeft = false;
6814 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6815 if (isShift && ShVal.hasOneUse()) {
6816 // If the shifted value has multiple uses, it may be cheaper to use
6817 // v_set0 + movlhps or movhlps, etc.
6818 EVT EltVT = VT.getVectorElementType();
6819 ShAmt *= EltVT.getSizeInBits();
6820 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6823 if (isMOVLMask(M, VT)) {
6824 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6825 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6826 if (!isMOVLPMask(M, VT)) {
6827 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6828 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6830 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6831 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6835 // FIXME: fold these into legal mask.
6836 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
6837 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6839 if (isMOVHLPSMask(M, VT))
6840 return getMOVHighToLow(Op, dl, DAG);
6842 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6843 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6845 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6846 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6848 if (isMOVLPMask(M, VT))
6849 return getMOVLP(Op, dl, DAG, HasSSE2);
6851 if (ShouldXformToMOVHLPS(M, VT) ||
6852 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6853 return CommuteVectorShuffle(SVOp, DAG);
6856 // No better options. Use a vshldq / vsrldq.
6857 EVT EltVT = VT.getVectorElementType();
6858 ShAmt *= EltVT.getSizeInBits();
6859 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6862 bool Commuted = false;
6863 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6864 // 1,1,1,1 -> v8i16 though.
6865 V1IsSplat = isSplatVector(V1.getNode());
6866 V2IsSplat = isSplatVector(V2.getNode());
6868 // Canonicalize the splat or undef, if present, to be on the RHS.
6869 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6870 CommuteVectorShuffleMask(M, NumElems);
6872 std::swap(V1IsSplat, V2IsSplat);
6876 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6877 // Shuffling low element of v1 into undef, just return v1.
6880 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6881 // the instruction selector will not match, so get a canonical MOVL with
6882 // swapped operands to undo the commute.
6883 return getMOVL(DAG, dl, VT, V2, V1);
6886 if (isUNPCKLMask(M, VT, HasInt256))
6887 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6889 if (isUNPCKHMask(M, VT, HasInt256))
6890 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6893 // Normalize mask so all entries that point to V2 points to its first
6894 // element then try to match unpck{h|l} again. If match, return a
6895 // new vector_shuffle with the corrected mask.p
6896 SmallVector<int, 8> NewMask(M.begin(), M.end());
6897 NormalizeMask(NewMask, NumElems);
6898 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
6899 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6900 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
6901 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6905 // Commute is back and try unpck* again.
6906 // FIXME: this seems wrong.
6907 CommuteVectorShuffleMask(M, NumElems);
6909 std::swap(V1IsSplat, V2IsSplat);
6912 if (isUNPCKLMask(M, VT, HasInt256))
6913 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6915 if (isUNPCKHMask(M, VT, HasInt256))
6916 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6919 // Normalize the node to match x86 shuffle ops if needed
6920 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
6921 return CommuteVectorShuffle(SVOp, DAG);
6923 // The checks below are all present in isShuffleMaskLegal, but they are
6924 // inlined here right now to enable us to directly emit target specific
6925 // nodes, and remove one by one until they don't return Op anymore.
6927 if (isPALIGNRMask(M, VT, Subtarget))
6928 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6929 getShufflePALIGNRImmediate(SVOp),
6932 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6933 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6934 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6935 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6938 if (isPSHUFHWMask(M, VT, HasInt256))
6939 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6940 getShufflePSHUFHWImmediate(SVOp),
6943 if (isPSHUFLWMask(M, VT, HasInt256))
6944 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6945 getShufflePSHUFLWImmediate(SVOp),
6948 if (isSHUFPMask(M, VT, HasFp256))
6949 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6950 getShuffleSHUFImmediate(SVOp), DAG);
6952 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6953 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6954 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6955 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6957 //===--------------------------------------------------------------------===//
6958 // Generate target specific nodes for 128 or 256-bit shuffles only
6959 // supported in the AVX instruction set.
6962 // Handle VMOVDDUPY permutations
6963 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
6964 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6966 // Handle VPERMILPS/D* permutations
6967 if (isVPERMILPMask(M, VT, HasFp256)) {
6968 if (HasInt256 && VT == MVT::v8i32)
6969 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6970 getShuffleSHUFImmediate(SVOp), DAG);
6971 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6972 getShuffleSHUFImmediate(SVOp), DAG);
6975 // Handle VPERM2F128/VPERM2I128 permutations
6976 if (isVPERM2X128Mask(M, VT, HasFp256))
6977 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6978 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6980 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6981 if (BlendOp.getNode())
6984 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6985 SmallVector<SDValue, 8> permclMask;
6986 for (unsigned i = 0; i != 8; ++i) {
6987 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6989 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6991 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6992 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6993 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6996 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6997 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6998 getShuffleCLImmediate(SVOp), DAG);
7001 //===--------------------------------------------------------------------===//
7002 // Since no target specific shuffle was selected for this generic one,
7003 // lower it into other known shuffles. FIXME: this isn't true yet, but
7004 // this is the plan.
7007 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7008 if (VT == MVT::v8i16) {
7009 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7010 if (NewOp.getNode())
7014 if (VT == MVT::v16i8) {
7015 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7016 if (NewOp.getNode())
7020 if (VT == MVT::v32i8) {
7021 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7022 if (NewOp.getNode())
7026 // Handle all 128-bit wide vectors with 4 elements, and match them with
7027 // several different shuffle types.
7028 if (NumElems == 4 && VT.is128BitVector())
7029 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7031 // Handle general 256-bit shuffles
7032 if (VT.is256BitVector())
7033 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7039 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
7040 SelectionDAG &DAG) const {
7041 EVT VT = Op.getValueType();
7042 DebugLoc dl = Op.getDebugLoc();
7044 if (!Op.getOperand(0).getValueType().is128BitVector())
7047 if (VT.getSizeInBits() == 8) {
7048 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7049 Op.getOperand(0), Op.getOperand(1));
7050 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7051 DAG.getValueType(VT));
7052 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7055 if (VT.getSizeInBits() == 16) {
7056 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7057 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7059 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7060 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7061 DAG.getNode(ISD::BITCAST, dl,
7065 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7066 Op.getOperand(0), Op.getOperand(1));
7067 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7068 DAG.getValueType(VT));
7069 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7072 if (VT == MVT::f32) {
7073 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7074 // the result back to FR32 register. It's only worth matching if the
7075 // result has a single use which is a store or a bitcast to i32. And in
7076 // the case of a store, it's not worth it if the index is a constant 0,
7077 // because a MOVSSmr can be used instead, which is smaller and faster.
7078 if (!Op.hasOneUse())
7080 SDNode *User = *Op.getNode()->use_begin();
7081 if ((User->getOpcode() != ISD::STORE ||
7082 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7083 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7084 (User->getOpcode() != ISD::BITCAST ||
7085 User->getValueType(0) != MVT::i32))
7087 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7088 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7091 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7094 if (VT == MVT::i32 || VT == MVT::i64) {
7095 // ExtractPS/pextrq works with constant index.
7096 if (isa<ConstantSDNode>(Op.getOperand(1)))
7104 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7105 SelectionDAG &DAG) const {
7106 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7109 SDValue Vec = Op.getOperand(0);
7110 EVT VecVT = Vec.getValueType();
7112 // If this is a 256-bit vector result, first extract the 128-bit vector and
7113 // then extract the element from the 128-bit vector.
7114 if (VecVT.is256BitVector()) {
7115 DebugLoc dl = Op.getNode()->getDebugLoc();
7116 unsigned NumElems = VecVT.getVectorNumElements();
7117 SDValue Idx = Op.getOperand(1);
7118 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7120 // Get the 128-bit vector.
7121 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7123 if (IdxVal >= NumElems/2)
7124 IdxVal -= NumElems/2;
7125 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7126 DAG.getConstant(IdxVal, MVT::i32));
7129 assert(VecVT.is128BitVector() && "Unexpected vector length");
7131 if (Subtarget->hasSSE41()) {
7132 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7137 EVT VT = Op.getValueType();
7138 DebugLoc dl = Op.getDebugLoc();
7139 // TODO: handle v16i8.
7140 if (VT.getSizeInBits() == 16) {
7141 SDValue Vec = Op.getOperand(0);
7142 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7144 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7145 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7146 DAG.getNode(ISD::BITCAST, dl,
7149 // Transform it so it match pextrw which produces a 32-bit result.
7150 EVT EltVT = MVT::i32;
7151 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7152 Op.getOperand(0), Op.getOperand(1));
7153 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7154 DAG.getValueType(VT));
7155 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7158 if (VT.getSizeInBits() == 32) {
7159 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7163 // SHUFPS the element to the lowest double word, then movss.
7164 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7165 EVT VVT = Op.getOperand(0).getValueType();
7166 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7167 DAG.getUNDEF(VVT), Mask);
7168 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7169 DAG.getIntPtrConstant(0));
7172 if (VT.getSizeInBits() == 64) {
7173 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7174 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7175 // to match extract_elt for f64.
7176 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7180 // UNPCKHPD the element to the lowest double word, then movsd.
7181 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7182 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7183 int Mask[2] = { 1, -1 };
7184 EVT VVT = Op.getOperand(0).getValueType();
7185 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7186 DAG.getUNDEF(VVT), Mask);
7187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7188 DAG.getIntPtrConstant(0));
7195 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
7196 SelectionDAG &DAG) const {
7197 EVT VT = Op.getValueType();
7198 EVT EltVT = VT.getVectorElementType();
7199 DebugLoc dl = Op.getDebugLoc();
7201 SDValue N0 = Op.getOperand(0);
7202 SDValue N1 = Op.getOperand(1);
7203 SDValue N2 = Op.getOperand(2);
7205 if (!VT.is128BitVector())
7208 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7209 isa<ConstantSDNode>(N2)) {
7211 if (VT == MVT::v8i16)
7212 Opc = X86ISD::PINSRW;
7213 else if (VT == MVT::v16i8)
7214 Opc = X86ISD::PINSRB;
7216 Opc = X86ISD::PINSRB;
7218 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7220 if (N1.getValueType() != MVT::i32)
7221 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7222 if (N2.getValueType() != MVT::i32)
7223 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7224 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7227 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7228 // Bits [7:6] of the constant are the source select. This will always be
7229 // zero here. The DAG Combiner may combine an extract_elt index into these
7230 // bits. For example (insert (extract, 3), 2) could be matched by putting
7231 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7232 // Bits [5:4] of the constant are the destination select. This is the
7233 // value of the incoming immediate.
7234 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7235 // combine either bitwise AND or insert of float 0.0 to set these bits.
7236 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7237 // Create this as a scalar to vector..
7238 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7239 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7242 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7243 // PINSR* works with constant index.
7250 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7251 EVT VT = Op.getValueType();
7252 EVT EltVT = VT.getVectorElementType();
7254 DebugLoc dl = Op.getDebugLoc();
7255 SDValue N0 = Op.getOperand(0);
7256 SDValue N1 = Op.getOperand(1);
7257 SDValue N2 = Op.getOperand(2);
7259 // If this is a 256-bit vector result, first extract the 128-bit vector,
7260 // insert the element into the extracted half and then place it back.
7261 if (VT.is256BitVector()) {
7262 if (!isa<ConstantSDNode>(N2))
7265 // Get the desired 128-bit vector half.
7266 unsigned NumElems = VT.getVectorNumElements();
7267 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7268 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7270 // Insert the element into the desired half.
7271 bool Upper = IdxVal >= NumElems/2;
7272 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7273 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7275 // Insert the changed part back to the 256-bit vector
7276 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7279 if (Subtarget->hasSSE41())
7280 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7282 if (EltVT == MVT::i8)
7285 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7286 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7287 // as its second argument.
7288 if (N1.getValueType() != MVT::i32)
7289 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7290 if (N2.getValueType() != MVT::i32)
7291 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7292 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7297 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7298 LLVMContext *Context = DAG.getContext();
7299 DebugLoc dl = Op.getDebugLoc();
7300 EVT OpVT = Op.getValueType();
7302 // If this is a 256-bit vector result, first insert into a 128-bit
7303 // vector and then insert into the 256-bit vector.
7304 if (!OpVT.is128BitVector()) {
7305 // Insert into a 128-bit vector.
7306 EVT VT128 = EVT::getVectorVT(*Context,
7307 OpVT.getVectorElementType(),
7308 OpVT.getVectorNumElements() / 2);
7310 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7312 // Insert the 128-bit vector.
7313 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7316 if (OpVT == MVT::v1i64 &&
7317 Op.getOperand(0).getValueType() == MVT::i64)
7318 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7320 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7321 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7322 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7323 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7326 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7327 // a simple subregister reference or explicit instructions to grab
7328 // upper bits of a vector.
7329 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7330 SelectionDAG &DAG) {
7331 if (Subtarget->hasFp256()) {
7332 DebugLoc dl = Op.getNode()->getDebugLoc();
7333 SDValue Vec = Op.getNode()->getOperand(0);
7334 SDValue Idx = Op.getNode()->getOperand(1);
7336 if (Op.getNode()->getValueType(0).is128BitVector() &&
7337 Vec.getNode()->getValueType(0).is256BitVector() &&
7338 isa<ConstantSDNode>(Idx)) {
7339 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7340 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7346 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7347 // simple superregister reference or explicit instructions to insert
7348 // the upper bits of a vector.
7349 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7350 SelectionDAG &DAG) {
7351 if (Subtarget->hasFp256()) {
7352 DebugLoc dl = Op.getNode()->getDebugLoc();
7353 SDValue Vec = Op.getNode()->getOperand(0);
7354 SDValue SubVec = Op.getNode()->getOperand(1);
7355 SDValue Idx = Op.getNode()->getOperand(2);
7357 if (Op.getNode()->getValueType(0).is256BitVector() &&
7358 SubVec.getNode()->getValueType(0).is128BitVector() &&
7359 isa<ConstantSDNode>(Idx)) {
7360 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7361 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7367 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7368 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7369 // one of the above mentioned nodes. It has to be wrapped because otherwise
7370 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7371 // be used to form addressing mode. These wrapped nodes will be selected
7374 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7375 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7377 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7379 unsigned char OpFlag = 0;
7380 unsigned WrapperKind = X86ISD::Wrapper;
7381 CodeModel::Model M = getTargetMachine().getCodeModel();
7383 if (Subtarget->isPICStyleRIPRel() &&
7384 (M == CodeModel::Small || M == CodeModel::Kernel))
7385 WrapperKind = X86ISD::WrapperRIP;
7386 else if (Subtarget->isPICStyleGOT())
7387 OpFlag = X86II::MO_GOTOFF;
7388 else if (Subtarget->isPICStyleStubPIC())
7389 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7391 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7393 CP->getOffset(), OpFlag);
7394 DebugLoc DL = CP->getDebugLoc();
7395 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7396 // With PIC, the address is actually $g + Offset.
7398 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7399 DAG.getNode(X86ISD::GlobalBaseReg,
7400 DebugLoc(), getPointerTy()),
7407 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7408 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7410 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7412 unsigned char OpFlag = 0;
7413 unsigned WrapperKind = X86ISD::Wrapper;
7414 CodeModel::Model M = getTargetMachine().getCodeModel();
7416 if (Subtarget->isPICStyleRIPRel() &&
7417 (M == CodeModel::Small || M == CodeModel::Kernel))
7418 WrapperKind = X86ISD::WrapperRIP;
7419 else if (Subtarget->isPICStyleGOT())
7420 OpFlag = X86II::MO_GOTOFF;
7421 else if (Subtarget->isPICStyleStubPIC())
7422 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7424 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7426 DebugLoc DL = JT->getDebugLoc();
7427 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7429 // With PIC, the address is actually $g + Offset.
7431 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7432 DAG.getNode(X86ISD::GlobalBaseReg,
7433 DebugLoc(), getPointerTy()),
7440 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7441 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7443 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7445 unsigned char OpFlag = 0;
7446 unsigned WrapperKind = X86ISD::Wrapper;
7447 CodeModel::Model M = getTargetMachine().getCodeModel();
7449 if (Subtarget->isPICStyleRIPRel() &&
7450 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7451 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7452 OpFlag = X86II::MO_GOTPCREL;
7453 WrapperKind = X86ISD::WrapperRIP;
7454 } else if (Subtarget->isPICStyleGOT()) {
7455 OpFlag = X86II::MO_GOT;
7456 } else if (Subtarget->isPICStyleStubPIC()) {
7457 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7458 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7459 OpFlag = X86II::MO_DARWIN_NONLAZY;
7462 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7464 DebugLoc DL = Op.getDebugLoc();
7465 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7468 // With PIC, the address is actually $g + Offset.
7469 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7470 !Subtarget->is64Bit()) {
7471 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7472 DAG.getNode(X86ISD::GlobalBaseReg,
7473 DebugLoc(), getPointerTy()),
7477 // For symbols that require a load from a stub to get the address, emit the
7479 if (isGlobalStubReference(OpFlag))
7480 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7481 MachinePointerInfo::getGOT(), false, false, false, 0);
7487 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7488 // Create the TargetBlockAddressAddress node.
7489 unsigned char OpFlags =
7490 Subtarget->ClassifyBlockAddressReference();
7491 CodeModel::Model M = getTargetMachine().getCodeModel();
7492 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7493 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7494 DebugLoc dl = Op.getDebugLoc();
7495 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7498 if (Subtarget->isPICStyleRIPRel() &&
7499 (M == CodeModel::Small || M == CodeModel::Kernel))
7500 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7502 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7504 // With PIC, the address is actually $g + Offset.
7505 if (isGlobalRelativeToPICBase(OpFlags)) {
7506 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7507 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7515 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7517 SelectionDAG &DAG) const {
7518 // Create the TargetGlobalAddress node, folding in the constant
7519 // offset if it is legal.
7520 unsigned char OpFlags =
7521 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7522 CodeModel::Model M = getTargetMachine().getCodeModel();
7524 if (OpFlags == X86II::MO_NO_FLAG &&
7525 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7526 // A direct static reference to a global.
7527 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7530 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7533 if (Subtarget->isPICStyleRIPRel() &&
7534 (M == CodeModel::Small || M == CodeModel::Kernel))
7535 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7537 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7539 // With PIC, the address is actually $g + Offset.
7540 if (isGlobalRelativeToPICBase(OpFlags)) {
7541 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7542 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7546 // For globals that require a load from a stub to get the address, emit the
7548 if (isGlobalStubReference(OpFlags))
7549 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7550 MachinePointerInfo::getGOT(), false, false, false, 0);
7552 // If there was a non-zero offset that we didn't fold, create an explicit
7555 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7556 DAG.getConstant(Offset, getPointerTy()));
7562 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7563 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7564 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7565 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7569 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7570 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7571 unsigned char OperandFlags, bool LocalDynamic = false) {
7572 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7573 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7574 DebugLoc dl = GA->getDebugLoc();
7575 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7576 GA->getValueType(0),
7580 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7584 SDValue Ops[] = { Chain, TGA, *InFlag };
7585 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7587 SDValue Ops[] = { Chain, TGA };
7588 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7591 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7592 MFI->setAdjustsStack(true);
7594 SDValue Flag = Chain.getValue(1);
7595 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7598 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7600 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7603 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7604 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7605 DAG.getNode(X86ISD::GlobalBaseReg,
7606 DebugLoc(), PtrVT), InFlag);
7607 InFlag = Chain.getValue(1);
7609 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7612 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7614 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7616 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7617 X86::RAX, X86II::MO_TLSGD);
7620 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7624 DebugLoc dl = GA->getDebugLoc();
7626 // Get the start address of the TLS block for this module.
7627 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7628 .getInfo<X86MachineFunctionInfo>();
7629 MFI->incNumLocalDynamicTLSAccesses();
7633 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7634 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7637 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7638 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7639 InFlag = Chain.getValue(1);
7640 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7641 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7644 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7648 unsigned char OperandFlags = X86II::MO_DTPOFF;
7649 unsigned WrapperKind = X86ISD::Wrapper;
7650 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7651 GA->getValueType(0),
7652 GA->getOffset(), OperandFlags);
7653 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7655 // Add x@dtpoff with the base.
7656 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7659 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7660 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7661 const EVT PtrVT, TLSModel::Model model,
7662 bool is64Bit, bool isPIC) {
7663 DebugLoc dl = GA->getDebugLoc();
7665 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7666 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7667 is64Bit ? 257 : 256));
7669 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7670 DAG.getIntPtrConstant(0),
7671 MachinePointerInfo(Ptr),
7672 false, false, false, 0);
7674 unsigned char OperandFlags = 0;
7675 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7677 unsigned WrapperKind = X86ISD::Wrapper;
7678 if (model == TLSModel::LocalExec) {
7679 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7680 } else if (model == TLSModel::InitialExec) {
7682 OperandFlags = X86II::MO_GOTTPOFF;
7683 WrapperKind = X86ISD::WrapperRIP;
7685 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7688 llvm_unreachable("Unexpected model");
7691 // emit "addl x@ntpoff,%eax" (local exec)
7692 // or "addl x@indntpoff,%eax" (initial exec)
7693 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7694 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7695 GA->getValueType(0),
7696 GA->getOffset(), OperandFlags);
7697 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7699 if (model == TLSModel::InitialExec) {
7700 if (isPIC && !is64Bit) {
7701 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7702 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7706 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7707 MachinePointerInfo::getGOT(), false, false, false,
7711 // The address of the thread local variable is the add of the thread
7712 // pointer with the offset of the variable.
7713 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7717 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7719 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7720 const GlobalValue *GV = GA->getGlobal();
7722 if (Subtarget->isTargetELF()) {
7723 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7726 case TLSModel::GeneralDynamic:
7727 if (Subtarget->is64Bit())
7728 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7729 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7730 case TLSModel::LocalDynamic:
7731 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7732 Subtarget->is64Bit());
7733 case TLSModel::InitialExec:
7734 case TLSModel::LocalExec:
7735 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7736 Subtarget->is64Bit(),
7737 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7739 llvm_unreachable("Unknown TLS model.");
7742 if (Subtarget->isTargetDarwin()) {
7743 // Darwin only has one model of TLS. Lower to that.
7744 unsigned char OpFlag = 0;
7745 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7746 X86ISD::WrapperRIP : X86ISD::Wrapper;
7748 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7750 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7751 !Subtarget->is64Bit();
7753 OpFlag = X86II::MO_TLVP_PIC_BASE;
7755 OpFlag = X86II::MO_TLVP;
7756 DebugLoc DL = Op.getDebugLoc();
7757 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7758 GA->getValueType(0),
7759 GA->getOffset(), OpFlag);
7760 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7762 // With PIC32, the address is actually $g + Offset.
7764 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7765 DAG.getNode(X86ISD::GlobalBaseReg,
7766 DebugLoc(), getPointerTy()),
7769 // Lowering the machine isd will make sure everything is in the right
7771 SDValue Chain = DAG.getEntryNode();
7772 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7773 SDValue Args[] = { Chain, Offset };
7774 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7776 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7777 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7778 MFI->setAdjustsStack(true);
7780 // And our return value (tls address) is in the standard call return value
7782 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7783 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7787 if (Subtarget->isTargetWindows()) {
7788 // Just use the implicit TLS architecture
7789 // Need to generate someting similar to:
7790 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7792 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7793 // mov rcx, qword [rdx+rcx*8]
7794 // mov eax, .tls$:tlsvar
7795 // [rax+rcx] contains the address
7796 // Windows 64bit: gs:0x58
7797 // Windows 32bit: fs:__tls_array
7799 // If GV is an alias then use the aliasee for determining
7800 // thread-localness.
7801 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7802 GV = GA->resolveAliasedGlobal(false);
7803 DebugLoc dl = GA->getDebugLoc();
7804 SDValue Chain = DAG.getEntryNode();
7806 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7807 // %gs:0x58 (64-bit).
7808 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7809 ? Type::getInt8PtrTy(*DAG.getContext(),
7811 : Type::getInt32PtrTy(*DAG.getContext(),
7814 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7815 Subtarget->is64Bit()
7816 ? DAG.getIntPtrConstant(0x58)
7817 : DAG.getExternalSymbol("_tls_array",
7819 MachinePointerInfo(Ptr),
7820 false, false, false, 0);
7822 // Load the _tls_index variable
7823 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7824 if (Subtarget->is64Bit())
7825 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7826 IDX, MachinePointerInfo(), MVT::i32,
7829 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7830 false, false, false, 0);
7832 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7834 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7836 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7837 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7838 false, false, false, 0);
7840 // Get the offset of start of .tls section
7841 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7842 GA->getValueType(0),
7843 GA->getOffset(), X86II::MO_SECREL);
7844 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7846 // The address of the thread local variable is the add of the thread
7847 // pointer with the offset of the variable.
7848 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7851 llvm_unreachable("TLS not implemented for this target.");
7855 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7856 /// and take a 2 x i32 value to shift plus a shift amount.
7857 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7858 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7859 EVT VT = Op.getValueType();
7860 unsigned VTBits = VT.getSizeInBits();
7861 DebugLoc dl = Op.getDebugLoc();
7862 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7863 SDValue ShOpLo = Op.getOperand(0);
7864 SDValue ShOpHi = Op.getOperand(1);
7865 SDValue ShAmt = Op.getOperand(2);
7866 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7867 DAG.getConstant(VTBits - 1, MVT::i8))
7868 : DAG.getConstant(0, VT);
7871 if (Op.getOpcode() == ISD::SHL_PARTS) {
7872 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7873 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7875 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7876 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7879 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7880 DAG.getConstant(VTBits, MVT::i8));
7881 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7882 AndNode, DAG.getConstant(0, MVT::i8));
7885 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7886 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7887 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7889 if (Op.getOpcode() == ISD::SHL_PARTS) {
7890 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7891 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7893 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7894 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7897 SDValue Ops[2] = { Lo, Hi };
7898 return DAG.getMergeValues(Ops, 2, dl);
7901 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7902 SelectionDAG &DAG) const {
7903 EVT SrcVT = Op.getOperand(0).getValueType();
7905 if (SrcVT.isVector())
7908 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7909 "Unknown SINT_TO_FP to lower!");
7911 // These are really Legal; return the operand so the caller accepts it as
7913 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7915 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7916 Subtarget->is64Bit()) {
7920 DebugLoc dl = Op.getDebugLoc();
7921 unsigned Size = SrcVT.getSizeInBits()/8;
7922 MachineFunction &MF = DAG.getMachineFunction();
7923 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7924 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7925 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7927 MachinePointerInfo::getFixedStack(SSFI),
7929 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7932 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7934 SelectionDAG &DAG) const {
7936 DebugLoc DL = Op.getDebugLoc();
7938 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7940 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7942 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7944 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7946 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7947 MachineMemOperand *MMO;
7949 int SSFI = FI->getIndex();
7951 DAG.getMachineFunction()
7952 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7953 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7955 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7956 StackSlot = StackSlot.getOperand(1);
7958 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7959 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7961 Tys, Ops, array_lengthof(Ops),
7965 Chain = Result.getValue(1);
7966 SDValue InFlag = Result.getValue(2);
7968 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7969 // shouldn't be necessary except that RFP cannot be live across
7970 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7971 MachineFunction &MF = DAG.getMachineFunction();
7972 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7973 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7974 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7975 Tys = DAG.getVTList(MVT::Other);
7977 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7979 MachineMemOperand *MMO =
7980 DAG.getMachineFunction()
7981 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7982 MachineMemOperand::MOStore, SSFISize, SSFISize);
7984 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7985 Ops, array_lengthof(Ops),
7986 Op.getValueType(), MMO);
7987 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7988 MachinePointerInfo::getFixedStack(SSFI),
7989 false, false, false, 0);
7995 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7996 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7997 SelectionDAG &DAG) const {
7998 // This algorithm is not obvious. Here it is what we're trying to output:
8001 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8002 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8006 pshufd $0x4e, %xmm0, %xmm1
8011 DebugLoc dl = Op.getDebugLoc();
8012 LLVMContext *Context = DAG.getContext();
8014 // Build some magic constants.
8015 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8016 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8017 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8019 SmallVector<Constant*,2> CV1;
8021 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
8023 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
8024 Constant *C1 = ConstantVector::get(CV1);
8025 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8027 // Load the 64-bit value into an XMM register.
8028 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8030 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8031 MachinePointerInfo::getConstantPool(),
8032 false, false, false, 16);
8033 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8034 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8037 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8038 MachinePointerInfo::getConstantPool(),
8039 false, false, false, 16);
8040 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8041 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8044 if (Subtarget->hasSSE3()) {
8045 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8046 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8048 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8049 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8051 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8052 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8056 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8057 DAG.getIntPtrConstant(0));
8060 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8061 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8062 SelectionDAG &DAG) const {
8063 DebugLoc dl = Op.getDebugLoc();
8064 // FP constant to bias correct the final result.
8065 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8068 // Load the 32-bit value into an XMM register.
8069 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8072 // Zero out the upper parts of the register.
8073 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8075 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8076 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8077 DAG.getIntPtrConstant(0));
8079 // Or the load with the bias.
8080 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8081 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8082 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8084 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8085 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8086 MVT::v2f64, Bias)));
8087 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8088 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8089 DAG.getIntPtrConstant(0));
8091 // Subtract the bias.
8092 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8094 // Handle final rounding.
8095 EVT DestVT = Op.getValueType();
8097 if (DestVT.bitsLT(MVT::f64))
8098 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8099 DAG.getIntPtrConstant(0));
8100 if (DestVT.bitsGT(MVT::f64))
8101 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8103 // Handle final rounding.
8107 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8108 SelectionDAG &DAG) const {
8109 SDValue N0 = Op.getOperand(0);
8110 EVT SVT = N0.getValueType();
8111 DebugLoc dl = Op.getDebugLoc();
8113 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8114 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8115 "Custom UINT_TO_FP is not supported!");
8117 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, SVT.getVectorNumElements());
8118 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8119 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8122 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8123 SelectionDAG &DAG) const {
8124 SDValue N0 = Op.getOperand(0);
8125 DebugLoc dl = Op.getDebugLoc();
8127 if (Op.getValueType().isVector())
8128 return lowerUINT_TO_FP_vec(Op, DAG);
8130 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8131 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8132 // the optimization here.
8133 if (DAG.SignBitIsZero(N0))
8134 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8136 EVT SrcVT = N0.getValueType();
8137 EVT DstVT = Op.getValueType();
8138 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8139 return LowerUINT_TO_FP_i64(Op, DAG);
8140 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8141 return LowerUINT_TO_FP_i32(Op, DAG);
8142 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8145 // Make a 64-bit buffer, and use it to build an FILD.
8146 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8147 if (SrcVT == MVT::i32) {
8148 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8149 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8150 getPointerTy(), StackSlot, WordOff);
8151 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8152 StackSlot, MachinePointerInfo(),
8154 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8155 OffsetSlot, MachinePointerInfo(),
8157 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8161 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8162 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8163 StackSlot, MachinePointerInfo(),
8165 // For i64 source, we need to add the appropriate power of 2 if the input
8166 // was negative. This is the same as the optimization in
8167 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8168 // we must be careful to do the computation in x87 extended precision, not
8169 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8170 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8171 MachineMemOperand *MMO =
8172 DAG.getMachineFunction()
8173 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8174 MachineMemOperand::MOLoad, 8, 8);
8176 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8177 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8178 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
8181 APInt FF(32, 0x5F800000ULL);
8183 // Check whether the sign bit is set.
8184 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
8185 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8188 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8189 SDValue FudgePtr = DAG.getConstantPool(
8190 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8193 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8194 SDValue Zero = DAG.getIntPtrConstant(0);
8195 SDValue Four = DAG.getIntPtrConstant(4);
8196 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8198 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8200 // Load the value out, extending it from f32 to f80.
8201 // FIXME: Avoid the extend by constructing the right constant pool?
8202 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8203 FudgePtr, MachinePointerInfo::getConstantPool(),
8204 MVT::f32, false, false, 4);
8205 // Extend everything to 80 bits to force it to be done on x87.
8206 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8207 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8210 std::pair<SDValue,SDValue> X86TargetLowering::
8211 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
8212 DebugLoc DL = Op.getDebugLoc();
8214 EVT DstTy = Op.getValueType();
8216 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8217 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8221 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8222 DstTy.getSimpleVT() >= MVT::i16 &&
8223 "Unknown FP_TO_INT to lower!");
8225 // These are really Legal.
8226 if (DstTy == MVT::i32 &&
8227 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8228 return std::make_pair(SDValue(), SDValue());
8229 if (Subtarget->is64Bit() &&
8230 DstTy == MVT::i64 &&
8231 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8232 return std::make_pair(SDValue(), SDValue());
8234 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8235 // stack slot, or into the FTOL runtime function.
8236 MachineFunction &MF = DAG.getMachineFunction();
8237 unsigned MemSize = DstTy.getSizeInBits()/8;
8238 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8239 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8242 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8243 Opc = X86ISD::WIN_FTOL;
8245 switch (DstTy.getSimpleVT().SimpleTy) {
8246 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8247 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8248 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8249 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8252 SDValue Chain = DAG.getEntryNode();
8253 SDValue Value = Op.getOperand(0);
8254 EVT TheVT = Op.getOperand(0).getValueType();
8255 // FIXME This causes a redundant load/store if the SSE-class value is already
8256 // in memory, such as if it is on the callstack.
8257 if (isScalarFPTypeInSSEReg(TheVT)) {
8258 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8259 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8260 MachinePointerInfo::getFixedStack(SSFI),
8262 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8264 Chain, StackSlot, DAG.getValueType(TheVT)
8267 MachineMemOperand *MMO =
8268 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8269 MachineMemOperand::MOLoad, MemSize, MemSize);
8270 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8272 Chain = Value.getValue(1);
8273 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8274 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8277 MachineMemOperand *MMO =
8278 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8279 MachineMemOperand::MOStore, MemSize, MemSize);
8281 if (Opc != X86ISD::WIN_FTOL) {
8282 // Build the FP_TO_INT*_IN_MEM
8283 SDValue Ops[] = { Chain, Value, StackSlot };
8284 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8285 Ops, 3, DstTy, MMO);
8286 return std::make_pair(FIST, StackSlot);
8288 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8289 DAG.getVTList(MVT::Other, MVT::Glue),
8291 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8292 MVT::i32, ftol.getValue(1));
8293 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8294 MVT::i32, eax.getValue(2));
8295 SDValue Ops[] = { eax, edx };
8296 SDValue pair = IsReplace
8297 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8298 : DAG.getMergeValues(Ops, 2, DL);
8299 return std::make_pair(pair, SDValue());
8303 SDValue X86TargetLowering::lowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const {
8304 DebugLoc DL = Op.getDebugLoc();
8305 EVT VT = Op.getValueType();
8306 SDValue In = Op.getOperand(0);
8307 EVT SVT = In.getValueType();
8309 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8310 VT.getVectorNumElements() != SVT.getVectorNumElements())
8313 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8315 // AVX2 has better support of integer extending.
8316 if (Subtarget->hasInt256())
8317 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8319 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8320 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8321 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8322 DAG.getVectorShuffle(MVT::v8i16, DL, In, DAG.getUNDEF(MVT::v8i16), &Mask[0]));
8324 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8327 SDValue X86TargetLowering::lowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8328 DebugLoc DL = Op.getDebugLoc();
8329 EVT VT = Op.getValueType();
8330 EVT SVT = Op.getOperand(0).getValueType();
8332 if (!VT.is128BitVector() || !SVT.is256BitVector() ||
8333 VT.getVectorNumElements() != SVT.getVectorNumElements())
8336 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8338 unsigned NumElems = VT.getVectorNumElements();
8339 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8342 SDValue In = Op.getOperand(0);
8343 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8344 // Prepare truncation shuffle mask
8345 for (unsigned i = 0; i != NumElems; ++i)
8347 SDValue V = DAG.getVectorShuffle(NVT, DL,
8348 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8349 DAG.getUNDEF(NVT), &MaskVec[0]);
8350 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8351 DAG.getIntPtrConstant(0));
8354 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8355 SelectionDAG &DAG) const {
8356 if (Op.getValueType().isVector()) {
8357 if (Op.getValueType() == MVT::v8i16)
8358 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), Op.getValueType(),
8359 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
8360 MVT::v8i32, Op.getOperand(0)));
8364 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8365 /*IsSigned=*/ true, /*IsReplace=*/ false);
8366 SDValue FIST = Vals.first, StackSlot = Vals.second;
8367 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8368 if (FIST.getNode() == 0) return Op;
8370 if (StackSlot.getNode())
8372 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8373 FIST, StackSlot, MachinePointerInfo(),
8374 false, false, false, 0);
8376 // The node is the result.
8380 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8381 SelectionDAG &DAG) const {
8382 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8383 /*IsSigned=*/ false, /*IsReplace=*/ false);
8384 SDValue FIST = Vals.first, StackSlot = Vals.second;
8385 assert(FIST.getNode() && "Unexpected failure");
8387 if (StackSlot.getNode())
8389 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8390 FIST, StackSlot, MachinePointerInfo(),
8391 false, false, false, 0);
8393 // The node is the result.
8397 SDValue X86TargetLowering::lowerFP_EXTEND(SDValue Op,
8398 SelectionDAG &DAG) const {
8399 DebugLoc DL = Op.getDebugLoc();
8400 EVT VT = Op.getValueType();
8401 SDValue In = Op.getOperand(0);
8402 EVT SVT = In.getValueType();
8404 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
8406 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
8407 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8408 In, DAG.getUNDEF(SVT)));
8411 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
8412 LLVMContext *Context = DAG.getContext();
8413 DebugLoc dl = Op.getDebugLoc();
8414 EVT VT = Op.getValueType();
8416 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8417 if (VT.isVector()) {
8418 EltVT = VT.getVectorElementType();
8419 NumElts = VT.getVectorNumElements();
8422 if (EltVT == MVT::f64)
8423 C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
8425 C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
8426 C = ConstantVector::getSplat(NumElts, C);
8427 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8428 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8429 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8430 MachinePointerInfo::getConstantPool(),
8431 false, false, false, Alignment);
8432 if (VT.isVector()) {
8433 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8434 return DAG.getNode(ISD::BITCAST, dl, VT,
8435 DAG.getNode(ISD::AND, dl, ANDVT,
8436 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8438 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8440 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8443 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8444 LLVMContext *Context = DAG.getContext();
8445 DebugLoc dl = Op.getDebugLoc();
8446 EVT VT = Op.getValueType();
8448 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8449 if (VT.isVector()) {
8450 EltVT = VT.getVectorElementType();
8451 NumElts = VT.getVectorNumElements();
8454 if (EltVT == MVT::f64)
8455 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8457 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8458 C = ConstantVector::getSplat(NumElts, C);
8459 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8460 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8461 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8462 MachinePointerInfo::getConstantPool(),
8463 false, false, false, Alignment);
8464 if (VT.isVector()) {
8465 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8466 return DAG.getNode(ISD::BITCAST, dl, VT,
8467 DAG.getNode(ISD::XOR, dl, XORVT,
8468 DAG.getNode(ISD::BITCAST, dl, XORVT,
8470 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8473 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8476 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8477 LLVMContext *Context = DAG.getContext();
8478 SDValue Op0 = Op.getOperand(0);
8479 SDValue Op1 = Op.getOperand(1);
8480 DebugLoc dl = Op.getDebugLoc();
8481 EVT VT = Op.getValueType();
8482 EVT SrcVT = Op1.getValueType();
8484 // If second operand is smaller, extend it first.
8485 if (SrcVT.bitsLT(VT)) {
8486 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8489 // And if it is bigger, shrink it first.
8490 if (SrcVT.bitsGT(VT)) {
8491 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8495 // At this point the operands and the result should have the same
8496 // type, and that won't be f80 since that is not custom lowered.
8498 // First get the sign bit of second operand.
8499 SmallVector<Constant*,4> CV;
8500 if (SrcVT == MVT::f64) {
8501 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8502 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8504 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8505 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8506 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8507 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8509 Constant *C = ConstantVector::get(CV);
8510 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8511 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8512 MachinePointerInfo::getConstantPool(),
8513 false, false, false, 16);
8514 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8516 // Shift sign bit right or left if the two operands have different types.
8517 if (SrcVT.bitsGT(VT)) {
8518 // Op0 is MVT::f32, Op1 is MVT::f64.
8519 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8520 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8521 DAG.getConstant(32, MVT::i32));
8522 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8523 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8524 DAG.getIntPtrConstant(0));
8527 // Clear first operand sign bit.
8529 if (VT == MVT::f64) {
8530 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8531 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8533 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8534 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8535 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8536 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8538 C = ConstantVector::get(CV);
8539 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8540 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8541 MachinePointerInfo::getConstantPool(),
8542 false, false, false, 16);
8543 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8545 // Or the value with the sign bit.
8546 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8549 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
8550 SDValue N0 = Op.getOperand(0);
8551 DebugLoc dl = Op.getDebugLoc();
8552 EVT VT = Op.getValueType();
8554 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8555 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8556 DAG.getConstant(1, VT));
8557 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8560 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
8562 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const {
8563 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8565 if (!Subtarget->hasSSE41())
8568 if (!Op->hasOneUse())
8571 SDNode *N = Op.getNode();
8572 DebugLoc DL = N->getDebugLoc();
8574 SmallVector<SDValue, 8> Opnds;
8575 DenseMap<SDValue, unsigned> VecInMap;
8576 EVT VT = MVT::Other;
8578 // Recognize a special case where a vector is casted into wide integer to
8580 Opnds.push_back(N->getOperand(0));
8581 Opnds.push_back(N->getOperand(1));
8583 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
8584 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot;
8585 // BFS traverse all OR'd operands.
8586 if (I->getOpcode() == ISD::OR) {
8587 Opnds.push_back(I->getOperand(0));
8588 Opnds.push_back(I->getOperand(1));
8589 // Re-evaluate the number of nodes to be traversed.
8590 e += 2; // 2 more nodes (LHS and RHS) are pushed.
8594 // Quit if a non-EXTRACT_VECTOR_ELT
8595 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8598 // Quit if without a constant index.
8599 SDValue Idx = I->getOperand(1);
8600 if (!isa<ConstantSDNode>(Idx))
8603 SDValue ExtractedFromVec = I->getOperand(0);
8604 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
8605 if (M == VecInMap.end()) {
8606 VT = ExtractedFromVec.getValueType();
8607 // Quit if not 128/256-bit vector.
8608 if (!VT.is128BitVector() && !VT.is256BitVector())
8610 // Quit if not the same type.
8611 if (VecInMap.begin() != VecInMap.end() &&
8612 VT != VecInMap.begin()->first.getValueType())
8614 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
8616 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
8619 assert((VT.is128BitVector() || VT.is256BitVector()) &&
8620 "Not extracted from 128-/256-bit vector.");
8622 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
8623 SmallVector<SDValue, 8> VecIns;
8625 for (DenseMap<SDValue, unsigned>::const_iterator
8626 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
8627 // Quit if not all elements are used.
8628 if (I->second != FullMask)
8630 VecIns.push_back(I->first);
8633 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8635 // Cast all vectors into TestVT for PTEST.
8636 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
8637 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
8639 // If more than one full vectors are evaluated, OR them first before PTEST.
8640 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
8641 // Each iteration will OR 2 nodes and append the result until there is only
8642 // 1 node left, i.e. the final OR'd value of all vectors.
8643 SDValue LHS = VecIns[Slot];
8644 SDValue RHS = VecIns[Slot + 1];
8645 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
8648 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
8649 VecIns.back(), VecIns.back());
8652 /// Emit nodes that will be selected as "test Op0,Op0", or something
8654 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8655 SelectionDAG &DAG) const {
8656 DebugLoc dl = Op.getDebugLoc();
8658 // CF and OF aren't always set the way we want. Determine which
8659 // of these we need.
8660 bool NeedCF = false;
8661 bool NeedOF = false;
8664 case X86::COND_A: case X86::COND_AE:
8665 case X86::COND_B: case X86::COND_BE:
8668 case X86::COND_G: case X86::COND_GE:
8669 case X86::COND_L: case X86::COND_LE:
8670 case X86::COND_O: case X86::COND_NO:
8675 // See if we can use the EFLAGS value from the operand instead of
8676 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8677 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8678 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8679 // Emit a CMP with 0, which is the TEST pattern.
8680 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8681 DAG.getConstant(0, Op.getValueType()));
8683 unsigned Opcode = 0;
8684 unsigned NumOperands = 0;
8686 // Truncate operations may prevent the merge of the SETCC instruction
8687 // and the arithmetic intruction before it. Attempt to truncate the operands
8688 // of the arithmetic instruction and use a reduced bit-width instruction.
8689 bool NeedTruncation = false;
8690 SDValue ArithOp = Op;
8691 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8692 SDValue Arith = Op->getOperand(0);
8693 // Both the trunc and the arithmetic op need to have one user each.
8694 if (Arith->hasOneUse())
8695 switch (Arith.getOpcode()) {
8702 NeedTruncation = true;
8708 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
8709 // which may be the result of a CAST. We use the variable 'Op', which is the
8710 // non-casted variable when we check for possible users.
8711 switch (ArithOp.getOpcode()) {
8713 // Due to an isel shortcoming, be conservative if this add is likely to be
8714 // selected as part of a load-modify-store instruction. When the root node
8715 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8716 // uses of other nodes in the match, such as the ADD in this case. This
8717 // leads to the ADD being left around and reselected, with the result being
8718 // two adds in the output. Alas, even if none our users are stores, that
8719 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8720 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8721 // climbing the DAG back to the root, and it doesn't seem to be worth the
8723 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8724 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8725 if (UI->getOpcode() != ISD::CopyToReg &&
8726 UI->getOpcode() != ISD::SETCC &&
8727 UI->getOpcode() != ISD::STORE)
8730 if (ConstantSDNode *C =
8731 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
8732 // An add of one will be selected as an INC.
8733 if (C->getAPIntValue() == 1) {
8734 Opcode = X86ISD::INC;
8739 // An add of negative one (subtract of one) will be selected as a DEC.
8740 if (C->getAPIntValue().isAllOnesValue()) {
8741 Opcode = X86ISD::DEC;
8747 // Otherwise use a regular EFLAGS-setting add.
8748 Opcode = X86ISD::ADD;
8752 // If the primary and result isn't used, don't bother using X86ISD::AND,
8753 // because a TEST instruction will be better.
8754 bool NonFlagUse = false;
8755 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8756 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8758 unsigned UOpNo = UI.getOperandNo();
8759 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8760 // Look pass truncate.
8761 UOpNo = User->use_begin().getOperandNo();
8762 User = *User->use_begin();
8765 if (User->getOpcode() != ISD::BRCOND &&
8766 User->getOpcode() != ISD::SETCC &&
8767 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
8780 // Due to the ISEL shortcoming noted above, be conservative if this op is
8781 // likely to be selected as part of a load-modify-store instruction.
8782 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8783 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8784 if (UI->getOpcode() == ISD::STORE)
8787 // Otherwise use a regular EFLAGS-setting instruction.
8788 switch (ArithOp.getOpcode()) {
8789 default: llvm_unreachable("unexpected operator!");
8790 case ISD::SUB: Opcode = X86ISD::SUB; break;
8791 case ISD::XOR: Opcode = X86ISD::XOR; break;
8792 case ISD::AND: Opcode = X86ISD::AND; break;
8794 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
8795 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
8796 if (EFLAGS.getNode())
8799 Opcode = X86ISD::OR;
8813 return SDValue(Op.getNode(), 1);
8819 // If we found that truncation is beneficial, perform the truncation and
8821 if (NeedTruncation) {
8822 EVT VT = Op.getValueType();
8823 SDValue WideVal = Op->getOperand(0);
8824 EVT WideVT = WideVal.getValueType();
8825 unsigned ConvertedOp = 0;
8826 // Use a target machine opcode to prevent further DAGCombine
8827 // optimizations that may separate the arithmetic operations
8828 // from the setcc node.
8829 switch (WideVal.getOpcode()) {
8831 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
8832 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
8833 case ISD::AND: ConvertedOp = X86ISD::AND; break;
8834 case ISD::OR: ConvertedOp = X86ISD::OR; break;
8835 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
8839 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8840 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
8841 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
8842 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
8843 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
8849 // Emit a CMP with 0, which is the TEST pattern.
8850 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8851 DAG.getConstant(0, Op.getValueType()));
8853 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8854 SmallVector<SDValue, 4> Ops;
8855 for (unsigned i = 0; i != NumOperands; ++i)
8856 Ops.push_back(Op.getOperand(i));
8858 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8859 DAG.ReplaceAllUsesWith(Op, New);
8860 return SDValue(New.getNode(), 1);
8863 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8865 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8866 SelectionDAG &DAG) const {
8867 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8868 if (C->getAPIntValue() == 0)
8869 return EmitTest(Op0, X86CC, DAG);
8871 DebugLoc dl = Op0.getDebugLoc();
8872 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
8873 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
8874 // Use SUB instead of CMP to enable CSE between SUB and CMP.
8875 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
8876 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
8878 return SDValue(Sub.getNode(), 1);
8880 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8883 /// Convert a comparison if required by the subtarget.
8884 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8885 SelectionDAG &DAG) const {
8886 // If the subtarget does not support the FUCOMI instruction, floating-point
8887 // comparisons have to be converted.
8888 if (Subtarget->hasCMov() ||
8889 Cmp.getOpcode() != X86ISD::CMP ||
8890 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8891 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8894 // The instruction selector will select an FUCOM instruction instead of
8895 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8896 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8897 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8898 DebugLoc dl = Cmp.getDebugLoc();
8899 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8900 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8901 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8902 DAG.getConstant(8, MVT::i8));
8903 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8904 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8907 static bool isAllOnes(SDValue V) {
8908 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8909 return C && C->isAllOnesValue();
8912 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8913 /// if it's possible.
8914 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8915 DebugLoc dl, SelectionDAG &DAG) const {
8916 SDValue Op0 = And.getOperand(0);
8917 SDValue Op1 = And.getOperand(1);
8918 if (Op0.getOpcode() == ISD::TRUNCATE)
8919 Op0 = Op0.getOperand(0);
8920 if (Op1.getOpcode() == ISD::TRUNCATE)
8921 Op1 = Op1.getOperand(0);
8924 if (Op1.getOpcode() == ISD::SHL)
8925 std::swap(Op0, Op1);
8926 if (Op0.getOpcode() == ISD::SHL) {
8927 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8928 if (And00C->getZExtValue() == 1) {
8929 // If we looked past a truncate, check that it's only truncating away
8931 unsigned BitWidth = Op0.getValueSizeInBits();
8932 unsigned AndBitWidth = And.getValueSizeInBits();
8933 if (BitWidth > AndBitWidth) {
8935 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8936 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8940 RHS = Op0.getOperand(1);
8942 } else if (Op1.getOpcode() == ISD::Constant) {
8943 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8944 uint64_t AndRHSVal = AndRHS->getZExtValue();
8945 SDValue AndLHS = Op0;
8947 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8948 LHS = AndLHS.getOperand(0);
8949 RHS = AndLHS.getOperand(1);
8952 // Use BT if the immediate can't be encoded in a TEST instruction.
8953 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8955 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8959 if (LHS.getNode()) {
8960 // If the LHS is of the form (x ^ -1) then replace the LHS with x and flip
8961 // the condition code later.
8962 bool Invert = false;
8963 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
8965 LHS = LHS.getOperand(0);
8968 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8969 // instruction. Since the shift amount is in-range-or-undefined, we know
8970 // that doing a bittest on the i32 value is ok. We extend to i32 because
8971 // the encoding for the i16 version is larger than the i32 version.
8972 // Also promote i16 to i32 for performance / code size reason.
8973 if (LHS.getValueType() == MVT::i8 ||
8974 LHS.getValueType() == MVT::i16)
8975 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8977 // If the operand types disagree, extend the shift amount to match. Since
8978 // BT ignores high bits (like shifts) we can use anyextend.
8979 if (LHS.getValueType() != RHS.getValueType())
8980 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8982 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8983 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8984 // Flip the condition if the LHS was a not instruction
8986 Cond = X86::GetOppositeBranchCondition(Cond);
8987 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8988 DAG.getConstant(Cond, MVT::i8), BT);
8994 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8996 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8998 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8999 SDValue Op0 = Op.getOperand(0);
9000 SDValue Op1 = Op.getOperand(1);
9001 DebugLoc dl = Op.getDebugLoc();
9002 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9004 // Optimize to BT if possible.
9005 // Lower (X & (1 << N)) == 0 to BT(X, N).
9006 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9007 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9008 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9009 Op1.getOpcode() == ISD::Constant &&
9010 cast<ConstantSDNode>(Op1)->isNullValue() &&
9011 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9012 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9013 if (NewSetCC.getNode())
9017 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9019 if (Op1.getOpcode() == ISD::Constant &&
9020 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9021 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9022 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9024 // If the input is a setcc, then reuse the input setcc or use a new one with
9025 // the inverted condition.
9026 if (Op0.getOpcode() == X86ISD::SETCC) {
9027 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9028 bool Invert = (CC == ISD::SETNE) ^
9029 cast<ConstantSDNode>(Op1)->isNullValue();
9030 if (!Invert) return Op0;
9032 CCode = X86::GetOppositeBranchCondition(CCode);
9033 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9034 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9038 bool isFP = Op1.getValueType().isFloatingPoint();
9039 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9040 if (X86CC == X86::COND_INVALID)
9043 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9044 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9045 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9046 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9049 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9050 // ones, and then concatenate the result back.
9051 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9052 EVT VT = Op.getValueType();
9054 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9055 "Unsupported value type for operation");
9057 unsigned NumElems = VT.getVectorNumElements();
9058 DebugLoc dl = Op.getDebugLoc();
9059 SDValue CC = Op.getOperand(2);
9061 // Extract the LHS vectors
9062 SDValue LHS = Op.getOperand(0);
9063 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9064 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9066 // Extract the RHS vectors
9067 SDValue RHS = Op.getOperand(1);
9068 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9069 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9071 // Issue the operation on the smaller types and concatenate the result back
9072 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9073 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9074 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9075 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9076 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9080 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
9082 SDValue Op0 = Op.getOperand(0);
9083 SDValue Op1 = Op.getOperand(1);
9084 SDValue CC = Op.getOperand(2);
9085 EVT VT = Op.getValueType();
9086 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9087 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
9088 DebugLoc dl = Op.getDebugLoc();
9092 EVT EltVT = Op0.getValueType().getVectorElementType();
9093 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9099 // SSE Condition code mapping:
9108 switch (SetCCOpcode) {
9109 default: llvm_unreachable("Unexpected SETCC condition");
9111 case ISD::SETEQ: SSECC = 0; break;
9113 case ISD::SETGT: Swap = true; // Fallthrough
9115 case ISD::SETOLT: SSECC = 1; break;
9117 case ISD::SETGE: Swap = true; // Fallthrough
9119 case ISD::SETOLE: SSECC = 2; break;
9120 case ISD::SETUO: SSECC = 3; break;
9122 case ISD::SETNE: SSECC = 4; break;
9123 case ISD::SETULE: Swap = true; // Fallthrough
9124 case ISD::SETUGE: SSECC = 5; break;
9125 case ISD::SETULT: Swap = true; // Fallthrough
9126 case ISD::SETUGT: SSECC = 6; break;
9127 case ISD::SETO: SSECC = 7; break;
9129 case ISD::SETONE: SSECC = 8; break;
9132 std::swap(Op0, Op1);
9134 // In the two special cases we can't handle, emit two comparisons.
9137 unsigned CombineOpc;
9138 if (SetCCOpcode == ISD::SETUEQ) {
9139 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9141 assert(SetCCOpcode == ISD::SETONE);
9142 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9145 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9146 DAG.getConstant(CC0, MVT::i8));
9147 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9148 DAG.getConstant(CC1, MVT::i8));
9149 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9151 // Handle all other FP comparisons here.
9152 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9153 DAG.getConstant(SSECC, MVT::i8));
9156 // Break 256-bit integer vector compare into smaller ones.
9157 if (VT.is256BitVector() && !Subtarget->hasInt256())
9158 return Lower256IntVSETCC(Op, DAG);
9160 // We are handling one of the integer comparisons here. Since SSE only has
9161 // GT and EQ comparisons for integer, swapping operands and multiple
9162 // operations may be required for some comparisons.
9164 bool Swap = false, Invert = false, FlipSigns = false;
9166 switch (SetCCOpcode) {
9167 default: llvm_unreachable("Unexpected SETCC condition");
9168 case ISD::SETNE: Invert = true;
9169 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9170 case ISD::SETLT: Swap = true;
9171 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9172 case ISD::SETGE: Swap = true;
9173 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9174 case ISD::SETULT: Swap = true;
9175 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9176 case ISD::SETUGE: Swap = true;
9177 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9180 std::swap(Op0, Op1);
9182 // Check that the operation in question is available (most are plain SSE2,
9183 // but PCMPGTQ and PCMPEQQ have different requirements).
9184 if (VT == MVT::v2i64) {
9185 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42())
9187 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41())
9191 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9192 // bits of the inputs before performing those operations.
9194 EVT EltVT = VT.getVectorElementType();
9195 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
9197 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
9198 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9200 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9201 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
9204 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9206 // If the logical-not of the result is required, perform that now.
9208 Result = DAG.getNOT(dl, Result, VT);
9213 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9214 static bool isX86LogicalCmp(SDValue Op) {
9215 unsigned Opc = Op.getNode()->getOpcode();
9216 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9217 Opc == X86ISD::SAHF)
9219 if (Op.getResNo() == 1 &&
9220 (Opc == X86ISD::ADD ||
9221 Opc == X86ISD::SUB ||
9222 Opc == X86ISD::ADC ||
9223 Opc == X86ISD::SBB ||
9224 Opc == X86ISD::SMUL ||
9225 Opc == X86ISD::UMUL ||
9226 Opc == X86ISD::INC ||
9227 Opc == X86ISD::DEC ||
9228 Opc == X86ISD::OR ||
9229 Opc == X86ISD::XOR ||
9230 Opc == X86ISD::AND))
9233 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
9239 static bool isZero(SDValue V) {
9240 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9241 return C && C->isNullValue();
9244 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
9245 if (V.getOpcode() != ISD::TRUNCATE)
9248 SDValue VOp0 = V.getOperand(0);
9249 unsigned InBits = VOp0.getValueSizeInBits();
9250 unsigned Bits = V.getValueSizeInBits();
9251 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
9254 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
9255 bool addTest = true;
9256 SDValue Cond = Op.getOperand(0);
9257 SDValue Op1 = Op.getOperand(1);
9258 SDValue Op2 = Op.getOperand(2);
9259 DebugLoc DL = Op.getDebugLoc();
9262 if (Cond.getOpcode() == ISD::SETCC) {
9263 SDValue NewCond = LowerSETCC(Cond, DAG);
9264 if (NewCond.getNode())
9268 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
9269 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
9270 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
9271 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
9272 if (Cond.getOpcode() == X86ISD::SETCC &&
9273 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9274 isZero(Cond.getOperand(1).getOperand(1))) {
9275 SDValue Cmp = Cond.getOperand(1);
9277 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
9279 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
9280 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
9281 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
9283 SDValue CmpOp0 = Cmp.getOperand(0);
9284 // Apply further optimizations for special cases
9285 // (select (x != 0), -1, 0) -> neg & sbb
9286 // (select (x == 0), 0, -1) -> neg & sbb
9287 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
9288 if (YC->isNullValue() &&
9289 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
9290 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
9291 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
9292 DAG.getConstant(0, CmpOp0.getValueType()),
9294 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9295 DAG.getConstant(X86::COND_B, MVT::i8),
9296 SDValue(Neg.getNode(), 1));
9300 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
9301 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
9302 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9304 SDValue Res = // Res = 0 or -1.
9305 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9306 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
9308 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
9309 Res = DAG.getNOT(DL, Res, Res.getValueType());
9311 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
9312 if (N2C == 0 || !N2C->isNullValue())
9313 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9318 // Look past (and (setcc_carry (cmp ...)), 1).
9319 if (Cond.getOpcode() == ISD::AND &&
9320 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9321 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9322 if (C && C->getAPIntValue() == 1)
9323 Cond = Cond.getOperand(0);
9326 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9327 // setting operand in place of the X86ISD::SETCC.
9328 unsigned CondOpcode = Cond.getOpcode();
9329 if (CondOpcode == X86ISD::SETCC ||
9330 CondOpcode == X86ISD::SETCC_CARRY) {
9331 CC = Cond.getOperand(0);
9333 SDValue Cmp = Cond.getOperand(1);
9334 unsigned Opc = Cmp.getOpcode();
9335 EVT VT = Op.getValueType();
9337 bool IllegalFPCMov = false;
9338 if (VT.isFloatingPoint() && !VT.isVector() &&
9339 !isScalarFPTypeInSSEReg(VT)) // FPStack?
9340 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9342 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
9343 Opc == X86ISD::BT) { // FIXME
9347 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9348 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9349 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9350 Cond.getOperand(0).getValueType() != MVT::i8)) {
9351 SDValue LHS = Cond.getOperand(0);
9352 SDValue RHS = Cond.getOperand(1);
9356 switch (CondOpcode) {
9357 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9358 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9359 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9360 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9361 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9362 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9363 default: llvm_unreachable("unexpected overflowing operator");
9365 if (CondOpcode == ISD::UMULO)
9366 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9369 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9371 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
9373 if (CondOpcode == ISD::UMULO)
9374 Cond = X86Op.getValue(2);
9376 Cond = X86Op.getValue(1);
9378 CC = DAG.getConstant(X86Cond, MVT::i8);
9383 // Look pass the truncate if the high bits are known zero.
9384 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9385 Cond = Cond.getOperand(0);
9387 // We know the result of AND is compared against zero. Try to match
9389 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9390 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9391 if (NewSetCC.getNode()) {
9392 CC = NewSetCC.getOperand(0);
9393 Cond = NewSetCC.getOperand(1);
9400 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9401 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9404 // a < b ? -1 : 0 -> RES = ~setcc_carry
9405 // a < b ? 0 : -1 -> RES = setcc_carry
9406 // a >= b ? -1 : 0 -> RES = setcc_carry
9407 // a >= b ? 0 : -1 -> RES = ~setcc_carry
9408 if (Cond.getOpcode() == X86ISD::SUB) {
9409 Cond = ConvertCmpIfNecessary(Cond, DAG);
9410 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9412 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
9413 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9414 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9415 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9416 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9417 return DAG.getNOT(DL, Res, Res.getValueType());
9422 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
9423 // widen the cmov and push the truncate through. This avoids introducing a new
9424 // branch during isel and doesn't add any extensions.
9425 if (Op.getValueType() == MVT::i8 &&
9426 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9427 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
9428 if (T1.getValueType() == T2.getValueType() &&
9429 // Blacklist CopyFromReg to avoid partial register stalls.
9430 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9431 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
9432 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
9433 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
9437 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9438 // condition is true.
9439 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
9440 SDValue Ops[] = { Op2, Op1, CC, Cond };
9441 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9444 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9445 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9446 // from the AND / OR.
9447 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9448 Opc = Op.getOpcode();
9449 if (Opc != ISD::OR && Opc != ISD::AND)
9451 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9452 Op.getOperand(0).hasOneUse() &&
9453 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9454 Op.getOperand(1).hasOneUse());
9457 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9458 // 1 and that the SETCC node has a single use.
9459 static bool isXor1OfSetCC(SDValue Op) {
9460 if (Op.getOpcode() != ISD::XOR)
9462 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9463 if (N1C && N1C->getAPIntValue() == 1) {
9464 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9465 Op.getOperand(0).hasOneUse();
9470 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9471 bool addTest = true;
9472 SDValue Chain = Op.getOperand(0);
9473 SDValue Cond = Op.getOperand(1);
9474 SDValue Dest = Op.getOperand(2);
9475 DebugLoc dl = Op.getDebugLoc();
9477 bool Inverted = false;
9479 if (Cond.getOpcode() == ISD::SETCC) {
9480 // Check for setcc([su]{add,sub,mul}o == 0).
9481 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9482 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9483 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9484 Cond.getOperand(0).getResNo() == 1 &&
9485 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9486 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9487 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9488 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9489 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9490 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9492 Cond = Cond.getOperand(0);
9494 SDValue NewCond = LowerSETCC(Cond, DAG);
9495 if (NewCond.getNode())
9500 // FIXME: LowerXALUO doesn't handle these!!
9501 else if (Cond.getOpcode() == X86ISD::ADD ||
9502 Cond.getOpcode() == X86ISD::SUB ||
9503 Cond.getOpcode() == X86ISD::SMUL ||
9504 Cond.getOpcode() == X86ISD::UMUL)
9505 Cond = LowerXALUO(Cond, DAG);
9508 // Look pass (and (setcc_carry (cmp ...)), 1).
9509 if (Cond.getOpcode() == ISD::AND &&
9510 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9511 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9512 if (C && C->getAPIntValue() == 1)
9513 Cond = Cond.getOperand(0);
9516 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9517 // setting operand in place of the X86ISD::SETCC.
9518 unsigned CondOpcode = Cond.getOpcode();
9519 if (CondOpcode == X86ISD::SETCC ||
9520 CondOpcode == X86ISD::SETCC_CARRY) {
9521 CC = Cond.getOperand(0);
9523 SDValue Cmp = Cond.getOperand(1);
9524 unsigned Opc = Cmp.getOpcode();
9525 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9526 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9530 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9534 // These can only come from an arithmetic instruction with overflow,
9535 // e.g. SADDO, UADDO.
9536 Cond = Cond.getNode()->getOperand(1);
9542 CondOpcode = Cond.getOpcode();
9543 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9544 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9545 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9546 Cond.getOperand(0).getValueType() != MVT::i8)) {
9547 SDValue LHS = Cond.getOperand(0);
9548 SDValue RHS = Cond.getOperand(1);
9552 switch (CondOpcode) {
9553 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9554 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9555 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9556 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9557 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9558 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9559 default: llvm_unreachable("unexpected overflowing operator");
9562 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9563 if (CondOpcode == ISD::UMULO)
9564 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9567 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9569 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9571 if (CondOpcode == ISD::UMULO)
9572 Cond = X86Op.getValue(2);
9574 Cond = X86Op.getValue(1);
9576 CC = DAG.getConstant(X86Cond, MVT::i8);
9580 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9581 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9582 if (CondOpc == ISD::OR) {
9583 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9584 // two branches instead of an explicit OR instruction with a
9586 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9587 isX86LogicalCmp(Cmp)) {
9588 CC = Cond.getOperand(0).getOperand(0);
9589 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9590 Chain, Dest, CC, Cmp);
9591 CC = Cond.getOperand(1).getOperand(0);
9595 } else { // ISD::AND
9596 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9597 // two branches instead of an explicit AND instruction with a
9598 // separate test. However, we only do this if this block doesn't
9599 // have a fall-through edge, because this requires an explicit
9600 // jmp when the condition is false.
9601 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9602 isX86LogicalCmp(Cmp) &&
9603 Op.getNode()->hasOneUse()) {
9604 X86::CondCode CCode =
9605 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9606 CCode = X86::GetOppositeBranchCondition(CCode);
9607 CC = DAG.getConstant(CCode, MVT::i8);
9608 SDNode *User = *Op.getNode()->use_begin();
9609 // Look for an unconditional branch following this conditional branch.
9610 // We need this because we need to reverse the successors in order
9611 // to implement FCMP_OEQ.
9612 if (User->getOpcode() == ISD::BR) {
9613 SDValue FalseBB = User->getOperand(1);
9615 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9616 assert(NewBR == User);
9620 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9621 Chain, Dest, CC, Cmp);
9622 X86::CondCode CCode =
9623 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9624 CCode = X86::GetOppositeBranchCondition(CCode);
9625 CC = DAG.getConstant(CCode, MVT::i8);
9631 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9632 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9633 // It should be transformed during dag combiner except when the condition
9634 // is set by a arithmetics with overflow node.
9635 X86::CondCode CCode =
9636 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9637 CCode = X86::GetOppositeBranchCondition(CCode);
9638 CC = DAG.getConstant(CCode, MVT::i8);
9639 Cond = Cond.getOperand(0).getOperand(1);
9641 } else if (Cond.getOpcode() == ISD::SETCC &&
9642 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9643 // For FCMP_OEQ, we can emit
9644 // two branches instead of an explicit AND instruction with a
9645 // separate test. However, we only do this if this block doesn't
9646 // have a fall-through edge, because this requires an explicit
9647 // jmp when the condition is false.
9648 if (Op.getNode()->hasOneUse()) {
9649 SDNode *User = *Op.getNode()->use_begin();
9650 // Look for an unconditional branch following this conditional branch.
9651 // We need this because we need to reverse the successors in order
9652 // to implement FCMP_OEQ.
9653 if (User->getOpcode() == ISD::BR) {
9654 SDValue FalseBB = User->getOperand(1);
9656 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9657 assert(NewBR == User);
9661 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9662 Cond.getOperand(0), Cond.getOperand(1));
9663 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9664 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9665 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9666 Chain, Dest, CC, Cmp);
9667 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9672 } else if (Cond.getOpcode() == ISD::SETCC &&
9673 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9674 // For FCMP_UNE, we can emit
9675 // two branches instead of an explicit AND instruction with a
9676 // separate test. However, we only do this if this block doesn't
9677 // have a fall-through edge, because this requires an explicit
9678 // jmp when the condition is false.
9679 if (Op.getNode()->hasOneUse()) {
9680 SDNode *User = *Op.getNode()->use_begin();
9681 // Look for an unconditional branch following this conditional branch.
9682 // We need this because we need to reverse the successors in order
9683 // to implement FCMP_UNE.
9684 if (User->getOpcode() == ISD::BR) {
9685 SDValue FalseBB = User->getOperand(1);
9687 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9688 assert(NewBR == User);
9691 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9692 Cond.getOperand(0), Cond.getOperand(1));
9693 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9694 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9695 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9696 Chain, Dest, CC, Cmp);
9697 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9707 // Look pass the truncate if the high bits are known zero.
9708 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9709 Cond = Cond.getOperand(0);
9711 // We know the result of AND is compared against zero. Try to match
9713 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9714 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9715 if (NewSetCC.getNode()) {
9716 CC = NewSetCC.getOperand(0);
9717 Cond = NewSetCC.getOperand(1);
9724 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9725 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9727 Cond = ConvertCmpIfNecessary(Cond, DAG);
9728 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9729 Chain, Dest, CC, Cond);
9733 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9734 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9735 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9736 // that the guard pages used by the OS virtual memory manager are allocated in
9737 // correct sequence.
9739 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9740 SelectionDAG &DAG) const {
9741 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9742 getTargetMachine().Options.EnableSegmentedStacks) &&
9743 "This should be used only on Windows targets or when segmented stacks "
9745 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9746 DebugLoc dl = Op.getDebugLoc();
9749 SDValue Chain = Op.getOperand(0);
9750 SDValue Size = Op.getOperand(1);
9751 // FIXME: Ensure alignment here
9753 bool Is64Bit = Subtarget->is64Bit();
9754 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9756 if (getTargetMachine().Options.EnableSegmentedStacks) {
9757 MachineFunction &MF = DAG.getMachineFunction();
9758 MachineRegisterInfo &MRI = MF.getRegInfo();
9761 // The 64 bit implementation of segmented stacks needs to clobber both r10
9762 // r11. This makes it impossible to use it along with nested parameters.
9763 const Function *F = MF.getFunction();
9765 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9767 if (I->hasNestAttr())
9768 report_fatal_error("Cannot use segmented stacks with functions that "
9769 "have nested arguments.");
9772 const TargetRegisterClass *AddrRegClass =
9773 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9774 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9775 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9776 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9777 DAG.getRegister(Vreg, SPTy));
9778 SDValue Ops1[2] = { Value, Chain };
9779 return DAG.getMergeValues(Ops1, 2, dl);
9782 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9784 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9785 Flag = Chain.getValue(1);
9786 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9788 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9789 Flag = Chain.getValue(1);
9791 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
9794 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9795 return DAG.getMergeValues(Ops1, 2, dl);
9799 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9800 MachineFunction &MF = DAG.getMachineFunction();
9801 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9803 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9804 DebugLoc DL = Op.getDebugLoc();
9806 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9807 // vastart just stores the address of the VarArgsFrameIndex slot into the
9808 // memory location argument.
9809 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9811 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9812 MachinePointerInfo(SV), false, false, 0);
9816 // gp_offset (0 - 6 * 8)
9817 // fp_offset (48 - 48 + 8 * 16)
9818 // overflow_arg_area (point to parameters coming in memory).
9820 SmallVector<SDValue, 8> MemOps;
9821 SDValue FIN = Op.getOperand(1);
9823 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9824 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9826 FIN, MachinePointerInfo(SV), false, false, 0);
9827 MemOps.push_back(Store);
9830 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9831 FIN, DAG.getIntPtrConstant(4));
9832 Store = DAG.getStore(Op.getOperand(0), DL,
9833 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9835 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9836 MemOps.push_back(Store);
9838 // Store ptr to overflow_arg_area
9839 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9840 FIN, DAG.getIntPtrConstant(4));
9841 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9843 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9844 MachinePointerInfo(SV, 8),
9846 MemOps.push_back(Store);
9848 // Store ptr to reg_save_area.
9849 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9850 FIN, DAG.getIntPtrConstant(8));
9851 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9853 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9854 MachinePointerInfo(SV, 16), false, false, 0);
9855 MemOps.push_back(Store);
9856 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9857 &MemOps[0], MemOps.size());
9860 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9861 assert(Subtarget->is64Bit() &&
9862 "LowerVAARG only handles 64-bit va_arg!");
9863 assert((Subtarget->isTargetLinux() ||
9864 Subtarget->isTargetDarwin()) &&
9865 "Unhandled target in LowerVAARG");
9866 assert(Op.getNode()->getNumOperands() == 4);
9867 SDValue Chain = Op.getOperand(0);
9868 SDValue SrcPtr = Op.getOperand(1);
9869 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9870 unsigned Align = Op.getConstantOperandVal(3);
9871 DebugLoc dl = Op.getDebugLoc();
9873 EVT ArgVT = Op.getNode()->getValueType(0);
9874 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9875 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
9878 // Decide which area this value should be read from.
9879 // TODO: Implement the AMD64 ABI in its entirety. This simple
9880 // selection mechanism works only for the basic types.
9881 if (ArgVT == MVT::f80) {
9882 llvm_unreachable("va_arg for f80 not yet implemented");
9883 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9884 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9885 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9886 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9888 llvm_unreachable("Unhandled argument type in LowerVAARG");
9892 // Sanity Check: Make sure using fp_offset makes sense.
9893 assert(!getTargetMachine().Options.UseSoftFloat &&
9894 !(DAG.getMachineFunction()
9895 .getFunction()->getFnAttributes()
9896 .hasAttribute(Attributes::NoImplicitFloat)) &&
9897 Subtarget->hasSSE1());
9900 // Insert VAARG_64 node into the DAG
9901 // VAARG_64 returns two values: Variable Argument Address, Chain
9902 SmallVector<SDValue, 11> InstOps;
9903 InstOps.push_back(Chain);
9904 InstOps.push_back(SrcPtr);
9905 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9906 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9907 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9908 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9909 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9910 VTs, &InstOps[0], InstOps.size(),
9912 MachinePointerInfo(SV),
9917 Chain = VAARG.getValue(1);
9919 // Load the next argument and return it
9920 return DAG.getLoad(ArgVT, dl,
9923 MachinePointerInfo(),
9924 false, false, false, 0);
9927 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
9928 SelectionDAG &DAG) {
9929 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9930 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9931 SDValue Chain = Op.getOperand(0);
9932 SDValue DstPtr = Op.getOperand(1);
9933 SDValue SrcPtr = Op.getOperand(2);
9934 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9935 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9936 DebugLoc DL = Op.getDebugLoc();
9938 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9939 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9941 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9944 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9945 // may or may not be a constant. Takes immediate version of shift as input.
9946 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9947 SDValue SrcOp, SDValue ShAmt,
9948 SelectionDAG &DAG) {
9949 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9951 if (isa<ConstantSDNode>(ShAmt)) {
9952 // Constant may be a TargetConstant. Use a regular constant.
9953 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
9955 default: llvm_unreachable("Unknown target vector shift node");
9959 return DAG.getNode(Opc, dl, VT, SrcOp,
9960 DAG.getConstant(ShiftAmt, MVT::i32));
9964 // Change opcode to non-immediate version
9966 default: llvm_unreachable("Unknown target vector shift node");
9967 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9968 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9969 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9972 // Need to build a vector containing shift amount
9973 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9976 ShOps[1] = DAG.getConstant(0, MVT::i32);
9977 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
9978 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9980 // The return type has to be a 128-bit type with the same element
9981 // type as the input type.
9982 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9983 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
9985 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
9986 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9989 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
9990 DebugLoc dl = Op.getDebugLoc();
9991 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9993 default: return SDValue(); // Don't custom lower most intrinsics.
9994 // Comparison intrinsics.
9995 case Intrinsic::x86_sse_comieq_ss:
9996 case Intrinsic::x86_sse_comilt_ss:
9997 case Intrinsic::x86_sse_comile_ss:
9998 case Intrinsic::x86_sse_comigt_ss:
9999 case Intrinsic::x86_sse_comige_ss:
10000 case Intrinsic::x86_sse_comineq_ss:
10001 case Intrinsic::x86_sse_ucomieq_ss:
10002 case Intrinsic::x86_sse_ucomilt_ss:
10003 case Intrinsic::x86_sse_ucomile_ss:
10004 case Intrinsic::x86_sse_ucomigt_ss:
10005 case Intrinsic::x86_sse_ucomige_ss:
10006 case Intrinsic::x86_sse_ucomineq_ss:
10007 case Intrinsic::x86_sse2_comieq_sd:
10008 case Intrinsic::x86_sse2_comilt_sd:
10009 case Intrinsic::x86_sse2_comile_sd:
10010 case Intrinsic::x86_sse2_comigt_sd:
10011 case Intrinsic::x86_sse2_comige_sd:
10012 case Intrinsic::x86_sse2_comineq_sd:
10013 case Intrinsic::x86_sse2_ucomieq_sd:
10014 case Intrinsic::x86_sse2_ucomilt_sd:
10015 case Intrinsic::x86_sse2_ucomile_sd:
10016 case Intrinsic::x86_sse2_ucomigt_sd:
10017 case Intrinsic::x86_sse2_ucomige_sd:
10018 case Intrinsic::x86_sse2_ucomineq_sd: {
10022 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10023 case Intrinsic::x86_sse_comieq_ss:
10024 case Intrinsic::x86_sse2_comieq_sd:
10025 Opc = X86ISD::COMI;
10028 case Intrinsic::x86_sse_comilt_ss:
10029 case Intrinsic::x86_sse2_comilt_sd:
10030 Opc = X86ISD::COMI;
10033 case Intrinsic::x86_sse_comile_ss:
10034 case Intrinsic::x86_sse2_comile_sd:
10035 Opc = X86ISD::COMI;
10038 case Intrinsic::x86_sse_comigt_ss:
10039 case Intrinsic::x86_sse2_comigt_sd:
10040 Opc = X86ISD::COMI;
10043 case Intrinsic::x86_sse_comige_ss:
10044 case Intrinsic::x86_sse2_comige_sd:
10045 Opc = X86ISD::COMI;
10048 case Intrinsic::x86_sse_comineq_ss:
10049 case Intrinsic::x86_sse2_comineq_sd:
10050 Opc = X86ISD::COMI;
10053 case Intrinsic::x86_sse_ucomieq_ss:
10054 case Intrinsic::x86_sse2_ucomieq_sd:
10055 Opc = X86ISD::UCOMI;
10058 case Intrinsic::x86_sse_ucomilt_ss:
10059 case Intrinsic::x86_sse2_ucomilt_sd:
10060 Opc = X86ISD::UCOMI;
10063 case Intrinsic::x86_sse_ucomile_ss:
10064 case Intrinsic::x86_sse2_ucomile_sd:
10065 Opc = X86ISD::UCOMI;
10068 case Intrinsic::x86_sse_ucomigt_ss:
10069 case Intrinsic::x86_sse2_ucomigt_sd:
10070 Opc = X86ISD::UCOMI;
10073 case Intrinsic::x86_sse_ucomige_ss:
10074 case Intrinsic::x86_sse2_ucomige_sd:
10075 Opc = X86ISD::UCOMI;
10078 case Intrinsic::x86_sse_ucomineq_ss:
10079 case Intrinsic::x86_sse2_ucomineq_sd:
10080 Opc = X86ISD::UCOMI;
10085 SDValue LHS = Op.getOperand(1);
10086 SDValue RHS = Op.getOperand(2);
10087 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10088 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10089 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10090 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10091 DAG.getConstant(X86CC, MVT::i8), Cond);
10092 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10095 // Arithmetic intrinsics.
10096 case Intrinsic::x86_sse2_pmulu_dq:
10097 case Intrinsic::x86_avx2_pmulu_dq:
10098 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10099 Op.getOperand(1), Op.getOperand(2));
10101 // SSE3/AVX horizontal add/sub intrinsics
10102 case Intrinsic::x86_sse3_hadd_ps:
10103 case Intrinsic::x86_sse3_hadd_pd:
10104 case Intrinsic::x86_avx_hadd_ps_256:
10105 case Intrinsic::x86_avx_hadd_pd_256:
10106 case Intrinsic::x86_sse3_hsub_ps:
10107 case Intrinsic::x86_sse3_hsub_pd:
10108 case Intrinsic::x86_avx_hsub_ps_256:
10109 case Intrinsic::x86_avx_hsub_pd_256:
10110 case Intrinsic::x86_ssse3_phadd_w_128:
10111 case Intrinsic::x86_ssse3_phadd_d_128:
10112 case Intrinsic::x86_avx2_phadd_w:
10113 case Intrinsic::x86_avx2_phadd_d:
10114 case Intrinsic::x86_ssse3_phsub_w_128:
10115 case Intrinsic::x86_ssse3_phsub_d_128:
10116 case Intrinsic::x86_avx2_phsub_w:
10117 case Intrinsic::x86_avx2_phsub_d: {
10120 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10121 case Intrinsic::x86_sse3_hadd_ps:
10122 case Intrinsic::x86_sse3_hadd_pd:
10123 case Intrinsic::x86_avx_hadd_ps_256:
10124 case Intrinsic::x86_avx_hadd_pd_256:
10125 Opcode = X86ISD::FHADD;
10127 case Intrinsic::x86_sse3_hsub_ps:
10128 case Intrinsic::x86_sse3_hsub_pd:
10129 case Intrinsic::x86_avx_hsub_ps_256:
10130 case Intrinsic::x86_avx_hsub_pd_256:
10131 Opcode = X86ISD::FHSUB;
10133 case Intrinsic::x86_ssse3_phadd_w_128:
10134 case Intrinsic::x86_ssse3_phadd_d_128:
10135 case Intrinsic::x86_avx2_phadd_w:
10136 case Intrinsic::x86_avx2_phadd_d:
10137 Opcode = X86ISD::HADD;
10139 case Intrinsic::x86_ssse3_phsub_w_128:
10140 case Intrinsic::x86_ssse3_phsub_d_128:
10141 case Intrinsic::x86_avx2_phsub_w:
10142 case Intrinsic::x86_avx2_phsub_d:
10143 Opcode = X86ISD::HSUB;
10146 return DAG.getNode(Opcode, dl, Op.getValueType(),
10147 Op.getOperand(1), Op.getOperand(2));
10150 // AVX2 variable shift intrinsics
10151 case Intrinsic::x86_avx2_psllv_d:
10152 case Intrinsic::x86_avx2_psllv_q:
10153 case Intrinsic::x86_avx2_psllv_d_256:
10154 case Intrinsic::x86_avx2_psllv_q_256:
10155 case Intrinsic::x86_avx2_psrlv_d:
10156 case Intrinsic::x86_avx2_psrlv_q:
10157 case Intrinsic::x86_avx2_psrlv_d_256:
10158 case Intrinsic::x86_avx2_psrlv_q_256:
10159 case Intrinsic::x86_avx2_psrav_d:
10160 case Intrinsic::x86_avx2_psrav_d_256: {
10163 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10164 case Intrinsic::x86_avx2_psllv_d:
10165 case Intrinsic::x86_avx2_psllv_q:
10166 case Intrinsic::x86_avx2_psllv_d_256:
10167 case Intrinsic::x86_avx2_psllv_q_256:
10170 case Intrinsic::x86_avx2_psrlv_d:
10171 case Intrinsic::x86_avx2_psrlv_q:
10172 case Intrinsic::x86_avx2_psrlv_d_256:
10173 case Intrinsic::x86_avx2_psrlv_q_256:
10176 case Intrinsic::x86_avx2_psrav_d:
10177 case Intrinsic::x86_avx2_psrav_d_256:
10181 return DAG.getNode(Opcode, dl, Op.getValueType(),
10182 Op.getOperand(1), Op.getOperand(2));
10185 case Intrinsic::x86_ssse3_pshuf_b_128:
10186 case Intrinsic::x86_avx2_pshuf_b:
10187 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
10188 Op.getOperand(1), Op.getOperand(2));
10190 case Intrinsic::x86_ssse3_psign_b_128:
10191 case Intrinsic::x86_ssse3_psign_w_128:
10192 case Intrinsic::x86_ssse3_psign_d_128:
10193 case Intrinsic::x86_avx2_psign_b:
10194 case Intrinsic::x86_avx2_psign_w:
10195 case Intrinsic::x86_avx2_psign_d:
10196 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
10197 Op.getOperand(1), Op.getOperand(2));
10199 case Intrinsic::x86_sse41_insertps:
10200 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
10201 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10203 case Intrinsic::x86_avx_vperm2f128_ps_256:
10204 case Intrinsic::x86_avx_vperm2f128_pd_256:
10205 case Intrinsic::x86_avx_vperm2f128_si_256:
10206 case Intrinsic::x86_avx2_vperm2i128:
10207 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
10208 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10210 case Intrinsic::x86_avx2_permd:
10211 case Intrinsic::x86_avx2_permps:
10212 // Operands intentionally swapped. Mask is last operand to intrinsic,
10213 // but second operand for node/intruction.
10214 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
10215 Op.getOperand(2), Op.getOperand(1));
10217 // ptest and testp intrinsics. The intrinsic these come from are designed to
10218 // return an integer value, not just an instruction so lower it to the ptest
10219 // or testp pattern and a setcc for the result.
10220 case Intrinsic::x86_sse41_ptestz:
10221 case Intrinsic::x86_sse41_ptestc:
10222 case Intrinsic::x86_sse41_ptestnzc:
10223 case Intrinsic::x86_avx_ptestz_256:
10224 case Intrinsic::x86_avx_ptestc_256:
10225 case Intrinsic::x86_avx_ptestnzc_256:
10226 case Intrinsic::x86_avx_vtestz_ps:
10227 case Intrinsic::x86_avx_vtestc_ps:
10228 case Intrinsic::x86_avx_vtestnzc_ps:
10229 case Intrinsic::x86_avx_vtestz_pd:
10230 case Intrinsic::x86_avx_vtestc_pd:
10231 case Intrinsic::x86_avx_vtestnzc_pd:
10232 case Intrinsic::x86_avx_vtestz_ps_256:
10233 case Intrinsic::x86_avx_vtestc_ps_256:
10234 case Intrinsic::x86_avx_vtestnzc_ps_256:
10235 case Intrinsic::x86_avx_vtestz_pd_256:
10236 case Intrinsic::x86_avx_vtestc_pd_256:
10237 case Intrinsic::x86_avx_vtestnzc_pd_256: {
10238 bool IsTestPacked = false;
10241 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
10242 case Intrinsic::x86_avx_vtestz_ps:
10243 case Intrinsic::x86_avx_vtestz_pd:
10244 case Intrinsic::x86_avx_vtestz_ps_256:
10245 case Intrinsic::x86_avx_vtestz_pd_256:
10246 IsTestPacked = true; // Fallthrough
10247 case Intrinsic::x86_sse41_ptestz:
10248 case Intrinsic::x86_avx_ptestz_256:
10250 X86CC = X86::COND_E;
10252 case Intrinsic::x86_avx_vtestc_ps:
10253 case Intrinsic::x86_avx_vtestc_pd:
10254 case Intrinsic::x86_avx_vtestc_ps_256:
10255 case Intrinsic::x86_avx_vtestc_pd_256:
10256 IsTestPacked = true; // Fallthrough
10257 case Intrinsic::x86_sse41_ptestc:
10258 case Intrinsic::x86_avx_ptestc_256:
10260 X86CC = X86::COND_B;
10262 case Intrinsic::x86_avx_vtestnzc_ps:
10263 case Intrinsic::x86_avx_vtestnzc_pd:
10264 case Intrinsic::x86_avx_vtestnzc_ps_256:
10265 case Intrinsic::x86_avx_vtestnzc_pd_256:
10266 IsTestPacked = true; // Fallthrough
10267 case Intrinsic::x86_sse41_ptestnzc:
10268 case Intrinsic::x86_avx_ptestnzc_256:
10270 X86CC = X86::COND_A;
10274 SDValue LHS = Op.getOperand(1);
10275 SDValue RHS = Op.getOperand(2);
10276 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
10277 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
10278 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
10279 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
10280 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10283 // SSE/AVX shift intrinsics
10284 case Intrinsic::x86_sse2_psll_w:
10285 case Intrinsic::x86_sse2_psll_d:
10286 case Intrinsic::x86_sse2_psll_q:
10287 case Intrinsic::x86_avx2_psll_w:
10288 case Intrinsic::x86_avx2_psll_d:
10289 case Intrinsic::x86_avx2_psll_q:
10290 case Intrinsic::x86_sse2_psrl_w:
10291 case Intrinsic::x86_sse2_psrl_d:
10292 case Intrinsic::x86_sse2_psrl_q:
10293 case Intrinsic::x86_avx2_psrl_w:
10294 case Intrinsic::x86_avx2_psrl_d:
10295 case Intrinsic::x86_avx2_psrl_q:
10296 case Intrinsic::x86_sse2_psra_w:
10297 case Intrinsic::x86_sse2_psra_d:
10298 case Intrinsic::x86_avx2_psra_w:
10299 case Intrinsic::x86_avx2_psra_d: {
10302 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10303 case Intrinsic::x86_sse2_psll_w:
10304 case Intrinsic::x86_sse2_psll_d:
10305 case Intrinsic::x86_sse2_psll_q:
10306 case Intrinsic::x86_avx2_psll_w:
10307 case Intrinsic::x86_avx2_psll_d:
10308 case Intrinsic::x86_avx2_psll_q:
10309 Opcode = X86ISD::VSHL;
10311 case Intrinsic::x86_sse2_psrl_w:
10312 case Intrinsic::x86_sse2_psrl_d:
10313 case Intrinsic::x86_sse2_psrl_q:
10314 case Intrinsic::x86_avx2_psrl_w:
10315 case Intrinsic::x86_avx2_psrl_d:
10316 case Intrinsic::x86_avx2_psrl_q:
10317 Opcode = X86ISD::VSRL;
10319 case Intrinsic::x86_sse2_psra_w:
10320 case Intrinsic::x86_sse2_psra_d:
10321 case Intrinsic::x86_avx2_psra_w:
10322 case Intrinsic::x86_avx2_psra_d:
10323 Opcode = X86ISD::VSRA;
10326 return DAG.getNode(Opcode, dl, Op.getValueType(),
10327 Op.getOperand(1), Op.getOperand(2));
10330 // SSE/AVX immediate shift intrinsics
10331 case Intrinsic::x86_sse2_pslli_w:
10332 case Intrinsic::x86_sse2_pslli_d:
10333 case Intrinsic::x86_sse2_pslli_q:
10334 case Intrinsic::x86_avx2_pslli_w:
10335 case Intrinsic::x86_avx2_pslli_d:
10336 case Intrinsic::x86_avx2_pslli_q:
10337 case Intrinsic::x86_sse2_psrli_w:
10338 case Intrinsic::x86_sse2_psrli_d:
10339 case Intrinsic::x86_sse2_psrli_q:
10340 case Intrinsic::x86_avx2_psrli_w:
10341 case Intrinsic::x86_avx2_psrli_d:
10342 case Intrinsic::x86_avx2_psrli_q:
10343 case Intrinsic::x86_sse2_psrai_w:
10344 case Intrinsic::x86_sse2_psrai_d:
10345 case Intrinsic::x86_avx2_psrai_w:
10346 case Intrinsic::x86_avx2_psrai_d: {
10349 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10350 case Intrinsic::x86_sse2_pslli_w:
10351 case Intrinsic::x86_sse2_pslli_d:
10352 case Intrinsic::x86_sse2_pslli_q:
10353 case Intrinsic::x86_avx2_pslli_w:
10354 case Intrinsic::x86_avx2_pslli_d:
10355 case Intrinsic::x86_avx2_pslli_q:
10356 Opcode = X86ISD::VSHLI;
10358 case Intrinsic::x86_sse2_psrli_w:
10359 case Intrinsic::x86_sse2_psrli_d:
10360 case Intrinsic::x86_sse2_psrli_q:
10361 case Intrinsic::x86_avx2_psrli_w:
10362 case Intrinsic::x86_avx2_psrli_d:
10363 case Intrinsic::x86_avx2_psrli_q:
10364 Opcode = X86ISD::VSRLI;
10366 case Intrinsic::x86_sse2_psrai_w:
10367 case Intrinsic::x86_sse2_psrai_d:
10368 case Intrinsic::x86_avx2_psrai_w:
10369 case Intrinsic::x86_avx2_psrai_d:
10370 Opcode = X86ISD::VSRAI;
10373 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
10374 Op.getOperand(1), Op.getOperand(2), DAG);
10377 case Intrinsic::x86_sse42_pcmpistria128:
10378 case Intrinsic::x86_sse42_pcmpestria128:
10379 case Intrinsic::x86_sse42_pcmpistric128:
10380 case Intrinsic::x86_sse42_pcmpestric128:
10381 case Intrinsic::x86_sse42_pcmpistrio128:
10382 case Intrinsic::x86_sse42_pcmpestrio128:
10383 case Intrinsic::x86_sse42_pcmpistris128:
10384 case Intrinsic::x86_sse42_pcmpestris128:
10385 case Intrinsic::x86_sse42_pcmpistriz128:
10386 case Intrinsic::x86_sse42_pcmpestriz128: {
10390 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10391 case Intrinsic::x86_sse42_pcmpistria128:
10392 Opcode = X86ISD::PCMPISTRI;
10393 X86CC = X86::COND_A;
10395 case Intrinsic::x86_sse42_pcmpestria128:
10396 Opcode = X86ISD::PCMPESTRI;
10397 X86CC = X86::COND_A;
10399 case Intrinsic::x86_sse42_pcmpistric128:
10400 Opcode = X86ISD::PCMPISTRI;
10401 X86CC = X86::COND_B;
10403 case Intrinsic::x86_sse42_pcmpestric128:
10404 Opcode = X86ISD::PCMPESTRI;
10405 X86CC = X86::COND_B;
10407 case Intrinsic::x86_sse42_pcmpistrio128:
10408 Opcode = X86ISD::PCMPISTRI;
10409 X86CC = X86::COND_O;
10411 case Intrinsic::x86_sse42_pcmpestrio128:
10412 Opcode = X86ISD::PCMPESTRI;
10413 X86CC = X86::COND_O;
10415 case Intrinsic::x86_sse42_pcmpistris128:
10416 Opcode = X86ISD::PCMPISTRI;
10417 X86CC = X86::COND_S;
10419 case Intrinsic::x86_sse42_pcmpestris128:
10420 Opcode = X86ISD::PCMPESTRI;
10421 X86CC = X86::COND_S;
10423 case Intrinsic::x86_sse42_pcmpistriz128:
10424 Opcode = X86ISD::PCMPISTRI;
10425 X86CC = X86::COND_E;
10427 case Intrinsic::x86_sse42_pcmpestriz128:
10428 Opcode = X86ISD::PCMPESTRI;
10429 X86CC = X86::COND_E;
10432 SmallVector<SDValue, 5> NewOps;
10433 NewOps.append(Op->op_begin()+1, Op->op_end());
10434 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10435 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10436 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10437 DAG.getConstant(X86CC, MVT::i8),
10438 SDValue(PCMP.getNode(), 1));
10439 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10442 case Intrinsic::x86_sse42_pcmpistri128:
10443 case Intrinsic::x86_sse42_pcmpestri128: {
10445 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10446 Opcode = X86ISD::PCMPISTRI;
10448 Opcode = X86ISD::PCMPESTRI;
10450 SmallVector<SDValue, 5> NewOps;
10451 NewOps.append(Op->op_begin()+1, Op->op_end());
10452 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10453 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10455 case Intrinsic::x86_fma_vfmadd_ps:
10456 case Intrinsic::x86_fma_vfmadd_pd:
10457 case Intrinsic::x86_fma_vfmsub_ps:
10458 case Intrinsic::x86_fma_vfmsub_pd:
10459 case Intrinsic::x86_fma_vfnmadd_ps:
10460 case Intrinsic::x86_fma_vfnmadd_pd:
10461 case Intrinsic::x86_fma_vfnmsub_ps:
10462 case Intrinsic::x86_fma_vfnmsub_pd:
10463 case Intrinsic::x86_fma_vfmaddsub_ps:
10464 case Intrinsic::x86_fma_vfmaddsub_pd:
10465 case Intrinsic::x86_fma_vfmsubadd_ps:
10466 case Intrinsic::x86_fma_vfmsubadd_pd:
10467 case Intrinsic::x86_fma_vfmadd_ps_256:
10468 case Intrinsic::x86_fma_vfmadd_pd_256:
10469 case Intrinsic::x86_fma_vfmsub_ps_256:
10470 case Intrinsic::x86_fma_vfmsub_pd_256:
10471 case Intrinsic::x86_fma_vfnmadd_ps_256:
10472 case Intrinsic::x86_fma_vfnmadd_pd_256:
10473 case Intrinsic::x86_fma_vfnmsub_ps_256:
10474 case Intrinsic::x86_fma_vfnmsub_pd_256:
10475 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10476 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10477 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10478 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
10481 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10482 case Intrinsic::x86_fma_vfmadd_ps:
10483 case Intrinsic::x86_fma_vfmadd_pd:
10484 case Intrinsic::x86_fma_vfmadd_ps_256:
10485 case Intrinsic::x86_fma_vfmadd_pd_256:
10486 Opc = X86ISD::FMADD;
10488 case Intrinsic::x86_fma_vfmsub_ps:
10489 case Intrinsic::x86_fma_vfmsub_pd:
10490 case Intrinsic::x86_fma_vfmsub_ps_256:
10491 case Intrinsic::x86_fma_vfmsub_pd_256:
10492 Opc = X86ISD::FMSUB;
10494 case Intrinsic::x86_fma_vfnmadd_ps:
10495 case Intrinsic::x86_fma_vfnmadd_pd:
10496 case Intrinsic::x86_fma_vfnmadd_ps_256:
10497 case Intrinsic::x86_fma_vfnmadd_pd_256:
10498 Opc = X86ISD::FNMADD;
10500 case Intrinsic::x86_fma_vfnmsub_ps:
10501 case Intrinsic::x86_fma_vfnmsub_pd:
10502 case Intrinsic::x86_fma_vfnmsub_ps_256:
10503 case Intrinsic::x86_fma_vfnmsub_pd_256:
10504 Opc = X86ISD::FNMSUB;
10506 case Intrinsic::x86_fma_vfmaddsub_ps:
10507 case Intrinsic::x86_fma_vfmaddsub_pd:
10508 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10509 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10510 Opc = X86ISD::FMADDSUB;
10512 case Intrinsic::x86_fma_vfmsubadd_ps:
10513 case Intrinsic::x86_fma_vfmsubadd_pd:
10514 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10515 case Intrinsic::x86_fma_vfmsubadd_pd_256:
10516 Opc = X86ISD::FMSUBADD;
10520 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
10521 Op.getOperand(2), Op.getOperand(3));
10526 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
10527 DebugLoc dl = Op.getDebugLoc();
10528 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10530 default: return SDValue(); // Don't custom lower most intrinsics.
10532 // RDRAND intrinsics.
10533 case Intrinsic::x86_rdrand_16:
10534 case Intrinsic::x86_rdrand_32:
10535 case Intrinsic::x86_rdrand_64: {
10536 // Emit the node with the right value type.
10537 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10538 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
10540 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
10541 // return the value from Rand, which is always 0, casted to i32.
10542 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10543 DAG.getConstant(1, Op->getValueType(1)),
10544 DAG.getConstant(X86::COND_B, MVT::i32),
10545 SDValue(Result.getNode(), 1) };
10546 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10547 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10550 // Return { result, isValid, chain }.
10551 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10552 SDValue(Result.getNode(), 2));
10557 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
10558 SelectionDAG &DAG) const {
10559 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10560 MFI->setReturnAddressIsTaken(true);
10562 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10563 DebugLoc dl = Op.getDebugLoc();
10564 EVT PtrVT = getPointerTy();
10567 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10569 DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
10570 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10571 DAG.getNode(ISD::ADD, dl, PtrVT,
10572 FrameAddr, Offset),
10573 MachinePointerInfo(), false, false, false, 0);
10576 // Just load the return address.
10577 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
10578 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10579 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10582 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
10583 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10584 MFI->setFrameAddressIsTaken(true);
10586 EVT VT = Op.getValueType();
10587 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
10588 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10589 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
10590 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
10592 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
10593 MachinePointerInfo(),
10594 false, false, false, 0);
10598 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
10599 SelectionDAG &DAG) const {
10600 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
10603 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
10604 SDValue Chain = Op.getOperand(0);
10605 SDValue Offset = Op.getOperand(1);
10606 SDValue Handler = Op.getOperand(2);
10607 DebugLoc dl = Op.getDebugLoc();
10609 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
10610 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
10612 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
10614 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
10615 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
10616 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
10617 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
10619 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
10621 return DAG.getNode(X86ISD::EH_RETURN, dl,
10623 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
10626 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
10627 SelectionDAG &DAG) const {
10628 DebugLoc DL = Op.getDebugLoc();
10629 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
10630 DAG.getVTList(MVT::i32, MVT::Other),
10631 Op.getOperand(0), Op.getOperand(1));
10634 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
10635 SelectionDAG &DAG) const {
10636 DebugLoc DL = Op.getDebugLoc();
10637 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
10638 Op.getOperand(0), Op.getOperand(1));
10641 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
10642 return Op.getOperand(0);
10645 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
10646 SelectionDAG &DAG) const {
10647 SDValue Root = Op.getOperand(0);
10648 SDValue Trmp = Op.getOperand(1); // trampoline
10649 SDValue FPtr = Op.getOperand(2); // nested function
10650 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
10651 DebugLoc dl = Op.getDebugLoc();
10653 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10654 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
10656 if (Subtarget->is64Bit()) {
10657 SDValue OutChains[6];
10659 // Large code-model.
10660 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
10661 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
10663 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
10664 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
10666 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
10668 // Load the pointer to the nested function into R11.
10669 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
10670 SDValue Addr = Trmp;
10671 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10672 Addr, MachinePointerInfo(TrmpAddr),
10675 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10676 DAG.getConstant(2, MVT::i64));
10677 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
10678 MachinePointerInfo(TrmpAddr, 2),
10681 // Load the 'nest' parameter value into R10.
10682 // R10 is specified in X86CallingConv.td
10683 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
10684 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10685 DAG.getConstant(10, MVT::i64));
10686 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10687 Addr, MachinePointerInfo(TrmpAddr, 10),
10690 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10691 DAG.getConstant(12, MVT::i64));
10692 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
10693 MachinePointerInfo(TrmpAddr, 12),
10696 // Jump to the nested function.
10697 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
10698 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10699 DAG.getConstant(20, MVT::i64));
10700 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10701 Addr, MachinePointerInfo(TrmpAddr, 20),
10704 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
10705 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10706 DAG.getConstant(22, MVT::i64));
10707 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
10708 MachinePointerInfo(TrmpAddr, 22),
10711 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
10713 const Function *Func =
10714 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
10715 CallingConv::ID CC = Func->getCallingConv();
10720 llvm_unreachable("Unsupported calling convention");
10721 case CallingConv::C:
10722 case CallingConv::X86_StdCall: {
10723 // Pass 'nest' parameter in ECX.
10724 // Must be kept in sync with X86CallingConv.td
10725 NestReg = X86::ECX;
10727 // Check that ECX wasn't needed by an 'inreg' parameter.
10728 FunctionType *FTy = Func->getFunctionType();
10729 const AttributeSet &Attrs = Func->getAttributes();
10731 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10732 unsigned InRegCount = 0;
10735 for (FunctionType::param_iterator I = FTy->param_begin(),
10736 E = FTy->param_end(); I != E; ++I, ++Idx)
10737 if (Attrs.getParamAttributes(Idx).hasAttribute(Attributes::InReg))
10738 // FIXME: should only count parameters that are lowered to integers.
10739 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10741 if (InRegCount > 2) {
10742 report_fatal_error("Nest register in use - reduce number of inreg"
10748 case CallingConv::X86_FastCall:
10749 case CallingConv::X86_ThisCall:
10750 case CallingConv::Fast:
10751 // Pass 'nest' parameter in EAX.
10752 // Must be kept in sync with X86CallingConv.td
10753 NestReg = X86::EAX;
10757 SDValue OutChains[4];
10758 SDValue Addr, Disp;
10760 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10761 DAG.getConstant(10, MVT::i32));
10762 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10764 // This is storing the opcode for MOV32ri.
10765 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10766 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
10767 OutChains[0] = DAG.getStore(Root, dl,
10768 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10769 Trmp, MachinePointerInfo(TrmpAddr),
10772 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10773 DAG.getConstant(1, MVT::i32));
10774 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10775 MachinePointerInfo(TrmpAddr, 1),
10778 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10779 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10780 DAG.getConstant(5, MVT::i32));
10781 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10782 MachinePointerInfo(TrmpAddr, 5),
10785 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10786 DAG.getConstant(6, MVT::i32));
10787 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10788 MachinePointerInfo(TrmpAddr, 6),
10791 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10795 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10796 SelectionDAG &DAG) const {
10798 The rounding mode is in bits 11:10 of FPSR, and has the following
10800 00 Round to nearest
10805 FLT_ROUNDS, on the other hand, expects the following:
10812 To perform the conversion, we do:
10813 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10816 MachineFunction &MF = DAG.getMachineFunction();
10817 const TargetMachine &TM = MF.getTarget();
10818 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10819 unsigned StackAlignment = TFI.getStackAlignment();
10820 EVT VT = Op.getValueType();
10821 DebugLoc DL = Op.getDebugLoc();
10823 // Save FP Control Word to stack slot
10824 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10825 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10828 MachineMemOperand *MMO =
10829 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10830 MachineMemOperand::MOStore, 2, 2);
10832 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10833 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10834 DAG.getVTList(MVT::Other),
10835 Ops, 2, MVT::i16, MMO);
10837 // Load FP Control Word from stack slot
10838 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10839 MachinePointerInfo(), false, false, false, 0);
10841 // Transform as necessary
10843 DAG.getNode(ISD::SRL, DL, MVT::i16,
10844 DAG.getNode(ISD::AND, DL, MVT::i16,
10845 CWD, DAG.getConstant(0x800, MVT::i16)),
10846 DAG.getConstant(11, MVT::i8));
10848 DAG.getNode(ISD::SRL, DL, MVT::i16,
10849 DAG.getNode(ISD::AND, DL, MVT::i16,
10850 CWD, DAG.getConstant(0x400, MVT::i16)),
10851 DAG.getConstant(9, MVT::i8));
10854 DAG.getNode(ISD::AND, DL, MVT::i16,
10855 DAG.getNode(ISD::ADD, DL, MVT::i16,
10856 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10857 DAG.getConstant(1, MVT::i16)),
10858 DAG.getConstant(3, MVT::i16));
10861 return DAG.getNode((VT.getSizeInBits() < 16 ?
10862 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10865 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
10866 EVT VT = Op.getValueType();
10868 unsigned NumBits = VT.getSizeInBits();
10869 DebugLoc dl = Op.getDebugLoc();
10871 Op = Op.getOperand(0);
10872 if (VT == MVT::i8) {
10873 // Zero extend to i32 since there is not an i8 bsr.
10875 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10878 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10879 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10880 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10882 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10885 DAG.getConstant(NumBits+NumBits-1, OpVT),
10886 DAG.getConstant(X86::COND_E, MVT::i8),
10889 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10891 // Finally xor with NumBits-1.
10892 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10895 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10899 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
10900 EVT VT = Op.getValueType();
10902 unsigned NumBits = VT.getSizeInBits();
10903 DebugLoc dl = Op.getDebugLoc();
10905 Op = Op.getOperand(0);
10906 if (VT == MVT::i8) {
10907 // Zero extend to i32 since there is not an i8 bsr.
10909 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10912 // Issue a bsr (scan bits in reverse).
10913 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10914 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10916 // And xor with NumBits-1.
10917 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10920 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10924 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
10925 EVT VT = Op.getValueType();
10926 unsigned NumBits = VT.getSizeInBits();
10927 DebugLoc dl = Op.getDebugLoc();
10928 Op = Op.getOperand(0);
10930 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10931 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10932 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10934 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10937 DAG.getConstant(NumBits, VT),
10938 DAG.getConstant(X86::COND_E, MVT::i8),
10941 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10944 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10945 // ones, and then concatenate the result back.
10946 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10947 EVT VT = Op.getValueType();
10949 assert(VT.is256BitVector() && VT.isInteger() &&
10950 "Unsupported value type for operation");
10952 unsigned NumElems = VT.getVectorNumElements();
10953 DebugLoc dl = Op.getDebugLoc();
10955 // Extract the LHS vectors
10956 SDValue LHS = Op.getOperand(0);
10957 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10958 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10960 // Extract the RHS vectors
10961 SDValue RHS = Op.getOperand(1);
10962 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10963 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10965 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10966 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10968 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10969 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10970 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10973 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
10974 assert(Op.getValueType().is256BitVector() &&
10975 Op.getValueType().isInteger() &&
10976 "Only handle AVX 256-bit vector integer operation");
10977 return Lower256IntArith(Op, DAG);
10980 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
10981 assert(Op.getValueType().is256BitVector() &&
10982 Op.getValueType().isInteger() &&
10983 "Only handle AVX 256-bit vector integer operation");
10984 return Lower256IntArith(Op, DAG);
10987 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
10988 SelectionDAG &DAG) {
10989 EVT VT = Op.getValueType();
10991 // Decompose 256-bit ops into smaller 128-bit ops.
10992 if (VT.is256BitVector() && !Subtarget->hasInt256())
10993 return Lower256IntArith(Op, DAG);
10995 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10996 "Only know how to lower V2I64/V4I64 multiply");
10998 DebugLoc dl = Op.getDebugLoc();
11000 // Ahi = psrlqi(a, 32);
11001 // Bhi = psrlqi(b, 32);
11003 // AloBlo = pmuludq(a, b);
11004 // AloBhi = pmuludq(a, Bhi);
11005 // AhiBlo = pmuludq(Ahi, b);
11007 // AloBhi = psllqi(AloBhi, 32);
11008 // AhiBlo = psllqi(AhiBlo, 32);
11009 // return AloBlo + AloBhi + AhiBlo;
11011 SDValue A = Op.getOperand(0);
11012 SDValue B = Op.getOperand(1);
11014 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11016 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
11017 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
11019 // Bit cast to 32-bit vectors for MULUDQ
11020 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11021 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11022 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11023 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11024 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11026 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
11027 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
11028 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
11030 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
11031 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
11033 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11034 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11037 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
11039 EVT VT = Op.getValueType();
11040 DebugLoc dl = Op.getDebugLoc();
11041 SDValue R = Op.getOperand(0);
11042 SDValue Amt = Op.getOperand(1);
11043 LLVMContext *Context = DAG.getContext();
11045 if (!Subtarget->hasSSE2())
11048 // Optimize shl/srl/sra with constant shift amount.
11049 if (isSplatVector(Amt.getNode())) {
11050 SDValue SclrAmt = Amt->getOperand(0);
11051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
11052 uint64_t ShiftAmt = C->getZExtValue();
11054 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
11055 (Subtarget->hasInt256() &&
11056 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
11057 if (Op.getOpcode() == ISD::SHL)
11058 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11059 DAG.getConstant(ShiftAmt, MVT::i32));
11060 if (Op.getOpcode() == ISD::SRL)
11061 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11062 DAG.getConstant(ShiftAmt, MVT::i32));
11063 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11064 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11065 DAG.getConstant(ShiftAmt, MVT::i32));
11068 if (VT == MVT::v16i8) {
11069 if (Op.getOpcode() == ISD::SHL) {
11070 // Make a large shift.
11071 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11072 DAG.getConstant(ShiftAmt, MVT::i32));
11073 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11074 // Zero out the rightmost bits.
11075 SmallVector<SDValue, 16> V(16,
11076 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11078 return DAG.getNode(ISD::AND, dl, VT, SHL,
11079 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11081 if (Op.getOpcode() == ISD::SRL) {
11082 // Make a large shift.
11083 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11084 DAG.getConstant(ShiftAmt, MVT::i32));
11085 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11086 // Zero out the leftmost bits.
11087 SmallVector<SDValue, 16> V(16,
11088 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11090 return DAG.getNode(ISD::AND, dl, VT, SRL,
11091 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11093 if (Op.getOpcode() == ISD::SRA) {
11094 if (ShiftAmt == 7) {
11095 // R s>> 7 === R s< 0
11096 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11097 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11100 // R s>> a === ((R u>> a) ^ m) - m
11101 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11102 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
11104 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11105 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11106 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11109 llvm_unreachable("Unknown shift opcode.");
11112 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
11113 if (Op.getOpcode() == ISD::SHL) {
11114 // Make a large shift.
11115 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11116 DAG.getConstant(ShiftAmt, MVT::i32));
11117 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11118 // Zero out the rightmost bits.
11119 SmallVector<SDValue, 32> V(32,
11120 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11122 return DAG.getNode(ISD::AND, dl, VT, SHL,
11123 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11125 if (Op.getOpcode() == ISD::SRL) {
11126 // Make a large shift.
11127 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11128 DAG.getConstant(ShiftAmt, MVT::i32));
11129 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11130 // Zero out the leftmost bits.
11131 SmallVector<SDValue, 32> V(32,
11132 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11134 return DAG.getNode(ISD::AND, dl, VT, SRL,
11135 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11137 if (Op.getOpcode() == ISD::SRA) {
11138 if (ShiftAmt == 7) {
11139 // R s>> 7 === R s< 0
11140 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11141 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11144 // R s>> a === ((R u>> a) ^ m) - m
11145 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11146 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
11148 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11149 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11150 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11153 llvm_unreachable("Unknown shift opcode.");
11158 // Lower SHL with variable shift amount.
11159 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11160 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
11161 DAG.getConstant(23, MVT::i32));
11163 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
11164 Constant *C = ConstantDataVector::get(*Context, CV);
11165 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
11166 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11167 MachinePointerInfo::getConstantPool(),
11168 false, false, false, 16);
11170 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
11171 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
11172 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
11173 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
11175 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11176 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
11179 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
11180 DAG.getConstant(5, MVT::i32));
11181 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
11183 // Turn 'a' into a mask suitable for VSELECT
11184 SDValue VSelM = DAG.getConstant(0x80, VT);
11185 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11186 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11188 SDValue CM1 = DAG.getConstant(0x0f, VT);
11189 SDValue CM2 = DAG.getConstant(0x3f, VT);
11191 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
11192 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
11193 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11194 DAG.getConstant(4, MVT::i32), DAG);
11195 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11196 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11199 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11200 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11201 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11203 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
11204 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
11205 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11206 DAG.getConstant(2, MVT::i32), DAG);
11207 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11208 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11211 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11212 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11213 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11215 // return VSELECT(r, r+r, a);
11216 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
11217 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
11221 // Decompose 256-bit shifts into smaller 128-bit shifts.
11222 if (VT.is256BitVector()) {
11223 unsigned NumElems = VT.getVectorNumElements();
11224 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11225 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11227 // Extract the two vectors
11228 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
11229 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
11231 // Recreate the shift amount vectors
11232 SDValue Amt1, Amt2;
11233 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11234 // Constant shift amount
11235 SmallVector<SDValue, 4> Amt1Csts;
11236 SmallVector<SDValue, 4> Amt2Csts;
11237 for (unsigned i = 0; i != NumElems/2; ++i)
11238 Amt1Csts.push_back(Amt->getOperand(i));
11239 for (unsigned i = NumElems/2; i != NumElems; ++i)
11240 Amt2Csts.push_back(Amt->getOperand(i));
11242 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11243 &Amt1Csts[0], NumElems/2);
11244 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11245 &Amt2Csts[0], NumElems/2);
11247 // Variable shift amount
11248 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
11249 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
11252 // Issue new vector shifts for the smaller types
11253 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
11254 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
11256 // Concatenate the result back
11257 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
11263 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
11264 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
11265 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
11266 // looks for this combo and may remove the "setcc" instruction if the "setcc"
11267 // has only one use.
11268 SDNode *N = Op.getNode();
11269 SDValue LHS = N->getOperand(0);
11270 SDValue RHS = N->getOperand(1);
11271 unsigned BaseOp = 0;
11273 DebugLoc DL = Op.getDebugLoc();
11274 switch (Op.getOpcode()) {
11275 default: llvm_unreachable("Unknown ovf instruction!");
11277 // A subtract of one will be selected as a INC. Note that INC doesn't
11278 // set CF, so we can't do this for UADDO.
11279 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11281 BaseOp = X86ISD::INC;
11282 Cond = X86::COND_O;
11285 BaseOp = X86ISD::ADD;
11286 Cond = X86::COND_O;
11289 BaseOp = X86ISD::ADD;
11290 Cond = X86::COND_B;
11293 // A subtract of one will be selected as a DEC. Note that DEC doesn't
11294 // set CF, so we can't do this for USUBO.
11295 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11297 BaseOp = X86ISD::DEC;
11298 Cond = X86::COND_O;
11301 BaseOp = X86ISD::SUB;
11302 Cond = X86::COND_O;
11305 BaseOp = X86ISD::SUB;
11306 Cond = X86::COND_B;
11309 BaseOp = X86ISD::SMUL;
11310 Cond = X86::COND_O;
11312 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
11313 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
11315 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
11318 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11319 DAG.getConstant(X86::COND_O, MVT::i32),
11320 SDValue(Sum.getNode(), 2));
11322 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11326 // Also sets EFLAGS.
11327 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
11328 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
11331 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
11332 DAG.getConstant(Cond, MVT::i32),
11333 SDValue(Sum.getNode(), 1));
11335 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11338 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
11339 SelectionDAG &DAG) const {
11340 DebugLoc dl = Op.getDebugLoc();
11341 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
11342 EVT VT = Op.getValueType();
11344 if (!Subtarget->hasSSE2() || !VT.isVector())
11347 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
11348 ExtraVT.getScalarType().getSizeInBits();
11349 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
11351 switch (VT.getSimpleVT().SimpleTy) {
11352 default: return SDValue();
11355 if (!Subtarget->hasFp256())
11357 if (!Subtarget->hasInt256()) {
11358 // needs to be split
11359 unsigned NumElems = VT.getVectorNumElements();
11361 // Extract the LHS vectors
11362 SDValue LHS = Op.getOperand(0);
11363 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11364 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11366 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11367 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11369 EVT ExtraEltVT = ExtraVT.getVectorElementType();
11370 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
11371 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
11373 SDValue Extra = DAG.getValueType(ExtraVT);
11375 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
11376 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
11378 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
11383 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
11384 Op.getOperand(0), ShAmt, DAG);
11385 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
11391 static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget,
11392 SelectionDAG &DAG) {
11393 DebugLoc dl = Op.getDebugLoc();
11395 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
11396 // There isn't any reason to disable it if the target processor supports it.
11397 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
11398 SDValue Chain = Op.getOperand(0);
11399 SDValue Zero = DAG.getConstant(0, MVT::i32);
11401 DAG.getRegister(X86::ESP, MVT::i32), // Base
11402 DAG.getTargetConstant(1, MVT::i8), // Scale
11403 DAG.getRegister(0, MVT::i32), // Index
11404 DAG.getTargetConstant(0, MVT::i32), // Disp
11405 DAG.getRegister(0, MVT::i32), // Segment.
11410 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11411 array_lengthof(Ops));
11412 return SDValue(Res, 0);
11415 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
11417 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11419 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11420 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11421 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
11422 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
11424 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
11425 if (!Op1 && !Op2 && !Op3 && Op4)
11426 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
11428 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
11429 if (Op1 && !Op2 && !Op3 && !Op4)
11430 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
11432 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
11434 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11437 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
11438 SelectionDAG &DAG) {
11439 DebugLoc dl = Op.getDebugLoc();
11440 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
11441 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
11442 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
11443 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
11445 // The only fence that needs an instruction is a sequentially-consistent
11446 // cross-thread fence.
11447 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
11448 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
11449 // no-sse2). There isn't any reason to disable it if the target processor
11451 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
11452 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11454 SDValue Chain = Op.getOperand(0);
11455 SDValue Zero = DAG.getConstant(0, MVT::i32);
11457 DAG.getRegister(X86::ESP, MVT::i32), // Base
11458 DAG.getTargetConstant(1, MVT::i8), // Scale
11459 DAG.getRegister(0, MVT::i32), // Index
11460 DAG.getTargetConstant(0, MVT::i32), // Disp
11461 DAG.getRegister(0, MVT::i32), // Segment.
11466 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11467 array_lengthof(Ops));
11468 return SDValue(Res, 0);
11471 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
11472 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11476 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
11477 SelectionDAG &DAG) {
11478 EVT T = Op.getValueType();
11479 DebugLoc DL = Op.getDebugLoc();
11482 switch(T.getSimpleVT().SimpleTy) {
11483 default: llvm_unreachable("Invalid value type!");
11484 case MVT::i8: Reg = X86::AL; size = 1; break;
11485 case MVT::i16: Reg = X86::AX; size = 2; break;
11486 case MVT::i32: Reg = X86::EAX; size = 4; break;
11488 assert(Subtarget->is64Bit() && "Node not type legal!");
11489 Reg = X86::RAX; size = 8;
11492 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
11493 Op.getOperand(2), SDValue());
11494 SDValue Ops[] = { cpIn.getValue(0),
11497 DAG.getTargetConstant(size, MVT::i8),
11498 cpIn.getValue(1) };
11499 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11500 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
11501 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
11504 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
11508 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
11509 SelectionDAG &DAG) {
11510 assert(Subtarget->is64Bit() && "Result not type legalized?");
11511 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11512 SDValue TheChain = Op.getOperand(0);
11513 DebugLoc dl = Op.getDebugLoc();
11514 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11515 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
11516 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
11518 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11519 DAG.getConstant(32, MVT::i8));
11521 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
11524 return DAG.getMergeValues(Ops, 2, dl);
11527 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
11528 EVT SrcVT = Op.getOperand(0).getValueType();
11529 EVT DstVT = Op.getValueType();
11530 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
11531 Subtarget->hasMMX() && "Unexpected custom BITCAST");
11532 assert((DstVT == MVT::i64 ||
11533 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
11534 "Unexpected custom BITCAST");
11535 // i64 <=> MMX conversions are Legal.
11536 if (SrcVT==MVT::i64 && DstVT.isVector())
11538 if (DstVT==MVT::i64 && SrcVT.isVector())
11540 // MMX <=> MMX conversions are Legal.
11541 if (SrcVT.isVector() && DstVT.isVector())
11543 // All other conversions need to be expanded.
11547 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
11548 SDNode *Node = Op.getNode();
11549 DebugLoc dl = Node->getDebugLoc();
11550 EVT T = Node->getValueType(0);
11551 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
11552 DAG.getConstant(0, T), Node->getOperand(2));
11553 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
11554 cast<AtomicSDNode>(Node)->getMemoryVT(),
11555 Node->getOperand(0),
11556 Node->getOperand(1), negOp,
11557 cast<AtomicSDNode>(Node)->getSrcValue(),
11558 cast<AtomicSDNode>(Node)->getAlignment(),
11559 cast<AtomicSDNode>(Node)->getOrdering(),
11560 cast<AtomicSDNode>(Node)->getSynchScope());
11563 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
11564 SDNode *Node = Op.getNode();
11565 DebugLoc dl = Node->getDebugLoc();
11566 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11568 // Convert seq_cst store -> xchg
11569 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
11570 // FIXME: On 32-bit, store -> fist or movq would be more efficient
11571 // (The only way to get a 16-byte store is cmpxchg16b)
11572 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
11573 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
11574 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
11575 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
11576 cast<AtomicSDNode>(Node)->getMemoryVT(),
11577 Node->getOperand(0),
11578 Node->getOperand(1), Node->getOperand(2),
11579 cast<AtomicSDNode>(Node)->getMemOperand(),
11580 cast<AtomicSDNode>(Node)->getOrdering(),
11581 cast<AtomicSDNode>(Node)->getSynchScope());
11582 return Swap.getValue(1);
11584 // Other atomic stores have a simple pattern.
11588 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
11589 EVT VT = Op.getNode()->getValueType(0);
11591 // Let legalize expand this if it isn't a legal type yet.
11592 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
11595 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11598 bool ExtraOp = false;
11599 switch (Op.getOpcode()) {
11600 default: llvm_unreachable("Invalid code");
11601 case ISD::ADDC: Opc = X86ISD::ADD; break;
11602 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
11603 case ISD::SUBC: Opc = X86ISD::SUB; break;
11604 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
11608 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11610 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11611 Op.getOperand(1), Op.getOperand(2));
11614 /// LowerOperation - Provide custom lowering hooks for some operations.
11616 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
11617 switch (Op.getOpcode()) {
11618 default: llvm_unreachable("Should not custom lower this!");
11619 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
11620 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG);
11621 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
11622 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
11623 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
11624 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
11625 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
11626 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
11627 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
11628 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
11629 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
11630 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
11631 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
11632 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
11633 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
11634 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
11635 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
11636 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
11637 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
11638 case ISD::SHL_PARTS:
11639 case ISD::SRA_PARTS:
11640 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
11641 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
11642 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
11643 case ISD::TRUNCATE: return lowerTRUNCATE(Op, DAG);
11644 case ISD::ZERO_EXTEND: return lowerZERO_EXTEND(Op, DAG);
11645 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
11646 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
11647 case ISD::FP_EXTEND: return lowerFP_EXTEND(Op, DAG);
11648 case ISD::FABS: return LowerFABS(Op, DAG);
11649 case ISD::FNEG: return LowerFNEG(Op, DAG);
11650 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
11651 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
11652 case ISD::SETCC: return LowerSETCC(Op, DAG);
11653 case ISD::SELECT: return LowerSELECT(Op, DAG);
11654 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
11655 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
11656 case ISD::VASTART: return LowerVASTART(Op, DAG);
11657 case ISD::VAARG: return LowerVAARG(Op, DAG);
11658 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
11659 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
11660 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
11661 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
11662 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
11663 case ISD::FRAME_TO_ARGS_OFFSET:
11664 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
11665 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
11666 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
11667 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
11668 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
11669 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
11670 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
11671 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
11672 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
11673 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
11674 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
11675 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
11678 case ISD::SHL: return LowerShift(Op, DAG);
11684 case ISD::UMULO: return LowerXALUO(Op, DAG);
11685 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
11686 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
11690 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
11691 case ISD::ADD: return LowerADD(Op, DAG);
11692 case ISD::SUB: return LowerSUB(Op, DAG);
11696 static void ReplaceATOMIC_LOAD(SDNode *Node,
11697 SmallVectorImpl<SDValue> &Results,
11698 SelectionDAG &DAG) {
11699 DebugLoc dl = Node->getDebugLoc();
11700 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11702 // Convert wide load -> cmpxchg8b/cmpxchg16b
11703 // FIXME: On 32-bit, load -> fild or movq would be more efficient
11704 // (The only way to get a 16-byte load is cmpxchg16b)
11705 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
11706 SDValue Zero = DAG.getConstant(0, VT);
11707 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
11708 Node->getOperand(0),
11709 Node->getOperand(1), Zero, Zero,
11710 cast<AtomicSDNode>(Node)->getMemOperand(),
11711 cast<AtomicSDNode>(Node)->getOrdering(),
11712 cast<AtomicSDNode>(Node)->getSynchScope());
11713 Results.push_back(Swap.getValue(0));
11714 Results.push_back(Swap.getValue(1));
11718 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
11719 SelectionDAG &DAG, unsigned NewOp) {
11720 DebugLoc dl = Node->getDebugLoc();
11721 assert (Node->getValueType(0) == MVT::i64 &&
11722 "Only know how to expand i64 atomics");
11724 SDValue Chain = Node->getOperand(0);
11725 SDValue In1 = Node->getOperand(1);
11726 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11727 Node->getOperand(2), DAG.getIntPtrConstant(0));
11728 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11729 Node->getOperand(2), DAG.getIntPtrConstant(1));
11730 SDValue Ops[] = { Chain, In1, In2L, In2H };
11731 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11733 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11734 cast<MemSDNode>(Node)->getMemOperand());
11735 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11736 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11737 Results.push_back(Result.getValue(2));
11740 /// ReplaceNodeResults - Replace a node with an illegal result type
11741 /// with a new node built out of custom code.
11742 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11743 SmallVectorImpl<SDValue>&Results,
11744 SelectionDAG &DAG) const {
11745 DebugLoc dl = N->getDebugLoc();
11746 switch (N->getOpcode()) {
11748 llvm_unreachable("Do not know how to custom type legalize this operation!");
11749 case ISD::SIGN_EXTEND_INREG:
11754 // We don't want to expand or promote these.
11756 case ISD::FP_TO_SINT:
11757 case ISD::FP_TO_UINT: {
11758 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11760 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11763 std::pair<SDValue,SDValue> Vals =
11764 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11765 SDValue FIST = Vals.first, StackSlot = Vals.second;
11766 if (FIST.getNode() != 0) {
11767 EVT VT = N->getValueType(0);
11768 // Return a load from the stack slot.
11769 if (StackSlot.getNode() != 0)
11770 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11771 MachinePointerInfo(),
11772 false, false, false, 0));
11774 Results.push_back(FIST);
11778 case ISD::UINT_TO_FP: {
11779 if (N->getOperand(0).getValueType() != MVT::v2i32 &&
11780 N->getValueType(0) != MVT::v2f32)
11782 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
11784 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11786 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
11787 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
11788 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
11789 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
11790 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
11791 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
11794 case ISD::FP_ROUND: {
11795 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
11796 Results.push_back(V);
11799 case ISD::READCYCLECOUNTER: {
11800 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11801 SDValue TheChain = N->getOperand(0);
11802 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11803 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11805 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11807 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11808 SDValue Ops[] = { eax, edx };
11809 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11810 Results.push_back(edx.getValue(1));
11813 case ISD::ATOMIC_CMP_SWAP: {
11814 EVT T = N->getValueType(0);
11815 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11816 bool Regs64bit = T == MVT::i128;
11817 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11818 SDValue cpInL, cpInH;
11819 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11820 DAG.getConstant(0, HalfT));
11821 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11822 DAG.getConstant(1, HalfT));
11823 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11824 Regs64bit ? X86::RAX : X86::EAX,
11826 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11827 Regs64bit ? X86::RDX : X86::EDX,
11828 cpInH, cpInL.getValue(1));
11829 SDValue swapInL, swapInH;
11830 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11831 DAG.getConstant(0, HalfT));
11832 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11833 DAG.getConstant(1, HalfT));
11834 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11835 Regs64bit ? X86::RBX : X86::EBX,
11836 swapInL, cpInH.getValue(1));
11837 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11838 Regs64bit ? X86::RCX : X86::ECX,
11839 swapInH, swapInL.getValue(1));
11840 SDValue Ops[] = { swapInH.getValue(0),
11842 swapInH.getValue(1) };
11843 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11844 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11845 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11846 X86ISD::LCMPXCHG8_DAG;
11847 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11849 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11850 Regs64bit ? X86::RAX : X86::EAX,
11851 HalfT, Result.getValue(1));
11852 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11853 Regs64bit ? X86::RDX : X86::EDX,
11854 HalfT, cpOutL.getValue(2));
11855 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11856 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11857 Results.push_back(cpOutH.getValue(1));
11860 case ISD::ATOMIC_LOAD_ADD:
11861 case ISD::ATOMIC_LOAD_AND:
11862 case ISD::ATOMIC_LOAD_NAND:
11863 case ISD::ATOMIC_LOAD_OR:
11864 case ISD::ATOMIC_LOAD_SUB:
11865 case ISD::ATOMIC_LOAD_XOR:
11866 case ISD::ATOMIC_LOAD_MAX:
11867 case ISD::ATOMIC_LOAD_MIN:
11868 case ISD::ATOMIC_LOAD_UMAX:
11869 case ISD::ATOMIC_LOAD_UMIN:
11870 case ISD::ATOMIC_SWAP: {
11872 switch (N->getOpcode()) {
11873 default: llvm_unreachable("Unexpected opcode");
11874 case ISD::ATOMIC_LOAD_ADD:
11875 Opc = X86ISD::ATOMADD64_DAG;
11877 case ISD::ATOMIC_LOAD_AND:
11878 Opc = X86ISD::ATOMAND64_DAG;
11880 case ISD::ATOMIC_LOAD_NAND:
11881 Opc = X86ISD::ATOMNAND64_DAG;
11883 case ISD::ATOMIC_LOAD_OR:
11884 Opc = X86ISD::ATOMOR64_DAG;
11886 case ISD::ATOMIC_LOAD_SUB:
11887 Opc = X86ISD::ATOMSUB64_DAG;
11889 case ISD::ATOMIC_LOAD_XOR:
11890 Opc = X86ISD::ATOMXOR64_DAG;
11892 case ISD::ATOMIC_LOAD_MAX:
11893 Opc = X86ISD::ATOMMAX64_DAG;
11895 case ISD::ATOMIC_LOAD_MIN:
11896 Opc = X86ISD::ATOMMIN64_DAG;
11898 case ISD::ATOMIC_LOAD_UMAX:
11899 Opc = X86ISD::ATOMUMAX64_DAG;
11901 case ISD::ATOMIC_LOAD_UMIN:
11902 Opc = X86ISD::ATOMUMIN64_DAG;
11904 case ISD::ATOMIC_SWAP:
11905 Opc = X86ISD::ATOMSWAP64_DAG;
11908 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
11911 case ISD::ATOMIC_LOAD:
11912 ReplaceATOMIC_LOAD(N, Results, DAG);
11916 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11918 default: return NULL;
11919 case X86ISD::BSF: return "X86ISD::BSF";
11920 case X86ISD::BSR: return "X86ISD::BSR";
11921 case X86ISD::SHLD: return "X86ISD::SHLD";
11922 case X86ISD::SHRD: return "X86ISD::SHRD";
11923 case X86ISD::FAND: return "X86ISD::FAND";
11924 case X86ISD::FOR: return "X86ISD::FOR";
11925 case X86ISD::FXOR: return "X86ISD::FXOR";
11926 case X86ISD::FSRL: return "X86ISD::FSRL";
11927 case X86ISD::FILD: return "X86ISD::FILD";
11928 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11929 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11930 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11931 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11932 case X86ISD::FLD: return "X86ISD::FLD";
11933 case X86ISD::FST: return "X86ISD::FST";
11934 case X86ISD::CALL: return "X86ISD::CALL";
11935 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11936 case X86ISD::BT: return "X86ISD::BT";
11937 case X86ISD::CMP: return "X86ISD::CMP";
11938 case X86ISD::COMI: return "X86ISD::COMI";
11939 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11940 case X86ISD::SETCC: return "X86ISD::SETCC";
11941 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11942 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11943 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11944 case X86ISD::CMOV: return "X86ISD::CMOV";
11945 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11946 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11947 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11948 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11949 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11950 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11951 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11952 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11953 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11954 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11955 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11956 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11957 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11958 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11959 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11960 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11961 case X86ISD::BLENDI: return "X86ISD::BLENDI";
11962 case X86ISD::HADD: return "X86ISD::HADD";
11963 case X86ISD::HSUB: return "X86ISD::HSUB";
11964 case X86ISD::FHADD: return "X86ISD::FHADD";
11965 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11966 case X86ISD::FMAX: return "X86ISD::FMAX";
11967 case X86ISD::FMIN: return "X86ISD::FMIN";
11968 case X86ISD::FMAXC: return "X86ISD::FMAXC";
11969 case X86ISD::FMINC: return "X86ISD::FMINC";
11970 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11971 case X86ISD::FRCP: return "X86ISD::FRCP";
11972 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11973 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11974 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11975 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
11976 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
11977 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11978 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11979 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11980 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11981 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11982 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11983 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11984 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11985 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11986 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11987 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11988 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11989 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11990 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
11991 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11992 case X86ISD::VZEXT: return "X86ISD::VZEXT";
11993 case X86ISD::VSEXT: return "X86ISD::VSEXT";
11994 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
11995 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
11996 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11997 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11998 case X86ISD::VSHL: return "X86ISD::VSHL";
11999 case X86ISD::VSRL: return "X86ISD::VSRL";
12000 case X86ISD::VSRA: return "X86ISD::VSRA";
12001 case X86ISD::VSHLI: return "X86ISD::VSHLI";
12002 case X86ISD::VSRLI: return "X86ISD::VSRLI";
12003 case X86ISD::VSRAI: return "X86ISD::VSRAI";
12004 case X86ISD::CMPP: return "X86ISD::CMPP";
12005 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
12006 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
12007 case X86ISD::ADD: return "X86ISD::ADD";
12008 case X86ISD::SUB: return "X86ISD::SUB";
12009 case X86ISD::ADC: return "X86ISD::ADC";
12010 case X86ISD::SBB: return "X86ISD::SBB";
12011 case X86ISD::SMUL: return "X86ISD::SMUL";
12012 case X86ISD::UMUL: return "X86ISD::UMUL";
12013 case X86ISD::INC: return "X86ISD::INC";
12014 case X86ISD::DEC: return "X86ISD::DEC";
12015 case X86ISD::OR: return "X86ISD::OR";
12016 case X86ISD::XOR: return "X86ISD::XOR";
12017 case X86ISD::AND: return "X86ISD::AND";
12018 case X86ISD::ANDN: return "X86ISD::ANDN";
12019 case X86ISD::BLSI: return "X86ISD::BLSI";
12020 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
12021 case X86ISD::BLSR: return "X86ISD::BLSR";
12022 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
12023 case X86ISD::PTEST: return "X86ISD::PTEST";
12024 case X86ISD::TESTP: return "X86ISD::TESTP";
12025 case X86ISD::PALIGN: return "X86ISD::PALIGN";
12026 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
12027 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
12028 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
12029 case X86ISD::SHUFP: return "X86ISD::SHUFP";
12030 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
12031 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
12032 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
12033 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
12034 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
12035 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
12036 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
12037 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
12038 case X86ISD::MOVSD: return "X86ISD::MOVSD";
12039 case X86ISD::MOVSS: return "X86ISD::MOVSS";
12040 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
12041 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
12042 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
12043 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
12044 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
12045 case X86ISD::VPERMV: return "X86ISD::VPERMV";
12046 case X86ISD::VPERMI: return "X86ISD::VPERMI";
12047 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
12048 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
12049 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
12050 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
12051 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
12052 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
12053 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
12054 case X86ISD::SAHF: return "X86ISD::SAHF";
12055 case X86ISD::RDRAND: return "X86ISD::RDRAND";
12056 case X86ISD::FMADD: return "X86ISD::FMADD";
12057 case X86ISD::FMSUB: return "X86ISD::FMSUB";
12058 case X86ISD::FNMADD: return "X86ISD::FNMADD";
12059 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
12060 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
12061 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
12062 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
12063 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
12067 // isLegalAddressingMode - Return true if the addressing mode represented
12068 // by AM is legal for this target, for a load/store of the specified type.
12069 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
12071 // X86 supports extremely general addressing modes.
12072 CodeModel::Model M = getTargetMachine().getCodeModel();
12073 Reloc::Model R = getTargetMachine().getRelocationModel();
12075 // X86 allows a sign-extended 32-bit immediate field as a displacement.
12076 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
12081 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
12083 // If a reference to this global requires an extra load, we can't fold it.
12084 if (isGlobalStubReference(GVFlags))
12087 // If BaseGV requires a register for the PIC base, we cannot also have a
12088 // BaseReg specified.
12089 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
12092 // If lower 4G is not available, then we must use rip-relative addressing.
12093 if ((M != CodeModel::Small || R != Reloc::Static) &&
12094 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
12098 switch (AM.Scale) {
12104 // These scales always work.
12109 // These scales are formed with basereg+scalereg. Only accept if there is
12114 default: // Other stuff never works.
12122 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
12123 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
12125 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
12126 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
12127 if (NumBits1 <= NumBits2)
12132 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
12133 return Imm == (int32_t)Imm;
12136 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
12137 // Can also use sub to handle negated immediates.
12138 return Imm == (int32_t)Imm;
12141 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
12142 if (!VT1.isInteger() || !VT2.isInteger())
12144 unsigned NumBits1 = VT1.getSizeInBits();
12145 unsigned NumBits2 = VT2.getSizeInBits();
12146 if (NumBits1 <= NumBits2)
12151 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
12152 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12153 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
12156 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
12157 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12158 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
12161 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
12162 EVT VT1 = Val.getValueType();
12163 if (isZExtFree(VT1, VT2))
12166 if (Val.getOpcode() != ISD::LOAD)
12169 if (!VT1.isSimple() || !VT1.isInteger() ||
12170 !VT2.isSimple() || !VT2.isInteger())
12173 switch (VT1.getSimpleVT().SimpleTy) {
12178 // X86 has 8, 16, and 32-bit zero-extending loads.
12185 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
12186 // i16 instructions are longer (0x66 prefix) and potentially slower.
12187 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
12190 /// isShuffleMaskLegal - Targets can use this to indicate that they only
12191 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
12192 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
12193 /// are assumed to be legal.
12195 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
12197 // Very little shuffling can be done for 64-bit vectors right now.
12198 if (VT.getSizeInBits() == 64)
12201 // FIXME: pshufb, blends, shifts.
12202 return (VT.getVectorNumElements() == 2 ||
12203 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
12204 isMOVLMask(M, VT) ||
12205 isSHUFPMask(M, VT, Subtarget->hasFp256()) ||
12206 isPSHUFDMask(M, VT) ||
12207 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) ||
12208 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) ||
12209 isPALIGNRMask(M, VT, Subtarget) ||
12210 isUNPCKLMask(M, VT, Subtarget->hasInt256()) ||
12211 isUNPCKHMask(M, VT, Subtarget->hasInt256()) ||
12212 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) ||
12213 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256()));
12217 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
12219 unsigned NumElts = VT.getVectorNumElements();
12220 // FIXME: This collection of masks seems suspect.
12223 if (NumElts == 4 && VT.is128BitVector()) {
12224 return (isMOVLMask(Mask, VT) ||
12225 isCommutedMOVLMask(Mask, VT, true) ||
12226 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) ||
12227 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true));
12232 //===----------------------------------------------------------------------===//
12233 // X86 Scheduler Hooks
12234 //===----------------------------------------------------------------------===//
12236 /// Utility function to emit xbegin specifying the start of an RTM region.
12237 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
12238 const TargetInstrInfo *TII) {
12239 DebugLoc DL = MI->getDebugLoc();
12241 const BasicBlock *BB = MBB->getBasicBlock();
12242 MachineFunction::iterator I = MBB;
12245 // For the v = xbegin(), we generate
12256 MachineBasicBlock *thisMBB = MBB;
12257 MachineFunction *MF = MBB->getParent();
12258 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12259 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12260 MF->insert(I, mainMBB);
12261 MF->insert(I, sinkMBB);
12263 // Transfer the remainder of BB and its successor edges to sinkMBB.
12264 sinkMBB->splice(sinkMBB->begin(), MBB,
12265 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12266 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12270 // # fallthrough to mainMBB
12271 // # abortion to sinkMBB
12272 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
12273 thisMBB->addSuccessor(mainMBB);
12274 thisMBB->addSuccessor(sinkMBB);
12278 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
12279 mainMBB->addSuccessor(sinkMBB);
12282 // EAX is live into the sinkMBB
12283 sinkMBB->addLiveIn(X86::EAX);
12284 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12285 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12288 MI->eraseFromParent();
12292 // Get CMPXCHG opcode for the specified data type.
12293 static unsigned getCmpXChgOpcode(EVT VT) {
12294 switch (VT.getSimpleVT().SimpleTy) {
12295 case MVT::i8: return X86::LCMPXCHG8;
12296 case MVT::i16: return X86::LCMPXCHG16;
12297 case MVT::i32: return X86::LCMPXCHG32;
12298 case MVT::i64: return X86::LCMPXCHG64;
12302 llvm_unreachable("Invalid operand size!");
12305 // Get LOAD opcode for the specified data type.
12306 static unsigned getLoadOpcode(EVT VT) {
12307 switch (VT.getSimpleVT().SimpleTy) {
12308 case MVT::i8: return X86::MOV8rm;
12309 case MVT::i16: return X86::MOV16rm;
12310 case MVT::i32: return X86::MOV32rm;
12311 case MVT::i64: return X86::MOV64rm;
12315 llvm_unreachable("Invalid operand size!");
12318 // Get opcode of the non-atomic one from the specified atomic instruction.
12319 static unsigned getNonAtomicOpcode(unsigned Opc) {
12321 case X86::ATOMAND8: return X86::AND8rr;
12322 case X86::ATOMAND16: return X86::AND16rr;
12323 case X86::ATOMAND32: return X86::AND32rr;
12324 case X86::ATOMAND64: return X86::AND64rr;
12325 case X86::ATOMOR8: return X86::OR8rr;
12326 case X86::ATOMOR16: return X86::OR16rr;
12327 case X86::ATOMOR32: return X86::OR32rr;
12328 case X86::ATOMOR64: return X86::OR64rr;
12329 case X86::ATOMXOR8: return X86::XOR8rr;
12330 case X86::ATOMXOR16: return X86::XOR16rr;
12331 case X86::ATOMXOR32: return X86::XOR32rr;
12332 case X86::ATOMXOR64: return X86::XOR64rr;
12334 llvm_unreachable("Unhandled atomic-load-op opcode!");
12337 // Get opcode of the non-atomic one from the specified atomic instruction with
12339 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
12340 unsigned &ExtraOpc) {
12342 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
12343 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
12344 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
12345 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
12346 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
12347 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
12348 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
12349 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
12350 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
12351 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
12352 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
12353 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
12354 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
12355 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
12356 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
12357 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
12358 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
12359 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
12360 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
12361 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
12363 llvm_unreachable("Unhandled atomic-load-op opcode!");
12366 // Get opcode of the non-atomic one from the specified atomic instruction for
12367 // 64-bit data type on 32-bit target.
12368 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
12370 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
12371 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
12372 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
12373 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
12374 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
12375 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
12376 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
12377 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
12378 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
12379 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
12381 llvm_unreachable("Unhandled atomic-load-op opcode!");
12384 // Get opcode of the non-atomic one from the specified atomic instruction for
12385 // 64-bit data type on 32-bit target with extra opcode.
12386 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
12388 unsigned &ExtraOpc) {
12390 case X86::ATOMNAND6432:
12391 ExtraOpc = X86::NOT32r;
12392 HiOpc = X86::AND32rr;
12393 return X86::AND32rr;
12395 llvm_unreachable("Unhandled atomic-load-op opcode!");
12398 // Get pseudo CMOV opcode from the specified data type.
12399 static unsigned getPseudoCMOVOpc(EVT VT) {
12400 switch (VT.getSimpleVT().SimpleTy) {
12401 case MVT::i8: return X86::CMOV_GR8;
12402 case MVT::i16: return X86::CMOV_GR16;
12403 case MVT::i32: return X86::CMOV_GR32;
12407 llvm_unreachable("Unknown CMOV opcode!");
12410 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
12411 // They will be translated into a spin-loop or compare-exchange loop from
12414 // dst = atomic-fetch-op MI.addr, MI.val
12420 // EAX = LOAD MI.addr
12422 // t1 = OP MI.val, EAX
12423 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12428 MachineBasicBlock *
12429 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
12430 MachineBasicBlock *MBB) const {
12431 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12432 DebugLoc DL = MI->getDebugLoc();
12434 MachineFunction *MF = MBB->getParent();
12435 MachineRegisterInfo &MRI = MF->getRegInfo();
12437 const BasicBlock *BB = MBB->getBasicBlock();
12438 MachineFunction::iterator I = MBB;
12441 assert(MI->getNumOperands() <= X86::AddrNumOperands + 2 &&
12442 "Unexpected number of operands");
12444 assert(MI->hasOneMemOperand() &&
12445 "Expected atomic-load-op to have one memoperand");
12447 // Memory Reference
12448 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12449 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12451 unsigned DstReg, SrcReg;
12452 unsigned MemOpndSlot;
12454 unsigned CurOp = 0;
12456 DstReg = MI->getOperand(CurOp++).getReg();
12457 MemOpndSlot = CurOp;
12458 CurOp += X86::AddrNumOperands;
12459 SrcReg = MI->getOperand(CurOp++).getReg();
12461 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
12462 MVT::SimpleValueType VT = *RC->vt_begin();
12463 unsigned AccPhyReg = getX86SubSuperRegister(X86::EAX, VT);
12465 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
12466 unsigned LOADOpc = getLoadOpcode(VT);
12468 // For the atomic load-arith operator, we generate
12471 // EAX = LOAD [MI.addr]
12473 // t1 = OP MI.val, EAX
12474 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12478 MachineBasicBlock *thisMBB = MBB;
12479 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12480 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12481 MF->insert(I, mainMBB);
12482 MF->insert(I, sinkMBB);
12484 MachineInstrBuilder MIB;
12486 // Transfer the remainder of BB and its successor edges to sinkMBB.
12487 sinkMBB->splice(sinkMBB->begin(), MBB,
12488 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12489 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12492 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), AccPhyReg);
12493 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12494 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12495 MIB.setMemRefs(MMOBegin, MMOEnd);
12497 thisMBB->addSuccessor(mainMBB);
12500 MachineBasicBlock *origMainMBB = mainMBB;
12501 mainMBB->addLiveIn(AccPhyReg);
12503 // Copy AccPhyReg as it is used more than once.
12504 unsigned AccReg = MRI.createVirtualRegister(RC);
12505 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccReg)
12506 .addReg(AccPhyReg);
12508 unsigned t1 = MRI.createVirtualRegister(RC);
12509 unsigned Opc = MI->getOpcode();
12512 llvm_unreachable("Unhandled atomic-load-op opcode!");
12513 case X86::ATOMAND8:
12514 case X86::ATOMAND16:
12515 case X86::ATOMAND32:
12516 case X86::ATOMAND64:
12518 case X86::ATOMOR16:
12519 case X86::ATOMOR32:
12520 case X86::ATOMOR64:
12521 case X86::ATOMXOR8:
12522 case X86::ATOMXOR16:
12523 case X86::ATOMXOR32:
12524 case X86::ATOMXOR64: {
12525 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
12526 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t1).addReg(SrcReg)
12530 case X86::ATOMNAND8:
12531 case X86::ATOMNAND16:
12532 case X86::ATOMNAND32:
12533 case X86::ATOMNAND64: {
12534 unsigned t2 = MRI.createVirtualRegister(RC);
12536 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
12537 BuildMI(mainMBB, DL, TII->get(ANDOpc), t2).addReg(SrcReg)
12539 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2);
12542 case X86::ATOMMAX8:
12543 case X86::ATOMMAX16:
12544 case X86::ATOMMAX32:
12545 case X86::ATOMMAX64:
12546 case X86::ATOMMIN8:
12547 case X86::ATOMMIN16:
12548 case X86::ATOMMIN32:
12549 case X86::ATOMMIN64:
12550 case X86::ATOMUMAX8:
12551 case X86::ATOMUMAX16:
12552 case X86::ATOMUMAX32:
12553 case X86::ATOMUMAX64:
12554 case X86::ATOMUMIN8:
12555 case X86::ATOMUMIN16:
12556 case X86::ATOMUMIN32:
12557 case X86::ATOMUMIN64: {
12559 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
12561 BuildMI(mainMBB, DL, TII->get(CMPOpc))
12565 if (Subtarget->hasCMov()) {
12566 if (VT != MVT::i8) {
12568 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t1)
12572 // Promote i8 to i32 to use CMOV32
12573 const TargetRegisterClass *RC32 = getRegClassFor(MVT::i32);
12574 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
12575 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
12576 unsigned t2 = MRI.createVirtualRegister(RC32);
12578 unsigned Undef = MRI.createVirtualRegister(RC32);
12579 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
12581 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
12584 .addImm(X86::sub_8bit);
12585 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
12588 .addImm(X86::sub_8bit);
12590 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
12594 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t1)
12595 .addReg(t2, 0, X86::sub_8bit);
12598 // Use pseudo select and lower them.
12599 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
12600 "Invalid atomic-load-op transformation!");
12601 unsigned SelOpc = getPseudoCMOVOpc(VT);
12602 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
12603 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
12604 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t1)
12605 .addReg(SrcReg).addReg(AccReg)
12607 mainMBB = EmitLoweredSelect(MIB, mainMBB);
12613 // Copy AccPhyReg back from virtual register.
12614 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccPhyReg)
12617 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
12618 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12619 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12621 MIB.setMemRefs(MMOBegin, MMOEnd);
12623 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
12625 mainMBB->addSuccessor(origMainMBB);
12626 mainMBB->addSuccessor(sinkMBB);
12629 sinkMBB->addLiveIn(AccPhyReg);
12631 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12632 TII->get(TargetOpcode::COPY), DstReg)
12633 .addReg(AccPhyReg);
12635 MI->eraseFromParent();
12639 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
12640 // instructions. They will be translated into a spin-loop or compare-exchange
12644 // dst = atomic-fetch-op MI.addr, MI.val
12650 // EAX = LOAD [MI.addr + 0]
12651 // EDX = LOAD [MI.addr + 4]
12653 // EBX = OP MI.val.lo, EAX
12654 // ECX = OP MI.val.hi, EDX
12655 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
12660 MachineBasicBlock *
12661 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
12662 MachineBasicBlock *MBB) const {
12663 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12664 DebugLoc DL = MI->getDebugLoc();
12666 MachineFunction *MF = MBB->getParent();
12667 MachineRegisterInfo &MRI = MF->getRegInfo();
12669 const BasicBlock *BB = MBB->getBasicBlock();
12670 MachineFunction::iterator I = MBB;
12673 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
12674 "Unexpected number of operands");
12676 assert(MI->hasOneMemOperand() &&
12677 "Expected atomic-load-op32 to have one memoperand");
12679 // Memory Reference
12680 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12681 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12683 unsigned DstLoReg, DstHiReg;
12684 unsigned SrcLoReg, SrcHiReg;
12685 unsigned MemOpndSlot;
12687 unsigned CurOp = 0;
12689 DstLoReg = MI->getOperand(CurOp++).getReg();
12690 DstHiReg = MI->getOperand(CurOp++).getReg();
12691 MemOpndSlot = CurOp;
12692 CurOp += X86::AddrNumOperands;
12693 SrcLoReg = MI->getOperand(CurOp++).getReg();
12694 SrcHiReg = MI->getOperand(CurOp++).getReg();
12696 const TargetRegisterClass *RC = &X86::GR32RegClass;
12697 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
12699 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
12700 unsigned LOADOpc = X86::MOV32rm;
12702 // For the atomic load-arith operator, we generate
12705 // EAX = LOAD [MI.addr + 0]
12706 // EDX = LOAD [MI.addr + 4]
12708 // EBX = OP MI.vallo, EAX
12709 // ECX = OP MI.valhi, EDX
12710 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
12714 MachineBasicBlock *thisMBB = MBB;
12715 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12716 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12717 MF->insert(I, mainMBB);
12718 MF->insert(I, sinkMBB);
12720 MachineInstrBuilder MIB;
12722 // Transfer the remainder of BB and its successor edges to sinkMBB.
12723 sinkMBB->splice(sinkMBB->begin(), MBB,
12724 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12725 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12729 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EAX);
12730 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12731 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12732 MIB.setMemRefs(MMOBegin, MMOEnd);
12734 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX);
12735 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
12736 if (i == X86::AddrDisp)
12737 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
12739 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12741 MIB.setMemRefs(MMOBegin, MMOEnd);
12743 thisMBB->addSuccessor(mainMBB);
12746 MachineBasicBlock *origMainMBB = mainMBB;
12747 mainMBB->addLiveIn(X86::EAX);
12748 mainMBB->addLiveIn(X86::EDX);
12750 // Copy EDX:EAX as they are used more than once.
12751 unsigned LoReg = MRI.createVirtualRegister(RC);
12752 unsigned HiReg = MRI.createVirtualRegister(RC);
12753 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), LoReg).addReg(X86::EAX);
12754 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), HiReg).addReg(X86::EDX);
12756 unsigned t1L = MRI.createVirtualRegister(RC);
12757 unsigned t1H = MRI.createVirtualRegister(RC);
12759 unsigned Opc = MI->getOpcode();
12762 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
12763 case X86::ATOMAND6432:
12764 case X86::ATOMOR6432:
12765 case X86::ATOMXOR6432:
12766 case X86::ATOMADD6432:
12767 case X86::ATOMSUB6432: {
12769 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
12770 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg);
12771 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg);
12774 case X86::ATOMNAND6432: {
12775 unsigned HiOpc, NOTOpc;
12776 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
12777 unsigned t2L = MRI.createVirtualRegister(RC);
12778 unsigned t2H = MRI.createVirtualRegister(RC);
12779 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg).addReg(LoReg);
12780 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg).addReg(HiReg);
12781 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1L).addReg(t2L);
12782 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1H).addReg(t2H);
12785 case X86::ATOMMAX6432:
12786 case X86::ATOMMIN6432:
12787 case X86::ATOMUMAX6432:
12788 case X86::ATOMUMIN6432: {
12790 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
12791 unsigned cL = MRI.createVirtualRegister(RC8);
12792 unsigned cH = MRI.createVirtualRegister(RC8);
12793 unsigned cL32 = MRI.createVirtualRegister(RC);
12794 unsigned cH32 = MRI.createVirtualRegister(RC);
12795 unsigned cc = MRI.createVirtualRegister(RC);
12796 // cl := cmp src_lo, lo
12797 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
12798 .addReg(SrcLoReg).addReg(LoReg);
12799 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
12800 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
12801 // ch := cmp src_hi, hi
12802 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
12803 .addReg(SrcHiReg).addReg(HiReg);
12804 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
12805 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
12806 // cc := if (src_hi == hi) ? cl : ch;
12807 if (Subtarget->hasCMov()) {
12808 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
12809 .addReg(cH32).addReg(cL32);
12811 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
12812 .addReg(cH32).addReg(cL32)
12813 .addImm(X86::COND_E);
12814 mainMBB = EmitLoweredSelect(MIB, mainMBB);
12816 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
12817 if (Subtarget->hasCMov()) {
12818 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1L)
12819 .addReg(SrcLoReg).addReg(LoReg);
12820 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1H)
12821 .addReg(SrcHiReg).addReg(HiReg);
12823 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1L)
12824 .addReg(SrcLoReg).addReg(LoReg)
12825 .addImm(X86::COND_NE);
12826 mainMBB = EmitLoweredSelect(MIB, mainMBB);
12827 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1H)
12828 .addReg(SrcHiReg).addReg(HiReg)
12829 .addImm(X86::COND_NE);
12830 mainMBB = EmitLoweredSelect(MIB, mainMBB);
12834 case X86::ATOMSWAP6432: {
12836 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
12837 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg);
12838 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg);
12843 // Copy EDX:EAX back from HiReg:LoReg
12844 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(LoReg);
12845 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(HiReg);
12846 // Copy ECX:EBX from t1H:t1L
12847 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t1L);
12848 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t1H);
12850 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
12851 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12852 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12853 MIB.setMemRefs(MMOBegin, MMOEnd);
12855 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
12857 mainMBB->addSuccessor(origMainMBB);
12858 mainMBB->addSuccessor(sinkMBB);
12861 sinkMBB->addLiveIn(X86::EAX);
12862 sinkMBB->addLiveIn(X86::EDX);
12864 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12865 TII->get(TargetOpcode::COPY), DstLoReg)
12867 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12868 TII->get(TargetOpcode::COPY), DstHiReg)
12871 MI->eraseFromParent();
12875 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
12876 // or XMM0_V32I8 in AVX all of this code can be replaced with that
12877 // in the .td file.
12878 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
12879 const TargetInstrInfo *TII) {
12881 switch (MI->getOpcode()) {
12882 default: llvm_unreachable("illegal opcode!");
12883 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
12884 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
12885 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
12886 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
12887 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
12888 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
12889 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
12890 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
12893 DebugLoc dl = MI->getDebugLoc();
12894 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
12896 unsigned NumArgs = MI->getNumOperands();
12897 for (unsigned i = 1; i < NumArgs; ++i) {
12898 MachineOperand &Op = MI->getOperand(i);
12899 if (!(Op.isReg() && Op.isImplicit()))
12900 MIB.addOperand(Op);
12902 if (MI->hasOneMemOperand())
12903 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
12905 BuildMI(*BB, MI, dl,
12906 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12907 .addReg(X86::XMM0);
12909 MI->eraseFromParent();
12913 // FIXME: Custom handling because TableGen doesn't support multiple implicit
12914 // defs in an instruction pattern
12915 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
12916 const TargetInstrInfo *TII) {
12918 switch (MI->getOpcode()) {
12919 default: llvm_unreachable("illegal opcode!");
12920 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
12921 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
12922 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
12923 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
12924 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
12925 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
12926 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
12927 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
12930 DebugLoc dl = MI->getDebugLoc();
12931 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
12933 unsigned NumArgs = MI->getNumOperands(); // remove the results
12934 for (unsigned i = 1; i < NumArgs; ++i) {
12935 MachineOperand &Op = MI->getOperand(i);
12936 if (!(Op.isReg() && Op.isImplicit()))
12937 MIB.addOperand(Op);
12939 if (MI->hasOneMemOperand())
12940 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
12942 BuildMI(*BB, MI, dl,
12943 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12946 MI->eraseFromParent();
12950 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
12951 const TargetInstrInfo *TII,
12952 const X86Subtarget* Subtarget) {
12953 DebugLoc dl = MI->getDebugLoc();
12955 // Address into RAX/EAX, other two args into ECX, EDX.
12956 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
12957 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12958 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
12959 for (int i = 0; i < X86::AddrNumOperands; ++i)
12960 MIB.addOperand(MI->getOperand(i));
12962 unsigned ValOps = X86::AddrNumOperands;
12963 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
12964 .addReg(MI->getOperand(ValOps).getReg());
12965 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
12966 .addReg(MI->getOperand(ValOps+1).getReg());
12968 // The instruction doesn't actually take any operands though.
12969 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
12971 MI->eraseFromParent(); // The pseudo is gone now.
12975 MachineBasicBlock *
12976 X86TargetLowering::EmitVAARG64WithCustomInserter(
12978 MachineBasicBlock *MBB) const {
12979 // Emit va_arg instruction on X86-64.
12981 // Operands to this pseudo-instruction:
12982 // 0 ) Output : destination address (reg)
12983 // 1-5) Input : va_list address (addr, i64mem)
12984 // 6 ) ArgSize : Size (in bytes) of vararg type
12985 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
12986 // 8 ) Align : Alignment of type
12987 // 9 ) EFLAGS (implicit-def)
12989 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
12990 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
12992 unsigned DestReg = MI->getOperand(0).getReg();
12993 MachineOperand &Base = MI->getOperand(1);
12994 MachineOperand &Scale = MI->getOperand(2);
12995 MachineOperand &Index = MI->getOperand(3);
12996 MachineOperand &Disp = MI->getOperand(4);
12997 MachineOperand &Segment = MI->getOperand(5);
12998 unsigned ArgSize = MI->getOperand(6).getImm();
12999 unsigned ArgMode = MI->getOperand(7).getImm();
13000 unsigned Align = MI->getOperand(8).getImm();
13002 // Memory Reference
13003 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
13004 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13005 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13007 // Machine Information
13008 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13009 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
13010 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
13011 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
13012 DebugLoc DL = MI->getDebugLoc();
13014 // struct va_list {
13017 // i64 overflow_area (address)
13018 // i64 reg_save_area (address)
13020 // sizeof(va_list) = 24
13021 // alignment(va_list) = 8
13023 unsigned TotalNumIntRegs = 6;
13024 unsigned TotalNumXMMRegs = 8;
13025 bool UseGPOffset = (ArgMode == 1);
13026 bool UseFPOffset = (ArgMode == 2);
13027 unsigned MaxOffset = TotalNumIntRegs * 8 +
13028 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
13030 /* Align ArgSize to a multiple of 8 */
13031 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
13032 bool NeedsAlign = (Align > 8);
13034 MachineBasicBlock *thisMBB = MBB;
13035 MachineBasicBlock *overflowMBB;
13036 MachineBasicBlock *offsetMBB;
13037 MachineBasicBlock *endMBB;
13039 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
13040 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
13041 unsigned OffsetReg = 0;
13043 if (!UseGPOffset && !UseFPOffset) {
13044 // If we only pull from the overflow region, we don't create a branch.
13045 // We don't need to alter control flow.
13046 OffsetDestReg = 0; // unused
13047 OverflowDestReg = DestReg;
13050 overflowMBB = thisMBB;
13053 // First emit code to check if gp_offset (or fp_offset) is below the bound.
13054 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
13055 // If not, pull from overflow_area. (branch to overflowMBB)
13060 // offsetMBB overflowMBB
13065 // Registers for the PHI in endMBB
13066 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
13067 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
13069 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13070 MachineFunction *MF = MBB->getParent();
13071 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13072 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13073 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13075 MachineFunction::iterator MBBIter = MBB;
13078 // Insert the new basic blocks
13079 MF->insert(MBBIter, offsetMBB);
13080 MF->insert(MBBIter, overflowMBB);
13081 MF->insert(MBBIter, endMBB);
13083 // Transfer the remainder of MBB and its successor edges to endMBB.
13084 endMBB->splice(endMBB->begin(), thisMBB,
13085 llvm::next(MachineBasicBlock::iterator(MI)),
13087 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
13089 // Make offsetMBB and overflowMBB successors of thisMBB
13090 thisMBB->addSuccessor(offsetMBB);
13091 thisMBB->addSuccessor(overflowMBB);
13093 // endMBB is a successor of both offsetMBB and overflowMBB
13094 offsetMBB->addSuccessor(endMBB);
13095 overflowMBB->addSuccessor(endMBB);
13097 // Load the offset value into a register
13098 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13099 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
13103 .addDisp(Disp, UseFPOffset ? 4 : 0)
13104 .addOperand(Segment)
13105 .setMemRefs(MMOBegin, MMOEnd);
13107 // Check if there is enough room left to pull this argument.
13108 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
13110 .addImm(MaxOffset + 8 - ArgSizeA8);
13112 // Branch to "overflowMBB" if offset >= max
13113 // Fall through to "offsetMBB" otherwise
13114 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
13115 .addMBB(overflowMBB);
13118 // In offsetMBB, emit code to use the reg_save_area.
13120 assert(OffsetReg != 0);
13122 // Read the reg_save_area address.
13123 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
13124 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
13129 .addOperand(Segment)
13130 .setMemRefs(MMOBegin, MMOEnd);
13132 // Zero-extend the offset
13133 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
13134 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
13137 .addImm(X86::sub_32bit);
13139 // Add the offset to the reg_save_area to get the final address.
13140 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
13141 .addReg(OffsetReg64)
13142 .addReg(RegSaveReg);
13144 // Compute the offset for the next argument
13145 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13146 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
13148 .addImm(UseFPOffset ? 16 : 8);
13150 // Store it back into the va_list.
13151 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
13155 .addDisp(Disp, UseFPOffset ? 4 : 0)
13156 .addOperand(Segment)
13157 .addReg(NextOffsetReg)
13158 .setMemRefs(MMOBegin, MMOEnd);
13161 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
13166 // Emit code to use overflow area
13169 // Load the overflow_area address into a register.
13170 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
13171 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
13176 .addOperand(Segment)
13177 .setMemRefs(MMOBegin, MMOEnd);
13179 // If we need to align it, do so. Otherwise, just copy the address
13180 // to OverflowDestReg.
13182 // Align the overflow address
13183 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
13184 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
13186 // aligned_addr = (addr + (align-1)) & ~(align-1)
13187 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
13188 .addReg(OverflowAddrReg)
13191 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
13193 .addImm(~(uint64_t)(Align-1));
13195 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
13196 .addReg(OverflowAddrReg);
13199 // Compute the next overflow address after this argument.
13200 // (the overflow address should be kept 8-byte aligned)
13201 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
13202 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
13203 .addReg(OverflowDestReg)
13204 .addImm(ArgSizeA8);
13206 // Store the new overflow address.
13207 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
13212 .addOperand(Segment)
13213 .addReg(NextAddrReg)
13214 .setMemRefs(MMOBegin, MMOEnd);
13216 // If we branched, emit the PHI to the front of endMBB.
13218 BuildMI(*endMBB, endMBB->begin(), DL,
13219 TII->get(X86::PHI), DestReg)
13220 .addReg(OffsetDestReg).addMBB(offsetMBB)
13221 .addReg(OverflowDestReg).addMBB(overflowMBB);
13224 // Erase the pseudo instruction
13225 MI->eraseFromParent();
13230 MachineBasicBlock *
13231 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
13233 MachineBasicBlock *MBB) const {
13234 // Emit code to save XMM registers to the stack. The ABI says that the
13235 // number of registers to save is given in %al, so it's theoretically
13236 // possible to do an indirect jump trick to avoid saving all of them,
13237 // however this code takes a simpler approach and just executes all
13238 // of the stores if %al is non-zero. It's less code, and it's probably
13239 // easier on the hardware branch predictor, and stores aren't all that
13240 // expensive anyway.
13242 // Create the new basic blocks. One block contains all the XMM stores,
13243 // and one block is the final destination regardless of whether any
13244 // stores were performed.
13245 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13246 MachineFunction *F = MBB->getParent();
13247 MachineFunction::iterator MBBIter = MBB;
13249 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
13250 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
13251 F->insert(MBBIter, XMMSaveMBB);
13252 F->insert(MBBIter, EndMBB);
13254 // Transfer the remainder of MBB and its successor edges to EndMBB.
13255 EndMBB->splice(EndMBB->begin(), MBB,
13256 llvm::next(MachineBasicBlock::iterator(MI)),
13258 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
13260 // The original block will now fall through to the XMM save block.
13261 MBB->addSuccessor(XMMSaveMBB);
13262 // The XMMSaveMBB will fall through to the end block.
13263 XMMSaveMBB->addSuccessor(EndMBB);
13265 // Now add the instructions.
13266 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13267 DebugLoc DL = MI->getDebugLoc();
13269 unsigned CountReg = MI->getOperand(0).getReg();
13270 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
13271 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
13273 if (!Subtarget->isTargetWin64()) {
13274 // If %al is 0, branch around the XMM save block.
13275 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
13276 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
13277 MBB->addSuccessor(EndMBB);
13280 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
13281 // In the XMM save block, save all the XMM argument registers.
13282 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
13283 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
13284 MachineMemOperand *MMO =
13285 F->getMachineMemOperand(
13286 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
13287 MachineMemOperand::MOStore,
13288 /*Size=*/16, /*Align=*/16);
13289 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
13290 .addFrameIndex(RegSaveFrameIndex)
13291 .addImm(/*Scale=*/1)
13292 .addReg(/*IndexReg=*/0)
13293 .addImm(/*Disp=*/Offset)
13294 .addReg(/*Segment=*/0)
13295 .addReg(MI->getOperand(i).getReg())
13296 .addMemOperand(MMO);
13299 MI->eraseFromParent(); // The pseudo instruction is gone now.
13304 // The EFLAGS operand of SelectItr might be missing a kill marker
13305 // because there were multiple uses of EFLAGS, and ISel didn't know
13306 // which to mark. Figure out whether SelectItr should have had a
13307 // kill marker, and set it if it should. Returns the correct kill
13309 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
13310 MachineBasicBlock* BB,
13311 const TargetRegisterInfo* TRI) {
13312 // Scan forward through BB for a use/def of EFLAGS.
13313 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
13314 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
13315 const MachineInstr& mi = *miI;
13316 if (mi.readsRegister(X86::EFLAGS))
13318 if (mi.definesRegister(X86::EFLAGS))
13319 break; // Should have kill-flag - update below.
13322 // If we hit the end of the block, check whether EFLAGS is live into a
13324 if (miI == BB->end()) {
13325 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
13326 sEnd = BB->succ_end();
13327 sItr != sEnd; ++sItr) {
13328 MachineBasicBlock* succ = *sItr;
13329 if (succ->isLiveIn(X86::EFLAGS))
13334 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
13335 // out. SelectMI should have a kill flag on EFLAGS.
13336 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
13340 MachineBasicBlock *
13341 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
13342 MachineBasicBlock *BB) const {
13343 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13344 DebugLoc DL = MI->getDebugLoc();
13346 // To "insert" a SELECT_CC instruction, we actually have to insert the
13347 // diamond control-flow pattern. The incoming instruction knows the
13348 // destination vreg to set, the condition code register to branch on, the
13349 // true/false values to select between, and a branch opcode to use.
13350 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13351 MachineFunction::iterator It = BB;
13357 // cmpTY ccX, r1, r2
13359 // fallthrough --> copy0MBB
13360 MachineBasicBlock *thisMBB = BB;
13361 MachineFunction *F = BB->getParent();
13362 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
13363 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
13364 F->insert(It, copy0MBB);
13365 F->insert(It, sinkMBB);
13367 // If the EFLAGS register isn't dead in the terminator, then claim that it's
13368 // live into the sink and copy blocks.
13369 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13370 if (!MI->killsRegister(X86::EFLAGS) &&
13371 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
13372 copy0MBB->addLiveIn(X86::EFLAGS);
13373 sinkMBB->addLiveIn(X86::EFLAGS);
13376 // Transfer the remainder of BB and its successor edges to sinkMBB.
13377 sinkMBB->splice(sinkMBB->begin(), BB,
13378 llvm::next(MachineBasicBlock::iterator(MI)),
13380 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
13382 // Add the true and fallthrough blocks as its successors.
13383 BB->addSuccessor(copy0MBB);
13384 BB->addSuccessor(sinkMBB);
13386 // Create the conditional branch instruction.
13388 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
13389 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
13392 // %FalseValue = ...
13393 // # fallthrough to sinkMBB
13394 copy0MBB->addSuccessor(sinkMBB);
13397 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
13399 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13400 TII->get(X86::PHI), MI->getOperand(0).getReg())
13401 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
13402 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
13404 MI->eraseFromParent(); // The pseudo instruction is gone now.
13408 MachineBasicBlock *
13409 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
13410 bool Is64Bit) const {
13411 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13412 DebugLoc DL = MI->getDebugLoc();
13413 MachineFunction *MF = BB->getParent();
13414 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13416 assert(getTargetMachine().Options.EnableSegmentedStacks);
13418 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
13419 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
13422 // ... [Till the alloca]
13423 // If stacklet is not large enough, jump to mallocMBB
13426 // Allocate by subtracting from RSP
13427 // Jump to continueMBB
13430 // Allocate by call to runtime
13434 // [rest of original BB]
13437 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13438 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13439 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13441 MachineRegisterInfo &MRI = MF->getRegInfo();
13442 const TargetRegisterClass *AddrRegClass =
13443 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
13445 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13446 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13447 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
13448 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
13449 sizeVReg = MI->getOperand(1).getReg(),
13450 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
13452 MachineFunction::iterator MBBIter = BB;
13455 MF->insert(MBBIter, bumpMBB);
13456 MF->insert(MBBIter, mallocMBB);
13457 MF->insert(MBBIter, continueMBB);
13459 continueMBB->splice(continueMBB->begin(), BB, llvm::next
13460 (MachineBasicBlock::iterator(MI)), BB->end());
13461 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
13463 // Add code to the main basic block to check if the stack limit has been hit,
13464 // and if so, jump to mallocMBB otherwise to bumpMBB.
13465 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
13466 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
13467 .addReg(tmpSPVReg).addReg(sizeVReg);
13468 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
13469 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
13470 .addReg(SPLimitVReg);
13471 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
13473 // bumpMBB simply decreases the stack pointer, since we know the current
13474 // stacklet has enough space.
13475 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
13476 .addReg(SPLimitVReg);
13477 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
13478 .addReg(SPLimitVReg);
13479 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13481 // Calls into a routine in libgcc to allocate more space from the heap.
13482 const uint32_t *RegMask =
13483 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13485 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
13487 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
13488 .addExternalSymbol("__morestack_allocate_stack_space")
13489 .addRegMask(RegMask)
13490 .addReg(X86::RDI, RegState::Implicit)
13491 .addReg(X86::RAX, RegState::ImplicitDefine);
13493 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
13495 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
13496 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
13497 .addExternalSymbol("__morestack_allocate_stack_space")
13498 .addRegMask(RegMask)
13499 .addReg(X86::EAX, RegState::ImplicitDefine);
13503 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
13506 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
13507 .addReg(Is64Bit ? X86::RAX : X86::EAX);
13508 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13510 // Set up the CFG correctly.
13511 BB->addSuccessor(bumpMBB);
13512 BB->addSuccessor(mallocMBB);
13513 mallocMBB->addSuccessor(continueMBB);
13514 bumpMBB->addSuccessor(continueMBB);
13516 // Take care of the PHI nodes.
13517 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
13518 MI->getOperand(0).getReg())
13519 .addReg(mallocPtrVReg).addMBB(mallocMBB)
13520 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
13522 // Delete the original pseudo instruction.
13523 MI->eraseFromParent();
13526 return continueMBB;
13529 MachineBasicBlock *
13530 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
13531 MachineBasicBlock *BB) const {
13532 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13533 DebugLoc DL = MI->getDebugLoc();
13535 assert(!Subtarget->isTargetEnvMacho());
13537 // The lowering is pretty easy: we're just emitting the call to _alloca. The
13538 // non-trivial part is impdef of ESP.
13540 if (Subtarget->isTargetWin64()) {
13541 if (Subtarget->isTargetCygMing()) {
13542 // ___chkstk(Mingw64):
13543 // Clobbers R10, R11, RAX and EFLAGS.
13545 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
13546 .addExternalSymbol("___chkstk")
13547 .addReg(X86::RAX, RegState::Implicit)
13548 .addReg(X86::RSP, RegState::Implicit)
13549 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
13550 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
13551 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13553 // __chkstk(MSVCRT): does not update stack pointer.
13554 // Clobbers R10, R11 and EFLAGS.
13555 // FIXME: RAX(allocated size) might be reused and not killed.
13556 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
13557 .addExternalSymbol("__chkstk")
13558 .addReg(X86::RAX, RegState::Implicit)
13559 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13560 // RAX has the offset to subtracted from RSP.
13561 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
13566 const char *StackProbeSymbol =
13567 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
13569 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
13570 .addExternalSymbol(StackProbeSymbol)
13571 .addReg(X86::EAX, RegState::Implicit)
13572 .addReg(X86::ESP, RegState::Implicit)
13573 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
13574 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
13575 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13578 MI->eraseFromParent(); // The pseudo instruction is gone now.
13582 MachineBasicBlock *
13583 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
13584 MachineBasicBlock *BB) const {
13585 // This is pretty easy. We're taking the value that we received from
13586 // our load from the relocation, sticking it in either RDI (x86-64)
13587 // or EAX and doing an indirect call. The return value will then
13588 // be in the normal return register.
13589 const X86InstrInfo *TII
13590 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
13591 DebugLoc DL = MI->getDebugLoc();
13592 MachineFunction *F = BB->getParent();
13594 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
13595 assert(MI->getOperand(3).isGlobal() && "This should be a global");
13597 // Get a register mask for the lowered call.
13598 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
13599 // proper register mask.
13600 const uint32_t *RegMask =
13601 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13602 if (Subtarget->is64Bit()) {
13603 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13604 TII->get(X86::MOV64rm), X86::RDI)
13606 .addImm(0).addReg(0)
13607 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13608 MI->getOperand(3).getTargetFlags())
13610 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
13611 addDirectMem(MIB, X86::RDI);
13612 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
13613 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
13614 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13615 TII->get(X86::MOV32rm), X86::EAX)
13617 .addImm(0).addReg(0)
13618 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13619 MI->getOperand(3).getTargetFlags())
13621 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
13622 addDirectMem(MIB, X86::EAX);
13623 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
13625 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13626 TII->get(X86::MOV32rm), X86::EAX)
13627 .addReg(TII->getGlobalBaseReg(F))
13628 .addImm(0).addReg(0)
13629 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13630 MI->getOperand(3).getTargetFlags())
13632 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
13633 addDirectMem(MIB, X86::EAX);
13634 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
13637 MI->eraseFromParent(); // The pseudo instruction is gone now.
13641 MachineBasicBlock *
13642 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
13643 MachineBasicBlock *MBB) const {
13644 DebugLoc DL = MI->getDebugLoc();
13645 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13647 MachineFunction *MF = MBB->getParent();
13648 MachineRegisterInfo &MRI = MF->getRegInfo();
13650 const BasicBlock *BB = MBB->getBasicBlock();
13651 MachineFunction::iterator I = MBB;
13654 // Memory Reference
13655 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13656 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13659 unsigned MemOpndSlot = 0;
13661 unsigned CurOp = 0;
13663 DstReg = MI->getOperand(CurOp++).getReg();
13664 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
13665 assert(RC->hasType(MVT::i32) && "Invalid destination!");
13666 unsigned mainDstReg = MRI.createVirtualRegister(RC);
13667 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
13669 MemOpndSlot = CurOp;
13671 MVT PVT = getPointerTy();
13672 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
13673 "Invalid Pointer Size!");
13675 // For v = setjmp(buf), we generate
13678 // buf[LabelOffset] = restoreMBB
13679 // SjLjSetup restoreMBB
13685 // v = phi(main, restore)
13690 MachineBasicBlock *thisMBB = MBB;
13691 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13692 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13693 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
13694 MF->insert(I, mainMBB);
13695 MF->insert(I, sinkMBB);
13696 MF->push_back(restoreMBB);
13698 MachineInstrBuilder MIB;
13700 // Transfer the remainder of BB and its successor edges to sinkMBB.
13701 sinkMBB->splice(sinkMBB->begin(), MBB,
13702 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13703 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13706 unsigned PtrStoreOpc = 0;
13707 unsigned LabelReg = 0;
13708 const int64_t LabelOffset = 1 * PVT.getStoreSize();
13709 Reloc::Model RM = getTargetMachine().getRelocationModel();
13710 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
13711 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
13713 // Prepare IP either in reg or imm.
13714 if (!UseImmLabel) {
13715 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
13716 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
13717 LabelReg = MRI.createVirtualRegister(PtrRC);
13718 if (Subtarget->is64Bit()) {
13719 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
13723 .addMBB(restoreMBB)
13726 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
13727 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
13728 .addReg(XII->getGlobalBaseReg(MF))
13731 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
13735 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
13737 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
13738 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13739 if (i == X86::AddrDisp)
13740 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
13742 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13745 MIB.addReg(LabelReg);
13747 MIB.addMBB(restoreMBB);
13748 MIB.setMemRefs(MMOBegin, MMOEnd);
13750 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
13751 .addMBB(restoreMBB);
13752 MIB.addRegMask(RegInfo->getNoPreservedMask());
13753 thisMBB->addSuccessor(mainMBB);
13754 thisMBB->addSuccessor(restoreMBB);
13758 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
13759 mainMBB->addSuccessor(sinkMBB);
13762 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13763 TII->get(X86::PHI), DstReg)
13764 .addReg(mainDstReg).addMBB(mainMBB)
13765 .addReg(restoreDstReg).addMBB(restoreMBB);
13768 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
13769 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
13770 restoreMBB->addSuccessor(sinkMBB);
13772 MI->eraseFromParent();
13776 MachineBasicBlock *
13777 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
13778 MachineBasicBlock *MBB) const {
13779 DebugLoc DL = MI->getDebugLoc();
13780 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13782 MachineFunction *MF = MBB->getParent();
13783 MachineRegisterInfo &MRI = MF->getRegInfo();
13785 // Memory Reference
13786 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13787 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13789 MVT PVT = getPointerTy();
13790 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
13791 "Invalid Pointer Size!");
13793 const TargetRegisterClass *RC =
13794 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
13795 unsigned Tmp = MRI.createVirtualRegister(RC);
13796 // Since FP is only updated here but NOT referenced, it's treated as GPR.
13797 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
13798 unsigned SP = RegInfo->getStackRegister();
13800 MachineInstrBuilder MIB;
13802 const int64_t LabelOffset = 1 * PVT.getStoreSize();
13803 const int64_t SPOffset = 2 * PVT.getStoreSize();
13805 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
13806 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
13809 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
13810 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13811 MIB.addOperand(MI->getOperand(i));
13812 MIB.setMemRefs(MMOBegin, MMOEnd);
13814 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
13815 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13816 if (i == X86::AddrDisp)
13817 MIB.addDisp(MI->getOperand(i), LabelOffset);
13819 MIB.addOperand(MI->getOperand(i));
13821 MIB.setMemRefs(MMOBegin, MMOEnd);
13823 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
13824 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13825 if (i == X86::AddrDisp)
13826 MIB.addDisp(MI->getOperand(i), SPOffset);
13828 MIB.addOperand(MI->getOperand(i));
13830 MIB.setMemRefs(MMOBegin, MMOEnd);
13832 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
13834 MI->eraseFromParent();
13838 MachineBasicBlock *
13839 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
13840 MachineBasicBlock *BB) const {
13841 switch (MI->getOpcode()) {
13842 default: llvm_unreachable("Unexpected instr type to insert");
13843 case X86::TAILJMPd64:
13844 case X86::TAILJMPr64:
13845 case X86::TAILJMPm64:
13846 llvm_unreachable("TAILJMP64 would not be touched here.");
13847 case X86::TCRETURNdi64:
13848 case X86::TCRETURNri64:
13849 case X86::TCRETURNmi64:
13851 case X86::WIN_ALLOCA:
13852 return EmitLoweredWinAlloca(MI, BB);
13853 case X86::SEG_ALLOCA_32:
13854 return EmitLoweredSegAlloca(MI, BB, false);
13855 case X86::SEG_ALLOCA_64:
13856 return EmitLoweredSegAlloca(MI, BB, true);
13857 case X86::TLSCall_32:
13858 case X86::TLSCall_64:
13859 return EmitLoweredTLSCall(MI, BB);
13860 case X86::CMOV_GR8:
13861 case X86::CMOV_FR32:
13862 case X86::CMOV_FR64:
13863 case X86::CMOV_V4F32:
13864 case X86::CMOV_V2F64:
13865 case X86::CMOV_V2I64:
13866 case X86::CMOV_V8F32:
13867 case X86::CMOV_V4F64:
13868 case X86::CMOV_V4I64:
13869 case X86::CMOV_GR16:
13870 case X86::CMOV_GR32:
13871 case X86::CMOV_RFP32:
13872 case X86::CMOV_RFP64:
13873 case X86::CMOV_RFP80:
13874 return EmitLoweredSelect(MI, BB);
13876 case X86::FP32_TO_INT16_IN_MEM:
13877 case X86::FP32_TO_INT32_IN_MEM:
13878 case X86::FP32_TO_INT64_IN_MEM:
13879 case X86::FP64_TO_INT16_IN_MEM:
13880 case X86::FP64_TO_INT32_IN_MEM:
13881 case X86::FP64_TO_INT64_IN_MEM:
13882 case X86::FP80_TO_INT16_IN_MEM:
13883 case X86::FP80_TO_INT32_IN_MEM:
13884 case X86::FP80_TO_INT64_IN_MEM: {
13885 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13886 DebugLoc DL = MI->getDebugLoc();
13888 // Change the floating point control register to use "round towards zero"
13889 // mode when truncating to an integer value.
13890 MachineFunction *F = BB->getParent();
13891 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
13892 addFrameReference(BuildMI(*BB, MI, DL,
13893 TII->get(X86::FNSTCW16m)), CWFrameIdx);
13895 // Load the old value of the high byte of the control word...
13897 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
13898 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
13901 // Set the high part to be round to zero...
13902 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
13905 // Reload the modified control word now...
13906 addFrameReference(BuildMI(*BB, MI, DL,
13907 TII->get(X86::FLDCW16m)), CWFrameIdx);
13909 // Restore the memory image of control word to original value
13910 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
13913 // Get the X86 opcode to use.
13915 switch (MI->getOpcode()) {
13916 default: llvm_unreachable("illegal opcode!");
13917 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
13918 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
13919 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
13920 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
13921 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
13922 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
13923 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
13924 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
13925 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
13929 MachineOperand &Op = MI->getOperand(0);
13931 AM.BaseType = X86AddressMode::RegBase;
13932 AM.Base.Reg = Op.getReg();
13934 AM.BaseType = X86AddressMode::FrameIndexBase;
13935 AM.Base.FrameIndex = Op.getIndex();
13937 Op = MI->getOperand(1);
13939 AM.Scale = Op.getImm();
13940 Op = MI->getOperand(2);
13942 AM.IndexReg = Op.getImm();
13943 Op = MI->getOperand(3);
13944 if (Op.isGlobal()) {
13945 AM.GV = Op.getGlobal();
13947 AM.Disp = Op.getImm();
13949 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
13950 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
13952 // Reload the original control word now.
13953 addFrameReference(BuildMI(*BB, MI, DL,
13954 TII->get(X86::FLDCW16m)), CWFrameIdx);
13956 MI->eraseFromParent(); // The pseudo instruction is gone now.
13959 // String/text processing lowering.
13960 case X86::PCMPISTRM128REG:
13961 case X86::VPCMPISTRM128REG:
13962 case X86::PCMPISTRM128MEM:
13963 case X86::VPCMPISTRM128MEM:
13964 case X86::PCMPESTRM128REG:
13965 case X86::VPCMPESTRM128REG:
13966 case X86::PCMPESTRM128MEM:
13967 case X86::VPCMPESTRM128MEM:
13968 assert(Subtarget->hasSSE42() &&
13969 "Target must have SSE4.2 or AVX features enabled");
13970 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
13972 // String/text processing lowering.
13973 case X86::PCMPISTRIREG:
13974 case X86::VPCMPISTRIREG:
13975 case X86::PCMPISTRIMEM:
13976 case X86::VPCMPISTRIMEM:
13977 case X86::PCMPESTRIREG:
13978 case X86::VPCMPESTRIREG:
13979 case X86::PCMPESTRIMEM:
13980 case X86::VPCMPESTRIMEM:
13981 assert(Subtarget->hasSSE42() &&
13982 "Target must have SSE4.2 or AVX features enabled");
13983 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
13985 // Thread synchronization.
13987 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
13991 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
13993 // Atomic Lowering.
13994 case X86::ATOMAND8:
13995 case X86::ATOMAND16:
13996 case X86::ATOMAND32:
13997 case X86::ATOMAND64:
14000 case X86::ATOMOR16:
14001 case X86::ATOMOR32:
14002 case X86::ATOMOR64:
14004 case X86::ATOMXOR16:
14005 case X86::ATOMXOR8:
14006 case X86::ATOMXOR32:
14007 case X86::ATOMXOR64:
14009 case X86::ATOMNAND8:
14010 case X86::ATOMNAND16:
14011 case X86::ATOMNAND32:
14012 case X86::ATOMNAND64:
14014 case X86::ATOMMAX8:
14015 case X86::ATOMMAX16:
14016 case X86::ATOMMAX32:
14017 case X86::ATOMMAX64:
14019 case X86::ATOMMIN8:
14020 case X86::ATOMMIN16:
14021 case X86::ATOMMIN32:
14022 case X86::ATOMMIN64:
14024 case X86::ATOMUMAX8:
14025 case X86::ATOMUMAX16:
14026 case X86::ATOMUMAX32:
14027 case X86::ATOMUMAX64:
14029 case X86::ATOMUMIN8:
14030 case X86::ATOMUMIN16:
14031 case X86::ATOMUMIN32:
14032 case X86::ATOMUMIN64:
14033 return EmitAtomicLoadArith(MI, BB);
14035 // This group does 64-bit operations on a 32-bit host.
14036 case X86::ATOMAND6432:
14037 case X86::ATOMOR6432:
14038 case X86::ATOMXOR6432:
14039 case X86::ATOMNAND6432:
14040 case X86::ATOMADD6432:
14041 case X86::ATOMSUB6432:
14042 case X86::ATOMMAX6432:
14043 case X86::ATOMMIN6432:
14044 case X86::ATOMUMAX6432:
14045 case X86::ATOMUMIN6432:
14046 case X86::ATOMSWAP6432:
14047 return EmitAtomicLoadArith6432(MI, BB);
14049 case X86::VASTART_SAVE_XMM_REGS:
14050 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
14052 case X86::VAARG_64:
14053 return EmitVAARG64WithCustomInserter(MI, BB);
14055 case X86::EH_SjLj_SetJmp32:
14056 case X86::EH_SjLj_SetJmp64:
14057 return emitEHSjLjSetJmp(MI, BB);
14059 case X86::EH_SjLj_LongJmp32:
14060 case X86::EH_SjLj_LongJmp64:
14061 return emitEHSjLjLongJmp(MI, BB);
14065 //===----------------------------------------------------------------------===//
14066 // X86 Optimization Hooks
14067 //===----------------------------------------------------------------------===//
14069 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
14072 const SelectionDAG &DAG,
14073 unsigned Depth) const {
14074 unsigned BitWidth = KnownZero.getBitWidth();
14075 unsigned Opc = Op.getOpcode();
14076 assert((Opc >= ISD::BUILTIN_OP_END ||
14077 Opc == ISD::INTRINSIC_WO_CHAIN ||
14078 Opc == ISD::INTRINSIC_W_CHAIN ||
14079 Opc == ISD::INTRINSIC_VOID) &&
14080 "Should use MaskedValueIsZero if you don't know whether Op"
14081 " is a target node!");
14083 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
14097 // These nodes' second result is a boolean.
14098 if (Op.getResNo() == 0)
14101 case X86ISD::SETCC:
14102 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
14104 case ISD::INTRINSIC_WO_CHAIN: {
14105 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14106 unsigned NumLoBits = 0;
14109 case Intrinsic::x86_sse_movmsk_ps:
14110 case Intrinsic::x86_avx_movmsk_ps_256:
14111 case Intrinsic::x86_sse2_movmsk_pd:
14112 case Intrinsic::x86_avx_movmsk_pd_256:
14113 case Intrinsic::x86_mmx_pmovmskb:
14114 case Intrinsic::x86_sse2_pmovmskb_128:
14115 case Intrinsic::x86_avx2_pmovmskb: {
14116 // High bits of movmskp{s|d}, pmovmskb are known zero.
14118 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14119 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
14120 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
14121 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
14122 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
14123 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
14124 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
14125 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
14127 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
14136 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
14137 unsigned Depth) const {
14138 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
14139 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
14140 return Op.getValueType().getScalarType().getSizeInBits();
14146 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
14147 /// node is a GlobalAddress + offset.
14148 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
14149 const GlobalValue* &GA,
14150 int64_t &Offset) const {
14151 if (N->getOpcode() == X86ISD::Wrapper) {
14152 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
14153 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
14154 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
14158 return TargetLowering::isGAPlusOffset(N, GA, Offset);
14161 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
14162 /// same as extracting the high 128-bit part of 256-bit vector and then
14163 /// inserting the result into the low part of a new 256-bit vector
14164 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
14165 EVT VT = SVOp->getValueType(0);
14166 unsigned NumElems = VT.getVectorNumElements();
14168 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14169 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
14170 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14171 SVOp->getMaskElt(j) >= 0)
14177 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
14178 /// same as extracting the low 128-bit part of 256-bit vector and then
14179 /// inserting the result into the high part of a new 256-bit vector
14180 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
14181 EVT VT = SVOp->getValueType(0);
14182 unsigned NumElems = VT.getVectorNumElements();
14184 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14185 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
14186 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14187 SVOp->getMaskElt(j) >= 0)
14193 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
14194 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
14195 TargetLowering::DAGCombinerInfo &DCI,
14196 const X86Subtarget* Subtarget) {
14197 DebugLoc dl = N->getDebugLoc();
14198 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
14199 SDValue V1 = SVOp->getOperand(0);
14200 SDValue V2 = SVOp->getOperand(1);
14201 EVT VT = SVOp->getValueType(0);
14202 unsigned NumElems = VT.getVectorNumElements();
14204 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
14205 V2.getOpcode() == ISD::CONCAT_VECTORS) {
14209 // V UNDEF BUILD_VECTOR UNDEF
14211 // CONCAT_VECTOR CONCAT_VECTOR
14214 // RESULT: V + zero extended
14216 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
14217 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
14218 V1.getOperand(1).getOpcode() != ISD::UNDEF)
14221 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
14224 // To match the shuffle mask, the first half of the mask should
14225 // be exactly the first vector, and all the rest a splat with the
14226 // first element of the second one.
14227 for (unsigned i = 0; i != NumElems/2; ++i)
14228 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
14229 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
14232 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
14233 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
14234 if (Ld->hasNUsesOfValue(1, 0)) {
14235 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
14236 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
14238 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
14240 Ld->getPointerInfo(),
14241 Ld->getAlignment(),
14242 false/*isVolatile*/, true/*ReadMem*/,
14243 false/*WriteMem*/);
14245 // Make sure the newly-created LOAD is in the same position as Ld in
14246 // terms of dependency. We create a TokenFactor for Ld and ResNode,
14247 // and update uses of Ld's output chain to use the TokenFactor.
14248 if (Ld->hasAnyUseOfValue(1)) {
14249 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
14250 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
14251 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
14252 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
14253 SDValue(ResNode.getNode(), 1));
14256 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
14260 // Emit a zeroed vector and insert the desired subvector on its
14262 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
14263 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
14264 return DCI.CombineTo(N, InsV);
14267 //===--------------------------------------------------------------------===//
14268 // Combine some shuffles into subvector extracts and inserts:
14271 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14272 if (isShuffleHigh128VectorInsertLow(SVOp)) {
14273 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
14274 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
14275 return DCI.CombineTo(N, InsV);
14278 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14279 if (isShuffleLow128VectorInsertHigh(SVOp)) {
14280 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
14281 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
14282 return DCI.CombineTo(N, InsV);
14288 /// PerformShuffleCombine - Performs several different shuffle combines.
14289 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
14290 TargetLowering::DAGCombinerInfo &DCI,
14291 const X86Subtarget *Subtarget) {
14292 DebugLoc dl = N->getDebugLoc();
14293 EVT VT = N->getValueType(0);
14295 // Don't create instructions with illegal types after legalize types has run.
14296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14297 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
14300 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
14301 if (Subtarget->hasFp256() && VT.is256BitVector() &&
14302 N->getOpcode() == ISD::VECTOR_SHUFFLE)
14303 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
14305 // Only handle 128 wide vector from here on.
14306 if (!VT.is128BitVector())
14309 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
14310 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
14311 // consecutive, non-overlapping, and in the right order.
14312 SmallVector<SDValue, 16> Elts;
14313 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
14314 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
14316 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
14320 /// PerformTruncateCombine - Converts truncate operation to
14321 /// a sequence of vector shuffle operations.
14322 /// It is possible when we truncate 256-bit vector to 128-bit vector
14323 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
14324 TargetLowering::DAGCombinerInfo &DCI,
14325 const X86Subtarget *Subtarget) {
14326 if (!DCI.isBeforeLegalizeOps())
14329 if (!Subtarget->hasFp256())
14332 EVT VT = N->getValueType(0);
14333 SDValue Op = N->getOperand(0);
14334 EVT OpVT = Op.getValueType();
14335 DebugLoc dl = N->getDebugLoc();
14337 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
14339 if (Subtarget->hasInt256()) {
14340 // AVX2: v4i64 -> v4i32
14343 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14345 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
14346 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
14349 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
14350 DAG.getIntPtrConstant(0));
14353 // AVX: v4i64 -> v4i32
14354 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
14355 DAG.getIntPtrConstant(0));
14357 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
14358 DAG.getIntPtrConstant(2));
14360 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
14361 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
14364 static const int ShufMask1[] = {0, 2, 0, 0};
14366 SDValue Undef = DAG.getUNDEF(VT);
14367 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, Undef, ShufMask1);
14368 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, Undef, ShufMask1);
14371 static const int ShufMask2[] = {0, 1, 4, 5};
14373 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
14376 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
14378 if (Subtarget->hasInt256()) {
14379 // AVX2: v8i32 -> v8i16
14381 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
14384 SmallVector<SDValue,32> pshufbMask;
14385 for (unsigned i = 0; i < 2; ++i) {
14386 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14387 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14388 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14389 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14390 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14391 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14392 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14393 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14394 for (unsigned j = 0; j < 8; ++j)
14395 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14397 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
14398 &pshufbMask[0], 32);
14399 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
14401 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
14403 static const int ShufMask[] = {0, 2, -1, -1};
14404 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
14407 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
14408 DAG.getIntPtrConstant(0));
14410 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
14413 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
14414 DAG.getIntPtrConstant(0));
14416 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
14417 DAG.getIntPtrConstant(4));
14419 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
14420 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
14423 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14424 -1, -1, -1, -1, -1, -1, -1, -1};
14426 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14427 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, Undef, ShufMask1);
14428 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, Undef, ShufMask1);
14430 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
14431 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
14434 static const int ShufMask2[] = {0, 1, 4, 5};
14436 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
14437 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
14443 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
14444 /// specific shuffle of a load can be folded into a single element load.
14445 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
14446 /// shuffles have been customed lowered so we need to handle those here.
14447 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
14448 TargetLowering::DAGCombinerInfo &DCI) {
14449 if (DCI.isBeforeLegalizeOps())
14452 SDValue InVec = N->getOperand(0);
14453 SDValue EltNo = N->getOperand(1);
14455 if (!isa<ConstantSDNode>(EltNo))
14458 EVT VT = InVec.getValueType();
14460 bool HasShuffleIntoBitcast = false;
14461 if (InVec.getOpcode() == ISD::BITCAST) {
14462 // Don't duplicate a load with other uses.
14463 if (!InVec.hasOneUse())
14465 EVT BCVT = InVec.getOperand(0).getValueType();
14466 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
14468 InVec = InVec.getOperand(0);
14469 HasShuffleIntoBitcast = true;
14472 if (!isTargetShuffle(InVec.getOpcode()))
14475 // Don't duplicate a load with other uses.
14476 if (!InVec.hasOneUse())
14479 SmallVector<int, 16> ShuffleMask;
14481 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
14485 // Select the input vector, guarding against out of range extract vector.
14486 unsigned NumElems = VT.getVectorNumElements();
14487 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
14488 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
14489 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
14490 : InVec.getOperand(1);
14492 // If inputs to shuffle are the same for both ops, then allow 2 uses
14493 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
14495 if (LdNode.getOpcode() == ISD::BITCAST) {
14496 // Don't duplicate a load with other uses.
14497 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
14500 AllowedUses = 1; // only allow 1 load use if we have a bitcast
14501 LdNode = LdNode.getOperand(0);
14504 if (!ISD::isNormalLoad(LdNode.getNode()))
14507 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
14509 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
14512 if (HasShuffleIntoBitcast) {
14513 // If there's a bitcast before the shuffle, check if the load type and
14514 // alignment is valid.
14515 unsigned Align = LN0->getAlignment();
14516 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14517 unsigned NewAlign = TLI.getDataLayout()->
14518 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
14520 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
14524 // All checks match so transform back to vector_shuffle so that DAG combiner
14525 // can finish the job
14526 DebugLoc dl = N->getDebugLoc();
14528 // Create shuffle node taking into account the case that its a unary shuffle
14529 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
14530 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
14531 InVec.getOperand(0), Shuffle,
14533 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
14534 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
14538 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
14539 /// generation and convert it from being a bunch of shuffles and extracts
14540 /// to a simple store and scalar loads to extract the elements.
14541 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
14542 TargetLowering::DAGCombinerInfo &DCI) {
14543 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
14544 if (NewOp.getNode())
14547 SDValue InputVector = N->getOperand(0);
14548 // Detect whether we are trying to convert from mmx to i32 and the bitcast
14549 // from mmx to v2i32 has a single usage.
14550 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
14551 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
14552 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
14553 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(),
14554 N->getValueType(0),
14555 InputVector.getNode()->getOperand(0));
14557 // Only operate on vectors of 4 elements, where the alternative shuffling
14558 // gets to be more expensive.
14559 if (InputVector.getValueType() != MVT::v4i32)
14562 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
14563 // single use which is a sign-extend or zero-extend, and all elements are
14565 SmallVector<SDNode *, 4> Uses;
14566 unsigned ExtractedElements = 0;
14567 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
14568 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
14569 if (UI.getUse().getResNo() != InputVector.getResNo())
14572 SDNode *Extract = *UI;
14573 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14576 if (Extract->getValueType(0) != MVT::i32)
14578 if (!Extract->hasOneUse())
14580 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
14581 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
14583 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
14586 // Record which element was extracted.
14587 ExtractedElements |=
14588 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
14590 Uses.push_back(Extract);
14593 // If not all the elements were used, this may not be worthwhile.
14594 if (ExtractedElements != 15)
14597 // Ok, we've now decided to do the transformation.
14598 DebugLoc dl = InputVector.getDebugLoc();
14600 // Store the value to a temporary stack slot.
14601 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
14602 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
14603 MachinePointerInfo(), false, false, 0);
14605 // Replace each use (extract) with a load of the appropriate element.
14606 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
14607 UE = Uses.end(); UI != UE; ++UI) {
14608 SDNode *Extract = *UI;
14610 // cOMpute the element's address.
14611 SDValue Idx = Extract->getOperand(1);
14613 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
14614 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
14615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14616 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
14618 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
14619 StackPtr, OffsetVal);
14621 // Load the scalar.
14622 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
14623 ScalarAddr, MachinePointerInfo(),
14624 false, false, false, 0);
14626 // Replace the exact with the load.
14627 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
14630 // The replacement was made in place; don't return anything.
14634 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
14636 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
14637 TargetLowering::DAGCombinerInfo &DCI,
14638 const X86Subtarget *Subtarget) {
14639 DebugLoc DL = N->getDebugLoc();
14640 SDValue Cond = N->getOperand(0);
14641 // Get the LHS/RHS of the select.
14642 SDValue LHS = N->getOperand(1);
14643 SDValue RHS = N->getOperand(2);
14644 EVT VT = LHS.getValueType();
14646 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
14647 // instructions match the semantics of the common C idiom x<y?x:y but not
14648 // x<=y?x:y, because of how they handle negative zero (which can be
14649 // ignored in unsafe-math mode).
14650 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
14651 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
14652 (Subtarget->hasSSE2() ||
14653 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
14654 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14656 unsigned Opcode = 0;
14657 // Check for x CC y ? x : y.
14658 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
14659 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
14663 // Converting this to a min would handle NaNs incorrectly, and swapping
14664 // the operands would cause it to handle comparisons between positive
14665 // and negative zero incorrectly.
14666 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
14667 if (!DAG.getTarget().Options.UnsafeFPMath &&
14668 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
14670 std::swap(LHS, RHS);
14672 Opcode = X86ISD::FMIN;
14675 // Converting this to a min would handle comparisons between positive
14676 // and negative zero incorrectly.
14677 if (!DAG.getTarget().Options.UnsafeFPMath &&
14678 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
14680 Opcode = X86ISD::FMIN;
14683 // Converting this to a min would handle both negative zeros and NaNs
14684 // incorrectly, but we can swap the operands to fix both.
14685 std::swap(LHS, RHS);
14689 Opcode = X86ISD::FMIN;
14693 // Converting this to a max would handle comparisons between positive
14694 // and negative zero incorrectly.
14695 if (!DAG.getTarget().Options.UnsafeFPMath &&
14696 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
14698 Opcode = X86ISD::FMAX;
14701 // Converting this to a max would handle NaNs incorrectly, and swapping
14702 // the operands would cause it to handle comparisons between positive
14703 // and negative zero incorrectly.
14704 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
14705 if (!DAG.getTarget().Options.UnsafeFPMath &&
14706 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
14708 std::swap(LHS, RHS);
14710 Opcode = X86ISD::FMAX;
14713 // Converting this to a max would handle both negative zeros and NaNs
14714 // incorrectly, but we can swap the operands to fix both.
14715 std::swap(LHS, RHS);
14719 Opcode = X86ISD::FMAX;
14722 // Check for x CC y ? y : x -- a min/max with reversed arms.
14723 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
14724 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
14728 // Converting this to a min would handle comparisons between positive
14729 // and negative zero incorrectly, and swapping the operands would
14730 // cause it to handle NaNs incorrectly.
14731 if (!DAG.getTarget().Options.UnsafeFPMath &&
14732 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
14733 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
14735 std::swap(LHS, RHS);
14737 Opcode = X86ISD::FMIN;
14740 // Converting this to a min would handle NaNs incorrectly.
14741 if (!DAG.getTarget().Options.UnsafeFPMath &&
14742 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
14744 Opcode = X86ISD::FMIN;
14747 // Converting this to a min would handle both negative zeros and NaNs
14748 // incorrectly, but we can swap the operands to fix both.
14749 std::swap(LHS, RHS);
14753 Opcode = X86ISD::FMIN;
14757 // Converting this to a max would handle NaNs incorrectly.
14758 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
14760 Opcode = X86ISD::FMAX;
14763 // Converting this to a max would handle comparisons between positive
14764 // and negative zero incorrectly, and swapping the operands would
14765 // cause it to handle NaNs incorrectly.
14766 if (!DAG.getTarget().Options.UnsafeFPMath &&
14767 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
14768 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
14770 std::swap(LHS, RHS);
14772 Opcode = X86ISD::FMAX;
14775 // Converting this to a max would handle both negative zeros and NaNs
14776 // incorrectly, but we can swap the operands to fix both.
14777 std::swap(LHS, RHS);
14781 Opcode = X86ISD::FMAX;
14787 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
14790 // If this is a select between two integer constants, try to do some
14792 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
14793 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
14794 // Don't do this for crazy integer types.
14795 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
14796 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
14797 // so that TrueC (the true value) is larger than FalseC.
14798 bool NeedsCondInvert = false;
14800 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
14801 // Efficiently invertible.
14802 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
14803 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
14804 isa<ConstantSDNode>(Cond.getOperand(1))))) {
14805 NeedsCondInvert = true;
14806 std::swap(TrueC, FalseC);
14809 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
14810 if (FalseC->getAPIntValue() == 0 &&
14811 TrueC->getAPIntValue().isPowerOf2()) {
14812 if (NeedsCondInvert) // Invert the condition if needed.
14813 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
14814 DAG.getConstant(1, Cond.getValueType()));
14816 // Zero extend the condition if needed.
14817 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
14819 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
14820 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
14821 DAG.getConstant(ShAmt, MVT::i8));
14824 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
14825 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
14826 if (NeedsCondInvert) // Invert the condition if needed.
14827 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
14828 DAG.getConstant(1, Cond.getValueType()));
14830 // Zero extend the condition if needed.
14831 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
14832 FalseC->getValueType(0), Cond);
14833 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
14834 SDValue(FalseC, 0));
14837 // Optimize cases that will turn into an LEA instruction. This requires
14838 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
14839 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
14840 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
14841 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
14843 bool isFastMultiplier = false;
14845 switch ((unsigned char)Diff) {
14847 case 1: // result = add base, cond
14848 case 2: // result = lea base( , cond*2)
14849 case 3: // result = lea base(cond, cond*2)
14850 case 4: // result = lea base( , cond*4)
14851 case 5: // result = lea base(cond, cond*4)
14852 case 8: // result = lea base( , cond*8)
14853 case 9: // result = lea base(cond, cond*8)
14854 isFastMultiplier = true;
14859 if (isFastMultiplier) {
14860 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
14861 if (NeedsCondInvert) // Invert the condition if needed.
14862 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
14863 DAG.getConstant(1, Cond.getValueType()));
14865 // Zero extend the condition if needed.
14866 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
14868 // Scale the condition by the difference.
14870 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
14871 DAG.getConstant(Diff, Cond.getValueType()));
14873 // Add the base if non-zero.
14874 if (FalseC->getAPIntValue() != 0)
14875 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
14876 SDValue(FalseC, 0));
14883 // Canonicalize max and min:
14884 // (x > y) ? x : y -> (x >= y) ? x : y
14885 // (x < y) ? x : y -> (x <= y) ? x : y
14886 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
14887 // the need for an extra compare
14888 // against zero. e.g.
14889 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
14891 // testl %edi, %edi
14893 // cmovgl %edi, %eax
14897 // cmovsl %eax, %edi
14898 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
14899 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
14900 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
14901 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14906 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
14907 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
14908 Cond.getOperand(0), Cond.getOperand(1), NewCC);
14909 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
14914 // If we know that this node is legal then we know that it is going to be
14915 // matched by one of the SSE/AVX BLEND instructions. These instructions only
14916 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
14917 // to simplify previous instructions.
14918 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14919 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
14920 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
14921 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
14923 // Don't optimize vector selects that map to mask-registers.
14927 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
14928 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
14930 APInt KnownZero, KnownOne;
14931 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
14932 DCI.isBeforeLegalizeOps());
14933 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
14934 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
14935 DCI.CommitTargetLoweringOpt(TLO);
14941 // Check whether a boolean test is testing a boolean value generated by
14942 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
14945 // Simplify the following patterns:
14946 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
14947 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
14948 // to (Op EFLAGS Cond)
14950 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
14951 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
14952 // to (Op EFLAGS !Cond)
14954 // where Op could be BRCOND or CMOV.
14956 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
14957 // Quit if not CMP and SUB with its value result used.
14958 if (Cmp.getOpcode() != X86ISD::CMP &&
14959 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
14962 // Quit if not used as a boolean value.
14963 if (CC != X86::COND_E && CC != X86::COND_NE)
14966 // Check CMP operands. One of them should be 0 or 1 and the other should be
14967 // an SetCC or extended from it.
14968 SDValue Op1 = Cmp.getOperand(0);
14969 SDValue Op2 = Cmp.getOperand(1);
14972 const ConstantSDNode* C = 0;
14973 bool needOppositeCond = (CC == X86::COND_E);
14975 if ((C = dyn_cast<ConstantSDNode>(Op1)))
14977 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
14979 else // Quit if all operands are not constants.
14982 if (C->getZExtValue() == 1)
14983 needOppositeCond = !needOppositeCond;
14984 else if (C->getZExtValue() != 0)
14985 // Quit if the constant is neither 0 or 1.
14988 // Skip 'zext' node.
14989 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
14990 SetCC = SetCC.getOperand(0);
14992 switch (SetCC.getOpcode()) {
14993 case X86ISD::SETCC:
14994 // Set the condition code or opposite one if necessary.
14995 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
14996 if (needOppositeCond)
14997 CC = X86::GetOppositeBranchCondition(CC);
14998 return SetCC.getOperand(1);
14999 case X86ISD::CMOV: {
15000 // Check whether false/true value has canonical one, i.e. 0 or 1.
15001 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
15002 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
15003 // Quit if true value is not a constant.
15006 // Quit if false value is not a constant.
15008 // A special case for rdrand, where 0 is set if false cond is found.
15009 SDValue Op = SetCC.getOperand(0);
15010 if (Op.getOpcode() != X86ISD::RDRAND)
15013 // Quit if false value is not the constant 0 or 1.
15014 bool FValIsFalse = true;
15015 if (FVal && FVal->getZExtValue() != 0) {
15016 if (FVal->getZExtValue() != 1)
15018 // If FVal is 1, opposite cond is needed.
15019 needOppositeCond = !needOppositeCond;
15020 FValIsFalse = false;
15022 // Quit if TVal is not the constant opposite of FVal.
15023 if (FValIsFalse && TVal->getZExtValue() != 1)
15025 if (!FValIsFalse && TVal->getZExtValue() != 0)
15027 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
15028 if (needOppositeCond)
15029 CC = X86::GetOppositeBranchCondition(CC);
15030 return SetCC.getOperand(3);
15037 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
15038 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
15039 TargetLowering::DAGCombinerInfo &DCI,
15040 const X86Subtarget *Subtarget) {
15041 DebugLoc DL = N->getDebugLoc();
15043 // If the flag operand isn't dead, don't touch this CMOV.
15044 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
15047 SDValue FalseOp = N->getOperand(0);
15048 SDValue TrueOp = N->getOperand(1);
15049 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
15050 SDValue Cond = N->getOperand(3);
15052 if (CC == X86::COND_E || CC == X86::COND_NE) {
15053 switch (Cond.getOpcode()) {
15057 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
15058 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
15059 return (CC == X86::COND_E) ? FalseOp : TrueOp;
15065 Flags = checkBoolTestSetCCCombine(Cond, CC);
15066 if (Flags.getNode() &&
15067 // Extra check as FCMOV only supports a subset of X86 cond.
15068 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
15069 SDValue Ops[] = { FalseOp, TrueOp,
15070 DAG.getConstant(CC, MVT::i8), Flags };
15071 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
15072 Ops, array_lengthof(Ops));
15075 // If this is a select between two integer constants, try to do some
15076 // optimizations. Note that the operands are ordered the opposite of SELECT
15078 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
15079 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
15080 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
15081 // larger than FalseC (the false value).
15082 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
15083 CC = X86::GetOppositeBranchCondition(CC);
15084 std::swap(TrueC, FalseC);
15085 std::swap(TrueOp, FalseOp);
15088 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
15089 // This is efficient for any integer data type (including i8/i16) and
15091 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
15092 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15093 DAG.getConstant(CC, MVT::i8), Cond);
15095 // Zero extend the condition if needed.
15096 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
15098 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15099 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
15100 DAG.getConstant(ShAmt, MVT::i8));
15101 if (N->getNumValues() == 2) // Dead flag value?
15102 return DCI.CombineTo(N, Cond, SDValue());
15106 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
15107 // for any integer data type, including i8/i16.
15108 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15109 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15110 DAG.getConstant(CC, MVT::i8), Cond);
15112 // Zero extend the condition if needed.
15113 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15114 FalseC->getValueType(0), Cond);
15115 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15116 SDValue(FalseC, 0));
15118 if (N->getNumValues() == 2) // Dead flag value?
15119 return DCI.CombineTo(N, Cond, SDValue());
15123 // Optimize cases that will turn into an LEA instruction. This requires
15124 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15125 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15126 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15127 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15129 bool isFastMultiplier = false;
15131 switch ((unsigned char)Diff) {
15133 case 1: // result = add base, cond
15134 case 2: // result = lea base( , cond*2)
15135 case 3: // result = lea base(cond, cond*2)
15136 case 4: // result = lea base( , cond*4)
15137 case 5: // result = lea base(cond, cond*4)
15138 case 8: // result = lea base( , cond*8)
15139 case 9: // result = lea base(cond, cond*8)
15140 isFastMultiplier = true;
15145 if (isFastMultiplier) {
15146 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15147 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15148 DAG.getConstant(CC, MVT::i8), Cond);
15149 // Zero extend the condition if needed.
15150 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15152 // Scale the condition by the difference.
15154 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15155 DAG.getConstant(Diff, Cond.getValueType()));
15157 // Add the base if non-zero.
15158 if (FalseC->getAPIntValue() != 0)
15159 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15160 SDValue(FalseC, 0));
15161 if (N->getNumValues() == 2) // Dead flag value?
15162 return DCI.CombineTo(N, Cond, SDValue());
15169 // Handle these cases:
15170 // (select (x != c), e, c) -> select (x != c), e, x),
15171 // (select (x == c), c, e) -> select (x == c), x, e)
15172 // where the c is an integer constant, and the "select" is the combination
15173 // of CMOV and CMP.
15175 // The rationale for this change is that the conditional-move from a constant
15176 // needs two instructions, however, conditional-move from a register needs
15177 // only one instruction.
15179 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
15180 // some instruction-combining opportunities. This opt needs to be
15181 // postponed as late as possible.
15183 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
15184 // the DCI.xxxx conditions are provided to postpone the optimization as
15185 // late as possible.
15187 ConstantSDNode *CmpAgainst = 0;
15188 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
15189 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
15190 dyn_cast<ConstantSDNode>(Cond.getOperand(0)) == 0) {
15192 if (CC == X86::COND_NE &&
15193 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
15194 CC = X86::GetOppositeBranchCondition(CC);
15195 std::swap(TrueOp, FalseOp);
15198 if (CC == X86::COND_E &&
15199 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
15200 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
15201 DAG.getConstant(CC, MVT::i8), Cond };
15202 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
15203 array_lengthof(Ops));
15212 /// PerformMulCombine - Optimize a single multiply with constant into two
15213 /// in order to implement it with two cheaper instructions, e.g.
15214 /// LEA + SHL, LEA + LEA.
15215 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
15216 TargetLowering::DAGCombinerInfo &DCI) {
15217 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
15220 EVT VT = N->getValueType(0);
15221 if (VT != MVT::i64)
15224 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
15227 uint64_t MulAmt = C->getZExtValue();
15228 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
15231 uint64_t MulAmt1 = 0;
15232 uint64_t MulAmt2 = 0;
15233 if ((MulAmt % 9) == 0) {
15235 MulAmt2 = MulAmt / 9;
15236 } else if ((MulAmt % 5) == 0) {
15238 MulAmt2 = MulAmt / 5;
15239 } else if ((MulAmt % 3) == 0) {
15241 MulAmt2 = MulAmt / 3;
15244 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
15245 DebugLoc DL = N->getDebugLoc();
15247 if (isPowerOf2_64(MulAmt2) &&
15248 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
15249 // If second multiplifer is pow2, issue it first. We want the multiply by
15250 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
15252 std::swap(MulAmt1, MulAmt2);
15255 if (isPowerOf2_64(MulAmt1))
15256 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
15257 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
15259 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
15260 DAG.getConstant(MulAmt1, VT));
15262 if (isPowerOf2_64(MulAmt2))
15263 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
15264 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
15266 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
15267 DAG.getConstant(MulAmt2, VT));
15269 // Do not add new nodes to DAG combiner worklist.
15270 DCI.CombineTo(N, NewMul, false);
15275 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
15276 SDValue N0 = N->getOperand(0);
15277 SDValue N1 = N->getOperand(1);
15278 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
15279 EVT VT = N0.getValueType();
15281 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
15282 // since the result of setcc_c is all zero's or all ones.
15283 if (VT.isInteger() && !VT.isVector() &&
15284 N1C && N0.getOpcode() == ISD::AND &&
15285 N0.getOperand(1).getOpcode() == ISD::Constant) {
15286 SDValue N00 = N0.getOperand(0);
15287 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
15288 ((N00.getOpcode() == ISD::ANY_EXTEND ||
15289 N00.getOpcode() == ISD::ZERO_EXTEND) &&
15290 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
15291 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
15292 APInt ShAmt = N1C->getAPIntValue();
15293 Mask = Mask.shl(ShAmt);
15295 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
15296 N00, DAG.getConstant(Mask, VT));
15301 // Hardware support for vector shifts is sparse which makes us scalarize the
15302 // vector operations in many cases. Also, on sandybridge ADD is faster than
15304 // (shl V, 1) -> add V,V
15305 if (isSplatVector(N1.getNode())) {
15306 assert(N0.getValueType().isVector() && "Invalid vector shift type");
15307 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
15308 // We shift all of the values by one. In many cases we do not have
15309 // hardware support for this operation. This is better expressed as an ADD
15311 if (N1C && (1 == N1C->getZExtValue())) {
15312 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
15319 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
15321 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
15322 TargetLowering::DAGCombinerInfo &DCI,
15323 const X86Subtarget *Subtarget) {
15324 EVT VT = N->getValueType(0);
15325 if (N->getOpcode() == ISD::SHL) {
15326 SDValue V = PerformSHLCombine(N, DAG);
15327 if (V.getNode()) return V;
15330 // On X86 with SSE2 support, we can transform this to a vector shift if
15331 // all elements are shifted by the same amount. We can't do this in legalize
15332 // because the a constant vector is typically transformed to a constant pool
15333 // so we have no knowledge of the shift amount.
15334 if (!Subtarget->hasSSE2())
15337 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
15338 (!Subtarget->hasInt256() ||
15339 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
15342 SDValue ShAmtOp = N->getOperand(1);
15343 EVT EltVT = VT.getVectorElementType();
15344 DebugLoc DL = N->getDebugLoc();
15345 SDValue BaseShAmt = SDValue();
15346 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
15347 unsigned NumElts = VT.getVectorNumElements();
15349 for (; i != NumElts; ++i) {
15350 SDValue Arg = ShAmtOp.getOperand(i);
15351 if (Arg.getOpcode() == ISD::UNDEF) continue;
15355 // Handle the case where the build_vector is all undef
15356 // FIXME: Should DAG allow this?
15360 for (; i != NumElts; ++i) {
15361 SDValue Arg = ShAmtOp.getOperand(i);
15362 if (Arg.getOpcode() == ISD::UNDEF) continue;
15363 if (Arg != BaseShAmt) {
15367 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
15368 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
15369 SDValue InVec = ShAmtOp.getOperand(0);
15370 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15371 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15373 for (; i != NumElts; ++i) {
15374 SDValue Arg = InVec.getOperand(i);
15375 if (Arg.getOpcode() == ISD::UNDEF) continue;
15379 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15380 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15381 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
15382 if (C->getZExtValue() == SplatIdx)
15383 BaseShAmt = InVec.getOperand(1);
15386 if (BaseShAmt.getNode() == 0) {
15387 // Don't create instructions with illegal types after legalize
15389 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
15390 !DCI.isBeforeLegalize())
15393 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
15394 DAG.getIntPtrConstant(0));
15399 // The shift amount is an i32.
15400 if (EltVT.bitsGT(MVT::i32))
15401 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
15402 else if (EltVT.bitsLT(MVT::i32))
15403 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
15405 // The shift amount is identical so we can do a vector shift.
15406 SDValue ValOp = N->getOperand(0);
15407 switch (N->getOpcode()) {
15409 llvm_unreachable("Unknown shift opcode!");
15411 switch (VT.getSimpleVT().SimpleTy) {
15412 default: return SDValue();
15419 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
15422 switch (VT.getSimpleVT().SimpleTy) {
15423 default: return SDValue();
15428 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
15431 switch (VT.getSimpleVT().SimpleTy) {
15432 default: return SDValue();
15439 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
15445 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
15446 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
15447 // and friends. Likewise for OR -> CMPNEQSS.
15448 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
15449 TargetLowering::DAGCombinerInfo &DCI,
15450 const X86Subtarget *Subtarget) {
15453 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
15454 // we're requiring SSE2 for both.
15455 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
15456 SDValue N0 = N->getOperand(0);
15457 SDValue N1 = N->getOperand(1);
15458 SDValue CMP0 = N0->getOperand(1);
15459 SDValue CMP1 = N1->getOperand(1);
15460 DebugLoc DL = N->getDebugLoc();
15462 // The SETCCs should both refer to the same CMP.
15463 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
15466 SDValue CMP00 = CMP0->getOperand(0);
15467 SDValue CMP01 = CMP0->getOperand(1);
15468 EVT VT = CMP00.getValueType();
15470 if (VT == MVT::f32 || VT == MVT::f64) {
15471 bool ExpectingFlags = false;
15472 // Check for any users that want flags:
15473 for (SDNode::use_iterator UI = N->use_begin(),
15475 !ExpectingFlags && UI != UE; ++UI)
15476 switch (UI->getOpcode()) {
15481 ExpectingFlags = true;
15483 case ISD::CopyToReg:
15484 case ISD::SIGN_EXTEND:
15485 case ISD::ZERO_EXTEND:
15486 case ISD::ANY_EXTEND:
15490 if (!ExpectingFlags) {
15491 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
15492 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
15494 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
15495 X86::CondCode tmp = cc0;
15500 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
15501 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
15502 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
15503 X86ISD::NodeType NTOperator = is64BitFP ?
15504 X86ISD::FSETCCsd : X86ISD::FSETCCss;
15505 // FIXME: need symbolic constants for these magic numbers.
15506 // See X86ATTInstPrinter.cpp:printSSECC().
15507 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
15508 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
15509 DAG.getConstant(x86cc, MVT::i8));
15510 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
15512 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
15513 DAG.getConstant(1, MVT::i32));
15514 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
15515 return OneBitOfTruth;
15523 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
15524 /// so it can be folded inside ANDNP.
15525 static bool CanFoldXORWithAllOnes(const SDNode *N) {
15526 EVT VT = N->getValueType(0);
15528 // Match direct AllOnes for 128 and 256-bit vectors
15529 if (ISD::isBuildVectorAllOnes(N))
15532 // Look through a bit convert.
15533 if (N->getOpcode() == ISD::BITCAST)
15534 N = N->getOperand(0).getNode();
15536 // Sometimes the operand may come from a insert_subvector building a 256-bit
15538 if (VT.is256BitVector() &&
15539 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
15540 SDValue V1 = N->getOperand(0);
15541 SDValue V2 = N->getOperand(1);
15543 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
15544 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
15545 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
15546 ISD::isBuildVectorAllOnes(V2.getNode()))
15553 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
15554 TargetLowering::DAGCombinerInfo &DCI,
15555 const X86Subtarget *Subtarget) {
15556 if (DCI.isBeforeLegalizeOps())
15559 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
15563 EVT VT = N->getValueType(0);
15565 // Create ANDN, BLSI, and BLSR instructions
15566 // BLSI is X & (-X)
15567 // BLSR is X & (X-1)
15568 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
15569 SDValue N0 = N->getOperand(0);
15570 SDValue N1 = N->getOperand(1);
15571 DebugLoc DL = N->getDebugLoc();
15573 // Check LHS for not
15574 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
15575 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
15576 // Check RHS for not
15577 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
15578 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
15580 // Check LHS for neg
15581 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
15582 isZero(N0.getOperand(0)))
15583 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
15585 // Check RHS for neg
15586 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
15587 isZero(N1.getOperand(0)))
15588 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
15590 // Check LHS for X-1
15591 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
15592 isAllOnes(N0.getOperand(1)))
15593 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
15595 // Check RHS for X-1
15596 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
15597 isAllOnes(N1.getOperand(1)))
15598 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
15603 // Want to form ANDNP nodes:
15604 // 1) In the hopes of then easily combining them with OR and AND nodes
15605 // to form PBLEND/PSIGN.
15606 // 2) To match ANDN packed intrinsics
15607 if (VT != MVT::v2i64 && VT != MVT::v4i64)
15610 SDValue N0 = N->getOperand(0);
15611 SDValue N1 = N->getOperand(1);
15612 DebugLoc DL = N->getDebugLoc();
15614 // Check LHS for vnot
15615 if (N0.getOpcode() == ISD::XOR &&
15616 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
15617 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
15618 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
15620 // Check RHS for vnot
15621 if (N1.getOpcode() == ISD::XOR &&
15622 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
15623 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
15624 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
15629 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
15630 TargetLowering::DAGCombinerInfo &DCI,
15631 const X86Subtarget *Subtarget) {
15632 if (DCI.isBeforeLegalizeOps())
15635 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
15639 EVT VT = N->getValueType(0);
15641 SDValue N0 = N->getOperand(0);
15642 SDValue N1 = N->getOperand(1);
15644 // look for psign/blend
15645 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
15646 if (!Subtarget->hasSSSE3() ||
15647 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
15650 // Canonicalize pandn to RHS
15651 if (N0.getOpcode() == X86ISD::ANDNP)
15653 // or (and (m, y), (pandn m, x))
15654 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
15655 SDValue Mask = N1.getOperand(0);
15656 SDValue X = N1.getOperand(1);
15658 if (N0.getOperand(0) == Mask)
15659 Y = N0.getOperand(1);
15660 if (N0.getOperand(1) == Mask)
15661 Y = N0.getOperand(0);
15663 // Check to see if the mask appeared in both the AND and ANDNP and
15667 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
15668 // Look through mask bitcast.
15669 if (Mask.getOpcode() == ISD::BITCAST)
15670 Mask = Mask.getOperand(0);
15671 if (X.getOpcode() == ISD::BITCAST)
15672 X = X.getOperand(0);
15673 if (Y.getOpcode() == ISD::BITCAST)
15674 Y = Y.getOperand(0);
15676 EVT MaskVT = Mask.getValueType();
15678 // Validate that the Mask operand is a vector sra node.
15679 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
15680 // there is no psrai.b
15681 if (Mask.getOpcode() != X86ISD::VSRAI)
15684 // Check that the SRA is all signbits.
15685 SDValue SraC = Mask.getOperand(1);
15686 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
15687 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
15688 if ((SraAmt + 1) != EltBits)
15691 DebugLoc DL = N->getDebugLoc();
15693 // We are going to replace the AND, OR, NAND with either BLEND
15694 // or PSIGN, which only look at the MSB. The VSRAI instruction
15695 // does not affect the highest bit, so we can get rid of it.
15696 Mask = Mask.getOperand(0);
15698 // Now we know we at least have a plendvb with the mask val. See if
15699 // we can form a psignb/w/d.
15700 // psign = x.type == y.type == mask.type && y = sub(0, x);
15701 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
15702 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
15703 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
15704 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
15705 "Unsupported VT for PSIGN");
15706 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask);
15707 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
15709 // PBLENDVB only available on SSE 4.1
15710 if (!Subtarget->hasSSE41())
15713 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
15715 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
15716 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
15717 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
15718 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
15719 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
15723 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
15726 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
15727 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
15729 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
15731 if (!N0.hasOneUse() || !N1.hasOneUse())
15734 SDValue ShAmt0 = N0.getOperand(1);
15735 if (ShAmt0.getValueType() != MVT::i8)
15737 SDValue ShAmt1 = N1.getOperand(1);
15738 if (ShAmt1.getValueType() != MVT::i8)
15740 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
15741 ShAmt0 = ShAmt0.getOperand(0);
15742 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
15743 ShAmt1 = ShAmt1.getOperand(0);
15745 DebugLoc DL = N->getDebugLoc();
15746 unsigned Opc = X86ISD::SHLD;
15747 SDValue Op0 = N0.getOperand(0);
15748 SDValue Op1 = N1.getOperand(0);
15749 if (ShAmt0.getOpcode() == ISD::SUB) {
15750 Opc = X86ISD::SHRD;
15751 std::swap(Op0, Op1);
15752 std::swap(ShAmt0, ShAmt1);
15755 unsigned Bits = VT.getSizeInBits();
15756 if (ShAmt1.getOpcode() == ISD::SUB) {
15757 SDValue Sum = ShAmt1.getOperand(0);
15758 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
15759 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
15760 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
15761 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
15762 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
15763 return DAG.getNode(Opc, DL, VT,
15765 DAG.getNode(ISD::TRUNCATE, DL,
15768 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
15769 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
15771 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
15772 return DAG.getNode(Opc, DL, VT,
15773 N0.getOperand(0), N1.getOperand(0),
15774 DAG.getNode(ISD::TRUNCATE, DL,
15781 // Generate NEG and CMOV for integer abs.
15782 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
15783 EVT VT = N->getValueType(0);
15785 // Since X86 does not have CMOV for 8-bit integer, we don't convert
15786 // 8-bit integer abs to NEG and CMOV.
15787 if (VT.isInteger() && VT.getSizeInBits() == 8)
15790 SDValue N0 = N->getOperand(0);
15791 SDValue N1 = N->getOperand(1);
15792 DebugLoc DL = N->getDebugLoc();
15794 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
15795 // and change it to SUB and CMOV.
15796 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
15797 N0.getOpcode() == ISD::ADD &&
15798 N0.getOperand(1) == N1 &&
15799 N1.getOpcode() == ISD::SRA &&
15800 N1.getOperand(0) == N0.getOperand(0))
15801 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
15802 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
15803 // Generate SUB & CMOV.
15804 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
15805 DAG.getConstant(0, VT), N0.getOperand(0));
15807 SDValue Ops[] = { N0.getOperand(0), Neg,
15808 DAG.getConstant(X86::COND_GE, MVT::i8),
15809 SDValue(Neg.getNode(), 1) };
15810 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
15811 Ops, array_lengthof(Ops));
15816 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
15817 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
15818 TargetLowering::DAGCombinerInfo &DCI,
15819 const X86Subtarget *Subtarget) {
15820 if (DCI.isBeforeLegalizeOps())
15823 if (Subtarget->hasCMov()) {
15824 SDValue RV = performIntegerAbsCombine(N, DAG);
15829 // Try forming BMI if it is available.
15830 if (!Subtarget->hasBMI())
15833 EVT VT = N->getValueType(0);
15835 if (VT != MVT::i32 && VT != MVT::i64)
15838 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
15840 // Create BLSMSK instructions by finding X ^ (X-1)
15841 SDValue N0 = N->getOperand(0);
15842 SDValue N1 = N->getOperand(1);
15843 DebugLoc DL = N->getDebugLoc();
15845 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
15846 isAllOnes(N0.getOperand(1)))
15847 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
15849 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
15850 isAllOnes(N1.getOperand(1)))
15851 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
15856 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
15857 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
15858 TargetLowering::DAGCombinerInfo &DCI,
15859 const X86Subtarget *Subtarget) {
15860 LoadSDNode *Ld = cast<LoadSDNode>(N);
15861 EVT RegVT = Ld->getValueType(0);
15862 EVT MemVT = Ld->getMemoryVT();
15863 DebugLoc dl = Ld->getDebugLoc();
15864 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15866 ISD::LoadExtType Ext = Ld->getExtensionType();
15868 // If this is a vector EXT Load then attempt to optimize it using a
15869 // shuffle. We need SSSE3 shuffles.
15870 // TODO: It is possible to support ZExt by zeroing the undef values
15871 // during the shuffle phase or after the shuffle.
15872 if (RegVT.isVector() && RegVT.isInteger() &&
15873 Ext == ISD::EXTLOAD && Subtarget->hasSSSE3()) {
15874 assert(MemVT != RegVT && "Cannot extend to the same type");
15875 assert(MemVT.isVector() && "Must load a vector from memory");
15877 unsigned NumElems = RegVT.getVectorNumElements();
15878 unsigned RegSz = RegVT.getSizeInBits();
15879 unsigned MemSz = MemVT.getSizeInBits();
15880 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15882 // All sizes must be a power of two.
15883 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
15886 // Attempt to load the original value using scalar loads.
15887 // Find the largest scalar type that divides the total loaded size.
15888 MVT SclrLoadTy = MVT::i8;
15889 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15890 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15891 MVT Tp = (MVT::SimpleValueType)tp;
15892 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15897 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15898 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15900 SclrLoadTy = MVT::f64;
15902 // Calculate the number of scalar loads that we need to perform
15903 // in order to load our vector from memory.
15904 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15906 // Represent our vector as a sequence of elements which are the
15907 // largest scalar that we can load.
15908 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
15909 RegSz/SclrLoadTy.getSizeInBits());
15911 // Represent the data using the same element type that is stored in
15912 // memory. In practice, we ''widen'' MemVT.
15913 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15914 RegSz/MemVT.getScalarType().getSizeInBits());
15916 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15917 "Invalid vector type");
15919 // We can't shuffle using an illegal type.
15920 if (!TLI.isTypeLegal(WideVecVT))
15923 SmallVector<SDValue, 8> Chains;
15924 SDValue Ptr = Ld->getBasePtr();
15925 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
15926 TLI.getPointerTy());
15927 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15929 for (unsigned i = 0; i < NumLoads; ++i) {
15930 // Perform a single load.
15931 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
15932 Ptr, Ld->getPointerInfo(),
15933 Ld->isVolatile(), Ld->isNonTemporal(),
15934 Ld->isInvariant(), Ld->getAlignment());
15935 Chains.push_back(ScalarLoad.getValue(1));
15936 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15937 // another round of DAGCombining.
15939 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15941 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15942 ScalarLoad, DAG.getIntPtrConstant(i));
15944 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15947 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
15950 // Bitcast the loaded value to a vector of the original element type, in
15951 // the size of the target vector type.
15952 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15953 unsigned SizeRatio = RegSz/MemSz;
15955 // Redistribute the loaded elements into the different locations.
15956 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
15957 for (unsigned i = 0; i != NumElems; ++i)
15958 ShuffleVec[i*SizeRatio] = i;
15960 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15961 DAG.getUNDEF(WideVecVT),
15964 // Bitcast to the requested type.
15965 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15966 // Replace the original load with the new sequence
15967 // and return the new chain.
15968 return DCI.CombineTo(N, Shuff, TF, true);
15974 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
15975 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
15976 const X86Subtarget *Subtarget) {
15977 StoreSDNode *St = cast<StoreSDNode>(N);
15978 EVT VT = St->getValue().getValueType();
15979 EVT StVT = St->getMemoryVT();
15980 DebugLoc dl = St->getDebugLoc();
15981 SDValue StoredVal = St->getOperand(1);
15982 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15984 // If we are saving a concatenation of two XMM registers, perform two stores.
15985 // On Sandy Bridge, 256-bit memory operations are executed by two
15986 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
15987 // memory operation.
15988 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
15989 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
15990 StoredVal.getNumOperands() == 2) {
15991 SDValue Value0 = StoredVal.getOperand(0);
15992 SDValue Value1 = StoredVal.getOperand(1);
15994 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
15995 SDValue Ptr0 = St->getBasePtr();
15996 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
15998 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
15999 St->getPointerInfo(), St->isVolatile(),
16000 St->isNonTemporal(), St->getAlignment());
16001 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
16002 St->getPointerInfo(), St->isVolatile(),
16003 St->isNonTemporal(), St->getAlignment());
16004 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
16007 // Optimize trunc store (of multiple scalars) to shuffle and store.
16008 // First, pack all of the elements in one place. Next, store to memory
16009 // in fewer chunks.
16010 if (St->isTruncatingStore() && VT.isVector()) {
16011 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16012 unsigned NumElems = VT.getVectorNumElements();
16013 assert(StVT != VT && "Cannot truncate to the same type");
16014 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
16015 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
16017 // From, To sizes and ElemCount must be pow of two
16018 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
16019 // We are going to use the original vector elt for storing.
16020 // Accumulated smaller vector elements must be a multiple of the store size.
16021 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
16023 unsigned SizeRatio = FromSz / ToSz;
16025 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
16027 // Create a type on which we perform the shuffle
16028 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
16029 StVT.getScalarType(), NumElems*SizeRatio);
16031 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
16033 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
16034 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16035 for (unsigned i = 0; i != NumElems; ++i)
16036 ShuffleVec[i] = i * SizeRatio;
16038 // Can't shuffle using an illegal type.
16039 if (!TLI.isTypeLegal(WideVecVT))
16042 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
16043 DAG.getUNDEF(WideVecVT),
16045 // At this point all of the data is stored at the bottom of the
16046 // register. We now need to save it to mem.
16048 // Find the largest store unit
16049 MVT StoreType = MVT::i8;
16050 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16051 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16052 MVT Tp = (MVT::SimpleValueType)tp;
16053 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
16057 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16058 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
16059 (64 <= NumElems * ToSz))
16060 StoreType = MVT::f64;
16062 // Bitcast the original vector into a vector of store-size units
16063 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
16064 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
16065 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
16066 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
16067 SmallVector<SDValue, 8> Chains;
16068 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
16069 TLI.getPointerTy());
16070 SDValue Ptr = St->getBasePtr();
16072 // Perform one or more big stores into memory.
16073 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
16074 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16075 StoreType, ShuffWide,
16076 DAG.getIntPtrConstant(i));
16077 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
16078 St->getPointerInfo(), St->isVolatile(),
16079 St->isNonTemporal(), St->getAlignment());
16080 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16081 Chains.push_back(Ch);
16084 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16089 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
16090 // the FP state in cases where an emms may be missing.
16091 // A preferable solution to the general problem is to figure out the right
16092 // places to insert EMMS. This qualifies as a quick hack.
16094 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
16095 if (VT.getSizeInBits() != 64)
16098 const Function *F = DAG.getMachineFunction().getFunction();
16099 bool NoImplicitFloatOps = F->getFnAttributes().
16100 hasAttribute(Attributes::NoImplicitFloat);
16101 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
16102 && Subtarget->hasSSE2();
16103 if ((VT.isVector() ||
16104 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
16105 isa<LoadSDNode>(St->getValue()) &&
16106 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
16107 St->getChain().hasOneUse() && !St->isVolatile()) {
16108 SDNode* LdVal = St->getValue().getNode();
16109 LoadSDNode *Ld = 0;
16110 int TokenFactorIndex = -1;
16111 SmallVector<SDValue, 8> Ops;
16112 SDNode* ChainVal = St->getChain().getNode();
16113 // Must be a store of a load. We currently handle two cases: the load
16114 // is a direct child, and it's under an intervening TokenFactor. It is
16115 // possible to dig deeper under nested TokenFactors.
16116 if (ChainVal == LdVal)
16117 Ld = cast<LoadSDNode>(St->getChain());
16118 else if (St->getValue().hasOneUse() &&
16119 ChainVal->getOpcode() == ISD::TokenFactor) {
16120 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
16121 if (ChainVal->getOperand(i).getNode() == LdVal) {
16122 TokenFactorIndex = i;
16123 Ld = cast<LoadSDNode>(St->getValue());
16125 Ops.push_back(ChainVal->getOperand(i));
16129 if (!Ld || !ISD::isNormalLoad(Ld))
16132 // If this is not the MMX case, i.e. we are just turning i64 load/store
16133 // into f64 load/store, avoid the transformation if there are multiple
16134 // uses of the loaded value.
16135 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
16138 DebugLoc LdDL = Ld->getDebugLoc();
16139 DebugLoc StDL = N->getDebugLoc();
16140 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
16141 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
16143 if (Subtarget->is64Bit() || F64IsLegal) {
16144 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
16145 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
16146 Ld->getPointerInfo(), Ld->isVolatile(),
16147 Ld->isNonTemporal(), Ld->isInvariant(),
16148 Ld->getAlignment());
16149 SDValue NewChain = NewLd.getValue(1);
16150 if (TokenFactorIndex != -1) {
16151 Ops.push_back(NewChain);
16152 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16155 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
16156 St->getPointerInfo(),
16157 St->isVolatile(), St->isNonTemporal(),
16158 St->getAlignment());
16161 // Otherwise, lower to two pairs of 32-bit loads / stores.
16162 SDValue LoAddr = Ld->getBasePtr();
16163 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
16164 DAG.getConstant(4, MVT::i32));
16166 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
16167 Ld->getPointerInfo(),
16168 Ld->isVolatile(), Ld->isNonTemporal(),
16169 Ld->isInvariant(), Ld->getAlignment());
16170 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
16171 Ld->getPointerInfo().getWithOffset(4),
16172 Ld->isVolatile(), Ld->isNonTemporal(),
16174 MinAlign(Ld->getAlignment(), 4));
16176 SDValue NewChain = LoLd.getValue(1);
16177 if (TokenFactorIndex != -1) {
16178 Ops.push_back(LoLd);
16179 Ops.push_back(HiLd);
16180 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16184 LoAddr = St->getBasePtr();
16185 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
16186 DAG.getConstant(4, MVT::i32));
16188 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
16189 St->getPointerInfo(),
16190 St->isVolatile(), St->isNonTemporal(),
16191 St->getAlignment());
16192 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
16193 St->getPointerInfo().getWithOffset(4),
16195 St->isNonTemporal(),
16196 MinAlign(St->getAlignment(), 4));
16197 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
16202 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
16203 /// and return the operands for the horizontal operation in LHS and RHS. A
16204 /// horizontal operation performs the binary operation on successive elements
16205 /// of its first operand, then on successive elements of its second operand,
16206 /// returning the resulting values in a vector. For example, if
16207 /// A = < float a0, float a1, float a2, float a3 >
16209 /// B = < float b0, float b1, float b2, float b3 >
16210 /// then the result of doing a horizontal operation on A and B is
16211 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
16212 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
16213 /// A horizontal-op B, for some already available A and B, and if so then LHS is
16214 /// set to A, RHS to B, and the routine returns 'true'.
16215 /// Note that the binary operation should have the property that if one of the
16216 /// operands is UNDEF then the result is UNDEF.
16217 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
16218 // Look for the following pattern: if
16219 // A = < float a0, float a1, float a2, float a3 >
16220 // B = < float b0, float b1, float b2, float b3 >
16222 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
16223 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
16224 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
16225 // which is A horizontal-op B.
16227 // At least one of the operands should be a vector shuffle.
16228 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
16229 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
16232 EVT VT = LHS.getValueType();
16234 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16235 "Unsupported vector type for horizontal add/sub");
16237 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
16238 // operate independently on 128-bit lanes.
16239 unsigned NumElts = VT.getVectorNumElements();
16240 unsigned NumLanes = VT.getSizeInBits()/128;
16241 unsigned NumLaneElts = NumElts / NumLanes;
16242 assert((NumLaneElts % 2 == 0) &&
16243 "Vector type should have an even number of elements in each lane");
16244 unsigned HalfLaneElts = NumLaneElts/2;
16246 // View LHS in the form
16247 // LHS = VECTOR_SHUFFLE A, B, LMask
16248 // If LHS is not a shuffle then pretend it is the shuffle
16249 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
16250 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
16253 SmallVector<int, 16> LMask(NumElts);
16254 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16255 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
16256 A = LHS.getOperand(0);
16257 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
16258 B = LHS.getOperand(1);
16259 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
16260 std::copy(Mask.begin(), Mask.end(), LMask.begin());
16262 if (LHS.getOpcode() != ISD::UNDEF)
16264 for (unsigned i = 0; i != NumElts; ++i)
16268 // Likewise, view RHS in the form
16269 // RHS = VECTOR_SHUFFLE C, D, RMask
16271 SmallVector<int, 16> RMask(NumElts);
16272 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16273 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
16274 C = RHS.getOperand(0);
16275 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
16276 D = RHS.getOperand(1);
16277 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
16278 std::copy(Mask.begin(), Mask.end(), RMask.begin());
16280 if (RHS.getOpcode() != ISD::UNDEF)
16282 for (unsigned i = 0; i != NumElts; ++i)
16286 // Check that the shuffles are both shuffling the same vectors.
16287 if (!(A == C && B == D) && !(A == D && B == C))
16290 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
16291 if (!A.getNode() && !B.getNode())
16294 // If A and B occur in reverse order in RHS, then "swap" them (which means
16295 // rewriting the mask).
16297 CommuteVectorShuffleMask(RMask, NumElts);
16299 // At this point LHS and RHS are equivalent to
16300 // LHS = VECTOR_SHUFFLE A, B, LMask
16301 // RHS = VECTOR_SHUFFLE A, B, RMask
16302 // Check that the masks correspond to performing a horizontal operation.
16303 for (unsigned i = 0; i != NumElts; ++i) {
16304 int LIdx = LMask[i], RIdx = RMask[i];
16306 // Ignore any UNDEF components.
16307 if (LIdx < 0 || RIdx < 0 ||
16308 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
16309 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
16312 // Check that successive elements are being operated on. If not, this is
16313 // not a horizontal operation.
16314 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
16315 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
16316 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
16317 if (!(LIdx == Index && RIdx == Index + 1) &&
16318 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
16322 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
16323 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
16327 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
16328 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
16329 const X86Subtarget *Subtarget) {
16330 EVT VT = N->getValueType(0);
16331 SDValue LHS = N->getOperand(0);
16332 SDValue RHS = N->getOperand(1);
16334 // Try to synthesize horizontal adds from adds of shuffles.
16335 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16336 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16337 isHorizontalBinOp(LHS, RHS, true))
16338 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
16342 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
16343 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
16344 const X86Subtarget *Subtarget) {
16345 EVT VT = N->getValueType(0);
16346 SDValue LHS = N->getOperand(0);
16347 SDValue RHS = N->getOperand(1);
16349 // Try to synthesize horizontal subs from subs of shuffles.
16350 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16351 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16352 isHorizontalBinOp(LHS, RHS, false))
16353 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
16357 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
16358 /// X86ISD::FXOR nodes.
16359 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
16360 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
16361 // F[X]OR(0.0, x) -> x
16362 // F[X]OR(x, 0.0) -> x
16363 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
16364 if (C->getValueAPF().isPosZero())
16365 return N->getOperand(1);
16366 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
16367 if (C->getValueAPF().isPosZero())
16368 return N->getOperand(0);
16372 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
16373 /// X86ISD::FMAX nodes.
16374 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
16375 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
16377 // Only perform optimizations if UnsafeMath is used.
16378 if (!DAG.getTarget().Options.UnsafeFPMath)
16381 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
16382 // into FMINC and FMAXC, which are Commutative operations.
16383 unsigned NewOp = 0;
16384 switch (N->getOpcode()) {
16385 default: llvm_unreachable("unknown opcode");
16386 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
16387 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
16390 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),
16391 N->getOperand(0), N->getOperand(1));
16395 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
16396 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
16397 // FAND(0.0, x) -> 0.0
16398 // FAND(x, 0.0) -> 0.0
16399 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
16400 if (C->getValueAPF().isPosZero())
16401 return N->getOperand(0);
16402 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
16403 if (C->getValueAPF().isPosZero())
16404 return N->getOperand(1);
16408 static SDValue PerformBTCombine(SDNode *N,
16410 TargetLowering::DAGCombinerInfo &DCI) {
16411 // BT ignores high bits in the bit index operand.
16412 SDValue Op1 = N->getOperand(1);
16413 if (Op1.hasOneUse()) {
16414 unsigned BitWidth = Op1.getValueSizeInBits();
16415 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
16416 APInt KnownZero, KnownOne;
16417 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
16418 !DCI.isBeforeLegalizeOps());
16419 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16420 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
16421 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
16422 DCI.CommitTargetLoweringOpt(TLO);
16427 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
16428 SDValue Op = N->getOperand(0);
16429 if (Op.getOpcode() == ISD::BITCAST)
16430 Op = Op.getOperand(0);
16431 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
16432 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
16433 VT.getVectorElementType().getSizeInBits() ==
16434 OpVT.getVectorElementType().getSizeInBits()) {
16435 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
16440 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
16441 TargetLowering::DAGCombinerInfo &DCI,
16442 const X86Subtarget *Subtarget) {
16443 if (!DCI.isBeforeLegalizeOps())
16446 if (!Subtarget->hasFp256())
16449 EVT VT = N->getValueType(0);
16450 SDValue Op = N->getOperand(0);
16451 EVT OpVT = Op.getValueType();
16452 DebugLoc dl = N->getDebugLoc();
16454 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
16455 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
16457 if (Subtarget->hasInt256())
16458 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
16460 // Optimize vectors in AVX mode
16461 // Sign extend v8i16 to v8i32 and
16464 // Divide input vector into two parts
16465 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
16466 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
16467 // concat the vectors to original VT
16469 unsigned NumElems = OpVT.getVectorNumElements();
16470 SDValue Undef = DAG.getUNDEF(OpVT);
16472 SmallVector<int,8> ShufMask1(NumElems, -1);
16473 for (unsigned i = 0; i != NumElems/2; ++i)
16476 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask1[0]);
16478 SmallVector<int,8> ShufMask2(NumElems, -1);
16479 for (unsigned i = 0; i != NumElems/2; ++i)
16480 ShufMask2[i] = i + NumElems/2;
16482 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask2[0]);
16484 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
16485 VT.getVectorNumElements()/2);
16487 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
16488 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
16490 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
16495 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
16496 const X86Subtarget* Subtarget) {
16497 DebugLoc dl = N->getDebugLoc();
16498 EVT VT = N->getValueType(0);
16500 // Let legalize expand this if it isn't a legal type yet.
16501 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16504 EVT ScalarVT = VT.getScalarType();
16505 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
16506 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
16509 SDValue A = N->getOperand(0);
16510 SDValue B = N->getOperand(1);
16511 SDValue C = N->getOperand(2);
16513 bool NegA = (A.getOpcode() == ISD::FNEG);
16514 bool NegB = (B.getOpcode() == ISD::FNEG);
16515 bool NegC = (C.getOpcode() == ISD::FNEG);
16517 // Negative multiplication when NegA xor NegB
16518 bool NegMul = (NegA != NegB);
16520 A = A.getOperand(0);
16522 B = B.getOperand(0);
16524 C = C.getOperand(0);
16528 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
16530 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
16532 return DAG.getNode(Opcode, dl, VT, A, B, C);
16535 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
16536 TargetLowering::DAGCombinerInfo &DCI,
16537 const X86Subtarget *Subtarget) {
16538 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
16539 // (and (i32 x86isd::setcc_carry), 1)
16540 // This eliminates the zext. This transformation is necessary because
16541 // ISD::SETCC is always legalized to i8.
16542 DebugLoc dl = N->getDebugLoc();
16543 SDValue N0 = N->getOperand(0);
16544 EVT VT = N->getValueType(0);
16545 EVT OpVT = N0.getValueType();
16547 if (N0.getOpcode() == ISD::AND &&
16549 N0.getOperand(0).hasOneUse()) {
16550 SDValue N00 = N0.getOperand(0);
16551 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
16553 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
16554 if (!C || C->getZExtValue() != 1)
16556 return DAG.getNode(ISD::AND, dl, VT,
16557 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
16558 N00.getOperand(0), N00.getOperand(1)),
16559 DAG.getConstant(1, VT));
16562 // Optimize vectors in AVX mode:
16565 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
16566 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
16567 // Concat upper and lower parts.
16570 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
16571 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
16572 // Concat upper and lower parts.
16574 if (!DCI.isBeforeLegalizeOps())
16577 if (!Subtarget->hasFp256())
16580 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
16581 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
16583 if (Subtarget->hasInt256())
16584 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
16586 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
16587 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
16588 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
16590 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
16591 VT.getVectorNumElements()/2);
16593 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
16594 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
16596 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
16602 // Optimize x == -y --> x+y == 0
16603 // x != -y --> x+y != 0
16604 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
16605 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
16606 SDValue LHS = N->getOperand(0);
16607 SDValue RHS = N->getOperand(1);
16609 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
16610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
16611 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
16612 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
16613 LHS.getValueType(), RHS, LHS.getOperand(1));
16614 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
16615 addV, DAG.getConstant(0, addV.getValueType()), CC);
16617 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
16618 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
16619 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
16620 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
16621 RHS.getValueType(), LHS, RHS.getOperand(1));
16622 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
16623 addV, DAG.getConstant(0, addV.getValueType()), CC);
16628 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
16629 // as "sbb reg,reg", since it can be extended without zext and produces
16630 // an all-ones bit which is more useful than 0/1 in some cases.
16631 static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
16632 return DAG.getNode(ISD::AND, DL, MVT::i8,
16633 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
16634 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
16635 DAG.getConstant(1, MVT::i8));
16638 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
16639 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
16640 TargetLowering::DAGCombinerInfo &DCI,
16641 const X86Subtarget *Subtarget) {
16642 DebugLoc DL = N->getDebugLoc();
16643 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
16644 SDValue EFLAGS = N->getOperand(1);
16646 if (CC == X86::COND_A) {
16647 // Try to convert COND_A into COND_B in an attempt to facilitate
16648 // materializing "setb reg".
16650 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
16651 // cannot take an immediate as its first operand.
16653 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
16654 EFLAGS.getValueType().isInteger() &&
16655 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
16656 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(),
16657 EFLAGS.getNode()->getVTList(),
16658 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
16659 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
16660 return MaterializeSETB(DL, NewEFLAGS, DAG);
16664 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
16665 // a zext and produces an all-ones bit which is more useful than 0/1 in some
16667 if (CC == X86::COND_B)
16668 return MaterializeSETB(DL, EFLAGS, DAG);
16672 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
16673 if (Flags.getNode()) {
16674 SDValue Cond = DAG.getConstant(CC, MVT::i8);
16675 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
16681 // Optimize branch condition evaluation.
16683 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
16684 TargetLowering::DAGCombinerInfo &DCI,
16685 const X86Subtarget *Subtarget) {
16686 DebugLoc DL = N->getDebugLoc();
16687 SDValue Chain = N->getOperand(0);
16688 SDValue Dest = N->getOperand(1);
16689 SDValue EFLAGS = N->getOperand(3);
16690 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
16694 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
16695 if (Flags.getNode()) {
16696 SDValue Cond = DAG.getConstant(CC, MVT::i8);
16697 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
16704 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
16705 const X86TargetLowering *XTLI) {
16706 SDValue Op0 = N->getOperand(0);
16707 EVT InVT = Op0->getValueType(0);
16709 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
16710 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
16711 DebugLoc dl = N->getDebugLoc();
16712 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
16713 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
16714 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
16717 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
16718 // a 32-bit target where SSE doesn't support i64->FP operations.
16719 if (Op0.getOpcode() == ISD::LOAD) {
16720 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
16721 EVT VT = Ld->getValueType(0);
16722 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
16723 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
16724 !XTLI->getSubtarget()->is64Bit() &&
16725 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16726 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
16727 Ld->getChain(), Op0, DAG);
16728 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
16735 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
16736 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
16737 X86TargetLowering::DAGCombinerInfo &DCI) {
16738 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
16739 // the result is either zero or one (depending on the input carry bit).
16740 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
16741 if (X86::isZeroNode(N->getOperand(0)) &&
16742 X86::isZeroNode(N->getOperand(1)) &&
16743 // We don't have a good way to replace an EFLAGS use, so only do this when
16745 SDValue(N, 1).use_empty()) {
16746 DebugLoc DL = N->getDebugLoc();
16747 EVT VT = N->getValueType(0);
16748 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
16749 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
16750 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
16751 DAG.getConstant(X86::COND_B,MVT::i8),
16753 DAG.getConstant(1, VT));
16754 return DCI.CombineTo(N, Res1, CarryOut);
16760 // fold (add Y, (sete X, 0)) -> adc 0, Y
16761 // (add Y, (setne X, 0)) -> sbb -1, Y
16762 // (sub (sete X, 0), Y) -> sbb 0, Y
16763 // (sub (setne X, 0), Y) -> adc -1, Y
16764 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
16765 DebugLoc DL = N->getDebugLoc();
16767 // Look through ZExts.
16768 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
16769 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
16772 SDValue SetCC = Ext.getOperand(0);
16773 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
16776 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
16777 if (CC != X86::COND_E && CC != X86::COND_NE)
16780 SDValue Cmp = SetCC.getOperand(1);
16781 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
16782 !X86::isZeroNode(Cmp.getOperand(1)) ||
16783 !Cmp.getOperand(0).getValueType().isInteger())
16786 SDValue CmpOp0 = Cmp.getOperand(0);
16787 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
16788 DAG.getConstant(1, CmpOp0.getValueType()));
16790 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
16791 if (CC == X86::COND_NE)
16792 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
16793 DL, OtherVal.getValueType(), OtherVal,
16794 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
16795 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
16796 DL, OtherVal.getValueType(), OtherVal,
16797 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
16800 /// PerformADDCombine - Do target-specific dag combines on integer adds.
16801 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
16802 const X86Subtarget *Subtarget) {
16803 EVT VT = N->getValueType(0);
16804 SDValue Op0 = N->getOperand(0);
16805 SDValue Op1 = N->getOperand(1);
16807 // Try to synthesize horizontal adds from adds of shuffles.
16808 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
16809 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
16810 isHorizontalBinOp(Op0, Op1, true))
16811 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
16813 return OptimizeConditionalInDecrement(N, DAG);
16816 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
16817 const X86Subtarget *Subtarget) {
16818 SDValue Op0 = N->getOperand(0);
16819 SDValue Op1 = N->getOperand(1);
16821 // X86 can't encode an immediate LHS of a sub. See if we can push the
16822 // negation into a preceding instruction.
16823 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
16824 // If the RHS of the sub is a XOR with one use and a constant, invert the
16825 // immediate. Then add one to the LHS of the sub so we can turn
16826 // X-Y -> X+~Y+1, saving one register.
16827 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
16828 isa<ConstantSDNode>(Op1.getOperand(1))) {
16829 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
16830 EVT VT = Op0.getValueType();
16831 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
16833 DAG.getConstant(~XorC, VT));
16834 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
16835 DAG.getConstant(C->getAPIntValue()+1, VT));
16839 // Try to synthesize horizontal adds from adds of shuffles.
16840 EVT VT = N->getValueType(0);
16841 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
16842 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
16843 isHorizontalBinOp(Op0, Op1, true))
16844 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
16846 return OptimizeConditionalInDecrement(N, DAG);
16849 /// performVZEXTCombine - Performs build vector combines
16850 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
16851 TargetLowering::DAGCombinerInfo &DCI,
16852 const X86Subtarget *Subtarget) {
16853 // (vzext (bitcast (vzext (x)) -> (vzext x)
16854 SDValue In = N->getOperand(0);
16855 while (In.getOpcode() == ISD::BITCAST)
16856 In = In.getOperand(0);
16858 if (In.getOpcode() != X86ISD::VZEXT)
16861 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0), In.getOperand(0));
16864 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
16865 DAGCombinerInfo &DCI) const {
16866 SelectionDAG &DAG = DCI.DAG;
16867 switch (N->getOpcode()) {
16869 case ISD::EXTRACT_VECTOR_ELT:
16870 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
16872 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
16873 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
16874 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
16875 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
16876 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
16877 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
16880 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
16881 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
16882 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
16883 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
16884 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
16885 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
16886 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
16887 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
16888 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
16890 case X86ISD::FOR: return PerformFORCombine(N, DAG);
16892 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
16893 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
16894 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
16895 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
16896 case ISD::ANY_EXTEND:
16897 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
16898 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
16899 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
16900 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
16901 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
16902 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
16903 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
16904 case X86ISD::SHUFP: // Handle all target specific shuffles
16905 case X86ISD::PALIGN:
16906 case X86ISD::UNPCKH:
16907 case X86ISD::UNPCKL:
16908 case X86ISD::MOVHLPS:
16909 case X86ISD::MOVLHPS:
16910 case X86ISD::PSHUFD:
16911 case X86ISD::PSHUFHW:
16912 case X86ISD::PSHUFLW:
16913 case X86ISD::MOVSS:
16914 case X86ISD::MOVSD:
16915 case X86ISD::VPERMILP:
16916 case X86ISD::VPERM2X128:
16917 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
16918 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
16924 /// isTypeDesirableForOp - Return true if the target has native support for
16925 /// the specified value type and it is 'desirable' to use the type for the
16926 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
16927 /// instruction encodings are longer and some i16 instructions are slow.
16928 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
16929 if (!isTypeLegal(VT))
16931 if (VT != MVT::i16)
16938 case ISD::SIGN_EXTEND:
16939 case ISD::ZERO_EXTEND:
16940 case ISD::ANY_EXTEND:
16953 /// IsDesirableToPromoteOp - This method query the target whether it is
16954 /// beneficial for dag combiner to promote the specified node. If true, it
16955 /// should return the desired promotion type by reference.
16956 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
16957 EVT VT = Op.getValueType();
16958 if (VT != MVT::i16)
16961 bool Promote = false;
16962 bool Commute = false;
16963 switch (Op.getOpcode()) {
16966 LoadSDNode *LD = cast<LoadSDNode>(Op);
16967 // If the non-extending load has a single use and it's not live out, then it
16968 // might be folded.
16969 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
16970 Op.hasOneUse()*/) {
16971 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
16972 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
16973 // The only case where we'd want to promote LOAD (rather then it being
16974 // promoted as an operand is when it's only use is liveout.
16975 if (UI->getOpcode() != ISD::CopyToReg)
16982 case ISD::SIGN_EXTEND:
16983 case ISD::ZERO_EXTEND:
16984 case ISD::ANY_EXTEND:
16989 SDValue N0 = Op.getOperand(0);
16990 // Look out for (store (shl (load), x)).
16991 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
17004 SDValue N0 = Op.getOperand(0);
17005 SDValue N1 = Op.getOperand(1);
17006 if (!Commute && MayFoldLoad(N1))
17008 // Avoid disabling potential load folding opportunities.
17009 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
17011 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
17021 //===----------------------------------------------------------------------===//
17022 // X86 Inline Assembly Support
17023 //===----------------------------------------------------------------------===//
17026 // Helper to match a string separated by whitespace.
17027 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
17028 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
17030 for (unsigned i = 0, e = args.size(); i != e; ++i) {
17031 StringRef piece(*args[i]);
17032 if (!s.startswith(piece)) // Check if the piece matches.
17035 s = s.substr(piece.size());
17036 StringRef::size_type pos = s.find_first_not_of(" \t");
17037 if (pos == 0) // We matched a prefix.
17045 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
17048 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
17049 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
17051 std::string AsmStr = IA->getAsmString();
17053 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
17054 if (!Ty || Ty->getBitWidth() % 16 != 0)
17057 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
17058 SmallVector<StringRef, 4> AsmPieces;
17059 SplitString(AsmStr, AsmPieces, ";\n");
17061 switch (AsmPieces.size()) {
17062 default: return false;
17064 // FIXME: this should verify that we are targeting a 486 or better. If not,
17065 // we will turn this bswap into something that will be lowered to logical
17066 // ops instead of emitting the bswap asm. For now, we don't support 486 or
17067 // lower so don't worry about this.
17069 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
17070 matchAsm(AsmPieces[0], "bswapl", "$0") ||
17071 matchAsm(AsmPieces[0], "bswapq", "$0") ||
17072 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
17073 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
17074 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
17075 // No need to check constraints, nothing other than the equivalent of
17076 // "=r,0" would be valid here.
17077 return IntrinsicLowering::LowerToByteSwap(CI);
17080 // rorw $$8, ${0:w} --> llvm.bswap.i16
17081 if (CI->getType()->isIntegerTy(16) &&
17082 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17083 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
17084 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
17086 const std::string &ConstraintsStr = IA->getConstraintString();
17087 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17088 std::sort(AsmPieces.begin(), AsmPieces.end());
17089 if (AsmPieces.size() == 4 &&
17090 AsmPieces[0] == "~{cc}" &&
17091 AsmPieces[1] == "~{dirflag}" &&
17092 AsmPieces[2] == "~{flags}" &&
17093 AsmPieces[3] == "~{fpsr}")
17094 return IntrinsicLowering::LowerToByteSwap(CI);
17098 if (CI->getType()->isIntegerTy(32) &&
17099 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17100 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
17101 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
17102 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
17104 const std::string &ConstraintsStr = IA->getConstraintString();
17105 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17106 std::sort(AsmPieces.begin(), AsmPieces.end());
17107 if (AsmPieces.size() == 4 &&
17108 AsmPieces[0] == "~{cc}" &&
17109 AsmPieces[1] == "~{dirflag}" &&
17110 AsmPieces[2] == "~{flags}" &&
17111 AsmPieces[3] == "~{fpsr}")
17112 return IntrinsicLowering::LowerToByteSwap(CI);
17115 if (CI->getType()->isIntegerTy(64)) {
17116 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
17117 if (Constraints.size() >= 2 &&
17118 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
17119 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
17120 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
17121 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
17122 matchAsm(AsmPieces[1], "bswap", "%edx") &&
17123 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
17124 return IntrinsicLowering::LowerToByteSwap(CI);
17134 /// getConstraintType - Given a constraint letter, return the type of
17135 /// constraint it is for this target.
17136 X86TargetLowering::ConstraintType
17137 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
17138 if (Constraint.size() == 1) {
17139 switch (Constraint[0]) {
17150 return C_RegisterClass;
17174 return TargetLowering::getConstraintType(Constraint);
17177 /// Examine constraint type and operand type and determine a weight value.
17178 /// This object must already have been set up with the operand type
17179 /// and the current alternative constraint selected.
17180 TargetLowering::ConstraintWeight
17181 X86TargetLowering::getSingleConstraintMatchWeight(
17182 AsmOperandInfo &info, const char *constraint) const {
17183 ConstraintWeight weight = CW_Invalid;
17184 Value *CallOperandVal = info.CallOperandVal;
17185 // If we don't have a value, we can't do a match,
17186 // but allow it at the lowest weight.
17187 if (CallOperandVal == NULL)
17189 Type *type = CallOperandVal->getType();
17190 // Look at the constraint type.
17191 switch (*constraint) {
17193 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
17204 if (CallOperandVal->getType()->isIntegerTy())
17205 weight = CW_SpecificReg;
17210 if (type->isFloatingPointTy())
17211 weight = CW_SpecificReg;
17214 if (type->isX86_MMXTy() && Subtarget->hasMMX())
17215 weight = CW_SpecificReg;
17219 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
17220 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
17221 weight = CW_Register;
17224 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
17225 if (C->getZExtValue() <= 31)
17226 weight = CW_Constant;
17230 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17231 if (C->getZExtValue() <= 63)
17232 weight = CW_Constant;
17236 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17237 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
17238 weight = CW_Constant;
17242 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17243 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
17244 weight = CW_Constant;
17248 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17249 if (C->getZExtValue() <= 3)
17250 weight = CW_Constant;
17254 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17255 if (C->getZExtValue() <= 0xff)
17256 weight = CW_Constant;
17261 if (dyn_cast<ConstantFP>(CallOperandVal)) {
17262 weight = CW_Constant;
17266 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17267 if ((C->getSExtValue() >= -0x80000000LL) &&
17268 (C->getSExtValue() <= 0x7fffffffLL))
17269 weight = CW_Constant;
17273 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17274 if (C->getZExtValue() <= 0xffffffff)
17275 weight = CW_Constant;
17282 /// LowerXConstraint - try to replace an X constraint, which matches anything,
17283 /// with another that has more specific requirements based on the type of the
17284 /// corresponding operand.
17285 const char *X86TargetLowering::
17286 LowerXConstraint(EVT ConstraintVT) const {
17287 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
17288 // 'f' like normal targets.
17289 if (ConstraintVT.isFloatingPoint()) {
17290 if (Subtarget->hasSSE2())
17292 if (Subtarget->hasSSE1())
17296 return TargetLowering::LowerXConstraint(ConstraintVT);
17299 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
17300 /// vector. If it is invalid, don't add anything to Ops.
17301 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
17302 std::string &Constraint,
17303 std::vector<SDValue>&Ops,
17304 SelectionDAG &DAG) const {
17305 SDValue Result(0, 0);
17307 // Only support length 1 constraints for now.
17308 if (Constraint.length() > 1) return;
17310 char ConstraintLetter = Constraint[0];
17311 switch (ConstraintLetter) {
17314 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17315 if (C->getZExtValue() <= 31) {
17316 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17323 if (C->getZExtValue() <= 63) {
17324 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17330 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17331 if (isInt<8>(C->getSExtValue())) {
17332 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17338 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17339 if (C->getZExtValue() <= 255) {
17340 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17346 // 32-bit signed value
17347 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17348 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17349 C->getSExtValue())) {
17350 // Widen to 64 bits here to get it sign extended.
17351 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
17354 // FIXME gcc accepts some relocatable values here too, but only in certain
17355 // memory models; it's complicated.
17360 // 32-bit unsigned value
17361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17362 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17363 C->getZExtValue())) {
17364 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17368 // FIXME gcc accepts some relocatable values here too, but only in certain
17369 // memory models; it's complicated.
17373 // Literal immediates are always ok.
17374 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
17375 // Widen to 64 bits here to get it sign extended.
17376 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
17380 // In any sort of PIC mode addresses need to be computed at runtime by
17381 // adding in a register or some sort of table lookup. These can't
17382 // be used as immediates.
17383 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
17386 // If we are in non-pic codegen mode, we allow the address of a global (with
17387 // an optional displacement) to be used with 'i'.
17388 GlobalAddressSDNode *GA = 0;
17389 int64_t Offset = 0;
17391 // Match either (GA), (GA+C), (GA+C1+C2), etc.
17393 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
17394 Offset += GA->getOffset();
17396 } else if (Op.getOpcode() == ISD::ADD) {
17397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17398 Offset += C->getZExtValue();
17399 Op = Op.getOperand(0);
17402 } else if (Op.getOpcode() == ISD::SUB) {
17403 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17404 Offset += -C->getZExtValue();
17405 Op = Op.getOperand(0);
17410 // Otherwise, this isn't something we can handle, reject it.
17414 const GlobalValue *GV = GA->getGlobal();
17415 // If we require an extra load to get this address, as in PIC mode, we
17416 // can't accept it.
17417 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
17418 getTargetMachine())))
17421 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
17422 GA->getValueType(0), Offset);
17427 if (Result.getNode()) {
17428 Ops.push_back(Result);
17431 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
17434 std::pair<unsigned, const TargetRegisterClass*>
17435 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
17437 // First, see if this is a constraint that directly corresponds to an LLVM
17439 if (Constraint.size() == 1) {
17440 // GCC Constraint Letters
17441 switch (Constraint[0]) {
17443 // TODO: Slight differences here in allocation order and leaving
17444 // RIP in the class. Do they matter any more here than they do
17445 // in the normal allocation?
17446 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
17447 if (Subtarget->is64Bit()) {
17448 if (VT == MVT::i32 || VT == MVT::f32)
17449 return std::make_pair(0U, &X86::GR32RegClass);
17450 if (VT == MVT::i16)
17451 return std::make_pair(0U, &X86::GR16RegClass);
17452 if (VT == MVT::i8 || VT == MVT::i1)
17453 return std::make_pair(0U, &X86::GR8RegClass);
17454 if (VT == MVT::i64 || VT == MVT::f64)
17455 return std::make_pair(0U, &X86::GR64RegClass);
17458 // 32-bit fallthrough
17459 case 'Q': // Q_REGS
17460 if (VT == MVT::i32 || VT == MVT::f32)
17461 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
17462 if (VT == MVT::i16)
17463 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
17464 if (VT == MVT::i8 || VT == MVT::i1)
17465 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
17466 if (VT == MVT::i64)
17467 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
17469 case 'r': // GENERAL_REGS
17470 case 'l': // INDEX_REGS
17471 if (VT == MVT::i8 || VT == MVT::i1)
17472 return std::make_pair(0U, &X86::GR8RegClass);
17473 if (VT == MVT::i16)
17474 return std::make_pair(0U, &X86::GR16RegClass);
17475 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
17476 return std::make_pair(0U, &X86::GR32RegClass);
17477 return std::make_pair(0U, &X86::GR64RegClass);
17478 case 'R': // LEGACY_REGS
17479 if (VT == MVT::i8 || VT == MVT::i1)
17480 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
17481 if (VT == MVT::i16)
17482 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
17483 if (VT == MVT::i32 || !Subtarget->is64Bit())
17484 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
17485 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
17486 case 'f': // FP Stack registers.
17487 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
17488 // value to the correct fpstack register class.
17489 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
17490 return std::make_pair(0U, &X86::RFP32RegClass);
17491 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
17492 return std::make_pair(0U, &X86::RFP64RegClass);
17493 return std::make_pair(0U, &X86::RFP80RegClass);
17494 case 'y': // MMX_REGS if MMX allowed.
17495 if (!Subtarget->hasMMX()) break;
17496 return std::make_pair(0U, &X86::VR64RegClass);
17497 case 'Y': // SSE_REGS if SSE2 allowed
17498 if (!Subtarget->hasSSE2()) break;
17500 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
17501 if (!Subtarget->hasSSE1()) break;
17503 switch (VT.getSimpleVT().SimpleTy) {
17505 // Scalar SSE types.
17508 return std::make_pair(0U, &X86::FR32RegClass);
17511 return std::make_pair(0U, &X86::FR64RegClass);
17519 return std::make_pair(0U, &X86::VR128RegClass);
17527 return std::make_pair(0U, &X86::VR256RegClass);
17533 // Use the default implementation in TargetLowering to convert the register
17534 // constraint into a member of a register class.
17535 std::pair<unsigned, const TargetRegisterClass*> Res;
17536 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
17538 // Not found as a standard register?
17539 if (Res.second == 0) {
17540 // Map st(0) -> st(7) -> ST0
17541 if (Constraint.size() == 7 && Constraint[0] == '{' &&
17542 tolower(Constraint[1]) == 's' &&
17543 tolower(Constraint[2]) == 't' &&
17544 Constraint[3] == '(' &&
17545 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
17546 Constraint[5] == ')' &&
17547 Constraint[6] == '}') {
17549 Res.first = X86::ST0+Constraint[4]-'0';
17550 Res.second = &X86::RFP80RegClass;
17554 // GCC allows "st(0)" to be called just plain "st".
17555 if (StringRef("{st}").equals_lower(Constraint)) {
17556 Res.first = X86::ST0;
17557 Res.second = &X86::RFP80RegClass;
17562 if (StringRef("{flags}").equals_lower(Constraint)) {
17563 Res.first = X86::EFLAGS;
17564 Res.second = &X86::CCRRegClass;
17568 // 'A' means EAX + EDX.
17569 if (Constraint == "A") {
17570 Res.first = X86::EAX;
17571 Res.second = &X86::GR32_ADRegClass;
17577 // Otherwise, check to see if this is a register class of the wrong value
17578 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
17579 // turn into {ax},{dx}.
17580 if (Res.second->hasType(VT))
17581 return Res; // Correct type already, nothing to do.
17583 // All of the single-register GCC register classes map their values onto
17584 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
17585 // really want an 8-bit or 32-bit register, map to the appropriate register
17586 // class and return the appropriate register.
17587 if (Res.second == &X86::GR16RegClass) {
17588 if (VT == MVT::i8) {
17589 unsigned DestReg = 0;
17590 switch (Res.first) {
17592 case X86::AX: DestReg = X86::AL; break;
17593 case X86::DX: DestReg = X86::DL; break;
17594 case X86::CX: DestReg = X86::CL; break;
17595 case X86::BX: DestReg = X86::BL; break;
17598 Res.first = DestReg;
17599 Res.second = &X86::GR8RegClass;
17601 } else if (VT == MVT::i32) {
17602 unsigned DestReg = 0;
17603 switch (Res.first) {
17605 case X86::AX: DestReg = X86::EAX; break;
17606 case X86::DX: DestReg = X86::EDX; break;
17607 case X86::CX: DestReg = X86::ECX; break;
17608 case X86::BX: DestReg = X86::EBX; break;
17609 case X86::SI: DestReg = X86::ESI; break;
17610 case X86::DI: DestReg = X86::EDI; break;
17611 case X86::BP: DestReg = X86::EBP; break;
17612 case X86::SP: DestReg = X86::ESP; break;
17615 Res.first = DestReg;
17616 Res.second = &X86::GR32RegClass;
17618 } else if (VT == MVT::i64) {
17619 unsigned DestReg = 0;
17620 switch (Res.first) {
17622 case X86::AX: DestReg = X86::RAX; break;
17623 case X86::DX: DestReg = X86::RDX; break;
17624 case X86::CX: DestReg = X86::RCX; break;
17625 case X86::BX: DestReg = X86::RBX; break;
17626 case X86::SI: DestReg = X86::RSI; break;
17627 case X86::DI: DestReg = X86::RDI; break;
17628 case X86::BP: DestReg = X86::RBP; break;
17629 case X86::SP: DestReg = X86::RSP; break;
17632 Res.first = DestReg;
17633 Res.second = &X86::GR64RegClass;
17636 } else if (Res.second == &X86::FR32RegClass ||
17637 Res.second == &X86::FR64RegClass ||
17638 Res.second == &X86::VR128RegClass) {
17639 // Handle references to XMM physical registers that got mapped into the
17640 // wrong class. This can happen with constraints like {xmm0} where the
17641 // target independent register mapper will just pick the first match it can
17642 // find, ignoring the required type.
17644 if (VT == MVT::f32 || VT == MVT::i32)
17645 Res.second = &X86::FR32RegClass;
17646 else if (VT == MVT::f64 || VT == MVT::i64)
17647 Res.second = &X86::FR64RegClass;
17648 else if (X86::VR128RegClass.hasType(VT))
17649 Res.second = &X86::VR128RegClass;
17650 else if (X86::VR256RegClass.hasType(VT))
17651 Res.second = &X86::VR256RegClass;
17657 //===----------------------------------------------------------------------===//
17661 //===----------------------------------------------------------------------===//
17663 struct X86CostTblEntry {
17670 FindInTable(const X86CostTblEntry *Tbl, unsigned len, int ISD, MVT Ty) {
17671 for (unsigned int i = 0; i < len; ++i)
17672 if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty)
17675 // Could not find an entry.
17679 struct X86TypeConversionCostTblEntry {
17687 FindInConvertTable(const X86TypeConversionCostTblEntry *Tbl, unsigned len,
17688 int ISD, MVT Dst, MVT Src) {
17689 for (unsigned int i = 0; i < len; ++i)
17690 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
17693 // Could not find an entry.
17697 ScalarTargetTransformInfo::PopcntHwSupport
17698 X86ScalarTargetTransformImpl::getPopcntHwSupport(unsigned TyWidth) const {
17699 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
17700 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget<X86Subtarget>();
17702 // TODO: Currently the __builtin_popcount() implementation using SSE3
17703 // instructions is inefficient. Once the problem is fixed, we should
17704 // call ST.hasSSE3() instead of ST.hasSSE4().
17705 return ST.hasSSE41() ? Fast : None;
17709 X86VectorTargetTransformInfo::getArithmeticInstrCost(unsigned Opcode,
17711 // Legalize the type.
17712 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(Ty);
17714 int ISD = InstructionOpcodeToISD(Opcode);
17715 assert(ISD && "Invalid opcode");
17717 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget<X86Subtarget>();
17719 static const X86CostTblEntry AVX1CostTable[] = {
17720 // We don't have to scalarize unsupported ops. We can issue two half-sized
17721 // operations and we only need to extract the upper YMM half.
17722 // Two ops + 1 extract + 1 insert = 4.
17723 { ISD::MUL, MVT::v8i32, 4 },
17724 { ISD::SUB, MVT::v8i32, 4 },
17725 { ISD::ADD, MVT::v8i32, 4 },
17726 { ISD::MUL, MVT::v4i64, 4 },
17727 { ISD::SUB, MVT::v4i64, 4 },
17728 { ISD::ADD, MVT::v4i64, 4 },
17731 // Look for AVX1 lowering tricks.
17733 int Idx = FindInTable(AVX1CostTable, array_lengthof(AVX1CostTable), ISD,
17736 return LT.first * AVX1CostTable[Idx].Cost;
17738 // Fallback to the default implementation.
17739 return VectorTargetTransformImpl::getArithmeticInstrCost(Opcode, Ty);
17743 X86VectorTargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
17744 unsigned Index) const {
17745 assert(Val->isVectorTy() && "This must be a vector type");
17747 if (Index != -1U) {
17748 // Legalize the type.
17749 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(Val);
17751 // This type is legalized to a scalar type.
17752 if (!LT.second.isVector())
17755 // The type may be split. Normalize the index to the new type.
17756 unsigned Width = LT.second.getVectorNumElements();
17757 Index = Index % Width;
17759 // Floating point scalars are already located in index #0.
17760 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
17764 return VectorTargetTransformImpl::getVectorInstrCost(Opcode, Val, Index);
17767 unsigned X86VectorTargetTransformInfo::getCmpSelInstrCost(unsigned Opcode,
17769 Type *CondTy) const {
17770 // Legalize the type.
17771 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(ValTy);
17773 MVT MTy = LT.second;
17775 int ISD = InstructionOpcodeToISD(Opcode);
17776 assert(ISD && "Invalid opcode");
17778 const X86Subtarget &ST =
17779 TLI->getTargetMachine().getSubtarget<X86Subtarget>();
17781 static const X86CostTblEntry SSE42CostTbl[] = {
17782 { ISD::SETCC, MVT::v2f64, 1 },
17783 { ISD::SETCC, MVT::v4f32, 1 },
17784 { ISD::SETCC, MVT::v2i64, 1 },
17785 { ISD::SETCC, MVT::v4i32, 1 },
17786 { ISD::SETCC, MVT::v8i16, 1 },
17787 { ISD::SETCC, MVT::v16i8, 1 },
17790 static const X86CostTblEntry AVX1CostTbl[] = {
17791 { ISD::SETCC, MVT::v4f64, 1 },
17792 { ISD::SETCC, MVT::v8f32, 1 },
17793 // AVX1 does not support 8-wide integer compare.
17794 { ISD::SETCC, MVT::v4i64, 4 },
17795 { ISD::SETCC, MVT::v8i32, 4 },
17796 { ISD::SETCC, MVT::v16i16, 4 },
17797 { ISD::SETCC, MVT::v32i8, 4 },
17800 static const X86CostTblEntry AVX2CostTbl[] = {
17801 { ISD::SETCC, MVT::v4i64, 1 },
17802 { ISD::SETCC, MVT::v8i32, 1 },
17803 { ISD::SETCC, MVT::v16i16, 1 },
17804 { ISD::SETCC, MVT::v32i8, 1 },
17807 if (ST.hasSSE42()) {
17808 int Idx = FindInTable(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
17810 return LT.first * SSE42CostTbl[Idx].Cost;
17814 int Idx = FindInTable(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
17816 return LT.first * AVX1CostTbl[Idx].Cost;
17819 if (ST.hasAVX2()) {
17820 int Idx = FindInTable(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
17822 return LT.first * AVX2CostTbl[Idx].Cost;
17825 return VectorTargetTransformImpl::getCmpSelInstrCost(Opcode, ValTy, CondTy);
17828 unsigned X86VectorTargetTransformInfo::getCastInstrCost(unsigned Opcode,
17831 int ISD = InstructionOpcodeToISD(Opcode);
17832 assert(ISD && "Invalid opcode");
17834 EVT SrcTy = TLI->getValueType(Src);
17835 EVT DstTy = TLI->getValueType(Dst);
17837 if (!SrcTy.isSimple() || !DstTy.isSimple())
17838 return VectorTargetTransformImpl::getCastInstrCost(Opcode, Dst, Src);
17840 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget<X86Subtarget>();
17842 static const X86TypeConversionCostTblEntry AVXConversionTbl[] = {
17843 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
17844 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
17845 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
17846 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
17847 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
17848 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
17849 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
17850 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
17851 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
17852 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
17853 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
17854 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
17855 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
17856 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
17857 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
17861 int Idx = FindInConvertTable(AVXConversionTbl,
17862 array_lengthof(AVXConversionTbl),
17863 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
17865 return AVXConversionTbl[Idx].Cost;
17868 return VectorTargetTransformImpl::getCastInstrCost(Opcode, Dst, Src);