1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
65 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
67 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
69 return new X8664_MachoTargetObjectFile();
70 return new TargetLoweringObjectFileMachO();
73 if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
75 return new X8664_ELFTargetObjectFile(TM);
76 return new X8632_ELFTargetObjectFile(TM);
78 if (TM.getSubtarget<X86Subtarget>().isTargetCOFF())
79 return new TargetLoweringObjectFileCOFF();
80 llvm_unreachable("unknown subtarget type");
83 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
84 : TargetLowering(TM, createTLOF(TM)) {
85 Subtarget = &TM.getSubtarget<X86Subtarget>();
86 X86ScalarSSEf64 = Subtarget->hasXMMInt();
87 X86ScalarSSEf32 = Subtarget->hasXMM();
88 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
90 RegInfo = TM.getRegisterInfo();
93 // Set up the TargetLowering object.
94 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
96 // X86 is weird, it always uses i8 for shift amounts and setcc results.
97 setShiftAmountType(MVT::i8);
98 setBooleanContents(ZeroOrOneBooleanContent);
99 setSchedulingPreference(Sched::RegPressure);
100 setStackPointerRegisterToSaveRestore(X86StackPtr);
102 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
103 // Setup Windows compiler runtime calls.
104 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
105 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
106 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
107 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
108 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
109 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
110 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
111 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
114 if (Subtarget->isTargetDarwin()) {
115 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
116 setUseUnderscoreSetJmp(false);
117 setUseUnderscoreLongJmp(false);
118 } else if (Subtarget->isTargetMingw()) {
119 // MS runtime is weird: it exports _setjmp, but longjmp!
120 setUseUnderscoreSetJmp(true);
121 setUseUnderscoreLongJmp(false);
123 setUseUnderscoreSetJmp(true);
124 setUseUnderscoreLongJmp(true);
127 // Set up the register classes.
128 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
129 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
130 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
131 if (Subtarget->is64Bit())
132 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
136 // We don't accept any truncstore of integer registers.
137 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
138 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
139 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
140 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
141 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
142 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
144 // SETOEQ and SETUNE require checking two conditions.
145 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
146 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
147 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
148 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
149 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
150 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
152 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
154 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
155 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
156 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
158 if (Subtarget->is64Bit()) {
159 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
160 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
161 } else if (!UseSoftFloat) {
162 // We have an algorithm for SSE2->double, and we turn this into a
163 // 64-bit FILD followed by conditional FADD for other targets.
164 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
165 // We have an algorithm for SSE2, and we turn this into a 64-bit
166 // FILD for other targets.
167 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
170 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
172 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
176 // SSE has no i16 to fp conversion, only i32
177 if (X86ScalarSSEf32) {
178 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
179 // f32 and f64 cases are Legal, f80 case is not
180 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
182 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
183 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
186 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
187 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
190 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
191 // are Legal, f80 is custom lowered.
192 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
193 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
195 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
197 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
198 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
200 if (X86ScalarSSEf32) {
201 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
202 // f32 and f64 cases are Legal, f80 case is not
203 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
206 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
209 // Handle FP_TO_UINT by promoting the destination to a larger signed
211 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
212 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
213 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
215 if (Subtarget->is64Bit()) {
216 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
217 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
218 } else if (!UseSoftFloat) {
219 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
220 // Expand FP_TO_UINT into a select.
221 // FIXME: We would like to use a Custom expander here eventually to do
222 // the optimal thing for SSE vs. the default expansion in the legalizer.
223 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
225 // With SSE3 we can use fisttpll to convert to a signed i64; without
226 // SSE, we're stuck with a fistpll.
227 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
230 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
231 if (!X86ScalarSSEf64) {
232 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
233 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
236 // Without SSE, i64->f64 goes through memory.
237 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
241 // Scalar integer divide and remainder are lowered to use operations that
242 // produce two results, to match the available instructions. This exposes
243 // the two-result form to trivial CSE, which is able to combine x/y and x%y
244 // into a single instruction.
246 // Scalar integer multiply-high is also lowered to use two-result
247 // operations, to match the available instructions. However, plain multiply
248 // (low) operations are left as Legal, as there are single-result
249 // instructions for this in x86. Using the two-result multiply instructions
250 // when both high and low results are needed must be arranged by dagcombine.
251 for (unsigned i = 0, e = 4; i != e; ++i) {
253 setOperationAction(ISD::MULHS, VT, Expand);
254 setOperationAction(ISD::MULHU, VT, Expand);
255 setOperationAction(ISD::SDIV, VT, Expand);
256 setOperationAction(ISD::UDIV, VT, Expand);
257 setOperationAction(ISD::SREM, VT, Expand);
258 setOperationAction(ISD::UREM, VT, Expand);
260 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
261 setOperationAction(ISD::ADDC, VT, Custom);
262 setOperationAction(ISD::ADDE, VT, Custom);
263 setOperationAction(ISD::SUBC, VT, Custom);
264 setOperationAction(ISD::SUBE, VT, Custom);
267 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
268 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
269 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
270 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
271 if (Subtarget->is64Bit())
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
276 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
277 setOperationAction(ISD::FREM , MVT::f32 , Expand);
278 setOperationAction(ISD::FREM , MVT::f64 , Expand);
279 setOperationAction(ISD::FREM , MVT::f80 , Expand);
280 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
282 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
283 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
284 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
285 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
286 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
287 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
288 if (Subtarget->is64Bit()) {
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 if (Subtarget->hasPOPCNT()) {
294 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
296 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
297 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
298 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
299 if (Subtarget->is64Bit())
300 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
303 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
304 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
306 // These should be promoted to a larger select which is supported.
307 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
308 // X86 wants to expand cmov itself.
309 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
310 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
311 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
312 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
313 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
314 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
315 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
316 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
317 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
318 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
319 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
320 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
323 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
325 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
328 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
329 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
330 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
331 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
332 if (Subtarget->is64Bit())
333 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
334 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
335 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
338 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
339 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
340 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
341 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
343 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
344 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
347 if (Subtarget->is64Bit()) {
348 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
349 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
350 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
353 if (Subtarget->hasXMM())
354 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
356 // We may not have a libcall for MEMBARRIER so we should lower this.
357 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
359 // On X86 and X86-64, atomic operations are lowered to locked instructions.
360 // Locked instructions, in turn, have implicit fence semantics (all memory
361 // operations are flushed before issuing the locked instruction, and they
362 // are not buffered), so we can fold away the common pattern of
363 // fence-atomic-fence.
364 setShouldFoldAtomicFences(true);
366 // Expand certain atomics
367 for (unsigned i = 0, e = 4; i != e; ++i) {
369 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
373 if (!Subtarget->is64Bit()) {
374 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
375 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
376 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
377 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
378 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
383 // FIXME - use subtarget debug flags
384 if (!Subtarget->isTargetDarwin() &&
385 !Subtarget->isTargetELF() &&
386 !Subtarget->isTargetCygMing()) {
387 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
390 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
391 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
392 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
393 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
394 if (Subtarget->is64Bit()) {
395 setExceptionPointerRegister(X86::RAX);
396 setExceptionSelectorRegister(X86::RDX);
398 setExceptionPointerRegister(X86::EAX);
399 setExceptionSelectorRegister(X86::EDX);
401 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
402 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
404 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
406 setOperationAction(ISD::TRAP, MVT::Other, Legal);
408 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
409 setOperationAction(ISD::VASTART , MVT::Other, Custom);
410 setOperationAction(ISD::VAEND , MVT::Other, Expand);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::VAARG , MVT::Other, Custom);
413 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
415 setOperationAction(ISD::VAARG , MVT::Other, Expand);
416 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
419 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
420 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
421 if (Subtarget->is64Bit())
422 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
423 if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows())
424 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
428 if (!UseSoftFloat && X86ScalarSSEf64) {
429 // f32 and f64 use SSE.
430 // Set up the FP register classes.
431 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
432 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
434 // Use ANDPD to simulate FABS.
435 setOperationAction(ISD::FABS , MVT::f64, Custom);
436 setOperationAction(ISD::FABS , MVT::f32, Custom);
438 // Use XORP to simulate FNEG.
439 setOperationAction(ISD::FNEG , MVT::f64, Custom);
440 setOperationAction(ISD::FNEG , MVT::f32, Custom);
442 // Use ANDPD and ORPD to simulate FCOPYSIGN.
443 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
444 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
446 // We don't support sin/cos/fmod
447 setOperationAction(ISD::FSIN , MVT::f64, Expand);
448 setOperationAction(ISD::FCOS , MVT::f64, Expand);
449 setOperationAction(ISD::FSIN , MVT::f32, Expand);
450 setOperationAction(ISD::FCOS , MVT::f32, Expand);
452 // Expand FP immediates into loads from the stack, except for the special
454 addLegalFPImmediate(APFloat(+0.0)); // xorpd
455 addLegalFPImmediate(APFloat(+0.0f)); // xorps
456 } else if (!UseSoftFloat && X86ScalarSSEf32) {
457 // Use SSE for f32, x87 for f64.
458 // Set up the FP register classes.
459 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
460 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
462 // Use ANDPS to simulate FABS.
463 setOperationAction(ISD::FABS , MVT::f32, Custom);
465 // Use XORP to simulate FNEG.
466 setOperationAction(ISD::FNEG , MVT::f32, Custom);
468 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
470 // Use ANDPS and ORPS to simulate FCOPYSIGN.
471 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
472 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
474 // We don't support sin/cos/fmod
475 setOperationAction(ISD::FSIN , MVT::f32, Expand);
476 setOperationAction(ISD::FCOS , MVT::f32, Expand);
478 // Special cases we handle for FP constants.
479 addLegalFPImmediate(APFloat(+0.0f)); // xorps
480 addLegalFPImmediate(APFloat(+0.0)); // FLD0
481 addLegalFPImmediate(APFloat(+1.0)); // FLD1
482 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
483 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
486 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
487 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
489 } else if (!UseSoftFloat) {
490 // f32 and f64 in x87.
491 // Set up the FP register classes.
492 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
493 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
495 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
496 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
497 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
498 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
501 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
502 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
504 addLegalFPImmediate(APFloat(+0.0)); // FLD0
505 addLegalFPImmediate(APFloat(+1.0)); // FLD1
506 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
507 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
508 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
509 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
510 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
511 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
514 // Long double always uses X87.
516 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
517 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
518 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
520 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
521 addLegalFPImmediate(TmpFlt); // FLD0
523 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
526 APFloat TmpFlt2(+1.0);
527 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
529 addLegalFPImmediate(TmpFlt2); // FLD1
530 TmpFlt2.changeSign();
531 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
535 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
536 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
540 // Always use a library call for pow.
541 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
542 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
543 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
545 setOperationAction(ISD::FLOG, MVT::f80, Expand);
546 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
547 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
548 setOperationAction(ISD::FEXP, MVT::f80, Expand);
549 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
551 // First set operation action for all vector types to either promote
552 // (for widening) or expand (for scalarization). Then we will selectively
553 // turn on ones that can be effectively codegen'd.
554 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
555 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
556 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
571 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
572 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
605 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
608 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
609 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
610 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
611 setTruncStoreAction((MVT::SimpleValueType)VT,
612 (MVT::SimpleValueType)InnerVT, Expand);
613 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
614 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
615 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
618 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
619 // with -msoft-float, disable use of MMX as well.
620 if (!UseSoftFloat && Subtarget->hasMMX()) {
621 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
622 // No operations on x86mmx supported, everything uses intrinsics.
625 // MMX-sized vectors (other than x86mmx) are expected to be expanded
626 // into smaller operations.
627 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
628 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
629 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
630 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
631 setOperationAction(ISD::AND, MVT::v8i8, Expand);
632 setOperationAction(ISD::AND, MVT::v4i16, Expand);
633 setOperationAction(ISD::AND, MVT::v2i32, Expand);
634 setOperationAction(ISD::AND, MVT::v1i64, Expand);
635 setOperationAction(ISD::OR, MVT::v8i8, Expand);
636 setOperationAction(ISD::OR, MVT::v4i16, Expand);
637 setOperationAction(ISD::OR, MVT::v2i32, Expand);
638 setOperationAction(ISD::OR, MVT::v1i64, Expand);
639 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
640 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
641 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
642 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
643 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
644 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
645 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
646 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
647 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
648 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
649 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
650 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
651 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
652 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
653 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
654 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
655 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
657 if (!UseSoftFloat && Subtarget->hasXMM()) {
658 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
660 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
661 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
662 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
663 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
664 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
665 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
666 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
667 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
668 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
669 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
670 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
671 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
674 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
675 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
677 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
678 // registers cannot be used even for integer operations.
679 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
680 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
681 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
682 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
684 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
685 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
686 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
687 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
688 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
689 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
690 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
691 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
692 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
693 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
694 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
695 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
696 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
697 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
698 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
699 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
701 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
702 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
703 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
704 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
706 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
707 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
708 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
709 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
710 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
712 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
713 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
714 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
715 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
716 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
718 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
719 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
720 EVT VT = (MVT::SimpleValueType)i;
721 // Do not attempt to custom lower non-power-of-2 vectors
722 if (!isPowerOf2_32(VT.getVectorNumElements()))
724 // Do not attempt to custom lower non-128-bit vectors
725 if (!VT.is128BitVector())
727 setOperationAction(ISD::BUILD_VECTOR,
728 VT.getSimpleVT().SimpleTy, Custom);
729 setOperationAction(ISD::VECTOR_SHUFFLE,
730 VT.getSimpleVT().SimpleTy, Custom);
731 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
732 VT.getSimpleVT().SimpleTy, Custom);
735 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
736 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
737 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
738 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
739 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
740 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
742 if (Subtarget->is64Bit()) {
743 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
744 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
747 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
748 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
749 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
752 // Do not attempt to promote non-128-bit vectors
753 if (!VT.is128BitVector())
756 setOperationAction(ISD::AND, SVT, Promote);
757 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
758 setOperationAction(ISD::OR, SVT, Promote);
759 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
760 setOperationAction(ISD::XOR, SVT, Promote);
761 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
762 setOperationAction(ISD::LOAD, SVT, Promote);
763 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
764 setOperationAction(ISD::SELECT, SVT, Promote);
765 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
768 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
770 // Custom lower v2i64 and v2f64 selects.
771 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
772 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
773 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
774 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
776 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
777 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
780 if (Subtarget->hasSSE41()) {
781 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
782 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
783 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
784 setOperationAction(ISD::FRINT, MVT::f32, Legal);
785 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
786 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
787 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
788 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
789 setOperationAction(ISD::FRINT, MVT::f64, Legal);
790 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
792 // FIXME: Do we need to handle scalar-to-vector here?
793 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
795 // Can turn SHL into an integer multiply.
796 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
797 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
799 // i8 and i16 vectors are custom , because the source register and source
800 // source memory operand types are not the same width. f32 vectors are
801 // custom since the immediate controlling the insert encodes additional
803 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
804 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
806 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
808 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
809 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
810 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
813 if (Subtarget->is64Bit()) {
814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
815 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
819 if (Subtarget->hasSSE42())
820 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
822 if (!UseSoftFloat && Subtarget->hasAVX()) {
823 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
824 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
825 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
826 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
827 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
829 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
830 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
831 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
832 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
833 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
834 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
835 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
836 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
837 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
838 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
839 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
840 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
841 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
842 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
843 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
845 // Operations to consider commented out -v16i16 v32i8
846 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
847 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
848 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
849 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
850 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
851 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
852 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
853 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
854 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
855 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
856 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
857 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
859 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
861 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
862 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
863 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
864 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
866 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
867 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
868 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
872 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
873 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
874 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
875 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
876 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
877 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
880 // Not sure we want to do this since there are no 256-bit integer
883 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
884 // This includes 256-bit vectors
885 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
886 EVT VT = (MVT::SimpleValueType)i;
888 // Do not attempt to custom lower non-power-of-2 vectors
889 if (!isPowerOf2_32(VT.getVectorNumElements()))
892 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
893 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
904 // Not sure we want to do this since there are no 256-bit integer
907 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
908 // Including 256-bit vectors
909 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
910 EVT VT = (MVT::SimpleValueType)i;
912 if (!VT.is256BitVector()) {
915 setOperationAction(ISD::AND, VT, Promote);
916 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
917 setOperationAction(ISD::OR, VT, Promote);
918 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
919 setOperationAction(ISD::XOR, VT, Promote);
920 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
921 setOperationAction(ISD::LOAD, VT, Promote);
922 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
923 setOperationAction(ISD::SELECT, VT, Promote);
924 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
927 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
931 // We want to custom lower some of our intrinsics.
932 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
935 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
936 // handle type legalization for these operations here.
938 // FIXME: We really should do custom legalization for addition and
939 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
940 // than generic legalization for 64-bit multiplication-with-overflow, though.
941 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
942 // Add/Sub/Mul with overflow operations are custom lowered.
944 setOperationAction(ISD::SADDO, VT, Custom);
945 setOperationAction(ISD::UADDO, VT, Custom);
946 setOperationAction(ISD::SSUBO, VT, Custom);
947 setOperationAction(ISD::USUBO, VT, Custom);
948 setOperationAction(ISD::SMULO, VT, Custom);
949 setOperationAction(ISD::UMULO, VT, Custom);
952 // There are no 8-bit 3-address imul/mul instructions
953 setOperationAction(ISD::SMULO, MVT::i8, Expand);
954 setOperationAction(ISD::UMULO, MVT::i8, Expand);
956 if (!Subtarget->is64Bit()) {
957 // These libcalls are not available in 32-bit.
958 setLibcallName(RTLIB::SHL_I128, 0);
959 setLibcallName(RTLIB::SRL_I128, 0);
960 setLibcallName(RTLIB::SRA_I128, 0);
963 // We have target-specific dag combine patterns for the following nodes:
964 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
965 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
966 setTargetDAGCombine(ISD::BUILD_VECTOR);
967 setTargetDAGCombine(ISD::SELECT);
968 setTargetDAGCombine(ISD::SHL);
969 setTargetDAGCombine(ISD::SRA);
970 setTargetDAGCombine(ISD::SRL);
971 setTargetDAGCombine(ISD::OR);
972 setTargetDAGCombine(ISD::AND);
973 setTargetDAGCombine(ISD::ADD);
974 setTargetDAGCombine(ISD::SUB);
975 setTargetDAGCombine(ISD::STORE);
976 setTargetDAGCombine(ISD::ZERO_EXTEND);
977 if (Subtarget->is64Bit())
978 setTargetDAGCombine(ISD::MUL);
980 computeRegisterProperties();
982 // On Darwin, -Os means optimize for size without hurting performance,
983 // do not reduce the limit.
984 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
985 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
986 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
987 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
988 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
989 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
990 setPrefLoopAlignment(16);
991 benefitFromCodePlacementOpt = true;
995 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1000 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1001 /// the desired ByVal argument alignment.
1002 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1005 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1006 if (VTy->getBitWidth() == 128)
1008 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1009 unsigned EltAlign = 0;
1010 getMaxByValAlign(ATy->getElementType(), EltAlign);
1011 if (EltAlign > MaxAlign)
1012 MaxAlign = EltAlign;
1013 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1014 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1015 unsigned EltAlign = 0;
1016 getMaxByValAlign(STy->getElementType(i), EltAlign);
1017 if (EltAlign > MaxAlign)
1018 MaxAlign = EltAlign;
1026 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1027 /// function arguments in the caller parameter area. For X86, aggregates
1028 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1029 /// are at 4-byte boundaries.
1030 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1031 if (Subtarget->is64Bit()) {
1032 // Max of 8 and alignment of type.
1033 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1040 if (Subtarget->hasXMM())
1041 getMaxByValAlign(Ty, Align);
1045 /// getOptimalMemOpType - Returns the target specific optimal type for load
1046 /// and store operations as a result of memset, memcpy, and memmove
1047 /// lowering. If DstAlign is zero that means it's safe to destination
1048 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1049 /// means there isn't a need to check it against alignment requirement,
1050 /// probably because the source does not need to be loaded. If
1051 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1052 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1053 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1054 /// constant so it does not need to be loaded.
1055 /// It returns EVT::Other if the type should be determined using generic
1056 /// target-independent logic.
1058 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1059 unsigned DstAlign, unsigned SrcAlign,
1060 bool NonScalarIntSafe,
1062 MachineFunction &MF) const {
1063 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1064 // linux. This is because the stack realignment code can't handle certain
1065 // cases like PR2962. This should be removed when PR2962 is fixed.
1066 const Function *F = MF.getFunction();
1067 if (NonScalarIntSafe &&
1068 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1070 (Subtarget->isUnalignedMemAccessFast() ||
1071 ((DstAlign == 0 || DstAlign >= 16) &&
1072 (SrcAlign == 0 || SrcAlign >= 16))) &&
1073 Subtarget->getStackAlignment() >= 16) {
1074 if (Subtarget->hasSSE2())
1076 if (Subtarget->hasSSE1())
1078 } else if (!MemcpyStrSrc && Size >= 8 &&
1079 !Subtarget->is64Bit() &&
1080 Subtarget->getStackAlignment() >= 8 &&
1081 Subtarget->hasXMMInt()) {
1082 // Do not use f64 to lower memcpy if source is string constant. It's
1083 // better to use i32 to avoid the loads.
1087 if (Subtarget->is64Bit() && Size >= 8)
1092 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1093 /// current function. The returned value is a member of the
1094 /// MachineJumpTableInfo::JTEntryKind enum.
1095 unsigned X86TargetLowering::getJumpTableEncoding() const {
1096 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1098 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1099 Subtarget->isPICStyleGOT())
1100 return MachineJumpTableInfo::EK_Custom32;
1102 // Otherwise, use the normal jump table encoding heuristics.
1103 return TargetLowering::getJumpTableEncoding();
1107 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1108 const MachineBasicBlock *MBB,
1109 unsigned uid,MCContext &Ctx) const{
1110 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1111 Subtarget->isPICStyleGOT());
1112 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1114 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1115 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1118 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1120 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1121 SelectionDAG &DAG) const {
1122 if (!Subtarget->is64Bit())
1123 // This doesn't have DebugLoc associated with it, but is not really the
1124 // same as a Register.
1125 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1129 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1130 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1132 const MCExpr *X86TargetLowering::
1133 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1134 MCContext &Ctx) const {
1135 // X86-64 uses RIP relative addressing based on the jump table label.
1136 if (Subtarget->isPICStyleRIPRel())
1137 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1139 // Otherwise, the reference is relative to the PIC base.
1140 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1143 /// getFunctionAlignment - Return the Log2 alignment of this function.
1144 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1145 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1148 // FIXME: Why this routine is here? Move to RegInfo!
1149 std::pair<const TargetRegisterClass*, uint8_t>
1150 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1151 const TargetRegisterClass *RRC = 0;
1153 switch (VT.getSimpleVT().SimpleTy) {
1155 return TargetLowering::findRepresentativeClass(VT);
1156 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1157 RRC = (Subtarget->is64Bit()
1158 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1161 RRC = X86::VR64RegisterClass;
1163 case MVT::f32: case MVT::f64:
1164 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1165 case MVT::v4f32: case MVT::v2f64:
1166 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1168 RRC = X86::VR128RegisterClass;
1171 return std::make_pair(RRC, Cost);
1174 // FIXME: Why this routine is here? Move to RegInfo!
1176 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1177 MachineFunction &MF) const {
1178 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1180 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
1181 switch (RC->getID()) {
1184 case X86::GR32RegClassID:
1186 case X86::GR64RegClassID:
1188 case X86::VR128RegClassID:
1189 return Subtarget->is64Bit() ? 10 : 4;
1190 case X86::VR64RegClassID:
1195 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1196 unsigned &Offset) const {
1197 if (!Subtarget->isTargetLinux())
1200 if (Subtarget->is64Bit()) {
1201 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1203 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1216 //===----------------------------------------------------------------------===//
1217 // Return Value Calling Convention Implementation
1218 //===----------------------------------------------------------------------===//
1220 #include "X86GenCallingConv.inc"
1223 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1224 const SmallVectorImpl<ISD::OutputArg> &Outs,
1225 LLVMContext &Context) const {
1226 SmallVector<CCValAssign, 16> RVLocs;
1227 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1229 return CCInfo.CheckReturn(Outs, RetCC_X86);
1233 X86TargetLowering::LowerReturn(SDValue Chain,
1234 CallingConv::ID CallConv, bool isVarArg,
1235 const SmallVectorImpl<ISD::OutputArg> &Outs,
1236 const SmallVectorImpl<SDValue> &OutVals,
1237 DebugLoc dl, SelectionDAG &DAG) const {
1238 MachineFunction &MF = DAG.getMachineFunction();
1239 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1241 SmallVector<CCValAssign, 16> RVLocs;
1242 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1243 RVLocs, *DAG.getContext());
1244 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1246 // Add the regs to the liveout set for the function.
1247 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1248 for (unsigned i = 0; i != RVLocs.size(); ++i)
1249 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1250 MRI.addLiveOut(RVLocs[i].getLocReg());
1254 SmallVector<SDValue, 6> RetOps;
1255 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1256 // Operand #1 = Bytes To Pop
1257 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1260 // Copy the result values into the output registers.
1261 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1262 CCValAssign &VA = RVLocs[i];
1263 assert(VA.isRegLoc() && "Can only return in registers!");
1264 SDValue ValToCopy = OutVals[i];
1265 EVT ValVT = ValToCopy.getValueType();
1267 // If this is x86-64, and we disabled SSE, we can't return FP values,
1268 // or SSE or MMX vectors.
1269 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1270 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1271 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1272 report_fatal_error("SSE register return with SSE disabled");
1274 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1275 // llvm-gcc has never done it right and no one has noticed, so this
1276 // should be OK for now.
1277 if (ValVT == MVT::f64 &&
1278 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1279 report_fatal_error("SSE2 register return with SSE2 disabled");
1281 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1282 // the RET instruction and handled by the FP Stackifier.
1283 if (VA.getLocReg() == X86::ST0 ||
1284 VA.getLocReg() == X86::ST1) {
1285 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1286 // change the value to the FP stack register class.
1287 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1288 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1289 RetOps.push_back(ValToCopy);
1290 // Don't emit a copytoreg.
1294 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1295 // which is returned in RAX / RDX.
1296 if (Subtarget->is64Bit()) {
1297 if (ValVT == MVT::x86mmx) {
1298 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1299 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1300 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1302 // If we don't have SSE2 available, convert to v4f32 so the generated
1303 // register is legal.
1304 if (!Subtarget->hasSSE2())
1305 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1310 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1311 Flag = Chain.getValue(1);
1314 // The x86-64 ABI for returning structs by value requires that we copy
1315 // the sret argument into %rax for the return. We saved the argument into
1316 // a virtual register in the entry block, so now we copy the value out
1318 if (Subtarget->is64Bit() &&
1319 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1320 MachineFunction &MF = DAG.getMachineFunction();
1321 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1322 unsigned Reg = FuncInfo->getSRetReturnReg();
1324 "SRetReturnReg should have been set in LowerFormalArguments().");
1325 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1327 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1328 Flag = Chain.getValue(1);
1330 // RAX now acts like a return value.
1331 MRI.addLiveOut(X86::RAX);
1334 RetOps[0] = Chain; // Update chain.
1336 // Add the flag if we have it.
1338 RetOps.push_back(Flag);
1340 return DAG.getNode(X86ISD::RET_FLAG, dl,
1341 MVT::Other, &RetOps[0], RetOps.size());
1344 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1345 if (N->getNumValues() != 1)
1347 if (!N->hasNUsesOfValue(1, 0))
1350 SDNode *Copy = *N->use_begin();
1351 if (Copy->getOpcode() != ISD::CopyToReg &&
1352 Copy->getOpcode() != ISD::FP_EXTEND)
1355 bool HasRet = false;
1356 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1358 if (UI->getOpcode() != X86ISD::RET_FLAG)
1366 /// LowerCallResult - Lower the result values of a call into the
1367 /// appropriate copies out of appropriate physical registers.
1370 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1371 CallingConv::ID CallConv, bool isVarArg,
1372 const SmallVectorImpl<ISD::InputArg> &Ins,
1373 DebugLoc dl, SelectionDAG &DAG,
1374 SmallVectorImpl<SDValue> &InVals) const {
1376 // Assign locations to each value returned by this call.
1377 SmallVector<CCValAssign, 16> RVLocs;
1378 bool Is64Bit = Subtarget->is64Bit();
1379 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1380 RVLocs, *DAG.getContext());
1381 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1383 // Copy all of the result registers out of their specified physreg.
1384 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1385 CCValAssign &VA = RVLocs[i];
1386 EVT CopyVT = VA.getValVT();
1388 // If this is x86-64, and we disabled SSE, we can't return FP values
1389 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1390 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1391 report_fatal_error("SSE register return with SSE disabled");
1396 // If this is a call to a function that returns an fp value on the floating
1397 // point stack, we must guarantee the the value is popped from the stack, so
1398 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1399 // if the return value is not used. We use the FpGET_ST0 instructions
1401 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1402 // If we prefer to use the value in xmm registers, copy it out as f80 and
1403 // use a truncate to move it from fp stack reg to xmm reg.
1404 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1405 bool isST0 = VA.getLocReg() == X86::ST0;
1407 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1408 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1409 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1410 SDValue Ops[] = { Chain, InFlag };
1411 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Glue,
1413 Val = Chain.getValue(0);
1415 // Round the f80 to the right size, which also moves it to the appropriate
1417 if (CopyVT != VA.getValVT())
1418 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1419 // This truncation won't change the value.
1420 DAG.getIntPtrConstant(1));
1421 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1422 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1423 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1424 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1425 MVT::v2i64, InFlag).getValue(1);
1426 Val = Chain.getValue(0);
1427 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1428 Val, DAG.getConstant(0, MVT::i64));
1430 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1431 MVT::i64, InFlag).getValue(1);
1432 Val = Chain.getValue(0);
1434 Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val);
1436 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1437 CopyVT, InFlag).getValue(1);
1438 Val = Chain.getValue(0);
1440 InFlag = Chain.getValue(2);
1441 InVals.push_back(Val);
1448 //===----------------------------------------------------------------------===//
1449 // C & StdCall & Fast Calling Convention implementation
1450 //===----------------------------------------------------------------------===//
1451 // StdCall calling convention seems to be standard for many Windows' API
1452 // routines and around. It differs from C calling convention just a little:
1453 // callee should clean up the stack, not caller. Symbols should be also
1454 // decorated in some fancy way :) It doesn't support any vector arguments.
1455 // For info on fast calling convention see Fast Calling Convention (tail call)
1456 // implementation LowerX86_32FastCCCallTo.
1458 /// CallIsStructReturn - Determines whether a call uses struct return
1460 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1464 return Outs[0].Flags.isSRet();
1467 /// ArgsAreStructReturn - Determines whether a function uses struct
1468 /// return semantics.
1470 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1474 return Ins[0].Flags.isSRet();
1477 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1478 /// by "Src" to address "Dst" with size and alignment information specified by
1479 /// the specific parameter attribute. The copy will be passed as a byval
1480 /// function parameter.
1482 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1483 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1485 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1487 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1488 /*isVolatile*/false, /*AlwaysInline=*/true,
1489 MachinePointerInfo(), MachinePointerInfo());
1492 /// IsTailCallConvention - Return true if the calling convention is one that
1493 /// supports tail call optimization.
1494 static bool IsTailCallConvention(CallingConv::ID CC) {
1495 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1498 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1499 /// a tailcall target by changing its ABI.
1500 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1501 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1505 X86TargetLowering::LowerMemArgument(SDValue Chain,
1506 CallingConv::ID CallConv,
1507 const SmallVectorImpl<ISD::InputArg> &Ins,
1508 DebugLoc dl, SelectionDAG &DAG,
1509 const CCValAssign &VA,
1510 MachineFrameInfo *MFI,
1512 // Create the nodes corresponding to a load from this parameter slot.
1513 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1514 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1515 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1518 // If value is passed by pointer we have address passed instead of the value
1520 if (VA.getLocInfo() == CCValAssign::Indirect)
1521 ValVT = VA.getLocVT();
1523 ValVT = VA.getValVT();
1525 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1526 // changed with more analysis.
1527 // In case of tail call optimization mark all arguments mutable. Since they
1528 // could be overwritten by lowering of arguments in case of a tail call.
1529 if (Flags.isByVal()) {
1530 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1531 VA.getLocMemOffset(), isImmutable);
1532 return DAG.getFrameIndex(FI, getPointerTy());
1534 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1535 VA.getLocMemOffset(), isImmutable);
1536 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1537 return DAG.getLoad(ValVT, dl, Chain, FIN,
1538 MachinePointerInfo::getFixedStack(FI),
1544 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1545 CallingConv::ID CallConv,
1547 const SmallVectorImpl<ISD::InputArg> &Ins,
1550 SmallVectorImpl<SDValue> &InVals)
1552 MachineFunction &MF = DAG.getMachineFunction();
1553 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1555 const Function* Fn = MF.getFunction();
1556 if (Fn->hasExternalLinkage() &&
1557 Subtarget->isTargetCygMing() &&
1558 Fn->getName() == "main")
1559 FuncInfo->setForceFramePointer(true);
1561 MachineFrameInfo *MFI = MF.getFrameInfo();
1562 bool Is64Bit = Subtarget->is64Bit();
1563 bool IsWin64 = Subtarget->isTargetWin64();
1565 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1566 "Var args not supported with calling convention fastcc or ghc");
1568 // Assign locations to all of the incoming arguments.
1569 SmallVector<CCValAssign, 16> ArgLocs;
1570 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1571 ArgLocs, *DAG.getContext());
1572 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1574 unsigned LastVal = ~0U;
1576 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1577 CCValAssign &VA = ArgLocs[i];
1578 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1580 assert(VA.getValNo() != LastVal &&
1581 "Don't support value assigned to multiple locs yet");
1582 LastVal = VA.getValNo();
1584 if (VA.isRegLoc()) {
1585 EVT RegVT = VA.getLocVT();
1586 TargetRegisterClass *RC = NULL;
1587 if (RegVT == MVT::i32)
1588 RC = X86::GR32RegisterClass;
1589 else if (Is64Bit && RegVT == MVT::i64)
1590 RC = X86::GR64RegisterClass;
1591 else if (RegVT == MVT::f32)
1592 RC = X86::FR32RegisterClass;
1593 else if (RegVT == MVT::f64)
1594 RC = X86::FR64RegisterClass;
1595 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1596 RC = X86::VR256RegisterClass;
1597 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1598 RC = X86::VR128RegisterClass;
1599 else if (RegVT == MVT::x86mmx)
1600 RC = X86::VR64RegisterClass;
1602 llvm_unreachable("Unknown argument type!");
1604 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1605 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1607 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1608 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1610 if (VA.getLocInfo() == CCValAssign::SExt)
1611 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1612 DAG.getValueType(VA.getValVT()));
1613 else if (VA.getLocInfo() == CCValAssign::ZExt)
1614 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1615 DAG.getValueType(VA.getValVT()));
1616 else if (VA.getLocInfo() == CCValAssign::BCvt)
1617 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1619 if (VA.isExtInLoc()) {
1620 // Handle MMX values passed in XMM regs.
1621 if (RegVT.isVector()) {
1622 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1625 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1628 assert(VA.isMemLoc());
1629 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1632 // If value is passed via pointer - do a load.
1633 if (VA.getLocInfo() == CCValAssign::Indirect)
1634 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1635 MachinePointerInfo(), false, false, 0);
1637 InVals.push_back(ArgValue);
1640 // The x86-64 ABI for returning structs by value requires that we copy
1641 // the sret argument into %rax for the return. Save the argument into
1642 // a virtual register so that we can access it from the return points.
1643 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1644 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1645 unsigned Reg = FuncInfo->getSRetReturnReg();
1647 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1648 FuncInfo->setSRetReturnReg(Reg);
1650 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1651 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1654 unsigned StackSize = CCInfo.getNextStackOffset();
1655 // Align stack specially for tail calls.
1656 if (FuncIsMadeTailCallSafe(CallConv))
1657 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1659 // If the function takes variable number of arguments, make a frame index for
1660 // the start of the first vararg value... for expansion of llvm.va_start.
1662 if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1663 CallConv != CallingConv::X86_ThisCall))) {
1664 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1667 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1669 // FIXME: We should really autogenerate these arrays
1670 static const unsigned GPR64ArgRegsWin64[] = {
1671 X86::RCX, X86::RDX, X86::R8, X86::R9
1673 static const unsigned GPR64ArgRegs64Bit[] = {
1674 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1676 static const unsigned XMMArgRegs64Bit[] = {
1677 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1678 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1680 const unsigned *GPR64ArgRegs;
1681 unsigned NumXMMRegs = 0;
1684 // The XMM registers which might contain var arg parameters are shadowed
1685 // in their paired GPR. So we only need to save the GPR to their home
1687 TotalNumIntRegs = 4;
1688 GPR64ArgRegs = GPR64ArgRegsWin64;
1690 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1691 GPR64ArgRegs = GPR64ArgRegs64Bit;
1693 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1695 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1698 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1699 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1700 "SSE register cannot be used when SSE is disabled!");
1701 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1702 "SSE register cannot be used when SSE is disabled!");
1703 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1704 // Kernel mode asks for SSE to be disabled, so don't push them
1706 TotalNumXMMRegs = 0;
1709 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1710 // Get to the caller-allocated home save location. Add 8 to account
1711 // for the return address.
1712 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1713 FuncInfo->setRegSaveFrameIndex(
1714 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1715 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1717 // For X86-64, if there are vararg parameters that are passed via
1718 // registers, then we must store them to their spots on the stack so they
1719 // may be loaded by deferencing the result of va_next.
1720 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1721 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1722 FuncInfo->setRegSaveFrameIndex(
1723 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1727 // Store the integer parameter registers.
1728 SmallVector<SDValue, 8> MemOps;
1729 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1731 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1732 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1733 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1734 DAG.getIntPtrConstant(Offset));
1735 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1736 X86::GR64RegisterClass);
1737 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1739 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1740 MachinePointerInfo::getFixedStack(
1741 FuncInfo->getRegSaveFrameIndex(), Offset),
1743 MemOps.push_back(Store);
1747 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1748 // Now store the XMM (fp + vector) parameter registers.
1749 SmallVector<SDValue, 11> SaveXMMOps;
1750 SaveXMMOps.push_back(Chain);
1752 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1753 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1754 SaveXMMOps.push_back(ALVal);
1756 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1757 FuncInfo->getRegSaveFrameIndex()));
1758 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1759 FuncInfo->getVarArgsFPOffset()));
1761 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1762 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1763 X86::VR128RegisterClass);
1764 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1765 SaveXMMOps.push_back(Val);
1767 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1769 &SaveXMMOps[0], SaveXMMOps.size()));
1772 if (!MemOps.empty())
1773 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1774 &MemOps[0], MemOps.size());
1778 // Some CCs need callee pop.
1779 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1780 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1782 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1783 // If this is an sret function, the return should pop the hidden pointer.
1784 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1785 FuncInfo->setBytesToPopOnReturn(4);
1789 // RegSaveFrameIndex is X86-64 only.
1790 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1791 if (CallConv == CallingConv::X86_FastCall ||
1792 CallConv == CallingConv::X86_ThisCall)
1793 // fastcc functions can't have varargs.
1794 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1801 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1802 SDValue StackPtr, SDValue Arg,
1803 DebugLoc dl, SelectionDAG &DAG,
1804 const CCValAssign &VA,
1805 ISD::ArgFlagsTy Flags) const {
1806 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1807 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1808 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1809 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1810 if (Flags.isByVal())
1811 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1813 return DAG.getStore(Chain, dl, Arg, PtrOff,
1814 MachinePointerInfo::getStack(LocMemOffset),
1818 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1819 /// optimization is performed and it is required.
1821 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1822 SDValue &OutRetAddr, SDValue Chain,
1823 bool IsTailCall, bool Is64Bit,
1824 int FPDiff, DebugLoc dl) const {
1825 // Adjust the Return address stack slot.
1826 EVT VT = getPointerTy();
1827 OutRetAddr = getReturnAddressFrameIndex(DAG);
1829 // Load the "old" Return address.
1830 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1832 return SDValue(OutRetAddr.getNode(), 1);
1835 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1836 /// optimization is performed and it is required (FPDiff!=0).
1838 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1839 SDValue Chain, SDValue RetAddrFrIdx,
1840 bool Is64Bit, int FPDiff, DebugLoc dl) {
1841 // Store the return address to the appropriate stack slot.
1842 if (!FPDiff) return Chain;
1843 // Calculate the new stack slot for the return address.
1844 int SlotSize = Is64Bit ? 8 : 4;
1845 int NewReturnAddrFI =
1846 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1847 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1848 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1849 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1850 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1856 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1857 CallingConv::ID CallConv, bool isVarArg,
1859 const SmallVectorImpl<ISD::OutputArg> &Outs,
1860 const SmallVectorImpl<SDValue> &OutVals,
1861 const SmallVectorImpl<ISD::InputArg> &Ins,
1862 DebugLoc dl, SelectionDAG &DAG,
1863 SmallVectorImpl<SDValue> &InVals) const {
1864 MachineFunction &MF = DAG.getMachineFunction();
1865 bool Is64Bit = Subtarget->is64Bit();
1866 bool IsStructRet = CallIsStructReturn(Outs);
1867 bool IsSibcall = false;
1870 // Check if it's really possible to do a tail call.
1871 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1872 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1873 Outs, OutVals, Ins, DAG);
1875 // Sibcalls are automatically detected tailcalls which do not require
1877 if (!GuaranteedTailCallOpt && isTailCall)
1884 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1885 "Var args not supported with calling convention fastcc or ghc");
1887 // Analyze operands of the call, assigning locations to each operand.
1888 SmallVector<CCValAssign, 16> ArgLocs;
1889 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1890 ArgLocs, *DAG.getContext());
1891 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
1893 // Get a count of how many bytes are to be pushed on the stack.
1894 unsigned NumBytes = CCInfo.getNextStackOffset();
1896 // This is a sibcall. The memory operands are available in caller's
1897 // own caller's stack.
1899 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1900 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1903 if (isTailCall && !IsSibcall) {
1904 // Lower arguments at fp - stackoffset + fpdiff.
1905 unsigned NumBytesCallerPushed =
1906 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1907 FPDiff = NumBytesCallerPushed - NumBytes;
1909 // Set the delta of movement of the returnaddr stackslot.
1910 // But only set if delta is greater than previous delta.
1911 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1912 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1916 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1918 SDValue RetAddrFrIdx;
1919 // Load return adress for tail calls.
1920 if (isTailCall && FPDiff)
1921 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1922 Is64Bit, FPDiff, dl);
1924 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1925 SmallVector<SDValue, 8> MemOpChains;
1928 // Walk the register/memloc assignments, inserting copies/loads. In the case
1929 // of tail call optimization arguments are handle later.
1930 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1931 CCValAssign &VA = ArgLocs[i];
1932 EVT RegVT = VA.getLocVT();
1933 SDValue Arg = OutVals[i];
1934 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1935 bool isByVal = Flags.isByVal();
1937 // Promote the value if needed.
1938 switch (VA.getLocInfo()) {
1939 default: llvm_unreachable("Unknown loc info!");
1940 case CCValAssign::Full: break;
1941 case CCValAssign::SExt:
1942 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1944 case CCValAssign::ZExt:
1945 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1947 case CCValAssign::AExt:
1948 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1949 // Special case: passing MMX values in XMM registers.
1950 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
1951 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1952 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1954 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1956 case CCValAssign::BCvt:
1957 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
1959 case CCValAssign::Indirect: {
1960 // Store the argument.
1961 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1962 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1963 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1964 MachinePointerInfo::getFixedStack(FI),
1971 if (VA.isRegLoc()) {
1972 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1973 if (isVarArg && Subtarget->isTargetWin64()) {
1974 // Win64 ABI requires argument XMM reg to be copied to the corresponding
1975 // shadow reg if callee is a varargs function.
1976 unsigned ShadowReg = 0;
1977 switch (VA.getLocReg()) {
1978 case X86::XMM0: ShadowReg = X86::RCX; break;
1979 case X86::XMM1: ShadowReg = X86::RDX; break;
1980 case X86::XMM2: ShadowReg = X86::R8; break;
1981 case X86::XMM3: ShadowReg = X86::R9; break;
1984 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
1986 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1987 assert(VA.isMemLoc());
1988 if (StackPtr.getNode() == 0)
1989 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1990 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1991 dl, DAG, VA, Flags));
1995 if (!MemOpChains.empty())
1996 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1997 &MemOpChains[0], MemOpChains.size());
1999 // Build a sequence of copy-to-reg nodes chained together with token chain
2000 // and flag operands which copy the outgoing args into registers.
2002 // Tail call byval lowering might overwrite argument registers so in case of
2003 // tail call optimization the copies to registers are lowered later.
2005 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2006 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2007 RegsToPass[i].second, InFlag);
2008 InFlag = Chain.getValue(1);
2011 if (Subtarget->isPICStyleGOT()) {
2012 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2015 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2016 DAG.getNode(X86ISD::GlobalBaseReg,
2017 DebugLoc(), getPointerTy()),
2019 InFlag = Chain.getValue(1);
2021 // If we are tail calling and generating PIC/GOT style code load the
2022 // address of the callee into ECX. The value in ecx is used as target of
2023 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2024 // for tail calls on PIC/GOT architectures. Normally we would just put the
2025 // address of GOT into ebx and then call target@PLT. But for tail calls
2026 // ebx would be restored (since ebx is callee saved) before jumping to the
2029 // Note: The actual moving to ECX is done further down.
2030 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2031 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2032 !G->getGlobal()->hasProtectedVisibility())
2033 Callee = LowerGlobalAddress(Callee, DAG);
2034 else if (isa<ExternalSymbolSDNode>(Callee))
2035 Callee = LowerExternalSymbol(Callee, DAG);
2039 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2040 // From AMD64 ABI document:
2041 // For calls that may call functions that use varargs or stdargs
2042 // (prototype-less calls or calls to functions containing ellipsis (...) in
2043 // the declaration) %al is used as hidden argument to specify the number
2044 // of SSE registers used. The contents of %al do not need to match exactly
2045 // the number of registers, but must be an ubound on the number of SSE
2046 // registers used and is in the range 0 - 8 inclusive.
2048 // Count the number of XMM registers allocated.
2049 static const unsigned XMMArgRegs[] = {
2050 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2051 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2053 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2054 assert((Subtarget->hasXMM() || !NumXMMRegs)
2055 && "SSE registers cannot be used when SSE is disabled");
2057 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2058 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2059 InFlag = Chain.getValue(1);
2063 // For tail calls lower the arguments to the 'real' stack slot.
2065 // Force all the incoming stack arguments to be loaded from the stack
2066 // before any new outgoing arguments are stored to the stack, because the
2067 // outgoing stack slots may alias the incoming argument stack slots, and
2068 // the alias isn't otherwise explicit. This is slightly more conservative
2069 // than necessary, because it means that each store effectively depends
2070 // on every argument instead of just those arguments it would clobber.
2071 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2073 SmallVector<SDValue, 8> MemOpChains2;
2076 // Do not flag preceeding copytoreg stuff together with the following stuff.
2078 if (GuaranteedTailCallOpt) {
2079 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2080 CCValAssign &VA = ArgLocs[i];
2083 assert(VA.isMemLoc());
2084 SDValue Arg = OutVals[i];
2085 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2086 // Create frame index.
2087 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2088 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2089 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2090 FIN = DAG.getFrameIndex(FI, getPointerTy());
2092 if (Flags.isByVal()) {
2093 // Copy relative to framepointer.
2094 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2095 if (StackPtr.getNode() == 0)
2096 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2098 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2100 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2104 // Store relative to framepointer.
2105 MemOpChains2.push_back(
2106 DAG.getStore(ArgChain, dl, Arg, FIN,
2107 MachinePointerInfo::getFixedStack(FI),
2113 if (!MemOpChains2.empty())
2114 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2115 &MemOpChains2[0], MemOpChains2.size());
2117 // Copy arguments to their registers.
2118 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2119 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2120 RegsToPass[i].second, InFlag);
2121 InFlag = Chain.getValue(1);
2125 // Store the return address to the appropriate stack slot.
2126 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2130 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2131 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2132 // In the 64-bit large code model, we have to make all calls
2133 // through a register, since the call instruction's 32-bit
2134 // pc-relative offset may not be large enough to hold the whole
2136 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2137 // If the callee is a GlobalAddress node (quite common, every direct call
2138 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2141 // We should use extra load for direct calls to dllimported functions in
2143 const GlobalValue *GV = G->getGlobal();
2144 if (!GV->hasDLLImportLinkage()) {
2145 unsigned char OpFlags = 0;
2147 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2148 // external symbols most go through the PLT in PIC mode. If the symbol
2149 // has hidden or protected visibility, or if it is static or local, then
2150 // we don't need to use the PLT - we can directly call it.
2151 if (Subtarget->isTargetELF() &&
2152 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2153 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2154 OpFlags = X86II::MO_PLT;
2155 } else if (Subtarget->isPICStyleStubAny() &&
2156 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2157 Subtarget->getDarwinVers() < 9) {
2158 // PC-relative references to external symbols should go through $stub,
2159 // unless we're building with the leopard linker or later, which
2160 // automatically synthesizes these stubs.
2161 OpFlags = X86II::MO_DARWIN_STUB;
2164 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2165 G->getOffset(), OpFlags);
2167 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2168 unsigned char OpFlags = 0;
2170 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2171 // external symbols should go through the PLT.
2172 if (Subtarget->isTargetELF() &&
2173 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2174 OpFlags = X86II::MO_PLT;
2175 } else if (Subtarget->isPICStyleStubAny() &&
2176 Subtarget->getDarwinVers() < 9) {
2177 // PC-relative references to external symbols should go through $stub,
2178 // unless we're building with the leopard linker or later, which
2179 // automatically synthesizes these stubs.
2180 OpFlags = X86II::MO_DARWIN_STUB;
2183 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2187 // Returns a chain & a flag for retval copy to use.
2188 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2189 SmallVector<SDValue, 8> Ops;
2191 if (!IsSibcall && isTailCall) {
2192 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2193 DAG.getIntPtrConstant(0, true), InFlag);
2194 InFlag = Chain.getValue(1);
2197 Ops.push_back(Chain);
2198 Ops.push_back(Callee);
2201 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2203 // Add argument registers to the end of the list so that they are known live
2205 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2206 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2207 RegsToPass[i].second.getValueType()));
2209 // Add an implicit use GOT pointer in EBX.
2210 if (!isTailCall && Subtarget->isPICStyleGOT())
2211 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2213 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2214 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2215 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2217 if (InFlag.getNode())
2218 Ops.push_back(InFlag);
2222 //// If this is the first return lowered for this function, add the regs
2223 //// to the liveout set for the function.
2224 // This isn't right, although it's probably harmless on x86; liveouts
2225 // should be computed from returns not tail calls. Consider a void
2226 // function making a tail call to a function returning int.
2227 return DAG.getNode(X86ISD::TC_RETURN, dl,
2228 NodeTys, &Ops[0], Ops.size());
2231 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2232 InFlag = Chain.getValue(1);
2234 // Create the CALLSEQ_END node.
2235 unsigned NumBytesForCalleeToPush;
2236 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2237 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2238 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2239 // If this is a call to a struct-return function, the callee
2240 // pops the hidden struct pointer, so we have to push it back.
2241 // This is common for Darwin/X86, Linux & Mingw32 targets.
2242 NumBytesForCalleeToPush = 4;
2244 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2246 // Returns a flag for retval copy to use.
2248 Chain = DAG.getCALLSEQ_END(Chain,
2249 DAG.getIntPtrConstant(NumBytes, true),
2250 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2253 InFlag = Chain.getValue(1);
2256 // Handle result values, copying them out of physregs into vregs that we
2258 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2259 Ins, dl, DAG, InVals);
2263 //===----------------------------------------------------------------------===//
2264 // Fast Calling Convention (tail call) implementation
2265 //===----------------------------------------------------------------------===//
2267 // Like std call, callee cleans arguments, convention except that ECX is
2268 // reserved for storing the tail called function address. Only 2 registers are
2269 // free for argument passing (inreg). Tail call optimization is performed
2271 // * tailcallopt is enabled
2272 // * caller/callee are fastcc
2273 // On X86_64 architecture with GOT-style position independent code only local
2274 // (within module) calls are supported at the moment.
2275 // To keep the stack aligned according to platform abi the function
2276 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2277 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2278 // If a tail called function callee has more arguments than the caller the
2279 // caller needs to make sure that there is room to move the RETADDR to. This is
2280 // achieved by reserving an area the size of the argument delta right after the
2281 // original REtADDR, but before the saved framepointer or the spilled registers
2282 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2294 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2295 /// for a 16 byte align requirement.
2297 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2298 SelectionDAG& DAG) const {
2299 MachineFunction &MF = DAG.getMachineFunction();
2300 const TargetMachine &TM = MF.getTarget();
2301 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2302 unsigned StackAlignment = TFI.getStackAlignment();
2303 uint64_t AlignMask = StackAlignment - 1;
2304 int64_t Offset = StackSize;
2305 uint64_t SlotSize = TD->getPointerSize();
2306 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2307 // Number smaller than 12 so just add the difference.
2308 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2310 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2311 Offset = ((~AlignMask) & Offset) + StackAlignment +
2312 (StackAlignment-SlotSize);
2317 /// MatchingStackOffset - Return true if the given stack call argument is
2318 /// already available in the same position (relatively) of the caller's
2319 /// incoming argument stack.
2321 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2322 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2323 const X86InstrInfo *TII) {
2324 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2326 if (Arg.getOpcode() == ISD::CopyFromReg) {
2327 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2328 if (!TargetRegisterInfo::isVirtualRegister(VR))
2330 MachineInstr *Def = MRI->getVRegDef(VR);
2333 if (!Flags.isByVal()) {
2334 if (!TII->isLoadFromStackSlot(Def, FI))
2337 unsigned Opcode = Def->getOpcode();
2338 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2339 Def->getOperand(1).isFI()) {
2340 FI = Def->getOperand(1).getIndex();
2341 Bytes = Flags.getByValSize();
2345 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2346 if (Flags.isByVal())
2347 // ByVal argument is passed in as a pointer but it's now being
2348 // dereferenced. e.g.
2349 // define @foo(%struct.X* %A) {
2350 // tail call @bar(%struct.X* byval %A)
2353 SDValue Ptr = Ld->getBasePtr();
2354 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2357 FI = FINode->getIndex();
2361 assert(FI != INT_MAX);
2362 if (!MFI->isFixedObjectIndex(FI))
2364 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2367 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2368 /// for tail call optimization. Targets which want to do tail call
2369 /// optimization should implement this function.
2371 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2372 CallingConv::ID CalleeCC,
2374 bool isCalleeStructRet,
2375 bool isCallerStructRet,
2376 const SmallVectorImpl<ISD::OutputArg> &Outs,
2377 const SmallVectorImpl<SDValue> &OutVals,
2378 const SmallVectorImpl<ISD::InputArg> &Ins,
2379 SelectionDAG& DAG) const {
2380 if (!IsTailCallConvention(CalleeCC) &&
2381 CalleeCC != CallingConv::C)
2384 // If -tailcallopt is specified, make fastcc functions tail-callable.
2385 const MachineFunction &MF = DAG.getMachineFunction();
2386 const Function *CallerF = DAG.getMachineFunction().getFunction();
2387 CallingConv::ID CallerCC = CallerF->getCallingConv();
2388 bool CCMatch = CallerCC == CalleeCC;
2390 if (GuaranteedTailCallOpt) {
2391 if (IsTailCallConvention(CalleeCC) && CCMatch)
2396 // Look for obvious safe cases to perform tail call optimization that do not
2397 // require ABI changes. This is what gcc calls sibcall.
2399 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2400 // emit a special epilogue.
2401 if (RegInfo->needsStackRealignment(MF))
2404 // Do not sibcall optimize vararg calls unless the call site is not passing
2406 if (isVarArg && !Outs.empty())
2409 // Also avoid sibcall optimization if either caller or callee uses struct
2410 // return semantics.
2411 if (isCalleeStructRet || isCallerStructRet)
2414 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2415 // Therefore if it's not used by the call it is not safe to optimize this into
2417 bool Unused = false;
2418 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2425 SmallVector<CCValAssign, 16> RVLocs;
2426 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2427 RVLocs, *DAG.getContext());
2428 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2429 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2430 CCValAssign &VA = RVLocs[i];
2431 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2436 // If the calling conventions do not match, then we'd better make sure the
2437 // results are returned in the same way as what the caller expects.
2439 SmallVector<CCValAssign, 16> RVLocs1;
2440 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2441 RVLocs1, *DAG.getContext());
2442 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2444 SmallVector<CCValAssign, 16> RVLocs2;
2445 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2446 RVLocs2, *DAG.getContext());
2447 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2449 if (RVLocs1.size() != RVLocs2.size())
2451 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2452 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2454 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2456 if (RVLocs1[i].isRegLoc()) {
2457 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2460 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2466 // If the callee takes no arguments then go on to check the results of the
2468 if (!Outs.empty()) {
2469 // Check if stack adjustment is needed. For now, do not do this if any
2470 // argument is passed on the stack.
2471 SmallVector<CCValAssign, 16> ArgLocs;
2472 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2473 ArgLocs, *DAG.getContext());
2474 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2475 if (CCInfo.getNextStackOffset()) {
2476 MachineFunction &MF = DAG.getMachineFunction();
2477 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2479 if (Subtarget->isTargetWin64())
2480 // Win64 ABI has additional complications.
2483 // Check if the arguments are already laid out in the right way as
2484 // the caller's fixed stack objects.
2485 MachineFrameInfo *MFI = MF.getFrameInfo();
2486 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2487 const X86InstrInfo *TII =
2488 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2489 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2490 CCValAssign &VA = ArgLocs[i];
2491 SDValue Arg = OutVals[i];
2492 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2493 if (VA.getLocInfo() == CCValAssign::Indirect)
2495 if (!VA.isRegLoc()) {
2496 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2503 // If the tailcall address may be in a register, then make sure it's
2504 // possible to register allocate for it. In 32-bit, the call address can
2505 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2506 // callee-saved registers are restored. These happen to be the same
2507 // registers used to pass 'inreg' arguments so watch out for those.
2508 if (!Subtarget->is64Bit() &&
2509 !isa<GlobalAddressSDNode>(Callee) &&
2510 !isa<ExternalSymbolSDNode>(Callee)) {
2511 unsigned NumInRegs = 0;
2512 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2513 CCValAssign &VA = ArgLocs[i];
2516 unsigned Reg = VA.getLocReg();
2519 case X86::EAX: case X86::EDX: case X86::ECX:
2520 if (++NumInRegs == 3)
2528 // An stdcall caller is expected to clean up its arguments; the callee
2529 // isn't going to do that.
2530 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2537 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2538 return X86::createFastISel(funcInfo);
2542 //===----------------------------------------------------------------------===//
2543 // Other Lowering Hooks
2544 //===----------------------------------------------------------------------===//
2546 static bool MayFoldLoad(SDValue Op) {
2547 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2550 static bool MayFoldIntoStore(SDValue Op) {
2551 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2554 static bool isTargetShuffle(unsigned Opcode) {
2556 default: return false;
2557 case X86ISD::PSHUFD:
2558 case X86ISD::PSHUFHW:
2559 case X86ISD::PSHUFLW:
2560 case X86ISD::SHUFPD:
2561 case X86ISD::PALIGN:
2562 case X86ISD::SHUFPS:
2563 case X86ISD::MOVLHPS:
2564 case X86ISD::MOVLHPD:
2565 case X86ISD::MOVHLPS:
2566 case X86ISD::MOVLPS:
2567 case X86ISD::MOVLPD:
2568 case X86ISD::MOVSHDUP:
2569 case X86ISD::MOVSLDUP:
2570 case X86ISD::MOVDDUP:
2573 case X86ISD::UNPCKLPS:
2574 case X86ISD::UNPCKLPD:
2575 case X86ISD::PUNPCKLWD:
2576 case X86ISD::PUNPCKLBW:
2577 case X86ISD::PUNPCKLDQ:
2578 case X86ISD::PUNPCKLQDQ:
2579 case X86ISD::UNPCKHPS:
2580 case X86ISD::UNPCKHPD:
2581 case X86ISD::PUNPCKHWD:
2582 case X86ISD::PUNPCKHBW:
2583 case X86ISD::PUNPCKHDQ:
2584 case X86ISD::PUNPCKHQDQ:
2590 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2591 SDValue V1, SelectionDAG &DAG) {
2593 default: llvm_unreachable("Unknown x86 shuffle node");
2594 case X86ISD::MOVSHDUP:
2595 case X86ISD::MOVSLDUP:
2596 case X86ISD::MOVDDUP:
2597 return DAG.getNode(Opc, dl, VT, V1);
2603 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2604 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2606 default: llvm_unreachable("Unknown x86 shuffle node");
2607 case X86ISD::PSHUFD:
2608 case X86ISD::PSHUFHW:
2609 case X86ISD::PSHUFLW:
2610 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2616 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2617 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2619 default: llvm_unreachable("Unknown x86 shuffle node");
2620 case X86ISD::PALIGN:
2621 case X86ISD::SHUFPD:
2622 case X86ISD::SHUFPS:
2623 return DAG.getNode(Opc, dl, VT, V1, V2,
2624 DAG.getConstant(TargetMask, MVT::i8));
2629 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2630 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2632 default: llvm_unreachable("Unknown x86 shuffle node");
2633 case X86ISD::MOVLHPS:
2634 case X86ISD::MOVLHPD:
2635 case X86ISD::MOVHLPS:
2636 case X86ISD::MOVLPS:
2637 case X86ISD::MOVLPD:
2640 case X86ISD::UNPCKLPS:
2641 case X86ISD::UNPCKLPD:
2642 case X86ISD::PUNPCKLWD:
2643 case X86ISD::PUNPCKLBW:
2644 case X86ISD::PUNPCKLDQ:
2645 case X86ISD::PUNPCKLQDQ:
2646 case X86ISD::UNPCKHPS:
2647 case X86ISD::UNPCKHPD:
2648 case X86ISD::PUNPCKHWD:
2649 case X86ISD::PUNPCKHBW:
2650 case X86ISD::PUNPCKHDQ:
2651 case X86ISD::PUNPCKHQDQ:
2652 return DAG.getNode(Opc, dl, VT, V1, V2);
2657 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2658 MachineFunction &MF = DAG.getMachineFunction();
2659 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2660 int ReturnAddrIndex = FuncInfo->getRAIndex();
2662 if (ReturnAddrIndex == 0) {
2663 // Set up a frame object for the return address.
2664 uint64_t SlotSize = TD->getPointerSize();
2665 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2667 FuncInfo->setRAIndex(ReturnAddrIndex);
2670 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2674 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2675 bool hasSymbolicDisplacement) {
2676 // Offset should fit into 32 bit immediate field.
2677 if (!isInt<32>(Offset))
2680 // If we don't have a symbolic displacement - we don't have any extra
2682 if (!hasSymbolicDisplacement)
2685 // FIXME: Some tweaks might be needed for medium code model.
2686 if (M != CodeModel::Small && M != CodeModel::Kernel)
2689 // For small code model we assume that latest object is 16MB before end of 31
2690 // bits boundary. We may also accept pretty large negative constants knowing
2691 // that all objects are in the positive half of address space.
2692 if (M == CodeModel::Small && Offset < 16*1024*1024)
2695 // For kernel code model we know that all object resist in the negative half
2696 // of 32bits address space. We may not accept negative offsets, since they may
2697 // be just off and we may accept pretty large positive ones.
2698 if (M == CodeModel::Kernel && Offset > 0)
2704 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2705 /// specific condition code, returning the condition code and the LHS/RHS of the
2706 /// comparison to make.
2707 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2708 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2710 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2711 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2712 // X > -1 -> X == 0, jump !sign.
2713 RHS = DAG.getConstant(0, RHS.getValueType());
2714 return X86::COND_NS;
2715 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2716 // X < 0 -> X == 0, jump on sign.
2718 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2720 RHS = DAG.getConstant(0, RHS.getValueType());
2721 return X86::COND_LE;
2725 switch (SetCCOpcode) {
2726 default: llvm_unreachable("Invalid integer condition!");
2727 case ISD::SETEQ: return X86::COND_E;
2728 case ISD::SETGT: return X86::COND_G;
2729 case ISD::SETGE: return X86::COND_GE;
2730 case ISD::SETLT: return X86::COND_L;
2731 case ISD::SETLE: return X86::COND_LE;
2732 case ISD::SETNE: return X86::COND_NE;
2733 case ISD::SETULT: return X86::COND_B;
2734 case ISD::SETUGT: return X86::COND_A;
2735 case ISD::SETULE: return X86::COND_BE;
2736 case ISD::SETUGE: return X86::COND_AE;
2740 // First determine if it is required or is profitable to flip the operands.
2742 // If LHS is a foldable load, but RHS is not, flip the condition.
2743 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2744 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2745 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2746 std::swap(LHS, RHS);
2749 switch (SetCCOpcode) {
2755 std::swap(LHS, RHS);
2759 // On a floating point condition, the flags are set as follows:
2761 // 0 | 0 | 0 | X > Y
2762 // 0 | 0 | 1 | X < Y
2763 // 1 | 0 | 0 | X == Y
2764 // 1 | 1 | 1 | unordered
2765 switch (SetCCOpcode) {
2766 default: llvm_unreachable("Condcode should be pre-legalized away");
2768 case ISD::SETEQ: return X86::COND_E;
2769 case ISD::SETOLT: // flipped
2771 case ISD::SETGT: return X86::COND_A;
2772 case ISD::SETOLE: // flipped
2774 case ISD::SETGE: return X86::COND_AE;
2775 case ISD::SETUGT: // flipped
2777 case ISD::SETLT: return X86::COND_B;
2778 case ISD::SETUGE: // flipped
2780 case ISD::SETLE: return X86::COND_BE;
2782 case ISD::SETNE: return X86::COND_NE;
2783 case ISD::SETUO: return X86::COND_P;
2784 case ISD::SETO: return X86::COND_NP;
2786 case ISD::SETUNE: return X86::COND_INVALID;
2790 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2791 /// code. Current x86 isa includes the following FP cmov instructions:
2792 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2793 static bool hasFPCMov(unsigned X86CC) {
2809 /// isFPImmLegal - Returns true if the target can instruction select the
2810 /// specified FP immediate natively. If false, the legalizer will
2811 /// materialize the FP immediate as a load from a constant pool.
2812 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2813 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2814 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2820 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2821 /// the specified range (L, H].
2822 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2823 return (Val < 0) || (Val >= Low && Val < Hi);
2826 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2827 /// specified value.
2828 static bool isUndefOrEqual(int Val, int CmpVal) {
2829 if (Val < 0 || Val == CmpVal)
2834 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2835 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2836 /// the second operand.
2837 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2838 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
2839 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2840 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2841 return (Mask[0] < 2 && Mask[1] < 2);
2845 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2846 SmallVector<int, 8> M;
2848 return ::isPSHUFDMask(M, N->getValueType(0));
2851 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2852 /// is suitable for input to PSHUFHW.
2853 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2854 if (VT != MVT::v8i16)
2857 // Lower quadword copied in order or undef.
2858 for (int i = 0; i != 4; ++i)
2859 if (Mask[i] >= 0 && Mask[i] != i)
2862 // Upper quadword shuffled.
2863 for (int i = 4; i != 8; ++i)
2864 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2870 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2871 SmallVector<int, 8> M;
2873 return ::isPSHUFHWMask(M, N->getValueType(0));
2876 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2877 /// is suitable for input to PSHUFLW.
2878 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2879 if (VT != MVT::v8i16)
2882 // Upper quadword copied in order.
2883 for (int i = 4; i != 8; ++i)
2884 if (Mask[i] >= 0 && Mask[i] != i)
2887 // Lower quadword shuffled.
2888 for (int i = 0; i != 4; ++i)
2895 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2896 SmallVector<int, 8> M;
2898 return ::isPSHUFLWMask(M, N->getValueType(0));
2901 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2902 /// is suitable for input to PALIGNR.
2903 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2905 int i, e = VT.getVectorNumElements();
2907 // Do not handle v2i64 / v2f64 shuffles with palignr.
2908 if (e < 4 || !hasSSSE3)
2911 for (i = 0; i != e; ++i)
2915 // All undef, not a palignr.
2919 // Determine if it's ok to perform a palignr with only the LHS, since we
2920 // don't have access to the actual shuffle elements to see if RHS is undef.
2921 bool Unary = Mask[i] < (int)e;
2922 bool NeedsUnary = false;
2924 int s = Mask[i] - i;
2926 // Check the rest of the elements to see if they are consecutive.
2927 for (++i; i != e; ++i) {
2932 Unary = Unary && (m < (int)e);
2933 NeedsUnary = NeedsUnary || (m < s);
2935 if (NeedsUnary && !Unary)
2937 if (Unary && m != ((s+i) & (e-1)))
2939 if (!Unary && m != (s+i))
2945 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2946 SmallVector<int, 8> M;
2948 return ::isPALIGNRMask(M, N->getValueType(0), true);
2951 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2952 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2953 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2954 int NumElems = VT.getVectorNumElements();
2955 if (NumElems != 2 && NumElems != 4)
2958 int Half = NumElems / 2;
2959 for (int i = 0; i < Half; ++i)
2960 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2962 for (int i = Half; i < NumElems; ++i)
2963 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2969 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2970 SmallVector<int, 8> M;
2972 return ::isSHUFPMask(M, N->getValueType(0));
2975 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2976 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2977 /// half elements to come from vector 1 (which would equal the dest.) and
2978 /// the upper half to come from vector 2.
2979 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2980 int NumElems = VT.getVectorNumElements();
2982 if (NumElems != 2 && NumElems != 4)
2985 int Half = NumElems / 2;
2986 for (int i = 0; i < Half; ++i)
2987 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2989 for (int i = Half; i < NumElems; ++i)
2990 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2995 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2996 SmallVector<int, 8> M;
2998 return isCommutedSHUFPMask(M, N->getValueType(0));
3001 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3002 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3003 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3004 if (N->getValueType(0).getVectorNumElements() != 4)
3007 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3008 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3009 isUndefOrEqual(N->getMaskElt(1), 7) &&
3010 isUndefOrEqual(N->getMaskElt(2), 2) &&
3011 isUndefOrEqual(N->getMaskElt(3), 3);
3014 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3015 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3017 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3018 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3023 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3024 isUndefOrEqual(N->getMaskElt(1), 3) &&
3025 isUndefOrEqual(N->getMaskElt(2), 2) &&
3026 isUndefOrEqual(N->getMaskElt(3), 3);
3029 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3030 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3031 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3032 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3034 if (NumElems != 2 && NumElems != 4)
3037 for (unsigned i = 0; i < NumElems/2; ++i)
3038 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3041 for (unsigned i = NumElems/2; i < NumElems; ++i)
3042 if (!isUndefOrEqual(N->getMaskElt(i), i))
3048 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3049 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3050 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3051 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3053 if (NumElems != 2 && NumElems != 4)
3056 for (unsigned i = 0; i < NumElems/2; ++i)
3057 if (!isUndefOrEqual(N->getMaskElt(i), i))
3060 for (unsigned i = 0; i < NumElems/2; ++i)
3061 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3067 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3068 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3069 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3070 bool V2IsSplat = false) {
3071 int NumElts = VT.getVectorNumElements();
3072 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3075 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3077 int BitI1 = Mask[i+1];
3078 if (!isUndefOrEqual(BitI, j))
3081 if (!isUndefOrEqual(BitI1, NumElts))
3084 if (!isUndefOrEqual(BitI1, j + NumElts))
3091 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3092 SmallVector<int, 8> M;
3094 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3097 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3098 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3099 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3100 bool V2IsSplat = false) {
3101 int NumElts = VT.getVectorNumElements();
3102 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3105 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3107 int BitI1 = Mask[i+1];
3108 if (!isUndefOrEqual(BitI, j + NumElts/2))
3111 if (isUndefOrEqual(BitI1, NumElts))
3114 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3121 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3122 SmallVector<int, 8> M;
3124 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3127 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3128 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3130 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3131 int NumElems = VT.getVectorNumElements();
3132 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3135 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3137 int BitI1 = Mask[i+1];
3138 if (!isUndefOrEqual(BitI, j))
3140 if (!isUndefOrEqual(BitI1, j))
3146 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3147 SmallVector<int, 8> M;
3149 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3152 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3153 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3155 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3156 int NumElems = VT.getVectorNumElements();
3157 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3160 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3162 int BitI1 = Mask[i+1];
3163 if (!isUndefOrEqual(BitI, j))
3165 if (!isUndefOrEqual(BitI1, j))
3171 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3172 SmallVector<int, 8> M;
3174 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3177 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3178 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3179 /// MOVSD, and MOVD, i.e. setting the lowest element.
3180 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3181 if (VT.getVectorElementType().getSizeInBits() < 32)
3184 int NumElts = VT.getVectorNumElements();
3186 if (!isUndefOrEqual(Mask[0], NumElts))
3189 for (int i = 1; i < NumElts; ++i)
3190 if (!isUndefOrEqual(Mask[i], i))
3196 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3197 SmallVector<int, 8> M;
3199 return ::isMOVLMask(M, N->getValueType(0));
3202 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3203 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3204 /// element of vector 2 and the other elements to come from vector 1 in order.
3205 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3206 bool V2IsSplat = false, bool V2IsUndef = false) {
3207 int NumOps = VT.getVectorNumElements();
3208 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3211 if (!isUndefOrEqual(Mask[0], 0))
3214 for (int i = 1; i < NumOps; ++i)
3215 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3216 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3217 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3223 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3224 bool V2IsUndef = false) {
3225 SmallVector<int, 8> M;
3227 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3230 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3231 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3232 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3233 if (N->getValueType(0).getVectorNumElements() != 4)
3236 // Expect 1, 1, 3, 3
3237 for (unsigned i = 0; i < 2; ++i) {
3238 int Elt = N->getMaskElt(i);
3239 if (Elt >= 0 && Elt != 1)
3244 for (unsigned i = 2; i < 4; ++i) {
3245 int Elt = N->getMaskElt(i);
3246 if (Elt >= 0 && Elt != 3)
3251 // Don't use movshdup if it can be done with a shufps.
3252 // FIXME: verify that matching u, u, 3, 3 is what we want.
3256 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3257 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3258 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3259 if (N->getValueType(0).getVectorNumElements() != 4)
3262 // Expect 0, 0, 2, 2
3263 for (unsigned i = 0; i < 2; ++i)
3264 if (N->getMaskElt(i) > 0)
3268 for (unsigned i = 2; i < 4; ++i) {
3269 int Elt = N->getMaskElt(i);
3270 if (Elt >= 0 && Elt != 2)
3275 // Don't use movsldup if it can be done with a shufps.
3279 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3280 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3281 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3282 int e = N->getValueType(0).getVectorNumElements() / 2;
3284 for (int i = 0; i < e; ++i)
3285 if (!isUndefOrEqual(N->getMaskElt(i), i))
3287 for (int i = 0; i < e; ++i)
3288 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3293 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3294 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3295 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3296 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3297 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3299 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3301 for (int i = 0; i < NumOperands; ++i) {
3302 int Val = SVOp->getMaskElt(NumOperands-i-1);
3303 if (Val < 0) Val = 0;
3304 if (Val >= NumOperands) Val -= NumOperands;
3306 if (i != NumOperands - 1)
3312 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3313 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3314 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3315 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3317 // 8 nodes, but we only care about the last 4.
3318 for (unsigned i = 7; i >= 4; --i) {
3319 int Val = SVOp->getMaskElt(i);
3328 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3329 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3330 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3331 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3333 // 8 nodes, but we only care about the first 4.
3334 for (int i = 3; i >= 0; --i) {
3335 int Val = SVOp->getMaskElt(i);
3344 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3345 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3346 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3348 EVT VVT = N->getValueType(0);
3349 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3353 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3354 Val = SVOp->getMaskElt(i);
3358 return (Val - i) * EltSize;
3361 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3363 bool X86::isZeroNode(SDValue Elt) {
3364 return ((isa<ConstantSDNode>(Elt) &&
3365 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3366 (isa<ConstantFPSDNode>(Elt) &&
3367 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3370 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3371 /// their permute mask.
3372 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3373 SelectionDAG &DAG) {
3374 EVT VT = SVOp->getValueType(0);
3375 unsigned NumElems = VT.getVectorNumElements();
3376 SmallVector<int, 8> MaskVec;
3378 for (unsigned i = 0; i != NumElems; ++i) {
3379 int idx = SVOp->getMaskElt(i);
3381 MaskVec.push_back(idx);
3382 else if (idx < (int)NumElems)
3383 MaskVec.push_back(idx + NumElems);
3385 MaskVec.push_back(idx - NumElems);
3387 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3388 SVOp->getOperand(0), &MaskVec[0]);
3391 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3392 /// the two vector operands have swapped position.
3393 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3394 unsigned NumElems = VT.getVectorNumElements();
3395 for (unsigned i = 0; i != NumElems; ++i) {
3399 else if (idx < (int)NumElems)
3400 Mask[i] = idx + NumElems;
3402 Mask[i] = idx - NumElems;
3406 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3407 /// match movhlps. The lower half elements should come from upper half of
3408 /// V1 (and in order), and the upper half elements should come from the upper
3409 /// half of V2 (and in order).
3410 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3411 if (Op->getValueType(0).getVectorNumElements() != 4)
3413 for (unsigned i = 0, e = 2; i != e; ++i)
3414 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3416 for (unsigned i = 2; i != 4; ++i)
3417 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3422 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3423 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3425 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3426 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3428 N = N->getOperand(0).getNode();
3429 if (!ISD::isNON_EXTLoad(N))
3432 *LD = cast<LoadSDNode>(N);
3436 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3437 /// match movlp{s|d}. The lower half elements should come from lower half of
3438 /// V1 (and in order), and the upper half elements should come from the upper
3439 /// half of V2 (and in order). And since V1 will become the source of the
3440 /// MOVLP, it must be either a vector load or a scalar load to vector.
3441 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3442 ShuffleVectorSDNode *Op) {
3443 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3445 // Is V2 is a vector load, don't do this transformation. We will try to use
3446 // load folding shufps op.
3447 if (ISD::isNON_EXTLoad(V2))
3450 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3452 if (NumElems != 2 && NumElems != 4)
3454 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3455 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3457 for (unsigned i = NumElems/2; i != NumElems; ++i)
3458 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3463 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3465 static bool isSplatVector(SDNode *N) {
3466 if (N->getOpcode() != ISD::BUILD_VECTOR)
3469 SDValue SplatValue = N->getOperand(0);
3470 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3471 if (N->getOperand(i) != SplatValue)
3476 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3477 /// to an zero vector.
3478 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3479 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3480 SDValue V1 = N->getOperand(0);
3481 SDValue V2 = N->getOperand(1);
3482 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3483 for (unsigned i = 0; i != NumElems; ++i) {
3484 int Idx = N->getMaskElt(i);
3485 if (Idx >= (int)NumElems) {
3486 unsigned Opc = V2.getOpcode();
3487 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3489 if (Opc != ISD::BUILD_VECTOR ||
3490 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3492 } else if (Idx >= 0) {
3493 unsigned Opc = V1.getOpcode();
3494 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3496 if (Opc != ISD::BUILD_VECTOR ||
3497 !X86::isZeroNode(V1.getOperand(Idx)))
3504 /// getZeroVector - Returns a vector of specified type with all zero elements.
3506 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3508 assert(VT.isVector() && "Expected a vector type");
3510 // Always build SSE zero vectors as <4 x i32> bitcasted
3511 // to their dest type. This ensures they get CSE'd.
3513 if (VT.getSizeInBits() == 128) { // SSE
3514 if (HasSSE2) { // SSE2
3515 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3516 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3518 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3519 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3521 } else if (VT.getSizeInBits() == 256) { // AVX
3522 // 256-bit logic and arithmetic instructions in AVX are
3523 // all floating-point, no support for integer ops. Default
3524 // to emitting fp zeroed vectors then.
3525 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3526 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3527 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3529 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3532 /// getOnesVector - Returns a vector of specified type with all bits set.
3534 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3535 assert(VT.isVector() && "Expected a vector type");
3537 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3538 // type. This ensures they get CSE'd.
3539 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3541 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3542 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3546 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3547 /// that point to V2 points to its first element.
3548 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3549 EVT VT = SVOp->getValueType(0);
3550 unsigned NumElems = VT.getVectorNumElements();
3552 bool Changed = false;
3553 SmallVector<int, 8> MaskVec;
3554 SVOp->getMask(MaskVec);
3556 for (unsigned i = 0; i != NumElems; ++i) {
3557 if (MaskVec[i] > (int)NumElems) {
3558 MaskVec[i] = NumElems;
3563 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3564 SVOp->getOperand(1), &MaskVec[0]);
3565 return SDValue(SVOp, 0);
3568 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3569 /// operation of specified width.
3570 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3572 unsigned NumElems = VT.getVectorNumElements();
3573 SmallVector<int, 8> Mask;
3574 Mask.push_back(NumElems);
3575 for (unsigned i = 1; i != NumElems; ++i)
3577 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3580 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3581 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3583 unsigned NumElems = VT.getVectorNumElements();
3584 SmallVector<int, 8> Mask;
3585 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3587 Mask.push_back(i + NumElems);
3589 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3592 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3593 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3595 unsigned NumElems = VT.getVectorNumElements();
3596 unsigned Half = NumElems/2;
3597 SmallVector<int, 8> Mask;
3598 for (unsigned i = 0; i != Half; ++i) {
3599 Mask.push_back(i + Half);
3600 Mask.push_back(i + NumElems + Half);
3602 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3605 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3606 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3607 EVT PVT = MVT::v4f32;
3608 EVT VT = SV->getValueType(0);
3609 DebugLoc dl = SV->getDebugLoc();
3610 SDValue V1 = SV->getOperand(0);
3611 int NumElems = VT.getVectorNumElements();
3612 int EltNo = SV->getSplatIndex();
3614 // unpack elements to the correct location
3615 while (NumElems > 4) {
3616 if (EltNo < NumElems/2) {
3617 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3619 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3620 EltNo -= NumElems/2;
3625 // Perform the splat.
3626 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3627 V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1);
3628 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3629 return DAG.getNode(ISD::BITCAST, dl, VT, V1);
3632 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3633 /// vector of zero or undef vector. This produces a shuffle where the low
3634 /// element of V2 is swizzled into the zero/undef vector, landing at element
3635 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3636 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3637 bool isZero, bool HasSSE2,
3638 SelectionDAG &DAG) {
3639 EVT VT = V2.getValueType();
3641 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3642 unsigned NumElems = VT.getVectorNumElements();
3643 SmallVector<int, 16> MaskVec;
3644 for (unsigned i = 0; i != NumElems; ++i)
3645 // If this is the insertion idx, put the low elt of V2 here.
3646 MaskVec.push_back(i == Idx ? NumElems : i);
3647 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3650 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3651 /// element of the result of the vector shuffle.
3652 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3655 return SDValue(); // Limit search depth.
3657 SDValue V = SDValue(N, 0);
3658 EVT VT = V.getValueType();
3659 unsigned Opcode = V.getOpcode();
3661 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3662 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3663 Index = SV->getMaskElt(Index);
3666 return DAG.getUNDEF(VT.getVectorElementType());
3668 int NumElems = VT.getVectorNumElements();
3669 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3670 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3673 // Recurse into target specific vector shuffles to find scalars.
3674 if (isTargetShuffle(Opcode)) {
3675 int NumElems = VT.getVectorNumElements();
3676 SmallVector<unsigned, 16> ShuffleMask;
3680 case X86ISD::SHUFPS:
3681 case X86ISD::SHUFPD:
3682 ImmN = N->getOperand(N->getNumOperands()-1);
3683 DecodeSHUFPSMask(NumElems,
3684 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3687 case X86ISD::PUNPCKHBW:
3688 case X86ISD::PUNPCKHWD:
3689 case X86ISD::PUNPCKHDQ:
3690 case X86ISD::PUNPCKHQDQ:
3691 DecodePUNPCKHMask(NumElems, ShuffleMask);
3693 case X86ISD::UNPCKHPS:
3694 case X86ISD::UNPCKHPD:
3695 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3697 case X86ISD::PUNPCKLBW:
3698 case X86ISD::PUNPCKLWD:
3699 case X86ISD::PUNPCKLDQ:
3700 case X86ISD::PUNPCKLQDQ:
3701 DecodePUNPCKLMask(NumElems, ShuffleMask);
3703 case X86ISD::UNPCKLPS:
3704 case X86ISD::UNPCKLPD:
3705 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3707 case X86ISD::MOVHLPS:
3708 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3710 case X86ISD::MOVLHPS:
3711 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3713 case X86ISD::PSHUFD:
3714 ImmN = N->getOperand(N->getNumOperands()-1);
3715 DecodePSHUFMask(NumElems,
3716 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3719 case X86ISD::PSHUFHW:
3720 ImmN = N->getOperand(N->getNumOperands()-1);
3721 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3724 case X86ISD::PSHUFLW:
3725 ImmN = N->getOperand(N->getNumOperands()-1);
3726 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3730 case X86ISD::MOVSD: {
3731 // The index 0 always comes from the first element of the second source,
3732 // this is why MOVSS and MOVSD are used in the first place. The other
3733 // elements come from the other positions of the first source vector.
3734 unsigned OpNum = (Index == 0) ? 1 : 0;
3735 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3739 assert("not implemented for target shuffle node");
3743 Index = ShuffleMask[Index];
3745 return DAG.getUNDEF(VT.getVectorElementType());
3747 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3748 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3752 // Actual nodes that may contain scalar elements
3753 if (Opcode == ISD::BITCAST) {
3754 V = V.getOperand(0);
3755 EVT SrcVT = V.getValueType();
3756 unsigned NumElems = VT.getVectorNumElements();
3758 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3762 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3763 return (Index == 0) ? V.getOperand(0)
3764 : DAG.getUNDEF(VT.getVectorElementType());
3766 if (V.getOpcode() == ISD::BUILD_VECTOR)
3767 return V.getOperand(Index);
3772 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3773 /// shuffle operation which come from a consecutively from a zero. The
3774 /// search can start in two diferent directions, from left or right.
3776 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3777 bool ZerosFromLeft, SelectionDAG &DAG) {
3780 while (i < NumElems) {
3781 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3782 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3783 if (!(Elt.getNode() &&
3784 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3792 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3793 /// MaskE correspond consecutively to elements from one of the vector operands,
3794 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3796 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3797 int OpIdx, int NumElems, unsigned &OpNum) {
3798 bool SeenV1 = false;
3799 bool SeenV2 = false;
3801 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3802 int Idx = SVOp->getMaskElt(i);
3803 // Ignore undef indicies
3812 // Only accept consecutive elements from the same vector
3813 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3817 OpNum = SeenV1 ? 0 : 1;
3821 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3822 /// logical left shift of a vector.
3823 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3824 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3825 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3826 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3827 false /* check zeros from right */, DAG);
3833 // Considering the elements in the mask that are not consecutive zeros,
3834 // check if they consecutively come from only one of the source vectors.
3836 // V1 = {X, A, B, C} 0
3838 // vector_shuffle V1, V2 <1, 2, 3, X>
3840 if (!isShuffleMaskConsecutive(SVOp,
3841 0, // Mask Start Index
3842 NumElems-NumZeros-1, // Mask End Index
3843 NumZeros, // Where to start looking in the src vector
3844 NumElems, // Number of elements in vector
3845 OpSrc)) // Which source operand ?
3850 ShVal = SVOp->getOperand(OpSrc);
3854 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3855 /// logical left shift of a vector.
3856 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3857 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3858 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3859 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3860 true /* check zeros from left */, DAG);
3866 // Considering the elements in the mask that are not consecutive zeros,
3867 // check if they consecutively come from only one of the source vectors.
3869 // 0 { A, B, X, X } = V2
3871 // vector_shuffle V1, V2 <X, X, 4, 5>
3873 if (!isShuffleMaskConsecutive(SVOp,
3874 NumZeros, // Mask Start Index
3875 NumElems-1, // Mask End Index
3876 0, // Where to start looking in the src vector
3877 NumElems, // Number of elements in vector
3878 OpSrc)) // Which source operand ?
3883 ShVal = SVOp->getOperand(OpSrc);
3887 /// isVectorShift - Returns true if the shuffle can be implemented as a
3888 /// logical left or right shift of a vector.
3889 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3890 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3891 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3892 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3898 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3900 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3901 unsigned NumNonZero, unsigned NumZero,
3903 const TargetLowering &TLI) {
3907 DebugLoc dl = Op.getDebugLoc();
3910 for (unsigned i = 0; i < 16; ++i) {
3911 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3912 if (ThisIsNonZero && First) {
3914 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3916 V = DAG.getUNDEF(MVT::v8i16);
3921 SDValue ThisElt(0, 0), LastElt(0, 0);
3922 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3923 if (LastIsNonZero) {
3924 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3925 MVT::i16, Op.getOperand(i-1));
3927 if (ThisIsNonZero) {
3928 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3929 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3930 ThisElt, DAG.getConstant(8, MVT::i8));
3932 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3936 if (ThisElt.getNode())
3937 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3938 DAG.getIntPtrConstant(i/2));
3942 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
3945 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3947 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3948 unsigned NumNonZero, unsigned NumZero,
3950 const TargetLowering &TLI) {
3954 DebugLoc dl = Op.getDebugLoc();
3957 for (unsigned i = 0; i < 8; ++i) {
3958 bool isNonZero = (NonZeros & (1 << i)) != 0;
3962 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3964 V = DAG.getUNDEF(MVT::v8i16);
3967 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3968 MVT::v8i16, V, Op.getOperand(i),
3969 DAG.getIntPtrConstant(i));
3976 /// getVShift - Return a vector logical shift node.
3978 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3979 unsigned NumBits, SelectionDAG &DAG,
3980 const TargetLowering &TLI, DebugLoc dl) {
3981 EVT ShVT = MVT::v2i64;
3982 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3983 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
3984 return DAG.getNode(ISD::BITCAST, dl, VT,
3985 DAG.getNode(Opc, dl, ShVT, SrcOp,
3986 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3990 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3991 SelectionDAG &DAG) const {
3993 // Check if the scalar load can be widened into a vector load. And if
3994 // the address is "base + cst" see if the cst can be "absorbed" into
3995 // the shuffle mask.
3996 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3997 SDValue Ptr = LD->getBasePtr();
3998 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4000 EVT PVT = LD->getValueType(0);
4001 if (PVT != MVT::i32 && PVT != MVT::f32)
4006 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4007 FI = FINode->getIndex();
4009 } else if (Ptr.getOpcode() == ISD::ADD &&
4010 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4011 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4012 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4013 Offset = Ptr.getConstantOperandVal(1);
4014 Ptr = Ptr.getOperand(0);
4019 SDValue Chain = LD->getChain();
4020 // Make sure the stack object alignment is at least 16.
4021 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4022 if (DAG.InferPtrAlignment(Ptr) < 16) {
4023 if (MFI->isFixedObjectIndex(FI)) {
4024 // Can't change the alignment. FIXME: It's possible to compute
4025 // the exact stack offset and reference FI + adjust offset instead.
4026 // If someone *really* cares about this. That's the way to implement it.
4029 MFI->setObjectAlignment(FI, 16);
4033 // (Offset % 16) must be multiple of 4. Then address is then
4034 // Ptr + (Offset & ~15).
4037 if ((Offset % 16) & 3)
4039 int64_t StartOffset = Offset & ~15;
4041 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4042 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4044 int EltNo = (Offset - StartOffset) >> 2;
4045 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4046 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4047 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4048 LD->getPointerInfo().getWithOffset(StartOffset),
4050 // Canonicalize it to a v4i32 shuffle.
4051 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
4052 return DAG.getNode(ISD::BITCAST, dl, VT,
4053 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4054 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4060 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4061 /// vector of type 'VT', see if the elements can be replaced by a single large
4062 /// load which has the same value as a build_vector whose operands are 'elts'.
4064 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4066 /// FIXME: we'd also like to handle the case where the last elements are zero
4067 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4068 /// There's even a handy isZeroNode for that purpose.
4069 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4070 DebugLoc &DL, SelectionDAG &DAG) {
4071 EVT EltVT = VT.getVectorElementType();
4072 unsigned NumElems = Elts.size();
4074 LoadSDNode *LDBase = NULL;
4075 unsigned LastLoadedElt = -1U;
4077 // For each element in the initializer, see if we've found a load or an undef.
4078 // If we don't find an initial load element, or later load elements are
4079 // non-consecutive, bail out.
4080 for (unsigned i = 0; i < NumElems; ++i) {
4081 SDValue Elt = Elts[i];
4083 if (!Elt.getNode() ||
4084 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4087 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4089 LDBase = cast<LoadSDNode>(Elt.getNode());
4093 if (Elt.getOpcode() == ISD::UNDEF)
4096 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4097 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4102 // If we have found an entire vector of loads and undefs, then return a large
4103 // load of the entire vector width starting at the base pointer. If we found
4104 // consecutive loads for the low half, generate a vzext_load node.
4105 if (LastLoadedElt == NumElems - 1) {
4106 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4107 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4108 LDBase->getPointerInfo(),
4109 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4110 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4111 LDBase->getPointerInfo(),
4112 LDBase->isVolatile(), LDBase->isNonTemporal(),
4113 LDBase->getAlignment());
4114 } else if (NumElems == 4 && LastLoadedElt == 1) {
4115 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4116 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4117 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4119 LDBase->getMemOperand());
4120 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4126 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4127 DebugLoc dl = Op.getDebugLoc();
4128 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4129 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4130 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4131 // is present, so AllOnes is ignored.
4132 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4133 (Op.getValueType().getSizeInBits() != 256 &&
4134 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4135 // Canonicalize this to <4 x i32> (SSE) to
4136 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4137 // eliminated on x86-32 hosts.
4138 if (Op.getValueType() == MVT::v4i32)
4141 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4142 return getOnesVector(Op.getValueType(), DAG, dl);
4143 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4146 EVT VT = Op.getValueType();
4147 EVT ExtVT = VT.getVectorElementType();
4148 unsigned EVTBits = ExtVT.getSizeInBits();
4150 unsigned NumElems = Op.getNumOperands();
4151 unsigned NumZero = 0;
4152 unsigned NumNonZero = 0;
4153 unsigned NonZeros = 0;
4154 bool IsAllConstants = true;
4155 SmallSet<SDValue, 8> Values;
4156 for (unsigned i = 0; i < NumElems; ++i) {
4157 SDValue Elt = Op.getOperand(i);
4158 if (Elt.getOpcode() == ISD::UNDEF)
4161 if (Elt.getOpcode() != ISD::Constant &&
4162 Elt.getOpcode() != ISD::ConstantFP)
4163 IsAllConstants = false;
4164 if (X86::isZeroNode(Elt))
4167 NonZeros |= (1 << i);
4172 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4173 if (NumNonZero == 0)
4174 return DAG.getUNDEF(VT);
4176 // Special case for single non-zero, non-undef, element.
4177 if (NumNonZero == 1) {
4178 unsigned Idx = CountTrailingZeros_32(NonZeros);
4179 SDValue Item = Op.getOperand(Idx);
4181 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4182 // the value are obviously zero, truncate the value to i32 and do the
4183 // insertion that way. Only do this if the value is non-constant or if the
4184 // value is a constant being inserted into element 0. It is cheaper to do
4185 // a constant pool load than it is to do a movd + shuffle.
4186 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4187 (!IsAllConstants || Idx == 0)) {
4188 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4190 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4191 EVT VecVT = MVT::v4i32;
4192 unsigned VecElts = 4;
4194 // Truncate the value (which may itself be a constant) to i32, and
4195 // convert it to a vector with movd (S2V+shuffle to zero extend).
4196 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4197 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4198 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4199 Subtarget->hasSSE2(), DAG);
4201 // Now we have our 32-bit value zero extended in the low element of
4202 // a vector. If Idx != 0, swizzle it into place.
4204 SmallVector<int, 4> Mask;
4205 Mask.push_back(Idx);
4206 for (unsigned i = 1; i != VecElts; ++i)
4208 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4209 DAG.getUNDEF(Item.getValueType()),
4212 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4216 // If we have a constant or non-constant insertion into the low element of
4217 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4218 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4219 // depending on what the source datatype is.
4222 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4223 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4224 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4225 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4226 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4227 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4229 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4230 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4231 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4232 EVT MiddleVT = MVT::v4i32;
4233 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4234 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4235 Subtarget->hasSSE2(), DAG);
4236 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4240 // Is it a vector logical left shift?
4241 if (NumElems == 2 && Idx == 1 &&
4242 X86::isZeroNode(Op.getOperand(0)) &&
4243 !X86::isZeroNode(Op.getOperand(1))) {
4244 unsigned NumBits = VT.getSizeInBits();
4245 return getVShift(true, VT,
4246 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4247 VT, Op.getOperand(1)),
4248 NumBits/2, DAG, *this, dl);
4251 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4254 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4255 // is a non-constant being inserted into an element other than the low one,
4256 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4257 // movd/movss) to move this into the low element, then shuffle it into
4259 if (EVTBits == 32) {
4260 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4262 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4263 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4264 Subtarget->hasSSE2(), DAG);
4265 SmallVector<int, 8> MaskVec;
4266 for (unsigned i = 0; i < NumElems; i++)
4267 MaskVec.push_back(i == Idx ? 0 : 1);
4268 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4272 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4273 if (Values.size() == 1) {
4274 if (EVTBits == 32) {
4275 // Instead of a shuffle like this:
4276 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4277 // Check if it's possible to issue this instead.
4278 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4279 unsigned Idx = CountTrailingZeros_32(NonZeros);
4280 SDValue Item = Op.getOperand(Idx);
4281 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4282 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4287 // A vector full of immediates; various special cases are already
4288 // handled, so this is best done with a single constant-pool load.
4292 // Let legalizer expand 2-wide build_vectors.
4293 if (EVTBits == 64) {
4294 if (NumNonZero == 1) {
4295 // One half is zero or undef.
4296 unsigned Idx = CountTrailingZeros_32(NonZeros);
4297 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4298 Op.getOperand(Idx));
4299 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4300 Subtarget->hasSSE2(), DAG);
4305 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4306 if (EVTBits == 8 && NumElems == 16) {
4307 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4309 if (V.getNode()) return V;
4312 if (EVTBits == 16 && NumElems == 8) {
4313 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4315 if (V.getNode()) return V;
4318 // If element VT is == 32 bits, turn it into a number of shuffles.
4319 SmallVector<SDValue, 8> V;
4321 if (NumElems == 4 && NumZero > 0) {
4322 for (unsigned i = 0; i < 4; ++i) {
4323 bool isZero = !(NonZeros & (1 << i));
4325 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4327 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4330 for (unsigned i = 0; i < 2; ++i) {
4331 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4334 V[i] = V[i*2]; // Must be a zero vector.
4337 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4340 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4343 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4348 SmallVector<int, 8> MaskVec;
4349 bool Reverse = (NonZeros & 0x3) == 2;
4350 for (unsigned i = 0; i < 2; ++i)
4351 MaskVec.push_back(Reverse ? 1-i : i);
4352 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4353 for (unsigned i = 0; i < 2; ++i)
4354 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4355 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4358 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4359 // Check for a build vector of consecutive loads.
4360 for (unsigned i = 0; i < NumElems; ++i)
4361 V[i] = Op.getOperand(i);
4363 // Check for elements which are consecutive loads.
4364 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4368 // For SSE 4.1, use insertps to put the high elements into the low element.
4369 if (getSubtarget()->hasSSE41()) {
4371 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4372 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4374 Result = DAG.getUNDEF(VT);
4376 for (unsigned i = 1; i < NumElems; ++i) {
4377 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4378 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4379 Op.getOperand(i), DAG.getIntPtrConstant(i));
4384 // Otherwise, expand into a number of unpckl*, start by extending each of
4385 // our (non-undef) elements to the full vector width with the element in the
4386 // bottom slot of the vector (which generates no code for SSE).
4387 for (unsigned i = 0; i < NumElems; ++i) {
4388 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4389 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4391 V[i] = DAG.getUNDEF(VT);
4394 // Next, we iteratively mix elements, e.g. for v4f32:
4395 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4396 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4397 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4398 unsigned EltStride = NumElems >> 1;
4399 while (EltStride != 0) {
4400 for (unsigned i = 0; i < EltStride; ++i) {
4401 // If V[i+EltStride] is undef and this is the first round of mixing,
4402 // then it is safe to just drop this shuffle: V[i] is already in the
4403 // right place, the one element (since it's the first round) being
4404 // inserted as undef can be dropped. This isn't safe for successive
4405 // rounds because they will permute elements within both vectors.
4406 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4407 EltStride == NumElems/2)
4410 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4420 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4421 // We support concatenate two MMX registers and place them in a MMX
4422 // register. This is better than doing a stack convert.
4423 DebugLoc dl = Op.getDebugLoc();
4424 EVT ResVT = Op.getValueType();
4425 assert(Op.getNumOperands() == 2);
4426 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4427 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4429 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
4430 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4431 InVec = Op.getOperand(1);
4432 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4433 unsigned NumElts = ResVT.getVectorNumElements();
4434 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4435 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4436 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4438 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
4439 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4440 Mask[0] = 0; Mask[1] = 2;
4441 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4443 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4446 // v8i16 shuffles - Prefer shuffles in the following order:
4447 // 1. [all] pshuflw, pshufhw, optional move
4448 // 2. [ssse3] 1 x pshufb
4449 // 3. [ssse3] 2 x pshufb + 1 x por
4450 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4452 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4453 SelectionDAG &DAG) const {
4454 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4455 SDValue V1 = SVOp->getOperand(0);
4456 SDValue V2 = SVOp->getOperand(1);
4457 DebugLoc dl = SVOp->getDebugLoc();
4458 SmallVector<int, 8> MaskVals;
4460 // Determine if more than 1 of the words in each of the low and high quadwords
4461 // of the result come from the same quadword of one of the two inputs. Undef
4462 // mask values count as coming from any quadword, for better codegen.
4463 SmallVector<unsigned, 4> LoQuad(4);
4464 SmallVector<unsigned, 4> HiQuad(4);
4465 BitVector InputQuads(4);
4466 for (unsigned i = 0; i < 8; ++i) {
4467 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4468 int EltIdx = SVOp->getMaskElt(i);
4469 MaskVals.push_back(EltIdx);
4478 InputQuads.set(EltIdx / 4);
4481 int BestLoQuad = -1;
4482 unsigned MaxQuad = 1;
4483 for (unsigned i = 0; i < 4; ++i) {
4484 if (LoQuad[i] > MaxQuad) {
4486 MaxQuad = LoQuad[i];
4490 int BestHiQuad = -1;
4492 for (unsigned i = 0; i < 4; ++i) {
4493 if (HiQuad[i] > MaxQuad) {
4495 MaxQuad = HiQuad[i];
4499 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4500 // of the two input vectors, shuffle them into one input vector so only a
4501 // single pshufb instruction is necessary. If There are more than 2 input
4502 // quads, disable the next transformation since it does not help SSSE3.
4503 bool V1Used = InputQuads[0] || InputQuads[1];
4504 bool V2Used = InputQuads[2] || InputQuads[3];
4505 if (Subtarget->hasSSSE3()) {
4506 if (InputQuads.count() == 2 && V1Used && V2Used) {
4507 BestLoQuad = InputQuads.find_first();
4508 BestHiQuad = InputQuads.find_next(BestLoQuad);
4510 if (InputQuads.count() > 2) {
4516 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4517 // the shuffle mask. If a quad is scored as -1, that means that it contains
4518 // words from all 4 input quadwords.
4520 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4521 SmallVector<int, 8> MaskV;
4522 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4523 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4524 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4525 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
4526 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
4527 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
4529 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4530 // source words for the shuffle, to aid later transformations.
4531 bool AllWordsInNewV = true;
4532 bool InOrder[2] = { true, true };
4533 for (unsigned i = 0; i != 8; ++i) {
4534 int idx = MaskVals[i];
4536 InOrder[i/4] = false;
4537 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4539 AllWordsInNewV = false;
4543 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4544 if (AllWordsInNewV) {
4545 for (int i = 0; i != 8; ++i) {
4546 int idx = MaskVals[i];
4549 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4550 if ((idx != i) && idx < 4)
4552 if ((idx != i) && idx > 3)
4561 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4562 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4563 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4564 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4565 unsigned TargetMask = 0;
4566 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4567 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4568 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4569 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4570 V1 = NewV.getOperand(0);
4571 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4575 // If we have SSSE3, and all words of the result are from 1 input vector,
4576 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4577 // is present, fall back to case 4.
4578 if (Subtarget->hasSSSE3()) {
4579 SmallVector<SDValue,16> pshufbMask;
4581 // If we have elements from both input vectors, set the high bit of the
4582 // shuffle mask element to zero out elements that come from V2 in the V1
4583 // mask, and elements that come from V1 in the V2 mask, so that the two
4584 // results can be OR'd together.
4585 bool TwoInputs = V1Used && V2Used;
4586 for (unsigned i = 0; i != 8; ++i) {
4587 int EltIdx = MaskVals[i] * 2;
4588 if (TwoInputs && (EltIdx >= 16)) {
4589 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4590 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4593 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4594 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4596 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
4597 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4598 DAG.getNode(ISD::BUILD_VECTOR, dl,
4599 MVT::v16i8, &pshufbMask[0], 16));
4601 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4603 // Calculate the shuffle mask for the second input, shuffle it, and
4604 // OR it with the first shuffled input.
4606 for (unsigned i = 0; i != 8; ++i) {
4607 int EltIdx = MaskVals[i] * 2;
4609 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4610 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4613 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4614 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4616 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
4617 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4618 DAG.getNode(ISD::BUILD_VECTOR, dl,
4619 MVT::v16i8, &pshufbMask[0], 16));
4620 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4621 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4624 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4625 // and update MaskVals with new element order.
4626 BitVector InOrder(8);
4627 if (BestLoQuad >= 0) {
4628 SmallVector<int, 8> MaskV;
4629 for (int i = 0; i != 4; ++i) {
4630 int idx = MaskVals[i];
4632 MaskV.push_back(-1);
4634 } else if ((idx / 4) == BestLoQuad) {
4635 MaskV.push_back(idx & 3);
4638 MaskV.push_back(-1);
4641 for (unsigned i = 4; i != 8; ++i)
4643 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4646 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4647 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4649 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4653 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4654 // and update MaskVals with the new element order.
4655 if (BestHiQuad >= 0) {
4656 SmallVector<int, 8> MaskV;
4657 for (unsigned i = 0; i != 4; ++i)
4659 for (unsigned i = 4; i != 8; ++i) {
4660 int idx = MaskVals[i];
4662 MaskV.push_back(-1);
4664 } else if ((idx / 4) == BestHiQuad) {
4665 MaskV.push_back((idx & 3) + 4);
4668 MaskV.push_back(-1);
4671 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4674 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4675 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4677 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4681 // In case BestHi & BestLo were both -1, which means each quadword has a word
4682 // from each of the four input quadwords, calculate the InOrder bitvector now
4683 // before falling through to the insert/extract cleanup.
4684 if (BestLoQuad == -1 && BestHiQuad == -1) {
4686 for (int i = 0; i != 8; ++i)
4687 if (MaskVals[i] < 0 || MaskVals[i] == i)
4691 // The other elements are put in the right place using pextrw and pinsrw.
4692 for (unsigned i = 0; i != 8; ++i) {
4695 int EltIdx = MaskVals[i];
4698 SDValue ExtOp = (EltIdx < 8)
4699 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4700 DAG.getIntPtrConstant(EltIdx))
4701 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4702 DAG.getIntPtrConstant(EltIdx - 8));
4703 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4704 DAG.getIntPtrConstant(i));
4709 // v16i8 shuffles - Prefer shuffles in the following order:
4710 // 1. [ssse3] 1 x pshufb
4711 // 2. [ssse3] 2 x pshufb + 1 x por
4712 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4714 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4716 const X86TargetLowering &TLI) {
4717 SDValue V1 = SVOp->getOperand(0);
4718 SDValue V2 = SVOp->getOperand(1);
4719 DebugLoc dl = SVOp->getDebugLoc();
4720 SmallVector<int, 16> MaskVals;
4721 SVOp->getMask(MaskVals);
4723 // If we have SSSE3, case 1 is generated when all result bytes come from
4724 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4725 // present, fall back to case 3.
4726 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4729 for (unsigned i = 0; i < 16; ++i) {
4730 int EltIdx = MaskVals[i];
4739 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4740 if (TLI.getSubtarget()->hasSSSE3()) {
4741 SmallVector<SDValue,16> pshufbMask;
4743 // If all result elements are from one input vector, then only translate
4744 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4746 // Otherwise, we have elements from both input vectors, and must zero out
4747 // elements that come from V2 in the first mask, and V1 in the second mask
4748 // so that we can OR them together.
4749 bool TwoInputs = !(V1Only || V2Only);
4750 for (unsigned i = 0; i != 16; ++i) {
4751 int EltIdx = MaskVals[i];
4752 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4753 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4756 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4758 // If all the elements are from V2, assign it to V1 and return after
4759 // building the first pshufb.
4762 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4763 DAG.getNode(ISD::BUILD_VECTOR, dl,
4764 MVT::v16i8, &pshufbMask[0], 16));
4768 // Calculate the shuffle mask for the second input, shuffle it, and
4769 // OR it with the first shuffled input.
4771 for (unsigned i = 0; i != 16; ++i) {
4772 int EltIdx = MaskVals[i];
4774 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4777 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4779 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4780 DAG.getNode(ISD::BUILD_VECTOR, dl,
4781 MVT::v16i8, &pshufbMask[0], 16));
4782 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4785 // No SSSE3 - Calculate in place words and then fix all out of place words
4786 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4787 // the 16 different words that comprise the two doublequadword input vectors.
4788 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4789 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
4790 SDValue NewV = V2Only ? V2 : V1;
4791 for (int i = 0; i != 8; ++i) {
4792 int Elt0 = MaskVals[i*2];
4793 int Elt1 = MaskVals[i*2+1];
4795 // This word of the result is all undef, skip it.
4796 if (Elt0 < 0 && Elt1 < 0)
4799 // This word of the result is already in the correct place, skip it.
4800 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4802 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4805 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4806 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4809 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4810 // using a single extract together, load it and store it.
4811 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4812 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4813 DAG.getIntPtrConstant(Elt1 / 2));
4814 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4815 DAG.getIntPtrConstant(i));
4819 // If Elt1 is defined, extract it from the appropriate source. If the
4820 // source byte is not also odd, shift the extracted word left 8 bits
4821 // otherwise clear the bottom 8 bits if we need to do an or.
4823 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4824 DAG.getIntPtrConstant(Elt1 / 2));
4825 if ((Elt1 & 1) == 0)
4826 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4827 DAG.getConstant(8, TLI.getShiftAmountTy()));
4829 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4830 DAG.getConstant(0xFF00, MVT::i16));
4832 // If Elt0 is defined, extract it from the appropriate source. If the
4833 // source byte is not also even, shift the extracted word right 8 bits. If
4834 // Elt1 was also defined, OR the extracted values together before
4835 // inserting them in the result.
4837 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4838 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4839 if ((Elt0 & 1) != 0)
4840 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4841 DAG.getConstant(8, TLI.getShiftAmountTy()));
4843 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4844 DAG.getConstant(0x00FF, MVT::i16));
4845 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4848 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4849 DAG.getIntPtrConstant(i));
4851 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
4854 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4855 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
4856 /// done when every pair / quad of shuffle mask elements point to elements in
4857 /// the right sequence. e.g.
4858 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
4860 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4861 SelectionDAG &DAG, DebugLoc dl) {
4862 EVT VT = SVOp->getValueType(0);
4863 SDValue V1 = SVOp->getOperand(0);
4864 SDValue V2 = SVOp->getOperand(1);
4865 unsigned NumElems = VT.getVectorNumElements();
4866 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4868 switch (VT.getSimpleVT().SimpleTy) {
4869 default: assert(false && "Unexpected!");
4870 case MVT::v4f32: NewVT = MVT::v2f64; break;
4871 case MVT::v4i32: NewVT = MVT::v2i64; break;
4872 case MVT::v8i16: NewVT = MVT::v4i32; break;
4873 case MVT::v16i8: NewVT = MVT::v4i32; break;
4876 int Scale = NumElems / NewWidth;
4877 SmallVector<int, 8> MaskVec;
4878 for (unsigned i = 0; i < NumElems; i += Scale) {
4880 for (int j = 0; j < Scale; ++j) {
4881 int EltIdx = SVOp->getMaskElt(i+j);
4885 StartIdx = EltIdx - (EltIdx % Scale);
4886 if (EltIdx != StartIdx + j)
4890 MaskVec.push_back(-1);
4892 MaskVec.push_back(StartIdx / Scale);
4895 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
4896 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
4897 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4900 /// getVZextMovL - Return a zero-extending vector move low node.
4902 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4903 SDValue SrcOp, SelectionDAG &DAG,
4904 const X86Subtarget *Subtarget, DebugLoc dl) {
4905 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4906 LoadSDNode *LD = NULL;
4907 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4908 LD = dyn_cast<LoadSDNode>(SrcOp);
4910 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4912 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4913 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
4914 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4915 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
4916 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4918 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4919 return DAG.getNode(ISD::BITCAST, dl, VT,
4920 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4921 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4929 return DAG.getNode(ISD::BITCAST, dl, VT,
4930 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4931 DAG.getNode(ISD::BITCAST, dl,
4935 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4938 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4939 SDValue V1 = SVOp->getOperand(0);
4940 SDValue V2 = SVOp->getOperand(1);
4941 DebugLoc dl = SVOp->getDebugLoc();
4942 EVT VT = SVOp->getValueType(0);
4944 SmallVector<std::pair<int, int>, 8> Locs;
4946 SmallVector<int, 8> Mask1(4U, -1);
4947 SmallVector<int, 8> PermMask;
4948 SVOp->getMask(PermMask);
4952 for (unsigned i = 0; i != 4; ++i) {
4953 int Idx = PermMask[i];
4955 Locs[i] = std::make_pair(-1, -1);
4957 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4959 Locs[i] = std::make_pair(0, NumLo);
4963 Locs[i] = std::make_pair(1, NumHi);
4965 Mask1[2+NumHi] = Idx;
4971 if (NumLo <= 2 && NumHi <= 2) {
4972 // If no more than two elements come from either vector. This can be
4973 // implemented with two shuffles. First shuffle gather the elements.
4974 // The second shuffle, which takes the first shuffle as both of its
4975 // vector operands, put the elements into the right order.
4976 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4978 SmallVector<int, 8> Mask2(4U, -1);
4980 for (unsigned i = 0; i != 4; ++i) {
4981 if (Locs[i].first == -1)
4984 unsigned Idx = (i < 2) ? 0 : 4;
4985 Idx += Locs[i].first * 2 + Locs[i].second;
4990 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4991 } else if (NumLo == 3 || NumHi == 3) {
4992 // Otherwise, we must have three elements from one vector, call it X, and
4993 // one element from the other, call it Y. First, use a shufps to build an
4994 // intermediate vector with the one element from Y and the element from X
4995 // that will be in the same half in the final destination (the indexes don't
4996 // matter). Then, use a shufps to build the final vector, taking the half
4997 // containing the element from Y from the intermediate, and the other half
5000 // Normalize it so the 3 elements come from V1.
5001 CommuteVectorShuffleMask(PermMask, VT);
5005 // Find the element from V2.
5007 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5008 int Val = PermMask[HiIndex];
5015 Mask1[0] = PermMask[HiIndex];
5017 Mask1[2] = PermMask[HiIndex^1];
5019 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5022 Mask1[0] = PermMask[0];
5023 Mask1[1] = PermMask[1];
5024 Mask1[2] = HiIndex & 1 ? 6 : 4;
5025 Mask1[3] = HiIndex & 1 ? 4 : 6;
5026 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5028 Mask1[0] = HiIndex & 1 ? 2 : 0;
5029 Mask1[1] = HiIndex & 1 ? 0 : 2;
5030 Mask1[2] = PermMask[2];
5031 Mask1[3] = PermMask[3];
5036 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5040 // Break it into (shuffle shuffle_hi, shuffle_lo).
5042 SmallVector<int,8> LoMask(4U, -1);
5043 SmallVector<int,8> HiMask(4U, -1);
5045 SmallVector<int,8> *MaskPtr = &LoMask;
5046 unsigned MaskIdx = 0;
5049 for (unsigned i = 0; i != 4; ++i) {
5056 int Idx = PermMask[i];
5058 Locs[i] = std::make_pair(-1, -1);
5059 } else if (Idx < 4) {
5060 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5061 (*MaskPtr)[LoIdx] = Idx;
5064 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5065 (*MaskPtr)[HiIdx] = Idx;
5070 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5071 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5072 SmallVector<int, 8> MaskOps;
5073 for (unsigned i = 0; i != 4; ++i) {
5074 if (Locs[i].first == -1) {
5075 MaskOps.push_back(-1);
5077 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5078 MaskOps.push_back(Idx);
5081 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5084 static bool MayFoldVectorLoad(SDValue V) {
5085 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5086 V = V.getOperand(0);
5087 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5088 V = V.getOperand(0);
5094 // FIXME: the version above should always be used. Since there's
5095 // a bug where several vector shuffles can't be folded because the
5096 // DAG is not updated during lowering and a node claims to have two
5097 // uses while it only has one, use this version, and let isel match
5098 // another instruction if the load really happens to have more than
5099 // one use. Remove this version after this bug get fixed.
5100 // rdar://8434668, PR8156
5101 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5102 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5103 V = V.getOperand(0);
5104 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5105 V = V.getOperand(0);
5106 if (ISD::isNormalLoad(V.getNode()))
5111 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5112 /// a vector extract, and if both can be later optimized into a single load.
5113 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5114 /// here because otherwise a target specific shuffle node is going to be
5115 /// emitted for this shuffle, and the optimization not done.
5116 /// FIXME: This is probably not the best approach, but fix the problem
5117 /// until the right path is decided.
5119 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5120 const TargetLowering &TLI) {
5121 EVT VT = V.getValueType();
5122 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5124 // Be sure that the vector shuffle is present in a pattern like this:
5125 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5129 SDNode *N = *V.getNode()->use_begin();
5130 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5133 SDValue EltNo = N->getOperand(1);
5134 if (!isa<ConstantSDNode>(EltNo))
5137 // If the bit convert changed the number of elements, it is unsafe
5138 // to examine the mask.
5139 bool HasShuffleIntoBitcast = false;
5140 if (V.getOpcode() == ISD::BITCAST) {
5141 EVT SrcVT = V.getOperand(0).getValueType();
5142 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5144 V = V.getOperand(0);
5145 HasShuffleIntoBitcast = true;
5148 // Select the input vector, guarding against out of range extract vector.
5149 unsigned NumElems = VT.getVectorNumElements();
5150 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5151 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5152 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5154 // Skip one more bit_convert if necessary
5155 if (V.getOpcode() == ISD::BITCAST)
5156 V = V.getOperand(0);
5158 if (ISD::isNormalLoad(V.getNode())) {
5159 // Is the original load suitable?
5160 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5162 // FIXME: avoid the multi-use bug that is preventing lots of
5163 // of foldings to be detected, this is still wrong of course, but
5164 // give the temporary desired behavior, and if it happens that
5165 // the load has real more uses, during isel it will not fold, and
5166 // will generate poor code.
5167 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5170 if (!HasShuffleIntoBitcast)
5173 // If there's a bitcast before the shuffle, check if the load type and
5174 // alignment is valid.
5175 unsigned Align = LN0->getAlignment();
5177 TLI.getTargetData()->getABITypeAlignment(
5178 VT.getTypeForEVT(*DAG.getContext()));
5180 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5188 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5189 EVT VT = Op.getValueType();
5191 // Canonizalize to v2f64.
5192 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
5193 return DAG.getNode(ISD::BITCAST, dl, VT,
5194 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5199 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5201 SDValue V1 = Op.getOperand(0);
5202 SDValue V2 = Op.getOperand(1);
5203 EVT VT = Op.getValueType();
5205 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5207 if (HasSSE2 && VT == MVT::v2f64)
5208 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5211 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5215 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5216 SDValue V1 = Op.getOperand(0);
5217 SDValue V2 = Op.getOperand(1);
5218 EVT VT = Op.getValueType();
5220 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5221 "unsupported shuffle type");
5223 if (V2.getOpcode() == ISD::UNDEF)
5227 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5231 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5232 SDValue V1 = Op.getOperand(0);
5233 SDValue V2 = Op.getOperand(1);
5234 EVT VT = Op.getValueType();
5235 unsigned NumElems = VT.getVectorNumElements();
5237 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5238 // operand of these instructions is only memory, so check if there's a
5239 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5241 bool CanFoldLoad = false;
5243 // Trivial case, when V2 comes from a load.
5244 if (MayFoldVectorLoad(V2))
5247 // When V1 is a load, it can be folded later into a store in isel, example:
5248 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5250 // (MOVLPSmr addr:$src1, VR128:$src2)
5251 // So, recognize this potential and also use MOVLPS or MOVLPD
5252 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5256 if (HasSSE2 && NumElems == 2)
5257 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5260 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5263 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5264 // movl and movlp will both match v2i64, but v2i64 is never matched by
5265 // movl earlier because we make it strict to avoid messing with the movlp load
5266 // folding logic (see the code above getMOVLP call). Match it here then,
5267 // this is horrible, but will stay like this until we move all shuffle
5268 // matching to x86 specific nodes. Note that for the 1st condition all
5269 // types are matched with movsd.
5270 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5271 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5273 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5276 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5278 // Invert the operand order and use SHUFPS to match it.
5279 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5280 X86::getShuffleSHUFImmediate(SVOp), DAG);
5283 static inline unsigned getUNPCKLOpcode(EVT VT) {
5284 switch(VT.getSimpleVT().SimpleTy) {
5285 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5286 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5287 case MVT::v4f32: return X86ISD::UNPCKLPS;
5288 case MVT::v2f64: return X86ISD::UNPCKLPD;
5289 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5290 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5292 llvm_unreachable("Unknow type for unpckl");
5297 static inline unsigned getUNPCKHOpcode(EVT VT) {
5298 switch(VT.getSimpleVT().SimpleTy) {
5299 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5300 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5301 case MVT::v4f32: return X86ISD::UNPCKHPS;
5302 case MVT::v2f64: return X86ISD::UNPCKHPD;
5303 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5304 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5306 llvm_unreachable("Unknow type for unpckh");
5312 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5313 const TargetLowering &TLI,
5314 const X86Subtarget *Subtarget) {
5315 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5316 EVT VT = Op.getValueType();
5317 DebugLoc dl = Op.getDebugLoc();
5318 SDValue V1 = Op.getOperand(0);
5319 SDValue V2 = Op.getOperand(1);
5321 if (isZeroShuffle(SVOp))
5322 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5324 // Handle splat operations
5325 if (SVOp->isSplat()) {
5326 // Special case, this is the only place now where it's
5327 // allowed to return a vector_shuffle operation without
5328 // using a target specific node, because *hopefully* it
5329 // will be optimized away by the dag combiner.
5330 if (VT.getVectorNumElements() <= 4 &&
5331 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5334 // Handle splats by matching through known masks
5335 if (VT.getVectorNumElements() <= 4)
5338 // Canonicalize all of the remaining to v4f32.
5339 return PromoteSplat(SVOp, DAG);
5342 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5344 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5345 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5346 if (NewOp.getNode())
5347 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
5348 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5349 // FIXME: Figure out a cleaner way to do this.
5350 // Try to make use of movq to zero out the top part.
5351 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5352 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5353 if (NewOp.getNode()) {
5354 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5355 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5356 DAG, Subtarget, dl);
5358 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5359 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5360 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5361 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5362 DAG, Subtarget, dl);
5369 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5371 SDValue V1 = Op.getOperand(0);
5372 SDValue V2 = Op.getOperand(1);
5373 EVT VT = Op.getValueType();
5374 DebugLoc dl = Op.getDebugLoc();
5375 unsigned NumElems = VT.getVectorNumElements();
5376 bool isMMX = VT.getSizeInBits() == 64;
5377 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5378 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5379 bool V1IsSplat = false;
5380 bool V2IsSplat = false;
5381 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5382 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5383 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5384 MachineFunction &MF = DAG.getMachineFunction();
5385 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5387 // Shuffle operations on MMX not supported.
5391 // Vector shuffle lowering takes 3 steps:
5393 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5394 // narrowing and commutation of operands should be handled.
5395 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5397 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5398 // so the shuffle can be broken into other shuffles and the legalizer can
5399 // try the lowering again.
5401 // The general ideia is that no vector_shuffle operation should be left to
5402 // be matched during isel, all of them must be converted to a target specific
5405 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5406 // narrowing and commutation of operands should be handled. The actual code
5407 // doesn't include all of those, work in progress...
5408 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5409 if (NewOp.getNode())
5412 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5413 // unpckh_undef). Only use pshufd if speed is more important than size.
5414 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5415 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5416 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5417 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5418 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5419 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5421 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5422 RelaxedMayFoldVectorLoad(V1))
5423 return getMOVDDup(Op, dl, V1, DAG);
5425 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
5426 return getMOVHighToLow(Op, dl, DAG);
5428 // Use to match splats
5429 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
5430 (VT == MVT::v2f64 || VT == MVT::v2i64))
5431 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5433 if (X86::isPSHUFDMask(SVOp)) {
5434 // The actual implementation will match the mask in the if above and then
5435 // during isel it can match several different instructions, not only pshufd
5436 // as its name says, sad but true, emulate the behavior for now...
5437 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5438 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5440 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5442 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5443 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5445 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5446 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5449 if (VT == MVT::v4f32)
5450 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5454 // Check if this can be converted into a logical shift.
5455 bool isLeft = false;
5458 bool isShift = getSubtarget()->hasSSE2() &&
5459 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5460 if (isShift && ShVal.hasOneUse()) {
5461 // If the shifted value has multiple uses, it may be cheaper to use
5462 // v_set0 + movlhps or movhlps, etc.
5463 EVT EltVT = VT.getVectorElementType();
5464 ShAmt *= EltVT.getSizeInBits();
5465 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5468 if (X86::isMOVLMask(SVOp)) {
5471 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5472 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5473 if (!X86::isMOVLPMask(SVOp)) {
5474 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5475 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5477 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5478 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5482 // FIXME: fold these into legal mask.
5483 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5484 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5486 if (X86::isMOVHLPSMask(SVOp))
5487 return getMOVHighToLow(Op, dl, DAG);
5489 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5490 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5492 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5493 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5495 if (X86::isMOVLPMask(SVOp))
5496 return getMOVLP(Op, dl, DAG, HasSSE2);
5498 if (ShouldXformToMOVHLPS(SVOp) ||
5499 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5500 return CommuteVectorShuffle(SVOp, DAG);
5503 // No better options. Use a vshl / vsrl.
5504 EVT EltVT = VT.getVectorElementType();
5505 ShAmt *= EltVT.getSizeInBits();
5506 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5509 bool Commuted = false;
5510 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5511 // 1,1,1,1 -> v8i16 though.
5512 V1IsSplat = isSplatVector(V1.getNode());
5513 V2IsSplat = isSplatVector(V2.getNode());
5515 // Canonicalize the splat or undef, if present, to be on the RHS.
5516 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5517 Op = CommuteVectorShuffle(SVOp, DAG);
5518 SVOp = cast<ShuffleVectorSDNode>(Op);
5519 V1 = SVOp->getOperand(0);
5520 V2 = SVOp->getOperand(1);
5521 std::swap(V1IsSplat, V2IsSplat);
5522 std::swap(V1IsUndef, V2IsUndef);
5526 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5527 // Shuffling low element of v1 into undef, just return v1.
5530 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5531 // the instruction selector will not match, so get a canonical MOVL with
5532 // swapped operands to undo the commute.
5533 return getMOVL(DAG, dl, VT, V2, V1);
5536 if (X86::isUNPCKLMask(SVOp))
5537 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5539 if (X86::isUNPCKHMask(SVOp))
5540 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5543 // Normalize mask so all entries that point to V2 points to its first
5544 // element then try to match unpck{h|l} again. If match, return a
5545 // new vector_shuffle with the corrected mask.
5546 SDValue NewMask = NormalizeMask(SVOp, DAG);
5547 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5548 if (NSVOp != SVOp) {
5549 if (X86::isUNPCKLMask(NSVOp, true)) {
5551 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5558 // Commute is back and try unpck* again.
5559 // FIXME: this seems wrong.
5560 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5561 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5563 if (X86::isUNPCKLMask(NewSVOp))
5564 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5566 if (X86::isUNPCKHMask(NewSVOp))
5567 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5570 // Normalize the node to match x86 shuffle ops if needed
5571 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5572 return CommuteVectorShuffle(SVOp, DAG);
5574 // The checks below are all present in isShuffleMaskLegal, but they are
5575 // inlined here right now to enable us to directly emit target specific
5576 // nodes, and remove one by one until they don't return Op anymore.
5577 SmallVector<int, 16> M;
5580 if (isPALIGNRMask(M, VT, HasSSSE3))
5581 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5582 X86::getShufflePALIGNRImmediate(SVOp),
5585 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5586 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5587 if (VT == MVT::v2f64)
5588 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
5589 if (VT == MVT::v2i64)
5590 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5593 if (isPSHUFHWMask(M, VT))
5594 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5595 X86::getShufflePSHUFHWImmediate(SVOp),
5598 if (isPSHUFLWMask(M, VT))
5599 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5600 X86::getShufflePSHUFLWImmediate(SVOp),
5603 if (isSHUFPMask(M, VT)) {
5604 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5605 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5606 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5608 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5609 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5613 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5614 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5615 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5616 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5617 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5618 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5620 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5621 if (VT == MVT::v8i16) {
5622 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5623 if (NewOp.getNode())
5627 if (VT == MVT::v16i8) {
5628 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5629 if (NewOp.getNode())
5633 // Handle all 4 wide cases with a number of shuffles.
5635 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5641 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5642 SelectionDAG &DAG) const {
5643 EVT VT = Op.getValueType();
5644 DebugLoc dl = Op.getDebugLoc();
5645 if (VT.getSizeInBits() == 8) {
5646 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5647 Op.getOperand(0), Op.getOperand(1));
5648 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5649 DAG.getValueType(VT));
5650 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5651 } else if (VT.getSizeInBits() == 16) {
5652 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5653 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5655 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5657 DAG.getNode(ISD::BITCAST, dl,
5661 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5662 Op.getOperand(0), Op.getOperand(1));
5663 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5664 DAG.getValueType(VT));
5665 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5666 } else if (VT == MVT::f32) {
5667 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5668 // the result back to FR32 register. It's only worth matching if the
5669 // result has a single use which is a store or a bitcast to i32. And in
5670 // the case of a store, it's not worth it if the index is a constant 0,
5671 // because a MOVSSmr can be used instead, which is smaller and faster.
5672 if (!Op.hasOneUse())
5674 SDNode *User = *Op.getNode()->use_begin();
5675 if ((User->getOpcode() != ISD::STORE ||
5676 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5677 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5678 (User->getOpcode() != ISD::BITCAST ||
5679 User->getValueType(0) != MVT::i32))
5681 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5682 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
5685 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
5686 } else if (VT == MVT::i32) {
5687 // ExtractPS works with constant index.
5688 if (isa<ConstantSDNode>(Op.getOperand(1)))
5696 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5697 SelectionDAG &DAG) const {
5698 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5701 if (Subtarget->hasSSE41()) {
5702 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5707 EVT VT = Op.getValueType();
5708 DebugLoc dl = Op.getDebugLoc();
5709 // TODO: handle v16i8.
5710 if (VT.getSizeInBits() == 16) {
5711 SDValue Vec = Op.getOperand(0);
5712 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5714 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5715 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5716 DAG.getNode(ISD::BITCAST, dl,
5719 // Transform it so it match pextrw which produces a 32-bit result.
5720 EVT EltVT = MVT::i32;
5721 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5722 Op.getOperand(0), Op.getOperand(1));
5723 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5724 DAG.getValueType(VT));
5725 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5726 } else if (VT.getSizeInBits() == 32) {
5727 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5731 // SHUFPS the element to the lowest double word, then movss.
5732 int Mask[4] = { Idx, -1, -1, -1 };
5733 EVT VVT = Op.getOperand(0).getValueType();
5734 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5735 DAG.getUNDEF(VVT), Mask);
5736 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5737 DAG.getIntPtrConstant(0));
5738 } else if (VT.getSizeInBits() == 64) {
5739 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5740 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5741 // to match extract_elt for f64.
5742 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5746 // UNPCKHPD the element to the lowest double word, then movsd.
5747 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5748 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5749 int Mask[2] = { 1, -1 };
5750 EVT VVT = Op.getOperand(0).getValueType();
5751 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5752 DAG.getUNDEF(VVT), Mask);
5753 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5754 DAG.getIntPtrConstant(0));
5761 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5762 SelectionDAG &DAG) const {
5763 EVT VT = Op.getValueType();
5764 EVT EltVT = VT.getVectorElementType();
5765 DebugLoc dl = Op.getDebugLoc();
5767 SDValue N0 = Op.getOperand(0);
5768 SDValue N1 = Op.getOperand(1);
5769 SDValue N2 = Op.getOperand(2);
5771 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5772 isa<ConstantSDNode>(N2)) {
5774 if (VT == MVT::v8i16)
5775 Opc = X86ISD::PINSRW;
5776 else if (VT == MVT::v16i8)
5777 Opc = X86ISD::PINSRB;
5779 Opc = X86ISD::PINSRB;
5781 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5783 if (N1.getValueType() != MVT::i32)
5784 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5785 if (N2.getValueType() != MVT::i32)
5786 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5787 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5788 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5789 // Bits [7:6] of the constant are the source select. This will always be
5790 // zero here. The DAG Combiner may combine an extract_elt index into these
5791 // bits. For example (insert (extract, 3), 2) could be matched by putting
5792 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5793 // Bits [5:4] of the constant are the destination select. This is the
5794 // value of the incoming immediate.
5795 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5796 // combine either bitwise AND or insert of float 0.0 to set these bits.
5797 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5798 // Create this as a scalar to vector..
5799 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5800 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5801 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5802 // PINSR* works with constant index.
5809 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5810 EVT VT = Op.getValueType();
5811 EVT EltVT = VT.getVectorElementType();
5813 if (Subtarget->hasSSE41())
5814 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5816 if (EltVT == MVT::i8)
5819 DebugLoc dl = Op.getDebugLoc();
5820 SDValue N0 = Op.getOperand(0);
5821 SDValue N1 = Op.getOperand(1);
5822 SDValue N2 = Op.getOperand(2);
5824 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5825 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5826 // as its second argument.
5827 if (N1.getValueType() != MVT::i32)
5828 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5829 if (N2.getValueType() != MVT::i32)
5830 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5831 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
5837 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5838 DebugLoc dl = Op.getDebugLoc();
5840 if (Op.getValueType() == MVT::v1i64 &&
5841 Op.getOperand(0).getValueType() == MVT::i64)
5842 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5844 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5845 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
5846 "Expected an SSE type!");
5847 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
5848 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
5851 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5852 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5853 // one of the above mentioned nodes. It has to be wrapped because otherwise
5854 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5855 // be used to form addressing mode. These wrapped nodes will be selected
5858 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5859 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5861 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5863 unsigned char OpFlag = 0;
5864 unsigned WrapperKind = X86ISD::Wrapper;
5865 CodeModel::Model M = getTargetMachine().getCodeModel();
5867 if (Subtarget->isPICStyleRIPRel() &&
5868 (M == CodeModel::Small || M == CodeModel::Kernel))
5869 WrapperKind = X86ISD::WrapperRIP;
5870 else if (Subtarget->isPICStyleGOT())
5871 OpFlag = X86II::MO_GOTOFF;
5872 else if (Subtarget->isPICStyleStubPIC())
5873 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5875 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5877 CP->getOffset(), OpFlag);
5878 DebugLoc DL = CP->getDebugLoc();
5879 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5880 // With PIC, the address is actually $g + Offset.
5882 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5883 DAG.getNode(X86ISD::GlobalBaseReg,
5884 DebugLoc(), getPointerTy()),
5891 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5892 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5894 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5896 unsigned char OpFlag = 0;
5897 unsigned WrapperKind = X86ISD::Wrapper;
5898 CodeModel::Model M = getTargetMachine().getCodeModel();
5900 if (Subtarget->isPICStyleRIPRel() &&
5901 (M == CodeModel::Small || M == CodeModel::Kernel))
5902 WrapperKind = X86ISD::WrapperRIP;
5903 else if (Subtarget->isPICStyleGOT())
5904 OpFlag = X86II::MO_GOTOFF;
5905 else if (Subtarget->isPICStyleStubPIC())
5906 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5908 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5910 DebugLoc DL = JT->getDebugLoc();
5911 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5913 // With PIC, the address is actually $g + Offset.
5915 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5916 DAG.getNode(X86ISD::GlobalBaseReg,
5917 DebugLoc(), getPointerTy()),
5924 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5925 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5927 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5929 unsigned char OpFlag = 0;
5930 unsigned WrapperKind = X86ISD::Wrapper;
5931 CodeModel::Model M = getTargetMachine().getCodeModel();
5933 if (Subtarget->isPICStyleRIPRel() &&
5934 (M == CodeModel::Small || M == CodeModel::Kernel))
5935 WrapperKind = X86ISD::WrapperRIP;
5936 else if (Subtarget->isPICStyleGOT())
5937 OpFlag = X86II::MO_GOTOFF;
5938 else if (Subtarget->isPICStyleStubPIC())
5939 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5941 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5943 DebugLoc DL = Op.getDebugLoc();
5944 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5947 // With PIC, the address is actually $g + Offset.
5948 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5949 !Subtarget->is64Bit()) {
5950 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5951 DAG.getNode(X86ISD::GlobalBaseReg,
5952 DebugLoc(), getPointerTy()),
5960 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5961 // Create the TargetBlockAddressAddress node.
5962 unsigned char OpFlags =
5963 Subtarget->ClassifyBlockAddressReference();
5964 CodeModel::Model M = getTargetMachine().getCodeModel();
5965 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5966 DebugLoc dl = Op.getDebugLoc();
5967 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5968 /*isTarget=*/true, OpFlags);
5970 if (Subtarget->isPICStyleRIPRel() &&
5971 (M == CodeModel::Small || M == CodeModel::Kernel))
5972 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5974 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5976 // With PIC, the address is actually $g + Offset.
5977 if (isGlobalRelativeToPICBase(OpFlags)) {
5978 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5979 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5987 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5989 SelectionDAG &DAG) const {
5990 // Create the TargetGlobalAddress node, folding in the constant
5991 // offset if it is legal.
5992 unsigned char OpFlags =
5993 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5994 CodeModel::Model M = getTargetMachine().getCodeModel();
5996 if (OpFlags == X86II::MO_NO_FLAG &&
5997 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5998 // A direct static reference to a global.
5999 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
6002 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
6005 if (Subtarget->isPICStyleRIPRel() &&
6006 (M == CodeModel::Small || M == CodeModel::Kernel))
6007 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6009 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6011 // With PIC, the address is actually $g + Offset.
6012 if (isGlobalRelativeToPICBase(OpFlags)) {
6013 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6014 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6018 // For globals that require a load from a stub to get the address, emit the
6020 if (isGlobalStubReference(OpFlags))
6021 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6022 MachinePointerInfo::getGOT(), false, false, 0);
6024 // If there was a non-zero offset that we didn't fold, create an explicit
6027 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6028 DAG.getConstant(Offset, getPointerTy()));
6034 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6035 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6036 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6037 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6041 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6042 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6043 unsigned char OperandFlags) {
6044 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6045 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6046 DebugLoc dl = GA->getDebugLoc();
6047 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6048 GA->getValueType(0),
6052 SDValue Ops[] = { Chain, TGA, *InFlag };
6053 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6055 SDValue Ops[] = { Chain, TGA };
6056 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6059 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6060 MFI->setAdjustsStack(true);
6062 SDValue Flag = Chain.getValue(1);
6063 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6066 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6068 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6071 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6072 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6073 DAG.getNode(X86ISD::GlobalBaseReg,
6074 DebugLoc(), PtrVT), InFlag);
6075 InFlag = Chain.getValue(1);
6077 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6080 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6082 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6084 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6085 X86::RAX, X86II::MO_TLSGD);
6088 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6089 // "local exec" model.
6090 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6091 const EVT PtrVT, TLSModel::Model model,
6093 DebugLoc dl = GA->getDebugLoc();
6095 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6096 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6097 is64Bit ? 257 : 256));
6099 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6100 DAG.getIntPtrConstant(0),
6101 MachinePointerInfo(Ptr), false, false, 0);
6103 unsigned char OperandFlags = 0;
6104 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6106 unsigned WrapperKind = X86ISD::Wrapper;
6107 if (model == TLSModel::LocalExec) {
6108 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6109 } else if (is64Bit) {
6110 assert(model == TLSModel::InitialExec);
6111 OperandFlags = X86II::MO_GOTTPOFF;
6112 WrapperKind = X86ISD::WrapperRIP;
6114 assert(model == TLSModel::InitialExec);
6115 OperandFlags = X86II::MO_INDNTPOFF;
6118 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6120 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6121 GA->getValueType(0),
6122 GA->getOffset(), OperandFlags);
6123 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6125 if (model == TLSModel::InitialExec)
6126 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6127 MachinePointerInfo::getGOT(), false, false, 0);
6129 // The address of the thread local variable is the add of the thread
6130 // pointer with the offset of the variable.
6131 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6135 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6137 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6138 const GlobalValue *GV = GA->getGlobal();
6140 if (Subtarget->isTargetELF()) {
6141 // TODO: implement the "local dynamic" model
6142 // TODO: implement the "initial exec"model for pic executables
6144 // If GV is an alias then use the aliasee for determining
6145 // thread-localness.
6146 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6147 GV = GA->resolveAliasedGlobal(false);
6149 TLSModel::Model model
6150 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6153 case TLSModel::GeneralDynamic:
6154 case TLSModel::LocalDynamic: // not implemented
6155 if (Subtarget->is64Bit())
6156 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6157 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6159 case TLSModel::InitialExec:
6160 case TLSModel::LocalExec:
6161 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6162 Subtarget->is64Bit());
6164 } else if (Subtarget->isTargetDarwin()) {
6165 // Darwin only has one model of TLS. Lower to that.
6166 unsigned char OpFlag = 0;
6167 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6168 X86ISD::WrapperRIP : X86ISD::Wrapper;
6170 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6172 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6173 !Subtarget->is64Bit();
6175 OpFlag = X86II::MO_TLVP_PIC_BASE;
6177 OpFlag = X86II::MO_TLVP;
6178 DebugLoc DL = Op.getDebugLoc();
6179 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6180 GA->getValueType(0),
6181 GA->getOffset(), OpFlag);
6182 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6184 // With PIC32, the address is actually $g + Offset.
6186 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6187 DAG.getNode(X86ISD::GlobalBaseReg,
6188 DebugLoc(), getPointerTy()),
6191 // Lowering the machine isd will make sure everything is in the right
6193 SDValue Chain = DAG.getEntryNode();
6194 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6195 SDValue Args[] = { Chain, Offset };
6196 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
6198 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6199 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6200 MFI->setAdjustsStack(true);
6202 // And our return value (tls address) is in the standard call return value
6204 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6205 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6209 "TLS not implemented for this target.");
6211 llvm_unreachable("Unreachable");
6216 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6217 /// take a 2 x i32 value to shift plus a shift amount.
6218 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6219 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6220 EVT VT = Op.getValueType();
6221 unsigned VTBits = VT.getSizeInBits();
6222 DebugLoc dl = Op.getDebugLoc();
6223 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6224 SDValue ShOpLo = Op.getOperand(0);
6225 SDValue ShOpHi = Op.getOperand(1);
6226 SDValue ShAmt = Op.getOperand(2);
6227 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6228 DAG.getConstant(VTBits - 1, MVT::i8))
6229 : DAG.getConstant(0, VT);
6232 if (Op.getOpcode() == ISD::SHL_PARTS) {
6233 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6234 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6236 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6237 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6240 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6241 DAG.getConstant(VTBits, MVT::i8));
6242 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6243 AndNode, DAG.getConstant(0, MVT::i8));
6246 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6247 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6248 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6250 if (Op.getOpcode() == ISD::SHL_PARTS) {
6251 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6252 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6254 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6255 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6258 SDValue Ops[2] = { Lo, Hi };
6259 return DAG.getMergeValues(Ops, 2, dl);
6262 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6263 SelectionDAG &DAG) const {
6264 EVT SrcVT = Op.getOperand(0).getValueType();
6266 if (SrcVT.isVector())
6269 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6270 "Unknown SINT_TO_FP to lower!");
6272 // These are really Legal; return the operand so the caller accepts it as
6274 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6276 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6277 Subtarget->is64Bit()) {
6281 DebugLoc dl = Op.getDebugLoc();
6282 unsigned Size = SrcVT.getSizeInBits()/8;
6283 MachineFunction &MF = DAG.getMachineFunction();
6284 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6285 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6286 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6288 MachinePointerInfo::getFixedStack(SSFI),
6290 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6293 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6295 SelectionDAG &DAG) const {
6297 DebugLoc DL = Op.getDebugLoc();
6299 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6301 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
6303 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6305 unsigned ByteSize = SrcVT.getSizeInBits()/8;
6307 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6308 MachineMemOperand *MMO =
6309 DAG.getMachineFunction()
6310 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6311 MachineMemOperand::MOLoad, ByteSize, ByteSize);
6313 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6314 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
6316 Tys, Ops, array_lengthof(Ops),
6320 Chain = Result.getValue(1);
6321 SDValue InFlag = Result.getValue(2);
6323 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6324 // shouldn't be necessary except that RFP cannot be live across
6325 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6326 MachineFunction &MF = DAG.getMachineFunction();
6327 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
6328 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
6329 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6330 Tys = DAG.getVTList(MVT::Other);
6332 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6334 MachineMemOperand *MMO =
6335 DAG.getMachineFunction()
6336 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6337 MachineMemOperand::MOStore, SSFISize, SSFISize);
6339 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
6340 Ops, array_lengthof(Ops),
6341 Op.getValueType(), MMO);
6342 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
6343 MachinePointerInfo::getFixedStack(SSFI),
6350 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6351 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6352 SelectionDAG &DAG) const {
6353 // This algorithm is not obvious. Here it is in C code, more or less:
6355 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6356 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6357 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6359 // Copy ints to xmm registers.
6360 __m128i xh = _mm_cvtsi32_si128( hi );
6361 __m128i xl = _mm_cvtsi32_si128( lo );
6363 // Combine into low half of a single xmm register.
6364 __m128i x = _mm_unpacklo_epi32( xh, xl );
6368 // Merge in appropriate exponents to give the integer bits the right
6370 x = _mm_unpacklo_epi32( x, exp );
6372 // Subtract away the biases to deal with the IEEE-754 double precision
6374 d = _mm_sub_pd( (__m128d) x, bias );
6376 // All conversions up to here are exact. The correctly rounded result is
6377 // calculated using the current rounding mode using the following
6379 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6380 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6381 // store doesn't really need to be here (except
6382 // maybe to zero the other double)
6387 DebugLoc dl = Op.getDebugLoc();
6388 LLVMContext *Context = DAG.getContext();
6390 // Build some magic constants.
6391 std::vector<Constant*> CV0;
6392 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6393 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6394 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6395 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6396 Constant *C0 = ConstantVector::get(CV0);
6397 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6399 std::vector<Constant*> CV1;
6401 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6403 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6404 Constant *C1 = ConstantVector::get(CV1);
6405 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6407 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6408 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6410 DAG.getIntPtrConstant(1)));
6411 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6412 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6414 DAG.getIntPtrConstant(0)));
6415 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6416 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6417 MachinePointerInfo::getConstantPool(),
6419 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6420 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
6421 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6422 MachinePointerInfo::getConstantPool(),
6424 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6426 // Add the halves; easiest way is to swap them into another reg first.
6427 int ShufMask[2] = { 1, -1 };
6428 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6429 DAG.getUNDEF(MVT::v2f64), ShufMask);
6430 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6431 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6432 DAG.getIntPtrConstant(0));
6435 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6436 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6437 SelectionDAG &DAG) const {
6438 DebugLoc dl = Op.getDebugLoc();
6439 // FP constant to bias correct the final result.
6440 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6443 // Load the 32-bit value into an XMM register.
6444 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6445 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6447 DAG.getIntPtrConstant(0)));
6449 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6450 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
6451 DAG.getIntPtrConstant(0));
6453 // Or the load with the bias.
6454 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6455 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6456 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6458 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6459 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6460 MVT::v2f64, Bias)));
6461 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6462 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
6463 DAG.getIntPtrConstant(0));
6465 // Subtract the bias.
6466 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6468 // Handle final rounding.
6469 EVT DestVT = Op.getValueType();
6471 if (DestVT.bitsLT(MVT::f64)) {
6472 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6473 DAG.getIntPtrConstant(0));
6474 } else if (DestVT.bitsGT(MVT::f64)) {
6475 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6478 // Handle final rounding.
6482 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6483 SelectionDAG &DAG) const {
6484 SDValue N0 = Op.getOperand(0);
6485 DebugLoc dl = Op.getDebugLoc();
6487 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6488 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6489 // the optimization here.
6490 if (DAG.SignBitIsZero(N0))
6491 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6493 EVT SrcVT = N0.getValueType();
6494 EVT DstVT = Op.getValueType();
6495 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6496 return LowerUINT_TO_FP_i64(Op, DAG);
6497 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6498 return LowerUINT_TO_FP_i32(Op, DAG);
6500 // Make a 64-bit buffer, and use it to build an FILD.
6501 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6502 if (SrcVT == MVT::i32) {
6503 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6504 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6505 getPointerTy(), StackSlot, WordOff);
6506 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6507 StackSlot, MachinePointerInfo(),
6509 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6510 OffsetSlot, MachinePointerInfo(),
6512 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6516 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6517 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6518 StackSlot, MachinePointerInfo(),
6520 // For i64 source, we need to add the appropriate power of 2 if the input
6521 // was negative. This is the same as the optimization in
6522 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6523 // we must be careful to do the computation in x87 extended precision, not
6524 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6525 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6526 MachineMemOperand *MMO =
6527 DAG.getMachineFunction()
6528 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6529 MachineMemOperand::MOLoad, 8, 8);
6531 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6532 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6533 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
6536 APInt FF(32, 0x5F800000ULL);
6538 // Check whether the sign bit is set.
6539 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6540 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6543 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6544 SDValue FudgePtr = DAG.getConstantPool(
6545 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6548 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6549 SDValue Zero = DAG.getIntPtrConstant(0);
6550 SDValue Four = DAG.getIntPtrConstant(4);
6551 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6553 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6555 // Load the value out, extending it from f32 to f80.
6556 // FIXME: Avoid the extend by constructing the right constant pool?
6557 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6558 FudgePtr, MachinePointerInfo::getConstantPool(),
6559 MVT::f32, false, false, 4);
6560 // Extend everything to 80 bits to force it to be done on x87.
6561 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6562 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6565 std::pair<SDValue,SDValue> X86TargetLowering::
6566 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6567 DebugLoc DL = Op.getDebugLoc();
6569 EVT DstTy = Op.getValueType();
6572 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6576 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6577 DstTy.getSimpleVT() >= MVT::i16 &&
6578 "Unknown FP_TO_SINT to lower!");
6580 // These are really Legal.
6581 if (DstTy == MVT::i32 &&
6582 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6583 return std::make_pair(SDValue(), SDValue());
6584 if (Subtarget->is64Bit() &&
6585 DstTy == MVT::i64 &&
6586 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6587 return std::make_pair(SDValue(), SDValue());
6589 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6591 MachineFunction &MF = DAG.getMachineFunction();
6592 unsigned MemSize = DstTy.getSizeInBits()/8;
6593 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6594 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6599 switch (DstTy.getSimpleVT().SimpleTy) {
6600 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6601 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6602 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6603 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6606 SDValue Chain = DAG.getEntryNode();
6607 SDValue Value = Op.getOperand(0);
6608 EVT TheVT = Op.getOperand(0).getValueType();
6609 if (isScalarFPTypeInSSEReg(TheVT)) {
6610 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6611 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
6612 MachinePointerInfo::getFixedStack(SSFI),
6614 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6616 Chain, StackSlot, DAG.getValueType(TheVT)
6619 MachineMemOperand *MMO =
6620 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6621 MachineMemOperand::MOLoad, MemSize, MemSize);
6622 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
6624 Chain = Value.getValue(1);
6625 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6626 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6629 MachineMemOperand *MMO =
6630 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6631 MachineMemOperand::MOStore, MemSize, MemSize);
6633 // Build the FP_TO_INT*_IN_MEM
6634 SDValue Ops[] = { Chain, Value, StackSlot };
6635 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
6636 Ops, 3, DstTy, MMO);
6638 return std::make_pair(FIST, StackSlot);
6641 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6642 SelectionDAG &DAG) const {
6643 if (Op.getValueType().isVector())
6646 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6647 SDValue FIST = Vals.first, StackSlot = Vals.second;
6648 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6649 if (FIST.getNode() == 0) return Op;
6652 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6653 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6656 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6657 SelectionDAG &DAG) const {
6658 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6659 SDValue FIST = Vals.first, StackSlot = Vals.second;
6660 assert(FIST.getNode() && "Unexpected failure");
6663 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6664 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6667 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6668 SelectionDAG &DAG) const {
6669 LLVMContext *Context = DAG.getContext();
6670 DebugLoc dl = Op.getDebugLoc();
6671 EVT VT = Op.getValueType();
6674 EltVT = VT.getVectorElementType();
6675 std::vector<Constant*> CV;
6676 if (EltVT == MVT::f64) {
6677 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6681 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6687 Constant *C = ConstantVector::get(CV);
6688 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6689 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6690 MachinePointerInfo::getConstantPool(),
6692 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6695 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6696 LLVMContext *Context = DAG.getContext();
6697 DebugLoc dl = Op.getDebugLoc();
6698 EVT VT = Op.getValueType();
6701 EltVT = VT.getVectorElementType();
6702 std::vector<Constant*> CV;
6703 if (EltVT == MVT::f64) {
6704 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6708 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6714 Constant *C = ConstantVector::get(CV);
6715 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6716 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6717 MachinePointerInfo::getConstantPool(),
6719 if (VT.isVector()) {
6720 return DAG.getNode(ISD::BITCAST, dl, VT,
6721 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6722 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6724 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
6726 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6730 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6731 LLVMContext *Context = DAG.getContext();
6732 SDValue Op0 = Op.getOperand(0);
6733 SDValue Op1 = Op.getOperand(1);
6734 DebugLoc dl = Op.getDebugLoc();
6735 EVT VT = Op.getValueType();
6736 EVT SrcVT = Op1.getValueType();
6738 // If second operand is smaller, extend it first.
6739 if (SrcVT.bitsLT(VT)) {
6740 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6743 // And if it is bigger, shrink it first.
6744 if (SrcVT.bitsGT(VT)) {
6745 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6749 // At this point the operands and the result should have the same
6750 // type, and that won't be f80 since that is not custom lowered.
6752 // First get the sign bit of second operand.
6753 std::vector<Constant*> CV;
6754 if (SrcVT == MVT::f64) {
6755 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6756 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6758 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6759 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6760 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6761 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6763 Constant *C = ConstantVector::get(CV);
6764 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6765 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6766 MachinePointerInfo::getConstantPool(),
6768 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6770 // Shift sign bit right or left if the two operands have different types.
6771 if (SrcVT.bitsGT(VT)) {
6772 // Op0 is MVT::f32, Op1 is MVT::f64.
6773 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6774 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6775 DAG.getConstant(32, MVT::i32));
6776 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
6777 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6778 DAG.getIntPtrConstant(0));
6781 // Clear first operand sign bit.
6783 if (VT == MVT::f64) {
6784 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6785 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6787 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6788 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6789 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6790 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6792 C = ConstantVector::get(CV);
6793 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6794 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6795 MachinePointerInfo::getConstantPool(),
6797 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6799 // Or the value with the sign bit.
6800 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6803 /// Emit nodes that will be selected as "test Op0,Op0", or something
6805 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6806 SelectionDAG &DAG) const {
6807 DebugLoc dl = Op.getDebugLoc();
6809 // CF and OF aren't always set the way we want. Determine which
6810 // of these we need.
6811 bool NeedCF = false;
6812 bool NeedOF = false;
6815 case X86::COND_A: case X86::COND_AE:
6816 case X86::COND_B: case X86::COND_BE:
6819 case X86::COND_G: case X86::COND_GE:
6820 case X86::COND_L: case X86::COND_LE:
6821 case X86::COND_O: case X86::COND_NO:
6826 // See if we can use the EFLAGS value from the operand instead of
6827 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6828 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6829 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6830 // Emit a CMP with 0, which is the TEST pattern.
6831 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6832 DAG.getConstant(0, Op.getValueType()));
6834 unsigned Opcode = 0;
6835 unsigned NumOperands = 0;
6836 switch (Op.getNode()->getOpcode()) {
6838 // Due to an isel shortcoming, be conservative if this add is likely to be
6839 // selected as part of a load-modify-store instruction. When the root node
6840 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6841 // uses of other nodes in the match, such as the ADD in this case. This
6842 // leads to the ADD being left around and reselected, with the result being
6843 // two adds in the output. Alas, even if none our users are stores, that
6844 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6845 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6846 // climbing the DAG back to the root, and it doesn't seem to be worth the
6848 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6849 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6850 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6853 if (ConstantSDNode *C =
6854 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6855 // An add of one will be selected as an INC.
6856 if (C->getAPIntValue() == 1) {
6857 Opcode = X86ISD::INC;
6862 // An add of negative one (subtract of one) will be selected as a DEC.
6863 if (C->getAPIntValue().isAllOnesValue()) {
6864 Opcode = X86ISD::DEC;
6870 // Otherwise use a regular EFLAGS-setting add.
6871 Opcode = X86ISD::ADD;
6875 // If the primary and result isn't used, don't bother using X86ISD::AND,
6876 // because a TEST instruction will be better.
6877 bool NonFlagUse = false;
6878 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6879 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6881 unsigned UOpNo = UI.getOperandNo();
6882 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6883 // Look pass truncate.
6884 UOpNo = User->use_begin().getOperandNo();
6885 User = *User->use_begin();
6888 if (User->getOpcode() != ISD::BRCOND &&
6889 User->getOpcode() != ISD::SETCC &&
6890 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6903 // Due to the ISEL shortcoming noted above, be conservative if this op is
6904 // likely to be selected as part of a load-modify-store instruction.
6905 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6906 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6907 if (UI->getOpcode() == ISD::STORE)
6910 // Otherwise use a regular EFLAGS-setting instruction.
6911 switch (Op.getNode()->getOpcode()) {
6912 default: llvm_unreachable("unexpected operator!");
6913 case ISD::SUB: Opcode = X86ISD::SUB; break;
6914 case ISD::OR: Opcode = X86ISD::OR; break;
6915 case ISD::XOR: Opcode = X86ISD::XOR; break;
6916 case ISD::AND: Opcode = X86ISD::AND; break;
6928 return SDValue(Op.getNode(), 1);
6935 // Emit a CMP with 0, which is the TEST pattern.
6936 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6937 DAG.getConstant(0, Op.getValueType()));
6939 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6940 SmallVector<SDValue, 4> Ops;
6941 for (unsigned i = 0; i != NumOperands; ++i)
6942 Ops.push_back(Op.getOperand(i));
6944 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6945 DAG.ReplaceAllUsesWith(Op, New);
6946 return SDValue(New.getNode(), 1);
6949 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6951 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6952 SelectionDAG &DAG) const {
6953 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6954 if (C->getAPIntValue() == 0)
6955 return EmitTest(Op0, X86CC, DAG);
6957 DebugLoc dl = Op0.getDebugLoc();
6958 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6961 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6962 /// if it's possible.
6963 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6964 DebugLoc dl, SelectionDAG &DAG) const {
6965 SDValue Op0 = And.getOperand(0);
6966 SDValue Op1 = And.getOperand(1);
6967 if (Op0.getOpcode() == ISD::TRUNCATE)
6968 Op0 = Op0.getOperand(0);
6969 if (Op1.getOpcode() == ISD::TRUNCATE)
6970 Op1 = Op1.getOperand(0);
6973 if (Op1.getOpcode() == ISD::SHL)
6974 std::swap(Op0, Op1);
6975 if (Op0.getOpcode() == ISD::SHL) {
6976 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6977 if (And00C->getZExtValue() == 1) {
6978 // If we looked past a truncate, check that it's only truncating away
6980 unsigned BitWidth = Op0.getValueSizeInBits();
6981 unsigned AndBitWidth = And.getValueSizeInBits();
6982 if (BitWidth > AndBitWidth) {
6983 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6984 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6985 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6989 RHS = Op0.getOperand(1);
6991 } else if (Op1.getOpcode() == ISD::Constant) {
6992 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6993 SDValue AndLHS = Op0;
6994 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6995 LHS = AndLHS.getOperand(0);
6996 RHS = AndLHS.getOperand(1);
7000 if (LHS.getNode()) {
7001 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
7002 // instruction. Since the shift amount is in-range-or-undefined, we know
7003 // that doing a bittest on the i32 value is ok. We extend to i32 because
7004 // the encoding for the i16 version is larger than the i32 version.
7005 // Also promote i16 to i32 for performance / code size reason.
7006 if (LHS.getValueType() == MVT::i8 ||
7007 LHS.getValueType() == MVT::i16)
7008 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7010 // If the operand types disagree, extend the shift amount to match. Since
7011 // BT ignores high bits (like shifts) we can use anyextend.
7012 if (LHS.getValueType() != RHS.getValueType())
7013 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7015 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7016 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7017 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7018 DAG.getConstant(Cond, MVT::i8), BT);
7024 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7025 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7026 SDValue Op0 = Op.getOperand(0);
7027 SDValue Op1 = Op.getOperand(1);
7028 DebugLoc dl = Op.getDebugLoc();
7029 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7031 // Optimize to BT if possible.
7032 // Lower (X & (1 << N)) == 0 to BT(X, N).
7033 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7034 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7035 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
7036 Op1.getOpcode() == ISD::Constant &&
7037 cast<ConstantSDNode>(Op1)->isNullValue() &&
7038 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7039 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7040 if (NewSetCC.getNode())
7044 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
7046 if (Op1.getOpcode() == ISD::Constant &&
7047 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7048 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7049 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7051 // If the input is a setcc, then reuse the input setcc or use a new one with
7052 // the inverted condition.
7053 if (Op0.getOpcode() == X86ISD::SETCC) {
7054 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7055 bool Invert = (CC == ISD::SETNE) ^
7056 cast<ConstantSDNode>(Op1)->isNullValue();
7057 if (!Invert) return Op0;
7059 CCode = X86::GetOppositeBranchCondition(CCode);
7060 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7061 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7065 bool isFP = Op1.getValueType().isFloatingPoint();
7066 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7067 if (X86CC == X86::COND_INVALID)
7070 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
7071 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7072 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
7075 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7077 SDValue Op0 = Op.getOperand(0);
7078 SDValue Op1 = Op.getOperand(1);
7079 SDValue CC = Op.getOperand(2);
7080 EVT VT = Op.getValueType();
7081 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7082 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7083 DebugLoc dl = Op.getDebugLoc();
7087 EVT VT0 = Op0.getValueType();
7088 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7089 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7092 switch (SetCCOpcode) {
7095 case ISD::SETEQ: SSECC = 0; break;
7097 case ISD::SETGT: Swap = true; // Fallthrough
7099 case ISD::SETOLT: SSECC = 1; break;
7101 case ISD::SETGE: Swap = true; // Fallthrough
7103 case ISD::SETOLE: SSECC = 2; break;
7104 case ISD::SETUO: SSECC = 3; break;
7106 case ISD::SETNE: SSECC = 4; break;
7107 case ISD::SETULE: Swap = true;
7108 case ISD::SETUGE: SSECC = 5; break;
7109 case ISD::SETULT: Swap = true;
7110 case ISD::SETUGT: SSECC = 6; break;
7111 case ISD::SETO: SSECC = 7; break;
7114 std::swap(Op0, Op1);
7116 // In the two special cases we can't handle, emit two comparisons.
7118 if (SetCCOpcode == ISD::SETUEQ) {
7120 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7121 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7122 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7124 else if (SetCCOpcode == ISD::SETONE) {
7126 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7127 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7128 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7130 llvm_unreachable("Illegal FP comparison");
7132 // Handle all other FP comparisons here.
7133 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7136 // We are handling one of the integer comparisons here. Since SSE only has
7137 // GT and EQ comparisons for integer, swapping operands and multiple
7138 // operations may be required for some comparisons.
7139 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7140 bool Swap = false, Invert = false, FlipSigns = false;
7142 switch (VT.getSimpleVT().SimpleTy) {
7144 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7145 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7146 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7147 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7150 switch (SetCCOpcode) {
7152 case ISD::SETNE: Invert = true;
7153 case ISD::SETEQ: Opc = EQOpc; break;
7154 case ISD::SETLT: Swap = true;
7155 case ISD::SETGT: Opc = GTOpc; break;
7156 case ISD::SETGE: Swap = true;
7157 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7158 case ISD::SETULT: Swap = true;
7159 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7160 case ISD::SETUGE: Swap = true;
7161 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7164 std::swap(Op0, Op1);
7166 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7167 // bits of the inputs before performing those operations.
7169 EVT EltVT = VT.getVectorElementType();
7170 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7172 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7173 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7175 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7176 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7179 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7181 // If the logical-not of the result is required, perform that now.
7183 Result = DAG.getNOT(dl, Result, VT);
7188 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7189 static bool isX86LogicalCmp(SDValue Op) {
7190 unsigned Opc = Op.getNode()->getOpcode();
7191 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7193 if (Op.getResNo() == 1 &&
7194 (Opc == X86ISD::ADD ||
7195 Opc == X86ISD::SUB ||
7196 Opc == X86ISD::ADC ||
7197 Opc == X86ISD::SBB ||
7198 Opc == X86ISD::SMUL ||
7199 Opc == X86ISD::UMUL ||
7200 Opc == X86ISD::INC ||
7201 Opc == X86ISD::DEC ||
7202 Opc == X86ISD::OR ||
7203 Opc == X86ISD::XOR ||
7204 Opc == X86ISD::AND))
7207 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
7213 static bool isZero(SDValue V) {
7214 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7215 return C && C->isNullValue();
7218 static bool isAllOnes(SDValue V) {
7219 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7220 return C && C->isAllOnesValue();
7223 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7224 bool addTest = true;
7225 SDValue Cond = Op.getOperand(0);
7226 SDValue Op1 = Op.getOperand(1);
7227 SDValue Op2 = Op.getOperand(2);
7228 DebugLoc DL = Op.getDebugLoc();
7231 if (Cond.getOpcode() == ISD::SETCC) {
7232 SDValue NewCond = LowerSETCC(Cond, DAG);
7233 if (NewCond.getNode())
7237 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
7238 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
7239 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
7240 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
7241 if (Cond.getOpcode() == X86ISD::SETCC &&
7242 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
7243 isZero(Cond.getOperand(1).getOperand(1))) {
7244 SDValue Cmp = Cond.getOperand(1);
7246 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
7248 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
7249 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
7250 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
7252 SDValue CmpOp0 = Cmp.getOperand(0);
7253 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
7254 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7256 SDValue Res = // Res = 0 or -1.
7257 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7258 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7260 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
7261 Res = DAG.getNOT(DL, Res, Res.getValueType());
7263 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7264 if (N2C == 0 || !N2C->isNullValue())
7265 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
7270 // Look past (and (setcc_carry (cmp ...)), 1).
7271 if (Cond.getOpcode() == ISD::AND &&
7272 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7273 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7274 if (C && C->getAPIntValue() == 1)
7275 Cond = Cond.getOperand(0);
7278 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7279 // setting operand in place of the X86ISD::SETCC.
7280 if (Cond.getOpcode() == X86ISD::SETCC ||
7281 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7282 CC = Cond.getOperand(0);
7284 SDValue Cmp = Cond.getOperand(1);
7285 unsigned Opc = Cmp.getOpcode();
7286 EVT VT = Op.getValueType();
7288 bool IllegalFPCMov = false;
7289 if (VT.isFloatingPoint() && !VT.isVector() &&
7290 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7291 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7293 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7294 Opc == X86ISD::BT) { // FIXME
7301 // Look pass the truncate.
7302 if (Cond.getOpcode() == ISD::TRUNCATE)
7303 Cond = Cond.getOperand(0);
7305 // We know the result of AND is compared against zero. Try to match
7307 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7308 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
7309 if (NewSetCC.getNode()) {
7310 CC = NewSetCC.getOperand(0);
7311 Cond = NewSetCC.getOperand(1);
7318 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7319 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7322 // a < b ? -1 : 0 -> RES = ~setcc_carry
7323 // a < b ? 0 : -1 -> RES = setcc_carry
7324 // a >= b ? -1 : 0 -> RES = setcc_carry
7325 // a >= b ? 0 : -1 -> RES = ~setcc_carry
7326 if (Cond.getOpcode() == X86ISD::CMP) {
7327 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
7329 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
7330 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
7331 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7332 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
7333 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
7334 return DAG.getNOT(DL, Res, Res.getValueType());
7339 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7340 // condition is true.
7341 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
7342 SDValue Ops[] = { Op2, Op1, CC, Cond };
7343 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
7346 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7347 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7348 // from the AND / OR.
7349 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7350 Opc = Op.getOpcode();
7351 if (Opc != ISD::OR && Opc != ISD::AND)
7353 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7354 Op.getOperand(0).hasOneUse() &&
7355 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7356 Op.getOperand(1).hasOneUse());
7359 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7360 // 1 and that the SETCC node has a single use.
7361 static bool isXor1OfSetCC(SDValue Op) {
7362 if (Op.getOpcode() != ISD::XOR)
7364 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7365 if (N1C && N1C->getAPIntValue() == 1) {
7366 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7367 Op.getOperand(0).hasOneUse();
7372 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7373 bool addTest = true;
7374 SDValue Chain = Op.getOperand(0);
7375 SDValue Cond = Op.getOperand(1);
7376 SDValue Dest = Op.getOperand(2);
7377 DebugLoc dl = Op.getDebugLoc();
7380 if (Cond.getOpcode() == ISD::SETCC) {
7381 SDValue NewCond = LowerSETCC(Cond, DAG);
7382 if (NewCond.getNode())
7386 // FIXME: LowerXALUO doesn't handle these!!
7387 else if (Cond.getOpcode() == X86ISD::ADD ||
7388 Cond.getOpcode() == X86ISD::SUB ||
7389 Cond.getOpcode() == X86ISD::SMUL ||
7390 Cond.getOpcode() == X86ISD::UMUL)
7391 Cond = LowerXALUO(Cond, DAG);
7394 // Look pass (and (setcc_carry (cmp ...)), 1).
7395 if (Cond.getOpcode() == ISD::AND &&
7396 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7397 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7398 if (C && C->getAPIntValue() == 1)
7399 Cond = Cond.getOperand(0);
7402 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7403 // setting operand in place of the X86ISD::SETCC.
7404 if (Cond.getOpcode() == X86ISD::SETCC ||
7405 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7406 CC = Cond.getOperand(0);
7408 SDValue Cmp = Cond.getOperand(1);
7409 unsigned Opc = Cmp.getOpcode();
7410 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7411 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7415 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7419 // These can only come from an arithmetic instruction with overflow,
7420 // e.g. SADDO, UADDO.
7421 Cond = Cond.getNode()->getOperand(1);
7428 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7429 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7430 if (CondOpc == ISD::OR) {
7431 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7432 // two branches instead of an explicit OR instruction with a
7434 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7435 isX86LogicalCmp(Cmp)) {
7436 CC = Cond.getOperand(0).getOperand(0);
7437 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7438 Chain, Dest, CC, Cmp);
7439 CC = Cond.getOperand(1).getOperand(0);
7443 } else { // ISD::AND
7444 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7445 // two branches instead of an explicit AND instruction with a
7446 // separate test. However, we only do this if this block doesn't
7447 // have a fall-through edge, because this requires an explicit
7448 // jmp when the condition is false.
7449 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7450 isX86LogicalCmp(Cmp) &&
7451 Op.getNode()->hasOneUse()) {
7452 X86::CondCode CCode =
7453 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7454 CCode = X86::GetOppositeBranchCondition(CCode);
7455 CC = DAG.getConstant(CCode, MVT::i8);
7456 SDNode *User = *Op.getNode()->use_begin();
7457 // Look for an unconditional branch following this conditional branch.
7458 // We need this because we need to reverse the successors in order
7459 // to implement FCMP_OEQ.
7460 if (User->getOpcode() == ISD::BR) {
7461 SDValue FalseBB = User->getOperand(1);
7463 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7464 assert(NewBR == User);
7468 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7469 Chain, Dest, CC, Cmp);
7470 X86::CondCode CCode =
7471 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7472 CCode = X86::GetOppositeBranchCondition(CCode);
7473 CC = DAG.getConstant(CCode, MVT::i8);
7479 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7480 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7481 // It should be transformed during dag combiner except when the condition
7482 // is set by a arithmetics with overflow node.
7483 X86::CondCode CCode =
7484 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7485 CCode = X86::GetOppositeBranchCondition(CCode);
7486 CC = DAG.getConstant(CCode, MVT::i8);
7487 Cond = Cond.getOperand(0).getOperand(1);
7493 // Look pass the truncate.
7494 if (Cond.getOpcode() == ISD::TRUNCATE)
7495 Cond = Cond.getOperand(0);
7497 // We know the result of AND is compared against zero. Try to match
7499 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7500 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7501 if (NewSetCC.getNode()) {
7502 CC = NewSetCC.getOperand(0);
7503 Cond = NewSetCC.getOperand(1);
7510 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7511 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7513 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7514 Chain, Dest, CC, Cond);
7518 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7519 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7520 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7521 // that the guard pages used by the OS virtual memory manager are allocated in
7522 // correct sequence.
7524 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7525 SelectionDAG &DAG) const {
7526 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
7527 "This should be used only on Windows targets");
7528 DebugLoc dl = Op.getDebugLoc();
7531 SDValue Chain = Op.getOperand(0);
7532 SDValue Size = Op.getOperand(1);
7533 // FIXME: Ensure alignment here
7537 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7539 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7540 Flag = Chain.getValue(1);
7542 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7544 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
7545 Flag = Chain.getValue(1);
7547 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7549 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7550 return DAG.getMergeValues(Ops1, 2, dl);
7553 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7554 MachineFunction &MF = DAG.getMachineFunction();
7555 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7557 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7558 DebugLoc DL = Op.getDebugLoc();
7560 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
7561 // vastart just stores the address of the VarArgsFrameIndex slot into the
7562 // memory location argument.
7563 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7565 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7566 MachinePointerInfo(SV), false, false, 0);
7570 // gp_offset (0 - 6 * 8)
7571 // fp_offset (48 - 48 + 8 * 16)
7572 // overflow_arg_area (point to parameters coming in memory).
7574 SmallVector<SDValue, 8> MemOps;
7575 SDValue FIN = Op.getOperand(1);
7577 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
7578 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7580 FIN, MachinePointerInfo(SV), false, false, 0);
7581 MemOps.push_back(Store);
7584 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7585 FIN, DAG.getIntPtrConstant(4));
7586 Store = DAG.getStore(Op.getOperand(0), DL,
7587 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7589 FIN, MachinePointerInfo(SV, 4), false, false, 0);
7590 MemOps.push_back(Store);
7592 // Store ptr to overflow_arg_area
7593 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7594 FIN, DAG.getIntPtrConstant(4));
7595 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7597 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
7598 MachinePointerInfo(SV, 8),
7600 MemOps.push_back(Store);
7602 // Store ptr to reg_save_area.
7603 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7604 FIN, DAG.getIntPtrConstant(8));
7605 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7607 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
7608 MachinePointerInfo(SV, 16), false, false, 0);
7609 MemOps.push_back(Store);
7610 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
7611 &MemOps[0], MemOps.size());
7614 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7615 assert(Subtarget->is64Bit() &&
7616 "LowerVAARG only handles 64-bit va_arg!");
7617 assert((Subtarget->isTargetLinux() ||
7618 Subtarget->isTargetDarwin()) &&
7619 "Unhandled target in LowerVAARG");
7620 assert(Op.getNode()->getNumOperands() == 4);
7621 SDValue Chain = Op.getOperand(0);
7622 SDValue SrcPtr = Op.getOperand(1);
7623 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7624 unsigned Align = Op.getConstantOperandVal(3);
7625 DebugLoc dl = Op.getDebugLoc();
7627 EVT ArgVT = Op.getNode()->getValueType(0);
7628 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
7629 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
7632 // Decide which area this value should be read from.
7633 // TODO: Implement the AMD64 ABI in its entirety. This simple
7634 // selection mechanism works only for the basic types.
7635 if (ArgVT == MVT::f80) {
7636 llvm_unreachable("va_arg for f80 not yet implemented");
7637 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
7638 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
7639 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
7640 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
7642 llvm_unreachable("Unhandled argument type in LowerVAARG");
7646 // Sanity Check: Make sure using fp_offset makes sense.
7647 assert(!UseSoftFloat &&
7648 !(DAG.getMachineFunction()
7649 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
7650 Subtarget->hasXMM());
7653 // Insert VAARG_64 node into the DAG
7654 // VAARG_64 returns two values: Variable Argument Address, Chain
7655 SmallVector<SDValue, 11> InstOps;
7656 InstOps.push_back(Chain);
7657 InstOps.push_back(SrcPtr);
7658 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
7659 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
7660 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
7661 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
7662 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
7663 VTs, &InstOps[0], InstOps.size(),
7665 MachinePointerInfo(SV),
7670 Chain = VAARG.getValue(1);
7672 // Load the next argument and return it
7673 return DAG.getLoad(ArgVT, dl,
7676 MachinePointerInfo(),
7680 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7681 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7682 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7683 SDValue Chain = Op.getOperand(0);
7684 SDValue DstPtr = Op.getOperand(1);
7685 SDValue SrcPtr = Op.getOperand(2);
7686 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7687 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7688 DebugLoc DL = Op.getDebugLoc();
7690 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
7691 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7693 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
7697 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7698 DebugLoc dl = Op.getDebugLoc();
7699 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7701 default: return SDValue(); // Don't custom lower most intrinsics.
7702 // Comparison intrinsics.
7703 case Intrinsic::x86_sse_comieq_ss:
7704 case Intrinsic::x86_sse_comilt_ss:
7705 case Intrinsic::x86_sse_comile_ss:
7706 case Intrinsic::x86_sse_comigt_ss:
7707 case Intrinsic::x86_sse_comige_ss:
7708 case Intrinsic::x86_sse_comineq_ss:
7709 case Intrinsic::x86_sse_ucomieq_ss:
7710 case Intrinsic::x86_sse_ucomilt_ss:
7711 case Intrinsic::x86_sse_ucomile_ss:
7712 case Intrinsic::x86_sse_ucomigt_ss:
7713 case Intrinsic::x86_sse_ucomige_ss:
7714 case Intrinsic::x86_sse_ucomineq_ss:
7715 case Intrinsic::x86_sse2_comieq_sd:
7716 case Intrinsic::x86_sse2_comilt_sd:
7717 case Intrinsic::x86_sse2_comile_sd:
7718 case Intrinsic::x86_sse2_comigt_sd:
7719 case Intrinsic::x86_sse2_comige_sd:
7720 case Intrinsic::x86_sse2_comineq_sd:
7721 case Intrinsic::x86_sse2_ucomieq_sd:
7722 case Intrinsic::x86_sse2_ucomilt_sd:
7723 case Intrinsic::x86_sse2_ucomile_sd:
7724 case Intrinsic::x86_sse2_ucomigt_sd:
7725 case Intrinsic::x86_sse2_ucomige_sd:
7726 case Intrinsic::x86_sse2_ucomineq_sd: {
7728 ISD::CondCode CC = ISD::SETCC_INVALID;
7731 case Intrinsic::x86_sse_comieq_ss:
7732 case Intrinsic::x86_sse2_comieq_sd:
7736 case Intrinsic::x86_sse_comilt_ss:
7737 case Intrinsic::x86_sse2_comilt_sd:
7741 case Intrinsic::x86_sse_comile_ss:
7742 case Intrinsic::x86_sse2_comile_sd:
7746 case Intrinsic::x86_sse_comigt_ss:
7747 case Intrinsic::x86_sse2_comigt_sd:
7751 case Intrinsic::x86_sse_comige_ss:
7752 case Intrinsic::x86_sse2_comige_sd:
7756 case Intrinsic::x86_sse_comineq_ss:
7757 case Intrinsic::x86_sse2_comineq_sd:
7761 case Intrinsic::x86_sse_ucomieq_ss:
7762 case Intrinsic::x86_sse2_ucomieq_sd:
7763 Opc = X86ISD::UCOMI;
7766 case Intrinsic::x86_sse_ucomilt_ss:
7767 case Intrinsic::x86_sse2_ucomilt_sd:
7768 Opc = X86ISD::UCOMI;
7771 case Intrinsic::x86_sse_ucomile_ss:
7772 case Intrinsic::x86_sse2_ucomile_sd:
7773 Opc = X86ISD::UCOMI;
7776 case Intrinsic::x86_sse_ucomigt_ss:
7777 case Intrinsic::x86_sse2_ucomigt_sd:
7778 Opc = X86ISD::UCOMI;
7781 case Intrinsic::x86_sse_ucomige_ss:
7782 case Intrinsic::x86_sse2_ucomige_sd:
7783 Opc = X86ISD::UCOMI;
7786 case Intrinsic::x86_sse_ucomineq_ss:
7787 case Intrinsic::x86_sse2_ucomineq_sd:
7788 Opc = X86ISD::UCOMI;
7793 SDValue LHS = Op.getOperand(1);
7794 SDValue RHS = Op.getOperand(2);
7795 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7796 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7797 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7798 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7799 DAG.getConstant(X86CC, MVT::i8), Cond);
7800 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7802 // ptest and testp intrinsics. The intrinsic these come from are designed to
7803 // return an integer value, not just an instruction so lower it to the ptest
7804 // or testp pattern and a setcc for the result.
7805 case Intrinsic::x86_sse41_ptestz:
7806 case Intrinsic::x86_sse41_ptestc:
7807 case Intrinsic::x86_sse41_ptestnzc:
7808 case Intrinsic::x86_avx_ptestz_256:
7809 case Intrinsic::x86_avx_ptestc_256:
7810 case Intrinsic::x86_avx_ptestnzc_256:
7811 case Intrinsic::x86_avx_vtestz_ps:
7812 case Intrinsic::x86_avx_vtestc_ps:
7813 case Intrinsic::x86_avx_vtestnzc_ps:
7814 case Intrinsic::x86_avx_vtestz_pd:
7815 case Intrinsic::x86_avx_vtestc_pd:
7816 case Intrinsic::x86_avx_vtestnzc_pd:
7817 case Intrinsic::x86_avx_vtestz_ps_256:
7818 case Intrinsic::x86_avx_vtestc_ps_256:
7819 case Intrinsic::x86_avx_vtestnzc_ps_256:
7820 case Intrinsic::x86_avx_vtestz_pd_256:
7821 case Intrinsic::x86_avx_vtestc_pd_256:
7822 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7823 bool IsTestPacked = false;
7826 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7827 case Intrinsic::x86_avx_vtestz_ps:
7828 case Intrinsic::x86_avx_vtestz_pd:
7829 case Intrinsic::x86_avx_vtestz_ps_256:
7830 case Intrinsic::x86_avx_vtestz_pd_256:
7831 IsTestPacked = true; // Fallthrough
7832 case Intrinsic::x86_sse41_ptestz:
7833 case Intrinsic::x86_avx_ptestz_256:
7835 X86CC = X86::COND_E;
7837 case Intrinsic::x86_avx_vtestc_ps:
7838 case Intrinsic::x86_avx_vtestc_pd:
7839 case Intrinsic::x86_avx_vtestc_ps_256:
7840 case Intrinsic::x86_avx_vtestc_pd_256:
7841 IsTestPacked = true; // Fallthrough
7842 case Intrinsic::x86_sse41_ptestc:
7843 case Intrinsic::x86_avx_ptestc_256:
7845 X86CC = X86::COND_B;
7847 case Intrinsic::x86_avx_vtestnzc_ps:
7848 case Intrinsic::x86_avx_vtestnzc_pd:
7849 case Intrinsic::x86_avx_vtestnzc_ps_256:
7850 case Intrinsic::x86_avx_vtestnzc_pd_256:
7851 IsTestPacked = true; // Fallthrough
7852 case Intrinsic::x86_sse41_ptestnzc:
7853 case Intrinsic::x86_avx_ptestnzc_256:
7855 X86CC = X86::COND_A;
7859 SDValue LHS = Op.getOperand(1);
7860 SDValue RHS = Op.getOperand(2);
7861 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7862 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7863 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7864 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7865 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7868 // Fix vector shift instructions where the last operand is a non-immediate
7870 case Intrinsic::x86_sse2_pslli_w:
7871 case Intrinsic::x86_sse2_pslli_d:
7872 case Intrinsic::x86_sse2_pslli_q:
7873 case Intrinsic::x86_sse2_psrli_w:
7874 case Intrinsic::x86_sse2_psrli_d:
7875 case Intrinsic::x86_sse2_psrli_q:
7876 case Intrinsic::x86_sse2_psrai_w:
7877 case Intrinsic::x86_sse2_psrai_d:
7878 case Intrinsic::x86_mmx_pslli_w:
7879 case Intrinsic::x86_mmx_pslli_d:
7880 case Intrinsic::x86_mmx_pslli_q:
7881 case Intrinsic::x86_mmx_psrli_w:
7882 case Intrinsic::x86_mmx_psrli_d:
7883 case Intrinsic::x86_mmx_psrli_q:
7884 case Intrinsic::x86_mmx_psrai_w:
7885 case Intrinsic::x86_mmx_psrai_d: {
7886 SDValue ShAmt = Op.getOperand(2);
7887 if (isa<ConstantSDNode>(ShAmt))
7890 unsigned NewIntNo = 0;
7891 EVT ShAmtVT = MVT::v4i32;
7893 case Intrinsic::x86_sse2_pslli_w:
7894 NewIntNo = Intrinsic::x86_sse2_psll_w;
7896 case Intrinsic::x86_sse2_pslli_d:
7897 NewIntNo = Intrinsic::x86_sse2_psll_d;
7899 case Intrinsic::x86_sse2_pslli_q:
7900 NewIntNo = Intrinsic::x86_sse2_psll_q;
7902 case Intrinsic::x86_sse2_psrli_w:
7903 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7905 case Intrinsic::x86_sse2_psrli_d:
7906 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7908 case Intrinsic::x86_sse2_psrli_q:
7909 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7911 case Intrinsic::x86_sse2_psrai_w:
7912 NewIntNo = Intrinsic::x86_sse2_psra_w;
7914 case Intrinsic::x86_sse2_psrai_d:
7915 NewIntNo = Intrinsic::x86_sse2_psra_d;
7918 ShAmtVT = MVT::v2i32;
7920 case Intrinsic::x86_mmx_pslli_w:
7921 NewIntNo = Intrinsic::x86_mmx_psll_w;
7923 case Intrinsic::x86_mmx_pslli_d:
7924 NewIntNo = Intrinsic::x86_mmx_psll_d;
7926 case Intrinsic::x86_mmx_pslli_q:
7927 NewIntNo = Intrinsic::x86_mmx_psll_q;
7929 case Intrinsic::x86_mmx_psrli_w:
7930 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7932 case Intrinsic::x86_mmx_psrli_d:
7933 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7935 case Intrinsic::x86_mmx_psrli_q:
7936 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7938 case Intrinsic::x86_mmx_psrai_w:
7939 NewIntNo = Intrinsic::x86_mmx_psra_w;
7941 case Intrinsic::x86_mmx_psrai_d:
7942 NewIntNo = Intrinsic::x86_mmx_psra_d;
7944 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7950 // The vector shift intrinsics with scalars uses 32b shift amounts but
7951 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7955 ShOps[1] = DAG.getConstant(0, MVT::i32);
7956 if (ShAmtVT == MVT::v4i32) {
7957 ShOps[2] = DAG.getUNDEF(MVT::i32);
7958 ShOps[3] = DAG.getUNDEF(MVT::i32);
7959 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7961 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7962 // FIXME this must be lowered to get rid of the invalid type.
7965 EVT VT = Op.getValueType();
7966 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
7967 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7968 DAG.getConstant(NewIntNo, MVT::i32),
7969 Op.getOperand(1), ShAmt);
7974 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7975 SelectionDAG &DAG) const {
7976 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7977 MFI->setReturnAddressIsTaken(true);
7979 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7980 DebugLoc dl = Op.getDebugLoc();
7983 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7985 DAG.getConstant(TD->getPointerSize(),
7986 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7987 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7988 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7990 MachinePointerInfo(), false, false, 0);
7993 // Just load the return address.
7994 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7995 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7996 RetAddrFI, MachinePointerInfo(), false, false, 0);
7999 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
8000 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8001 MFI->setFrameAddressIsTaken(true);
8003 EVT VT = Op.getValueType();
8004 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
8005 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8006 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
8007 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
8009 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
8010 MachinePointerInfo(),
8015 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
8016 SelectionDAG &DAG) const {
8017 return DAG.getIntPtrConstant(2*TD->getPointerSize());
8020 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
8021 MachineFunction &MF = DAG.getMachineFunction();
8022 SDValue Chain = Op.getOperand(0);
8023 SDValue Offset = Op.getOperand(1);
8024 SDValue Handler = Op.getOperand(2);
8025 DebugLoc dl = Op.getDebugLoc();
8027 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
8028 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
8030 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
8032 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
8033 DAG.getIntPtrConstant(TD->getPointerSize()));
8034 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
8035 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
8037 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
8038 MF.getRegInfo().addLiveOut(StoreAddrReg);
8040 return DAG.getNode(X86ISD::EH_RETURN, dl,
8042 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
8045 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
8046 SelectionDAG &DAG) const {
8047 SDValue Root = Op.getOperand(0);
8048 SDValue Trmp = Op.getOperand(1); // trampoline
8049 SDValue FPtr = Op.getOperand(2); // nested function
8050 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
8051 DebugLoc dl = Op.getDebugLoc();
8053 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8055 if (Subtarget->is64Bit()) {
8056 SDValue OutChains[6];
8058 // Large code-model.
8059 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
8060 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
8062 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
8063 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
8065 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
8067 // Load the pointer to the nested function into R11.
8068 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
8069 SDValue Addr = Trmp;
8070 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8071 Addr, MachinePointerInfo(TrmpAddr),
8074 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8075 DAG.getConstant(2, MVT::i64));
8076 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8077 MachinePointerInfo(TrmpAddr, 2),
8080 // Load the 'nest' parameter value into R10.
8081 // R10 is specified in X86CallingConv.td
8082 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8083 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8084 DAG.getConstant(10, MVT::i64));
8085 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8086 Addr, MachinePointerInfo(TrmpAddr, 10),
8089 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8090 DAG.getConstant(12, MVT::i64));
8091 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8092 MachinePointerInfo(TrmpAddr, 12),
8095 // Jump to the nested function.
8096 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8097 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8098 DAG.getConstant(20, MVT::i64));
8099 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8100 Addr, MachinePointerInfo(TrmpAddr, 20),
8103 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8104 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8105 DAG.getConstant(22, MVT::i64));
8106 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8107 MachinePointerInfo(TrmpAddr, 22),
8111 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8112 return DAG.getMergeValues(Ops, 2, dl);
8114 const Function *Func =
8115 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8116 CallingConv::ID CC = Func->getCallingConv();
8121 llvm_unreachable("Unsupported calling convention");
8122 case CallingConv::C:
8123 case CallingConv::X86_StdCall: {
8124 // Pass 'nest' parameter in ECX.
8125 // Must be kept in sync with X86CallingConv.td
8128 // Check that ECX wasn't needed by an 'inreg' parameter.
8129 const FunctionType *FTy = Func->getFunctionType();
8130 const AttrListPtr &Attrs = Func->getAttributes();
8132 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8133 unsigned InRegCount = 0;
8136 for (FunctionType::param_iterator I = FTy->param_begin(),
8137 E = FTy->param_end(); I != E; ++I, ++Idx)
8138 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8139 // FIXME: should only count parameters that are lowered to integers.
8140 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8142 if (InRegCount > 2) {
8143 report_fatal_error("Nest register in use - reduce number of inreg"
8149 case CallingConv::X86_FastCall:
8150 case CallingConv::X86_ThisCall:
8151 case CallingConv::Fast:
8152 // Pass 'nest' parameter in EAX.
8153 // Must be kept in sync with X86CallingConv.td
8158 SDValue OutChains[4];
8161 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8162 DAG.getConstant(10, MVT::i32));
8163 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8165 // This is storing the opcode for MOV32ri.
8166 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8167 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8168 OutChains[0] = DAG.getStore(Root, dl,
8169 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8170 Trmp, MachinePointerInfo(TrmpAddr),
8173 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8174 DAG.getConstant(1, MVT::i32));
8175 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8176 MachinePointerInfo(TrmpAddr, 1),
8179 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8180 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8181 DAG.getConstant(5, MVT::i32));
8182 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8183 MachinePointerInfo(TrmpAddr, 5),
8186 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8187 DAG.getConstant(6, MVT::i32));
8188 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8189 MachinePointerInfo(TrmpAddr, 6),
8193 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8194 return DAG.getMergeValues(Ops, 2, dl);
8198 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8199 SelectionDAG &DAG) const {
8201 The rounding mode is in bits 11:10 of FPSR, and has the following
8208 FLT_ROUNDS, on the other hand, expects the following:
8215 To perform the conversion, we do:
8216 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8219 MachineFunction &MF = DAG.getMachineFunction();
8220 const TargetMachine &TM = MF.getTarget();
8221 const TargetFrameLowering &TFI = *TM.getFrameLowering();
8222 unsigned StackAlignment = TFI.getStackAlignment();
8223 EVT VT = Op.getValueType();
8224 DebugLoc DL = Op.getDebugLoc();
8226 // Save FP Control Word to stack slot
8227 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8228 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8231 MachineMemOperand *MMO =
8232 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8233 MachineMemOperand::MOStore, 2, 2);
8235 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
8236 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
8237 DAG.getVTList(MVT::Other),
8238 Ops, 2, MVT::i16, MMO);
8240 // Load FP Control Word from stack slot
8241 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
8242 MachinePointerInfo(), false, false, 0);
8244 // Transform as necessary
8246 DAG.getNode(ISD::SRL, DL, MVT::i16,
8247 DAG.getNode(ISD::AND, DL, MVT::i16,
8248 CWD, DAG.getConstant(0x800, MVT::i16)),
8249 DAG.getConstant(11, MVT::i8));
8251 DAG.getNode(ISD::SRL, DL, MVT::i16,
8252 DAG.getNode(ISD::AND, DL, MVT::i16,
8253 CWD, DAG.getConstant(0x400, MVT::i16)),
8254 DAG.getConstant(9, MVT::i8));
8257 DAG.getNode(ISD::AND, DL, MVT::i16,
8258 DAG.getNode(ISD::ADD, DL, MVT::i16,
8259 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
8260 DAG.getConstant(1, MVT::i16)),
8261 DAG.getConstant(3, MVT::i16));
8264 return DAG.getNode((VT.getSizeInBits() < 16 ?
8265 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
8268 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8269 EVT VT = Op.getValueType();
8271 unsigned NumBits = VT.getSizeInBits();
8272 DebugLoc dl = Op.getDebugLoc();
8274 Op = Op.getOperand(0);
8275 if (VT == MVT::i8) {
8276 // Zero extend to i32 since there is not an i8 bsr.
8278 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8281 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8282 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8283 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8285 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8288 DAG.getConstant(NumBits+NumBits-1, OpVT),
8289 DAG.getConstant(X86::COND_E, MVT::i8),
8292 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8294 // Finally xor with NumBits-1.
8295 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8298 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8302 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8303 EVT VT = Op.getValueType();
8305 unsigned NumBits = VT.getSizeInBits();
8306 DebugLoc dl = Op.getDebugLoc();
8308 Op = Op.getOperand(0);
8309 if (VT == MVT::i8) {
8311 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8314 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8315 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8316 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8318 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8321 DAG.getConstant(NumBits, OpVT),
8322 DAG.getConstant(X86::COND_E, MVT::i8),
8325 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8328 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8332 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8333 EVT VT = Op.getValueType();
8334 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8335 DebugLoc dl = Op.getDebugLoc();
8337 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8338 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8339 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8340 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8341 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8343 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8344 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8345 // return AloBlo + AloBhi + AhiBlo;
8347 SDValue A = Op.getOperand(0);
8348 SDValue B = Op.getOperand(1);
8350 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8351 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8352 A, DAG.getConstant(32, MVT::i32));
8353 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8354 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8355 B, DAG.getConstant(32, MVT::i32));
8356 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8357 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8359 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8360 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8362 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8363 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8365 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8366 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8367 AloBhi, DAG.getConstant(32, MVT::i32));
8368 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8369 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8370 AhiBlo, DAG.getConstant(32, MVT::i32));
8371 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8372 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8376 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8377 EVT VT = Op.getValueType();
8378 DebugLoc dl = Op.getDebugLoc();
8379 SDValue R = Op.getOperand(0);
8381 LLVMContext *Context = DAG.getContext();
8383 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8385 if (VT == MVT::v4i32) {
8386 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8387 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8388 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8390 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8392 std::vector<Constant*> CV(4, CI);
8393 Constant *C = ConstantVector::get(CV);
8394 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8395 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8396 MachinePointerInfo::getConstantPool(),
8399 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8400 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
8401 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8402 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8404 if (VT == MVT::v16i8) {
8406 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8407 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8408 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8410 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8411 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8413 std::vector<Constant*> CVM1(16, CM1);
8414 std::vector<Constant*> CVM2(16, CM2);
8415 Constant *C = ConstantVector::get(CVM1);
8416 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8417 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8418 MachinePointerInfo::getConstantPool(),
8421 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8422 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8423 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8424 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8425 DAG.getConstant(4, MVT::i32));
8426 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8428 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8430 C = ConstantVector::get(CVM2);
8431 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8432 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8433 MachinePointerInfo::getConstantPool(),
8436 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8437 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8438 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8439 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8440 DAG.getConstant(2, MVT::i32));
8441 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8443 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8445 // return pblendv(r, r+r, a);
8446 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
8447 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8453 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8454 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8455 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8456 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8457 // has only one use.
8458 SDNode *N = Op.getNode();
8459 SDValue LHS = N->getOperand(0);
8460 SDValue RHS = N->getOperand(1);
8461 unsigned BaseOp = 0;
8463 DebugLoc DL = Op.getDebugLoc();
8464 switch (Op.getOpcode()) {
8465 default: llvm_unreachable("Unknown ovf instruction!");
8467 // A subtract of one will be selected as a INC. Note that INC doesn't
8468 // set CF, so we can't do this for UADDO.
8469 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8470 if (C->getAPIntValue() == 1) {
8471 BaseOp = X86ISD::INC;
8475 BaseOp = X86ISD::ADD;
8479 BaseOp = X86ISD::ADD;
8483 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8484 // set CF, so we can't do this for USUBO.
8485 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8486 if (C->getAPIntValue() == 1) {
8487 BaseOp = X86ISD::DEC;
8491 BaseOp = X86ISD::SUB;
8495 BaseOp = X86ISD::SUB;
8499 BaseOp = X86ISD::SMUL;
8502 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
8503 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
8505 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
8508 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8509 DAG.getConstant(X86::COND_O, MVT::i32),
8510 SDValue(Sum.getNode(), 2));
8512 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8517 // Also sets EFLAGS.
8518 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8519 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
8522 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
8523 DAG.getConstant(Cond, MVT::i32),
8524 SDValue(Sum.getNode(), 1));
8526 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8530 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8531 DebugLoc dl = Op.getDebugLoc();
8533 if (!Subtarget->hasSSE2()) {
8534 SDValue Chain = Op.getOperand(0);
8535 SDValue Zero = DAG.getConstant(0,
8536 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8538 DAG.getRegister(X86::ESP, MVT::i32), // Base
8539 DAG.getTargetConstant(1, MVT::i8), // Scale
8540 DAG.getRegister(0, MVT::i32), // Index
8541 DAG.getTargetConstant(0, MVT::i32), // Disp
8542 DAG.getRegister(0, MVT::i32), // Segment.
8547 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8548 array_lengthof(Ops));
8549 return SDValue(Res, 0);
8552 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8554 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8556 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8557 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8558 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8559 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8561 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8562 if (!Op1 && !Op2 && !Op3 && Op4)
8563 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8565 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8566 if (Op1 && !Op2 && !Op3 && !Op4)
8567 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8569 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8571 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8574 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8575 EVT T = Op.getValueType();
8576 DebugLoc DL = Op.getDebugLoc();
8579 switch(T.getSimpleVT().SimpleTy) {
8581 assert(false && "Invalid value type!");
8582 case MVT::i8: Reg = X86::AL; size = 1; break;
8583 case MVT::i16: Reg = X86::AX; size = 2; break;
8584 case MVT::i32: Reg = X86::EAX; size = 4; break;
8586 assert(Subtarget->is64Bit() && "Node not type legal!");
8587 Reg = X86::RAX; size = 8;
8590 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
8591 Op.getOperand(2), SDValue());
8592 SDValue Ops[] = { cpIn.getValue(0),
8595 DAG.getTargetConstant(size, MVT::i8),
8597 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8598 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
8599 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
8602 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
8606 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8607 SelectionDAG &DAG) const {
8608 assert(Subtarget->is64Bit() && "Result not type legalized?");
8609 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8610 SDValue TheChain = Op.getOperand(0);
8611 DebugLoc dl = Op.getDebugLoc();
8612 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8613 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8614 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8616 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8617 DAG.getConstant(32, MVT::i8));
8619 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8622 return DAG.getMergeValues(Ops, 2, dl);
8625 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
8626 SelectionDAG &DAG) const {
8627 EVT SrcVT = Op.getOperand(0).getValueType();
8628 EVT DstVT = Op.getValueType();
8629 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8630 Subtarget->hasMMX() && "Unexpected custom BITCAST");
8631 assert((DstVT == MVT::i64 ||
8632 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8633 "Unexpected custom BITCAST");
8634 // i64 <=> MMX conversions are Legal.
8635 if (SrcVT==MVT::i64 && DstVT.isVector())
8637 if (DstVT==MVT::i64 && SrcVT.isVector())
8639 // MMX <=> MMX conversions are Legal.
8640 if (SrcVT.isVector() && DstVT.isVector())
8642 // All other conversions need to be expanded.
8646 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8647 SDNode *Node = Op.getNode();
8648 DebugLoc dl = Node->getDebugLoc();
8649 EVT T = Node->getValueType(0);
8650 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8651 DAG.getConstant(0, T), Node->getOperand(2));
8652 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8653 cast<AtomicSDNode>(Node)->getMemoryVT(),
8654 Node->getOperand(0),
8655 Node->getOperand(1), negOp,
8656 cast<AtomicSDNode>(Node)->getSrcValue(),
8657 cast<AtomicSDNode>(Node)->getAlignment());
8660 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
8661 EVT VT = Op.getNode()->getValueType(0);
8663 // Let legalize expand this if it isn't a legal type yet.
8664 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8667 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
8670 bool ExtraOp = false;
8671 switch (Op.getOpcode()) {
8672 default: assert(0 && "Invalid code");
8673 case ISD::ADDC: Opc = X86ISD::ADD; break;
8674 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
8675 case ISD::SUBC: Opc = X86ISD::SUB; break;
8676 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
8680 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
8682 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
8683 Op.getOperand(1), Op.getOperand(2));
8686 /// LowerOperation - Provide custom lowering hooks for some operations.
8688 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8689 switch (Op.getOpcode()) {
8690 default: llvm_unreachable("Should not custom lower this!");
8691 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8692 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8693 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8694 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8695 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8696 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8697 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8698 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8699 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8700 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8701 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8702 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8703 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8704 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8705 case ISD::SHL_PARTS:
8706 case ISD::SRA_PARTS:
8707 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8708 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8709 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8710 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8711 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8712 case ISD::FABS: return LowerFABS(Op, DAG);
8713 case ISD::FNEG: return LowerFNEG(Op, DAG);
8714 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8715 case ISD::SETCC: return LowerSETCC(Op, DAG);
8716 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8717 case ISD::SELECT: return LowerSELECT(Op, DAG);
8718 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8719 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8720 case ISD::VASTART: return LowerVASTART(Op, DAG);
8721 case ISD::VAARG: return LowerVAARG(Op, DAG);
8722 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8723 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8724 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8725 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8726 case ISD::FRAME_TO_ARGS_OFFSET:
8727 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8728 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8729 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8730 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8731 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8732 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8733 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8734 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8735 case ISD::SHL: return LowerSHL(Op, DAG);
8741 case ISD::UMULO: return LowerXALUO(Op, DAG);
8742 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8743 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
8747 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
8751 void X86TargetLowering::
8752 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8753 SelectionDAG &DAG, unsigned NewOp) const {
8754 EVT T = Node->getValueType(0);
8755 DebugLoc dl = Node->getDebugLoc();
8756 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8758 SDValue Chain = Node->getOperand(0);
8759 SDValue In1 = Node->getOperand(1);
8760 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8761 Node->getOperand(2), DAG.getIntPtrConstant(0));
8762 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8763 Node->getOperand(2), DAG.getIntPtrConstant(1));
8764 SDValue Ops[] = { Chain, In1, In2L, In2H };
8765 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8767 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8768 cast<MemSDNode>(Node)->getMemOperand());
8769 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8770 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8771 Results.push_back(Result.getValue(2));
8774 /// ReplaceNodeResults - Replace a node with an illegal result type
8775 /// with a new node built out of custom code.
8776 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8777 SmallVectorImpl<SDValue>&Results,
8778 SelectionDAG &DAG) const {
8779 DebugLoc dl = N->getDebugLoc();
8780 switch (N->getOpcode()) {
8782 assert(false && "Do not know how to custom type legalize this operation!");
8788 // We don't want to expand or promote these.
8790 case ISD::FP_TO_SINT: {
8791 std::pair<SDValue,SDValue> Vals =
8792 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8793 SDValue FIST = Vals.first, StackSlot = Vals.second;
8794 if (FIST.getNode() != 0) {
8795 EVT VT = N->getValueType(0);
8796 // Return a load from the stack slot.
8797 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
8798 MachinePointerInfo(), false, false, 0));
8802 case ISD::READCYCLECOUNTER: {
8803 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8804 SDValue TheChain = N->getOperand(0);
8805 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8806 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8808 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8810 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8811 SDValue Ops[] = { eax, edx };
8812 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8813 Results.push_back(edx.getValue(1));
8816 case ISD::ATOMIC_CMP_SWAP: {
8817 EVT T = N->getValueType(0);
8818 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8819 SDValue cpInL, cpInH;
8820 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8821 DAG.getConstant(0, MVT::i32));
8822 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8823 DAG.getConstant(1, MVT::i32));
8824 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8825 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8827 SDValue swapInL, swapInH;
8828 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8829 DAG.getConstant(0, MVT::i32));
8830 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8831 DAG.getConstant(1, MVT::i32));
8832 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8834 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8835 swapInL.getValue(1));
8836 SDValue Ops[] = { swapInH.getValue(0),
8838 swapInH.getValue(1) };
8839 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8840 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
8841 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
8843 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8844 MVT::i32, Result.getValue(1));
8845 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8846 MVT::i32, cpOutL.getValue(2));
8847 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8848 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8849 Results.push_back(cpOutH.getValue(1));
8852 case ISD::ATOMIC_LOAD_ADD:
8853 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8855 case ISD::ATOMIC_LOAD_AND:
8856 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8858 case ISD::ATOMIC_LOAD_NAND:
8859 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8861 case ISD::ATOMIC_LOAD_OR:
8862 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8864 case ISD::ATOMIC_LOAD_SUB:
8865 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8867 case ISD::ATOMIC_LOAD_XOR:
8868 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8870 case ISD::ATOMIC_SWAP:
8871 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8876 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8878 default: return NULL;
8879 case X86ISD::BSF: return "X86ISD::BSF";
8880 case X86ISD::BSR: return "X86ISD::BSR";
8881 case X86ISD::SHLD: return "X86ISD::SHLD";
8882 case X86ISD::SHRD: return "X86ISD::SHRD";
8883 case X86ISD::FAND: return "X86ISD::FAND";
8884 case X86ISD::FOR: return "X86ISD::FOR";
8885 case X86ISD::FXOR: return "X86ISD::FXOR";
8886 case X86ISD::FSRL: return "X86ISD::FSRL";
8887 case X86ISD::FILD: return "X86ISD::FILD";
8888 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8889 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8890 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8891 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8892 case X86ISD::FLD: return "X86ISD::FLD";
8893 case X86ISD::FST: return "X86ISD::FST";
8894 case X86ISD::CALL: return "X86ISD::CALL";
8895 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8896 case X86ISD::BT: return "X86ISD::BT";
8897 case X86ISD::CMP: return "X86ISD::CMP";
8898 case X86ISD::COMI: return "X86ISD::COMI";
8899 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8900 case X86ISD::SETCC: return "X86ISD::SETCC";
8901 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8902 case X86ISD::CMOV: return "X86ISD::CMOV";
8903 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8904 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8905 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8906 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8907 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8908 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8909 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8910 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8911 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8912 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8913 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8914 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8915 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8916 case X86ISD::PANDN: return "X86ISD::PANDN";
8917 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
8918 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
8919 case X86ISD::PSIGND: return "X86ISD::PSIGND";
8920 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
8921 case X86ISD::FMAX: return "X86ISD::FMAX";
8922 case X86ISD::FMIN: return "X86ISD::FMIN";
8923 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8924 case X86ISD::FRCP: return "X86ISD::FRCP";
8925 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8926 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8927 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8928 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8929 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8930 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8931 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8932 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8933 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8934 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8935 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8936 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8937 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8938 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8939 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8940 case X86ISD::VSHL: return "X86ISD::VSHL";
8941 case X86ISD::VSRL: return "X86ISD::VSRL";
8942 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8943 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8944 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8945 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8946 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8947 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8948 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8949 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8950 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8951 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8952 case X86ISD::ADD: return "X86ISD::ADD";
8953 case X86ISD::SUB: return "X86ISD::SUB";
8954 case X86ISD::ADC: return "X86ISD::ADC";
8955 case X86ISD::SBB: return "X86ISD::SBB";
8956 case X86ISD::SMUL: return "X86ISD::SMUL";
8957 case X86ISD::UMUL: return "X86ISD::UMUL";
8958 case X86ISD::INC: return "X86ISD::INC";
8959 case X86ISD::DEC: return "X86ISD::DEC";
8960 case X86ISD::OR: return "X86ISD::OR";
8961 case X86ISD::XOR: return "X86ISD::XOR";
8962 case X86ISD::AND: return "X86ISD::AND";
8963 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8964 case X86ISD::PTEST: return "X86ISD::PTEST";
8965 case X86ISD::TESTP: return "X86ISD::TESTP";
8966 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8967 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8968 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8969 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8970 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8971 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8972 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8973 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8974 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8975 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8976 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8977 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8978 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8979 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8980 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8981 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8982 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8983 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8984 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8985 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8986 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8987 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8988 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8989 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8990 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8991 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8992 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8993 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8994 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8995 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8996 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8997 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8998 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8999 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
9000 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
9001 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
9005 // isLegalAddressingMode - Return true if the addressing mode represented
9006 // by AM is legal for this target, for a load/store of the specified type.
9007 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
9008 const Type *Ty) const {
9009 // X86 supports extremely general addressing modes.
9010 CodeModel::Model M = getTargetMachine().getCodeModel();
9011 Reloc::Model R = getTargetMachine().getRelocationModel();
9013 // X86 allows a sign-extended 32-bit immediate field as a displacement.
9014 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
9019 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
9021 // If a reference to this global requires an extra load, we can't fold it.
9022 if (isGlobalStubReference(GVFlags))
9025 // If BaseGV requires a register for the PIC base, we cannot also have a
9026 // BaseReg specified.
9027 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
9030 // If lower 4G is not available, then we must use rip-relative addressing.
9031 if ((M != CodeModel::Small || R != Reloc::Static) &&
9032 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
9042 // These scales always work.
9047 // These scales are formed with basereg+scalereg. Only accept if there is
9052 default: // Other stuff never works.
9060 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
9061 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9063 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9064 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9065 if (NumBits1 <= NumBits2)
9070 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9071 if (!VT1.isInteger() || !VT2.isInteger())
9073 unsigned NumBits1 = VT1.getSizeInBits();
9074 unsigned NumBits2 = VT2.getSizeInBits();
9075 if (NumBits1 <= NumBits2)
9080 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
9081 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9082 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
9085 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
9086 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9087 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
9090 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
9091 // i16 instructions are longer (0x66 prefix) and potentially slower.
9092 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
9095 /// isShuffleMaskLegal - Targets can use this to indicate that they only
9096 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
9097 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
9098 /// are assumed to be legal.
9100 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
9102 // Very little shuffling can be done for 64-bit vectors right now.
9103 if (VT.getSizeInBits() == 64)
9104 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
9106 // FIXME: pshufb, blends, shifts.
9107 return (VT.getVectorNumElements() == 2 ||
9108 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
9109 isMOVLMask(M, VT) ||
9110 isSHUFPMask(M, VT) ||
9111 isPSHUFDMask(M, VT) ||
9112 isPSHUFHWMask(M, VT) ||
9113 isPSHUFLWMask(M, VT) ||
9114 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
9115 isUNPCKLMask(M, VT) ||
9116 isUNPCKHMask(M, VT) ||
9117 isUNPCKL_v_undef_Mask(M, VT) ||
9118 isUNPCKH_v_undef_Mask(M, VT));
9122 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
9124 unsigned NumElts = VT.getVectorNumElements();
9125 // FIXME: This collection of masks seems suspect.
9128 if (NumElts == 4 && VT.getSizeInBits() == 128) {
9129 return (isMOVLMask(Mask, VT) ||
9130 isCommutedMOVLMask(Mask, VT, true) ||
9131 isSHUFPMask(Mask, VT) ||
9132 isCommutedSHUFPMask(Mask, VT));
9137 //===----------------------------------------------------------------------===//
9138 // X86 Scheduler Hooks
9139 //===----------------------------------------------------------------------===//
9141 // private utility function
9143 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
9144 MachineBasicBlock *MBB,
9151 TargetRegisterClass *RC,
9152 bool invSrc) const {
9153 // For the atomic bitwise operator, we generate
9156 // ld t1 = [bitinstr.addr]
9157 // op t2 = t1, [bitinstr.val]
9159 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9161 // fallthrough -->nextMBB
9162 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9163 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9164 MachineFunction::iterator MBBIter = MBB;
9167 /// First build the CFG
9168 MachineFunction *F = MBB->getParent();
9169 MachineBasicBlock *thisMBB = MBB;
9170 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9171 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9172 F->insert(MBBIter, newMBB);
9173 F->insert(MBBIter, nextMBB);
9175 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9176 nextMBB->splice(nextMBB->begin(), thisMBB,
9177 llvm::next(MachineBasicBlock::iterator(bInstr)),
9179 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9181 // Update thisMBB to fall through to newMBB
9182 thisMBB->addSuccessor(newMBB);
9184 // newMBB jumps to itself and fall through to nextMBB
9185 newMBB->addSuccessor(nextMBB);
9186 newMBB->addSuccessor(newMBB);
9188 // Insert instructions into newMBB based on incoming instruction
9189 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9190 "unexpected number of operands");
9191 DebugLoc dl = bInstr->getDebugLoc();
9192 MachineOperand& destOper = bInstr->getOperand(0);
9193 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9194 int numArgs = bInstr->getNumOperands() - 1;
9195 for (int i=0; i < numArgs; ++i)
9196 argOpers[i] = &bInstr->getOperand(i+1);
9198 // x86 address has 4 operands: base, index, scale, and displacement
9199 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9200 int valArgIndx = lastAddrIndx + 1;
9202 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9203 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
9204 for (int i=0; i <= lastAddrIndx; ++i)
9205 (*MIB).addOperand(*argOpers[i]);
9207 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
9209 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
9214 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9215 assert((argOpers[valArgIndx]->isReg() ||
9216 argOpers[valArgIndx]->isImm()) &&
9218 if (argOpers[valArgIndx]->isReg())
9219 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
9221 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
9223 (*MIB).addOperand(*argOpers[valArgIndx]);
9225 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
9228 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
9229 for (int i=0; i <= lastAddrIndx; ++i)
9230 (*MIB).addOperand(*argOpers[i]);
9232 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9233 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9234 bInstr->memoperands_end());
9236 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9240 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9242 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9246 // private utility function: 64 bit atomics on 32 bit host.
9248 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
9249 MachineBasicBlock *MBB,
9254 bool invSrc) const {
9255 // For the atomic bitwise operator, we generate
9256 // thisMBB (instructions are in pairs, except cmpxchg8b)
9257 // ld t1,t2 = [bitinstr.addr]
9259 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
9260 // op t5, t6 <- out1, out2, [bitinstr.val]
9261 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
9262 // mov ECX, EBX <- t5, t6
9263 // mov EAX, EDX <- t1, t2
9264 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
9265 // mov t3, t4 <- EAX, EDX
9267 // result in out1, out2
9268 // fallthrough -->nextMBB
9270 const TargetRegisterClass *RC = X86::GR32RegisterClass;
9271 const unsigned LoadOpc = X86::MOV32rm;
9272 const unsigned NotOpc = X86::NOT32r;
9273 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9274 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9275 MachineFunction::iterator MBBIter = MBB;
9278 /// First build the CFG
9279 MachineFunction *F = MBB->getParent();
9280 MachineBasicBlock *thisMBB = MBB;
9281 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9282 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9283 F->insert(MBBIter, newMBB);
9284 F->insert(MBBIter, nextMBB);
9286 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9287 nextMBB->splice(nextMBB->begin(), thisMBB,
9288 llvm::next(MachineBasicBlock::iterator(bInstr)),
9290 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9292 // Update thisMBB to fall through to newMBB
9293 thisMBB->addSuccessor(newMBB);
9295 // newMBB jumps to itself and fall through to nextMBB
9296 newMBB->addSuccessor(nextMBB);
9297 newMBB->addSuccessor(newMBB);
9299 DebugLoc dl = bInstr->getDebugLoc();
9300 // Insert instructions into newMBB based on incoming instruction
9301 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9302 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9303 "unexpected number of operands");
9304 MachineOperand& dest1Oper = bInstr->getOperand(0);
9305 MachineOperand& dest2Oper = bInstr->getOperand(1);
9306 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9307 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9308 argOpers[i] = &bInstr->getOperand(i+2);
9310 // We use some of the operands multiple times, so conservatively just
9311 // clear any kill flags that might be present.
9312 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9313 argOpers[i]->setIsKill(false);
9316 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9317 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9319 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9320 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9321 for (int i=0; i <= lastAddrIndx; ++i)
9322 (*MIB).addOperand(*argOpers[i]);
9323 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9324 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9325 // add 4 to displacement.
9326 for (int i=0; i <= lastAddrIndx-2; ++i)
9327 (*MIB).addOperand(*argOpers[i]);
9328 MachineOperand newOp3 = *(argOpers[3]);
9330 newOp3.setImm(newOp3.getImm()+4);
9332 newOp3.setOffset(newOp3.getOffset()+4);
9333 (*MIB).addOperand(newOp3);
9334 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9336 // t3/4 are defined later, at the bottom of the loop
9337 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9338 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9339 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9340 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9341 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9342 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9344 // The subsequent operations should be using the destination registers of
9345 //the PHI instructions.
9347 t1 = F->getRegInfo().createVirtualRegister(RC);
9348 t2 = F->getRegInfo().createVirtualRegister(RC);
9349 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9350 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9352 t1 = dest1Oper.getReg();
9353 t2 = dest2Oper.getReg();
9356 int valArgIndx = lastAddrIndx + 1;
9357 assert((argOpers[valArgIndx]->isReg() ||
9358 argOpers[valArgIndx]->isImm()) &&
9360 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9361 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9362 if (argOpers[valArgIndx]->isReg())
9363 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9365 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9366 if (regOpcL != X86::MOV32rr)
9368 (*MIB).addOperand(*argOpers[valArgIndx]);
9369 assert(argOpers[valArgIndx + 1]->isReg() ==
9370 argOpers[valArgIndx]->isReg());
9371 assert(argOpers[valArgIndx + 1]->isImm() ==
9372 argOpers[valArgIndx]->isImm());
9373 if (argOpers[valArgIndx + 1]->isReg())
9374 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9376 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9377 if (regOpcH != X86::MOV32rr)
9379 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9381 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9383 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9386 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9388 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9391 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9392 for (int i=0; i <= lastAddrIndx; ++i)
9393 (*MIB).addOperand(*argOpers[i]);
9395 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9396 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9397 bInstr->memoperands_end());
9399 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9400 MIB.addReg(X86::EAX);
9401 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9402 MIB.addReg(X86::EDX);
9405 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9407 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9411 // private utility function
9413 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9414 MachineBasicBlock *MBB,
9415 unsigned cmovOpc) const {
9416 // For the atomic min/max operator, we generate
9419 // ld t1 = [min/max.addr]
9420 // mov t2 = [min/max.val]
9422 // cmov[cond] t2 = t1
9424 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9426 // fallthrough -->nextMBB
9428 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9429 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9430 MachineFunction::iterator MBBIter = MBB;
9433 /// First build the CFG
9434 MachineFunction *F = MBB->getParent();
9435 MachineBasicBlock *thisMBB = MBB;
9436 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9437 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9438 F->insert(MBBIter, newMBB);
9439 F->insert(MBBIter, nextMBB);
9441 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9442 nextMBB->splice(nextMBB->begin(), thisMBB,
9443 llvm::next(MachineBasicBlock::iterator(mInstr)),
9445 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9447 // Update thisMBB to fall through to newMBB
9448 thisMBB->addSuccessor(newMBB);
9450 // newMBB jumps to newMBB and fall through to nextMBB
9451 newMBB->addSuccessor(nextMBB);
9452 newMBB->addSuccessor(newMBB);
9454 DebugLoc dl = mInstr->getDebugLoc();
9455 // Insert instructions into newMBB based on incoming instruction
9456 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9457 "unexpected number of operands");
9458 MachineOperand& destOper = mInstr->getOperand(0);
9459 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9460 int numArgs = mInstr->getNumOperands() - 1;
9461 for (int i=0; i < numArgs; ++i)
9462 argOpers[i] = &mInstr->getOperand(i+1);
9464 // x86 address has 4 operands: base, index, scale, and displacement
9465 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9466 int valArgIndx = lastAddrIndx + 1;
9468 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9469 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9470 for (int i=0; i <= lastAddrIndx; ++i)
9471 (*MIB).addOperand(*argOpers[i]);
9473 // We only support register and immediate values
9474 assert((argOpers[valArgIndx]->isReg() ||
9475 argOpers[valArgIndx]->isImm()) &&
9478 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9479 if (argOpers[valArgIndx]->isReg())
9480 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9482 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9483 (*MIB).addOperand(*argOpers[valArgIndx]);
9485 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9488 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9493 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9494 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9498 // Cmp and exchange if none has modified the memory location
9499 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9500 for (int i=0; i <= lastAddrIndx; ++i)
9501 (*MIB).addOperand(*argOpers[i]);
9503 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9504 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9505 mInstr->memoperands_end());
9507 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9508 MIB.addReg(X86::EAX);
9511 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9513 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9517 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9518 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9521 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9522 unsigned numArgs, bool memArg) const {
9523 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9524 "Target must have SSE4.2 or AVX features enabled");
9526 DebugLoc dl = MI->getDebugLoc();
9527 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9529 if (!Subtarget->hasAVX()) {
9531 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9533 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9536 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9538 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9541 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
9542 for (unsigned i = 0; i < numArgs; ++i) {
9543 MachineOperand &Op = MI->getOperand(i+1);
9544 if (!(Op.isReg() && Op.isImplicit()))
9547 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9550 MI->eraseFromParent();
9555 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
9556 DebugLoc dl = MI->getDebugLoc();
9557 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9559 // Address into RAX/EAX, other two args into ECX, EDX.
9560 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
9561 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
9562 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
9563 for (int i = 0; i < X86::AddrNumOperands; ++i)
9564 MIB.addOperand(MI->getOperand(i));
9566 unsigned ValOps = X86::AddrNumOperands;
9567 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9568 .addReg(MI->getOperand(ValOps).getReg());
9569 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
9570 .addReg(MI->getOperand(ValOps+1).getReg());
9572 // The instruction doesn't actually take any operands though.
9573 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
9575 MI->eraseFromParent(); // The pseudo is gone now.
9580 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
9581 DebugLoc dl = MI->getDebugLoc();
9582 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9584 // First arg in ECX, the second in EAX.
9585 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9586 .addReg(MI->getOperand(0).getReg());
9587 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
9588 .addReg(MI->getOperand(1).getReg());
9590 // The instruction doesn't actually take any operands though.
9591 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
9593 MI->eraseFromParent(); // The pseudo is gone now.
9598 X86TargetLowering::EmitVAARG64WithCustomInserter(
9600 MachineBasicBlock *MBB) const {
9601 // Emit va_arg instruction on X86-64.
9603 // Operands to this pseudo-instruction:
9604 // 0 ) Output : destination address (reg)
9605 // 1-5) Input : va_list address (addr, i64mem)
9606 // 6 ) ArgSize : Size (in bytes) of vararg type
9607 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
9608 // 8 ) Align : Alignment of type
9609 // 9 ) EFLAGS (implicit-def)
9611 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
9612 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
9614 unsigned DestReg = MI->getOperand(0).getReg();
9615 MachineOperand &Base = MI->getOperand(1);
9616 MachineOperand &Scale = MI->getOperand(2);
9617 MachineOperand &Index = MI->getOperand(3);
9618 MachineOperand &Disp = MI->getOperand(4);
9619 MachineOperand &Segment = MI->getOperand(5);
9620 unsigned ArgSize = MI->getOperand(6).getImm();
9621 unsigned ArgMode = MI->getOperand(7).getImm();
9622 unsigned Align = MI->getOperand(8).getImm();
9625 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
9626 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
9627 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
9629 // Machine Information
9630 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9631 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
9632 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
9633 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
9634 DebugLoc DL = MI->getDebugLoc();
9639 // i64 overflow_area (address)
9640 // i64 reg_save_area (address)
9642 // sizeof(va_list) = 24
9643 // alignment(va_list) = 8
9645 unsigned TotalNumIntRegs = 6;
9646 unsigned TotalNumXMMRegs = 8;
9647 bool UseGPOffset = (ArgMode == 1);
9648 bool UseFPOffset = (ArgMode == 2);
9649 unsigned MaxOffset = TotalNumIntRegs * 8 +
9650 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
9652 /* Align ArgSize to a multiple of 8 */
9653 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
9654 bool NeedsAlign = (Align > 8);
9656 MachineBasicBlock *thisMBB = MBB;
9657 MachineBasicBlock *overflowMBB;
9658 MachineBasicBlock *offsetMBB;
9659 MachineBasicBlock *endMBB;
9661 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
9662 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
9663 unsigned OffsetReg = 0;
9665 if (!UseGPOffset && !UseFPOffset) {
9666 // If we only pull from the overflow region, we don't create a branch.
9667 // We don't need to alter control flow.
9668 OffsetDestReg = 0; // unused
9669 OverflowDestReg = DestReg;
9672 overflowMBB = thisMBB;
9675 // First emit code to check if gp_offset (or fp_offset) is below the bound.
9676 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
9677 // If not, pull from overflow_area. (branch to overflowMBB)
9682 // offsetMBB overflowMBB
9687 // Registers for the PHI in endMBB
9688 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
9689 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
9691 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9692 MachineFunction *MF = MBB->getParent();
9693 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9694 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9695 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9697 MachineFunction::iterator MBBIter = MBB;
9700 // Insert the new basic blocks
9701 MF->insert(MBBIter, offsetMBB);
9702 MF->insert(MBBIter, overflowMBB);
9703 MF->insert(MBBIter, endMBB);
9705 // Transfer the remainder of MBB and its successor edges to endMBB.
9706 endMBB->splice(endMBB->begin(), thisMBB,
9707 llvm::next(MachineBasicBlock::iterator(MI)),
9709 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9711 // Make offsetMBB and overflowMBB successors of thisMBB
9712 thisMBB->addSuccessor(offsetMBB);
9713 thisMBB->addSuccessor(overflowMBB);
9715 // endMBB is a successor of both offsetMBB and overflowMBB
9716 offsetMBB->addSuccessor(endMBB);
9717 overflowMBB->addSuccessor(endMBB);
9719 // Load the offset value into a register
9720 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9721 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
9725 .addDisp(Disp, UseFPOffset ? 4 : 0)
9726 .addOperand(Segment)
9727 .setMemRefs(MMOBegin, MMOEnd);
9729 // Check if there is enough room left to pull this argument.
9730 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
9732 .addImm(MaxOffset + 8 - ArgSizeA8);
9734 // Branch to "overflowMBB" if offset >= max
9735 // Fall through to "offsetMBB" otherwise
9736 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
9737 .addMBB(overflowMBB);
9740 // In offsetMBB, emit code to use the reg_save_area.
9742 assert(OffsetReg != 0);
9744 // Read the reg_save_area address.
9745 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
9746 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
9751 .addOperand(Segment)
9752 .setMemRefs(MMOBegin, MMOEnd);
9754 // Zero-extend the offset
9755 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
9756 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
9759 .addImm(X86::sub_32bit);
9761 // Add the offset to the reg_save_area to get the final address.
9762 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
9763 .addReg(OffsetReg64)
9764 .addReg(RegSaveReg);
9766 // Compute the offset for the next argument
9767 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9768 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
9770 .addImm(UseFPOffset ? 16 : 8);
9772 // Store it back into the va_list.
9773 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
9777 .addDisp(Disp, UseFPOffset ? 4 : 0)
9778 .addOperand(Segment)
9779 .addReg(NextOffsetReg)
9780 .setMemRefs(MMOBegin, MMOEnd);
9783 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
9788 // Emit code to use overflow area
9791 // Load the overflow_area address into a register.
9792 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
9793 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
9798 .addOperand(Segment)
9799 .setMemRefs(MMOBegin, MMOEnd);
9801 // If we need to align it, do so. Otherwise, just copy the address
9802 // to OverflowDestReg.
9804 // Align the overflow address
9805 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
9806 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
9808 // aligned_addr = (addr + (align-1)) & ~(align-1)
9809 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
9810 .addReg(OverflowAddrReg)
9813 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
9815 .addImm(~(uint64_t)(Align-1));
9817 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
9818 .addReg(OverflowAddrReg);
9821 // Compute the next overflow address after this argument.
9822 // (the overflow address should be kept 8-byte aligned)
9823 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
9824 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
9825 .addReg(OverflowDestReg)
9828 // Store the new overflow address.
9829 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
9834 .addOperand(Segment)
9835 .addReg(NextAddrReg)
9836 .setMemRefs(MMOBegin, MMOEnd);
9838 // If we branched, emit the PHI to the front of endMBB.
9840 BuildMI(*endMBB, endMBB->begin(), DL,
9841 TII->get(X86::PHI), DestReg)
9842 .addReg(OffsetDestReg).addMBB(offsetMBB)
9843 .addReg(OverflowDestReg).addMBB(overflowMBB);
9846 // Erase the pseudo instruction
9847 MI->eraseFromParent();
9853 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9855 MachineBasicBlock *MBB) const {
9856 // Emit code to save XMM registers to the stack. The ABI says that the
9857 // number of registers to save is given in %al, so it's theoretically
9858 // possible to do an indirect jump trick to avoid saving all of them,
9859 // however this code takes a simpler approach and just executes all
9860 // of the stores if %al is non-zero. It's less code, and it's probably
9861 // easier on the hardware branch predictor, and stores aren't all that
9862 // expensive anyway.
9864 // Create the new basic blocks. One block contains all the XMM stores,
9865 // and one block is the final destination regardless of whether any
9866 // stores were performed.
9867 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9868 MachineFunction *F = MBB->getParent();
9869 MachineFunction::iterator MBBIter = MBB;
9871 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9872 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9873 F->insert(MBBIter, XMMSaveMBB);
9874 F->insert(MBBIter, EndMBB);
9876 // Transfer the remainder of MBB and its successor edges to EndMBB.
9877 EndMBB->splice(EndMBB->begin(), MBB,
9878 llvm::next(MachineBasicBlock::iterator(MI)),
9880 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9882 // The original block will now fall through to the XMM save block.
9883 MBB->addSuccessor(XMMSaveMBB);
9884 // The XMMSaveMBB will fall through to the end block.
9885 XMMSaveMBB->addSuccessor(EndMBB);
9887 // Now add the instructions.
9888 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9889 DebugLoc DL = MI->getDebugLoc();
9891 unsigned CountReg = MI->getOperand(0).getReg();
9892 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9893 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9895 if (!Subtarget->isTargetWin64()) {
9896 // If %al is 0, branch around the XMM save block.
9897 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9898 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9899 MBB->addSuccessor(EndMBB);
9902 // In the XMM save block, save all the XMM argument registers.
9903 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9904 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9905 MachineMemOperand *MMO =
9906 F->getMachineMemOperand(
9907 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
9908 MachineMemOperand::MOStore,
9909 /*Size=*/16, /*Align=*/16);
9910 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9911 .addFrameIndex(RegSaveFrameIndex)
9912 .addImm(/*Scale=*/1)
9913 .addReg(/*IndexReg=*/0)
9914 .addImm(/*Disp=*/Offset)
9915 .addReg(/*Segment=*/0)
9916 .addReg(MI->getOperand(i).getReg())
9917 .addMemOperand(MMO);
9920 MI->eraseFromParent(); // The pseudo instruction is gone now.
9926 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9927 MachineBasicBlock *BB) const {
9928 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9929 DebugLoc DL = MI->getDebugLoc();
9931 // To "insert" a SELECT_CC instruction, we actually have to insert the
9932 // diamond control-flow pattern. The incoming instruction knows the
9933 // destination vreg to set, the condition code register to branch on, the
9934 // true/false values to select between, and a branch opcode to use.
9935 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9936 MachineFunction::iterator It = BB;
9942 // cmpTY ccX, r1, r2
9944 // fallthrough --> copy0MBB
9945 MachineBasicBlock *thisMBB = BB;
9946 MachineFunction *F = BB->getParent();
9947 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9948 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9949 F->insert(It, copy0MBB);
9950 F->insert(It, sinkMBB);
9952 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9953 // live into the sink and copy blocks.
9954 const MachineFunction *MF = BB->getParent();
9955 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9956 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9958 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9959 const MachineOperand &MO = MI->getOperand(I);
9960 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9961 unsigned Reg = MO.getReg();
9962 if (Reg != X86::EFLAGS) continue;
9963 copy0MBB->addLiveIn(Reg);
9964 sinkMBB->addLiveIn(Reg);
9967 // Transfer the remainder of BB and its successor edges to sinkMBB.
9968 sinkMBB->splice(sinkMBB->begin(), BB,
9969 llvm::next(MachineBasicBlock::iterator(MI)),
9971 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9973 // Add the true and fallthrough blocks as its successors.
9974 BB->addSuccessor(copy0MBB);
9975 BB->addSuccessor(sinkMBB);
9977 // Create the conditional branch instruction.
9979 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9980 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9983 // %FalseValue = ...
9984 // # fallthrough to sinkMBB
9985 copy0MBB->addSuccessor(sinkMBB);
9988 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9990 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9991 TII->get(X86::PHI), MI->getOperand(0).getReg())
9992 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9993 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9995 MI->eraseFromParent(); // The pseudo instruction is gone now.
10000 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
10001 MachineBasicBlock *BB) const {
10002 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10003 DebugLoc DL = MI->getDebugLoc();
10005 // The lowering is pretty easy: we're just emitting the call to _alloca. The
10006 // non-trivial part is impdef of ESP.
10007 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
10010 const char *StackProbeSymbol =
10011 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
10013 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
10014 .addExternalSymbol(StackProbeSymbol)
10015 .addReg(X86::EAX, RegState::Implicit)
10016 .addReg(X86::ESP, RegState::Implicit)
10017 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
10018 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
10019 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10021 MI->eraseFromParent(); // The pseudo instruction is gone now.
10025 MachineBasicBlock *
10026 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
10027 MachineBasicBlock *BB) const {
10028 // This is pretty easy. We're taking the value that we received from
10029 // our load from the relocation, sticking it in either RDI (x86-64)
10030 // or EAX and doing an indirect call. The return value will then
10031 // be in the normal return register.
10032 const X86InstrInfo *TII
10033 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
10034 DebugLoc DL = MI->getDebugLoc();
10035 MachineFunction *F = BB->getParent();
10037 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
10038 assert(MI->getOperand(3).isGlobal() && "This should be a global");
10040 if (Subtarget->is64Bit()) {
10041 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10042 TII->get(X86::MOV64rm), X86::RDI)
10044 .addImm(0).addReg(0)
10045 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10046 MI->getOperand(3).getTargetFlags())
10048 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
10049 addDirectMem(MIB, X86::RDI);
10050 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
10051 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10052 TII->get(X86::MOV32rm), X86::EAX)
10054 .addImm(0).addReg(0)
10055 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10056 MI->getOperand(3).getTargetFlags())
10058 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10059 addDirectMem(MIB, X86::EAX);
10061 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10062 TII->get(X86::MOV32rm), X86::EAX)
10063 .addReg(TII->getGlobalBaseReg(F))
10064 .addImm(0).addReg(0)
10065 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10066 MI->getOperand(3).getTargetFlags())
10068 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10069 addDirectMem(MIB, X86::EAX);
10072 MI->eraseFromParent(); // The pseudo instruction is gone now.
10076 MachineBasicBlock *
10077 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
10078 MachineBasicBlock *BB) const {
10079 switch (MI->getOpcode()) {
10080 default: assert(false && "Unexpected instr type to insert");
10081 case X86::WIN_ALLOCA:
10082 return EmitLoweredWinAlloca(MI, BB);
10083 case X86::TLSCall_32:
10084 case X86::TLSCall_64:
10085 return EmitLoweredTLSCall(MI, BB);
10086 case X86::CMOV_GR8:
10087 case X86::CMOV_FR32:
10088 case X86::CMOV_FR64:
10089 case X86::CMOV_V4F32:
10090 case X86::CMOV_V2F64:
10091 case X86::CMOV_V2I64:
10092 case X86::CMOV_GR16:
10093 case X86::CMOV_GR32:
10094 case X86::CMOV_RFP32:
10095 case X86::CMOV_RFP64:
10096 case X86::CMOV_RFP80:
10097 return EmitLoweredSelect(MI, BB);
10099 case X86::FP32_TO_INT16_IN_MEM:
10100 case X86::FP32_TO_INT32_IN_MEM:
10101 case X86::FP32_TO_INT64_IN_MEM:
10102 case X86::FP64_TO_INT16_IN_MEM:
10103 case X86::FP64_TO_INT32_IN_MEM:
10104 case X86::FP64_TO_INT64_IN_MEM:
10105 case X86::FP80_TO_INT16_IN_MEM:
10106 case X86::FP80_TO_INT32_IN_MEM:
10107 case X86::FP80_TO_INT64_IN_MEM: {
10108 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10109 DebugLoc DL = MI->getDebugLoc();
10111 // Change the floating point control register to use "round towards zero"
10112 // mode when truncating to an integer value.
10113 MachineFunction *F = BB->getParent();
10114 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
10115 addFrameReference(BuildMI(*BB, MI, DL,
10116 TII->get(X86::FNSTCW16m)), CWFrameIdx);
10118 // Load the old value of the high byte of the control word...
10120 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
10121 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
10124 // Set the high part to be round to zero...
10125 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
10128 // Reload the modified control word now...
10129 addFrameReference(BuildMI(*BB, MI, DL,
10130 TII->get(X86::FLDCW16m)), CWFrameIdx);
10132 // Restore the memory image of control word to original value
10133 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
10136 // Get the X86 opcode to use.
10138 switch (MI->getOpcode()) {
10139 default: llvm_unreachable("illegal opcode!");
10140 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
10141 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
10142 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
10143 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
10144 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
10145 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
10146 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
10147 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
10148 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
10152 MachineOperand &Op = MI->getOperand(0);
10154 AM.BaseType = X86AddressMode::RegBase;
10155 AM.Base.Reg = Op.getReg();
10157 AM.BaseType = X86AddressMode::FrameIndexBase;
10158 AM.Base.FrameIndex = Op.getIndex();
10160 Op = MI->getOperand(1);
10162 AM.Scale = Op.getImm();
10163 Op = MI->getOperand(2);
10165 AM.IndexReg = Op.getImm();
10166 Op = MI->getOperand(3);
10167 if (Op.isGlobal()) {
10168 AM.GV = Op.getGlobal();
10170 AM.Disp = Op.getImm();
10172 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
10173 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
10175 // Reload the original control word now.
10176 addFrameReference(BuildMI(*BB, MI, DL,
10177 TII->get(X86::FLDCW16m)), CWFrameIdx);
10179 MI->eraseFromParent(); // The pseudo instruction is gone now.
10182 // String/text processing lowering.
10183 case X86::PCMPISTRM128REG:
10184 case X86::VPCMPISTRM128REG:
10185 return EmitPCMP(MI, BB, 3, false /* in-mem */);
10186 case X86::PCMPISTRM128MEM:
10187 case X86::VPCMPISTRM128MEM:
10188 return EmitPCMP(MI, BB, 3, true /* in-mem */);
10189 case X86::PCMPESTRM128REG:
10190 case X86::VPCMPESTRM128REG:
10191 return EmitPCMP(MI, BB, 5, false /* in mem */);
10192 case X86::PCMPESTRM128MEM:
10193 case X86::VPCMPESTRM128MEM:
10194 return EmitPCMP(MI, BB, 5, true /* in mem */);
10196 // Thread synchronization.
10198 return EmitMonitor(MI, BB);
10200 return EmitMwait(MI, BB);
10202 // Atomic Lowering.
10203 case X86::ATOMAND32:
10204 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10205 X86::AND32ri, X86::MOV32rm,
10207 X86::NOT32r, X86::EAX,
10208 X86::GR32RegisterClass);
10209 case X86::ATOMOR32:
10210 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
10211 X86::OR32ri, X86::MOV32rm,
10213 X86::NOT32r, X86::EAX,
10214 X86::GR32RegisterClass);
10215 case X86::ATOMXOR32:
10216 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
10217 X86::XOR32ri, X86::MOV32rm,
10219 X86::NOT32r, X86::EAX,
10220 X86::GR32RegisterClass);
10221 case X86::ATOMNAND32:
10222 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10223 X86::AND32ri, X86::MOV32rm,
10225 X86::NOT32r, X86::EAX,
10226 X86::GR32RegisterClass, true);
10227 case X86::ATOMMIN32:
10228 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
10229 case X86::ATOMMAX32:
10230 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
10231 case X86::ATOMUMIN32:
10232 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
10233 case X86::ATOMUMAX32:
10234 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
10236 case X86::ATOMAND16:
10237 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10238 X86::AND16ri, X86::MOV16rm,
10240 X86::NOT16r, X86::AX,
10241 X86::GR16RegisterClass);
10242 case X86::ATOMOR16:
10243 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
10244 X86::OR16ri, X86::MOV16rm,
10246 X86::NOT16r, X86::AX,
10247 X86::GR16RegisterClass);
10248 case X86::ATOMXOR16:
10249 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
10250 X86::XOR16ri, X86::MOV16rm,
10252 X86::NOT16r, X86::AX,
10253 X86::GR16RegisterClass);
10254 case X86::ATOMNAND16:
10255 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10256 X86::AND16ri, X86::MOV16rm,
10258 X86::NOT16r, X86::AX,
10259 X86::GR16RegisterClass, true);
10260 case X86::ATOMMIN16:
10261 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
10262 case X86::ATOMMAX16:
10263 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
10264 case X86::ATOMUMIN16:
10265 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
10266 case X86::ATOMUMAX16:
10267 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
10269 case X86::ATOMAND8:
10270 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10271 X86::AND8ri, X86::MOV8rm,
10273 X86::NOT8r, X86::AL,
10274 X86::GR8RegisterClass);
10276 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
10277 X86::OR8ri, X86::MOV8rm,
10279 X86::NOT8r, X86::AL,
10280 X86::GR8RegisterClass);
10281 case X86::ATOMXOR8:
10282 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
10283 X86::XOR8ri, X86::MOV8rm,
10285 X86::NOT8r, X86::AL,
10286 X86::GR8RegisterClass);
10287 case X86::ATOMNAND8:
10288 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10289 X86::AND8ri, X86::MOV8rm,
10291 X86::NOT8r, X86::AL,
10292 X86::GR8RegisterClass, true);
10293 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
10294 // This group is for 64-bit host.
10295 case X86::ATOMAND64:
10296 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10297 X86::AND64ri32, X86::MOV64rm,
10299 X86::NOT64r, X86::RAX,
10300 X86::GR64RegisterClass);
10301 case X86::ATOMOR64:
10302 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
10303 X86::OR64ri32, X86::MOV64rm,
10305 X86::NOT64r, X86::RAX,
10306 X86::GR64RegisterClass);
10307 case X86::ATOMXOR64:
10308 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
10309 X86::XOR64ri32, X86::MOV64rm,
10311 X86::NOT64r, X86::RAX,
10312 X86::GR64RegisterClass);
10313 case X86::ATOMNAND64:
10314 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10315 X86::AND64ri32, X86::MOV64rm,
10317 X86::NOT64r, X86::RAX,
10318 X86::GR64RegisterClass, true);
10319 case X86::ATOMMIN64:
10320 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
10321 case X86::ATOMMAX64:
10322 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
10323 case X86::ATOMUMIN64:
10324 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
10325 case X86::ATOMUMAX64:
10326 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
10328 // This group does 64-bit operations on a 32-bit host.
10329 case X86::ATOMAND6432:
10330 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10331 X86::AND32rr, X86::AND32rr,
10332 X86::AND32ri, X86::AND32ri,
10334 case X86::ATOMOR6432:
10335 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10336 X86::OR32rr, X86::OR32rr,
10337 X86::OR32ri, X86::OR32ri,
10339 case X86::ATOMXOR6432:
10340 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10341 X86::XOR32rr, X86::XOR32rr,
10342 X86::XOR32ri, X86::XOR32ri,
10344 case X86::ATOMNAND6432:
10345 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10346 X86::AND32rr, X86::AND32rr,
10347 X86::AND32ri, X86::AND32ri,
10349 case X86::ATOMADD6432:
10350 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10351 X86::ADD32rr, X86::ADC32rr,
10352 X86::ADD32ri, X86::ADC32ri,
10354 case X86::ATOMSUB6432:
10355 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10356 X86::SUB32rr, X86::SBB32rr,
10357 X86::SUB32ri, X86::SBB32ri,
10359 case X86::ATOMSWAP6432:
10360 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10361 X86::MOV32rr, X86::MOV32rr,
10362 X86::MOV32ri, X86::MOV32ri,
10364 case X86::VASTART_SAVE_XMM_REGS:
10365 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
10367 case X86::VAARG_64:
10368 return EmitVAARG64WithCustomInserter(MI, BB);
10372 //===----------------------------------------------------------------------===//
10373 // X86 Optimization Hooks
10374 //===----------------------------------------------------------------------===//
10376 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
10380 const SelectionDAG &DAG,
10381 unsigned Depth) const {
10382 unsigned Opc = Op.getOpcode();
10383 assert((Opc >= ISD::BUILTIN_OP_END ||
10384 Opc == ISD::INTRINSIC_WO_CHAIN ||
10385 Opc == ISD::INTRINSIC_W_CHAIN ||
10386 Opc == ISD::INTRINSIC_VOID) &&
10387 "Should use MaskedValueIsZero if you don't know whether Op"
10388 " is a target node!");
10390 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
10404 // These nodes' second result is a boolean.
10405 if (Op.getResNo() == 0)
10408 case X86ISD::SETCC:
10409 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
10410 Mask.getBitWidth() - 1);
10415 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
10416 unsigned Depth) const {
10417 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
10418 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
10419 return Op.getValueType().getScalarType().getSizeInBits();
10425 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
10426 /// node is a GlobalAddress + offset.
10427 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
10428 const GlobalValue* &GA,
10429 int64_t &Offset) const {
10430 if (N->getOpcode() == X86ISD::Wrapper) {
10431 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
10432 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
10433 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
10437 return TargetLowering::isGAPlusOffset(N, GA, Offset);
10440 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
10441 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
10442 /// if the load addresses are consecutive, non-overlapping, and in the right
10444 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
10445 TargetLowering::DAGCombinerInfo &DCI) {
10446 DebugLoc dl = N->getDebugLoc();
10447 EVT VT = N->getValueType(0);
10449 if (VT.getSizeInBits() != 128)
10452 // Don't create instructions with illegal types after legalize types has run.
10453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10454 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
10457 SmallVector<SDValue, 16> Elts;
10458 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
10459 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
10461 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
10464 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
10465 /// generation and convert it from being a bunch of shuffles and extracts
10466 /// to a simple store and scalar loads to extract the elements.
10467 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
10468 const TargetLowering &TLI) {
10469 SDValue InputVector = N->getOperand(0);
10471 // Only operate on vectors of 4 elements, where the alternative shuffling
10472 // gets to be more expensive.
10473 if (InputVector.getValueType() != MVT::v4i32)
10476 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
10477 // single use which is a sign-extend or zero-extend, and all elements are
10479 SmallVector<SDNode *, 4> Uses;
10480 unsigned ExtractedElements = 0;
10481 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
10482 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
10483 if (UI.getUse().getResNo() != InputVector.getResNo())
10486 SDNode *Extract = *UI;
10487 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10490 if (Extract->getValueType(0) != MVT::i32)
10492 if (!Extract->hasOneUse())
10494 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
10495 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
10497 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
10500 // Record which element was extracted.
10501 ExtractedElements |=
10502 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
10504 Uses.push_back(Extract);
10507 // If not all the elements were used, this may not be worthwhile.
10508 if (ExtractedElements != 15)
10511 // Ok, we've now decided to do the transformation.
10512 DebugLoc dl = InputVector.getDebugLoc();
10514 // Store the value to a temporary stack slot.
10515 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
10516 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
10517 MachinePointerInfo(), false, false, 0);
10519 // Replace each use (extract) with a load of the appropriate element.
10520 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
10521 UE = Uses.end(); UI != UE; ++UI) {
10522 SDNode *Extract = *UI;
10524 // Compute the element's address.
10525 SDValue Idx = Extract->getOperand(1);
10527 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
10528 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
10529 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
10531 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
10532 StackPtr, OffsetVal);
10534 // Load the scalar.
10535 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
10536 ScalarAddr, MachinePointerInfo(),
10539 // Replace the exact with the load.
10540 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
10543 // The replacement was made in place; don't return anything.
10547 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
10548 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
10549 const X86Subtarget *Subtarget) {
10550 DebugLoc DL = N->getDebugLoc();
10551 SDValue Cond = N->getOperand(0);
10552 // Get the LHS/RHS of the select.
10553 SDValue LHS = N->getOperand(1);
10554 SDValue RHS = N->getOperand(2);
10556 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
10557 // instructions match the semantics of the common C idiom x<y?x:y but not
10558 // x<=y?x:y, because of how they handle negative zero (which can be
10559 // ignored in unsafe-math mode).
10560 if (Subtarget->hasSSE2() &&
10561 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
10562 Cond.getOpcode() == ISD::SETCC) {
10563 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
10565 unsigned Opcode = 0;
10566 // Check for x CC y ? x : y.
10567 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
10568 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
10572 // Converting this to a min would handle NaNs incorrectly, and swapping
10573 // the operands would cause it to handle comparisons between positive
10574 // and negative zero incorrectly.
10575 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10576 if (!UnsafeFPMath &&
10577 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10579 std::swap(LHS, RHS);
10581 Opcode = X86ISD::FMIN;
10584 // Converting this to a min would handle comparisons between positive
10585 // and negative zero incorrectly.
10586 if (!UnsafeFPMath &&
10587 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
10589 Opcode = X86ISD::FMIN;
10592 // Converting this to a min would handle both negative zeros and NaNs
10593 // incorrectly, but we can swap the operands to fix both.
10594 std::swap(LHS, RHS);
10598 Opcode = X86ISD::FMIN;
10602 // Converting this to a max would handle comparisons between positive
10603 // and negative zero incorrectly.
10604 if (!UnsafeFPMath &&
10605 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
10607 Opcode = X86ISD::FMAX;
10610 // Converting this to a max would handle NaNs incorrectly, and swapping
10611 // the operands would cause it to handle comparisons between positive
10612 // and negative zero incorrectly.
10613 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10614 if (!UnsafeFPMath &&
10615 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10617 std::swap(LHS, RHS);
10619 Opcode = X86ISD::FMAX;
10622 // Converting this to a max would handle both negative zeros and NaNs
10623 // incorrectly, but we can swap the operands to fix both.
10624 std::swap(LHS, RHS);
10628 Opcode = X86ISD::FMAX;
10631 // Check for x CC y ? y : x -- a min/max with reversed arms.
10632 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
10633 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
10637 // Converting this to a min would handle comparisons between positive
10638 // and negative zero incorrectly, and swapping the operands would
10639 // cause it to handle NaNs incorrectly.
10640 if (!UnsafeFPMath &&
10641 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
10642 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10644 std::swap(LHS, RHS);
10646 Opcode = X86ISD::FMIN;
10649 // Converting this to a min would handle NaNs incorrectly.
10650 if (!UnsafeFPMath &&
10651 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10653 Opcode = X86ISD::FMIN;
10656 // Converting this to a min would handle both negative zeros and NaNs
10657 // incorrectly, but we can swap the operands to fix both.
10658 std::swap(LHS, RHS);
10662 Opcode = X86ISD::FMIN;
10666 // Converting this to a max would handle NaNs incorrectly.
10667 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10669 Opcode = X86ISD::FMAX;
10672 // Converting this to a max would handle comparisons between positive
10673 // and negative zero incorrectly, and swapping the operands would
10674 // cause it to handle NaNs incorrectly.
10675 if (!UnsafeFPMath &&
10676 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10677 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10679 std::swap(LHS, RHS);
10681 Opcode = X86ISD::FMAX;
10684 // Converting this to a max would handle both negative zeros and NaNs
10685 // incorrectly, but we can swap the operands to fix both.
10686 std::swap(LHS, RHS);
10690 Opcode = X86ISD::FMAX;
10696 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10699 // If this is a select between two integer constants, try to do some
10701 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10702 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10703 // Don't do this for crazy integer types.
10704 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10705 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10706 // so that TrueC (the true value) is larger than FalseC.
10707 bool NeedsCondInvert = false;
10709 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10710 // Efficiently invertible.
10711 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10712 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10713 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10714 NeedsCondInvert = true;
10715 std::swap(TrueC, FalseC);
10718 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10719 if (FalseC->getAPIntValue() == 0 &&
10720 TrueC->getAPIntValue().isPowerOf2()) {
10721 if (NeedsCondInvert) // Invert the condition if needed.
10722 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10723 DAG.getConstant(1, Cond.getValueType()));
10725 // Zero extend the condition if needed.
10726 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10728 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10729 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10730 DAG.getConstant(ShAmt, MVT::i8));
10733 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10734 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10735 if (NeedsCondInvert) // Invert the condition if needed.
10736 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10737 DAG.getConstant(1, Cond.getValueType()));
10739 // Zero extend the condition if needed.
10740 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10741 FalseC->getValueType(0), Cond);
10742 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10743 SDValue(FalseC, 0));
10746 // Optimize cases that will turn into an LEA instruction. This requires
10747 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10748 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10749 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10750 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10752 bool isFastMultiplier = false;
10754 switch ((unsigned char)Diff) {
10756 case 1: // result = add base, cond
10757 case 2: // result = lea base( , cond*2)
10758 case 3: // result = lea base(cond, cond*2)
10759 case 4: // result = lea base( , cond*4)
10760 case 5: // result = lea base(cond, cond*4)
10761 case 8: // result = lea base( , cond*8)
10762 case 9: // result = lea base(cond, cond*8)
10763 isFastMultiplier = true;
10768 if (isFastMultiplier) {
10769 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10770 if (NeedsCondInvert) // Invert the condition if needed.
10771 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10772 DAG.getConstant(1, Cond.getValueType()));
10774 // Zero extend the condition if needed.
10775 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10777 // Scale the condition by the difference.
10779 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10780 DAG.getConstant(Diff, Cond.getValueType()));
10782 // Add the base if non-zero.
10783 if (FalseC->getAPIntValue() != 0)
10784 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10785 SDValue(FalseC, 0));
10795 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10796 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10797 TargetLowering::DAGCombinerInfo &DCI) {
10798 DebugLoc DL = N->getDebugLoc();
10800 // If the flag operand isn't dead, don't touch this CMOV.
10801 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10804 // If this is a select between two integer constants, try to do some
10805 // optimizations. Note that the operands are ordered the opposite of SELECT
10807 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10808 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10809 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10810 // larger than FalseC (the false value).
10811 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10813 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10814 CC = X86::GetOppositeBranchCondition(CC);
10815 std::swap(TrueC, FalseC);
10818 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10819 // This is efficient for any integer data type (including i8/i16) and
10821 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10822 SDValue Cond = N->getOperand(3);
10823 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10824 DAG.getConstant(CC, MVT::i8), Cond);
10826 // Zero extend the condition if needed.
10827 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10829 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10830 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10831 DAG.getConstant(ShAmt, MVT::i8));
10832 if (N->getNumValues() == 2) // Dead flag value?
10833 return DCI.CombineTo(N, Cond, SDValue());
10837 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10838 // for any integer data type, including i8/i16.
10839 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10840 SDValue Cond = N->getOperand(3);
10841 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10842 DAG.getConstant(CC, MVT::i8), Cond);
10844 // Zero extend the condition if needed.
10845 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10846 FalseC->getValueType(0), Cond);
10847 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10848 SDValue(FalseC, 0));
10850 if (N->getNumValues() == 2) // Dead flag value?
10851 return DCI.CombineTo(N, Cond, SDValue());
10855 // Optimize cases that will turn into an LEA instruction. This requires
10856 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10857 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10858 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10859 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10861 bool isFastMultiplier = false;
10863 switch ((unsigned char)Diff) {
10865 case 1: // result = add base, cond
10866 case 2: // result = lea base( , cond*2)
10867 case 3: // result = lea base(cond, cond*2)
10868 case 4: // result = lea base( , cond*4)
10869 case 5: // result = lea base(cond, cond*4)
10870 case 8: // result = lea base( , cond*8)
10871 case 9: // result = lea base(cond, cond*8)
10872 isFastMultiplier = true;
10877 if (isFastMultiplier) {
10878 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10879 SDValue Cond = N->getOperand(3);
10880 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10881 DAG.getConstant(CC, MVT::i8), Cond);
10882 // Zero extend the condition if needed.
10883 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10885 // Scale the condition by the difference.
10887 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10888 DAG.getConstant(Diff, Cond.getValueType()));
10890 // Add the base if non-zero.
10891 if (FalseC->getAPIntValue() != 0)
10892 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10893 SDValue(FalseC, 0));
10894 if (N->getNumValues() == 2) // Dead flag value?
10895 return DCI.CombineTo(N, Cond, SDValue());
10905 /// PerformMulCombine - Optimize a single multiply with constant into two
10906 /// in order to implement it with two cheaper instructions, e.g.
10907 /// LEA + SHL, LEA + LEA.
10908 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10909 TargetLowering::DAGCombinerInfo &DCI) {
10910 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10913 EVT VT = N->getValueType(0);
10914 if (VT != MVT::i64)
10917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10920 uint64_t MulAmt = C->getZExtValue();
10921 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10924 uint64_t MulAmt1 = 0;
10925 uint64_t MulAmt2 = 0;
10926 if ((MulAmt % 9) == 0) {
10928 MulAmt2 = MulAmt / 9;
10929 } else if ((MulAmt % 5) == 0) {
10931 MulAmt2 = MulAmt / 5;
10932 } else if ((MulAmt % 3) == 0) {
10934 MulAmt2 = MulAmt / 3;
10937 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10938 DebugLoc DL = N->getDebugLoc();
10940 if (isPowerOf2_64(MulAmt2) &&
10941 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10942 // If second multiplifer is pow2, issue it first. We want the multiply by
10943 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10945 std::swap(MulAmt1, MulAmt2);
10948 if (isPowerOf2_64(MulAmt1))
10949 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10950 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10952 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10953 DAG.getConstant(MulAmt1, VT));
10955 if (isPowerOf2_64(MulAmt2))
10956 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10957 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10959 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10960 DAG.getConstant(MulAmt2, VT));
10962 // Do not add new nodes to DAG combiner worklist.
10963 DCI.CombineTo(N, NewMul, false);
10968 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10969 SDValue N0 = N->getOperand(0);
10970 SDValue N1 = N->getOperand(1);
10971 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10972 EVT VT = N0.getValueType();
10974 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10975 // since the result of setcc_c is all zero's or all ones.
10976 if (N1C && N0.getOpcode() == ISD::AND &&
10977 N0.getOperand(1).getOpcode() == ISD::Constant) {
10978 SDValue N00 = N0.getOperand(0);
10979 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10980 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10981 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10982 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10983 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10984 APInt ShAmt = N1C->getAPIntValue();
10985 Mask = Mask.shl(ShAmt);
10987 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10988 N00, DAG.getConstant(Mask, VT));
10995 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10997 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10998 const X86Subtarget *Subtarget) {
10999 EVT VT = N->getValueType(0);
11000 if (!VT.isVector() && VT.isInteger() &&
11001 N->getOpcode() == ISD::SHL)
11002 return PerformSHLCombine(N, DAG);
11004 // On X86 with SSE2 support, we can transform this to a vector shift if
11005 // all elements are shifted by the same amount. We can't do this in legalize
11006 // because the a constant vector is typically transformed to a constant pool
11007 // so we have no knowledge of the shift amount.
11008 if (!Subtarget->hasSSE2())
11011 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
11014 SDValue ShAmtOp = N->getOperand(1);
11015 EVT EltVT = VT.getVectorElementType();
11016 DebugLoc DL = N->getDebugLoc();
11017 SDValue BaseShAmt = SDValue();
11018 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
11019 unsigned NumElts = VT.getVectorNumElements();
11021 for (; i != NumElts; ++i) {
11022 SDValue Arg = ShAmtOp.getOperand(i);
11023 if (Arg.getOpcode() == ISD::UNDEF) continue;
11027 for (; i != NumElts; ++i) {
11028 SDValue Arg = ShAmtOp.getOperand(i);
11029 if (Arg.getOpcode() == ISD::UNDEF) continue;
11030 if (Arg != BaseShAmt) {
11034 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
11035 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
11036 SDValue InVec = ShAmtOp.getOperand(0);
11037 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
11038 unsigned NumElts = InVec.getValueType().getVectorNumElements();
11040 for (; i != NumElts; ++i) {
11041 SDValue Arg = InVec.getOperand(i);
11042 if (Arg.getOpcode() == ISD::UNDEF) continue;
11046 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
11047 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
11048 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
11049 if (C->getZExtValue() == SplatIdx)
11050 BaseShAmt = InVec.getOperand(1);
11053 if (BaseShAmt.getNode() == 0)
11054 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
11055 DAG.getIntPtrConstant(0));
11059 // The shift amount is an i32.
11060 if (EltVT.bitsGT(MVT::i32))
11061 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
11062 else if (EltVT.bitsLT(MVT::i32))
11063 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
11065 // The shift amount is identical so we can do a vector shift.
11066 SDValue ValOp = N->getOperand(0);
11067 switch (N->getOpcode()) {
11069 llvm_unreachable("Unknown shift opcode!");
11072 if (VT == MVT::v2i64)
11073 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11074 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
11076 if (VT == MVT::v4i32)
11077 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11078 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
11080 if (VT == MVT::v8i16)
11081 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11082 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
11086 if (VT == MVT::v4i32)
11087 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11088 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
11090 if (VT == MVT::v8i16)
11091 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11092 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
11096 if (VT == MVT::v2i64)
11097 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11098 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
11100 if (VT == MVT::v4i32)
11101 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11102 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
11104 if (VT == MVT::v8i16)
11105 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11106 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
11114 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
11115 TargetLowering::DAGCombinerInfo &DCI,
11116 const X86Subtarget *Subtarget) {
11117 if (DCI.isBeforeLegalizeOps())
11120 // Want to form PANDN nodes, in the hopes of then easily combining them with
11121 // OR and AND nodes to form PBLEND/PSIGN.
11122 EVT VT = N->getValueType(0);
11123 if (VT != MVT::v2i64)
11126 SDValue N0 = N->getOperand(0);
11127 SDValue N1 = N->getOperand(1);
11128 DebugLoc DL = N->getDebugLoc();
11130 // Check LHS for vnot
11131 if (N0.getOpcode() == ISD::XOR &&
11132 ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
11133 return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1);
11135 // Check RHS for vnot
11136 if (N1.getOpcode() == ISD::XOR &&
11137 ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
11138 return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0);
11143 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
11144 TargetLowering::DAGCombinerInfo &DCI,
11145 const X86Subtarget *Subtarget) {
11146 if (DCI.isBeforeLegalizeOps())
11149 EVT VT = N->getValueType(0);
11150 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
11153 SDValue N0 = N->getOperand(0);
11154 SDValue N1 = N->getOperand(1);
11156 // look for psign/blend
11157 if (Subtarget->hasSSSE3()) {
11158 if (VT == MVT::v2i64) {
11159 // Canonicalize pandn to RHS
11160 if (N0.getOpcode() == X86ISD::PANDN)
11162 // or (and (m, x), (pandn m, y))
11163 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::PANDN) {
11164 SDValue Mask = N1.getOperand(0);
11165 SDValue X = N1.getOperand(1);
11167 if (N0.getOperand(0) == Mask)
11168 Y = N0.getOperand(1);
11169 if (N0.getOperand(1) == Mask)
11170 Y = N0.getOperand(0);
11172 // Check to see if the mask appeared in both the AND and PANDN and
11176 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
11177 if (Mask.getOpcode() != ISD::BITCAST ||
11178 X.getOpcode() != ISD::BITCAST ||
11179 Y.getOpcode() != ISD::BITCAST)
11182 // Look through mask bitcast.
11183 Mask = Mask.getOperand(0);
11184 EVT MaskVT = Mask.getValueType();
11186 // Validate that the Mask operand is a vector sra node. The sra node
11187 // will be an intrinsic.
11188 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
11191 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
11192 // there is no psrai.b
11193 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
11194 case Intrinsic::x86_sse2_psrai_w:
11195 case Intrinsic::x86_sse2_psrai_d:
11197 default: return SDValue();
11200 // Check that the SRA is all signbits.
11201 SDValue SraC = Mask.getOperand(2);
11202 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
11203 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
11204 if ((SraAmt + 1) != EltBits)
11207 DebugLoc DL = N->getDebugLoc();
11209 // Now we know we at least have a plendvb with the mask val. See if
11210 // we can form a psignb/w/d.
11211 // psign = x.type == y.type == mask.type && y = sub(0, x);
11212 X = X.getOperand(0);
11213 Y = Y.getOperand(0);
11214 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
11215 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
11216 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
11219 case 8: Opc = X86ISD::PSIGNB; break;
11220 case 16: Opc = X86ISD::PSIGNW; break;
11221 case 32: Opc = X86ISD::PSIGND; break;
11225 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
11226 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
11229 // PBLENDVB only available on SSE 4.1
11230 if (!Subtarget->hasSSE41())
11233 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
11234 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
11235 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
11236 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
11237 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
11242 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
11243 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
11245 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
11247 if (!N0.hasOneUse() || !N1.hasOneUse())
11250 SDValue ShAmt0 = N0.getOperand(1);
11251 if (ShAmt0.getValueType() != MVT::i8)
11253 SDValue ShAmt1 = N1.getOperand(1);
11254 if (ShAmt1.getValueType() != MVT::i8)
11256 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
11257 ShAmt0 = ShAmt0.getOperand(0);
11258 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
11259 ShAmt1 = ShAmt1.getOperand(0);
11261 DebugLoc DL = N->getDebugLoc();
11262 unsigned Opc = X86ISD::SHLD;
11263 SDValue Op0 = N0.getOperand(0);
11264 SDValue Op1 = N1.getOperand(0);
11265 if (ShAmt0.getOpcode() == ISD::SUB) {
11266 Opc = X86ISD::SHRD;
11267 std::swap(Op0, Op1);
11268 std::swap(ShAmt0, ShAmt1);
11271 unsigned Bits = VT.getSizeInBits();
11272 if (ShAmt1.getOpcode() == ISD::SUB) {
11273 SDValue Sum = ShAmt1.getOperand(0);
11274 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
11275 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
11276 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
11277 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
11278 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
11279 return DAG.getNode(Opc, DL, VT,
11281 DAG.getNode(ISD::TRUNCATE, DL,
11284 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
11285 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
11287 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
11288 return DAG.getNode(Opc, DL, VT,
11289 N0.getOperand(0), N1.getOperand(0),
11290 DAG.getNode(ISD::TRUNCATE, DL,
11297 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
11298 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
11299 const X86Subtarget *Subtarget) {
11300 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
11301 // the FP state in cases where an emms may be missing.
11302 // A preferable solution to the general problem is to figure out the right
11303 // places to insert EMMS. This qualifies as a quick hack.
11305 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
11306 StoreSDNode *St = cast<StoreSDNode>(N);
11307 EVT VT = St->getValue().getValueType();
11308 if (VT.getSizeInBits() != 64)
11311 const Function *F = DAG.getMachineFunction().getFunction();
11312 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
11313 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
11314 && Subtarget->hasSSE2();
11315 if ((VT.isVector() ||
11316 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
11317 isa<LoadSDNode>(St->getValue()) &&
11318 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
11319 St->getChain().hasOneUse() && !St->isVolatile()) {
11320 SDNode* LdVal = St->getValue().getNode();
11321 LoadSDNode *Ld = 0;
11322 int TokenFactorIndex = -1;
11323 SmallVector<SDValue, 8> Ops;
11324 SDNode* ChainVal = St->getChain().getNode();
11325 // Must be a store of a load. We currently handle two cases: the load
11326 // is a direct child, and it's under an intervening TokenFactor. It is
11327 // possible to dig deeper under nested TokenFactors.
11328 if (ChainVal == LdVal)
11329 Ld = cast<LoadSDNode>(St->getChain());
11330 else if (St->getValue().hasOneUse() &&
11331 ChainVal->getOpcode() == ISD::TokenFactor) {
11332 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
11333 if (ChainVal->getOperand(i).getNode() == LdVal) {
11334 TokenFactorIndex = i;
11335 Ld = cast<LoadSDNode>(St->getValue());
11337 Ops.push_back(ChainVal->getOperand(i));
11341 if (!Ld || !ISD::isNormalLoad(Ld))
11344 // If this is not the MMX case, i.e. we are just turning i64 load/store
11345 // into f64 load/store, avoid the transformation if there are multiple
11346 // uses of the loaded value.
11347 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
11350 DebugLoc LdDL = Ld->getDebugLoc();
11351 DebugLoc StDL = N->getDebugLoc();
11352 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
11353 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
11355 if (Subtarget->is64Bit() || F64IsLegal) {
11356 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
11357 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
11358 Ld->getPointerInfo(), Ld->isVolatile(),
11359 Ld->isNonTemporal(), Ld->getAlignment());
11360 SDValue NewChain = NewLd.getValue(1);
11361 if (TokenFactorIndex != -1) {
11362 Ops.push_back(NewChain);
11363 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11366 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
11367 St->getPointerInfo(),
11368 St->isVolatile(), St->isNonTemporal(),
11369 St->getAlignment());
11372 // Otherwise, lower to two pairs of 32-bit loads / stores.
11373 SDValue LoAddr = Ld->getBasePtr();
11374 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
11375 DAG.getConstant(4, MVT::i32));
11377 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
11378 Ld->getPointerInfo(),
11379 Ld->isVolatile(), Ld->isNonTemporal(),
11380 Ld->getAlignment());
11381 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
11382 Ld->getPointerInfo().getWithOffset(4),
11383 Ld->isVolatile(), Ld->isNonTemporal(),
11384 MinAlign(Ld->getAlignment(), 4));
11386 SDValue NewChain = LoLd.getValue(1);
11387 if (TokenFactorIndex != -1) {
11388 Ops.push_back(LoLd);
11389 Ops.push_back(HiLd);
11390 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11394 LoAddr = St->getBasePtr();
11395 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
11396 DAG.getConstant(4, MVT::i32));
11398 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
11399 St->getPointerInfo(),
11400 St->isVolatile(), St->isNonTemporal(),
11401 St->getAlignment());
11402 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
11403 St->getPointerInfo().getWithOffset(4),
11405 St->isNonTemporal(),
11406 MinAlign(St->getAlignment(), 4));
11407 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
11412 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
11413 /// X86ISD::FXOR nodes.
11414 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
11415 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
11416 // F[X]OR(0.0, x) -> x
11417 // F[X]OR(x, 0.0) -> x
11418 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11419 if (C->getValueAPF().isPosZero())
11420 return N->getOperand(1);
11421 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11422 if (C->getValueAPF().isPosZero())
11423 return N->getOperand(0);
11427 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
11428 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
11429 // FAND(0.0, x) -> 0.0
11430 // FAND(x, 0.0) -> 0.0
11431 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11432 if (C->getValueAPF().isPosZero())
11433 return N->getOperand(0);
11434 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11435 if (C->getValueAPF().isPosZero())
11436 return N->getOperand(1);
11440 static SDValue PerformBTCombine(SDNode *N,
11442 TargetLowering::DAGCombinerInfo &DCI) {
11443 // BT ignores high bits in the bit index operand.
11444 SDValue Op1 = N->getOperand(1);
11445 if (Op1.hasOneUse()) {
11446 unsigned BitWidth = Op1.getValueSizeInBits();
11447 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
11448 APInt KnownZero, KnownOne;
11449 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
11450 !DCI.isBeforeLegalizeOps());
11451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11452 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
11453 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
11454 DCI.CommitTargetLoweringOpt(TLO);
11459 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
11460 SDValue Op = N->getOperand(0);
11461 if (Op.getOpcode() == ISD::BITCAST)
11462 Op = Op.getOperand(0);
11463 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
11464 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
11465 VT.getVectorElementType().getSizeInBits() ==
11466 OpVT.getVectorElementType().getSizeInBits()) {
11467 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
11472 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
11473 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
11474 // (and (i32 x86isd::setcc_carry), 1)
11475 // This eliminates the zext. This transformation is necessary because
11476 // ISD::SETCC is always legalized to i8.
11477 DebugLoc dl = N->getDebugLoc();
11478 SDValue N0 = N->getOperand(0);
11479 EVT VT = N->getValueType(0);
11480 if (N0.getOpcode() == ISD::AND &&
11482 N0.getOperand(0).hasOneUse()) {
11483 SDValue N00 = N0.getOperand(0);
11484 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
11486 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11487 if (!C || C->getZExtValue() != 1)
11489 return DAG.getNode(ISD::AND, dl, VT,
11490 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
11491 N00.getOperand(0), N00.getOperand(1)),
11492 DAG.getConstant(1, VT));
11498 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
11499 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
11500 unsigned X86CC = N->getConstantOperandVal(0);
11501 SDValue EFLAG = N->getOperand(1);
11502 DebugLoc DL = N->getDebugLoc();
11504 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
11505 // a zext and produces an all-ones bit which is more useful than 0/1 in some
11507 if (X86CC == X86::COND_B)
11508 return DAG.getNode(ISD::AND, DL, MVT::i8,
11509 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
11510 DAG.getConstant(X86CC, MVT::i8), EFLAG),
11511 DAG.getConstant(1, MVT::i8));
11516 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
11517 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
11518 X86TargetLowering::DAGCombinerInfo &DCI) {
11519 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
11520 // the result is either zero or one (depending on the input carry bit).
11521 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
11522 if (X86::isZeroNode(N->getOperand(0)) &&
11523 X86::isZeroNode(N->getOperand(1)) &&
11524 // We don't have a good way to replace an EFLAGS use, so only do this when
11526 SDValue(N, 1).use_empty()) {
11527 DebugLoc DL = N->getDebugLoc();
11528 EVT VT = N->getValueType(0);
11529 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
11530 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
11531 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
11532 DAG.getConstant(X86::COND_B,MVT::i8),
11534 DAG.getConstant(1, VT));
11535 return DCI.CombineTo(N, Res1, CarryOut);
11541 // fold (add Y, (sete X, 0)) -> adc 0, Y
11542 // (add Y, (setne X, 0)) -> sbb -1, Y
11543 // (sub (sete X, 0), Y) -> sbb 0, Y
11544 // (sub (setne X, 0), Y) -> adc -1, Y
11545 static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) {
11546 DebugLoc DL = N->getDebugLoc();
11548 // Look through ZExts.
11549 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
11550 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
11553 SDValue SetCC = Ext.getOperand(0);
11554 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
11557 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
11558 if (CC != X86::COND_E && CC != X86::COND_NE)
11561 SDValue Cmp = SetCC.getOperand(1);
11562 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
11563 !X86::isZeroNode(Cmp.getOperand(1)) ||
11564 !Cmp.getOperand(0).getValueType().isInteger())
11567 SDValue CmpOp0 = Cmp.getOperand(0);
11568 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
11569 DAG.getConstant(1, CmpOp0.getValueType()));
11571 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
11572 if (CC == X86::COND_NE)
11573 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
11574 DL, OtherVal.getValueType(), OtherVal,
11575 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
11576 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
11577 DL, OtherVal.getValueType(), OtherVal,
11578 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
11581 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
11582 DAGCombinerInfo &DCI) const {
11583 SelectionDAG &DAG = DCI.DAG;
11584 switch (N->getOpcode()) {
11586 case ISD::EXTRACT_VECTOR_ELT:
11587 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
11588 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
11589 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
11591 case ISD::SUB: return OptimizeConditonalInDecrement(N, DAG);
11592 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
11593 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
11596 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
11597 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
11598 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
11599 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
11601 case X86ISD::FOR: return PerformFORCombine(N, DAG);
11602 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
11603 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
11604 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
11605 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
11606 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
11607 case X86ISD::SHUFPS: // Handle all target specific shuffles
11608 case X86ISD::SHUFPD:
11609 case X86ISD::PALIGN:
11610 case X86ISD::PUNPCKHBW:
11611 case X86ISD::PUNPCKHWD:
11612 case X86ISD::PUNPCKHDQ:
11613 case X86ISD::PUNPCKHQDQ:
11614 case X86ISD::UNPCKHPS:
11615 case X86ISD::UNPCKHPD:
11616 case X86ISD::PUNPCKLBW:
11617 case X86ISD::PUNPCKLWD:
11618 case X86ISD::PUNPCKLDQ:
11619 case X86ISD::PUNPCKLQDQ:
11620 case X86ISD::UNPCKLPS:
11621 case X86ISD::UNPCKLPD:
11622 case X86ISD::MOVHLPS:
11623 case X86ISD::MOVLHPS:
11624 case X86ISD::PSHUFD:
11625 case X86ISD::PSHUFHW:
11626 case X86ISD::PSHUFLW:
11627 case X86ISD::MOVSS:
11628 case X86ISD::MOVSD:
11629 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
11635 /// isTypeDesirableForOp - Return true if the target has native support for
11636 /// the specified value type and it is 'desirable' to use the type for the
11637 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
11638 /// instruction encodings are longer and some i16 instructions are slow.
11639 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
11640 if (!isTypeLegal(VT))
11642 if (VT != MVT::i16)
11649 case ISD::SIGN_EXTEND:
11650 case ISD::ZERO_EXTEND:
11651 case ISD::ANY_EXTEND:
11664 /// IsDesirableToPromoteOp - This method query the target whether it is
11665 /// beneficial for dag combiner to promote the specified node. If true, it
11666 /// should return the desired promotion type by reference.
11667 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
11668 EVT VT = Op.getValueType();
11669 if (VT != MVT::i16)
11672 bool Promote = false;
11673 bool Commute = false;
11674 switch (Op.getOpcode()) {
11677 LoadSDNode *LD = cast<LoadSDNode>(Op);
11678 // If the non-extending load has a single use and it's not live out, then it
11679 // might be folded.
11680 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
11681 Op.hasOneUse()*/) {
11682 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11683 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
11684 // The only case where we'd want to promote LOAD (rather then it being
11685 // promoted as an operand is when it's only use is liveout.
11686 if (UI->getOpcode() != ISD::CopyToReg)
11693 case ISD::SIGN_EXTEND:
11694 case ISD::ZERO_EXTEND:
11695 case ISD::ANY_EXTEND:
11700 SDValue N0 = Op.getOperand(0);
11701 // Look out for (store (shl (load), x)).
11702 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
11715 SDValue N0 = Op.getOperand(0);
11716 SDValue N1 = Op.getOperand(1);
11717 if (!Commute && MayFoldLoad(N1))
11719 // Avoid disabling potential load folding opportunities.
11720 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
11722 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
11732 //===----------------------------------------------------------------------===//
11733 // X86 Inline Assembly Support
11734 //===----------------------------------------------------------------------===//
11736 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
11737 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
11739 std::string AsmStr = IA->getAsmString();
11741 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
11742 SmallVector<StringRef, 4> AsmPieces;
11743 SplitString(AsmStr, AsmPieces, ";\n");
11745 switch (AsmPieces.size()) {
11746 default: return false;
11748 AsmStr = AsmPieces[0];
11750 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
11752 // FIXME: this should verify that we are targetting a 486 or better. If not,
11753 // we will turn this bswap into something that will be lowered to logical ops
11754 // instead of emitting the bswap asm. For now, we don't support 486 or lower
11755 // so don't worry about this.
11757 if (AsmPieces.size() == 2 &&
11758 (AsmPieces[0] == "bswap" ||
11759 AsmPieces[0] == "bswapq" ||
11760 AsmPieces[0] == "bswapl") &&
11761 (AsmPieces[1] == "$0" ||
11762 AsmPieces[1] == "${0:q}")) {
11763 // No need to check constraints, nothing other than the equivalent of
11764 // "=r,0" would be valid here.
11765 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11766 if (!Ty || Ty->getBitWidth() % 16 != 0)
11768 return IntrinsicLowering::LowerToByteSwap(CI);
11770 // rorw $$8, ${0:w} --> llvm.bswap.i16
11771 if (CI->getType()->isIntegerTy(16) &&
11772 AsmPieces.size() == 3 &&
11773 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
11774 AsmPieces[1] == "$$8," &&
11775 AsmPieces[2] == "${0:w}" &&
11776 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11778 const std::string &ConstraintsStr = IA->getConstraintString();
11779 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
11780 std::sort(AsmPieces.begin(), AsmPieces.end());
11781 if (AsmPieces.size() == 4 &&
11782 AsmPieces[0] == "~{cc}" &&
11783 AsmPieces[1] == "~{dirflag}" &&
11784 AsmPieces[2] == "~{flags}" &&
11785 AsmPieces[3] == "~{fpsr}") {
11786 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11787 if (!Ty || Ty->getBitWidth() % 16 != 0)
11789 return IntrinsicLowering::LowerToByteSwap(CI);
11794 if (CI->getType()->isIntegerTy(32) &&
11795 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11796 SmallVector<StringRef, 4> Words;
11797 SplitString(AsmPieces[0], Words, " \t,");
11798 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11799 Words[2] == "${0:w}") {
11801 SplitString(AsmPieces[1], Words, " \t,");
11802 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
11803 Words[2] == "$0") {
11805 SplitString(AsmPieces[2], Words, " \t,");
11806 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11807 Words[2] == "${0:w}") {
11809 const std::string &ConstraintsStr = IA->getConstraintString();
11810 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
11811 std::sort(AsmPieces.begin(), AsmPieces.end());
11812 if (AsmPieces.size() == 4 &&
11813 AsmPieces[0] == "~{cc}" &&
11814 AsmPieces[1] == "~{dirflag}" &&
11815 AsmPieces[2] == "~{flags}" &&
11816 AsmPieces[3] == "~{fpsr}") {
11817 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11818 if (!Ty || Ty->getBitWidth() % 16 != 0)
11820 return IntrinsicLowering::LowerToByteSwap(CI);
11827 if (CI->getType()->isIntegerTy(64)) {
11828 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
11829 if (Constraints.size() >= 2 &&
11830 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
11831 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
11832 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
11833 SmallVector<StringRef, 4> Words;
11834 SplitString(AsmPieces[0], Words, " \t");
11835 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
11837 SplitString(AsmPieces[1], Words, " \t");
11838 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
11840 SplitString(AsmPieces[2], Words, " \t,");
11841 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
11842 Words[2] == "%edx") {
11843 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11844 if (!Ty || Ty->getBitWidth() % 16 != 0)
11846 return IntrinsicLowering::LowerToByteSwap(CI);
11859 /// getConstraintType - Given a constraint letter, return the type of
11860 /// constraint it is for this target.
11861 X86TargetLowering::ConstraintType
11862 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
11863 if (Constraint.size() == 1) {
11864 switch (Constraint[0]) {
11874 return C_RegisterClass;
11898 return TargetLowering::getConstraintType(Constraint);
11901 /// Examine constraint type and operand type and determine a weight value.
11902 /// This object must already have been set up with the operand type
11903 /// and the current alternative constraint selected.
11904 TargetLowering::ConstraintWeight
11905 X86TargetLowering::getSingleConstraintMatchWeight(
11906 AsmOperandInfo &info, const char *constraint) const {
11907 ConstraintWeight weight = CW_Invalid;
11908 Value *CallOperandVal = info.CallOperandVal;
11909 // If we don't have a value, we can't do a match,
11910 // but allow it at the lowest weight.
11911 if (CallOperandVal == NULL)
11913 const Type *type = CallOperandVal->getType();
11914 // Look at the constraint type.
11915 switch (*constraint) {
11917 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11928 if (CallOperandVal->getType()->isIntegerTy())
11929 weight = CW_SpecificReg;
11934 if (type->isFloatingPointTy())
11935 weight = CW_SpecificReg;
11938 if (type->isX86_MMXTy() && Subtarget->hasMMX())
11939 weight = CW_SpecificReg;
11943 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
11944 weight = CW_Register;
11947 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
11948 if (C->getZExtValue() <= 31)
11949 weight = CW_Constant;
11953 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11954 if (C->getZExtValue() <= 63)
11955 weight = CW_Constant;
11959 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11960 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
11961 weight = CW_Constant;
11965 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11966 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
11967 weight = CW_Constant;
11971 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11972 if (C->getZExtValue() <= 3)
11973 weight = CW_Constant;
11977 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11978 if (C->getZExtValue() <= 0xff)
11979 weight = CW_Constant;
11984 if (dyn_cast<ConstantFP>(CallOperandVal)) {
11985 weight = CW_Constant;
11989 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11990 if ((C->getSExtValue() >= -0x80000000LL) &&
11991 (C->getSExtValue() <= 0x7fffffffLL))
11992 weight = CW_Constant;
11996 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11997 if (C->getZExtValue() <= 0xffffffff)
11998 weight = CW_Constant;
12005 /// LowerXConstraint - try to replace an X constraint, which matches anything,
12006 /// with another that has more specific requirements based on the type of the
12007 /// corresponding operand.
12008 const char *X86TargetLowering::
12009 LowerXConstraint(EVT ConstraintVT) const {
12010 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
12011 // 'f' like normal targets.
12012 if (ConstraintVT.isFloatingPoint()) {
12013 if (Subtarget->hasXMMInt())
12015 if (Subtarget->hasXMM())
12019 return TargetLowering::LowerXConstraint(ConstraintVT);
12022 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
12023 /// vector. If it is invalid, don't add anything to Ops.
12024 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
12026 std::vector<SDValue>&Ops,
12027 SelectionDAG &DAG) const {
12028 SDValue Result(0, 0);
12030 switch (Constraint) {
12033 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12034 if (C->getZExtValue() <= 31) {
12035 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12042 if (C->getZExtValue() <= 63) {
12043 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12049 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12050 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
12051 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12058 if (C->getZExtValue() <= 255) {
12059 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12065 // 32-bit signed value
12066 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12067 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12068 C->getSExtValue())) {
12069 // Widen to 64 bits here to get it sign extended.
12070 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
12073 // FIXME gcc accepts some relocatable values here too, but only in certain
12074 // memory models; it's complicated.
12079 // 32-bit unsigned value
12080 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12081 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12082 C->getZExtValue())) {
12083 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12087 // FIXME gcc accepts some relocatable values here too, but only in certain
12088 // memory models; it's complicated.
12092 // Literal immediates are always ok.
12093 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
12094 // Widen to 64 bits here to get it sign extended.
12095 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
12099 // In any sort of PIC mode addresses need to be computed at runtime by
12100 // adding in a register or some sort of table lookup. These can't
12101 // be used as immediates.
12102 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
12105 // If we are in non-pic codegen mode, we allow the address of a global (with
12106 // an optional displacement) to be used with 'i'.
12107 GlobalAddressSDNode *GA = 0;
12108 int64_t Offset = 0;
12110 // Match either (GA), (GA+C), (GA+C1+C2), etc.
12112 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
12113 Offset += GA->getOffset();
12115 } else if (Op.getOpcode() == ISD::ADD) {
12116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12117 Offset += C->getZExtValue();
12118 Op = Op.getOperand(0);
12121 } else if (Op.getOpcode() == ISD::SUB) {
12122 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12123 Offset += -C->getZExtValue();
12124 Op = Op.getOperand(0);
12129 // Otherwise, this isn't something we can handle, reject it.
12133 const GlobalValue *GV = GA->getGlobal();
12134 // If we require an extra load to get this address, as in PIC mode, we
12135 // can't accept it.
12136 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
12137 getTargetMachine())))
12140 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
12141 GA->getValueType(0), Offset);
12146 if (Result.getNode()) {
12147 Ops.push_back(Result);
12150 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
12153 std::vector<unsigned> X86TargetLowering::
12154 getRegClassForInlineAsmConstraint(const std::string &Constraint,
12156 if (Constraint.size() == 1) {
12157 // FIXME: not handling fp-stack yet!
12158 switch (Constraint[0]) { // GCC X86 Constraint Letters
12159 default: break; // Unknown constraint letter
12160 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
12161 if (Subtarget->is64Bit()) {
12162 if (VT == MVT::i32)
12163 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
12164 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
12165 X86::R10D,X86::R11D,X86::R12D,
12166 X86::R13D,X86::R14D,X86::R15D,
12167 X86::EBP, X86::ESP, 0);
12168 else if (VT == MVT::i16)
12169 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
12170 X86::SI, X86::DI, X86::R8W,X86::R9W,
12171 X86::R10W,X86::R11W,X86::R12W,
12172 X86::R13W,X86::R14W,X86::R15W,
12173 X86::BP, X86::SP, 0);
12174 else if (VT == MVT::i8)
12175 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
12176 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
12177 X86::R10B,X86::R11B,X86::R12B,
12178 X86::R13B,X86::R14B,X86::R15B,
12179 X86::BPL, X86::SPL, 0);
12181 else if (VT == MVT::i64)
12182 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
12183 X86::RSI, X86::RDI, X86::R8, X86::R9,
12184 X86::R10, X86::R11, X86::R12,
12185 X86::R13, X86::R14, X86::R15,
12186 X86::RBP, X86::RSP, 0);
12190 // 32-bit fallthrough
12191 case 'Q': // Q_REGS
12192 if (VT == MVT::i32)
12193 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
12194 else if (VT == MVT::i16)
12195 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
12196 else if (VT == MVT::i8)
12197 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
12198 else if (VT == MVT::i64)
12199 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
12204 return std::vector<unsigned>();
12207 std::pair<unsigned, const TargetRegisterClass*>
12208 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
12210 // First, see if this is a constraint that directly corresponds to an LLVM
12212 if (Constraint.size() == 1) {
12213 // GCC Constraint Letters
12214 switch (Constraint[0]) {
12216 case 'r': // GENERAL_REGS
12217 case 'l': // INDEX_REGS
12219 return std::make_pair(0U, X86::GR8RegisterClass);
12220 if (VT == MVT::i16)
12221 return std::make_pair(0U, X86::GR16RegisterClass);
12222 if (VT == MVT::i32 || !Subtarget->is64Bit())
12223 return std::make_pair(0U, X86::GR32RegisterClass);
12224 return std::make_pair(0U, X86::GR64RegisterClass);
12225 case 'R': // LEGACY_REGS
12227 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
12228 if (VT == MVT::i16)
12229 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
12230 if (VT == MVT::i32 || !Subtarget->is64Bit())
12231 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
12232 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
12233 case 'f': // FP Stack registers.
12234 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
12235 // value to the correct fpstack register class.
12236 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
12237 return std::make_pair(0U, X86::RFP32RegisterClass);
12238 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
12239 return std::make_pair(0U, X86::RFP64RegisterClass);
12240 return std::make_pair(0U, X86::RFP80RegisterClass);
12241 case 'y': // MMX_REGS if MMX allowed.
12242 if (!Subtarget->hasMMX()) break;
12243 return std::make_pair(0U, X86::VR64RegisterClass);
12244 case 'Y': // SSE_REGS if SSE2 allowed
12245 if (!Subtarget->hasXMMInt()) break;
12247 case 'x': // SSE_REGS if SSE1 allowed
12248 if (!Subtarget->hasXMM()) break;
12250 switch (VT.getSimpleVT().SimpleTy) {
12252 // Scalar SSE types.
12255 return std::make_pair(0U, X86::FR32RegisterClass);
12258 return std::make_pair(0U, X86::FR64RegisterClass);
12266 return std::make_pair(0U, X86::VR128RegisterClass);
12272 // Use the default implementation in TargetLowering to convert the register
12273 // constraint into a member of a register class.
12274 std::pair<unsigned, const TargetRegisterClass*> Res;
12275 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
12277 // Not found as a standard register?
12278 if (Res.second == 0) {
12279 // Map st(0) -> st(7) -> ST0
12280 if (Constraint.size() == 7 && Constraint[0] == '{' &&
12281 tolower(Constraint[1]) == 's' &&
12282 tolower(Constraint[2]) == 't' &&
12283 Constraint[3] == '(' &&
12284 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
12285 Constraint[5] == ')' &&
12286 Constraint[6] == '}') {
12288 Res.first = X86::ST0+Constraint[4]-'0';
12289 Res.second = X86::RFP80RegisterClass;
12293 // GCC allows "st(0)" to be called just plain "st".
12294 if (StringRef("{st}").equals_lower(Constraint)) {
12295 Res.first = X86::ST0;
12296 Res.second = X86::RFP80RegisterClass;
12301 if (StringRef("{flags}").equals_lower(Constraint)) {
12302 Res.first = X86::EFLAGS;
12303 Res.second = X86::CCRRegisterClass;
12307 // 'A' means EAX + EDX.
12308 if (Constraint == "A") {
12309 Res.first = X86::EAX;
12310 Res.second = X86::GR32_ADRegisterClass;
12316 // Otherwise, check to see if this is a register class of the wrong value
12317 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
12318 // turn into {ax},{dx}.
12319 if (Res.second->hasType(VT))
12320 return Res; // Correct type already, nothing to do.
12322 // All of the single-register GCC register classes map their values onto
12323 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
12324 // really want an 8-bit or 32-bit register, map to the appropriate register
12325 // class and return the appropriate register.
12326 if (Res.second == X86::GR16RegisterClass) {
12327 if (VT == MVT::i8) {
12328 unsigned DestReg = 0;
12329 switch (Res.first) {
12331 case X86::AX: DestReg = X86::AL; break;
12332 case X86::DX: DestReg = X86::DL; break;
12333 case X86::CX: DestReg = X86::CL; break;
12334 case X86::BX: DestReg = X86::BL; break;
12337 Res.first = DestReg;
12338 Res.second = X86::GR8RegisterClass;
12340 } else if (VT == MVT::i32) {
12341 unsigned DestReg = 0;
12342 switch (Res.first) {
12344 case X86::AX: DestReg = X86::EAX; break;
12345 case X86::DX: DestReg = X86::EDX; break;
12346 case X86::CX: DestReg = X86::ECX; break;
12347 case X86::BX: DestReg = X86::EBX; break;
12348 case X86::SI: DestReg = X86::ESI; break;
12349 case X86::DI: DestReg = X86::EDI; break;
12350 case X86::BP: DestReg = X86::EBP; break;
12351 case X86::SP: DestReg = X86::ESP; break;
12354 Res.first = DestReg;
12355 Res.second = X86::GR32RegisterClass;
12357 } else if (VT == MVT::i64) {
12358 unsigned DestReg = 0;
12359 switch (Res.first) {
12361 case X86::AX: DestReg = X86::RAX; break;
12362 case X86::DX: DestReg = X86::RDX; break;
12363 case X86::CX: DestReg = X86::RCX; break;
12364 case X86::BX: DestReg = X86::RBX; break;
12365 case X86::SI: DestReg = X86::RSI; break;
12366 case X86::DI: DestReg = X86::RDI; break;
12367 case X86::BP: DestReg = X86::RBP; break;
12368 case X86::SP: DestReg = X86::RSP; break;
12371 Res.first = DestReg;
12372 Res.second = X86::GR64RegisterClass;
12375 } else if (Res.second == X86::FR32RegisterClass ||
12376 Res.second == X86::FR64RegisterClass ||
12377 Res.second == X86::VR128RegisterClass) {
12378 // Handle references to XMM physical registers that got mapped into the
12379 // wrong class. This can happen with constraints like {xmm0} where the
12380 // target independent register mapper will just pick the first match it can
12381 // find, ignoring the required type.
12382 if (VT == MVT::f32)
12383 Res.second = X86::FR32RegisterClass;
12384 else if (VT == MVT::f64)
12385 Res.second = X86::FR64RegisterClass;
12386 else if (X86::VR128RegisterClass->hasType(VT))
12387 Res.second = X86::VR128RegisterClass;