1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/LLVMContext.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCExpr.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/Dwarf.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
53 using namespace dwarf;
55 STATISTIC(NumTailCalls, "Number of tail calls");
58 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
66 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
68 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
69 if (is64Bit) return new X8664_MachoTargetObjectFile();
70 return new TargetLoweringObjectFileMachO();
71 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
72 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
73 return new X8632_ELFTargetObjectFile(TM);
74 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
75 return new TargetLoweringObjectFileCOFF();
77 llvm_unreachable("unknown subtarget type");
80 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
81 : TargetLowering(TM, createTLOF(TM)) {
82 Subtarget = &TM.getSubtarget<X86Subtarget>();
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
85 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
87 RegInfo = TM.getRegisterInfo();
90 // Set up the TargetLowering object.
92 // X86 is weird, it always uses i8 for shift amounts and setcc results.
93 setShiftAmountType(MVT::i8);
94 setBooleanContents(ZeroOrOneBooleanContent);
95 setSchedulingPreference(Sched::RegPressure);
96 setStackPointerRegisterToSaveRestore(X86StackPtr);
98 if (Subtarget->isTargetDarwin()) {
99 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
100 setUseUnderscoreSetJmp(false);
101 setUseUnderscoreLongJmp(false);
102 } else if (Subtarget->isTargetMingw()) {
103 // MS runtime is weird: it exports _setjmp, but longjmp!
104 setUseUnderscoreSetJmp(true);
105 setUseUnderscoreLongJmp(false);
107 setUseUnderscoreSetJmp(true);
108 setUseUnderscoreLongJmp(true);
111 // Set up the register classes.
112 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
122 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
124 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
125 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
128 // SETOEQ and SETUNE require checking two conditions.
129 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
130 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
131 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
132 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
133 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
136 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
138 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
139 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
140 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
142 if (Subtarget->is64Bit()) {
143 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
144 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
145 } else if (!UseSoftFloat) {
146 // We have an algorithm for SSE2->double, and we turn this into a
147 // 64-bit FILD followed by conditional FADD for other targets.
148 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
149 // We have an algorithm for SSE2, and we turn this into a 64-bit
150 // FILD for other targets.
151 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
154 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
156 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
157 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
160 // SSE has no i16 to fp conversion, only i32
161 if (X86ScalarSSEf32) {
162 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
163 // f32 and f64 cases are Legal, f80 case is not
164 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
166 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
174 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
175 // are Legal, f80 is custom lowered.
176 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
177 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
179 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
181 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
182 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
184 if (X86ScalarSSEf32) {
185 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
186 // f32 and f64 cases are Legal, f80 case is not
187 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
189 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
193 // Handle FP_TO_UINT by promoting the destination to a larger signed
195 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
196 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
197 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
199 if (Subtarget->is64Bit()) {
200 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
202 } else if (!UseSoftFloat) {
203 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
204 // Expand FP_TO_UINT into a select.
205 // FIXME: We would like to use a Custom expander here eventually to do
206 // the optimal thing for SSE vs. the default expansion in the legalizer.
207 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
209 // With SSE3 we can use fisttpll to convert to a signed i64; without
210 // SSE, we're stuck with a fistpll.
211 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
214 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
215 if (!X86ScalarSSEf64) {
216 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
217 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
218 if (Subtarget->is64Bit()) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
220 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
221 if (Subtarget->hasMMX() && !DisableMMX)
222 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
228 // Scalar integer divide and remainder are lowered to use operations that
229 // produce two results, to match the available instructions. This exposes
230 // the two-result form to trivial CSE, which is able to combine x/y and x%y
231 // into a single instruction.
233 // Scalar integer multiply-high is also lowered to use two-result
234 // operations, to match the available instructions. However, plain multiply
235 // (low) operations are left as Legal, as there are single-result
236 // instructions for this in x86. Using the two-result multiply instructions
237 // when both high and low results are needed must be arranged by dagcombine.
238 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
240 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
241 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
242 setOperationAction(ISD::SREM , MVT::i8 , Expand);
243 setOperationAction(ISD::UREM , MVT::i8 , Expand);
244 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
246 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
247 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
248 setOperationAction(ISD::SREM , MVT::i16 , Expand);
249 setOperationAction(ISD::UREM , MVT::i16 , Expand);
250 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
252 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
253 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
254 setOperationAction(ISD::SREM , MVT::i32 , Expand);
255 setOperationAction(ISD::UREM , MVT::i32 , Expand);
256 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
257 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
258 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
259 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
260 setOperationAction(ISD::SREM , MVT::i64 , Expand);
261 setOperationAction(ISD::UREM , MVT::i64 , Expand);
263 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
264 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
265 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
266 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
267 if (Subtarget->is64Bit())
268 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
272 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
273 setOperationAction(ISD::FREM , MVT::f32 , Expand);
274 setOperationAction(ISD::FREM , MVT::f64 , Expand);
275 setOperationAction(ISD::FREM , MVT::f80 , Expand);
276 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
278 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
279 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
280 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
281 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
282 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
283 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
300 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
302 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
303 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
305 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
306 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
308 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
309 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
315 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
318 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
319 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
320 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
321 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
322 if (Subtarget->is64Bit())
323 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
324 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
325 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
328 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
329 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
330 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
333 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
334 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
335 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
336 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
339 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
340 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
343 if (Subtarget->hasSSE1())
344 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
346 if (!Subtarget->hasSSE2())
347 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
348 // On X86 and X86-64, atomic operations are lowered to locked instructions.
349 // Locked instructions, in turn, have implicit fence semantics (all memory
350 // operations are flushed before issuing the locked instruction, and they
351 // are not buffered), so we can fold away the common pattern of
352 // fence-atomic-fence.
353 setShouldFoldAtomicFences(true);
355 // Expand certain atomics
356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
366 if (!Subtarget->is64Bit()) {
367 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
376 // FIXME - use subtarget debug flags
377 if (!Subtarget->isTargetDarwin() &&
378 !Subtarget->isTargetELF() &&
379 !Subtarget->isTargetCygMing()) {
380 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
383 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
384 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
387 if (Subtarget->is64Bit()) {
388 setExceptionPointerRegister(X86::RAX);
389 setExceptionSelectorRegister(X86::RDX);
391 setExceptionPointerRegister(X86::EAX);
392 setExceptionSelectorRegister(X86::EDX);
394 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
397 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
402 setOperationAction(ISD::VASTART , MVT::Other, Custom);
403 setOperationAction(ISD::VAEND , MVT::Other, Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::VAARG , MVT::Other, Custom);
406 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
408 setOperationAction(ISD::VAARG , MVT::Other, Expand);
409 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
412 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
413 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
414 if (Subtarget->is64Bit())
415 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
416 if (Subtarget->isTargetCygMing())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
421 if (!UseSoftFloat && X86ScalarSSEf64) {
422 // f32 and f64 use SSE.
423 // Set up the FP register classes.
424 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
425 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
427 // Use ANDPD to simulate FABS.
428 setOperationAction(ISD::FABS , MVT::f64, Custom);
429 setOperationAction(ISD::FABS , MVT::f32, Custom);
431 // Use XORP to simulate FNEG.
432 setOperationAction(ISD::FNEG , MVT::f64, Custom);
433 setOperationAction(ISD::FNEG , MVT::f32, Custom);
435 // Use ANDPD and ORPD to simulate FCOPYSIGN.
436 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
437 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
439 // We don't support sin/cos/fmod
440 setOperationAction(ISD::FSIN , MVT::f64, Expand);
441 setOperationAction(ISD::FCOS , MVT::f64, Expand);
442 setOperationAction(ISD::FSIN , MVT::f32, Expand);
443 setOperationAction(ISD::FCOS , MVT::f32, Expand);
445 // Expand FP immediates into loads from the stack, except for the special
447 addLegalFPImmediate(APFloat(+0.0)); // xorpd
448 addLegalFPImmediate(APFloat(+0.0f)); // xorps
449 } else if (!UseSoftFloat && X86ScalarSSEf32) {
450 // Use SSE for f32, x87 for f64.
451 // Set up the FP register classes.
452 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
453 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
455 // Use ANDPS to simulate FABS.
456 setOperationAction(ISD::FABS , MVT::f32, Custom);
458 // Use XORP to simulate FNEG.
459 setOperationAction(ISD::FNEG , MVT::f32, Custom);
461 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
463 // Use ANDPS and ORPS to simulate FCOPYSIGN.
464 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
465 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
467 // We don't support sin/cos/fmod
468 setOperationAction(ISD::FSIN , MVT::f32, Expand);
469 setOperationAction(ISD::FCOS , MVT::f32, Expand);
471 // Special cases we handle for FP constants.
472 addLegalFPImmediate(APFloat(+0.0f)); // xorps
473 addLegalFPImmediate(APFloat(+0.0)); // FLD0
474 addLegalFPImmediate(APFloat(+1.0)); // FLD1
475 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
476 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
479 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
480 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
482 } else if (!UseSoftFloat) {
483 // f32 and f64 in x87.
484 // Set up the FP register classes.
485 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
486 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
488 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
489 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
490 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
494 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
495 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
497 addLegalFPImmediate(APFloat(+0.0)); // FLD0
498 addLegalFPImmediate(APFloat(+1.0)); // FLD1
499 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
500 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
501 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
502 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
503 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
504 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
507 // Long double always uses X87.
509 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
510 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
511 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
514 APFloat TmpFlt(+0.0);
515 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
517 addLegalFPImmediate(TmpFlt); // FLD0
519 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
520 APFloat TmpFlt2(+1.0);
521 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
523 addLegalFPImmediate(TmpFlt2); // FLD1
524 TmpFlt2.changeSign();
525 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
529 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
530 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
534 // Always use a library call for pow.
535 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
536 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
539 setOperationAction(ISD::FLOG, MVT::f80, Expand);
540 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
542 setOperationAction(ISD::FEXP, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
545 // First set operation action for all vector types to either promote
546 // (for widening) or expand (for scalarization). Then we will selectively
547 // turn on ones that can be effectively codegen'd.
548 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
549 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
550 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
565 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
599 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
604 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
605 setTruncStoreAction((MVT::SimpleValueType)VT,
606 (MVT::SimpleValueType)InnerVT, Expand);
607 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
608 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
609 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
612 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
613 // with -msoft-float, disable use of MMX as well.
614 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
615 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
616 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
617 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
619 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
621 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
622 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
623 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
624 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
626 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
627 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
628 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
629 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
631 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
632 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
634 setOperationAction(ISD::AND, MVT::v8i8, Promote);
635 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
636 setOperationAction(ISD::AND, MVT::v4i16, Promote);
637 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
638 setOperationAction(ISD::AND, MVT::v2i32, Promote);
639 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
640 setOperationAction(ISD::AND, MVT::v1i64, Legal);
642 setOperationAction(ISD::OR, MVT::v8i8, Promote);
643 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
644 setOperationAction(ISD::OR, MVT::v4i16, Promote);
645 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
646 setOperationAction(ISD::OR, MVT::v2i32, Promote);
647 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
648 setOperationAction(ISD::OR, MVT::v1i64, Legal);
650 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
651 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
652 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
653 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
654 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
655 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
656 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
658 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
659 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
660 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
661 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
662 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
663 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
664 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
666 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
667 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
671 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
672 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
676 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
680 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
682 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
683 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
684 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
685 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
686 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
687 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
688 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
690 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
691 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
692 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
693 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
694 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
698 if (!UseSoftFloat && Subtarget->hasSSE1()) {
699 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
701 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
702 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
703 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
704 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
705 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
706 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
707 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
708 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
709 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
710 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
711 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
712 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
715 if (!UseSoftFloat && Subtarget->hasSSE2()) {
716 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
718 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
719 // registers cannot be used even for integer operations.
720 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
721 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
722 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
723 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
725 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
726 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
727 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
728 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
729 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
730 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
731 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
732 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
733 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
734 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
735 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
736 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
737 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
738 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
739 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
740 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
742 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
743 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
744 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
745 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
747 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
749 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
750 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
753 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
754 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
759 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
760 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
761 EVT VT = (MVT::SimpleValueType)i;
762 // Do not attempt to custom lower non-power-of-2 vectors
763 if (!isPowerOf2_32(VT.getVectorNumElements()))
765 // Do not attempt to custom lower non-128-bit vectors
766 if (!VT.is128BitVector())
768 setOperationAction(ISD::BUILD_VECTOR,
769 VT.getSimpleVT().SimpleTy, Custom);
770 setOperationAction(ISD::VECTOR_SHUFFLE,
771 VT.getSimpleVT().SimpleTy, Custom);
772 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
773 VT.getSimpleVT().SimpleTy, Custom);
776 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
777 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
778 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
780 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
783 if (Subtarget->is64Bit()) {
784 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
785 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
788 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
789 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
790 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
793 // Do not attempt to promote non-128-bit vectors
794 if (!VT.is128BitVector())
797 setOperationAction(ISD::AND, SVT, Promote);
798 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
799 setOperationAction(ISD::OR, SVT, Promote);
800 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
801 setOperationAction(ISD::XOR, SVT, Promote);
802 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
803 setOperationAction(ISD::LOAD, SVT, Promote);
804 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
805 setOperationAction(ISD::SELECT, SVT, Promote);
806 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
809 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
811 // Custom lower v2i64 and v2f64 selects.
812 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
813 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
814 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
815 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
817 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
818 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
819 if (!DisableMMX && Subtarget->hasMMX()) {
820 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
821 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
825 if (Subtarget->hasSSE41()) {
826 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
827 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
828 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
829 setOperationAction(ISD::FRINT, MVT::f32, Legal);
830 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
831 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
832 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
833 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
834 setOperationAction(ISD::FRINT, MVT::f64, Legal);
835 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
837 // FIXME: Do we need to handle scalar-to-vector here?
838 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
840 // i8 and i16 vectors are custom , because the source register and source
841 // source memory operand types are not the same width. f32 vectors are
842 // custom since the immediate controlling the insert encodes additional
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
854 if (Subtarget->is64Bit()) {
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
860 if (Subtarget->hasSSE42()) {
861 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
864 if (!UseSoftFloat && Subtarget->hasAVX()) {
865 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
866 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
867 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
868 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
870 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
871 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
872 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
873 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
874 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
875 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
876 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
877 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
878 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
879 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
880 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
881 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
882 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
883 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
884 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
886 // Operations to consider commented out -v16i16 v32i8
887 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
888 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
889 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
890 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
891 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
892 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
893 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
894 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
895 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
896 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
897 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
898 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
899 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
900 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
902 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
903 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
904 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
905 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
907 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
908 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
909 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
913 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
914 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
915 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
918 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
921 // Not sure we want to do this since there are no 256-bit integer
924 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
925 // This includes 256-bit vectors
926 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
927 EVT VT = (MVT::SimpleValueType)i;
929 // Do not attempt to custom lower non-power-of-2 vectors
930 if (!isPowerOf2_32(VT.getVectorNumElements()))
933 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
934 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
935 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
938 if (Subtarget->is64Bit()) {
939 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
940 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
945 // Not sure we want to do this since there are no 256-bit integer
948 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
949 // Including 256-bit vectors
950 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
951 EVT VT = (MVT::SimpleValueType)i;
953 if (!VT.is256BitVector()) {
956 setOperationAction(ISD::AND, VT, Promote);
957 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
958 setOperationAction(ISD::OR, VT, Promote);
959 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
960 setOperationAction(ISD::XOR, VT, Promote);
961 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
962 setOperationAction(ISD::LOAD, VT, Promote);
963 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
964 setOperationAction(ISD::SELECT, VT, Promote);
965 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
968 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
972 // We want to custom lower some of our intrinsics.
973 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
975 // Add/Sub/Mul with overflow operations are custom lowered.
976 setOperationAction(ISD::SADDO, MVT::i32, Custom);
977 setOperationAction(ISD::UADDO, MVT::i32, Custom);
978 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
979 setOperationAction(ISD::USUBO, MVT::i32, Custom);
980 setOperationAction(ISD::SMULO, MVT::i32, Custom);
982 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
983 // handle type legalization for these operations here.
985 // FIXME: We really should do custom legalization for addition and
986 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
987 // than generic legalization for 64-bit multiplication-with-overflow, though.
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::SADDO, MVT::i64, Custom);
990 setOperationAction(ISD::UADDO, MVT::i64, Custom);
991 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
992 setOperationAction(ISD::USUBO, MVT::i64, Custom);
993 setOperationAction(ISD::SMULO, MVT::i64, Custom);
996 if (!Subtarget->is64Bit()) {
997 // These libcalls are not available in 32-bit.
998 setLibcallName(RTLIB::SHL_I128, 0);
999 setLibcallName(RTLIB::SRL_I128, 0);
1000 setLibcallName(RTLIB::SRA_I128, 0);
1003 // We have target-specific dag combine patterns for the following nodes:
1004 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1005 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1006 setTargetDAGCombine(ISD::BUILD_VECTOR);
1007 setTargetDAGCombine(ISD::SELECT);
1008 setTargetDAGCombine(ISD::SHL);
1009 setTargetDAGCombine(ISD::SRA);
1010 setTargetDAGCombine(ISD::SRL);
1011 setTargetDAGCombine(ISD::OR);
1012 setTargetDAGCombine(ISD::STORE);
1013 setTargetDAGCombine(ISD::ZERO_EXTEND);
1014 if (Subtarget->is64Bit())
1015 setTargetDAGCombine(ISD::MUL);
1017 computeRegisterProperties();
1019 // FIXME: These should be based on subtarget info. Plus, the values should
1020 // be smaller when we are in optimizing for size mode.
1021 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1022 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1023 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1024 setPrefLoopAlignment(16);
1025 benefitFromCodePlacementOpt = true;
1029 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1034 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1035 /// the desired ByVal argument alignment.
1036 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1039 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1040 if (VTy->getBitWidth() == 128)
1042 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1043 unsigned EltAlign = 0;
1044 getMaxByValAlign(ATy->getElementType(), EltAlign);
1045 if (EltAlign > MaxAlign)
1046 MaxAlign = EltAlign;
1047 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1048 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1049 unsigned EltAlign = 0;
1050 getMaxByValAlign(STy->getElementType(i), EltAlign);
1051 if (EltAlign > MaxAlign)
1052 MaxAlign = EltAlign;
1060 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1061 /// function arguments in the caller parameter area. For X86, aggregates
1062 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1063 /// are at 4-byte boundaries.
1064 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1065 if (Subtarget->is64Bit()) {
1066 // Max of 8 and alignment of type.
1067 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1074 if (Subtarget->hasSSE1())
1075 getMaxByValAlign(Ty, Align);
1079 /// getOptimalMemOpType - Returns the target specific optimal type for load
1080 /// and store operations as a result of memset, memcpy, and memmove
1081 /// lowering. If DstAlign is zero that means it's safe to destination
1082 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1083 /// means there isn't a need to check it against alignment requirement,
1084 /// probably because the source does not need to be loaded. If
1085 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1086 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1087 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1088 /// constant so it does not need to be loaded.
1089 /// It returns EVT::Other if the type should be determined using generic
1090 /// target-independent logic.
1092 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1093 unsigned DstAlign, unsigned SrcAlign,
1094 bool NonScalarIntSafe,
1096 MachineFunction &MF) const {
1097 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1098 // linux. This is because the stack realignment code can't handle certain
1099 // cases like PR2962. This should be removed when PR2962 is fixed.
1100 const Function *F = MF.getFunction();
1101 if (NonScalarIntSafe &&
1102 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1104 (Subtarget->isUnalignedMemAccessFast() ||
1105 ((DstAlign == 0 || DstAlign >= 16) &&
1106 (SrcAlign == 0 || SrcAlign >= 16))) &&
1107 Subtarget->getStackAlignment() >= 16) {
1108 if (Subtarget->hasSSE2())
1110 if (Subtarget->hasSSE1())
1112 } else if (!MemcpyStrSrc && Size >= 8 &&
1113 !Subtarget->is64Bit() &&
1114 Subtarget->getStackAlignment() >= 8 &&
1115 Subtarget->hasSSE2()) {
1116 // Do not use f64 to lower memcpy if source is string constant. It's
1117 // better to use i32 to avoid the loads.
1121 if (Subtarget->is64Bit() && Size >= 8)
1126 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1127 /// current function. The returned value is a member of the
1128 /// MachineJumpTableInfo::JTEntryKind enum.
1129 unsigned X86TargetLowering::getJumpTableEncoding() const {
1130 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1132 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1133 Subtarget->isPICStyleGOT())
1134 return MachineJumpTableInfo::EK_Custom32;
1136 // Otherwise, use the normal jump table encoding heuristics.
1137 return TargetLowering::getJumpTableEncoding();
1140 /// getPICBaseSymbol - Return the X86-32 PIC base.
1142 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1143 MCContext &Ctx) const {
1144 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1145 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1146 Twine(MF->getFunctionNumber())+"$pb");
1151 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1152 const MachineBasicBlock *MBB,
1153 unsigned uid,MCContext &Ctx) const{
1154 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1155 Subtarget->isPICStyleGOT());
1156 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1158 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1159 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1162 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1164 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1165 SelectionDAG &DAG) const {
1166 if (!Subtarget->is64Bit())
1167 // This doesn't have DebugLoc associated with it, but is not really the
1168 // same as a Register.
1169 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1173 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1174 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1176 const MCExpr *X86TargetLowering::
1177 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1178 MCContext &Ctx) const {
1179 // X86-64 uses RIP relative addressing based on the jump table label.
1180 if (Subtarget->isPICStyleRIPRel())
1181 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1183 // Otherwise, the reference is relative to the PIC base.
1184 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1187 /// getFunctionAlignment - Return the Log2 alignment of this function.
1188 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1189 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1192 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1193 unsigned &Offset) const {
1194 if (!Subtarget->isTargetLinux())
1197 if (Subtarget->is64Bit()) {
1198 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1200 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1213 //===----------------------------------------------------------------------===//
1214 // Return Value Calling Convention Implementation
1215 //===----------------------------------------------------------------------===//
1217 #include "X86GenCallingConv.inc"
1220 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1221 const SmallVectorImpl<EVT> &OutTys,
1222 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1223 LLVMContext &Context) const {
1224 SmallVector<CCValAssign, 16> RVLocs;
1225 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1227 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1231 X86TargetLowering::LowerReturn(SDValue Chain,
1232 CallingConv::ID CallConv, bool isVarArg,
1233 const SmallVectorImpl<ISD::OutputArg> &Outs,
1234 DebugLoc dl, SelectionDAG &DAG) const {
1235 MachineFunction &MF = DAG.getMachineFunction();
1236 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1238 SmallVector<CCValAssign, 16> RVLocs;
1239 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1240 RVLocs, *DAG.getContext());
1241 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1243 // Add the regs to the liveout set for the function.
1244 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1245 for (unsigned i = 0; i != RVLocs.size(); ++i)
1246 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1247 MRI.addLiveOut(RVLocs[i].getLocReg());
1251 SmallVector<SDValue, 6> RetOps;
1252 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1253 // Operand #1 = Bytes To Pop
1254 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1257 // Copy the result values into the output registers.
1258 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1259 CCValAssign &VA = RVLocs[i];
1260 assert(VA.isRegLoc() && "Can only return in registers!");
1261 SDValue ValToCopy = Outs[i].Val;
1263 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1264 // the RET instruction and handled by the FP Stackifier.
1265 if (VA.getLocReg() == X86::ST0 ||
1266 VA.getLocReg() == X86::ST1) {
1267 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1268 // change the value to the FP stack register class.
1269 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1270 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1271 RetOps.push_back(ValToCopy);
1272 // Don't emit a copytoreg.
1276 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1277 // which is returned in RAX / RDX.
1278 if (Subtarget->is64Bit()) {
1279 EVT ValVT = ValToCopy.getValueType();
1280 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1281 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1282 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1283 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1287 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1288 Flag = Chain.getValue(1);
1291 // The x86-64 ABI for returning structs by value requires that we copy
1292 // the sret argument into %rax for the return. We saved the argument into
1293 // a virtual register in the entry block, so now we copy the value out
1295 if (Subtarget->is64Bit() &&
1296 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1297 MachineFunction &MF = DAG.getMachineFunction();
1298 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1299 unsigned Reg = FuncInfo->getSRetReturnReg();
1301 "SRetReturnReg should have been set in LowerFormalArguments().");
1302 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1304 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1305 Flag = Chain.getValue(1);
1307 // RAX now acts like a return value.
1308 MRI.addLiveOut(X86::RAX);
1311 RetOps[0] = Chain; // Update chain.
1313 // Add the flag if we have it.
1315 RetOps.push_back(Flag);
1317 return DAG.getNode(X86ISD::RET_FLAG, dl,
1318 MVT::Other, &RetOps[0], RetOps.size());
1321 /// LowerCallResult - Lower the result values of a call into the
1322 /// appropriate copies out of appropriate physical registers.
1325 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1326 CallingConv::ID CallConv, bool isVarArg,
1327 const SmallVectorImpl<ISD::InputArg> &Ins,
1328 DebugLoc dl, SelectionDAG &DAG,
1329 SmallVectorImpl<SDValue> &InVals) const {
1331 // Assign locations to each value returned by this call.
1332 SmallVector<CCValAssign, 16> RVLocs;
1333 bool Is64Bit = Subtarget->is64Bit();
1334 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1335 RVLocs, *DAG.getContext());
1336 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1338 // Copy all of the result registers out of their specified physreg.
1339 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1340 CCValAssign &VA = RVLocs[i];
1341 EVT CopyVT = VA.getValVT();
1343 // If this is x86-64, and we disabled SSE, we can't return FP values
1344 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1345 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1346 report_fatal_error("SSE register return with SSE disabled");
1349 // If this is a call to a function that returns an fp value on the floating
1350 // point stack, but where we prefer to use the value in xmm registers, copy
1351 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1352 if ((VA.getLocReg() == X86::ST0 ||
1353 VA.getLocReg() == X86::ST1) &&
1354 isScalarFPTypeInSSEReg(VA.getValVT())) {
1359 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1360 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1361 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1362 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1363 MVT::v2i64, InFlag).getValue(1);
1364 Val = Chain.getValue(0);
1365 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1366 Val, DAG.getConstant(0, MVT::i64));
1368 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1369 MVT::i64, InFlag).getValue(1);
1370 Val = Chain.getValue(0);
1372 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1374 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1375 CopyVT, InFlag).getValue(1);
1376 Val = Chain.getValue(0);
1378 InFlag = Chain.getValue(2);
1380 if (CopyVT != VA.getValVT()) {
1381 // Round the F80 the right size, which also moves to the appropriate xmm
1383 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1384 // This truncation won't change the value.
1385 DAG.getIntPtrConstant(1));
1388 InVals.push_back(Val);
1395 //===----------------------------------------------------------------------===//
1396 // C & StdCall & Fast Calling Convention implementation
1397 //===----------------------------------------------------------------------===//
1398 // StdCall calling convention seems to be standard for many Windows' API
1399 // routines and around. It differs from C calling convention just a little:
1400 // callee should clean up the stack, not caller. Symbols should be also
1401 // decorated in some fancy way :) It doesn't support any vector arguments.
1402 // For info on fast calling convention see Fast Calling Convention (tail call)
1403 // implementation LowerX86_32FastCCCallTo.
1405 /// CallIsStructReturn - Determines whether a call uses struct return
1407 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1411 return Outs[0].Flags.isSRet();
1414 /// ArgsAreStructReturn - Determines whether a function uses struct
1415 /// return semantics.
1417 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1421 return Ins[0].Flags.isSRet();
1424 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1425 /// given CallingConvention value.
1426 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1427 if (Subtarget->is64Bit()) {
1428 if (CC == CallingConv::GHC)
1429 return CC_X86_64_GHC;
1430 else if (Subtarget->isTargetWin64())
1431 return CC_X86_Win64_C;
1436 if (CC == CallingConv::X86_FastCall)
1437 return CC_X86_32_FastCall;
1438 else if (CC == CallingConv::X86_ThisCall)
1439 return CC_X86_32_ThisCall;
1440 else if (CC == CallingConv::Fast)
1441 return CC_X86_32_FastCC;
1442 else if (CC == CallingConv::GHC)
1443 return CC_X86_32_GHC;
1448 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1449 /// by "Src" to address "Dst" with size and alignment information specified by
1450 /// the specific parameter attribute. The copy will be passed as a byval
1451 /// function parameter.
1453 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1454 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1456 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1457 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1458 /*isVolatile*/false, /*AlwaysInline=*/true,
1462 /// IsTailCallConvention - Return true if the calling convention is one that
1463 /// supports tail call optimization.
1464 static bool IsTailCallConvention(CallingConv::ID CC) {
1465 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1468 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1469 /// a tailcall target by changing its ABI.
1470 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1471 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1475 X86TargetLowering::LowerMemArgument(SDValue Chain,
1476 CallingConv::ID CallConv,
1477 const SmallVectorImpl<ISD::InputArg> &Ins,
1478 DebugLoc dl, SelectionDAG &DAG,
1479 const CCValAssign &VA,
1480 MachineFrameInfo *MFI,
1482 // Create the nodes corresponding to a load from this parameter slot.
1483 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1484 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1485 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1488 // If value is passed by pointer we have address passed instead of the value
1490 if (VA.getLocInfo() == CCValAssign::Indirect)
1491 ValVT = VA.getLocVT();
1493 ValVT = VA.getValVT();
1495 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1496 // changed with more analysis.
1497 // In case of tail call optimization mark all arguments mutable. Since they
1498 // could be overwritten by lowering of arguments in case of a tail call.
1499 if (Flags.isByVal()) {
1500 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1501 VA.getLocMemOffset(), isImmutable);
1502 return DAG.getFrameIndex(FI, getPointerTy());
1504 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1505 VA.getLocMemOffset(), isImmutable);
1506 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1507 return DAG.getLoad(ValVT, dl, Chain, FIN,
1508 PseudoSourceValue::getFixedStack(FI), 0,
1514 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1515 CallingConv::ID CallConv,
1517 const SmallVectorImpl<ISD::InputArg> &Ins,
1520 SmallVectorImpl<SDValue> &InVals)
1522 MachineFunction &MF = DAG.getMachineFunction();
1523 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1525 const Function* Fn = MF.getFunction();
1526 if (Fn->hasExternalLinkage() &&
1527 Subtarget->isTargetCygMing() &&
1528 Fn->getName() == "main")
1529 FuncInfo->setForceFramePointer(true);
1531 MachineFrameInfo *MFI = MF.getFrameInfo();
1532 bool Is64Bit = Subtarget->is64Bit();
1533 bool IsWin64 = Subtarget->isTargetWin64();
1535 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1536 "Var args not supported with calling convention fastcc or ghc");
1538 // Assign locations to all of the incoming arguments.
1539 SmallVector<CCValAssign, 16> ArgLocs;
1540 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1541 ArgLocs, *DAG.getContext());
1542 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1544 unsigned LastVal = ~0U;
1546 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1547 CCValAssign &VA = ArgLocs[i];
1548 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1550 assert(VA.getValNo() != LastVal &&
1551 "Don't support value assigned to multiple locs yet");
1552 LastVal = VA.getValNo();
1554 if (VA.isRegLoc()) {
1555 EVT RegVT = VA.getLocVT();
1556 TargetRegisterClass *RC = NULL;
1557 if (RegVT == MVT::i32)
1558 RC = X86::GR32RegisterClass;
1559 else if (Is64Bit && RegVT == MVT::i64)
1560 RC = X86::GR64RegisterClass;
1561 else if (RegVT == MVT::f32)
1562 RC = X86::FR32RegisterClass;
1563 else if (RegVT == MVT::f64)
1564 RC = X86::FR64RegisterClass;
1565 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1566 RC = X86::VR128RegisterClass;
1567 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1568 RC = X86::VR64RegisterClass;
1570 llvm_unreachable("Unknown argument type!");
1572 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1573 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1575 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1576 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1578 if (VA.getLocInfo() == CCValAssign::SExt)
1579 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1580 DAG.getValueType(VA.getValVT()));
1581 else if (VA.getLocInfo() == CCValAssign::ZExt)
1582 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1583 DAG.getValueType(VA.getValVT()));
1584 else if (VA.getLocInfo() == CCValAssign::BCvt)
1585 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1587 if (VA.isExtInLoc()) {
1588 // Handle MMX values passed in XMM regs.
1589 if (RegVT.isVector()) {
1590 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1591 ArgValue, DAG.getConstant(0, MVT::i64));
1592 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1594 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1597 assert(VA.isMemLoc());
1598 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1601 // If value is passed via pointer - do a load.
1602 if (VA.getLocInfo() == CCValAssign::Indirect)
1603 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1606 InVals.push_back(ArgValue);
1609 // The x86-64 ABI for returning structs by value requires that we copy
1610 // the sret argument into %rax for the return. Save the argument into
1611 // a virtual register so that we can access it from the return points.
1612 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1613 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1614 unsigned Reg = FuncInfo->getSRetReturnReg();
1616 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1617 FuncInfo->setSRetReturnReg(Reg);
1619 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1620 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1623 unsigned StackSize = CCInfo.getNextStackOffset();
1624 // Align stack specially for tail calls.
1625 if (FuncIsMadeTailCallSafe(CallConv))
1626 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1628 // If the function takes variable number of arguments, make a frame index for
1629 // the start of the first vararg value... for expansion of llvm.va_start.
1631 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1632 CallConv != CallingConv::X86_ThisCall)) {
1633 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1636 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1638 // FIXME: We should really autogenerate these arrays
1639 static const unsigned GPR64ArgRegsWin64[] = {
1640 X86::RCX, X86::RDX, X86::R8, X86::R9
1642 static const unsigned XMMArgRegsWin64[] = {
1643 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1645 static const unsigned GPR64ArgRegs64Bit[] = {
1646 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1648 static const unsigned XMMArgRegs64Bit[] = {
1649 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1650 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1652 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1655 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1656 GPR64ArgRegs = GPR64ArgRegsWin64;
1657 XMMArgRegs = XMMArgRegsWin64;
1659 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1660 GPR64ArgRegs = GPR64ArgRegs64Bit;
1661 XMMArgRegs = XMMArgRegs64Bit;
1663 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1665 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1668 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1669 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1670 "SSE register cannot be used when SSE is disabled!");
1671 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1672 "SSE register cannot be used when SSE is disabled!");
1673 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1674 // Kernel mode asks for SSE to be disabled, so don't push them
1676 TotalNumXMMRegs = 0;
1678 // For X86-64, if there are vararg parameters that are passed via
1679 // registers, then we must store them to their spots on the stack so they
1680 // may be loaded by deferencing the result of va_next.
1681 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1682 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1683 FuncInfo->setRegSaveFrameIndex(
1684 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1687 // Store the integer parameter registers.
1688 SmallVector<SDValue, 8> MemOps;
1689 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1691 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1692 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1693 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1694 DAG.getIntPtrConstant(Offset));
1695 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1696 X86::GR64RegisterClass);
1697 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1699 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1700 PseudoSourceValue::getFixedStack(
1701 FuncInfo->getRegSaveFrameIndex()),
1702 Offset, false, false, 0);
1703 MemOps.push_back(Store);
1707 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1708 // Now store the XMM (fp + vector) parameter registers.
1709 SmallVector<SDValue, 11> SaveXMMOps;
1710 SaveXMMOps.push_back(Chain);
1712 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1713 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1714 SaveXMMOps.push_back(ALVal);
1716 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1717 FuncInfo->getRegSaveFrameIndex()));
1718 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1719 FuncInfo->getVarArgsFPOffset()));
1721 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1722 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1723 X86::VR128RegisterClass);
1724 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1725 SaveXMMOps.push_back(Val);
1727 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1729 &SaveXMMOps[0], SaveXMMOps.size()));
1732 if (!MemOps.empty())
1733 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1734 &MemOps[0], MemOps.size());
1738 // Some CCs need callee pop.
1739 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1740 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1742 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1743 // If this is an sret function, the return should pop the hidden pointer.
1744 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1745 FuncInfo->setBytesToPopOnReturn(4);
1749 // RegSaveFrameIndex is X86-64 only.
1750 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1751 if (CallConv == CallingConv::X86_FastCall ||
1752 CallConv == CallingConv::X86_ThisCall)
1753 // fastcc functions can't have varargs.
1754 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1761 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1762 SDValue StackPtr, SDValue Arg,
1763 DebugLoc dl, SelectionDAG &DAG,
1764 const CCValAssign &VA,
1765 ISD::ArgFlagsTy Flags) const {
1766 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1767 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1768 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1769 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1770 if (Flags.isByVal()) {
1771 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1773 return DAG.getStore(Chain, dl, Arg, PtrOff,
1774 PseudoSourceValue::getStack(), LocMemOffset,
1778 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1779 /// optimization is performed and it is required.
1781 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1782 SDValue &OutRetAddr, SDValue Chain,
1783 bool IsTailCall, bool Is64Bit,
1784 int FPDiff, DebugLoc dl) const {
1785 // Adjust the Return address stack slot.
1786 EVT VT = getPointerTy();
1787 OutRetAddr = getReturnAddressFrameIndex(DAG);
1789 // Load the "old" Return address.
1790 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1791 return SDValue(OutRetAddr.getNode(), 1);
1794 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1795 /// optimization is performed and it is required (FPDiff!=0).
1797 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1798 SDValue Chain, SDValue RetAddrFrIdx,
1799 bool Is64Bit, int FPDiff, DebugLoc dl) {
1800 // Store the return address to the appropriate stack slot.
1801 if (!FPDiff) return Chain;
1802 // Calculate the new stack slot for the return address.
1803 int SlotSize = Is64Bit ? 8 : 4;
1804 int NewReturnAddrFI =
1805 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1806 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1807 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1808 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1809 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1815 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1816 CallingConv::ID CallConv, bool isVarArg,
1818 const SmallVectorImpl<ISD::OutputArg> &Outs,
1819 const SmallVectorImpl<ISD::InputArg> &Ins,
1820 DebugLoc dl, SelectionDAG &DAG,
1821 SmallVectorImpl<SDValue> &InVals) const {
1822 MachineFunction &MF = DAG.getMachineFunction();
1823 bool Is64Bit = Subtarget->is64Bit();
1824 bool IsStructRet = CallIsStructReturn(Outs);
1825 bool IsSibcall = false;
1828 // Check if it's really possible to do a tail call.
1829 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1830 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1833 // Sibcalls are automatically detected tailcalls which do not require
1835 if (!GuaranteedTailCallOpt && isTailCall)
1842 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1843 "Var args not supported with calling convention fastcc or ghc");
1845 // Analyze operands of the call, assigning locations to each operand.
1846 SmallVector<CCValAssign, 16> ArgLocs;
1847 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1848 ArgLocs, *DAG.getContext());
1849 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1851 // Get a count of how many bytes are to be pushed on the stack.
1852 unsigned NumBytes = CCInfo.getNextStackOffset();
1854 // This is a sibcall. The memory operands are available in caller's
1855 // own caller's stack.
1857 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1858 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1861 if (isTailCall && !IsSibcall) {
1862 // Lower arguments at fp - stackoffset + fpdiff.
1863 unsigned NumBytesCallerPushed =
1864 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1865 FPDiff = NumBytesCallerPushed - NumBytes;
1867 // Set the delta of movement of the returnaddr stackslot.
1868 // But only set if delta is greater than previous delta.
1869 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1870 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1874 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1876 SDValue RetAddrFrIdx;
1877 // Load return adress for tail calls.
1878 if (isTailCall && FPDiff)
1879 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1880 Is64Bit, FPDiff, dl);
1882 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1883 SmallVector<SDValue, 8> MemOpChains;
1886 // Walk the register/memloc assignments, inserting copies/loads. In the case
1887 // of tail call optimization arguments are handle later.
1888 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1889 CCValAssign &VA = ArgLocs[i];
1890 EVT RegVT = VA.getLocVT();
1891 SDValue Arg = Outs[i].Val;
1892 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1893 bool isByVal = Flags.isByVal();
1895 // Promote the value if needed.
1896 switch (VA.getLocInfo()) {
1897 default: llvm_unreachable("Unknown loc info!");
1898 case CCValAssign::Full: break;
1899 case CCValAssign::SExt:
1900 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1902 case CCValAssign::ZExt:
1903 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1905 case CCValAssign::AExt:
1906 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1907 // Special case: passing MMX values in XMM registers.
1908 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1909 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1910 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1912 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1914 case CCValAssign::BCvt:
1915 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1917 case CCValAssign::Indirect: {
1918 // Store the argument.
1919 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1920 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1921 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1922 PseudoSourceValue::getFixedStack(FI), 0,
1929 if (VA.isRegLoc()) {
1930 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1931 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1932 assert(VA.isMemLoc());
1933 if (StackPtr.getNode() == 0)
1934 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1935 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1936 dl, DAG, VA, Flags));
1940 if (!MemOpChains.empty())
1941 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1942 &MemOpChains[0], MemOpChains.size());
1944 // Build a sequence of copy-to-reg nodes chained together with token chain
1945 // and flag operands which copy the outgoing args into registers.
1947 // Tail call byval lowering might overwrite argument registers so in case of
1948 // tail call optimization the copies to registers are lowered later.
1950 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1951 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1952 RegsToPass[i].second, InFlag);
1953 InFlag = Chain.getValue(1);
1956 if (Subtarget->isPICStyleGOT()) {
1957 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1960 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1961 DAG.getNode(X86ISD::GlobalBaseReg,
1962 DebugLoc(), getPointerTy()),
1964 InFlag = Chain.getValue(1);
1966 // If we are tail calling and generating PIC/GOT style code load the
1967 // address of the callee into ECX. The value in ecx is used as target of
1968 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1969 // for tail calls on PIC/GOT architectures. Normally we would just put the
1970 // address of GOT into ebx and then call target@PLT. But for tail calls
1971 // ebx would be restored (since ebx is callee saved) before jumping to the
1974 // Note: The actual moving to ECX is done further down.
1975 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1976 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1977 !G->getGlobal()->hasProtectedVisibility())
1978 Callee = LowerGlobalAddress(Callee, DAG);
1979 else if (isa<ExternalSymbolSDNode>(Callee))
1980 Callee = LowerExternalSymbol(Callee, DAG);
1984 if (Is64Bit && isVarArg) {
1985 // From AMD64 ABI document:
1986 // For calls that may call functions that use varargs or stdargs
1987 // (prototype-less calls or calls to functions containing ellipsis (...) in
1988 // the declaration) %al is used as hidden argument to specify the number
1989 // of SSE registers used. The contents of %al do not need to match exactly
1990 // the number of registers, but must be an ubound on the number of SSE
1991 // registers used and is in the range 0 - 8 inclusive.
1993 // FIXME: Verify this on Win64
1994 // Count the number of XMM registers allocated.
1995 static const unsigned XMMArgRegs[] = {
1996 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1997 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1999 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2000 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2001 && "SSE registers cannot be used when SSE is disabled");
2003 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2004 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2005 InFlag = Chain.getValue(1);
2009 // For tail calls lower the arguments to the 'real' stack slot.
2011 // Force all the incoming stack arguments to be loaded from the stack
2012 // before any new outgoing arguments are stored to the stack, because the
2013 // outgoing stack slots may alias the incoming argument stack slots, and
2014 // the alias isn't otherwise explicit. This is slightly more conservative
2015 // than necessary, because it means that each store effectively depends
2016 // on every argument instead of just those arguments it would clobber.
2017 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2019 SmallVector<SDValue, 8> MemOpChains2;
2022 // Do not flag preceeding copytoreg stuff together with the following stuff.
2024 if (GuaranteedTailCallOpt) {
2025 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2026 CCValAssign &VA = ArgLocs[i];
2029 assert(VA.isMemLoc());
2030 SDValue Arg = Outs[i].Val;
2031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2032 // Create frame index.
2033 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2034 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2035 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2036 FIN = DAG.getFrameIndex(FI, getPointerTy());
2038 if (Flags.isByVal()) {
2039 // Copy relative to framepointer.
2040 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2041 if (StackPtr.getNode() == 0)
2042 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2044 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2046 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2050 // Store relative to framepointer.
2051 MemOpChains2.push_back(
2052 DAG.getStore(ArgChain, dl, Arg, FIN,
2053 PseudoSourceValue::getFixedStack(FI), 0,
2059 if (!MemOpChains2.empty())
2060 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2061 &MemOpChains2[0], MemOpChains2.size());
2063 // Copy arguments to their registers.
2064 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2065 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2066 RegsToPass[i].second, InFlag);
2067 InFlag = Chain.getValue(1);
2071 // Store the return address to the appropriate stack slot.
2072 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2076 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2077 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2078 // In the 64-bit large code model, we have to make all calls
2079 // through a register, since the call instruction's 32-bit
2080 // pc-relative offset may not be large enough to hold the whole
2082 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2083 // If the callee is a GlobalAddress node (quite common, every direct call
2084 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2087 // We should use extra load for direct calls to dllimported functions in
2089 const GlobalValue *GV = G->getGlobal();
2090 if (!GV->hasDLLImportLinkage()) {
2091 unsigned char OpFlags = 0;
2093 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2094 // external symbols most go through the PLT in PIC mode. If the symbol
2095 // has hidden or protected visibility, or if it is static or local, then
2096 // we don't need to use the PLT - we can directly call it.
2097 if (Subtarget->isTargetELF() &&
2098 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2099 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2100 OpFlags = X86II::MO_PLT;
2101 } else if (Subtarget->isPICStyleStubAny() &&
2102 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2103 Subtarget->getDarwinVers() < 9) {
2104 // PC-relative references to external symbols should go through $stub,
2105 // unless we're building with the leopard linker or later, which
2106 // automatically synthesizes these stubs.
2107 OpFlags = X86II::MO_DARWIN_STUB;
2110 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2111 G->getOffset(), OpFlags);
2113 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2114 unsigned char OpFlags = 0;
2116 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2117 // symbols should go through the PLT.
2118 if (Subtarget->isTargetELF() &&
2119 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2120 OpFlags = X86II::MO_PLT;
2121 } else if (Subtarget->isPICStyleStubAny() &&
2122 Subtarget->getDarwinVers() < 9) {
2123 // PC-relative references to external symbols should go through $stub,
2124 // unless we're building with the leopard linker or later, which
2125 // automatically synthesizes these stubs.
2126 OpFlags = X86II::MO_DARWIN_STUB;
2129 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2133 // Returns a chain & a flag for retval copy to use.
2134 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2135 SmallVector<SDValue, 8> Ops;
2137 if (!IsSibcall && isTailCall) {
2138 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2139 DAG.getIntPtrConstant(0, true), InFlag);
2140 InFlag = Chain.getValue(1);
2143 Ops.push_back(Chain);
2144 Ops.push_back(Callee);
2147 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2149 // Add argument registers to the end of the list so that they are known live
2151 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2152 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2153 RegsToPass[i].second.getValueType()));
2155 // Add an implicit use GOT pointer in EBX.
2156 if (!isTailCall && Subtarget->isPICStyleGOT())
2157 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2159 // Add an implicit use of AL for x86 vararg functions.
2160 if (Is64Bit && isVarArg)
2161 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2163 if (InFlag.getNode())
2164 Ops.push_back(InFlag);
2168 //// If this is the first return lowered for this function, add the regs
2169 //// to the liveout set for the function.
2170 // This isn't right, although it's probably harmless on x86; liveouts
2171 // should be computed from returns not tail calls. Consider a void
2172 // function making a tail call to a function returning int.
2173 return DAG.getNode(X86ISD::TC_RETURN, dl,
2174 NodeTys, &Ops[0], Ops.size());
2177 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2178 InFlag = Chain.getValue(1);
2180 // Create the CALLSEQ_END node.
2181 unsigned NumBytesForCalleeToPush;
2182 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2183 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2184 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2185 // If this is a call to a struct-return function, the callee
2186 // pops the hidden struct pointer, so we have to push it back.
2187 // This is common for Darwin/X86, Linux & Mingw32 targets.
2188 NumBytesForCalleeToPush = 4;
2190 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2192 // Returns a flag for retval copy to use.
2194 Chain = DAG.getCALLSEQ_END(Chain,
2195 DAG.getIntPtrConstant(NumBytes, true),
2196 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2199 InFlag = Chain.getValue(1);
2202 // Handle result values, copying them out of physregs into vregs that we
2204 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2205 Ins, dl, DAG, InVals);
2209 //===----------------------------------------------------------------------===//
2210 // Fast Calling Convention (tail call) implementation
2211 //===----------------------------------------------------------------------===//
2213 // Like std call, callee cleans arguments, convention except that ECX is
2214 // reserved for storing the tail called function address. Only 2 registers are
2215 // free for argument passing (inreg). Tail call optimization is performed
2217 // * tailcallopt is enabled
2218 // * caller/callee are fastcc
2219 // On X86_64 architecture with GOT-style position independent code only local
2220 // (within module) calls are supported at the moment.
2221 // To keep the stack aligned according to platform abi the function
2222 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2223 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2224 // If a tail called function callee has more arguments than the caller the
2225 // caller needs to make sure that there is room to move the RETADDR to. This is
2226 // achieved by reserving an area the size of the argument delta right after the
2227 // original REtADDR, but before the saved framepointer or the spilled registers
2228 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2240 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2241 /// for a 16 byte align requirement.
2243 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2244 SelectionDAG& DAG) const {
2245 MachineFunction &MF = DAG.getMachineFunction();
2246 const TargetMachine &TM = MF.getTarget();
2247 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2248 unsigned StackAlignment = TFI.getStackAlignment();
2249 uint64_t AlignMask = StackAlignment - 1;
2250 int64_t Offset = StackSize;
2251 uint64_t SlotSize = TD->getPointerSize();
2252 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2253 // Number smaller than 12 so just add the difference.
2254 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2256 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2257 Offset = ((~AlignMask) & Offset) + StackAlignment +
2258 (StackAlignment-SlotSize);
2263 /// MatchingStackOffset - Return true if the given stack call argument is
2264 /// already available in the same position (relatively) of the caller's
2265 /// incoming argument stack.
2267 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2268 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2269 const X86InstrInfo *TII) {
2270 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2272 if (Arg.getOpcode() == ISD::CopyFromReg) {
2273 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2274 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2276 MachineInstr *Def = MRI->getVRegDef(VR);
2279 if (!Flags.isByVal()) {
2280 if (!TII->isLoadFromStackSlot(Def, FI))
2283 unsigned Opcode = Def->getOpcode();
2284 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2285 Def->getOperand(1).isFI()) {
2286 FI = Def->getOperand(1).getIndex();
2287 Bytes = Flags.getByValSize();
2291 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2292 if (Flags.isByVal())
2293 // ByVal argument is passed in as a pointer but it's now being
2294 // dereferenced. e.g.
2295 // define @foo(%struct.X* %A) {
2296 // tail call @bar(%struct.X* byval %A)
2299 SDValue Ptr = Ld->getBasePtr();
2300 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2303 FI = FINode->getIndex();
2307 assert(FI != INT_MAX);
2308 if (!MFI->isFixedObjectIndex(FI))
2310 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2313 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2314 /// for tail call optimization. Targets which want to do tail call
2315 /// optimization should implement this function.
2317 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2318 CallingConv::ID CalleeCC,
2320 bool isCalleeStructRet,
2321 bool isCallerStructRet,
2322 const SmallVectorImpl<ISD::OutputArg> &Outs,
2323 const SmallVectorImpl<ISD::InputArg> &Ins,
2324 SelectionDAG& DAG) const {
2325 if (!IsTailCallConvention(CalleeCC) &&
2326 CalleeCC != CallingConv::C)
2329 // If -tailcallopt is specified, make fastcc functions tail-callable.
2330 const MachineFunction &MF = DAG.getMachineFunction();
2331 const Function *CallerF = DAG.getMachineFunction().getFunction();
2332 CallingConv::ID CallerCC = CallerF->getCallingConv();
2333 bool CCMatch = CallerCC == CalleeCC;
2335 if (GuaranteedTailCallOpt) {
2336 if (IsTailCallConvention(CalleeCC) && CCMatch)
2341 // Look for obvious safe cases to perform tail call optimization that do not
2342 // require ABI changes. This is what gcc calls sibcall.
2344 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2345 // emit a special epilogue.
2346 if (RegInfo->needsStackRealignment(MF))
2349 // Do not sibcall optimize vararg calls unless the call site is not passing any
2351 if (isVarArg && !Outs.empty())
2354 // Also avoid sibcall optimization if either caller or callee uses struct
2355 // return semantics.
2356 if (isCalleeStructRet || isCallerStructRet)
2359 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2360 // Therefore if it's not used by the call it is not safe to optimize this into
2362 bool Unused = false;
2363 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2370 SmallVector<CCValAssign, 16> RVLocs;
2371 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2372 RVLocs, *DAG.getContext());
2373 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2374 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2375 CCValAssign &VA = RVLocs[i];
2376 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2381 // If the calling conventions do not match, then we'd better make sure the
2382 // results are returned in the same way as what the caller expects.
2384 SmallVector<CCValAssign, 16> RVLocs1;
2385 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2386 RVLocs1, *DAG.getContext());
2387 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2389 SmallVector<CCValAssign, 16> RVLocs2;
2390 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2391 RVLocs2, *DAG.getContext());
2392 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2394 if (RVLocs1.size() != RVLocs2.size())
2396 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2397 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2399 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2401 if (RVLocs1[i].isRegLoc()) {
2402 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2405 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2411 // If the callee takes no arguments then go on to check the results of the
2413 if (!Outs.empty()) {
2414 // Check if stack adjustment is needed. For now, do not do this if any
2415 // argument is passed on the stack.
2416 SmallVector<CCValAssign, 16> ArgLocs;
2417 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2418 ArgLocs, *DAG.getContext());
2419 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2420 if (CCInfo.getNextStackOffset()) {
2421 MachineFunction &MF = DAG.getMachineFunction();
2422 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2424 if (Subtarget->isTargetWin64())
2425 // Win64 ABI has additional complications.
2428 // Check if the arguments are already laid out in the right way as
2429 // the caller's fixed stack objects.
2430 MachineFrameInfo *MFI = MF.getFrameInfo();
2431 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2432 const X86InstrInfo *TII =
2433 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2434 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2435 CCValAssign &VA = ArgLocs[i];
2436 SDValue Arg = Outs[i].Val;
2437 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2438 if (VA.getLocInfo() == CCValAssign::Indirect)
2440 if (!VA.isRegLoc()) {
2441 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2448 // If the tailcall address may be in a register, then make sure it's
2449 // possible to register allocate for it. In 32-bit, the call address can
2450 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2451 // callee-saved registers are restored. In 64-bit, it's RAX, RCX, RDX, RSI,
2452 // RDI, R8, R9, R11.
2453 if (!isa<GlobalAddressSDNode>(Callee) &&
2454 !isa<ExternalSymbolSDNode>(Callee)) {
2455 unsigned Limit = Subtarget->is64Bit() ? 8 : 3;
2456 unsigned NumInRegs = 0;
2457 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2458 CCValAssign &VA = ArgLocs[i];
2459 if (VA.isRegLoc()) {
2460 if (++NumInRegs == Limit)
2471 X86TargetLowering::createFastISel(MachineFunction &mf,
2472 DenseMap<const Value *, unsigned> &vm,
2473 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2474 DenseMap<const AllocaInst *, int> &am,
2475 std::vector<std::pair<MachineInstr*, unsigned> > &pn
2477 , SmallSet<const Instruction *, 8> &cil
2480 return X86::createFastISel(mf, vm, bm, am, pn
2488 //===----------------------------------------------------------------------===//
2489 // Other Lowering Hooks
2490 //===----------------------------------------------------------------------===//
2493 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2494 MachineFunction &MF = DAG.getMachineFunction();
2495 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2496 int ReturnAddrIndex = FuncInfo->getRAIndex();
2498 if (ReturnAddrIndex == 0) {
2499 // Set up a frame object for the return address.
2500 uint64_t SlotSize = TD->getPointerSize();
2501 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2503 FuncInfo->setRAIndex(ReturnAddrIndex);
2506 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2510 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2511 bool hasSymbolicDisplacement) {
2512 // Offset should fit into 32 bit immediate field.
2513 if (!isInt<32>(Offset))
2516 // If we don't have a symbolic displacement - we don't have any extra
2518 if (!hasSymbolicDisplacement)
2521 // FIXME: Some tweaks might be needed for medium code model.
2522 if (M != CodeModel::Small && M != CodeModel::Kernel)
2525 // For small code model we assume that latest object is 16MB before end of 31
2526 // bits boundary. We may also accept pretty large negative constants knowing
2527 // that all objects are in the positive half of address space.
2528 if (M == CodeModel::Small && Offset < 16*1024*1024)
2531 // For kernel code model we know that all object resist in the negative half
2532 // of 32bits address space. We may not accept negative offsets, since they may
2533 // be just off and we may accept pretty large positive ones.
2534 if (M == CodeModel::Kernel && Offset > 0)
2540 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2541 /// specific condition code, returning the condition code and the LHS/RHS of the
2542 /// comparison to make.
2543 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2544 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2546 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2547 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2548 // X > -1 -> X == 0, jump !sign.
2549 RHS = DAG.getConstant(0, RHS.getValueType());
2550 return X86::COND_NS;
2551 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2552 // X < 0 -> X == 0, jump on sign.
2554 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2556 RHS = DAG.getConstant(0, RHS.getValueType());
2557 return X86::COND_LE;
2561 switch (SetCCOpcode) {
2562 default: llvm_unreachable("Invalid integer condition!");
2563 case ISD::SETEQ: return X86::COND_E;
2564 case ISD::SETGT: return X86::COND_G;
2565 case ISD::SETGE: return X86::COND_GE;
2566 case ISD::SETLT: return X86::COND_L;
2567 case ISD::SETLE: return X86::COND_LE;
2568 case ISD::SETNE: return X86::COND_NE;
2569 case ISD::SETULT: return X86::COND_B;
2570 case ISD::SETUGT: return X86::COND_A;
2571 case ISD::SETULE: return X86::COND_BE;
2572 case ISD::SETUGE: return X86::COND_AE;
2576 // First determine if it is required or is profitable to flip the operands.
2578 // If LHS is a foldable load, but RHS is not, flip the condition.
2579 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2580 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2581 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2582 std::swap(LHS, RHS);
2585 switch (SetCCOpcode) {
2591 std::swap(LHS, RHS);
2595 // On a floating point condition, the flags are set as follows:
2597 // 0 | 0 | 0 | X > Y
2598 // 0 | 0 | 1 | X < Y
2599 // 1 | 0 | 0 | X == Y
2600 // 1 | 1 | 1 | unordered
2601 switch (SetCCOpcode) {
2602 default: llvm_unreachable("Condcode should be pre-legalized away");
2604 case ISD::SETEQ: return X86::COND_E;
2605 case ISD::SETOLT: // flipped
2607 case ISD::SETGT: return X86::COND_A;
2608 case ISD::SETOLE: // flipped
2610 case ISD::SETGE: return X86::COND_AE;
2611 case ISD::SETUGT: // flipped
2613 case ISD::SETLT: return X86::COND_B;
2614 case ISD::SETUGE: // flipped
2616 case ISD::SETLE: return X86::COND_BE;
2618 case ISD::SETNE: return X86::COND_NE;
2619 case ISD::SETUO: return X86::COND_P;
2620 case ISD::SETO: return X86::COND_NP;
2622 case ISD::SETUNE: return X86::COND_INVALID;
2626 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2627 /// code. Current x86 isa includes the following FP cmov instructions:
2628 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2629 static bool hasFPCMov(unsigned X86CC) {
2645 /// isFPImmLegal - Returns true if the target can instruction select the
2646 /// specified FP immediate natively. If false, the legalizer will
2647 /// materialize the FP immediate as a load from a constant pool.
2648 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2649 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2650 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2656 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2657 /// the specified range (L, H].
2658 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2659 return (Val < 0) || (Val >= Low && Val < Hi);
2662 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2663 /// specified value.
2664 static bool isUndefOrEqual(int Val, int CmpVal) {
2665 if (Val < 0 || Val == CmpVal)
2670 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2671 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2672 /// the second operand.
2673 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2674 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2675 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2676 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2677 return (Mask[0] < 2 && Mask[1] < 2);
2681 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2682 SmallVector<int, 8> M;
2684 return ::isPSHUFDMask(M, N->getValueType(0));
2687 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2688 /// is suitable for input to PSHUFHW.
2689 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2690 if (VT != MVT::v8i16)
2693 // Lower quadword copied in order or undef.
2694 for (int i = 0; i != 4; ++i)
2695 if (Mask[i] >= 0 && Mask[i] != i)
2698 // Upper quadword shuffled.
2699 for (int i = 4; i != 8; ++i)
2700 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2706 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2707 SmallVector<int, 8> M;
2709 return ::isPSHUFHWMask(M, N->getValueType(0));
2712 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2713 /// is suitable for input to PSHUFLW.
2714 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2715 if (VT != MVT::v8i16)
2718 // Upper quadword copied in order.
2719 for (int i = 4; i != 8; ++i)
2720 if (Mask[i] >= 0 && Mask[i] != i)
2723 // Lower quadword shuffled.
2724 for (int i = 0; i != 4; ++i)
2731 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2732 SmallVector<int, 8> M;
2734 return ::isPSHUFLWMask(M, N->getValueType(0));
2737 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2738 /// is suitable for input to PALIGNR.
2739 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2741 int i, e = VT.getVectorNumElements();
2743 // Do not handle v2i64 / v2f64 shuffles with palignr.
2744 if (e < 4 || !hasSSSE3)
2747 for (i = 0; i != e; ++i)
2751 // All undef, not a palignr.
2755 // Determine if it's ok to perform a palignr with only the LHS, since we
2756 // don't have access to the actual shuffle elements to see if RHS is undef.
2757 bool Unary = Mask[i] < (int)e;
2758 bool NeedsUnary = false;
2760 int s = Mask[i] - i;
2762 // Check the rest of the elements to see if they are consecutive.
2763 for (++i; i != e; ++i) {
2768 Unary = Unary && (m < (int)e);
2769 NeedsUnary = NeedsUnary || (m < s);
2771 if (NeedsUnary && !Unary)
2773 if (Unary && m != ((s+i) & (e-1)))
2775 if (!Unary && m != (s+i))
2781 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2782 SmallVector<int, 8> M;
2784 return ::isPALIGNRMask(M, N->getValueType(0), true);
2787 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2788 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2789 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2790 int NumElems = VT.getVectorNumElements();
2791 if (NumElems != 2 && NumElems != 4)
2794 int Half = NumElems / 2;
2795 for (int i = 0; i < Half; ++i)
2796 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2798 for (int i = Half; i < NumElems; ++i)
2799 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2805 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2806 SmallVector<int, 8> M;
2808 return ::isSHUFPMask(M, N->getValueType(0));
2811 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2812 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2813 /// half elements to come from vector 1 (which would equal the dest.) and
2814 /// the upper half to come from vector 2.
2815 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2816 int NumElems = VT.getVectorNumElements();
2818 if (NumElems != 2 && NumElems != 4)
2821 int Half = NumElems / 2;
2822 for (int i = 0; i < Half; ++i)
2823 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2825 for (int i = Half; i < NumElems; ++i)
2826 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2831 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2832 SmallVector<int, 8> M;
2834 return isCommutedSHUFPMask(M, N->getValueType(0));
2837 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2838 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2839 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2840 if (N->getValueType(0).getVectorNumElements() != 4)
2843 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2844 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2845 isUndefOrEqual(N->getMaskElt(1), 7) &&
2846 isUndefOrEqual(N->getMaskElt(2), 2) &&
2847 isUndefOrEqual(N->getMaskElt(3), 3);
2850 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2851 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2853 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2854 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2859 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2860 isUndefOrEqual(N->getMaskElt(1), 3) &&
2861 isUndefOrEqual(N->getMaskElt(2), 2) &&
2862 isUndefOrEqual(N->getMaskElt(3), 3);
2865 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2866 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2867 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2868 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2870 if (NumElems != 2 && NumElems != 4)
2873 for (unsigned i = 0; i < NumElems/2; ++i)
2874 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2877 for (unsigned i = NumElems/2; i < NumElems; ++i)
2878 if (!isUndefOrEqual(N->getMaskElt(i), i))
2884 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2885 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2886 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2887 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2889 if (NumElems != 2 && NumElems != 4)
2892 for (unsigned i = 0; i < NumElems/2; ++i)
2893 if (!isUndefOrEqual(N->getMaskElt(i), i))
2896 for (unsigned i = 0; i < NumElems/2; ++i)
2897 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2903 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2904 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2905 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2906 bool V2IsSplat = false) {
2907 int NumElts = VT.getVectorNumElements();
2908 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2911 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2913 int BitI1 = Mask[i+1];
2914 if (!isUndefOrEqual(BitI, j))
2917 if (!isUndefOrEqual(BitI1, NumElts))
2920 if (!isUndefOrEqual(BitI1, j + NumElts))
2927 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2928 SmallVector<int, 8> M;
2930 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2933 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2934 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2935 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2936 bool V2IsSplat = false) {
2937 int NumElts = VT.getVectorNumElements();
2938 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2941 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2943 int BitI1 = Mask[i+1];
2944 if (!isUndefOrEqual(BitI, j + NumElts/2))
2947 if (isUndefOrEqual(BitI1, NumElts))
2950 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2957 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2958 SmallVector<int, 8> M;
2960 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2963 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2964 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2966 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2967 int NumElems = VT.getVectorNumElements();
2968 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2971 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2973 int BitI1 = Mask[i+1];
2974 if (!isUndefOrEqual(BitI, j))
2976 if (!isUndefOrEqual(BitI1, j))
2982 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2983 SmallVector<int, 8> M;
2985 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2988 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2989 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2991 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2992 int NumElems = VT.getVectorNumElements();
2993 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2996 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2998 int BitI1 = Mask[i+1];
2999 if (!isUndefOrEqual(BitI, j))
3001 if (!isUndefOrEqual(BitI1, j))
3007 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3008 SmallVector<int, 8> M;
3010 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3013 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3014 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3015 /// MOVSD, and MOVD, i.e. setting the lowest element.
3016 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3017 if (VT.getVectorElementType().getSizeInBits() < 32)
3020 int NumElts = VT.getVectorNumElements();
3022 if (!isUndefOrEqual(Mask[0], NumElts))
3025 for (int i = 1; i < NumElts; ++i)
3026 if (!isUndefOrEqual(Mask[i], i))
3032 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3033 SmallVector<int, 8> M;
3035 return ::isMOVLMask(M, N->getValueType(0));
3038 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3039 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3040 /// element of vector 2 and the other elements to come from vector 1 in order.
3041 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3042 bool V2IsSplat = false, bool V2IsUndef = false) {
3043 int NumOps = VT.getVectorNumElements();
3044 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3047 if (!isUndefOrEqual(Mask[0], 0))
3050 for (int i = 1; i < NumOps; ++i)
3051 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3052 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3053 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3059 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3060 bool V2IsUndef = false) {
3061 SmallVector<int, 8> M;
3063 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3066 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3067 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3068 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3069 if (N->getValueType(0).getVectorNumElements() != 4)
3072 // Expect 1, 1, 3, 3
3073 for (unsigned i = 0; i < 2; ++i) {
3074 int Elt = N->getMaskElt(i);
3075 if (Elt >= 0 && Elt != 1)
3080 for (unsigned i = 2; i < 4; ++i) {
3081 int Elt = N->getMaskElt(i);
3082 if (Elt >= 0 && Elt != 3)
3087 // Don't use movshdup if it can be done with a shufps.
3088 // FIXME: verify that matching u, u, 3, 3 is what we want.
3092 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3093 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3094 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3095 if (N->getValueType(0).getVectorNumElements() != 4)
3098 // Expect 0, 0, 2, 2
3099 for (unsigned i = 0; i < 2; ++i)
3100 if (N->getMaskElt(i) > 0)
3104 for (unsigned i = 2; i < 4; ++i) {
3105 int Elt = N->getMaskElt(i);
3106 if (Elt >= 0 && Elt != 2)
3111 // Don't use movsldup if it can be done with a shufps.
3115 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3116 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3117 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3118 int e = N->getValueType(0).getVectorNumElements() / 2;
3120 for (int i = 0; i < e; ++i)
3121 if (!isUndefOrEqual(N->getMaskElt(i), i))
3123 for (int i = 0; i < e; ++i)
3124 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3129 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3130 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3131 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3132 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3133 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3135 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3137 for (int i = 0; i < NumOperands; ++i) {
3138 int Val = SVOp->getMaskElt(NumOperands-i-1);
3139 if (Val < 0) Val = 0;
3140 if (Val >= NumOperands) Val -= NumOperands;
3142 if (i != NumOperands - 1)
3148 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3149 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3150 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3151 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3153 // 8 nodes, but we only care about the last 4.
3154 for (unsigned i = 7; i >= 4; --i) {
3155 int Val = SVOp->getMaskElt(i);
3164 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3165 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3166 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3167 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3169 // 8 nodes, but we only care about the first 4.
3170 for (int i = 3; i >= 0; --i) {
3171 int Val = SVOp->getMaskElt(i);
3180 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3181 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3182 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3184 EVT VVT = N->getValueType(0);
3185 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3189 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3190 Val = SVOp->getMaskElt(i);
3194 return (Val - i) * EltSize;
3197 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3199 bool X86::isZeroNode(SDValue Elt) {
3200 return ((isa<ConstantSDNode>(Elt) &&
3201 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3202 (isa<ConstantFPSDNode>(Elt) &&
3203 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3206 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3207 /// their permute mask.
3208 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3209 SelectionDAG &DAG) {
3210 EVT VT = SVOp->getValueType(0);
3211 unsigned NumElems = VT.getVectorNumElements();
3212 SmallVector<int, 8> MaskVec;
3214 for (unsigned i = 0; i != NumElems; ++i) {
3215 int idx = SVOp->getMaskElt(i);
3217 MaskVec.push_back(idx);
3218 else if (idx < (int)NumElems)
3219 MaskVec.push_back(idx + NumElems);
3221 MaskVec.push_back(idx - NumElems);
3223 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3224 SVOp->getOperand(0), &MaskVec[0]);
3227 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3228 /// the two vector operands have swapped position.
3229 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3230 unsigned NumElems = VT.getVectorNumElements();
3231 for (unsigned i = 0; i != NumElems; ++i) {
3235 else if (idx < (int)NumElems)
3236 Mask[i] = idx + NumElems;
3238 Mask[i] = idx - NumElems;
3242 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3243 /// match movhlps. The lower half elements should come from upper half of
3244 /// V1 (and in order), and the upper half elements should come from the upper
3245 /// half of V2 (and in order).
3246 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3247 if (Op->getValueType(0).getVectorNumElements() != 4)
3249 for (unsigned i = 0, e = 2; i != e; ++i)
3250 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3252 for (unsigned i = 2; i != 4; ++i)
3253 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3258 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3259 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3261 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3262 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3264 N = N->getOperand(0).getNode();
3265 if (!ISD::isNON_EXTLoad(N))
3268 *LD = cast<LoadSDNode>(N);
3272 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3273 /// match movlp{s|d}. The lower half elements should come from lower half of
3274 /// V1 (and in order), and the upper half elements should come from the upper
3275 /// half of V2 (and in order). And since V1 will become the source of the
3276 /// MOVLP, it must be either a vector load or a scalar load to vector.
3277 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3278 ShuffleVectorSDNode *Op) {
3279 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3281 // Is V2 is a vector load, don't do this transformation. We will try to use
3282 // load folding shufps op.
3283 if (ISD::isNON_EXTLoad(V2))
3286 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3288 if (NumElems != 2 && NumElems != 4)
3290 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3291 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3293 for (unsigned i = NumElems/2; i != NumElems; ++i)
3294 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3299 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3301 static bool isSplatVector(SDNode *N) {
3302 if (N->getOpcode() != ISD::BUILD_VECTOR)
3305 SDValue SplatValue = N->getOperand(0);
3306 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3307 if (N->getOperand(i) != SplatValue)
3312 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3313 /// to an zero vector.
3314 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3315 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3316 SDValue V1 = N->getOperand(0);
3317 SDValue V2 = N->getOperand(1);
3318 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3319 for (unsigned i = 0; i != NumElems; ++i) {
3320 int Idx = N->getMaskElt(i);
3321 if (Idx >= (int)NumElems) {
3322 unsigned Opc = V2.getOpcode();
3323 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3325 if (Opc != ISD::BUILD_VECTOR ||
3326 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3328 } else if (Idx >= 0) {
3329 unsigned Opc = V1.getOpcode();
3330 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3332 if (Opc != ISD::BUILD_VECTOR ||
3333 !X86::isZeroNode(V1.getOperand(Idx)))
3340 /// getZeroVector - Returns a vector of specified type with all zero elements.
3342 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3344 assert(VT.isVector() && "Expected a vector type");
3346 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3347 // type. This ensures they get CSE'd.
3349 if (VT.getSizeInBits() == 64) { // MMX
3350 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3351 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3352 } else if (HasSSE2) { // SSE2
3353 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3354 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3356 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3357 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3359 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3362 /// getOnesVector - Returns a vector of specified type with all bits set.
3364 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3365 assert(VT.isVector() && "Expected a vector type");
3367 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3368 // type. This ensures they get CSE'd.
3369 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3371 if (VT.getSizeInBits() == 64) // MMX
3372 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3374 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3375 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3379 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3380 /// that point to V2 points to its first element.
3381 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3382 EVT VT = SVOp->getValueType(0);
3383 unsigned NumElems = VT.getVectorNumElements();
3385 bool Changed = false;
3386 SmallVector<int, 8> MaskVec;
3387 SVOp->getMask(MaskVec);
3389 for (unsigned i = 0; i != NumElems; ++i) {
3390 if (MaskVec[i] > (int)NumElems) {
3391 MaskVec[i] = NumElems;
3396 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3397 SVOp->getOperand(1), &MaskVec[0]);
3398 return SDValue(SVOp, 0);
3401 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3402 /// operation of specified width.
3403 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3405 unsigned NumElems = VT.getVectorNumElements();
3406 SmallVector<int, 8> Mask;
3407 Mask.push_back(NumElems);
3408 for (unsigned i = 1; i != NumElems; ++i)
3410 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3413 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3414 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3416 unsigned NumElems = VT.getVectorNumElements();
3417 SmallVector<int, 8> Mask;
3418 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3420 Mask.push_back(i + NumElems);
3422 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3425 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3426 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3428 unsigned NumElems = VT.getVectorNumElements();
3429 unsigned Half = NumElems/2;
3430 SmallVector<int, 8> Mask;
3431 for (unsigned i = 0; i != Half; ++i) {
3432 Mask.push_back(i + Half);
3433 Mask.push_back(i + NumElems + Half);
3435 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3438 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3439 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3441 if (SV->getValueType(0).getVectorNumElements() <= 4)
3442 return SDValue(SV, 0);
3444 EVT PVT = MVT::v4f32;
3445 EVT VT = SV->getValueType(0);
3446 DebugLoc dl = SV->getDebugLoc();
3447 SDValue V1 = SV->getOperand(0);
3448 int NumElems = VT.getVectorNumElements();
3449 int EltNo = SV->getSplatIndex();
3451 // unpack elements to the correct location
3452 while (NumElems > 4) {
3453 if (EltNo < NumElems/2) {
3454 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3456 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3457 EltNo -= NumElems/2;
3462 // Perform the splat.
3463 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3464 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3465 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3466 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3469 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3470 /// vector of zero or undef vector. This produces a shuffle where the low
3471 /// element of V2 is swizzled into the zero/undef vector, landing at element
3472 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3473 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3474 bool isZero, bool HasSSE2,
3475 SelectionDAG &DAG) {
3476 EVT VT = V2.getValueType();
3478 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3479 unsigned NumElems = VT.getVectorNumElements();
3480 SmallVector<int, 16> MaskVec;
3481 for (unsigned i = 0; i != NumElems; ++i)
3482 // If this is the insertion idx, put the low elt of V2 here.
3483 MaskVec.push_back(i == Idx ? NumElems : i);
3484 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3487 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3488 /// a shuffle that is zero.
3490 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3491 bool Low, SelectionDAG &DAG) {
3492 unsigned NumZeros = 0;
3493 for (int i = 0; i < NumElems; ++i) {
3494 unsigned Index = Low ? i : NumElems-i-1;
3495 int Idx = SVOp->getMaskElt(Index);
3500 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3501 if (Elt.getNode() && X86::isZeroNode(Elt))
3509 /// isVectorShift - Returns true if the shuffle can be implemented as a
3510 /// logical left or right shift of a vector.
3511 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3512 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3513 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3514 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3517 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3520 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3524 bool SeenV1 = false;
3525 bool SeenV2 = false;
3526 for (unsigned i = NumZeros; i < NumElems; ++i) {
3527 unsigned Val = isLeft ? (i - NumZeros) : i;
3528 int Idx_ = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3531 unsigned Idx = (unsigned) Idx_;
3541 if (SeenV1 && SeenV2)
3544 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3550 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3552 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3553 unsigned NumNonZero, unsigned NumZero,
3555 const TargetLowering &TLI) {
3559 DebugLoc dl = Op.getDebugLoc();
3562 for (unsigned i = 0; i < 16; ++i) {
3563 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3564 if (ThisIsNonZero && First) {
3566 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3568 V = DAG.getUNDEF(MVT::v8i16);
3573 SDValue ThisElt(0, 0), LastElt(0, 0);
3574 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3575 if (LastIsNonZero) {
3576 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3577 MVT::i16, Op.getOperand(i-1));
3579 if (ThisIsNonZero) {
3580 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3581 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3582 ThisElt, DAG.getConstant(8, MVT::i8));
3584 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3588 if (ThisElt.getNode())
3589 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3590 DAG.getIntPtrConstant(i/2));
3594 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3597 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3599 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3600 unsigned NumNonZero, unsigned NumZero,
3602 const TargetLowering &TLI) {
3606 DebugLoc dl = Op.getDebugLoc();
3609 for (unsigned i = 0; i < 8; ++i) {
3610 bool isNonZero = (NonZeros & (1 << i)) != 0;
3614 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3616 V = DAG.getUNDEF(MVT::v8i16);
3619 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3620 MVT::v8i16, V, Op.getOperand(i),
3621 DAG.getIntPtrConstant(i));
3628 /// getVShift - Return a vector logical shift node.
3630 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3631 unsigned NumBits, SelectionDAG &DAG,
3632 const TargetLowering &TLI, DebugLoc dl) {
3633 bool isMMX = VT.getSizeInBits() == 64;
3634 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3635 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3636 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3637 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3638 DAG.getNode(Opc, dl, ShVT, SrcOp,
3639 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3643 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3644 SelectionDAG &DAG) const {
3646 // Check if the scalar load can be widened into a vector load. And if
3647 // the address is "base + cst" see if the cst can be "absorbed" into
3648 // the shuffle mask.
3649 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3650 SDValue Ptr = LD->getBasePtr();
3651 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3653 EVT PVT = LD->getValueType(0);
3654 if (PVT != MVT::i32 && PVT != MVT::f32)
3659 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3660 FI = FINode->getIndex();
3662 } else if (Ptr.getOpcode() == ISD::ADD &&
3663 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3664 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3665 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3666 Offset = Ptr.getConstantOperandVal(1);
3667 Ptr = Ptr.getOperand(0);
3672 SDValue Chain = LD->getChain();
3673 // Make sure the stack object alignment is at least 16.
3674 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3675 if (DAG.InferPtrAlignment(Ptr) < 16) {
3676 if (MFI->isFixedObjectIndex(FI)) {
3677 // Can't change the alignment. FIXME: It's possible to compute
3678 // the exact stack offset and reference FI + adjust offset instead.
3679 // If someone *really* cares about this. That's the way to implement it.
3682 MFI->setObjectAlignment(FI, 16);
3686 // (Offset % 16) must be multiple of 4. Then address is then
3687 // Ptr + (Offset & ~15).
3690 if ((Offset % 16) & 3)
3692 int64_t StartOffset = Offset & ~15;
3694 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3695 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3697 int EltNo = (Offset - StartOffset) >> 2;
3698 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3699 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3700 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3702 // Canonicalize it to a v4i32 shuffle.
3703 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3704 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3705 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3706 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3712 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
3713 /// vector of type 'VT', see if the elements can be replaced by a single large
3714 /// load which has the same value as a build_vector whose operands are 'elts'.
3716 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
3718 /// FIXME: we'd also like to handle the case where the last elements are zero
3719 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
3720 /// There's even a handy isZeroNode for that purpose.
3721 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
3722 DebugLoc &dl, SelectionDAG &DAG) {
3723 EVT EltVT = VT.getVectorElementType();
3724 unsigned NumElems = Elts.size();
3726 LoadSDNode *LDBase = NULL;
3727 unsigned LastLoadedElt = -1U;
3729 // For each element in the initializer, see if we've found a load or an undef.
3730 // If we don't find an initial load element, or later load elements are
3731 // non-consecutive, bail out.
3732 for (unsigned i = 0; i < NumElems; ++i) {
3733 SDValue Elt = Elts[i];
3735 if (!Elt.getNode() ||
3736 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
3739 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
3741 LDBase = cast<LoadSDNode>(Elt.getNode());
3745 if (Elt.getOpcode() == ISD::UNDEF)
3748 LoadSDNode *LD = cast<LoadSDNode>(Elt);
3749 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
3754 // If we have found an entire vector of loads and undefs, then return a large
3755 // load of the entire vector width starting at the base pointer. If we found
3756 // consecutive loads for the low half, generate a vzext_load node.
3757 if (LastLoadedElt == NumElems - 1) {
3758 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
3759 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3760 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3761 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
3762 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3763 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3764 LDBase->isVolatile(), LDBase->isNonTemporal(),
3765 LDBase->getAlignment());
3766 } else if (NumElems == 4 && LastLoadedElt == 1) {
3767 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
3768 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
3769 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
3770 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
3776 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
3777 DebugLoc dl = Op.getDebugLoc();
3778 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3779 if (ISD::isBuildVectorAllZeros(Op.getNode())
3780 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3781 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3782 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3783 // eliminated on x86-32 hosts.
3784 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3787 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3788 return getOnesVector(Op.getValueType(), DAG, dl);
3789 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3792 EVT VT = Op.getValueType();
3793 EVT ExtVT = VT.getVectorElementType();
3794 unsigned EVTBits = ExtVT.getSizeInBits();
3796 unsigned NumElems = Op.getNumOperands();
3797 unsigned NumZero = 0;
3798 unsigned NumNonZero = 0;
3799 unsigned NonZeros = 0;
3800 bool IsAllConstants = true;
3801 SmallSet<SDValue, 8> Values;
3802 for (unsigned i = 0; i < NumElems; ++i) {
3803 SDValue Elt = Op.getOperand(i);
3804 if (Elt.getOpcode() == ISD::UNDEF)
3807 if (Elt.getOpcode() != ISD::Constant &&
3808 Elt.getOpcode() != ISD::ConstantFP)
3809 IsAllConstants = false;
3810 if (X86::isZeroNode(Elt))
3813 NonZeros |= (1 << i);
3818 if (NumNonZero == 0) {
3819 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3820 return DAG.getUNDEF(VT);
3823 // Special case for single non-zero, non-undef, element.
3824 if (NumNonZero == 1) {
3825 unsigned Idx = CountTrailingZeros_32(NonZeros);
3826 SDValue Item = Op.getOperand(Idx);
3828 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3829 // the value are obviously zero, truncate the value to i32 and do the
3830 // insertion that way. Only do this if the value is non-constant or if the
3831 // value is a constant being inserted into element 0. It is cheaper to do
3832 // a constant pool load than it is to do a movd + shuffle.
3833 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3834 (!IsAllConstants || Idx == 0)) {
3835 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3836 // Handle MMX and SSE both.
3837 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3838 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3840 // Truncate the value (which may itself be a constant) to i32, and
3841 // convert it to a vector with movd (S2V+shuffle to zero extend).
3842 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3843 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3844 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3845 Subtarget->hasSSE2(), DAG);
3847 // Now we have our 32-bit value zero extended in the low element of
3848 // a vector. If Idx != 0, swizzle it into place.
3850 SmallVector<int, 4> Mask;
3851 Mask.push_back(Idx);
3852 for (unsigned i = 1; i != VecElts; ++i)
3854 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3855 DAG.getUNDEF(Item.getValueType()),
3858 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3862 // If we have a constant or non-constant insertion into the low element of
3863 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3864 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3865 // depending on what the source datatype is.
3868 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3869 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3870 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3871 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3872 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3873 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3875 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3876 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3877 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3878 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3879 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3880 Subtarget->hasSSE2(), DAG);
3881 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3885 // Is it a vector logical left shift?
3886 if (NumElems == 2 && Idx == 1 &&
3887 X86::isZeroNode(Op.getOperand(0)) &&
3888 !X86::isZeroNode(Op.getOperand(1))) {
3889 unsigned NumBits = VT.getSizeInBits();
3890 return getVShift(true, VT,
3891 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3892 VT, Op.getOperand(1)),
3893 NumBits/2, DAG, *this, dl);
3896 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3899 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3900 // is a non-constant being inserted into an element other than the low one,
3901 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3902 // movd/movss) to move this into the low element, then shuffle it into
3904 if (EVTBits == 32) {
3905 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3907 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3908 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3909 Subtarget->hasSSE2(), DAG);
3910 SmallVector<int, 8> MaskVec;
3911 for (unsigned i = 0; i < NumElems; i++)
3912 MaskVec.push_back(i == Idx ? 0 : 1);
3913 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3917 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3918 if (Values.size() == 1) {
3919 if (EVTBits == 32) {
3920 // Instead of a shuffle like this:
3921 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3922 // Check if it's possible to issue this instead.
3923 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3924 unsigned Idx = CountTrailingZeros_32(NonZeros);
3925 SDValue Item = Op.getOperand(Idx);
3926 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3927 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3932 // A vector full of immediates; various special cases are already
3933 // handled, so this is best done with a single constant-pool load.
3937 // Let legalizer expand 2-wide build_vectors.
3938 if (EVTBits == 64) {
3939 if (NumNonZero == 1) {
3940 // One half is zero or undef.
3941 unsigned Idx = CountTrailingZeros_32(NonZeros);
3942 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3943 Op.getOperand(Idx));
3944 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3945 Subtarget->hasSSE2(), DAG);
3950 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3951 if (EVTBits == 8 && NumElems == 16) {
3952 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3954 if (V.getNode()) return V;
3957 if (EVTBits == 16 && NumElems == 8) {
3958 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3960 if (V.getNode()) return V;
3963 // If element VT is == 32 bits, turn it into a number of shuffles.
3964 SmallVector<SDValue, 8> V;
3966 if (NumElems == 4 && NumZero > 0) {
3967 for (unsigned i = 0; i < 4; ++i) {
3968 bool isZero = !(NonZeros & (1 << i));
3970 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3972 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3975 for (unsigned i = 0; i < 2; ++i) {
3976 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3979 V[i] = V[i*2]; // Must be a zero vector.
3982 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3985 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3988 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3993 SmallVector<int, 8> MaskVec;
3994 bool Reverse = (NonZeros & 0x3) == 2;
3995 for (unsigned i = 0; i < 2; ++i)
3996 MaskVec.push_back(Reverse ? 1-i : i);
3997 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3998 for (unsigned i = 0; i < 2; ++i)
3999 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4000 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4003 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4004 // Check for a build vector of consecutive loads.
4005 for (unsigned i = 0; i < NumElems; ++i)
4006 V[i] = Op.getOperand(i);
4008 // Check for elements which are consecutive loads.
4009 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4013 // For SSE 4.1, use inserts into undef.
4014 if (getSubtarget()->hasSSE41()) {
4015 V[0] = DAG.getUNDEF(VT);
4016 for (unsigned i = 0; i < NumElems; ++i)
4017 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4018 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
4019 Op.getOperand(i), DAG.getIntPtrConstant(i));
4023 // Otherwise, expand into a number of unpckl*
4025 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4026 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4027 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4028 for (unsigned i = 0; i < NumElems; ++i)
4029 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4031 while (NumElems != 0) {
4032 for (unsigned i = 0; i < NumElems; ++i)
4033 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
4042 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4043 // We support concatenate two MMX registers and place them in a MMX
4044 // register. This is better than doing a stack convert.
4045 DebugLoc dl = Op.getDebugLoc();
4046 EVT ResVT = Op.getValueType();
4047 assert(Op.getNumOperands() == 2);
4048 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4049 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4051 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4052 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4053 InVec = Op.getOperand(1);
4054 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4055 unsigned NumElts = ResVT.getVectorNumElements();
4056 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4057 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4058 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4060 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4061 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4062 Mask[0] = 0; Mask[1] = 2;
4063 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4065 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4068 // v8i16 shuffles - Prefer shuffles in the following order:
4069 // 1. [all] pshuflw, pshufhw, optional move
4070 // 2. [ssse3] 1 x pshufb
4071 // 3. [ssse3] 2 x pshufb + 1 x por
4072 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4074 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
4076 const X86TargetLowering &TLI) {
4077 SDValue V1 = SVOp->getOperand(0);
4078 SDValue V2 = SVOp->getOperand(1);
4079 DebugLoc dl = SVOp->getDebugLoc();
4080 SmallVector<int, 8> MaskVals;
4082 // Determine if more than 1 of the words in each of the low and high quadwords
4083 // of the result come from the same quadword of one of the two inputs. Undef
4084 // mask values count as coming from any quadword, for better codegen.
4085 SmallVector<unsigned, 4> LoQuad(4);
4086 SmallVector<unsigned, 4> HiQuad(4);
4087 BitVector InputQuads(4);
4088 for (unsigned i = 0; i < 8; ++i) {
4089 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4090 int EltIdx = SVOp->getMaskElt(i);
4091 MaskVals.push_back(EltIdx);
4100 InputQuads.set(EltIdx / 4);
4103 int BestLoQuad = -1;
4104 unsigned MaxQuad = 1;
4105 for (unsigned i = 0; i < 4; ++i) {
4106 if (LoQuad[i] > MaxQuad) {
4108 MaxQuad = LoQuad[i];
4112 int BestHiQuad = -1;
4114 for (unsigned i = 0; i < 4; ++i) {
4115 if (HiQuad[i] > MaxQuad) {
4117 MaxQuad = HiQuad[i];
4121 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4122 // of the two input vectors, shuffle them into one input vector so only a
4123 // single pshufb instruction is necessary. If There are more than 2 input
4124 // quads, disable the next transformation since it does not help SSSE3.
4125 bool V1Used = InputQuads[0] || InputQuads[1];
4126 bool V2Used = InputQuads[2] || InputQuads[3];
4127 if (TLI.getSubtarget()->hasSSSE3()) {
4128 if (InputQuads.count() == 2 && V1Used && V2Used) {
4129 BestLoQuad = InputQuads.find_first();
4130 BestHiQuad = InputQuads.find_next(BestLoQuad);
4132 if (InputQuads.count() > 2) {
4138 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4139 // the shuffle mask. If a quad is scored as -1, that means that it contains
4140 // words from all 4 input quadwords.
4142 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4143 SmallVector<int, 8> MaskV;
4144 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4145 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4146 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4147 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4148 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4149 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4151 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4152 // source words for the shuffle, to aid later transformations.
4153 bool AllWordsInNewV = true;
4154 bool InOrder[2] = { true, true };
4155 for (unsigned i = 0; i != 8; ++i) {
4156 int idx = MaskVals[i];
4158 InOrder[i/4] = false;
4159 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4161 AllWordsInNewV = false;
4165 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4166 if (AllWordsInNewV) {
4167 for (int i = 0; i != 8; ++i) {
4168 int idx = MaskVals[i];
4171 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4172 if ((idx != i) && idx < 4)
4174 if ((idx != i) && idx > 3)
4183 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4184 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4185 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4186 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4187 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4191 // If we have SSSE3, and all words of the result are from 1 input vector,
4192 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4193 // is present, fall back to case 4.
4194 if (TLI.getSubtarget()->hasSSSE3()) {
4195 SmallVector<SDValue,16> pshufbMask;
4197 // If we have elements from both input vectors, set the high bit of the
4198 // shuffle mask element to zero out elements that come from V2 in the V1
4199 // mask, and elements that come from V1 in the V2 mask, so that the two
4200 // results can be OR'd together.
4201 bool TwoInputs = V1Used && V2Used;
4202 for (unsigned i = 0; i != 8; ++i) {
4203 int EltIdx = MaskVals[i] * 2;
4204 if (TwoInputs && (EltIdx >= 16)) {
4205 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4206 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4209 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4210 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4212 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4213 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4214 DAG.getNode(ISD::BUILD_VECTOR, dl,
4215 MVT::v16i8, &pshufbMask[0], 16));
4217 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4219 // Calculate the shuffle mask for the second input, shuffle it, and
4220 // OR it with the first shuffled input.
4222 for (unsigned i = 0; i != 8; ++i) {
4223 int EltIdx = MaskVals[i] * 2;
4225 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4226 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4229 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4230 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4232 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4233 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4234 DAG.getNode(ISD::BUILD_VECTOR, dl,
4235 MVT::v16i8, &pshufbMask[0], 16));
4236 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4237 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4240 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4241 // and update MaskVals with new element order.
4242 BitVector InOrder(8);
4243 if (BestLoQuad >= 0) {
4244 SmallVector<int, 8> MaskV;
4245 for (int i = 0; i != 4; ++i) {
4246 int idx = MaskVals[i];
4248 MaskV.push_back(-1);
4250 } else if ((idx / 4) == BestLoQuad) {
4251 MaskV.push_back(idx & 3);
4254 MaskV.push_back(-1);
4257 for (unsigned i = 4; i != 8; ++i)
4259 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4263 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4264 // and update MaskVals with the new element order.
4265 if (BestHiQuad >= 0) {
4266 SmallVector<int, 8> MaskV;
4267 for (unsigned i = 0; i != 4; ++i)
4269 for (unsigned i = 4; i != 8; ++i) {
4270 int idx = MaskVals[i];
4272 MaskV.push_back(-1);
4274 } else if ((idx / 4) == BestHiQuad) {
4275 MaskV.push_back((idx & 3) + 4);
4278 MaskV.push_back(-1);
4281 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4285 // In case BestHi & BestLo were both -1, which means each quadword has a word
4286 // from each of the four input quadwords, calculate the InOrder bitvector now
4287 // before falling through to the insert/extract cleanup.
4288 if (BestLoQuad == -1 && BestHiQuad == -1) {
4290 for (int i = 0; i != 8; ++i)
4291 if (MaskVals[i] < 0 || MaskVals[i] == i)
4295 // The other elements are put in the right place using pextrw and pinsrw.
4296 for (unsigned i = 0; i != 8; ++i) {
4299 int EltIdx = MaskVals[i];
4302 SDValue ExtOp = (EltIdx < 8)
4303 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4304 DAG.getIntPtrConstant(EltIdx))
4305 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4306 DAG.getIntPtrConstant(EltIdx - 8));
4307 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4308 DAG.getIntPtrConstant(i));
4313 // v16i8 shuffles - Prefer shuffles in the following order:
4314 // 1. [ssse3] 1 x pshufb
4315 // 2. [ssse3] 2 x pshufb + 1 x por
4316 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4318 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4320 const X86TargetLowering &TLI) {
4321 SDValue V1 = SVOp->getOperand(0);
4322 SDValue V2 = SVOp->getOperand(1);
4323 DebugLoc dl = SVOp->getDebugLoc();
4324 SmallVector<int, 16> MaskVals;
4325 SVOp->getMask(MaskVals);
4327 // If we have SSSE3, case 1 is generated when all result bytes come from
4328 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4329 // present, fall back to case 3.
4330 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4333 for (unsigned i = 0; i < 16; ++i) {
4334 int EltIdx = MaskVals[i];
4343 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4344 if (TLI.getSubtarget()->hasSSSE3()) {
4345 SmallVector<SDValue,16> pshufbMask;
4347 // If all result elements are from one input vector, then only translate
4348 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4350 // Otherwise, we have elements from both input vectors, and must zero out
4351 // elements that come from V2 in the first mask, and V1 in the second mask
4352 // so that we can OR them together.
4353 bool TwoInputs = !(V1Only || V2Only);
4354 for (unsigned i = 0; i != 16; ++i) {
4355 int EltIdx = MaskVals[i];
4356 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4357 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4360 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4362 // If all the elements are from V2, assign it to V1 and return after
4363 // building the first pshufb.
4366 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4367 DAG.getNode(ISD::BUILD_VECTOR, dl,
4368 MVT::v16i8, &pshufbMask[0], 16));
4372 // Calculate the shuffle mask for the second input, shuffle it, and
4373 // OR it with the first shuffled input.
4375 for (unsigned i = 0; i != 16; ++i) {
4376 int EltIdx = MaskVals[i];
4378 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4381 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4383 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4384 DAG.getNode(ISD::BUILD_VECTOR, dl,
4385 MVT::v16i8, &pshufbMask[0], 16));
4386 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4389 // No SSSE3 - Calculate in place words and then fix all out of place words
4390 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4391 // the 16 different words that comprise the two doublequadword input vectors.
4392 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4393 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4394 SDValue NewV = V2Only ? V2 : V1;
4395 for (int i = 0; i != 8; ++i) {
4396 int Elt0 = MaskVals[i*2];
4397 int Elt1 = MaskVals[i*2+1];
4399 // This word of the result is all undef, skip it.
4400 if (Elt0 < 0 && Elt1 < 0)
4403 // This word of the result is already in the correct place, skip it.
4404 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4406 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4409 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4410 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4413 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4414 // using a single extract together, load it and store it.
4415 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4416 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4417 DAG.getIntPtrConstant(Elt1 / 2));
4418 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4419 DAG.getIntPtrConstant(i));
4423 // If Elt1 is defined, extract it from the appropriate source. If the
4424 // source byte is not also odd, shift the extracted word left 8 bits
4425 // otherwise clear the bottom 8 bits if we need to do an or.
4427 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4428 DAG.getIntPtrConstant(Elt1 / 2));
4429 if ((Elt1 & 1) == 0)
4430 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4431 DAG.getConstant(8, TLI.getShiftAmountTy()));
4433 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4434 DAG.getConstant(0xFF00, MVT::i16));
4436 // If Elt0 is defined, extract it from the appropriate source. If the
4437 // source byte is not also even, shift the extracted word right 8 bits. If
4438 // Elt1 was also defined, OR the extracted values together before
4439 // inserting them in the result.
4441 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4442 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4443 if ((Elt0 & 1) != 0)
4444 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4445 DAG.getConstant(8, TLI.getShiftAmountTy()));
4447 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4448 DAG.getConstant(0x00FF, MVT::i16));
4449 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4452 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4453 DAG.getIntPtrConstant(i));
4455 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4458 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4459 /// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be
4460 /// done when every pair / quad of shuffle mask elements point to elements in
4461 /// the right sequence. e.g.
4462 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4464 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4466 const TargetLowering &TLI, DebugLoc dl) {
4467 EVT VT = SVOp->getValueType(0);
4468 SDValue V1 = SVOp->getOperand(0);
4469 SDValue V2 = SVOp->getOperand(1);
4470 unsigned NumElems = VT.getVectorNumElements();
4471 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4472 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4474 switch (VT.getSimpleVT().SimpleTy) {
4475 default: assert(false && "Unexpected!");
4476 case MVT::v4f32: NewVT = MVT::v2f64; break;
4477 case MVT::v4i32: NewVT = MVT::v2i64; break;
4478 case MVT::v8i16: NewVT = MVT::v4i32; break;
4479 case MVT::v16i8: NewVT = MVT::v4i32; break;
4482 if (NewWidth == 2) {
4488 int Scale = NumElems / NewWidth;
4489 SmallVector<int, 8> MaskVec;
4490 for (unsigned i = 0; i < NumElems; i += Scale) {
4492 for (int j = 0; j < Scale; ++j) {
4493 int EltIdx = SVOp->getMaskElt(i+j);
4497 StartIdx = EltIdx - (EltIdx % Scale);
4498 if (EltIdx != StartIdx + j)
4502 MaskVec.push_back(-1);
4504 MaskVec.push_back(StartIdx / Scale);
4507 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4508 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4509 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4512 /// getVZextMovL - Return a zero-extending vector move low node.
4514 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4515 SDValue SrcOp, SelectionDAG &DAG,
4516 const X86Subtarget *Subtarget, DebugLoc dl) {
4517 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4518 LoadSDNode *LD = NULL;
4519 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4520 LD = dyn_cast<LoadSDNode>(SrcOp);
4522 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4524 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4525 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4526 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4527 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4528 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4530 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4531 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4532 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4533 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4541 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4542 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4543 DAG.getNode(ISD::BIT_CONVERT, dl,
4547 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4550 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4551 SDValue V1 = SVOp->getOperand(0);
4552 SDValue V2 = SVOp->getOperand(1);
4553 DebugLoc dl = SVOp->getDebugLoc();
4554 EVT VT = SVOp->getValueType(0);
4556 SmallVector<std::pair<int, int>, 8> Locs;
4558 SmallVector<int, 8> Mask1(4U, -1);
4559 SmallVector<int, 8> PermMask;
4560 SVOp->getMask(PermMask);
4564 for (unsigned i = 0; i != 4; ++i) {
4565 int Idx = PermMask[i];
4567 Locs[i] = std::make_pair(-1, -1);
4569 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4571 Locs[i] = std::make_pair(0, NumLo);
4575 Locs[i] = std::make_pair(1, NumHi);
4577 Mask1[2+NumHi] = Idx;
4583 if (NumLo <= 2 && NumHi <= 2) {
4584 // If no more than two elements come from either vector. This can be
4585 // implemented with two shuffles. First shuffle gather the elements.
4586 // The second shuffle, which takes the first shuffle as both of its
4587 // vector operands, put the elements into the right order.
4588 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4590 SmallVector<int, 8> Mask2(4U, -1);
4592 for (unsigned i = 0; i != 4; ++i) {
4593 if (Locs[i].first == -1)
4596 unsigned Idx = (i < 2) ? 0 : 4;
4597 Idx += Locs[i].first * 2 + Locs[i].second;
4602 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4603 } else if (NumLo == 3 || NumHi == 3) {
4604 // Otherwise, we must have three elements from one vector, call it X, and
4605 // one element from the other, call it Y. First, use a shufps to build an
4606 // intermediate vector with the one element from Y and the element from X
4607 // that will be in the same half in the final destination (the indexes don't
4608 // matter). Then, use a shufps to build the final vector, taking the half
4609 // containing the element from Y from the intermediate, and the other half
4612 // Normalize it so the 3 elements come from V1.
4613 CommuteVectorShuffleMask(PermMask, VT);
4617 // Find the element from V2.
4619 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4620 int Val = PermMask[HiIndex];
4627 Mask1[0] = PermMask[HiIndex];
4629 Mask1[2] = PermMask[HiIndex^1];
4631 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4634 Mask1[0] = PermMask[0];
4635 Mask1[1] = PermMask[1];
4636 Mask1[2] = HiIndex & 1 ? 6 : 4;
4637 Mask1[3] = HiIndex & 1 ? 4 : 6;
4638 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4640 Mask1[0] = HiIndex & 1 ? 2 : 0;
4641 Mask1[1] = HiIndex & 1 ? 0 : 2;
4642 Mask1[2] = PermMask[2];
4643 Mask1[3] = PermMask[3];
4648 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4652 // Break it into (shuffle shuffle_hi, shuffle_lo).
4654 SmallVector<int,8> LoMask(4U, -1);
4655 SmallVector<int,8> HiMask(4U, -1);
4657 SmallVector<int,8> *MaskPtr = &LoMask;
4658 unsigned MaskIdx = 0;
4661 for (unsigned i = 0; i != 4; ++i) {
4668 int Idx = PermMask[i];
4670 Locs[i] = std::make_pair(-1, -1);
4671 } else if (Idx < 4) {
4672 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4673 (*MaskPtr)[LoIdx] = Idx;
4676 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4677 (*MaskPtr)[HiIdx] = Idx;
4682 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4683 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4684 SmallVector<int, 8> MaskOps;
4685 for (unsigned i = 0; i != 4; ++i) {
4686 if (Locs[i].first == -1) {
4687 MaskOps.push_back(-1);
4689 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4690 MaskOps.push_back(Idx);
4693 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4697 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
4698 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4699 SDValue V1 = Op.getOperand(0);
4700 SDValue V2 = Op.getOperand(1);
4701 EVT VT = Op.getValueType();
4702 DebugLoc dl = Op.getDebugLoc();
4703 unsigned NumElems = VT.getVectorNumElements();
4704 bool isMMX = VT.getSizeInBits() == 64;
4705 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4706 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4707 bool V1IsSplat = false;
4708 bool V2IsSplat = false;
4710 if (isZeroShuffle(SVOp))
4711 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4713 // Promote splats to v4f32.
4714 if (SVOp->isSplat()) {
4715 if (isMMX || NumElems < 4)
4717 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4720 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4722 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4723 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4724 if (NewOp.getNode())
4725 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4726 LowerVECTOR_SHUFFLE(NewOp, DAG));
4727 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4728 // FIXME: Figure out a cleaner way to do this.
4729 // Try to make use of movq to zero out the top part.
4730 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4731 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4732 if (NewOp.getNode()) {
4733 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4734 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4735 DAG, Subtarget, dl);
4737 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4738 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4739 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4740 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4741 DAG, Subtarget, dl);
4745 if (X86::isPSHUFDMask(SVOp))
4748 // Check if this can be converted into a logical shift.
4749 bool isLeft = false;
4752 bool isShift = getSubtarget()->hasSSE2() &&
4753 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4754 if (isShift && ShVal.hasOneUse()) {
4755 // If the shifted value has multiple uses, it may be cheaper to use
4756 // v_set0 + movlhps or movhlps, etc.
4757 EVT EltVT = VT.getVectorElementType();
4758 ShAmt *= EltVT.getSizeInBits();
4759 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4762 if (X86::isMOVLMask(SVOp)) {
4765 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4766 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4771 // FIXME: fold these into legal mask.
4772 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4773 X86::isMOVSLDUPMask(SVOp) ||
4774 X86::isMOVHLPSMask(SVOp) ||
4775 X86::isMOVLHPSMask(SVOp) ||
4776 X86::isMOVLPMask(SVOp)))
4779 if (ShouldXformToMOVHLPS(SVOp) ||
4780 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4781 return CommuteVectorShuffle(SVOp, DAG);
4784 // No better options. Use a vshl / vsrl.
4785 EVT EltVT = VT.getVectorElementType();
4786 ShAmt *= EltVT.getSizeInBits();
4787 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4790 bool Commuted = false;
4791 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4792 // 1,1,1,1 -> v8i16 though.
4793 V1IsSplat = isSplatVector(V1.getNode());
4794 V2IsSplat = isSplatVector(V2.getNode());
4796 // Canonicalize the splat or undef, if present, to be on the RHS.
4797 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4798 Op = CommuteVectorShuffle(SVOp, DAG);
4799 SVOp = cast<ShuffleVectorSDNode>(Op);
4800 V1 = SVOp->getOperand(0);
4801 V2 = SVOp->getOperand(1);
4802 std::swap(V1IsSplat, V2IsSplat);
4803 std::swap(V1IsUndef, V2IsUndef);
4807 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4808 // Shuffling low element of v1 into undef, just return v1.
4811 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4812 // the instruction selector will not match, so get a canonical MOVL with
4813 // swapped operands to undo the commute.
4814 return getMOVL(DAG, dl, VT, V2, V1);
4817 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4818 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4819 X86::isUNPCKLMask(SVOp) ||
4820 X86::isUNPCKHMask(SVOp))
4824 // Normalize mask so all entries that point to V2 points to its first
4825 // element then try to match unpck{h|l} again. If match, return a
4826 // new vector_shuffle with the corrected mask.
4827 SDValue NewMask = NormalizeMask(SVOp, DAG);
4828 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4829 if (NSVOp != SVOp) {
4830 if (X86::isUNPCKLMask(NSVOp, true)) {
4832 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4839 // Commute is back and try unpck* again.
4840 // FIXME: this seems wrong.
4841 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4842 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4843 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4844 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4845 X86::isUNPCKLMask(NewSVOp) ||
4846 X86::isUNPCKHMask(NewSVOp))
4850 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4852 // Normalize the node to match x86 shuffle ops if needed
4853 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4854 return CommuteVectorShuffle(SVOp, DAG);
4856 // Check for legal shuffle and return?
4857 SmallVector<int, 16> PermMask;
4858 SVOp->getMask(PermMask);
4859 if (isShuffleMaskLegal(PermMask, VT))
4862 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4863 if (VT == MVT::v8i16) {
4864 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4865 if (NewOp.getNode())
4869 if (VT == MVT::v16i8) {
4870 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4871 if (NewOp.getNode())
4875 // Handle all 4 wide cases with a number of shuffles except for MMX.
4876 if (NumElems == 4 && !isMMX)
4877 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4883 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4884 SelectionDAG &DAG) const {
4885 EVT VT = Op.getValueType();
4886 DebugLoc dl = Op.getDebugLoc();
4887 if (VT.getSizeInBits() == 8) {
4888 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4889 Op.getOperand(0), Op.getOperand(1));
4890 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4891 DAG.getValueType(VT));
4892 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4893 } else if (VT.getSizeInBits() == 16) {
4894 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4895 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4897 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4898 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4899 DAG.getNode(ISD::BIT_CONVERT, dl,
4903 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4904 Op.getOperand(0), Op.getOperand(1));
4905 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4906 DAG.getValueType(VT));
4907 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4908 } else if (VT == MVT::f32) {
4909 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4910 // the result back to FR32 register. It's only worth matching if the
4911 // result has a single use which is a store or a bitcast to i32. And in
4912 // the case of a store, it's not worth it if the index is a constant 0,
4913 // because a MOVSSmr can be used instead, which is smaller and faster.
4914 if (!Op.hasOneUse())
4916 SDNode *User = *Op.getNode()->use_begin();
4917 if ((User->getOpcode() != ISD::STORE ||
4918 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4919 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4920 (User->getOpcode() != ISD::BIT_CONVERT ||
4921 User->getValueType(0) != MVT::i32))
4923 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4924 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4927 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4928 } else if (VT == MVT::i32) {
4929 // ExtractPS works with constant index.
4930 if (isa<ConstantSDNode>(Op.getOperand(1)))
4938 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
4939 SelectionDAG &DAG) const {
4940 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4943 if (Subtarget->hasSSE41()) {
4944 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4949 EVT VT = Op.getValueType();
4950 DebugLoc dl = Op.getDebugLoc();
4951 // TODO: handle v16i8.
4952 if (VT.getSizeInBits() == 16) {
4953 SDValue Vec = Op.getOperand(0);
4954 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4956 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4957 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4958 DAG.getNode(ISD::BIT_CONVERT, dl,
4961 // Transform it so it match pextrw which produces a 32-bit result.
4962 EVT EltVT = MVT::i32;
4963 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4964 Op.getOperand(0), Op.getOperand(1));
4965 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4966 DAG.getValueType(VT));
4967 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4968 } else if (VT.getSizeInBits() == 32) {
4969 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4973 // SHUFPS the element to the lowest double word, then movss.
4974 int Mask[4] = { Idx, -1, -1, -1 };
4975 EVT VVT = Op.getOperand(0).getValueType();
4976 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4977 DAG.getUNDEF(VVT), Mask);
4978 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4979 DAG.getIntPtrConstant(0));
4980 } else if (VT.getSizeInBits() == 64) {
4981 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4982 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4983 // to match extract_elt for f64.
4984 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4988 // UNPCKHPD the element to the lowest double word, then movsd.
4989 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4990 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4991 int Mask[2] = { 1, -1 };
4992 EVT VVT = Op.getOperand(0).getValueType();
4993 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4994 DAG.getUNDEF(VVT), Mask);
4995 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4996 DAG.getIntPtrConstant(0));
5003 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5004 SelectionDAG &DAG) const {
5005 EVT VT = Op.getValueType();
5006 EVT EltVT = VT.getVectorElementType();
5007 DebugLoc dl = Op.getDebugLoc();
5009 SDValue N0 = Op.getOperand(0);
5010 SDValue N1 = Op.getOperand(1);
5011 SDValue N2 = Op.getOperand(2);
5013 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5014 isa<ConstantSDNode>(N2)) {
5016 if (VT == MVT::v8i16)
5017 Opc = X86ISD::PINSRW;
5018 else if (VT == MVT::v4i16)
5019 Opc = X86ISD::MMX_PINSRW;
5020 else if (VT == MVT::v16i8)
5021 Opc = X86ISD::PINSRB;
5023 Opc = X86ISD::PINSRB;
5025 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5027 if (N1.getValueType() != MVT::i32)
5028 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5029 if (N2.getValueType() != MVT::i32)
5030 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5031 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5032 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5033 // Bits [7:6] of the constant are the source select. This will always be
5034 // zero here. The DAG Combiner may combine an extract_elt index into these
5035 // bits. For example (insert (extract, 3), 2) could be matched by putting
5036 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5037 // Bits [5:4] of the constant are the destination select. This is the
5038 // value of the incoming immediate.
5039 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5040 // combine either bitwise AND or insert of float 0.0 to set these bits.
5041 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5042 // Create this as a scalar to vector..
5043 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5044 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5045 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5046 // PINSR* works with constant index.
5053 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5054 EVT VT = Op.getValueType();
5055 EVT EltVT = VT.getVectorElementType();
5057 if (Subtarget->hasSSE41())
5058 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5060 if (EltVT == MVT::i8)
5063 DebugLoc dl = Op.getDebugLoc();
5064 SDValue N0 = Op.getOperand(0);
5065 SDValue N1 = Op.getOperand(1);
5066 SDValue N2 = Op.getOperand(2);
5068 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5069 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5070 // as its second argument.
5071 if (N1.getValueType() != MVT::i32)
5072 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5073 if (N2.getValueType() != MVT::i32)
5074 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5075 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5076 dl, VT, N0, N1, N2);
5082 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5083 DebugLoc dl = Op.getDebugLoc();
5085 if (Op.getValueType() == MVT::v1i64 &&
5086 Op.getOperand(0).getValueType() == MVT::i64)
5087 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5089 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5090 EVT VT = MVT::v2i32;
5091 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5098 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5099 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5102 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5103 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5104 // one of the above mentioned nodes. It has to be wrapped because otherwise
5105 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5106 // be used to form addressing mode. These wrapped nodes will be selected
5109 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5110 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5112 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5114 unsigned char OpFlag = 0;
5115 unsigned WrapperKind = X86ISD::Wrapper;
5116 CodeModel::Model M = getTargetMachine().getCodeModel();
5118 if (Subtarget->isPICStyleRIPRel() &&
5119 (M == CodeModel::Small || M == CodeModel::Kernel))
5120 WrapperKind = X86ISD::WrapperRIP;
5121 else if (Subtarget->isPICStyleGOT())
5122 OpFlag = X86II::MO_GOTOFF;
5123 else if (Subtarget->isPICStyleStubPIC())
5124 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5126 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5128 CP->getOffset(), OpFlag);
5129 DebugLoc DL = CP->getDebugLoc();
5130 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5131 // With PIC, the address is actually $g + Offset.
5133 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5134 DAG.getNode(X86ISD::GlobalBaseReg,
5135 DebugLoc(), getPointerTy()),
5142 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5143 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5145 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5147 unsigned char OpFlag = 0;
5148 unsigned WrapperKind = X86ISD::Wrapper;
5149 CodeModel::Model M = getTargetMachine().getCodeModel();
5151 if (Subtarget->isPICStyleRIPRel() &&
5152 (M == CodeModel::Small || M == CodeModel::Kernel))
5153 WrapperKind = X86ISD::WrapperRIP;
5154 else if (Subtarget->isPICStyleGOT())
5155 OpFlag = X86II::MO_GOTOFF;
5156 else if (Subtarget->isPICStyleStubPIC())
5157 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5159 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5161 DebugLoc DL = JT->getDebugLoc();
5162 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5164 // With PIC, the address is actually $g + Offset.
5166 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5167 DAG.getNode(X86ISD::GlobalBaseReg,
5168 DebugLoc(), getPointerTy()),
5176 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5177 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5179 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5181 unsigned char OpFlag = 0;
5182 unsigned WrapperKind = X86ISD::Wrapper;
5183 CodeModel::Model M = getTargetMachine().getCodeModel();
5185 if (Subtarget->isPICStyleRIPRel() &&
5186 (M == CodeModel::Small || M == CodeModel::Kernel))
5187 WrapperKind = X86ISD::WrapperRIP;
5188 else if (Subtarget->isPICStyleGOT())
5189 OpFlag = X86II::MO_GOTOFF;
5190 else if (Subtarget->isPICStyleStubPIC())
5191 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5193 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5195 DebugLoc DL = Op.getDebugLoc();
5196 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5199 // With PIC, the address is actually $g + Offset.
5200 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5201 !Subtarget->is64Bit()) {
5202 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5203 DAG.getNode(X86ISD::GlobalBaseReg,
5204 DebugLoc(), getPointerTy()),
5212 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5213 // Create the TargetBlockAddressAddress node.
5214 unsigned char OpFlags =
5215 Subtarget->ClassifyBlockAddressReference();
5216 CodeModel::Model M = getTargetMachine().getCodeModel();
5217 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5218 DebugLoc dl = Op.getDebugLoc();
5219 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5220 /*isTarget=*/true, OpFlags);
5222 if (Subtarget->isPICStyleRIPRel() &&
5223 (M == CodeModel::Small || M == CodeModel::Kernel))
5224 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5226 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5228 // With PIC, the address is actually $g + Offset.
5229 if (isGlobalRelativeToPICBase(OpFlags)) {
5230 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5231 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5239 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5241 SelectionDAG &DAG) const {
5242 // Create the TargetGlobalAddress node, folding in the constant
5243 // offset if it is legal.
5244 unsigned char OpFlags =
5245 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5246 CodeModel::Model M = getTargetMachine().getCodeModel();
5248 if (OpFlags == X86II::MO_NO_FLAG &&
5249 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5250 // A direct static reference to a global.
5251 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5254 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
5257 if (Subtarget->isPICStyleRIPRel() &&
5258 (M == CodeModel::Small || M == CodeModel::Kernel))
5259 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5261 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5263 // With PIC, the address is actually $g + Offset.
5264 if (isGlobalRelativeToPICBase(OpFlags)) {
5265 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5266 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5270 // For globals that require a load from a stub to get the address, emit the
5272 if (isGlobalStubReference(OpFlags))
5273 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5274 PseudoSourceValue::getGOT(), 0, false, false, 0);
5276 // If there was a non-zero offset that we didn't fold, create an explicit
5279 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5280 DAG.getConstant(Offset, getPointerTy()));
5286 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
5287 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5288 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5289 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5293 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5294 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5295 unsigned char OperandFlags) {
5296 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5297 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5298 DebugLoc dl = GA->getDebugLoc();
5299 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5300 GA->getValueType(0),
5304 SDValue Ops[] = { Chain, TGA, *InFlag };
5305 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5307 SDValue Ops[] = { Chain, TGA };
5308 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5311 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5312 MFI->setAdjustsStack(true);
5314 SDValue Flag = Chain.getValue(1);
5315 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5318 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5320 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5323 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5324 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5325 DAG.getNode(X86ISD::GlobalBaseReg,
5326 DebugLoc(), PtrVT), InFlag);
5327 InFlag = Chain.getValue(1);
5329 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5332 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5334 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5336 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5337 X86::RAX, X86II::MO_TLSGD);
5340 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5341 // "local exec" model.
5342 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5343 const EVT PtrVT, TLSModel::Model model,
5345 DebugLoc dl = GA->getDebugLoc();
5346 // Get the Thread Pointer
5347 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5349 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5352 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5353 NULL, 0, false, false, 0);
5355 unsigned char OperandFlags = 0;
5356 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5358 unsigned WrapperKind = X86ISD::Wrapper;
5359 if (model == TLSModel::LocalExec) {
5360 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5361 } else if (is64Bit) {
5362 assert(model == TLSModel::InitialExec);
5363 OperandFlags = X86II::MO_GOTTPOFF;
5364 WrapperKind = X86ISD::WrapperRIP;
5366 assert(model == TLSModel::InitialExec);
5367 OperandFlags = X86II::MO_INDNTPOFF;
5370 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5372 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5373 GA->getValueType(0),
5374 GA->getOffset(), OperandFlags);
5375 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5377 if (model == TLSModel::InitialExec)
5378 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5379 PseudoSourceValue::getGOT(), 0, false, false, 0);
5381 // The address of the thread local variable is the add of the thread
5382 // pointer with the offset of the variable.
5383 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5387 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
5389 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5390 const GlobalValue *GV = GA->getGlobal();
5392 if (Subtarget->isTargetELF()) {
5393 // TODO: implement the "local dynamic" model
5394 // TODO: implement the "initial exec"model for pic executables
5396 // If GV is an alias then use the aliasee for determining
5397 // thread-localness.
5398 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5399 GV = GA->resolveAliasedGlobal(false);
5401 TLSModel::Model model
5402 = getTLSModel(GV, getTargetMachine().getRelocationModel());
5405 case TLSModel::GeneralDynamic:
5406 case TLSModel::LocalDynamic: // not implemented
5407 if (Subtarget->is64Bit())
5408 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5409 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5411 case TLSModel::InitialExec:
5412 case TLSModel::LocalExec:
5413 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5414 Subtarget->is64Bit());
5416 } else if (Subtarget->isTargetDarwin()) {
5417 // Darwin only has one model of TLS. Lower to that.
5418 unsigned char OpFlag = 0;
5419 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
5420 X86ISD::WrapperRIP : X86ISD::Wrapper;
5422 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5424 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
5425 !Subtarget->is64Bit();
5427 OpFlag = X86II::MO_TLVP_PIC_BASE;
5429 OpFlag = X86II::MO_TLVP;
5430 DebugLoc DL = Op.getDebugLoc();
5431 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
5433 GA->getOffset(), OpFlag);
5434 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5436 // With PIC32, the address is actually $g + Offset.
5438 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5439 DAG.getNode(X86ISD::GlobalBaseReg,
5440 DebugLoc(), getPointerTy()),
5443 // Lowering the machine isd will make sure everything is in the right
5445 SDValue Args[] = { Offset };
5446 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
5448 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
5449 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5450 MFI->setAdjustsStack(true);
5452 // And our return value (tls address) is in the standard call return value
5454 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
5455 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
5459 "TLS not implemented for this target.");
5461 llvm_unreachable("Unreachable");
5466 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5467 /// take a 2 x i32 value to shift plus a shift amount.
5468 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
5469 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5470 EVT VT = Op.getValueType();
5471 unsigned VTBits = VT.getSizeInBits();
5472 DebugLoc dl = Op.getDebugLoc();
5473 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5474 SDValue ShOpLo = Op.getOperand(0);
5475 SDValue ShOpHi = Op.getOperand(1);
5476 SDValue ShAmt = Op.getOperand(2);
5477 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5478 DAG.getConstant(VTBits - 1, MVT::i8))
5479 : DAG.getConstant(0, VT);
5482 if (Op.getOpcode() == ISD::SHL_PARTS) {
5483 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5484 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5486 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5487 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5490 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5491 DAG.getConstant(VTBits, MVT::i8));
5492 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5493 AndNode, DAG.getConstant(0, MVT::i8));
5496 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5497 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5498 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5500 if (Op.getOpcode() == ISD::SHL_PARTS) {
5501 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5502 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5504 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5505 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5508 SDValue Ops[2] = { Lo, Hi };
5509 return DAG.getMergeValues(Ops, 2, dl);
5512 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
5513 SelectionDAG &DAG) const {
5514 EVT SrcVT = Op.getOperand(0).getValueType();
5516 if (SrcVT.isVector()) {
5517 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5523 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5524 "Unknown SINT_TO_FP to lower!");
5526 // These are really Legal; return the operand so the caller accepts it as
5528 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5530 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5531 Subtarget->is64Bit()) {
5535 DebugLoc dl = Op.getDebugLoc();
5536 unsigned Size = SrcVT.getSizeInBits()/8;
5537 MachineFunction &MF = DAG.getMachineFunction();
5538 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5539 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5540 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5542 PseudoSourceValue::getFixedStack(SSFI), 0,
5544 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5547 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5549 SelectionDAG &DAG) const {
5551 DebugLoc dl = Op.getDebugLoc();
5553 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5555 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5557 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5558 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5559 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5560 Tys, Ops, array_lengthof(Ops));
5563 Chain = Result.getValue(1);
5564 SDValue InFlag = Result.getValue(2);
5566 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5567 // shouldn't be necessary except that RFP cannot be live across
5568 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5569 MachineFunction &MF = DAG.getMachineFunction();
5570 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5571 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5572 Tys = DAG.getVTList(MVT::Other);
5574 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5576 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5577 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5578 PseudoSourceValue::getFixedStack(SSFI), 0,
5585 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5586 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
5587 SelectionDAG &DAG) const {
5588 // This algorithm is not obvious. Here it is in C code, more or less:
5590 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5591 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5592 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5594 // Copy ints to xmm registers.
5595 __m128i xh = _mm_cvtsi32_si128( hi );
5596 __m128i xl = _mm_cvtsi32_si128( lo );
5598 // Combine into low half of a single xmm register.
5599 __m128i x = _mm_unpacklo_epi32( xh, xl );
5603 // Merge in appropriate exponents to give the integer bits the right
5605 x = _mm_unpacklo_epi32( x, exp );
5607 // Subtract away the biases to deal with the IEEE-754 double precision
5609 d = _mm_sub_pd( (__m128d) x, bias );
5611 // All conversions up to here are exact. The correctly rounded result is
5612 // calculated using the current rounding mode using the following
5614 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5615 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5616 // store doesn't really need to be here (except
5617 // maybe to zero the other double)
5622 DebugLoc dl = Op.getDebugLoc();
5623 LLVMContext *Context = DAG.getContext();
5625 // Build some magic constants.
5626 std::vector<Constant*> CV0;
5627 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5628 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5629 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5630 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5631 Constant *C0 = ConstantVector::get(CV0);
5632 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5634 std::vector<Constant*> CV1;
5636 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5638 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5639 Constant *C1 = ConstantVector::get(CV1);
5640 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5642 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5643 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5645 DAG.getIntPtrConstant(1)));
5646 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5647 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5649 DAG.getIntPtrConstant(0)));
5650 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5651 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5652 PseudoSourceValue::getConstantPool(), 0,
5654 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5655 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5656 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5657 PseudoSourceValue::getConstantPool(), 0,
5659 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5661 // Add the halves; easiest way is to swap them into another reg first.
5662 int ShufMask[2] = { 1, -1 };
5663 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5664 DAG.getUNDEF(MVT::v2f64), ShufMask);
5665 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5666 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5667 DAG.getIntPtrConstant(0));
5670 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5671 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
5672 SelectionDAG &DAG) const {
5673 DebugLoc dl = Op.getDebugLoc();
5674 // FP constant to bias correct the final result.
5675 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5678 // Load the 32-bit value into an XMM register.
5679 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5680 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5682 DAG.getIntPtrConstant(0)));
5684 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5685 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5686 DAG.getIntPtrConstant(0));
5688 // Or the load with the bias.
5689 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5690 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5691 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5693 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5694 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5695 MVT::v2f64, Bias)));
5696 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5697 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5698 DAG.getIntPtrConstant(0));
5700 // Subtract the bias.
5701 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5703 // Handle final rounding.
5704 EVT DestVT = Op.getValueType();
5706 if (DestVT.bitsLT(MVT::f64)) {
5707 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5708 DAG.getIntPtrConstant(0));
5709 } else if (DestVT.bitsGT(MVT::f64)) {
5710 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5713 // Handle final rounding.
5717 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
5718 SelectionDAG &DAG) const {
5719 SDValue N0 = Op.getOperand(0);
5720 DebugLoc dl = Op.getDebugLoc();
5722 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
5723 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5724 // the optimization here.
5725 if (DAG.SignBitIsZero(N0))
5726 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5728 EVT SrcVT = N0.getValueType();
5729 EVT DstVT = Op.getValueType();
5730 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
5731 return LowerUINT_TO_FP_i64(Op, DAG);
5732 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
5733 return LowerUINT_TO_FP_i32(Op, DAG);
5735 // Make a 64-bit buffer, and use it to build an FILD.
5736 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5737 if (SrcVT == MVT::i32) {
5738 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5739 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5740 getPointerTy(), StackSlot, WordOff);
5741 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5742 StackSlot, NULL, 0, false, false, 0);
5743 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5744 OffsetSlot, NULL, 0, false, false, 0);
5745 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5749 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
5750 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5751 StackSlot, NULL, 0, false, false, 0);
5752 // For i64 source, we need to add the appropriate power of 2 if the input
5753 // was negative. This is the same as the optimization in
5754 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
5755 // we must be careful to do the computation in x87 extended precision, not
5756 // in SSE. (The generic code can't know it's OK to do this, or how to.)
5757 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
5758 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
5759 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
5761 APInt FF(32, 0x5F800000ULL);
5763 // Check whether the sign bit is set.
5764 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
5765 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
5768 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
5769 SDValue FudgePtr = DAG.getConstantPool(
5770 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
5773 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
5774 SDValue Zero = DAG.getIntPtrConstant(0);
5775 SDValue Four = DAG.getIntPtrConstant(4);
5776 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
5778 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
5780 // Load the value out, extending it from f32 to f80.
5781 // FIXME: Avoid the extend by constructing the right constant pool?
5782 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
5783 FudgePtr, PseudoSourceValue::getConstantPool(),
5784 0, MVT::f32, false, false, 4);
5785 // Extend everything to 80 bits to force it to be done on x87.
5786 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
5787 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
5790 std::pair<SDValue,SDValue> X86TargetLowering::
5791 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
5792 DebugLoc dl = Op.getDebugLoc();
5794 EVT DstTy = Op.getValueType();
5797 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5801 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5802 DstTy.getSimpleVT() >= MVT::i16 &&
5803 "Unknown FP_TO_SINT to lower!");
5805 // These are really Legal.
5806 if (DstTy == MVT::i32 &&
5807 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5808 return std::make_pair(SDValue(), SDValue());
5809 if (Subtarget->is64Bit() &&
5810 DstTy == MVT::i64 &&
5811 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5812 return std::make_pair(SDValue(), SDValue());
5814 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5816 MachineFunction &MF = DAG.getMachineFunction();
5817 unsigned MemSize = DstTy.getSizeInBits()/8;
5818 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5819 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5822 switch (DstTy.getSimpleVT().SimpleTy) {
5823 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5824 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5825 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5826 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5829 SDValue Chain = DAG.getEntryNode();
5830 SDValue Value = Op.getOperand(0);
5831 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5832 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5833 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5834 PseudoSourceValue::getFixedStack(SSFI), 0,
5836 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5838 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5840 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5841 Chain = Value.getValue(1);
5842 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5843 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5846 // Build the FP_TO_INT*_IN_MEM
5847 SDValue Ops[] = { Chain, Value, StackSlot };
5848 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5850 return std::make_pair(FIST, StackSlot);
5853 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
5854 SelectionDAG &DAG) const {
5855 if (Op.getValueType().isVector()) {
5856 if (Op.getValueType() == MVT::v2i32 &&
5857 Op.getOperand(0).getValueType() == MVT::v2f64) {
5863 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5864 SDValue FIST = Vals.first, StackSlot = Vals.second;
5865 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5866 if (FIST.getNode() == 0) return Op;
5869 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5870 FIST, StackSlot, NULL, 0, false, false, 0);
5873 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
5874 SelectionDAG &DAG) const {
5875 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5876 SDValue FIST = Vals.first, StackSlot = Vals.second;
5877 assert(FIST.getNode() && "Unexpected failure");
5880 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5881 FIST, StackSlot, NULL, 0, false, false, 0);
5884 SDValue X86TargetLowering::LowerFABS(SDValue Op,
5885 SelectionDAG &DAG) const {
5886 LLVMContext *Context = DAG.getContext();
5887 DebugLoc dl = Op.getDebugLoc();
5888 EVT VT = Op.getValueType();
5891 EltVT = VT.getVectorElementType();
5892 std::vector<Constant*> CV;
5893 if (EltVT == MVT::f64) {
5894 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5898 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5904 Constant *C = ConstantVector::get(CV);
5905 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5906 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5907 PseudoSourceValue::getConstantPool(), 0,
5909 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5912 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
5913 LLVMContext *Context = DAG.getContext();
5914 DebugLoc dl = Op.getDebugLoc();
5915 EVT VT = Op.getValueType();
5918 EltVT = VT.getVectorElementType();
5919 std::vector<Constant*> CV;
5920 if (EltVT == MVT::f64) {
5921 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5925 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5931 Constant *C = ConstantVector::get(CV);
5932 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5933 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5934 PseudoSourceValue::getConstantPool(), 0,
5936 if (VT.isVector()) {
5937 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5938 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5939 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5941 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5943 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5947 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5948 LLVMContext *Context = DAG.getContext();
5949 SDValue Op0 = Op.getOperand(0);
5950 SDValue Op1 = Op.getOperand(1);
5951 DebugLoc dl = Op.getDebugLoc();
5952 EVT VT = Op.getValueType();
5953 EVT SrcVT = Op1.getValueType();
5955 // If second operand is smaller, extend it first.
5956 if (SrcVT.bitsLT(VT)) {
5957 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5960 // And if it is bigger, shrink it first.
5961 if (SrcVT.bitsGT(VT)) {
5962 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5966 // At this point the operands and the result should have the same
5967 // type, and that won't be f80 since that is not custom lowered.
5969 // First get the sign bit of second operand.
5970 std::vector<Constant*> CV;
5971 if (SrcVT == MVT::f64) {
5972 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5973 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5975 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5976 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5977 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5978 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5980 Constant *C = ConstantVector::get(CV);
5981 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5982 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5983 PseudoSourceValue::getConstantPool(), 0,
5985 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5987 // Shift sign bit right or left if the two operands have different types.
5988 if (SrcVT.bitsGT(VT)) {
5989 // Op0 is MVT::f32, Op1 is MVT::f64.
5990 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5991 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5992 DAG.getConstant(32, MVT::i32));
5993 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5994 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5995 DAG.getIntPtrConstant(0));
5998 // Clear first operand sign bit.
6000 if (VT == MVT::f64) {
6001 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6002 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6005 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6006 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6007 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6009 C = ConstantVector::get(CV);
6010 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6011 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6012 PseudoSourceValue::getConstantPool(), 0,
6014 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6016 // Or the value with the sign bit.
6017 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6020 /// Emit nodes that will be selected as "test Op0,Op0", or something
6022 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6023 SelectionDAG &DAG) const {
6024 DebugLoc dl = Op.getDebugLoc();
6026 // CF and OF aren't always set the way we want. Determine which
6027 // of these we need.
6028 bool NeedCF = false;
6029 bool NeedOF = false;
6032 case X86::COND_A: case X86::COND_AE:
6033 case X86::COND_B: case X86::COND_BE:
6036 case X86::COND_G: case X86::COND_GE:
6037 case X86::COND_L: case X86::COND_LE:
6038 case X86::COND_O: case X86::COND_NO:
6043 // See if we can use the EFLAGS value from the operand instead of
6044 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6045 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6046 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6047 // Emit a CMP with 0, which is the TEST pattern.
6048 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6049 DAG.getConstant(0, Op.getValueType()));
6051 unsigned Opcode = 0;
6052 unsigned NumOperands = 0;
6053 switch (Op.getNode()->getOpcode()) {
6055 // Due to an isel shortcoming, be conservative if this add is likely to be
6056 // selected as part of a load-modify-store instruction. When the root node
6057 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6058 // uses of other nodes in the match, such as the ADD in this case. This
6059 // leads to the ADD being left around and reselected, with the result being
6060 // two adds in the output. Alas, even if none our users are stores, that
6061 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6062 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6063 // climbing the DAG back to the root, and it doesn't seem to be worth the
6065 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6066 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6067 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6070 if (ConstantSDNode *C =
6071 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6072 // An add of one will be selected as an INC.
6073 if (C->getAPIntValue() == 1) {
6074 Opcode = X86ISD::INC;
6079 // An add of negative one (subtract of one) will be selected as a DEC.
6080 if (C->getAPIntValue().isAllOnesValue()) {
6081 Opcode = X86ISD::DEC;
6087 // Otherwise use a regular EFLAGS-setting add.
6088 Opcode = X86ISD::ADD;
6092 // If the primary and result isn't used, don't bother using X86ISD::AND,
6093 // because a TEST instruction will be better.
6094 bool NonFlagUse = false;
6095 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6096 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6098 unsigned UOpNo = UI.getOperandNo();
6099 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6100 // Look pass truncate.
6101 UOpNo = User->use_begin().getOperandNo();
6102 User = *User->use_begin();
6105 if (User->getOpcode() != ISD::BRCOND &&
6106 User->getOpcode() != ISD::SETCC &&
6107 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6120 // Due to the ISEL shortcoming noted above, be conservative if this op is
6121 // likely to be selected as part of a load-modify-store instruction.
6122 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6123 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6124 if (UI->getOpcode() == ISD::STORE)
6127 // Otherwise use a regular EFLAGS-setting instruction.
6128 switch (Op.getNode()->getOpcode()) {
6129 default: llvm_unreachable("unexpected operator!");
6130 case ISD::SUB: Opcode = X86ISD::SUB; break;
6131 case ISD::OR: Opcode = X86ISD::OR; break;
6132 case ISD::XOR: Opcode = X86ISD::XOR; break;
6133 case ISD::AND: Opcode = X86ISD::AND; break;
6145 return SDValue(Op.getNode(), 1);
6152 // Emit a CMP with 0, which is the TEST pattern.
6153 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6154 DAG.getConstant(0, Op.getValueType()));
6156 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6157 SmallVector<SDValue, 4> Ops;
6158 for (unsigned i = 0; i != NumOperands; ++i)
6159 Ops.push_back(Op.getOperand(i));
6161 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6162 DAG.ReplaceAllUsesWith(Op, New);
6163 return SDValue(New.getNode(), 1);
6166 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6168 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6169 SelectionDAG &DAG) const {
6170 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6171 if (C->getAPIntValue() == 0)
6172 return EmitTest(Op0, X86CC, DAG);
6174 DebugLoc dl = Op0.getDebugLoc();
6175 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6178 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6179 /// if it's possible.
6180 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6181 DebugLoc dl, SelectionDAG &DAG) const {
6182 SDValue Op0 = And.getOperand(0);
6183 SDValue Op1 = And.getOperand(1);
6184 if (Op0.getOpcode() == ISD::TRUNCATE)
6185 Op0 = Op0.getOperand(0);
6186 if (Op1.getOpcode() == ISD::TRUNCATE)
6187 Op1 = Op1.getOperand(0);
6190 if (Op1.getOpcode() == ISD::SHL)
6191 std::swap(Op0, Op1);
6192 if (Op0.getOpcode() == ISD::SHL) {
6193 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6194 if (And00C->getZExtValue() == 1) {
6195 // If we looked past a truncate, check that it's only truncating away
6197 unsigned BitWidth = Op0.getValueSizeInBits();
6198 unsigned AndBitWidth = And.getValueSizeInBits();
6199 if (BitWidth > AndBitWidth) {
6200 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6201 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6202 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6206 RHS = Op0.getOperand(1);
6208 } else if (Op1.getOpcode() == ISD::Constant) {
6209 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6210 SDValue AndLHS = Op0;
6211 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6212 LHS = AndLHS.getOperand(0);
6213 RHS = AndLHS.getOperand(1);
6217 if (LHS.getNode()) {
6218 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6219 // instruction. Since the shift amount is in-range-or-undefined, we know
6220 // that doing a bittest on the i32 value is ok. We extend to i32 because
6221 // the encoding for the i16 version is larger than the i32 version.
6222 // Also promote i16 to i32 for performance / code size reason.
6223 if (LHS.getValueType() == MVT::i8 ||
6224 LHS.getValueType() == MVT::i16)
6225 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6227 // If the operand types disagree, extend the shift amount to match. Since
6228 // BT ignores high bits (like shifts) we can use anyextend.
6229 if (LHS.getValueType() != RHS.getValueType())
6230 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6232 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6233 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6234 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6235 DAG.getConstant(Cond, MVT::i8), BT);
6241 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6242 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6243 SDValue Op0 = Op.getOperand(0);
6244 SDValue Op1 = Op.getOperand(1);
6245 DebugLoc dl = Op.getDebugLoc();
6246 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6248 // Optimize to BT if possible.
6249 // Lower (X & (1 << N)) == 0 to BT(X, N).
6250 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
6251 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
6252 if (Op0.getOpcode() == ISD::AND &&
6254 Op1.getOpcode() == ISD::Constant &&
6255 cast<ConstantSDNode>(Op1)->isNullValue() &&
6256 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6257 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
6258 if (NewSetCC.getNode())
6262 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
6263 if (Op0.getOpcode() == X86ISD::SETCC &&
6264 Op1.getOpcode() == ISD::Constant &&
6265 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
6266 cast<ConstantSDNode>(Op1)->isNullValue()) &&
6267 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6268 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
6269 bool Invert = (CC == ISD::SETNE) ^
6270 cast<ConstantSDNode>(Op1)->isNullValue();
6272 CCode = X86::GetOppositeBranchCondition(CCode);
6273 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6274 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
6277 bool isFP = Op1.getValueType().isFloatingPoint();
6278 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
6279 if (X86CC == X86::COND_INVALID)
6282 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
6284 // Use sbb x, x to materialize carry bit into a GPR.
6285 if (X86CC == X86::COND_B)
6286 return DAG.getNode(ISD::AND, dl, MVT::i8,
6287 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6288 DAG.getConstant(X86CC, MVT::i8), Cond),
6289 DAG.getConstant(1, MVT::i8));
6291 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6292 DAG.getConstant(X86CC, MVT::i8), Cond);
6295 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
6297 SDValue Op0 = Op.getOperand(0);
6298 SDValue Op1 = Op.getOperand(1);
6299 SDValue CC = Op.getOperand(2);
6300 EVT VT = Op.getValueType();
6301 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6302 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6303 DebugLoc dl = Op.getDebugLoc();
6307 EVT VT0 = Op0.getValueType();
6308 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6309 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6312 switch (SetCCOpcode) {
6315 case ISD::SETEQ: SSECC = 0; break;
6317 case ISD::SETGT: Swap = true; // Fallthrough
6319 case ISD::SETOLT: SSECC = 1; break;
6321 case ISD::SETGE: Swap = true; // Fallthrough
6323 case ISD::SETOLE: SSECC = 2; break;
6324 case ISD::SETUO: SSECC = 3; break;
6326 case ISD::SETNE: SSECC = 4; break;
6327 case ISD::SETULE: Swap = true;
6328 case ISD::SETUGE: SSECC = 5; break;
6329 case ISD::SETULT: Swap = true;
6330 case ISD::SETUGT: SSECC = 6; break;
6331 case ISD::SETO: SSECC = 7; break;
6334 std::swap(Op0, Op1);
6336 // In the two special cases we can't handle, emit two comparisons.
6338 if (SetCCOpcode == ISD::SETUEQ) {
6340 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6341 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6342 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6344 else if (SetCCOpcode == ISD::SETONE) {
6346 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6347 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6348 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6350 llvm_unreachable("Illegal FP comparison");
6352 // Handle all other FP comparisons here.
6353 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6356 // We are handling one of the integer comparisons here. Since SSE only has
6357 // GT and EQ comparisons for integer, swapping operands and multiple
6358 // operations may be required for some comparisons.
6359 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6360 bool Swap = false, Invert = false, FlipSigns = false;
6362 switch (VT.getSimpleVT().SimpleTy) {
6365 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6367 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6369 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6370 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6373 switch (SetCCOpcode) {
6375 case ISD::SETNE: Invert = true;
6376 case ISD::SETEQ: Opc = EQOpc; break;
6377 case ISD::SETLT: Swap = true;
6378 case ISD::SETGT: Opc = GTOpc; break;
6379 case ISD::SETGE: Swap = true;
6380 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6381 case ISD::SETULT: Swap = true;
6382 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6383 case ISD::SETUGE: Swap = true;
6384 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6387 std::swap(Op0, Op1);
6389 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6390 // bits of the inputs before performing those operations.
6392 EVT EltVT = VT.getVectorElementType();
6393 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6395 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6396 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6398 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6399 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6402 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6404 // If the logical-not of the result is required, perform that now.
6406 Result = DAG.getNOT(dl, Result, VT);
6411 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6412 static bool isX86LogicalCmp(SDValue Op) {
6413 unsigned Opc = Op.getNode()->getOpcode();
6414 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6416 if (Op.getResNo() == 1 &&
6417 (Opc == X86ISD::ADD ||
6418 Opc == X86ISD::SUB ||
6419 Opc == X86ISD::SMUL ||
6420 Opc == X86ISD::UMUL ||
6421 Opc == X86ISD::INC ||
6422 Opc == X86ISD::DEC ||
6423 Opc == X86ISD::OR ||
6424 Opc == X86ISD::XOR ||
6425 Opc == X86ISD::AND))
6431 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
6432 bool addTest = true;
6433 SDValue Cond = Op.getOperand(0);
6434 DebugLoc dl = Op.getDebugLoc();
6437 if (Cond.getOpcode() == ISD::SETCC) {
6438 SDValue NewCond = LowerSETCC(Cond, DAG);
6439 if (NewCond.getNode())
6443 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6444 SDValue Op1 = Op.getOperand(1);
6445 SDValue Op2 = Op.getOperand(2);
6446 if (Cond.getOpcode() == X86ISD::SETCC &&
6447 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6448 SDValue Cmp = Cond.getOperand(1);
6449 if (Cmp.getOpcode() == X86ISD::CMP) {
6450 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6451 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6452 ConstantSDNode *RHSC =
6453 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6454 if (N1C && N1C->isAllOnesValue() &&
6455 N2C && N2C->isNullValue() &&
6456 RHSC && RHSC->isNullValue()) {
6457 SDValue CmpOp0 = Cmp.getOperand(0);
6458 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6459 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6460 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6461 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6466 // Look pass (and (setcc_carry (cmp ...)), 1).
6467 if (Cond.getOpcode() == ISD::AND &&
6468 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6469 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6470 if (C && C->getAPIntValue() == 1)
6471 Cond = Cond.getOperand(0);
6474 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6475 // setting operand in place of the X86ISD::SETCC.
6476 if (Cond.getOpcode() == X86ISD::SETCC ||
6477 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6478 CC = Cond.getOperand(0);
6480 SDValue Cmp = Cond.getOperand(1);
6481 unsigned Opc = Cmp.getOpcode();
6482 EVT VT = Op.getValueType();
6484 bool IllegalFPCMov = false;
6485 if (VT.isFloatingPoint() && !VT.isVector() &&
6486 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6487 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6489 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6490 Opc == X86ISD::BT) { // FIXME
6497 // Look pass the truncate.
6498 if (Cond.getOpcode() == ISD::TRUNCATE)
6499 Cond = Cond.getOperand(0);
6501 // We know the result of AND is compared against zero. Try to match
6503 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6504 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6505 if (NewSetCC.getNode()) {
6506 CC = NewSetCC.getOperand(0);
6507 Cond = NewSetCC.getOperand(1);
6514 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6515 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6518 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6519 // condition is true.
6520 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6521 SDValue Ops[] = { Op2, Op1, CC, Cond };
6522 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6525 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6526 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6527 // from the AND / OR.
6528 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6529 Opc = Op.getOpcode();
6530 if (Opc != ISD::OR && Opc != ISD::AND)
6532 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6533 Op.getOperand(0).hasOneUse() &&
6534 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6535 Op.getOperand(1).hasOneUse());
6538 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6539 // 1 and that the SETCC node has a single use.
6540 static bool isXor1OfSetCC(SDValue Op) {
6541 if (Op.getOpcode() != ISD::XOR)
6543 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6544 if (N1C && N1C->getAPIntValue() == 1) {
6545 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6546 Op.getOperand(0).hasOneUse();
6551 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
6552 bool addTest = true;
6553 SDValue Chain = Op.getOperand(0);
6554 SDValue Cond = Op.getOperand(1);
6555 SDValue Dest = Op.getOperand(2);
6556 DebugLoc dl = Op.getDebugLoc();
6559 if (Cond.getOpcode() == ISD::SETCC) {
6560 SDValue NewCond = LowerSETCC(Cond, DAG);
6561 if (NewCond.getNode())
6565 // FIXME: LowerXALUO doesn't handle these!!
6566 else if (Cond.getOpcode() == X86ISD::ADD ||
6567 Cond.getOpcode() == X86ISD::SUB ||
6568 Cond.getOpcode() == X86ISD::SMUL ||
6569 Cond.getOpcode() == X86ISD::UMUL)
6570 Cond = LowerXALUO(Cond, DAG);
6573 // Look pass (and (setcc_carry (cmp ...)), 1).
6574 if (Cond.getOpcode() == ISD::AND &&
6575 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6576 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6577 if (C && C->getAPIntValue() == 1)
6578 Cond = Cond.getOperand(0);
6581 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6582 // setting operand in place of the X86ISD::SETCC.
6583 if (Cond.getOpcode() == X86ISD::SETCC ||
6584 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6585 CC = Cond.getOperand(0);
6587 SDValue Cmp = Cond.getOperand(1);
6588 unsigned Opc = Cmp.getOpcode();
6589 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6590 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6594 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6598 // These can only come from an arithmetic instruction with overflow,
6599 // e.g. SADDO, UADDO.
6600 Cond = Cond.getNode()->getOperand(1);
6607 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6608 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6609 if (CondOpc == ISD::OR) {
6610 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6611 // two branches instead of an explicit OR instruction with a
6613 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6614 isX86LogicalCmp(Cmp)) {
6615 CC = Cond.getOperand(0).getOperand(0);
6616 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6617 Chain, Dest, CC, Cmp);
6618 CC = Cond.getOperand(1).getOperand(0);
6622 } else { // ISD::AND
6623 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6624 // two branches instead of an explicit AND instruction with a
6625 // separate test. However, we only do this if this block doesn't
6626 // have a fall-through edge, because this requires an explicit
6627 // jmp when the condition is false.
6628 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6629 isX86LogicalCmp(Cmp) &&
6630 Op.getNode()->hasOneUse()) {
6631 X86::CondCode CCode =
6632 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6633 CCode = X86::GetOppositeBranchCondition(CCode);
6634 CC = DAG.getConstant(CCode, MVT::i8);
6635 SDNode *User = *Op.getNode()->use_begin();
6636 // Look for an unconditional branch following this conditional branch.
6637 // We need this because we need to reverse the successors in order
6638 // to implement FCMP_OEQ.
6639 if (User->getOpcode() == ISD::BR) {
6640 SDValue FalseBB = User->getOperand(1);
6642 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
6643 assert(NewBR == User);
6647 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6648 Chain, Dest, CC, Cmp);
6649 X86::CondCode CCode =
6650 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6651 CCode = X86::GetOppositeBranchCondition(CCode);
6652 CC = DAG.getConstant(CCode, MVT::i8);
6658 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6659 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6660 // It should be transformed during dag combiner except when the condition
6661 // is set by a arithmetics with overflow node.
6662 X86::CondCode CCode =
6663 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6664 CCode = X86::GetOppositeBranchCondition(CCode);
6665 CC = DAG.getConstant(CCode, MVT::i8);
6666 Cond = Cond.getOperand(0).getOperand(1);
6672 // Look pass the truncate.
6673 if (Cond.getOpcode() == ISD::TRUNCATE)
6674 Cond = Cond.getOperand(0);
6676 // We know the result of AND is compared against zero. Try to match
6678 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6679 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6680 if (NewSetCC.getNode()) {
6681 CC = NewSetCC.getOperand(0);
6682 Cond = NewSetCC.getOperand(1);
6689 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6690 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6692 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6693 Chain, Dest, CC, Cond);
6697 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6698 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6699 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6700 // that the guard pages used by the OS virtual memory manager are allocated in
6701 // correct sequence.
6703 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6704 SelectionDAG &DAG) const {
6705 assert(Subtarget->isTargetCygMing() &&
6706 "This should be used only on Cygwin/Mingw targets");
6707 DebugLoc dl = Op.getDebugLoc();
6710 SDValue Chain = Op.getOperand(0);
6711 SDValue Size = Op.getOperand(1);
6712 // FIXME: Ensure alignment here
6716 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6718 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6719 Flag = Chain.getValue(1);
6721 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6723 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6724 Flag = Chain.getValue(1);
6726 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6728 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6729 return DAG.getMergeValues(Ops1, 2, dl);
6732 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
6733 MachineFunction &MF = DAG.getMachineFunction();
6734 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
6736 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6737 DebugLoc dl = Op.getDebugLoc();
6739 if (!Subtarget->is64Bit()) {
6740 // vastart just stores the address of the VarArgsFrameIndex slot into the
6741 // memory location argument.
6742 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6744 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6749 // gp_offset (0 - 6 * 8)
6750 // fp_offset (48 - 48 + 8 * 16)
6751 // overflow_arg_area (point to parameters coming in memory).
6753 SmallVector<SDValue, 8> MemOps;
6754 SDValue FIN = Op.getOperand(1);
6756 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6757 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
6759 FIN, SV, 0, false, false, 0);
6760 MemOps.push_back(Store);
6763 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6764 FIN, DAG.getIntPtrConstant(4));
6765 Store = DAG.getStore(Op.getOperand(0), dl,
6766 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
6768 FIN, SV, 0, false, false, 0);
6769 MemOps.push_back(Store);
6771 // Store ptr to overflow_arg_area
6772 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6773 FIN, DAG.getIntPtrConstant(4));
6774 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6776 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0,
6778 MemOps.push_back(Store);
6780 // Store ptr to reg_save_area.
6781 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6782 FIN, DAG.getIntPtrConstant(8));
6783 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
6785 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0,
6787 MemOps.push_back(Store);
6788 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6789 &MemOps[0], MemOps.size());
6792 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
6793 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6794 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6796 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
6800 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
6801 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6802 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6803 SDValue Chain = Op.getOperand(0);
6804 SDValue DstPtr = Op.getOperand(1);
6805 SDValue SrcPtr = Op.getOperand(2);
6806 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6807 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6808 DebugLoc dl = Op.getDebugLoc();
6810 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6811 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
6812 false, DstSV, 0, SrcSV, 0);
6816 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
6817 DebugLoc dl = Op.getDebugLoc();
6818 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6820 default: return SDValue(); // Don't custom lower most intrinsics.
6821 // Comparison intrinsics.
6822 case Intrinsic::x86_sse_comieq_ss:
6823 case Intrinsic::x86_sse_comilt_ss:
6824 case Intrinsic::x86_sse_comile_ss:
6825 case Intrinsic::x86_sse_comigt_ss:
6826 case Intrinsic::x86_sse_comige_ss:
6827 case Intrinsic::x86_sse_comineq_ss:
6828 case Intrinsic::x86_sse_ucomieq_ss:
6829 case Intrinsic::x86_sse_ucomilt_ss:
6830 case Intrinsic::x86_sse_ucomile_ss:
6831 case Intrinsic::x86_sse_ucomigt_ss:
6832 case Intrinsic::x86_sse_ucomige_ss:
6833 case Intrinsic::x86_sse_ucomineq_ss:
6834 case Intrinsic::x86_sse2_comieq_sd:
6835 case Intrinsic::x86_sse2_comilt_sd:
6836 case Intrinsic::x86_sse2_comile_sd:
6837 case Intrinsic::x86_sse2_comigt_sd:
6838 case Intrinsic::x86_sse2_comige_sd:
6839 case Intrinsic::x86_sse2_comineq_sd:
6840 case Intrinsic::x86_sse2_ucomieq_sd:
6841 case Intrinsic::x86_sse2_ucomilt_sd:
6842 case Intrinsic::x86_sse2_ucomile_sd:
6843 case Intrinsic::x86_sse2_ucomigt_sd:
6844 case Intrinsic::x86_sse2_ucomige_sd:
6845 case Intrinsic::x86_sse2_ucomineq_sd: {
6847 ISD::CondCode CC = ISD::SETCC_INVALID;
6850 case Intrinsic::x86_sse_comieq_ss:
6851 case Intrinsic::x86_sse2_comieq_sd:
6855 case Intrinsic::x86_sse_comilt_ss:
6856 case Intrinsic::x86_sse2_comilt_sd:
6860 case Intrinsic::x86_sse_comile_ss:
6861 case Intrinsic::x86_sse2_comile_sd:
6865 case Intrinsic::x86_sse_comigt_ss:
6866 case Intrinsic::x86_sse2_comigt_sd:
6870 case Intrinsic::x86_sse_comige_ss:
6871 case Intrinsic::x86_sse2_comige_sd:
6875 case Intrinsic::x86_sse_comineq_ss:
6876 case Intrinsic::x86_sse2_comineq_sd:
6880 case Intrinsic::x86_sse_ucomieq_ss:
6881 case Intrinsic::x86_sse2_ucomieq_sd:
6882 Opc = X86ISD::UCOMI;
6885 case Intrinsic::x86_sse_ucomilt_ss:
6886 case Intrinsic::x86_sse2_ucomilt_sd:
6887 Opc = X86ISD::UCOMI;
6890 case Intrinsic::x86_sse_ucomile_ss:
6891 case Intrinsic::x86_sse2_ucomile_sd:
6892 Opc = X86ISD::UCOMI;
6895 case Intrinsic::x86_sse_ucomigt_ss:
6896 case Intrinsic::x86_sse2_ucomigt_sd:
6897 Opc = X86ISD::UCOMI;
6900 case Intrinsic::x86_sse_ucomige_ss:
6901 case Intrinsic::x86_sse2_ucomige_sd:
6902 Opc = X86ISD::UCOMI;
6905 case Intrinsic::x86_sse_ucomineq_ss:
6906 case Intrinsic::x86_sse2_ucomineq_sd:
6907 Opc = X86ISD::UCOMI;
6912 SDValue LHS = Op.getOperand(1);
6913 SDValue RHS = Op.getOperand(2);
6914 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6915 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6916 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6917 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6918 DAG.getConstant(X86CC, MVT::i8), Cond);
6919 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6921 // ptest intrinsics. The intrinsic these come from are designed to return
6922 // an integer value, not just an instruction so lower it to the ptest
6923 // pattern and a setcc for the result.
6924 case Intrinsic::x86_sse41_ptestz:
6925 case Intrinsic::x86_sse41_ptestc:
6926 case Intrinsic::x86_sse41_ptestnzc:{
6929 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6930 case Intrinsic::x86_sse41_ptestz:
6932 X86CC = X86::COND_E;
6934 case Intrinsic::x86_sse41_ptestc:
6936 X86CC = X86::COND_B;
6938 case Intrinsic::x86_sse41_ptestnzc:
6940 X86CC = X86::COND_A;
6944 SDValue LHS = Op.getOperand(1);
6945 SDValue RHS = Op.getOperand(2);
6946 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6947 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6948 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6949 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6952 // Fix vector shift instructions where the last operand is a non-immediate
6954 case Intrinsic::x86_sse2_pslli_w:
6955 case Intrinsic::x86_sse2_pslli_d:
6956 case Intrinsic::x86_sse2_pslli_q:
6957 case Intrinsic::x86_sse2_psrli_w:
6958 case Intrinsic::x86_sse2_psrli_d:
6959 case Intrinsic::x86_sse2_psrli_q:
6960 case Intrinsic::x86_sse2_psrai_w:
6961 case Intrinsic::x86_sse2_psrai_d:
6962 case Intrinsic::x86_mmx_pslli_w:
6963 case Intrinsic::x86_mmx_pslli_d:
6964 case Intrinsic::x86_mmx_pslli_q:
6965 case Intrinsic::x86_mmx_psrli_w:
6966 case Intrinsic::x86_mmx_psrli_d:
6967 case Intrinsic::x86_mmx_psrli_q:
6968 case Intrinsic::x86_mmx_psrai_w:
6969 case Intrinsic::x86_mmx_psrai_d: {
6970 SDValue ShAmt = Op.getOperand(2);
6971 if (isa<ConstantSDNode>(ShAmt))
6974 unsigned NewIntNo = 0;
6975 EVT ShAmtVT = MVT::v4i32;
6977 case Intrinsic::x86_sse2_pslli_w:
6978 NewIntNo = Intrinsic::x86_sse2_psll_w;
6980 case Intrinsic::x86_sse2_pslli_d:
6981 NewIntNo = Intrinsic::x86_sse2_psll_d;
6983 case Intrinsic::x86_sse2_pslli_q:
6984 NewIntNo = Intrinsic::x86_sse2_psll_q;
6986 case Intrinsic::x86_sse2_psrli_w:
6987 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6989 case Intrinsic::x86_sse2_psrli_d:
6990 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6992 case Intrinsic::x86_sse2_psrli_q:
6993 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6995 case Intrinsic::x86_sse2_psrai_w:
6996 NewIntNo = Intrinsic::x86_sse2_psra_w;
6998 case Intrinsic::x86_sse2_psrai_d:
6999 NewIntNo = Intrinsic::x86_sse2_psra_d;
7002 ShAmtVT = MVT::v2i32;
7004 case Intrinsic::x86_mmx_pslli_w:
7005 NewIntNo = Intrinsic::x86_mmx_psll_w;
7007 case Intrinsic::x86_mmx_pslli_d:
7008 NewIntNo = Intrinsic::x86_mmx_psll_d;
7010 case Intrinsic::x86_mmx_pslli_q:
7011 NewIntNo = Intrinsic::x86_mmx_psll_q;
7013 case Intrinsic::x86_mmx_psrli_w:
7014 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7016 case Intrinsic::x86_mmx_psrli_d:
7017 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7019 case Intrinsic::x86_mmx_psrli_q:
7020 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7022 case Intrinsic::x86_mmx_psrai_w:
7023 NewIntNo = Intrinsic::x86_mmx_psra_w;
7025 case Intrinsic::x86_mmx_psrai_d:
7026 NewIntNo = Intrinsic::x86_mmx_psra_d;
7028 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7034 // The vector shift intrinsics with scalars uses 32b shift amounts but
7035 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7039 ShOps[1] = DAG.getConstant(0, MVT::i32);
7040 if (ShAmtVT == MVT::v4i32) {
7041 ShOps[2] = DAG.getUNDEF(MVT::i32);
7042 ShOps[3] = DAG.getUNDEF(MVT::i32);
7043 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7045 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7048 EVT VT = Op.getValueType();
7049 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7050 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7051 DAG.getConstant(NewIntNo, MVT::i32),
7052 Op.getOperand(1), ShAmt);
7057 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7058 SelectionDAG &DAG) const {
7059 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7060 MFI->setReturnAddressIsTaken(true);
7062 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7063 DebugLoc dl = Op.getDebugLoc();
7066 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7068 DAG.getConstant(TD->getPointerSize(),
7069 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7070 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7071 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7073 NULL, 0, false, false, 0);
7076 // Just load the return address.
7077 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7078 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7079 RetAddrFI, NULL, 0, false, false, 0);
7082 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7083 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7084 MFI->setFrameAddressIsTaken(true);
7086 EVT VT = Op.getValueType();
7087 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7088 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7089 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7090 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7092 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7097 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7098 SelectionDAG &DAG) const {
7099 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7102 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7103 MachineFunction &MF = DAG.getMachineFunction();
7104 SDValue Chain = Op.getOperand(0);
7105 SDValue Offset = Op.getOperand(1);
7106 SDValue Handler = Op.getOperand(2);
7107 DebugLoc dl = Op.getDebugLoc();
7109 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7111 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7113 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7114 DAG.getIntPtrConstant(-TD->getPointerSize()));
7115 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7116 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7117 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7118 MF.getRegInfo().addLiveOut(StoreAddrReg);
7120 return DAG.getNode(X86ISD::EH_RETURN, dl,
7122 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7125 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7126 SelectionDAG &DAG) const {
7127 SDValue Root = Op.getOperand(0);
7128 SDValue Trmp = Op.getOperand(1); // trampoline
7129 SDValue FPtr = Op.getOperand(2); // nested function
7130 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7131 DebugLoc dl = Op.getDebugLoc();
7133 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7135 if (Subtarget->is64Bit()) {
7136 SDValue OutChains[6];
7138 // Large code-model.
7139 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7140 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7142 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7143 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7145 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7147 // Load the pointer to the nested function into R11.
7148 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7149 SDValue Addr = Trmp;
7150 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7151 Addr, TrmpAddr, 0, false, false, 0);
7153 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7154 DAG.getConstant(2, MVT::i64));
7155 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7158 // Load the 'nest' parameter value into R10.
7159 // R10 is specified in X86CallingConv.td
7160 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7161 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7162 DAG.getConstant(10, MVT::i64));
7163 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7164 Addr, TrmpAddr, 10, false, false, 0);
7166 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7167 DAG.getConstant(12, MVT::i64));
7168 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7171 // Jump to the nested function.
7172 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7173 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7174 DAG.getConstant(20, MVT::i64));
7175 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7176 Addr, TrmpAddr, 20, false, false, 0);
7178 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7179 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7180 DAG.getConstant(22, MVT::i64));
7181 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7182 TrmpAddr, 22, false, false, 0);
7185 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7186 return DAG.getMergeValues(Ops, 2, dl);
7188 const Function *Func =
7189 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7190 CallingConv::ID CC = Func->getCallingConv();
7195 llvm_unreachable("Unsupported calling convention");
7196 case CallingConv::C:
7197 case CallingConv::X86_StdCall: {
7198 // Pass 'nest' parameter in ECX.
7199 // Must be kept in sync with X86CallingConv.td
7202 // Check that ECX wasn't needed by an 'inreg' parameter.
7203 const FunctionType *FTy = Func->getFunctionType();
7204 const AttrListPtr &Attrs = Func->getAttributes();
7206 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7207 unsigned InRegCount = 0;
7210 for (FunctionType::param_iterator I = FTy->param_begin(),
7211 E = FTy->param_end(); I != E; ++I, ++Idx)
7212 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7213 // FIXME: should only count parameters that are lowered to integers.
7214 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7216 if (InRegCount > 2) {
7217 report_fatal_error("Nest register in use - reduce number of inreg parameters!");
7222 case CallingConv::X86_FastCall:
7223 case CallingConv::X86_ThisCall:
7224 case CallingConv::Fast:
7225 // Pass 'nest' parameter in EAX.
7226 // Must be kept in sync with X86CallingConv.td
7231 SDValue OutChains[4];
7234 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7235 DAG.getConstant(10, MVT::i32));
7236 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7238 // This is storing the opcode for MOV32ri.
7239 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7240 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7241 OutChains[0] = DAG.getStore(Root, dl,
7242 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7243 Trmp, TrmpAddr, 0, false, false, 0);
7245 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7246 DAG.getConstant(1, MVT::i32));
7247 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7250 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7251 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7252 DAG.getConstant(5, MVT::i32));
7253 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7254 TrmpAddr, 5, false, false, 1);
7256 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7257 DAG.getConstant(6, MVT::i32));
7258 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7262 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7263 return DAG.getMergeValues(Ops, 2, dl);
7267 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7268 SelectionDAG &DAG) const {
7270 The rounding mode is in bits 11:10 of FPSR, and has the following
7277 FLT_ROUNDS, on the other hand, expects the following:
7284 To perform the conversion, we do:
7285 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7288 MachineFunction &MF = DAG.getMachineFunction();
7289 const TargetMachine &TM = MF.getTarget();
7290 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7291 unsigned StackAlignment = TFI.getStackAlignment();
7292 EVT VT = Op.getValueType();
7293 DebugLoc dl = Op.getDebugLoc();
7295 // Save FP Control Word to stack slot
7296 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7297 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7299 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7300 DAG.getEntryNode(), StackSlot);
7302 // Load FP Control Word from stack slot
7303 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7306 // Transform as necessary
7308 DAG.getNode(ISD::SRL, dl, MVT::i16,
7309 DAG.getNode(ISD::AND, dl, MVT::i16,
7310 CWD, DAG.getConstant(0x800, MVT::i16)),
7311 DAG.getConstant(11, MVT::i8));
7313 DAG.getNode(ISD::SRL, dl, MVT::i16,
7314 DAG.getNode(ISD::AND, dl, MVT::i16,
7315 CWD, DAG.getConstant(0x400, MVT::i16)),
7316 DAG.getConstant(9, MVT::i8));
7319 DAG.getNode(ISD::AND, dl, MVT::i16,
7320 DAG.getNode(ISD::ADD, dl, MVT::i16,
7321 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7322 DAG.getConstant(1, MVT::i16)),
7323 DAG.getConstant(3, MVT::i16));
7326 return DAG.getNode((VT.getSizeInBits() < 16 ?
7327 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7330 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
7331 EVT VT = Op.getValueType();
7333 unsigned NumBits = VT.getSizeInBits();
7334 DebugLoc dl = Op.getDebugLoc();
7336 Op = Op.getOperand(0);
7337 if (VT == MVT::i8) {
7338 // Zero extend to i32 since there is not an i8 bsr.
7340 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7343 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7344 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7345 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7347 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7350 DAG.getConstant(NumBits+NumBits-1, OpVT),
7351 DAG.getConstant(X86::COND_E, MVT::i8),
7354 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7356 // Finally xor with NumBits-1.
7357 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7360 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7364 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
7365 EVT VT = Op.getValueType();
7367 unsigned NumBits = VT.getSizeInBits();
7368 DebugLoc dl = Op.getDebugLoc();
7370 Op = Op.getOperand(0);
7371 if (VT == MVT::i8) {
7373 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7376 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7377 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7378 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7380 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7383 DAG.getConstant(NumBits, OpVT),
7384 DAG.getConstant(X86::COND_E, MVT::i8),
7387 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7390 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7394 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
7395 EVT VT = Op.getValueType();
7396 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7397 DebugLoc dl = Op.getDebugLoc();
7399 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7400 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7401 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7402 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7403 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7405 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7406 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7407 // return AloBlo + AloBhi + AhiBlo;
7409 SDValue A = Op.getOperand(0);
7410 SDValue B = Op.getOperand(1);
7412 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7413 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7414 A, DAG.getConstant(32, MVT::i32));
7415 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7416 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7417 B, DAG.getConstant(32, MVT::i32));
7418 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7419 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7421 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7422 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7424 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7425 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7427 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7428 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7429 AloBhi, DAG.getConstant(32, MVT::i32));
7430 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7431 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7432 AhiBlo, DAG.getConstant(32, MVT::i32));
7433 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7434 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7439 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
7440 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7441 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7442 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7443 // has only one use.
7444 SDNode *N = Op.getNode();
7445 SDValue LHS = N->getOperand(0);
7446 SDValue RHS = N->getOperand(1);
7447 unsigned BaseOp = 0;
7449 DebugLoc dl = Op.getDebugLoc();
7451 switch (Op.getOpcode()) {
7452 default: llvm_unreachable("Unknown ovf instruction!");
7454 // A subtract of one will be selected as a INC. Note that INC doesn't
7455 // set CF, so we can't do this for UADDO.
7456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7457 if (C->getAPIntValue() == 1) {
7458 BaseOp = X86ISD::INC;
7462 BaseOp = X86ISD::ADD;
7466 BaseOp = X86ISD::ADD;
7470 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7471 // set CF, so we can't do this for USUBO.
7472 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7473 if (C->getAPIntValue() == 1) {
7474 BaseOp = X86ISD::DEC;
7478 BaseOp = X86ISD::SUB;
7482 BaseOp = X86ISD::SUB;
7486 BaseOp = X86ISD::SMUL;
7490 BaseOp = X86ISD::UMUL;
7495 // Also sets EFLAGS.
7496 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7497 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7500 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7501 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7503 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7507 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
7508 EVT T = Op.getValueType();
7509 DebugLoc dl = Op.getDebugLoc();
7512 switch(T.getSimpleVT().SimpleTy) {
7514 assert(false && "Invalid value type!");
7515 case MVT::i8: Reg = X86::AL; size = 1; break;
7516 case MVT::i16: Reg = X86::AX; size = 2; break;
7517 case MVT::i32: Reg = X86::EAX; size = 4; break;
7519 assert(Subtarget->is64Bit() && "Node not type legal!");
7520 Reg = X86::RAX; size = 8;
7523 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7524 Op.getOperand(2), SDValue());
7525 SDValue Ops[] = { cpIn.getValue(0),
7528 DAG.getTargetConstant(size, MVT::i8),
7530 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7531 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7533 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7537 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7538 SelectionDAG &DAG) const {
7539 assert(Subtarget->is64Bit() && "Result not type legalized?");
7540 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7541 SDValue TheChain = Op.getOperand(0);
7542 DebugLoc dl = Op.getDebugLoc();
7543 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7544 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7545 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7547 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7548 DAG.getConstant(32, MVT::i8));
7550 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7553 return DAG.getMergeValues(Ops, 2, dl);
7556 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
7557 SelectionDAG &DAG) const {
7558 EVT SrcVT = Op.getOperand(0).getValueType();
7559 EVT DstVT = Op.getValueType();
7560 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
7561 Subtarget->hasMMX() && !DisableMMX) &&
7562 "Unexpected custom BIT_CONVERT");
7563 assert((DstVT == MVT::i64 ||
7564 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
7565 "Unexpected custom BIT_CONVERT");
7566 // i64 <=> MMX conversions are Legal.
7567 if (SrcVT==MVT::i64 && DstVT.isVector())
7569 if (DstVT==MVT::i64 && SrcVT.isVector())
7571 // MMX <=> MMX conversions are Legal.
7572 if (SrcVT.isVector() && DstVT.isVector())
7574 // All other conversions need to be expanded.
7577 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
7578 SDNode *Node = Op.getNode();
7579 DebugLoc dl = Node->getDebugLoc();
7580 EVT T = Node->getValueType(0);
7581 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7582 DAG.getConstant(0, T), Node->getOperand(2));
7583 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7584 cast<AtomicSDNode>(Node)->getMemoryVT(),
7585 Node->getOperand(0),
7586 Node->getOperand(1), negOp,
7587 cast<AtomicSDNode>(Node)->getSrcValue(),
7588 cast<AtomicSDNode>(Node)->getAlignment());
7591 /// LowerOperation - Provide custom lowering hooks for some operations.
7593 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7594 switch (Op.getOpcode()) {
7595 default: llvm_unreachable("Should not custom lower this!");
7596 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7597 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7598 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7599 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7600 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7601 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7602 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7603 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7604 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7605 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7606 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7607 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7608 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7609 case ISD::SHL_PARTS:
7610 case ISD::SRA_PARTS:
7611 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7612 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7613 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7614 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7615 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7616 case ISD::FABS: return LowerFABS(Op, DAG);
7617 case ISD::FNEG: return LowerFNEG(Op, DAG);
7618 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7619 case ISD::SETCC: return LowerSETCC(Op, DAG);
7620 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7621 case ISD::SELECT: return LowerSELECT(Op, DAG);
7622 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7623 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7624 case ISD::VASTART: return LowerVASTART(Op, DAG);
7625 case ISD::VAARG: return LowerVAARG(Op, DAG);
7626 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7627 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7628 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7629 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7630 case ISD::FRAME_TO_ARGS_OFFSET:
7631 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7632 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7633 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7634 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7635 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7636 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7637 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7638 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7644 case ISD::UMULO: return LowerXALUO(Op, DAG);
7645 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7646 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
7650 void X86TargetLowering::
7651 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7652 SelectionDAG &DAG, unsigned NewOp) const {
7653 EVT T = Node->getValueType(0);
7654 DebugLoc dl = Node->getDebugLoc();
7655 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7657 SDValue Chain = Node->getOperand(0);
7658 SDValue In1 = Node->getOperand(1);
7659 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7660 Node->getOperand(2), DAG.getIntPtrConstant(0));
7661 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7662 Node->getOperand(2), DAG.getIntPtrConstant(1));
7663 SDValue Ops[] = { Chain, In1, In2L, In2H };
7664 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7666 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7667 cast<MemSDNode>(Node)->getMemOperand());
7668 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7669 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7670 Results.push_back(Result.getValue(2));
7673 /// ReplaceNodeResults - Replace a node with an illegal result type
7674 /// with a new node built out of custom code.
7675 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7676 SmallVectorImpl<SDValue>&Results,
7677 SelectionDAG &DAG) const {
7678 DebugLoc dl = N->getDebugLoc();
7679 switch (N->getOpcode()) {
7681 assert(false && "Do not know how to custom type legalize this operation!");
7683 case ISD::FP_TO_SINT: {
7684 std::pair<SDValue,SDValue> Vals =
7685 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7686 SDValue FIST = Vals.first, StackSlot = Vals.second;
7687 if (FIST.getNode() != 0) {
7688 EVT VT = N->getValueType(0);
7689 // Return a load from the stack slot.
7690 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7695 case ISD::READCYCLECOUNTER: {
7696 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7697 SDValue TheChain = N->getOperand(0);
7698 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7699 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7701 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7703 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7704 SDValue Ops[] = { eax, edx };
7705 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7706 Results.push_back(edx.getValue(1));
7709 case ISD::ATOMIC_CMP_SWAP: {
7710 EVT T = N->getValueType(0);
7711 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7712 SDValue cpInL, cpInH;
7713 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7714 DAG.getConstant(0, MVT::i32));
7715 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7716 DAG.getConstant(1, MVT::i32));
7717 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7718 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7720 SDValue swapInL, swapInH;
7721 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7722 DAG.getConstant(0, MVT::i32));
7723 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7724 DAG.getConstant(1, MVT::i32));
7725 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7727 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7728 swapInL.getValue(1));
7729 SDValue Ops[] = { swapInH.getValue(0),
7731 swapInH.getValue(1) };
7732 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7733 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7734 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7735 MVT::i32, Result.getValue(1));
7736 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7737 MVT::i32, cpOutL.getValue(2));
7738 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7739 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7740 Results.push_back(cpOutH.getValue(1));
7743 case ISD::ATOMIC_LOAD_ADD:
7744 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7746 case ISD::ATOMIC_LOAD_AND:
7747 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7749 case ISD::ATOMIC_LOAD_NAND:
7750 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7752 case ISD::ATOMIC_LOAD_OR:
7753 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7755 case ISD::ATOMIC_LOAD_SUB:
7756 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7758 case ISD::ATOMIC_LOAD_XOR:
7759 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7761 case ISD::ATOMIC_SWAP:
7762 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7767 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7769 default: return NULL;
7770 case X86ISD::BSF: return "X86ISD::BSF";
7771 case X86ISD::BSR: return "X86ISD::BSR";
7772 case X86ISD::SHLD: return "X86ISD::SHLD";
7773 case X86ISD::SHRD: return "X86ISD::SHRD";
7774 case X86ISD::FAND: return "X86ISD::FAND";
7775 case X86ISD::FOR: return "X86ISD::FOR";
7776 case X86ISD::FXOR: return "X86ISD::FXOR";
7777 case X86ISD::FSRL: return "X86ISD::FSRL";
7778 case X86ISD::FILD: return "X86ISD::FILD";
7779 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7780 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7781 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7782 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7783 case X86ISD::FLD: return "X86ISD::FLD";
7784 case X86ISD::FST: return "X86ISD::FST";
7785 case X86ISD::CALL: return "X86ISD::CALL";
7786 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7787 case X86ISD::BT: return "X86ISD::BT";
7788 case X86ISD::CMP: return "X86ISD::CMP";
7789 case X86ISD::COMI: return "X86ISD::COMI";
7790 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7791 case X86ISD::SETCC: return "X86ISD::SETCC";
7792 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7793 case X86ISD::CMOV: return "X86ISD::CMOV";
7794 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7795 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7796 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7797 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7798 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7799 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7800 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7801 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7802 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7803 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7804 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7805 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7806 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7807 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7808 case X86ISD::FMAX: return "X86ISD::FMAX";
7809 case X86ISD::FMIN: return "X86ISD::FMIN";
7810 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7811 case X86ISD::FRCP: return "X86ISD::FRCP";
7812 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7813 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
7814 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7815 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7816 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7817 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7818 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7819 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7820 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7821 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7822 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7823 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7824 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7825 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7826 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7827 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7828 case X86ISD::VSHL: return "X86ISD::VSHL";
7829 case X86ISD::VSRL: return "X86ISD::VSRL";
7830 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7831 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7832 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7833 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7834 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7835 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7836 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7837 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7838 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7839 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7840 case X86ISD::ADD: return "X86ISD::ADD";
7841 case X86ISD::SUB: return "X86ISD::SUB";
7842 case X86ISD::SMUL: return "X86ISD::SMUL";
7843 case X86ISD::UMUL: return "X86ISD::UMUL";
7844 case X86ISD::INC: return "X86ISD::INC";
7845 case X86ISD::DEC: return "X86ISD::DEC";
7846 case X86ISD::OR: return "X86ISD::OR";
7847 case X86ISD::XOR: return "X86ISD::XOR";
7848 case X86ISD::AND: return "X86ISD::AND";
7849 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7850 case X86ISD::PTEST: return "X86ISD::PTEST";
7851 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7852 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7856 // isLegalAddressingMode - Return true if the addressing mode represented
7857 // by AM is legal for this target, for a load/store of the specified type.
7858 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7859 const Type *Ty) const {
7860 // X86 supports extremely general addressing modes.
7861 CodeModel::Model M = getTargetMachine().getCodeModel();
7863 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7864 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7869 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7871 // If a reference to this global requires an extra load, we can't fold it.
7872 if (isGlobalStubReference(GVFlags))
7875 // If BaseGV requires a register for the PIC base, we cannot also have a
7876 // BaseReg specified.
7877 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7880 // If lower 4G is not available, then we must use rip-relative addressing.
7881 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7891 // These scales always work.
7896 // These scales are formed with basereg+scalereg. Only accept if there is
7901 default: // Other stuff never works.
7909 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7910 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7912 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7913 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7914 if (NumBits1 <= NumBits2)
7919 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7920 if (!VT1.isInteger() || !VT2.isInteger())
7922 unsigned NumBits1 = VT1.getSizeInBits();
7923 unsigned NumBits2 = VT2.getSizeInBits();
7924 if (NumBits1 <= NumBits2)
7929 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7930 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7931 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
7934 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7935 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7936 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7939 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7940 // i16 instructions are longer (0x66 prefix) and potentially slower.
7941 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7944 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7945 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7946 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7947 /// are assumed to be legal.
7949 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7951 // Very little shuffling can be done for 64-bit vectors right now.
7952 if (VT.getSizeInBits() == 64)
7953 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
7955 // FIXME: pshufb, blends, shifts.
7956 return (VT.getVectorNumElements() == 2 ||
7957 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7958 isMOVLMask(M, VT) ||
7959 isSHUFPMask(M, VT) ||
7960 isPSHUFDMask(M, VT) ||
7961 isPSHUFHWMask(M, VT) ||
7962 isPSHUFLWMask(M, VT) ||
7963 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7964 isUNPCKLMask(M, VT) ||
7965 isUNPCKHMask(M, VT) ||
7966 isUNPCKL_v_undef_Mask(M, VT) ||
7967 isUNPCKH_v_undef_Mask(M, VT));
7971 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7973 unsigned NumElts = VT.getVectorNumElements();
7974 // FIXME: This collection of masks seems suspect.
7977 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7978 return (isMOVLMask(Mask, VT) ||
7979 isCommutedMOVLMask(Mask, VT, true) ||
7980 isSHUFPMask(Mask, VT) ||
7981 isCommutedSHUFPMask(Mask, VT));
7986 //===----------------------------------------------------------------------===//
7987 // X86 Scheduler Hooks
7988 //===----------------------------------------------------------------------===//
7990 // private utility function
7992 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7993 MachineBasicBlock *MBB,
8001 TargetRegisterClass *RC,
8002 bool invSrc) const {
8003 // For the atomic bitwise operator, we generate
8006 // ld t1 = [bitinstr.addr]
8007 // op t2 = t1, [bitinstr.val]
8009 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8011 // fallthrough -->nextMBB
8012 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8013 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8014 MachineFunction::iterator MBBIter = MBB;
8017 /// First build the CFG
8018 MachineFunction *F = MBB->getParent();
8019 MachineBasicBlock *thisMBB = MBB;
8020 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8021 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8022 F->insert(MBBIter, newMBB);
8023 F->insert(MBBIter, nextMBB);
8025 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8026 nextMBB->splice(nextMBB->begin(), thisMBB,
8027 llvm::next(MachineBasicBlock::iterator(bInstr)),
8029 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8031 // Update thisMBB to fall through to newMBB
8032 thisMBB->addSuccessor(newMBB);
8034 // newMBB jumps to itself and fall through to nextMBB
8035 newMBB->addSuccessor(nextMBB);
8036 newMBB->addSuccessor(newMBB);
8038 // Insert instructions into newMBB based on incoming instruction
8039 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8040 "unexpected number of operands");
8041 DebugLoc dl = bInstr->getDebugLoc();
8042 MachineOperand& destOper = bInstr->getOperand(0);
8043 MachineOperand* argOpers[2 + X86AddrNumOperands];
8044 int numArgs = bInstr->getNumOperands() - 1;
8045 for (int i=0; i < numArgs; ++i)
8046 argOpers[i] = &bInstr->getOperand(i+1);
8048 // x86 address has 4 operands: base, index, scale, and displacement
8049 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8050 int valArgIndx = lastAddrIndx + 1;
8052 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8053 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
8054 for (int i=0; i <= lastAddrIndx; ++i)
8055 (*MIB).addOperand(*argOpers[i]);
8057 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
8059 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
8064 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8065 assert((argOpers[valArgIndx]->isReg() ||
8066 argOpers[valArgIndx]->isImm()) &&
8068 if (argOpers[valArgIndx]->isReg())
8069 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
8071 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
8073 (*MIB).addOperand(*argOpers[valArgIndx]);
8075 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
8078 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
8079 for (int i=0; i <= lastAddrIndx; ++i)
8080 (*MIB).addOperand(*argOpers[i]);
8082 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8083 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8084 bInstr->memoperands_end());
8086 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
8090 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8092 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8096 // private utility function: 64 bit atomics on 32 bit host.
8098 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
8099 MachineBasicBlock *MBB,
8104 bool invSrc) const {
8105 // For the atomic bitwise operator, we generate
8106 // thisMBB (instructions are in pairs, except cmpxchg8b)
8107 // ld t1,t2 = [bitinstr.addr]
8109 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8110 // op t5, t6 <- out1, out2, [bitinstr.val]
8111 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8112 // mov ECX, EBX <- t5, t6
8113 // mov EAX, EDX <- t1, t2
8114 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8115 // mov t3, t4 <- EAX, EDX
8117 // result in out1, out2
8118 // fallthrough -->nextMBB
8120 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8121 const unsigned LoadOpc = X86::MOV32rm;
8122 const unsigned copyOpc = X86::MOV32rr;
8123 const unsigned NotOpc = X86::NOT32r;
8124 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8125 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8126 MachineFunction::iterator MBBIter = MBB;
8129 /// First build the CFG
8130 MachineFunction *F = MBB->getParent();
8131 MachineBasicBlock *thisMBB = MBB;
8132 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8133 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8134 F->insert(MBBIter, newMBB);
8135 F->insert(MBBIter, nextMBB);
8137 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8138 nextMBB->splice(nextMBB->begin(), thisMBB,
8139 llvm::next(MachineBasicBlock::iterator(bInstr)),
8141 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8143 // Update thisMBB to fall through to newMBB
8144 thisMBB->addSuccessor(newMBB);
8146 // newMBB jumps to itself and fall through to nextMBB
8147 newMBB->addSuccessor(nextMBB);
8148 newMBB->addSuccessor(newMBB);
8150 DebugLoc dl = bInstr->getDebugLoc();
8151 // Insert instructions into newMBB based on incoming instruction
8152 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8153 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
8154 "unexpected number of operands");
8155 MachineOperand& dest1Oper = bInstr->getOperand(0);
8156 MachineOperand& dest2Oper = bInstr->getOperand(1);
8157 MachineOperand* argOpers[2 + X86AddrNumOperands];
8158 for (int i=0; i < 2 + X86AddrNumOperands; ++i) {
8159 argOpers[i] = &bInstr->getOperand(i+2);
8161 // We use some of the operands multiple times, so conservatively just
8162 // clear any kill flags that might be present.
8163 if (argOpers[i]->isReg() && argOpers[i]->isUse())
8164 argOpers[i]->setIsKill(false);
8167 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8168 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8170 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8171 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8172 for (int i=0; i <= lastAddrIndx; ++i)
8173 (*MIB).addOperand(*argOpers[i]);
8174 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8175 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8176 // add 4 to displacement.
8177 for (int i=0; i <= lastAddrIndx-2; ++i)
8178 (*MIB).addOperand(*argOpers[i]);
8179 MachineOperand newOp3 = *(argOpers[3]);
8181 newOp3.setImm(newOp3.getImm()+4);
8183 newOp3.setOffset(newOp3.getOffset()+4);
8184 (*MIB).addOperand(newOp3);
8185 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8187 // t3/4 are defined later, at the bottom of the loop
8188 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8189 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8190 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8191 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8192 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8193 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8195 // The subsequent operations should be using the destination registers of
8196 //the PHI instructions.
8198 t1 = F->getRegInfo().createVirtualRegister(RC);
8199 t2 = F->getRegInfo().createVirtualRegister(RC);
8200 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8201 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8203 t1 = dest1Oper.getReg();
8204 t2 = dest2Oper.getReg();
8207 int valArgIndx = lastAddrIndx + 1;
8208 assert((argOpers[valArgIndx]->isReg() ||
8209 argOpers[valArgIndx]->isImm()) &&
8211 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8212 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8213 if (argOpers[valArgIndx]->isReg())
8214 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8216 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8217 if (regOpcL != X86::MOV32rr)
8219 (*MIB).addOperand(*argOpers[valArgIndx]);
8220 assert(argOpers[valArgIndx + 1]->isReg() ==
8221 argOpers[valArgIndx]->isReg());
8222 assert(argOpers[valArgIndx + 1]->isImm() ==
8223 argOpers[valArgIndx]->isImm());
8224 if (argOpers[valArgIndx + 1]->isReg())
8225 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8227 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8228 if (regOpcH != X86::MOV32rr)
8230 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8232 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8234 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8237 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8239 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8242 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8243 for (int i=0; i <= lastAddrIndx; ++i)
8244 (*MIB).addOperand(*argOpers[i]);
8246 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8247 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8248 bInstr->memoperands_end());
8250 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8251 MIB.addReg(X86::EAX);
8252 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8253 MIB.addReg(X86::EDX);
8256 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8258 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8262 // private utility function
8264 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8265 MachineBasicBlock *MBB,
8266 unsigned cmovOpc) const {
8267 // For the atomic min/max operator, we generate
8270 // ld t1 = [min/max.addr]
8271 // mov t2 = [min/max.val]
8273 // cmov[cond] t2 = t1
8275 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8277 // fallthrough -->nextMBB
8279 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8280 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8281 MachineFunction::iterator MBBIter = MBB;
8284 /// First build the CFG
8285 MachineFunction *F = MBB->getParent();
8286 MachineBasicBlock *thisMBB = MBB;
8287 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8288 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8289 F->insert(MBBIter, newMBB);
8290 F->insert(MBBIter, nextMBB);
8292 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8293 nextMBB->splice(nextMBB->begin(), thisMBB,
8294 llvm::next(MachineBasicBlock::iterator(mInstr)),
8296 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8298 // Update thisMBB to fall through to newMBB
8299 thisMBB->addSuccessor(newMBB);
8301 // newMBB jumps to newMBB and fall through to nextMBB
8302 newMBB->addSuccessor(nextMBB);
8303 newMBB->addSuccessor(newMBB);
8305 DebugLoc dl = mInstr->getDebugLoc();
8306 // Insert instructions into newMBB based on incoming instruction
8307 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8308 "unexpected number of operands");
8309 MachineOperand& destOper = mInstr->getOperand(0);
8310 MachineOperand* argOpers[2 + X86AddrNumOperands];
8311 int numArgs = mInstr->getNumOperands() - 1;
8312 for (int i=0; i < numArgs; ++i)
8313 argOpers[i] = &mInstr->getOperand(i+1);
8315 // x86 address has 4 operands: base, index, scale, and displacement
8316 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8317 int valArgIndx = lastAddrIndx + 1;
8319 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8320 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8321 for (int i=0; i <= lastAddrIndx; ++i)
8322 (*MIB).addOperand(*argOpers[i]);
8324 // We only support register and immediate values
8325 assert((argOpers[valArgIndx]->isReg() ||
8326 argOpers[valArgIndx]->isImm()) &&
8329 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8330 if (argOpers[valArgIndx]->isReg())
8331 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8333 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8334 (*MIB).addOperand(*argOpers[valArgIndx]);
8336 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8339 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8344 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8345 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8349 // Cmp and exchange if none has modified the memory location
8350 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8351 for (int i=0; i <= lastAddrIndx; ++i)
8352 (*MIB).addOperand(*argOpers[i]);
8354 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8355 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8356 mInstr->memoperands_end());
8358 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8359 MIB.addReg(X86::EAX);
8362 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8364 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
8368 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8369 // all of this code can be replaced with that in the .td file.
8371 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8372 unsigned numArgs, bool memArg) const {
8374 DebugLoc dl = MI->getDebugLoc();
8375 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8379 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8381 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8383 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8385 for (unsigned i = 0; i < numArgs; ++i) {
8386 MachineOperand &Op = MI->getOperand(i+1);
8388 if (!(Op.isReg() && Op.isImplicit()))
8392 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8395 MI->eraseFromParent();
8401 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8403 MachineBasicBlock *MBB) const {
8404 // Emit code to save XMM registers to the stack. The ABI says that the
8405 // number of registers to save is given in %al, so it's theoretically
8406 // possible to do an indirect jump trick to avoid saving all of them,
8407 // however this code takes a simpler approach and just executes all
8408 // of the stores if %al is non-zero. It's less code, and it's probably
8409 // easier on the hardware branch predictor, and stores aren't all that
8410 // expensive anyway.
8412 // Create the new basic blocks. One block contains all the XMM stores,
8413 // and one block is the final destination regardless of whether any
8414 // stores were performed.
8415 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8416 MachineFunction *F = MBB->getParent();
8417 MachineFunction::iterator MBBIter = MBB;
8419 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8420 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8421 F->insert(MBBIter, XMMSaveMBB);
8422 F->insert(MBBIter, EndMBB);
8424 // Transfer the remainder of MBB and its successor edges to EndMBB.
8425 EndMBB->splice(EndMBB->begin(), MBB,
8426 llvm::next(MachineBasicBlock::iterator(MI)),
8428 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
8430 // The original block will now fall through to the XMM save block.
8431 MBB->addSuccessor(XMMSaveMBB);
8432 // The XMMSaveMBB will fall through to the end block.
8433 XMMSaveMBB->addSuccessor(EndMBB);
8435 // Now add the instructions.
8436 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8437 DebugLoc DL = MI->getDebugLoc();
8439 unsigned CountReg = MI->getOperand(0).getReg();
8440 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8441 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8443 if (!Subtarget->isTargetWin64()) {
8444 // If %al is 0, branch around the XMM save block.
8445 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8446 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8447 MBB->addSuccessor(EndMBB);
8450 // In the XMM save block, save all the XMM argument registers.
8451 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8452 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8453 MachineMemOperand *MMO =
8454 F->getMachineMemOperand(
8455 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8456 MachineMemOperand::MOStore, Offset,
8457 /*Size=*/16, /*Align=*/16);
8458 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8459 .addFrameIndex(RegSaveFrameIndex)
8460 .addImm(/*Scale=*/1)
8461 .addReg(/*IndexReg=*/0)
8462 .addImm(/*Disp=*/Offset)
8463 .addReg(/*Segment=*/0)
8464 .addReg(MI->getOperand(i).getReg())
8465 .addMemOperand(MMO);
8468 MI->eraseFromParent(); // The pseudo instruction is gone now.
8474 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8475 MachineBasicBlock *BB) const {
8476 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8477 DebugLoc DL = MI->getDebugLoc();
8479 // To "insert" a SELECT_CC instruction, we actually have to insert the
8480 // diamond control-flow pattern. The incoming instruction knows the
8481 // destination vreg to set, the condition code register to branch on, the
8482 // true/false values to select between, and a branch opcode to use.
8483 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8484 MachineFunction::iterator It = BB;
8490 // cmpTY ccX, r1, r2
8492 // fallthrough --> copy0MBB
8493 MachineBasicBlock *thisMBB = BB;
8494 MachineFunction *F = BB->getParent();
8495 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8496 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8497 F->insert(It, copy0MBB);
8498 F->insert(It, sinkMBB);
8500 // If the EFLAGS register isn't dead in the terminator, then claim that it's
8501 // live into the sink and copy blocks.
8502 const MachineFunction *MF = BB->getParent();
8503 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
8504 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
8506 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
8507 const MachineOperand &MO = MI->getOperand(I);
8508 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
8509 unsigned Reg = MO.getReg();
8510 if (Reg != X86::EFLAGS) continue;
8511 copy0MBB->addLiveIn(Reg);
8512 sinkMBB->addLiveIn(Reg);
8515 // Transfer the remainder of BB and its successor edges to sinkMBB.
8516 sinkMBB->splice(sinkMBB->begin(), BB,
8517 llvm::next(MachineBasicBlock::iterator(MI)),
8519 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8521 // Add the true and fallthrough blocks as its successors.
8522 BB->addSuccessor(copy0MBB);
8523 BB->addSuccessor(sinkMBB);
8525 // Create the conditional branch instruction.
8527 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8528 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8531 // %FalseValue = ...
8532 // # fallthrough to sinkMBB
8533 copy0MBB->addSuccessor(sinkMBB);
8536 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8538 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8539 TII->get(X86::PHI), MI->getOperand(0).getReg())
8540 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8541 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8543 MI->eraseFromParent(); // The pseudo instruction is gone now.
8548 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8549 MachineBasicBlock *BB) const {
8550 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8551 DebugLoc DL = MI->getDebugLoc();
8553 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8554 // non-trivial part is impdef of ESP.
8555 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8558 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
8559 .addExternalSymbol("_alloca")
8560 .addReg(X86::EAX, RegState::Implicit)
8561 .addReg(X86::ESP, RegState::Implicit)
8562 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8563 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8565 MI->eraseFromParent(); // The pseudo instruction is gone now.
8570 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
8571 MachineBasicBlock *BB) const {
8572 // This is pretty easy. We're taking the value that we received from
8573 // our load from the relocation, sticking it in either RDI (x86-64)
8574 // or EAX and doing an indirect call. The return value will then
8575 // be in the normal return register.
8576 const X86InstrInfo *TII
8577 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
8578 DebugLoc DL = MI->getDebugLoc();
8579 MachineFunction *F = BB->getParent();
8581 assert(MI->getOperand(3).isGlobal() && "This should be a global");
8583 if (Subtarget->is64Bit()) {
8584 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8585 TII->get(X86::MOV64rm), X86::RDI)
8587 .addImm(0).addReg(0)
8588 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8589 MI->getOperand(3).getTargetFlags())
8591 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
8592 addDirectMem(MIB, X86::RDI).addReg(0);
8593 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
8594 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8595 TII->get(X86::MOV32rm), X86::EAX)
8597 .addImm(0).addReg(0)
8598 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8599 MI->getOperand(3).getTargetFlags())
8601 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8602 addDirectMem(MIB, X86::EAX).addReg(0);
8604 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8605 TII->get(X86::MOV32rm), X86::EAX)
8606 .addReg(TII->getGlobalBaseReg(F))
8607 .addImm(0).addReg(0)
8608 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8609 MI->getOperand(3).getTargetFlags())
8611 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8612 addDirectMem(MIB, X86::EAX).addReg(0);
8615 MI->eraseFromParent(); // The pseudo instruction is gone now.
8620 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8621 MachineBasicBlock *BB) const {
8622 switch (MI->getOpcode()) {
8623 default: assert(false && "Unexpected instr type to insert");
8624 case X86::MINGW_ALLOCA:
8625 return EmitLoweredMingwAlloca(MI, BB);
8626 case X86::TLSCall_32:
8627 case X86::TLSCall_64:
8628 return EmitLoweredTLSCall(MI, BB);
8630 case X86::CMOV_V1I64:
8631 case X86::CMOV_FR32:
8632 case X86::CMOV_FR64:
8633 case X86::CMOV_V4F32:
8634 case X86::CMOV_V2F64:
8635 case X86::CMOV_V2I64:
8636 case X86::CMOV_GR16:
8637 case X86::CMOV_GR32:
8638 case X86::CMOV_RFP32:
8639 case X86::CMOV_RFP64:
8640 case X86::CMOV_RFP80:
8641 return EmitLoweredSelect(MI, BB);
8643 case X86::FP32_TO_INT16_IN_MEM:
8644 case X86::FP32_TO_INT32_IN_MEM:
8645 case X86::FP32_TO_INT64_IN_MEM:
8646 case X86::FP64_TO_INT16_IN_MEM:
8647 case X86::FP64_TO_INT32_IN_MEM:
8648 case X86::FP64_TO_INT64_IN_MEM:
8649 case X86::FP80_TO_INT16_IN_MEM:
8650 case X86::FP80_TO_INT32_IN_MEM:
8651 case X86::FP80_TO_INT64_IN_MEM: {
8652 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8653 DebugLoc DL = MI->getDebugLoc();
8655 // Change the floating point control register to use "round towards zero"
8656 // mode when truncating to an integer value.
8657 MachineFunction *F = BB->getParent();
8658 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8659 addFrameReference(BuildMI(*BB, MI, DL,
8660 TII->get(X86::FNSTCW16m)), CWFrameIdx);
8662 // Load the old value of the high byte of the control word...
8664 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8665 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
8668 // Set the high part to be round to zero...
8669 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8672 // Reload the modified control word now...
8673 addFrameReference(BuildMI(*BB, MI, DL,
8674 TII->get(X86::FLDCW16m)), CWFrameIdx);
8676 // Restore the memory image of control word to original value
8677 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8680 // Get the X86 opcode to use.
8682 switch (MI->getOpcode()) {
8683 default: llvm_unreachable("illegal opcode!");
8684 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8685 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8686 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8687 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8688 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8689 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8690 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8691 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8692 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8696 MachineOperand &Op = MI->getOperand(0);
8698 AM.BaseType = X86AddressMode::RegBase;
8699 AM.Base.Reg = Op.getReg();
8701 AM.BaseType = X86AddressMode::FrameIndexBase;
8702 AM.Base.FrameIndex = Op.getIndex();
8704 Op = MI->getOperand(1);
8706 AM.Scale = Op.getImm();
8707 Op = MI->getOperand(2);
8709 AM.IndexReg = Op.getImm();
8710 Op = MI->getOperand(3);
8711 if (Op.isGlobal()) {
8712 AM.GV = Op.getGlobal();
8714 AM.Disp = Op.getImm();
8716 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
8717 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8719 // Reload the original control word now.
8720 addFrameReference(BuildMI(*BB, MI, DL,
8721 TII->get(X86::FLDCW16m)), CWFrameIdx);
8723 MI->eraseFromParent(); // The pseudo instruction is gone now.
8726 // String/text processing lowering.
8727 case X86::PCMPISTRM128REG:
8728 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8729 case X86::PCMPISTRM128MEM:
8730 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8731 case X86::PCMPESTRM128REG:
8732 return EmitPCMP(MI, BB, 5, false /* in mem */);
8733 case X86::PCMPESTRM128MEM:
8734 return EmitPCMP(MI, BB, 5, true /* in mem */);
8737 case X86::ATOMAND32:
8738 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8739 X86::AND32ri, X86::MOV32rm,
8740 X86::LCMPXCHG32, X86::MOV32rr,
8741 X86::NOT32r, X86::EAX,
8742 X86::GR32RegisterClass);
8744 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8745 X86::OR32ri, X86::MOV32rm,
8746 X86::LCMPXCHG32, X86::MOV32rr,
8747 X86::NOT32r, X86::EAX,
8748 X86::GR32RegisterClass);
8749 case X86::ATOMXOR32:
8750 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8751 X86::XOR32ri, X86::MOV32rm,
8752 X86::LCMPXCHG32, X86::MOV32rr,
8753 X86::NOT32r, X86::EAX,
8754 X86::GR32RegisterClass);
8755 case X86::ATOMNAND32:
8756 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8757 X86::AND32ri, X86::MOV32rm,
8758 X86::LCMPXCHG32, X86::MOV32rr,
8759 X86::NOT32r, X86::EAX,
8760 X86::GR32RegisterClass, true);
8761 case X86::ATOMMIN32:
8762 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8763 case X86::ATOMMAX32:
8764 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8765 case X86::ATOMUMIN32:
8766 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8767 case X86::ATOMUMAX32:
8768 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8770 case X86::ATOMAND16:
8771 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8772 X86::AND16ri, X86::MOV16rm,
8773 X86::LCMPXCHG16, X86::MOV16rr,
8774 X86::NOT16r, X86::AX,
8775 X86::GR16RegisterClass);
8777 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8778 X86::OR16ri, X86::MOV16rm,
8779 X86::LCMPXCHG16, X86::MOV16rr,
8780 X86::NOT16r, X86::AX,
8781 X86::GR16RegisterClass);
8782 case X86::ATOMXOR16:
8783 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8784 X86::XOR16ri, X86::MOV16rm,
8785 X86::LCMPXCHG16, X86::MOV16rr,
8786 X86::NOT16r, X86::AX,
8787 X86::GR16RegisterClass);
8788 case X86::ATOMNAND16:
8789 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8790 X86::AND16ri, X86::MOV16rm,
8791 X86::LCMPXCHG16, X86::MOV16rr,
8792 X86::NOT16r, X86::AX,
8793 X86::GR16RegisterClass, true);
8794 case X86::ATOMMIN16:
8795 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8796 case X86::ATOMMAX16:
8797 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8798 case X86::ATOMUMIN16:
8799 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8800 case X86::ATOMUMAX16:
8801 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8804 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8805 X86::AND8ri, X86::MOV8rm,
8806 X86::LCMPXCHG8, X86::MOV8rr,
8807 X86::NOT8r, X86::AL,
8808 X86::GR8RegisterClass);
8810 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8811 X86::OR8ri, X86::MOV8rm,
8812 X86::LCMPXCHG8, X86::MOV8rr,
8813 X86::NOT8r, X86::AL,
8814 X86::GR8RegisterClass);
8816 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8817 X86::XOR8ri, X86::MOV8rm,
8818 X86::LCMPXCHG8, X86::MOV8rr,
8819 X86::NOT8r, X86::AL,
8820 X86::GR8RegisterClass);
8821 case X86::ATOMNAND8:
8822 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8823 X86::AND8ri, X86::MOV8rm,
8824 X86::LCMPXCHG8, X86::MOV8rr,
8825 X86::NOT8r, X86::AL,
8826 X86::GR8RegisterClass, true);
8827 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8828 // This group is for 64-bit host.
8829 case X86::ATOMAND64:
8830 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8831 X86::AND64ri32, X86::MOV64rm,
8832 X86::LCMPXCHG64, X86::MOV64rr,
8833 X86::NOT64r, X86::RAX,
8834 X86::GR64RegisterClass);
8836 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8837 X86::OR64ri32, X86::MOV64rm,
8838 X86::LCMPXCHG64, X86::MOV64rr,
8839 X86::NOT64r, X86::RAX,
8840 X86::GR64RegisterClass);
8841 case X86::ATOMXOR64:
8842 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8843 X86::XOR64ri32, X86::MOV64rm,
8844 X86::LCMPXCHG64, X86::MOV64rr,
8845 X86::NOT64r, X86::RAX,
8846 X86::GR64RegisterClass);
8847 case X86::ATOMNAND64:
8848 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8849 X86::AND64ri32, X86::MOV64rm,
8850 X86::LCMPXCHG64, X86::MOV64rr,
8851 X86::NOT64r, X86::RAX,
8852 X86::GR64RegisterClass, true);
8853 case X86::ATOMMIN64:
8854 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8855 case X86::ATOMMAX64:
8856 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8857 case X86::ATOMUMIN64:
8858 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8859 case X86::ATOMUMAX64:
8860 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8862 // This group does 64-bit operations on a 32-bit host.
8863 case X86::ATOMAND6432:
8864 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8865 X86::AND32rr, X86::AND32rr,
8866 X86::AND32ri, X86::AND32ri,
8868 case X86::ATOMOR6432:
8869 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8870 X86::OR32rr, X86::OR32rr,
8871 X86::OR32ri, X86::OR32ri,
8873 case X86::ATOMXOR6432:
8874 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8875 X86::XOR32rr, X86::XOR32rr,
8876 X86::XOR32ri, X86::XOR32ri,
8878 case X86::ATOMNAND6432:
8879 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8880 X86::AND32rr, X86::AND32rr,
8881 X86::AND32ri, X86::AND32ri,
8883 case X86::ATOMADD6432:
8884 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8885 X86::ADD32rr, X86::ADC32rr,
8886 X86::ADD32ri, X86::ADC32ri,
8888 case X86::ATOMSUB6432:
8889 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8890 X86::SUB32rr, X86::SBB32rr,
8891 X86::SUB32ri, X86::SBB32ri,
8893 case X86::ATOMSWAP6432:
8894 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8895 X86::MOV32rr, X86::MOV32rr,
8896 X86::MOV32ri, X86::MOV32ri,
8898 case X86::VASTART_SAVE_XMM_REGS:
8899 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8903 //===----------------------------------------------------------------------===//
8904 // X86 Optimization Hooks
8905 //===----------------------------------------------------------------------===//
8907 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8911 const SelectionDAG &DAG,
8912 unsigned Depth) const {
8913 unsigned Opc = Op.getOpcode();
8914 assert((Opc >= ISD::BUILTIN_OP_END ||
8915 Opc == ISD::INTRINSIC_WO_CHAIN ||
8916 Opc == ISD::INTRINSIC_W_CHAIN ||
8917 Opc == ISD::INTRINSIC_VOID) &&
8918 "Should use MaskedValueIsZero if you don't know whether Op"
8919 " is a target node!");
8921 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8933 // These nodes' second result is a boolean.
8934 if (Op.getResNo() == 0)
8938 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8939 Mask.getBitWidth() - 1);
8944 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8945 /// node is a GlobalAddress + offset.
8946 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8947 const GlobalValue* &GA,
8948 int64_t &Offset) const {
8949 if (N->getOpcode() == X86ISD::Wrapper) {
8950 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8951 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8952 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8956 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8959 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8960 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8961 /// if the load addresses are consecutive, non-overlapping, and in the right
8963 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8964 const TargetLowering &TLI) {
8965 DebugLoc dl = N->getDebugLoc();
8966 EVT VT = N->getValueType(0);
8967 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8969 if (VT.getSizeInBits() != 128)
8972 SmallVector<SDValue, 16> Elts;
8973 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
8974 Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
8976 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
8979 /// PerformShuffleCombine - Detect vector gather/scatter index generation
8980 /// and convert it from being a bunch of shuffles and extracts to a simple
8981 /// store and scalar loads to extract the elements.
8982 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
8983 const TargetLowering &TLI) {
8984 SDValue InputVector = N->getOperand(0);
8986 // Only operate on vectors of 4 elements, where the alternative shuffling
8987 // gets to be more expensive.
8988 if (InputVector.getValueType() != MVT::v4i32)
8991 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
8992 // single use which is a sign-extend or zero-extend, and all elements are
8994 SmallVector<SDNode *, 4> Uses;
8995 unsigned ExtractedElements = 0;
8996 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
8997 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
8998 if (UI.getUse().getResNo() != InputVector.getResNo())
9001 SDNode *Extract = *UI;
9002 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9005 if (Extract->getValueType(0) != MVT::i32)
9007 if (!Extract->hasOneUse())
9009 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
9010 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
9012 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
9015 // Record which element was extracted.
9016 ExtractedElements |=
9017 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
9019 Uses.push_back(Extract);
9022 // If not all the elements were used, this may not be worthwhile.
9023 if (ExtractedElements != 15)
9026 // Ok, we've now decided to do the transformation.
9027 DebugLoc dl = InputVector.getDebugLoc();
9029 // Store the value to a temporary stack slot.
9030 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
9031 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 0,
9034 // Replace each use (extract) with a load of the appropriate element.
9035 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
9036 UE = Uses.end(); UI != UE; ++UI) {
9037 SDNode *Extract = *UI;
9039 // Compute the element's address.
9040 SDValue Idx = Extract->getOperand(1);
9042 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
9043 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
9044 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
9046 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), OffsetVal, StackPtr);
9049 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr,
9050 NULL, 0, false, false, 0);
9052 // Replace the exact with the load.
9053 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
9056 // The replacement was made in place; don't return anything.
9060 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
9061 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
9062 const X86Subtarget *Subtarget) {
9063 DebugLoc DL = N->getDebugLoc();
9064 SDValue Cond = N->getOperand(0);
9065 // Get the LHS/RHS of the select.
9066 SDValue LHS = N->getOperand(1);
9067 SDValue RHS = N->getOperand(2);
9069 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
9070 // instructions match the semantics of the common C idiom x<y?x:y but not
9071 // x<=y?x:y, because of how they handle negative zero (which can be
9072 // ignored in unsafe-math mode).
9073 if (Subtarget->hasSSE2() &&
9074 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
9075 Cond.getOpcode() == ISD::SETCC) {
9076 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
9078 unsigned Opcode = 0;
9079 // Check for x CC y ? x : y.
9080 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
9081 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
9085 // Converting this to a min would handle NaNs incorrectly, and swapping
9086 // the operands would cause it to handle comparisons between positive
9087 // and negative zero incorrectly.
9088 if (!FiniteOnlyFPMath() &&
9089 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
9090 if (!UnsafeFPMath &&
9091 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9093 std::swap(LHS, RHS);
9095 Opcode = X86ISD::FMIN;
9098 // Converting this to a min would handle comparisons between positive
9099 // and negative zero incorrectly.
9100 if (!UnsafeFPMath &&
9101 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
9103 Opcode = X86ISD::FMIN;
9106 // Converting this to a min would handle both negative zeros and NaNs
9107 // incorrectly, but we can swap the operands to fix both.
9108 std::swap(LHS, RHS);
9112 Opcode = X86ISD::FMIN;
9116 // Converting this to a max would handle comparisons between positive
9117 // and negative zero incorrectly.
9118 if (!UnsafeFPMath &&
9119 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
9121 Opcode = X86ISD::FMAX;
9124 // Converting this to a max would handle NaNs incorrectly, and swapping
9125 // the operands would cause it to handle comparisons between positive
9126 // and negative zero incorrectly.
9127 if (!FiniteOnlyFPMath() &&
9128 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
9129 if (!UnsafeFPMath &&
9130 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9132 std::swap(LHS, RHS);
9134 Opcode = X86ISD::FMAX;
9137 // Converting this to a max would handle both negative zeros and NaNs
9138 // incorrectly, but we can swap the operands to fix both.
9139 std::swap(LHS, RHS);
9143 Opcode = X86ISD::FMAX;
9146 // Check for x CC y ? y : x -- a min/max with reversed arms.
9147 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
9148 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
9152 // Converting this to a min would handle comparisons between positive
9153 // and negative zero incorrectly, and swapping the operands would
9154 // cause it to handle NaNs incorrectly.
9155 if (!UnsafeFPMath &&
9156 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
9157 if (!FiniteOnlyFPMath() &&
9158 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9160 std::swap(LHS, RHS);
9162 Opcode = X86ISD::FMIN;
9165 // Converting this to a min would handle NaNs incorrectly.
9166 if (!UnsafeFPMath &&
9167 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9169 Opcode = X86ISD::FMIN;
9172 // Converting this to a min would handle both negative zeros and NaNs
9173 // incorrectly, but we can swap the operands to fix both.
9174 std::swap(LHS, RHS);
9178 Opcode = X86ISD::FMIN;
9182 // Converting this to a max would handle NaNs incorrectly.
9183 if (!FiniteOnlyFPMath() &&
9184 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9186 Opcode = X86ISD::FMAX;
9189 // Converting this to a max would handle comparisons between positive
9190 // and negative zero incorrectly, and swapping the operands would
9191 // cause it to handle NaNs incorrectly.
9192 if (!UnsafeFPMath &&
9193 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
9194 if (!FiniteOnlyFPMath() &&
9195 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9197 std::swap(LHS, RHS);
9199 Opcode = X86ISD::FMAX;
9202 // Converting this to a max would handle both negative zeros and NaNs
9203 // incorrectly, but we can swap the operands to fix both.
9204 std::swap(LHS, RHS);
9208 Opcode = X86ISD::FMAX;
9214 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9217 // If this is a select between two integer constants, try to do some
9219 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9220 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9221 // Don't do this for crazy integer types.
9222 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9223 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9224 // so that TrueC (the true value) is larger than FalseC.
9225 bool NeedsCondInvert = false;
9227 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9228 // Efficiently invertible.
9229 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9230 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9231 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9232 NeedsCondInvert = true;
9233 std::swap(TrueC, FalseC);
9236 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9237 if (FalseC->getAPIntValue() == 0 &&
9238 TrueC->getAPIntValue().isPowerOf2()) {
9239 if (NeedsCondInvert) // Invert the condition if needed.
9240 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9241 DAG.getConstant(1, Cond.getValueType()));
9243 // Zero extend the condition if needed.
9244 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9246 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9247 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9248 DAG.getConstant(ShAmt, MVT::i8));
9251 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9252 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9253 if (NeedsCondInvert) // Invert the condition if needed.
9254 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9255 DAG.getConstant(1, Cond.getValueType()));
9257 // Zero extend the condition if needed.
9258 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9259 FalseC->getValueType(0), Cond);
9260 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9261 SDValue(FalseC, 0));
9264 // Optimize cases that will turn into an LEA instruction. This requires
9265 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9266 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9267 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9268 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9270 bool isFastMultiplier = false;
9272 switch ((unsigned char)Diff) {
9274 case 1: // result = add base, cond
9275 case 2: // result = lea base( , cond*2)
9276 case 3: // result = lea base(cond, cond*2)
9277 case 4: // result = lea base( , cond*4)
9278 case 5: // result = lea base(cond, cond*4)
9279 case 8: // result = lea base( , cond*8)
9280 case 9: // result = lea base(cond, cond*8)
9281 isFastMultiplier = true;
9286 if (isFastMultiplier) {
9287 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9288 if (NeedsCondInvert) // Invert the condition if needed.
9289 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9290 DAG.getConstant(1, Cond.getValueType()));
9292 // Zero extend the condition if needed.
9293 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9295 // Scale the condition by the difference.
9297 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9298 DAG.getConstant(Diff, Cond.getValueType()));
9300 // Add the base if non-zero.
9301 if (FalseC->getAPIntValue() != 0)
9302 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9303 SDValue(FalseC, 0));
9313 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9314 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9315 TargetLowering::DAGCombinerInfo &DCI) {
9316 DebugLoc DL = N->getDebugLoc();
9318 // If the flag operand isn't dead, don't touch this CMOV.
9319 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9322 // If this is a select between two integer constants, try to do some
9323 // optimizations. Note that the operands are ordered the opposite of SELECT
9325 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9326 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9327 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9328 // larger than FalseC (the false value).
9329 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9331 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9332 CC = X86::GetOppositeBranchCondition(CC);
9333 std::swap(TrueC, FalseC);
9336 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9337 // This is efficient for any integer data type (including i8/i16) and
9339 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9340 SDValue Cond = N->getOperand(3);
9341 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9342 DAG.getConstant(CC, MVT::i8), Cond);
9344 // Zero extend the condition if needed.
9345 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9347 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9348 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9349 DAG.getConstant(ShAmt, MVT::i8));
9350 if (N->getNumValues() == 2) // Dead flag value?
9351 return DCI.CombineTo(N, Cond, SDValue());
9355 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9356 // for any integer data type, including i8/i16.
9357 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9358 SDValue Cond = N->getOperand(3);
9359 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9360 DAG.getConstant(CC, MVT::i8), Cond);
9362 // Zero extend the condition if needed.
9363 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9364 FalseC->getValueType(0), Cond);
9365 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9366 SDValue(FalseC, 0));
9368 if (N->getNumValues() == 2) // Dead flag value?
9369 return DCI.CombineTo(N, Cond, SDValue());
9373 // Optimize cases that will turn into an LEA instruction. This requires
9374 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9375 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9376 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9377 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9379 bool isFastMultiplier = false;
9381 switch ((unsigned char)Diff) {
9383 case 1: // result = add base, cond
9384 case 2: // result = lea base( , cond*2)
9385 case 3: // result = lea base(cond, cond*2)
9386 case 4: // result = lea base( , cond*4)
9387 case 5: // result = lea base(cond, cond*4)
9388 case 8: // result = lea base( , cond*8)
9389 case 9: // result = lea base(cond, cond*8)
9390 isFastMultiplier = true;
9395 if (isFastMultiplier) {
9396 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9397 SDValue Cond = N->getOperand(3);
9398 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9399 DAG.getConstant(CC, MVT::i8), Cond);
9400 // Zero extend the condition if needed.
9401 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9403 // Scale the condition by the difference.
9405 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9406 DAG.getConstant(Diff, Cond.getValueType()));
9408 // Add the base if non-zero.
9409 if (FalseC->getAPIntValue() != 0)
9410 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9411 SDValue(FalseC, 0));
9412 if (N->getNumValues() == 2) // Dead flag value?
9413 return DCI.CombineTo(N, Cond, SDValue());
9423 /// PerformMulCombine - Optimize a single multiply with constant into two
9424 /// in order to implement it with two cheaper instructions, e.g.
9425 /// LEA + SHL, LEA + LEA.
9426 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9427 TargetLowering::DAGCombinerInfo &DCI) {
9428 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9431 EVT VT = N->getValueType(0);
9435 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9438 uint64_t MulAmt = C->getZExtValue();
9439 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9442 uint64_t MulAmt1 = 0;
9443 uint64_t MulAmt2 = 0;
9444 if ((MulAmt % 9) == 0) {
9446 MulAmt2 = MulAmt / 9;
9447 } else if ((MulAmt % 5) == 0) {
9449 MulAmt2 = MulAmt / 5;
9450 } else if ((MulAmt % 3) == 0) {
9452 MulAmt2 = MulAmt / 3;
9455 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9456 DebugLoc DL = N->getDebugLoc();
9458 if (isPowerOf2_64(MulAmt2) &&
9459 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9460 // If second multiplifer is pow2, issue it first. We want the multiply by
9461 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9463 std::swap(MulAmt1, MulAmt2);
9466 if (isPowerOf2_64(MulAmt1))
9467 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9468 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9470 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9471 DAG.getConstant(MulAmt1, VT));
9473 if (isPowerOf2_64(MulAmt2))
9474 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9475 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9477 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9478 DAG.getConstant(MulAmt2, VT));
9480 // Do not add new nodes to DAG combiner worklist.
9481 DCI.CombineTo(N, NewMul, false);
9486 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9487 SDValue N0 = N->getOperand(0);
9488 SDValue N1 = N->getOperand(1);
9489 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9490 EVT VT = N0.getValueType();
9492 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9493 // since the result of setcc_c is all zero's or all ones.
9494 if (N1C && N0.getOpcode() == ISD::AND &&
9495 N0.getOperand(1).getOpcode() == ISD::Constant) {
9496 SDValue N00 = N0.getOperand(0);
9497 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9498 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9499 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9500 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9501 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9502 APInt ShAmt = N1C->getAPIntValue();
9503 Mask = Mask.shl(ShAmt);
9505 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9506 N00, DAG.getConstant(Mask, VT));
9513 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9515 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9516 const X86Subtarget *Subtarget) {
9517 EVT VT = N->getValueType(0);
9518 if (!VT.isVector() && VT.isInteger() &&
9519 N->getOpcode() == ISD::SHL)
9520 return PerformSHLCombine(N, DAG);
9522 // On X86 with SSE2 support, we can transform this to a vector shift if
9523 // all elements are shifted by the same amount. We can't do this in legalize
9524 // because the a constant vector is typically transformed to a constant pool
9525 // so we have no knowledge of the shift amount.
9526 if (!Subtarget->hasSSE2())
9529 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9532 SDValue ShAmtOp = N->getOperand(1);
9533 EVT EltVT = VT.getVectorElementType();
9534 DebugLoc DL = N->getDebugLoc();
9535 SDValue BaseShAmt = SDValue();
9536 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9537 unsigned NumElts = VT.getVectorNumElements();
9539 for (; i != NumElts; ++i) {
9540 SDValue Arg = ShAmtOp.getOperand(i);
9541 if (Arg.getOpcode() == ISD::UNDEF) continue;
9545 for (; i != NumElts; ++i) {
9546 SDValue Arg = ShAmtOp.getOperand(i);
9547 if (Arg.getOpcode() == ISD::UNDEF) continue;
9548 if (Arg != BaseShAmt) {
9552 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9553 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9554 SDValue InVec = ShAmtOp.getOperand(0);
9555 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9556 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9558 for (; i != NumElts; ++i) {
9559 SDValue Arg = InVec.getOperand(i);
9560 if (Arg.getOpcode() == ISD::UNDEF) continue;
9564 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9565 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9566 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9567 if (C->getZExtValue() == SplatIdx)
9568 BaseShAmt = InVec.getOperand(1);
9571 if (BaseShAmt.getNode() == 0)
9572 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9573 DAG.getIntPtrConstant(0));
9577 // The shift amount is an i32.
9578 if (EltVT.bitsGT(MVT::i32))
9579 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9580 else if (EltVT.bitsLT(MVT::i32))
9581 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9583 // The shift amount is identical so we can do a vector shift.
9584 SDValue ValOp = N->getOperand(0);
9585 switch (N->getOpcode()) {
9587 llvm_unreachable("Unknown shift opcode!");
9590 if (VT == MVT::v2i64)
9591 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9592 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9594 if (VT == MVT::v4i32)
9595 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9596 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9598 if (VT == MVT::v8i16)
9599 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9600 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9604 if (VT == MVT::v4i32)
9605 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9606 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9608 if (VT == MVT::v8i16)
9609 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9610 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9614 if (VT == MVT::v2i64)
9615 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9616 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9618 if (VT == MVT::v4i32)
9619 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9620 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9622 if (VT == MVT::v8i16)
9623 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9624 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9631 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9632 TargetLowering::DAGCombinerInfo &DCI,
9633 const X86Subtarget *Subtarget) {
9634 if (DCI.isBeforeLegalizeOps())
9637 EVT VT = N->getValueType(0);
9638 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
9641 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9642 SDValue N0 = N->getOperand(0);
9643 SDValue N1 = N->getOperand(1);
9644 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9646 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9648 if (!N0.hasOneUse() || !N1.hasOneUse())
9651 SDValue ShAmt0 = N0.getOperand(1);
9652 if (ShAmt0.getValueType() != MVT::i8)
9654 SDValue ShAmt1 = N1.getOperand(1);
9655 if (ShAmt1.getValueType() != MVT::i8)
9657 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9658 ShAmt0 = ShAmt0.getOperand(0);
9659 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9660 ShAmt1 = ShAmt1.getOperand(0);
9662 DebugLoc DL = N->getDebugLoc();
9663 unsigned Opc = X86ISD::SHLD;
9664 SDValue Op0 = N0.getOperand(0);
9665 SDValue Op1 = N1.getOperand(0);
9666 if (ShAmt0.getOpcode() == ISD::SUB) {
9668 std::swap(Op0, Op1);
9669 std::swap(ShAmt0, ShAmt1);
9672 unsigned Bits = VT.getSizeInBits();
9673 if (ShAmt1.getOpcode() == ISD::SUB) {
9674 SDValue Sum = ShAmt1.getOperand(0);
9675 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9676 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
9677 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
9678 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
9679 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
9680 return DAG.getNode(Opc, DL, VT,
9682 DAG.getNode(ISD::TRUNCATE, DL,
9685 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9686 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9688 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
9689 return DAG.getNode(Opc, DL, VT,
9690 N0.getOperand(0), N1.getOperand(0),
9691 DAG.getNode(ISD::TRUNCATE, DL,
9698 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9699 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9700 const X86Subtarget *Subtarget) {
9701 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9702 // the FP state in cases where an emms may be missing.
9703 // A preferable solution to the general problem is to figure out the right
9704 // places to insert EMMS. This qualifies as a quick hack.
9706 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9707 StoreSDNode *St = cast<StoreSDNode>(N);
9708 EVT VT = St->getValue().getValueType();
9709 if (VT.getSizeInBits() != 64)
9712 const Function *F = DAG.getMachineFunction().getFunction();
9713 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9714 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9715 && Subtarget->hasSSE2();
9716 if ((VT.isVector() ||
9717 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9718 isa<LoadSDNode>(St->getValue()) &&
9719 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9720 St->getChain().hasOneUse() && !St->isVolatile()) {
9721 SDNode* LdVal = St->getValue().getNode();
9723 int TokenFactorIndex = -1;
9724 SmallVector<SDValue, 8> Ops;
9725 SDNode* ChainVal = St->getChain().getNode();
9726 // Must be a store of a load. We currently handle two cases: the load
9727 // is a direct child, and it's under an intervening TokenFactor. It is
9728 // possible to dig deeper under nested TokenFactors.
9729 if (ChainVal == LdVal)
9730 Ld = cast<LoadSDNode>(St->getChain());
9731 else if (St->getValue().hasOneUse() &&
9732 ChainVal->getOpcode() == ISD::TokenFactor) {
9733 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9734 if (ChainVal->getOperand(i).getNode() == LdVal) {
9735 TokenFactorIndex = i;
9736 Ld = cast<LoadSDNode>(St->getValue());
9738 Ops.push_back(ChainVal->getOperand(i));
9742 if (!Ld || !ISD::isNormalLoad(Ld))
9745 // If this is not the MMX case, i.e. we are just turning i64 load/store
9746 // into f64 load/store, avoid the transformation if there are multiple
9747 // uses of the loaded value.
9748 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9751 DebugLoc LdDL = Ld->getDebugLoc();
9752 DebugLoc StDL = N->getDebugLoc();
9753 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9754 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9756 if (Subtarget->is64Bit() || F64IsLegal) {
9757 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9758 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9759 Ld->getBasePtr(), Ld->getSrcValue(),
9760 Ld->getSrcValueOffset(), Ld->isVolatile(),
9761 Ld->isNonTemporal(), Ld->getAlignment());
9762 SDValue NewChain = NewLd.getValue(1);
9763 if (TokenFactorIndex != -1) {
9764 Ops.push_back(NewChain);
9765 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9768 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9769 St->getSrcValue(), St->getSrcValueOffset(),
9770 St->isVolatile(), St->isNonTemporal(),
9771 St->getAlignment());
9774 // Otherwise, lower to two pairs of 32-bit loads / stores.
9775 SDValue LoAddr = Ld->getBasePtr();
9776 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9777 DAG.getConstant(4, MVT::i32));
9779 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9780 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9781 Ld->isVolatile(), Ld->isNonTemporal(),
9782 Ld->getAlignment());
9783 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9784 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9785 Ld->isVolatile(), Ld->isNonTemporal(),
9786 MinAlign(Ld->getAlignment(), 4));
9788 SDValue NewChain = LoLd.getValue(1);
9789 if (TokenFactorIndex != -1) {
9790 Ops.push_back(LoLd);
9791 Ops.push_back(HiLd);
9792 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9796 LoAddr = St->getBasePtr();
9797 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9798 DAG.getConstant(4, MVT::i32));
9800 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9801 St->getSrcValue(), St->getSrcValueOffset(),
9802 St->isVolatile(), St->isNonTemporal(),
9803 St->getAlignment());
9804 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9806 St->getSrcValueOffset() + 4,
9808 St->isNonTemporal(),
9809 MinAlign(St->getAlignment(), 4));
9810 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9815 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9816 /// X86ISD::FXOR nodes.
9817 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9818 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9819 // F[X]OR(0.0, x) -> x
9820 // F[X]OR(x, 0.0) -> x
9821 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9822 if (C->getValueAPF().isPosZero())
9823 return N->getOperand(1);
9824 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9825 if (C->getValueAPF().isPosZero())
9826 return N->getOperand(0);
9830 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9831 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9832 // FAND(0.0, x) -> 0.0
9833 // FAND(x, 0.0) -> 0.0
9834 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9835 if (C->getValueAPF().isPosZero())
9836 return N->getOperand(0);
9837 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9838 if (C->getValueAPF().isPosZero())
9839 return N->getOperand(1);
9843 static SDValue PerformBTCombine(SDNode *N,
9845 TargetLowering::DAGCombinerInfo &DCI) {
9846 // BT ignores high bits in the bit index operand.
9847 SDValue Op1 = N->getOperand(1);
9848 if (Op1.hasOneUse()) {
9849 unsigned BitWidth = Op1.getValueSizeInBits();
9850 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9851 APInt KnownZero, KnownOne;
9852 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
9853 !DCI.isBeforeLegalizeOps());
9854 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9855 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9856 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9857 DCI.CommitTargetLoweringOpt(TLO);
9862 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9863 SDValue Op = N->getOperand(0);
9864 if (Op.getOpcode() == ISD::BIT_CONVERT)
9865 Op = Op.getOperand(0);
9866 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9867 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9868 VT.getVectorElementType().getSizeInBits() ==
9869 OpVT.getVectorElementType().getSizeInBits()) {
9870 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9875 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9876 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9877 // (and (i32 x86isd::setcc_carry), 1)
9878 // This eliminates the zext. This transformation is necessary because
9879 // ISD::SETCC is always legalized to i8.
9880 DebugLoc dl = N->getDebugLoc();
9881 SDValue N0 = N->getOperand(0);
9882 EVT VT = N->getValueType(0);
9883 if (N0.getOpcode() == ISD::AND &&
9885 N0.getOperand(0).hasOneUse()) {
9886 SDValue N00 = N0.getOperand(0);
9887 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9889 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9890 if (!C || C->getZExtValue() != 1)
9892 return DAG.getNode(ISD::AND, dl, VT,
9893 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9894 N00.getOperand(0), N00.getOperand(1)),
9895 DAG.getConstant(1, VT));
9901 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9902 DAGCombinerInfo &DCI) const {
9903 SelectionDAG &DAG = DCI.DAG;
9904 switch (N->getOpcode()) {
9906 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9907 case ISD::EXTRACT_VECTOR_ELT:
9908 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
9909 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9910 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9911 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9914 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9915 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
9916 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9918 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9919 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9920 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9921 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9922 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9928 /// isTypeDesirableForOp - Return true if the target has native support for
9929 /// the specified value type and it is 'desirable' to use the type for the
9930 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
9931 /// instruction encodings are longer and some i16 instructions are slow.
9932 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
9933 if (!isTypeLegal(VT))
9942 case ISD::SIGN_EXTEND:
9943 case ISD::ZERO_EXTEND:
9944 case ISD::ANY_EXTEND:
9957 static bool MayFoldLoad(SDValue Op) {
9958 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
9961 static bool MayFoldIntoStore(SDValue Op) {
9962 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
9965 /// IsDesirableToPromoteOp - This method query the target whether it is
9966 /// beneficial for dag combiner to promote the specified node. If true, it
9967 /// should return the desired promotion type by reference.
9968 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
9969 EVT VT = Op.getValueType();
9973 bool Promote = false;
9974 bool Commute = false;
9975 switch (Op.getOpcode()) {
9978 LoadSDNode *LD = cast<LoadSDNode>(Op);
9979 // If the non-extending load has a single use and it's not live out, then it
9981 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
9983 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9984 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9985 // The only case where we'd want to promote LOAD (rather then it being
9986 // promoted as an operand is when it's only use is liveout.
9987 if (UI->getOpcode() != ISD::CopyToReg)
9994 case ISD::SIGN_EXTEND:
9995 case ISD::ZERO_EXTEND:
9996 case ISD::ANY_EXTEND:
10001 SDValue N0 = Op.getOperand(0);
10002 // Look out for (store (shl (load), x)).
10003 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
10016 SDValue N0 = Op.getOperand(0);
10017 SDValue N1 = Op.getOperand(1);
10018 if (!Commute && MayFoldLoad(N1))
10020 // Avoid disabling potential load folding opportunities.
10021 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
10023 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
10033 //===----------------------------------------------------------------------===//
10034 // X86 Inline Assembly Support
10035 //===----------------------------------------------------------------------===//
10037 static bool LowerToBSwap(CallInst *CI) {
10038 // FIXME: this should verify that we are targetting a 486 or better. If not,
10039 // we will turn this bswap into something that will be lowered to logical ops
10040 // instead of emitting the bswap asm. For now, we don't support 486 or lower
10041 // so don't worry about this.
10043 // Verify this is a simple bswap.
10044 if (CI->getNumArgOperands() != 1 ||
10045 CI->getType() != CI->getArgOperand(0)->getType() ||
10046 !CI->getType()->isIntegerTy())
10049 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10050 if (!Ty || Ty->getBitWidth() % 16 != 0)
10053 // Okay, we can do this xform, do so now.
10054 const Type *Tys[] = { Ty };
10055 Module *M = CI->getParent()->getParent()->getParent();
10056 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
10058 Value *Op = CI->getArgOperand(0);
10059 Op = CallInst::Create(Int, Op, CI->getName(), CI);
10061 CI->replaceAllUsesWith(Op);
10062 CI->eraseFromParent();
10066 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
10067 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10068 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
10070 std::string AsmStr = IA->getAsmString();
10072 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
10073 SmallVector<StringRef, 4> AsmPieces;
10074 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
10076 switch (AsmPieces.size()) {
10077 default: return false;
10079 AsmStr = AsmPieces[0];
10081 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
10084 if (AsmPieces.size() == 2 &&
10085 (AsmPieces[0] == "bswap" ||
10086 AsmPieces[0] == "bswapq" ||
10087 AsmPieces[0] == "bswapl") &&
10088 (AsmPieces[1] == "$0" ||
10089 AsmPieces[1] == "${0:q}")) {
10090 // No need to check constraints, nothing other than the equivalent of
10091 // "=r,0" would be valid here.
10092 return LowerToBSwap(CI);
10094 // rorw $$8, ${0:w} --> llvm.bswap.i16
10095 if (CI->getType()->isIntegerTy(16) &&
10096 AsmPieces.size() == 3 &&
10097 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
10098 AsmPieces[1] == "$$8," &&
10099 AsmPieces[2] == "${0:w}" &&
10100 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
10102 const std::string &Constraints = IA->getConstraintString();
10103 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
10104 std::sort(AsmPieces.begin(), AsmPieces.end());
10105 if (AsmPieces.size() == 4 &&
10106 AsmPieces[0] == "~{cc}" &&
10107 AsmPieces[1] == "~{dirflag}" &&
10108 AsmPieces[2] == "~{flags}" &&
10109 AsmPieces[3] == "~{fpsr}") {
10110 return LowerToBSwap(CI);
10115 if (CI->getType()->isIntegerTy(64) &&
10116 Constraints.size() >= 2 &&
10117 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
10118 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
10119 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
10120 SmallVector<StringRef, 4> Words;
10121 SplitString(AsmPieces[0], Words, " \t");
10122 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
10124 SplitString(AsmPieces[1], Words, " \t");
10125 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
10127 SplitString(AsmPieces[2], Words, " \t,");
10128 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
10129 Words[2] == "%edx") {
10130 return LowerToBSwap(CI);
10142 /// getConstraintType - Given a constraint letter, return the type of
10143 /// constraint it is for this target.
10144 X86TargetLowering::ConstraintType
10145 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
10146 if (Constraint.size() == 1) {
10147 switch (Constraint[0]) {
10159 return C_RegisterClass;
10167 return TargetLowering::getConstraintType(Constraint);
10170 /// LowerXConstraint - try to replace an X constraint, which matches anything,
10171 /// with another that has more specific requirements based on the type of the
10172 /// corresponding operand.
10173 const char *X86TargetLowering::
10174 LowerXConstraint(EVT ConstraintVT) const {
10175 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
10176 // 'f' like normal targets.
10177 if (ConstraintVT.isFloatingPoint()) {
10178 if (Subtarget->hasSSE2())
10180 if (Subtarget->hasSSE1())
10184 return TargetLowering::LowerXConstraint(ConstraintVT);
10187 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10188 /// vector. If it is invalid, don't add anything to Ops.
10189 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10191 std::vector<SDValue>&Ops,
10192 SelectionDAG &DAG) const {
10193 SDValue Result(0, 0);
10195 switch (Constraint) {
10198 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10199 if (C->getZExtValue() <= 31) {
10200 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10206 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10207 if (C->getZExtValue() <= 63) {
10208 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10214 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10215 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
10216 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10222 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10223 if (C->getZExtValue() <= 255) {
10224 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10230 // 32-bit signed value
10231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10232 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10233 C->getSExtValue())) {
10234 // Widen to 64 bits here to get it sign extended.
10235 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
10238 // FIXME gcc accepts some relocatable values here too, but only in certain
10239 // memory models; it's complicated.
10244 // 32-bit unsigned value
10245 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10246 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10247 C->getZExtValue())) {
10248 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10252 // FIXME gcc accepts some relocatable values here too, but only in certain
10253 // memory models; it's complicated.
10257 // Literal immediates are always ok.
10258 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
10259 // Widen to 64 bits here to get it sign extended.
10260 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10264 // In any sort of PIC mode addresses need to be computed at runtime by
10265 // adding in a register or some sort of table lookup. These can't
10266 // be used as immediates.
10267 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC() ||
10268 Subtarget->isPICStyleRIPRel())
10271 // If we are in non-pic codegen mode, we allow the address of a global (with
10272 // an optional displacement) to be used with 'i'.
10273 GlobalAddressSDNode *GA = 0;
10274 int64_t Offset = 0;
10276 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10278 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10279 Offset += GA->getOffset();
10281 } else if (Op.getOpcode() == ISD::ADD) {
10282 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10283 Offset += C->getZExtValue();
10284 Op = Op.getOperand(0);
10287 } else if (Op.getOpcode() == ISD::SUB) {
10288 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10289 Offset += -C->getZExtValue();
10290 Op = Op.getOperand(0);
10295 // Otherwise, this isn't something we can handle, reject it.
10299 const GlobalValue *GV = GA->getGlobal();
10300 // If we require an extra load to get this address, as in PIC mode, we
10301 // can't accept it.
10302 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10303 getTargetMachine())))
10306 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
10307 GA->getValueType(0), Offset);
10312 if (Result.getNode()) {
10313 Ops.push_back(Result);
10316 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10319 std::vector<unsigned> X86TargetLowering::
10320 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10322 if (Constraint.size() == 1) {
10323 // FIXME: not handling fp-stack yet!
10324 switch (Constraint[0]) { // GCC X86 Constraint Letters
10325 default: break; // Unknown constraint letter
10326 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10327 if (Subtarget->is64Bit()) {
10328 if (VT == MVT::i32)
10329 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10330 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10331 X86::R10D,X86::R11D,X86::R12D,
10332 X86::R13D,X86::R14D,X86::R15D,
10333 X86::EBP, X86::ESP, 0);
10334 else if (VT == MVT::i16)
10335 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10336 X86::SI, X86::DI, X86::R8W,X86::R9W,
10337 X86::R10W,X86::R11W,X86::R12W,
10338 X86::R13W,X86::R14W,X86::R15W,
10339 X86::BP, X86::SP, 0);
10340 else if (VT == MVT::i8)
10341 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10342 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10343 X86::R10B,X86::R11B,X86::R12B,
10344 X86::R13B,X86::R14B,X86::R15B,
10345 X86::BPL, X86::SPL, 0);
10347 else if (VT == MVT::i64)
10348 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10349 X86::RSI, X86::RDI, X86::R8, X86::R9,
10350 X86::R10, X86::R11, X86::R12,
10351 X86::R13, X86::R14, X86::R15,
10352 X86::RBP, X86::RSP, 0);
10356 // 32-bit fallthrough
10357 case 'Q': // Q_REGS
10358 if (VT == MVT::i32)
10359 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10360 else if (VT == MVT::i16)
10361 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10362 else if (VT == MVT::i8)
10363 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10364 else if (VT == MVT::i64)
10365 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10370 return std::vector<unsigned>();
10373 std::pair<unsigned, const TargetRegisterClass*>
10374 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10376 // First, see if this is a constraint that directly corresponds to an LLVM
10378 if (Constraint.size() == 1) {
10379 // GCC Constraint Letters
10380 switch (Constraint[0]) {
10382 case 'r': // GENERAL_REGS
10383 case 'l': // INDEX_REGS
10385 return std::make_pair(0U, X86::GR8RegisterClass);
10386 if (VT == MVT::i16)
10387 return std::make_pair(0U, X86::GR16RegisterClass);
10388 if (VT == MVT::i32 || !Subtarget->is64Bit())
10389 return std::make_pair(0U, X86::GR32RegisterClass);
10390 return std::make_pair(0U, X86::GR64RegisterClass);
10391 case 'R': // LEGACY_REGS
10393 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10394 if (VT == MVT::i16)
10395 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10396 if (VT == MVT::i32 || !Subtarget->is64Bit())
10397 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10398 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10399 case 'f': // FP Stack registers.
10400 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10401 // value to the correct fpstack register class.
10402 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10403 return std::make_pair(0U, X86::RFP32RegisterClass);
10404 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10405 return std::make_pair(0U, X86::RFP64RegisterClass);
10406 return std::make_pair(0U, X86::RFP80RegisterClass);
10407 case 'y': // MMX_REGS if MMX allowed.
10408 if (!Subtarget->hasMMX()) break;
10409 return std::make_pair(0U, X86::VR64RegisterClass);
10410 case 'Y': // SSE_REGS if SSE2 allowed
10411 if (!Subtarget->hasSSE2()) break;
10413 case 'x': // SSE_REGS if SSE1 allowed
10414 if (!Subtarget->hasSSE1()) break;
10416 switch (VT.getSimpleVT().SimpleTy) {
10418 // Scalar SSE types.
10421 return std::make_pair(0U, X86::FR32RegisterClass);
10424 return std::make_pair(0U, X86::FR64RegisterClass);
10432 return std::make_pair(0U, X86::VR128RegisterClass);
10438 // Use the default implementation in TargetLowering to convert the register
10439 // constraint into a member of a register class.
10440 std::pair<unsigned, const TargetRegisterClass*> Res;
10441 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10443 // Not found as a standard register?
10444 if (Res.second == 0) {
10445 // Map st(0) -> st(7) -> ST0
10446 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10447 tolower(Constraint[1]) == 's' &&
10448 tolower(Constraint[2]) == 't' &&
10449 Constraint[3] == '(' &&
10450 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10451 Constraint[5] == ')' &&
10452 Constraint[6] == '}') {
10454 Res.first = X86::ST0+Constraint[4]-'0';
10455 Res.second = X86::RFP80RegisterClass;
10459 // GCC allows "st(0)" to be called just plain "st".
10460 if (StringRef("{st}").equals_lower(Constraint)) {
10461 Res.first = X86::ST0;
10462 Res.second = X86::RFP80RegisterClass;
10467 if (StringRef("{flags}").equals_lower(Constraint)) {
10468 Res.first = X86::EFLAGS;
10469 Res.second = X86::CCRRegisterClass;
10473 // 'A' means EAX + EDX.
10474 if (Constraint == "A") {
10475 Res.first = X86::EAX;
10476 Res.second = X86::GR32_ADRegisterClass;
10482 // Otherwise, check to see if this is a register class of the wrong value
10483 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10484 // turn into {ax},{dx}.
10485 if (Res.second->hasType(VT))
10486 return Res; // Correct type already, nothing to do.
10488 // All of the single-register GCC register classes map their values onto
10489 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10490 // really want an 8-bit or 32-bit register, map to the appropriate register
10491 // class and return the appropriate register.
10492 if (Res.second == X86::GR16RegisterClass) {
10493 if (VT == MVT::i8) {
10494 unsigned DestReg = 0;
10495 switch (Res.first) {
10497 case X86::AX: DestReg = X86::AL; break;
10498 case X86::DX: DestReg = X86::DL; break;
10499 case X86::CX: DestReg = X86::CL; break;
10500 case X86::BX: DestReg = X86::BL; break;
10503 Res.first = DestReg;
10504 Res.second = X86::GR8RegisterClass;
10506 } else if (VT == MVT::i32) {
10507 unsigned DestReg = 0;
10508 switch (Res.first) {
10510 case X86::AX: DestReg = X86::EAX; break;
10511 case X86::DX: DestReg = X86::EDX; break;
10512 case X86::CX: DestReg = X86::ECX; break;
10513 case X86::BX: DestReg = X86::EBX; break;
10514 case X86::SI: DestReg = X86::ESI; break;
10515 case X86::DI: DestReg = X86::EDI; break;
10516 case X86::BP: DestReg = X86::EBP; break;
10517 case X86::SP: DestReg = X86::ESP; break;
10520 Res.first = DestReg;
10521 Res.second = X86::GR32RegisterClass;
10523 } else if (VT == MVT::i64) {
10524 unsigned DestReg = 0;
10525 switch (Res.first) {
10527 case X86::AX: DestReg = X86::RAX; break;
10528 case X86::DX: DestReg = X86::RDX; break;
10529 case X86::CX: DestReg = X86::RCX; break;
10530 case X86::BX: DestReg = X86::RBX; break;
10531 case X86::SI: DestReg = X86::RSI; break;
10532 case X86::DI: DestReg = X86::RDI; break;
10533 case X86::BP: DestReg = X86::RBP; break;
10534 case X86::SP: DestReg = X86::RSP; break;
10537 Res.first = DestReg;
10538 Res.second = X86::GR64RegisterClass;
10541 } else if (Res.second == X86::FR32RegisterClass ||
10542 Res.second == X86::FR64RegisterClass ||
10543 Res.second == X86::VR128RegisterClass) {
10544 // Handle references to XMM physical registers that got mapped into the
10545 // wrong class. This can happen with constraints like {xmm0} where the
10546 // target independent register mapper will just pick the first match it can
10547 // find, ignoring the required type.
10548 if (VT == MVT::f32)
10549 Res.second = X86::FR32RegisterClass;
10550 else if (VT == MVT::f64)
10551 Res.second = X86::FR64RegisterClass;
10552 else if (X86::VR128RegisterClass->hasType(VT))
10553 Res.second = X86::VR128RegisterClass;