1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
172 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
184 // For 64-bit since we have so many registers use the ILP scheduler, for
185 // 32-bit code use the register pressure specific scheduling.
186 if (Subtarget->is64Bit())
187 setSchedulingPreference(Sched::ILP);
189 setSchedulingPreference(Sched::RegPressure);
190 setStackPointerRegisterToSaveRestore(X86StackPtr);
192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
193 // Setup Windows compiler runtime calls.
194 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
196 setLibcallName(RTLIB::SREM_I64, "_allrem");
197 setLibcallName(RTLIB::UREM_I64, "_aullrem");
198 setLibcallName(RTLIB::MUL_I64, "_allmul");
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
210 if (Subtarget->isTargetDarwin()) {
211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
212 setUseUnderscoreSetJmp(false);
213 setUseUnderscoreLongJmp(false);
214 } else if (Subtarget->isTargetMingw()) {
215 // MS runtime is weird: it exports _setjmp, but longjmp!
216 setUseUnderscoreSetJmp(true);
217 setUseUnderscoreLongJmp(false);
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(true);
223 // Set up the register classes.
224 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
225 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
226 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
227 if (Subtarget->is64Bit())
228 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
232 // We don't accept any truncstore of integer registers.
233 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
240 // SETOEQ and SETUNE require checking two conditions.
241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
257 } else if (!UseSoftFloat) {
258 // We have an algorithm for SSE2->double, and we turn this into a
259 // 64-bit FILD followed by conditional FADD for other targets.
260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
261 // We have an algorithm for SSE2, and we turn this into a 64-bit
262 // FILD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
272 // SSE has no i16 to fp conversion, only i32
273 if (X86ScalarSSEf32) {
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
275 // f32 and f64 cases are Legal, f80 case is not
276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
287 // are Legal, f80 is custom lowered.
288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
296 if (X86ScalarSSEf32) {
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
298 // f32 and f64 cases are Legal, f80 case is not
299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
305 // Handle FP_TO_UINT by promoting the destination to a larger signed
307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
314 } else if (!UseSoftFloat) {
315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
443 if (Subtarget->is64Bit()) {
444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
449 if (Subtarget->hasXMM())
450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
452 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
453 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
455 // On X86 and X86-64, atomic operations are lowered to locked instructions.
456 // Locked instructions, in turn, have implicit fence semantics (all memory
457 // operations are flushed before issuing the locked instruction, and they
458 // are not buffered), so we can fold away the common pattern of
459 // fence-atomic-fence.
460 setShouldFoldAtomicFences(true);
462 // Expand certain atomics
463 for (unsigned i = 0, e = 4; i != e; ++i) {
465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
467 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
470 if (!Subtarget->is64Bit()) {
471 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
477 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
478 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
481 // FIXME - use subtarget debug flags
482 if (!Subtarget->isTargetDarwin() &&
483 !Subtarget->isTargetELF() &&
484 !Subtarget->isTargetCygMing()) {
485 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
488 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
489 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
490 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
491 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
492 if (Subtarget->is64Bit()) {
493 setExceptionPointerRegister(X86::RAX);
494 setExceptionSelectorRegister(X86::RDX);
496 setExceptionPointerRegister(X86::EAX);
497 setExceptionSelectorRegister(X86::EDX);
499 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
500 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
502 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
504 setOperationAction(ISD::TRAP, MVT::Other, Legal);
506 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
507 setOperationAction(ISD::VASTART , MVT::Other, Custom);
508 setOperationAction(ISD::VAEND , MVT::Other, Expand);
509 if (Subtarget->is64Bit()) {
510 setOperationAction(ISD::VAARG , MVT::Other, Custom);
511 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
513 setOperationAction(ISD::VAARG , MVT::Other, Expand);
514 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
517 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
518 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
519 setOperationAction(ISD::DYNAMIC_STACKALLOC,
520 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
521 (Subtarget->isTargetCOFF()
522 && !Subtarget->isTargetEnvMacho()
525 if (!UseSoftFloat && X86ScalarSSEf64) {
526 // f32 and f64 use SSE.
527 // Set up the FP register classes.
528 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
529 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
531 // Use ANDPD to simulate FABS.
532 setOperationAction(ISD::FABS , MVT::f64, Custom);
533 setOperationAction(ISD::FABS , MVT::f32, Custom);
535 // Use XORP to simulate FNEG.
536 setOperationAction(ISD::FNEG , MVT::f64, Custom);
537 setOperationAction(ISD::FNEG , MVT::f32, Custom);
539 // Use ANDPD and ORPD to simulate FCOPYSIGN.
540 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
541 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
543 // Lower this to FGETSIGNx86 plus an AND.
544 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
545 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
547 // We don't support sin/cos/fmod
548 setOperationAction(ISD::FSIN , MVT::f64, Expand);
549 setOperationAction(ISD::FCOS , MVT::f64, Expand);
550 setOperationAction(ISD::FSIN , MVT::f32, Expand);
551 setOperationAction(ISD::FCOS , MVT::f32, Expand);
553 // Expand FP immediates into loads from the stack, except for the special
555 addLegalFPImmediate(APFloat(+0.0)); // xorpd
556 addLegalFPImmediate(APFloat(+0.0f)); // xorps
557 } else if (!UseSoftFloat && X86ScalarSSEf32) {
558 // Use SSE for f32, x87 for f64.
559 // Set up the FP register classes.
560 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
561 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
563 // Use ANDPS to simulate FABS.
564 setOperationAction(ISD::FABS , MVT::f32, Custom);
566 // Use XORP to simulate FNEG.
567 setOperationAction(ISD::FNEG , MVT::f32, Custom);
569 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
571 // Use ANDPS and ORPS to simulate FCOPYSIGN.
572 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
573 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
575 // We don't support sin/cos/fmod
576 setOperationAction(ISD::FSIN , MVT::f32, Expand);
577 setOperationAction(ISD::FCOS , MVT::f32, Expand);
579 // Special cases we handle for FP constants.
580 addLegalFPImmediate(APFloat(+0.0f)); // xorps
581 addLegalFPImmediate(APFloat(+0.0)); // FLD0
582 addLegalFPImmediate(APFloat(+1.0)); // FLD1
583 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
584 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
587 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
588 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
590 } else if (!UseSoftFloat) {
591 // f32 and f64 in x87.
592 // Set up the FP register classes.
593 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
594 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
596 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
597 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
599 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
602 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
603 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
605 addLegalFPImmediate(APFloat(+0.0)); // FLD0
606 addLegalFPImmediate(APFloat(+1.0)); // FLD1
607 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
608 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
609 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
610 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
611 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
612 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
615 // We don't support FMA.
616 setOperationAction(ISD::FMA, MVT::f64, Expand);
617 setOperationAction(ISD::FMA, MVT::f32, Expand);
619 // Long double always uses X87.
621 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
622 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
623 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
625 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
626 addLegalFPImmediate(TmpFlt); // FLD0
628 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
631 APFloat TmpFlt2(+1.0);
632 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
634 addLegalFPImmediate(TmpFlt2); // FLD1
635 TmpFlt2.changeSign();
636 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
640 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
644 setOperationAction(ISD::FMA, MVT::f80, Expand);
647 // Always use a library call for pow.
648 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
649 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
650 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
652 setOperationAction(ISD::FLOG, MVT::f80, Expand);
653 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
654 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
655 setOperationAction(ISD::FEXP, MVT::f80, Expand);
656 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
658 // First set operation action for all vector types to either promote
659 // (for widening) or expand (for scalarization). Then we will selectively
660 // turn on ones that can be effectively codegen'd.
661 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
662 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
663 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
664 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
665 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
666 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
667 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
668 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
669 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
670 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
671 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
672 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
673 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
674 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
675 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
676 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
678 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
679 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
680 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
681 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
713 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
717 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
718 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
719 setTruncStoreAction((MVT::SimpleValueType)VT,
720 (MVT::SimpleValueType)InnerVT, Expand);
721 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
722 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
723 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
726 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
727 // with -msoft-float, disable use of MMX as well.
728 if (!UseSoftFloat && Subtarget->hasMMX()) {
729 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
730 // No operations on x86mmx supported, everything uses intrinsics.
733 // MMX-sized vectors (other than x86mmx) are expected to be expanded
734 // into smaller operations.
735 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
736 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
737 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
738 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
739 setOperationAction(ISD::AND, MVT::v8i8, Expand);
740 setOperationAction(ISD::AND, MVT::v4i16, Expand);
741 setOperationAction(ISD::AND, MVT::v2i32, Expand);
742 setOperationAction(ISD::AND, MVT::v1i64, Expand);
743 setOperationAction(ISD::OR, MVT::v8i8, Expand);
744 setOperationAction(ISD::OR, MVT::v4i16, Expand);
745 setOperationAction(ISD::OR, MVT::v2i32, Expand);
746 setOperationAction(ISD::OR, MVT::v1i64, Expand);
747 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
748 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
749 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
750 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
751 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
754 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
756 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
757 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
758 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
759 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
760 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
761 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
762 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
763 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
765 if (!UseSoftFloat && Subtarget->hasXMM()) {
766 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
768 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
769 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
770 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
771 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
772 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
773 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
774 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
775 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
776 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
777 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
778 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
779 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
782 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
783 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
785 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
786 // registers cannot be used even for integer operations.
787 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
788 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
789 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
790 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
792 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
793 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
794 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
795 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
796 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
797 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
798 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
799 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
800 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
801 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
802 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
803 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
804 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
805 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
806 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
807 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
809 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
810 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
811 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
812 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
814 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
815 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
817 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
818 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
821 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
822 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
823 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
824 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
826 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
827 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
828 EVT VT = (MVT::SimpleValueType)i;
829 // Do not attempt to custom lower non-power-of-2 vectors
830 if (!isPowerOf2_32(VT.getVectorNumElements()))
832 // Do not attempt to custom lower non-128-bit vectors
833 if (!VT.is128BitVector())
835 setOperationAction(ISD::BUILD_VECTOR,
836 VT.getSimpleVT().SimpleTy, Custom);
837 setOperationAction(ISD::VECTOR_SHUFFLE,
838 VT.getSimpleVT().SimpleTy, Custom);
839 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
840 VT.getSimpleVT().SimpleTy, Custom);
843 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
844 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
845 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
846 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
848 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
850 if (Subtarget->is64Bit()) {
851 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
855 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
856 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
857 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
860 // Do not attempt to promote non-128-bit vectors
861 if (!VT.is128BitVector())
864 setOperationAction(ISD::AND, SVT, Promote);
865 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
866 setOperationAction(ISD::OR, SVT, Promote);
867 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
868 setOperationAction(ISD::XOR, SVT, Promote);
869 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
870 setOperationAction(ISD::LOAD, SVT, Promote);
871 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
872 setOperationAction(ISD::SELECT, SVT, Promote);
873 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
876 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
878 // Custom lower v2i64 and v2f64 selects.
879 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
880 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
881 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
882 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
884 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
885 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
888 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
889 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
890 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
891 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
892 setOperationAction(ISD::FRINT, MVT::f32, Legal);
893 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
894 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
895 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
896 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
897 setOperationAction(ISD::FRINT, MVT::f64, Legal);
898 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
900 // FIXME: Do we need to handle scalar-to-vector here?
901 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
903 // Can turn SHL into an integer multiply.
904 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
905 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
907 // i8 and i16 vectors are custom , because the source register and source
908 // source memory operand types are not the same width. f32 vectors are
909 // custom since the immediate controlling the insert encodes additional
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
913 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
914 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
916 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
918 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
921 if (Subtarget->is64Bit()) {
922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
927 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
928 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
929 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
930 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
931 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
933 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
934 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
935 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
937 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
938 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
941 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
942 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
944 if (!UseSoftFloat && Subtarget->hasAVX()) {
945 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
946 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
947 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
948 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
949 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
950 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
952 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
953 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
954 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
956 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
957 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
958 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
959 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
960 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
961 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
963 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
964 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
965 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
966 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
967 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
968 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
970 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
971 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
972 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
974 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
975 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
976 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
977 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
978 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
979 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
981 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
982 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
983 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
984 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
986 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
987 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
988 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
989 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
991 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
992 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
994 setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
995 setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
996 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
997 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
999 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1000 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1001 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1003 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1004 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1005 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1006 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1008 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1009 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1010 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1011 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1013 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1014 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1015 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1016 // Don't lower v32i8 because there is no 128-bit byte mul
1018 // Custom lower several nodes for 256-bit types.
1019 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1020 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1021 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1024 // Extract subvector is special because the value type
1025 // (result) is 128-bit but the source is 256-bit wide.
1026 if (VT.is128BitVector())
1027 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1029 // Do not attempt to custom lower other non-256-bit vectors
1030 if (!VT.is256BitVector())
1033 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1037 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1038 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1041 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1042 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1043 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1046 // Do not attempt to promote non-256-bit vectors
1047 if (!VT.is256BitVector())
1050 setOperationAction(ISD::AND, SVT, Promote);
1051 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1052 setOperationAction(ISD::OR, SVT, Promote);
1053 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1054 setOperationAction(ISD::XOR, SVT, Promote);
1055 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1056 setOperationAction(ISD::LOAD, SVT, Promote);
1057 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1058 setOperationAction(ISD::SELECT, SVT, Promote);
1059 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1063 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1064 // of this type with custom code.
1065 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1066 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1067 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1070 // We want to custom lower some of our intrinsics.
1071 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1074 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1075 // handle type legalization for these operations here.
1077 // FIXME: We really should do custom legalization for addition and
1078 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1079 // than generic legalization for 64-bit multiplication-with-overflow, though.
1080 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1081 // Add/Sub/Mul with overflow operations are custom lowered.
1083 setOperationAction(ISD::SADDO, VT, Custom);
1084 setOperationAction(ISD::UADDO, VT, Custom);
1085 setOperationAction(ISD::SSUBO, VT, Custom);
1086 setOperationAction(ISD::USUBO, VT, Custom);
1087 setOperationAction(ISD::SMULO, VT, Custom);
1088 setOperationAction(ISD::UMULO, VT, Custom);
1091 // There are no 8-bit 3-address imul/mul instructions
1092 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1093 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1095 if (!Subtarget->is64Bit()) {
1096 // These libcalls are not available in 32-bit.
1097 setLibcallName(RTLIB::SHL_I128, 0);
1098 setLibcallName(RTLIB::SRL_I128, 0);
1099 setLibcallName(RTLIB::SRA_I128, 0);
1102 // We have target-specific dag combine patterns for the following nodes:
1103 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1104 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1105 setTargetDAGCombine(ISD::BUILD_VECTOR);
1106 setTargetDAGCombine(ISD::SELECT);
1107 setTargetDAGCombine(ISD::SHL);
1108 setTargetDAGCombine(ISD::SRA);
1109 setTargetDAGCombine(ISD::SRL);
1110 setTargetDAGCombine(ISD::OR);
1111 setTargetDAGCombine(ISD::AND);
1112 setTargetDAGCombine(ISD::ADD);
1113 setTargetDAGCombine(ISD::SUB);
1114 setTargetDAGCombine(ISD::STORE);
1115 setTargetDAGCombine(ISD::ZERO_EXTEND);
1116 setTargetDAGCombine(ISD::SINT_TO_FP);
1117 if (Subtarget->is64Bit())
1118 setTargetDAGCombine(ISD::MUL);
1120 computeRegisterProperties();
1122 // On Darwin, -Os means optimize for size without hurting performance,
1123 // do not reduce the limit.
1124 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1125 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1126 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1127 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1128 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1129 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1130 setPrefLoopAlignment(16);
1131 benefitFromCodePlacementOpt = true;
1133 setPrefFunctionAlignment(4);
1137 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1142 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1143 /// the desired ByVal argument alignment.
1144 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1147 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1148 if (VTy->getBitWidth() == 128)
1150 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1151 unsigned EltAlign = 0;
1152 getMaxByValAlign(ATy->getElementType(), EltAlign);
1153 if (EltAlign > MaxAlign)
1154 MaxAlign = EltAlign;
1155 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1156 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1157 unsigned EltAlign = 0;
1158 getMaxByValAlign(STy->getElementType(i), EltAlign);
1159 if (EltAlign > MaxAlign)
1160 MaxAlign = EltAlign;
1168 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1169 /// function arguments in the caller parameter area. For X86, aggregates
1170 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1171 /// are at 4-byte boundaries.
1172 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1173 if (Subtarget->is64Bit()) {
1174 // Max of 8 and alignment of type.
1175 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1182 if (Subtarget->hasXMM())
1183 getMaxByValAlign(Ty, Align);
1187 /// getOptimalMemOpType - Returns the target specific optimal type for load
1188 /// and store operations as a result of memset, memcpy, and memmove
1189 /// lowering. If DstAlign is zero that means it's safe to destination
1190 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1191 /// means there isn't a need to check it against alignment requirement,
1192 /// probably because the source does not need to be loaded. If
1193 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1194 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1195 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1196 /// constant so it does not need to be loaded.
1197 /// It returns EVT::Other if the type should be determined using generic
1198 /// target-independent logic.
1200 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1201 unsigned DstAlign, unsigned SrcAlign,
1202 bool NonScalarIntSafe,
1204 MachineFunction &MF) const {
1205 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1206 // linux. This is because the stack realignment code can't handle certain
1207 // cases like PR2962. This should be removed when PR2962 is fixed.
1208 const Function *F = MF.getFunction();
1209 if (NonScalarIntSafe &&
1210 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1212 (Subtarget->isUnalignedMemAccessFast() ||
1213 ((DstAlign == 0 || DstAlign >= 16) &&
1214 (SrcAlign == 0 || SrcAlign >= 16))) &&
1215 Subtarget->getStackAlignment() >= 16) {
1216 if (Subtarget->hasSSE2())
1218 if (Subtarget->hasSSE1())
1220 } else if (!MemcpyStrSrc && Size >= 8 &&
1221 !Subtarget->is64Bit() &&
1222 Subtarget->getStackAlignment() >= 8 &&
1223 Subtarget->hasXMMInt()) {
1224 // Do not use f64 to lower memcpy if source is string constant. It's
1225 // better to use i32 to avoid the loads.
1229 if (Subtarget->is64Bit() && Size >= 8)
1234 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1235 /// current function. The returned value is a member of the
1236 /// MachineJumpTableInfo::JTEntryKind enum.
1237 unsigned X86TargetLowering::getJumpTableEncoding() const {
1238 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1240 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1241 Subtarget->isPICStyleGOT())
1242 return MachineJumpTableInfo::EK_Custom32;
1244 // Otherwise, use the normal jump table encoding heuristics.
1245 return TargetLowering::getJumpTableEncoding();
1249 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1250 const MachineBasicBlock *MBB,
1251 unsigned uid,MCContext &Ctx) const{
1252 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1253 Subtarget->isPICStyleGOT());
1254 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1256 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1257 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1260 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1262 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1263 SelectionDAG &DAG) const {
1264 if (!Subtarget->is64Bit())
1265 // This doesn't have DebugLoc associated with it, but is not really the
1266 // same as a Register.
1267 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1271 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1272 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1274 const MCExpr *X86TargetLowering::
1275 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1276 MCContext &Ctx) const {
1277 // X86-64 uses RIP relative addressing based on the jump table label.
1278 if (Subtarget->isPICStyleRIPRel())
1279 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1281 // Otherwise, the reference is relative to the PIC base.
1282 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1285 // FIXME: Why this routine is here? Move to RegInfo!
1286 std::pair<const TargetRegisterClass*, uint8_t>
1287 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1288 const TargetRegisterClass *RRC = 0;
1290 switch (VT.getSimpleVT().SimpleTy) {
1292 return TargetLowering::findRepresentativeClass(VT);
1293 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1294 RRC = (Subtarget->is64Bit()
1295 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1298 RRC = X86::VR64RegisterClass;
1300 case MVT::f32: case MVT::f64:
1301 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1302 case MVT::v4f32: case MVT::v2f64:
1303 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1305 RRC = X86::VR128RegisterClass;
1308 return std::make_pair(RRC, Cost);
1311 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1312 unsigned &Offset) const {
1313 if (!Subtarget->isTargetLinux())
1316 if (Subtarget->is64Bit()) {
1317 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1319 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1332 //===----------------------------------------------------------------------===//
1333 // Return Value Calling Convention Implementation
1334 //===----------------------------------------------------------------------===//
1336 #include "X86GenCallingConv.inc"
1339 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1340 MachineFunction &MF, bool isVarArg,
1341 const SmallVectorImpl<ISD::OutputArg> &Outs,
1342 LLVMContext &Context) const {
1343 SmallVector<CCValAssign, 16> RVLocs;
1344 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1346 return CCInfo.CheckReturn(Outs, RetCC_X86);
1350 X86TargetLowering::LowerReturn(SDValue Chain,
1351 CallingConv::ID CallConv, bool isVarArg,
1352 const SmallVectorImpl<ISD::OutputArg> &Outs,
1353 const SmallVectorImpl<SDValue> &OutVals,
1354 DebugLoc dl, SelectionDAG &DAG) const {
1355 MachineFunction &MF = DAG.getMachineFunction();
1356 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1358 SmallVector<CCValAssign, 16> RVLocs;
1359 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1360 RVLocs, *DAG.getContext());
1361 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1363 // Add the regs to the liveout set for the function.
1364 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1365 for (unsigned i = 0; i != RVLocs.size(); ++i)
1366 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1367 MRI.addLiveOut(RVLocs[i].getLocReg());
1371 SmallVector<SDValue, 6> RetOps;
1372 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1373 // Operand #1 = Bytes To Pop
1374 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1377 // Copy the result values into the output registers.
1378 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1379 CCValAssign &VA = RVLocs[i];
1380 assert(VA.isRegLoc() && "Can only return in registers!");
1381 SDValue ValToCopy = OutVals[i];
1382 EVT ValVT = ValToCopy.getValueType();
1384 // If this is x86-64, and we disabled SSE, we can't return FP values,
1385 // or SSE or MMX vectors.
1386 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1387 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1388 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1389 report_fatal_error("SSE register return with SSE disabled");
1391 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1392 // llvm-gcc has never done it right and no one has noticed, so this
1393 // should be OK for now.
1394 if (ValVT == MVT::f64 &&
1395 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1396 report_fatal_error("SSE2 register return with SSE2 disabled");
1398 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1399 // the RET instruction and handled by the FP Stackifier.
1400 if (VA.getLocReg() == X86::ST0 ||
1401 VA.getLocReg() == X86::ST1) {
1402 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1403 // change the value to the FP stack register class.
1404 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1405 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1406 RetOps.push_back(ValToCopy);
1407 // Don't emit a copytoreg.
1411 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1412 // which is returned in RAX / RDX.
1413 if (Subtarget->is64Bit()) {
1414 if (ValVT == MVT::x86mmx) {
1415 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1416 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1417 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1419 // If we don't have SSE2 available, convert to v4f32 so the generated
1420 // register is legal.
1421 if (!Subtarget->hasSSE2())
1422 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1427 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1428 Flag = Chain.getValue(1);
1431 // The x86-64 ABI for returning structs by value requires that we copy
1432 // the sret argument into %rax for the return. We saved the argument into
1433 // a virtual register in the entry block, so now we copy the value out
1435 if (Subtarget->is64Bit() &&
1436 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1437 MachineFunction &MF = DAG.getMachineFunction();
1438 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1439 unsigned Reg = FuncInfo->getSRetReturnReg();
1441 "SRetReturnReg should have been set in LowerFormalArguments().");
1442 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1444 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1445 Flag = Chain.getValue(1);
1447 // RAX now acts like a return value.
1448 MRI.addLiveOut(X86::RAX);
1451 RetOps[0] = Chain; // Update chain.
1453 // Add the flag if we have it.
1455 RetOps.push_back(Flag);
1457 return DAG.getNode(X86ISD::RET_FLAG, dl,
1458 MVT::Other, &RetOps[0], RetOps.size());
1461 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1462 if (N->getNumValues() != 1)
1464 if (!N->hasNUsesOfValue(1, 0))
1467 SDNode *Copy = *N->use_begin();
1468 if (Copy->getOpcode() != ISD::CopyToReg &&
1469 Copy->getOpcode() != ISD::FP_EXTEND)
1472 bool HasRet = false;
1473 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1475 if (UI->getOpcode() != X86ISD::RET_FLAG)
1484 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1485 ISD::NodeType ExtendKind) const {
1487 // TODO: Is this also valid on 32-bit?
1488 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1489 ReturnMVT = MVT::i8;
1491 ReturnMVT = MVT::i32;
1493 EVT MinVT = getRegisterType(Context, ReturnMVT);
1494 return VT.bitsLT(MinVT) ? MinVT : VT;
1497 /// LowerCallResult - Lower the result values of a call into the
1498 /// appropriate copies out of appropriate physical registers.
1501 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1502 CallingConv::ID CallConv, bool isVarArg,
1503 const SmallVectorImpl<ISD::InputArg> &Ins,
1504 DebugLoc dl, SelectionDAG &DAG,
1505 SmallVectorImpl<SDValue> &InVals) const {
1507 // Assign locations to each value returned by this call.
1508 SmallVector<CCValAssign, 16> RVLocs;
1509 bool Is64Bit = Subtarget->is64Bit();
1510 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1511 getTargetMachine(), RVLocs, *DAG.getContext());
1512 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1514 // Copy all of the result registers out of their specified physreg.
1515 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1516 CCValAssign &VA = RVLocs[i];
1517 EVT CopyVT = VA.getValVT();
1519 // If this is x86-64, and we disabled SSE, we can't return FP values
1520 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1521 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1522 report_fatal_error("SSE register return with SSE disabled");
1527 // If this is a call to a function that returns an fp value on the floating
1528 // point stack, we must guarantee the the value is popped from the stack, so
1529 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1530 // if the return value is not used. We use the FpPOP_RETVAL instruction
1532 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1533 // If we prefer to use the value in xmm registers, copy it out as f80 and
1534 // use a truncate to move it from fp stack reg to xmm reg.
1535 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1536 SDValue Ops[] = { Chain, InFlag };
1537 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1538 MVT::Other, MVT::Glue, Ops, 2), 1);
1539 Val = Chain.getValue(0);
1541 // Round the f80 to the right size, which also moves it to the appropriate
1543 if (CopyVT != VA.getValVT())
1544 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1545 // This truncation won't change the value.
1546 DAG.getIntPtrConstant(1));
1548 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1549 CopyVT, InFlag).getValue(1);
1550 Val = Chain.getValue(0);
1552 InFlag = Chain.getValue(2);
1553 InVals.push_back(Val);
1560 //===----------------------------------------------------------------------===//
1561 // C & StdCall & Fast Calling Convention implementation
1562 //===----------------------------------------------------------------------===//
1563 // StdCall calling convention seems to be standard for many Windows' API
1564 // routines and around. It differs from C calling convention just a little:
1565 // callee should clean up the stack, not caller. Symbols should be also
1566 // decorated in some fancy way :) It doesn't support any vector arguments.
1567 // For info on fast calling convention see Fast Calling Convention (tail call)
1568 // implementation LowerX86_32FastCCCallTo.
1570 /// CallIsStructReturn - Determines whether a call uses struct return
1572 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1576 return Outs[0].Flags.isSRet();
1579 /// ArgsAreStructReturn - Determines whether a function uses struct
1580 /// return semantics.
1582 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1586 return Ins[0].Flags.isSRet();
1589 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1590 /// by "Src" to address "Dst" with size and alignment information specified by
1591 /// the specific parameter attribute. The copy will be passed as a byval
1592 /// function parameter.
1594 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1595 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1597 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1599 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1600 /*isVolatile*/false, /*AlwaysInline=*/true,
1601 MachinePointerInfo(), MachinePointerInfo());
1604 /// IsTailCallConvention - Return true if the calling convention is one that
1605 /// supports tail call optimization.
1606 static bool IsTailCallConvention(CallingConv::ID CC) {
1607 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1610 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1611 if (!CI->isTailCall())
1615 CallingConv::ID CalleeCC = CS.getCallingConv();
1616 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1622 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1623 /// a tailcall target by changing its ABI.
1624 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1625 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1629 X86TargetLowering::LowerMemArgument(SDValue Chain,
1630 CallingConv::ID CallConv,
1631 const SmallVectorImpl<ISD::InputArg> &Ins,
1632 DebugLoc dl, SelectionDAG &DAG,
1633 const CCValAssign &VA,
1634 MachineFrameInfo *MFI,
1636 // Create the nodes corresponding to a load from this parameter slot.
1637 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1638 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1639 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1642 // If value is passed by pointer we have address passed instead of the value
1644 if (VA.getLocInfo() == CCValAssign::Indirect)
1645 ValVT = VA.getLocVT();
1647 ValVT = VA.getValVT();
1649 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1650 // changed with more analysis.
1651 // In case of tail call optimization mark all arguments mutable. Since they
1652 // could be overwritten by lowering of arguments in case of a tail call.
1653 if (Flags.isByVal()) {
1654 unsigned Bytes = Flags.getByValSize();
1655 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1656 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1657 return DAG.getFrameIndex(FI, getPointerTy());
1659 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1660 VA.getLocMemOffset(), isImmutable);
1661 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1662 return DAG.getLoad(ValVT, dl, Chain, FIN,
1663 MachinePointerInfo::getFixedStack(FI),
1669 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1670 CallingConv::ID CallConv,
1672 const SmallVectorImpl<ISD::InputArg> &Ins,
1675 SmallVectorImpl<SDValue> &InVals)
1677 MachineFunction &MF = DAG.getMachineFunction();
1678 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1680 const Function* Fn = MF.getFunction();
1681 if (Fn->hasExternalLinkage() &&
1682 Subtarget->isTargetCygMing() &&
1683 Fn->getName() == "main")
1684 FuncInfo->setForceFramePointer(true);
1686 MachineFrameInfo *MFI = MF.getFrameInfo();
1687 bool Is64Bit = Subtarget->is64Bit();
1688 bool IsWin64 = Subtarget->isTargetWin64();
1690 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1691 "Var args not supported with calling convention fastcc or ghc");
1693 // Assign locations to all of the incoming arguments.
1694 SmallVector<CCValAssign, 16> ArgLocs;
1695 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1696 ArgLocs, *DAG.getContext());
1698 // Allocate shadow area for Win64
1700 CCInfo.AllocateStack(32, 8);
1703 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1705 unsigned LastVal = ~0U;
1707 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1708 CCValAssign &VA = ArgLocs[i];
1709 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1711 assert(VA.getValNo() != LastVal &&
1712 "Don't support value assigned to multiple locs yet");
1713 LastVal = VA.getValNo();
1715 if (VA.isRegLoc()) {
1716 EVT RegVT = VA.getLocVT();
1717 TargetRegisterClass *RC = NULL;
1718 if (RegVT == MVT::i32)
1719 RC = X86::GR32RegisterClass;
1720 else if (Is64Bit && RegVT == MVT::i64)
1721 RC = X86::GR64RegisterClass;
1722 else if (RegVT == MVT::f32)
1723 RC = X86::FR32RegisterClass;
1724 else if (RegVT == MVT::f64)
1725 RC = X86::FR64RegisterClass;
1726 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1727 RC = X86::VR256RegisterClass;
1728 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1729 RC = X86::VR128RegisterClass;
1730 else if (RegVT == MVT::x86mmx)
1731 RC = X86::VR64RegisterClass;
1733 llvm_unreachable("Unknown argument type!");
1735 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1736 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1738 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1739 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1741 if (VA.getLocInfo() == CCValAssign::SExt)
1742 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1743 DAG.getValueType(VA.getValVT()));
1744 else if (VA.getLocInfo() == CCValAssign::ZExt)
1745 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1746 DAG.getValueType(VA.getValVT()));
1747 else if (VA.getLocInfo() == CCValAssign::BCvt)
1748 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1750 if (VA.isExtInLoc()) {
1751 // Handle MMX values passed in XMM regs.
1752 if (RegVT.isVector()) {
1753 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1756 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1759 assert(VA.isMemLoc());
1760 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1763 // If value is passed via pointer - do a load.
1764 if (VA.getLocInfo() == CCValAssign::Indirect)
1765 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1766 MachinePointerInfo(), false, false, 0);
1768 InVals.push_back(ArgValue);
1771 // The x86-64 ABI for returning structs by value requires that we copy
1772 // the sret argument into %rax for the return. Save the argument into
1773 // a virtual register so that we can access it from the return points.
1774 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1775 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1776 unsigned Reg = FuncInfo->getSRetReturnReg();
1778 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1779 FuncInfo->setSRetReturnReg(Reg);
1781 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1785 unsigned StackSize = CCInfo.getNextStackOffset();
1786 // Align stack specially for tail calls.
1787 if (FuncIsMadeTailCallSafe(CallConv))
1788 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1790 // If the function takes variable number of arguments, make a frame index for
1791 // the start of the first vararg value... for expansion of llvm.va_start.
1793 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1794 CallConv != CallingConv::X86_ThisCall)) {
1795 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1798 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1800 // FIXME: We should really autogenerate these arrays
1801 static const unsigned GPR64ArgRegsWin64[] = {
1802 X86::RCX, X86::RDX, X86::R8, X86::R9
1804 static const unsigned GPR64ArgRegs64Bit[] = {
1805 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1807 static const unsigned XMMArgRegs64Bit[] = {
1808 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1809 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1811 const unsigned *GPR64ArgRegs;
1812 unsigned NumXMMRegs = 0;
1815 // The XMM registers which might contain var arg parameters are shadowed
1816 // in their paired GPR. So we only need to save the GPR to their home
1818 TotalNumIntRegs = 4;
1819 GPR64ArgRegs = GPR64ArgRegsWin64;
1821 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1822 GPR64ArgRegs = GPR64ArgRegs64Bit;
1824 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1826 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1829 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1830 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1831 "SSE register cannot be used when SSE is disabled!");
1832 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1833 "SSE register cannot be used when SSE is disabled!");
1834 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1835 // Kernel mode asks for SSE to be disabled, so don't push them
1837 TotalNumXMMRegs = 0;
1840 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1841 // Get to the caller-allocated home save location. Add 8 to account
1842 // for the return address.
1843 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1844 FuncInfo->setRegSaveFrameIndex(
1845 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1846 // Fixup to set vararg frame on shadow area (4 x i64).
1848 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1850 // For X86-64, if there are vararg parameters that are passed via
1851 // registers, then we must store them to their spots on the stack so they
1852 // may be loaded by deferencing the result of va_next.
1853 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1854 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1855 FuncInfo->setRegSaveFrameIndex(
1856 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1860 // Store the integer parameter registers.
1861 SmallVector<SDValue, 8> MemOps;
1862 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1864 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1865 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1866 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1867 DAG.getIntPtrConstant(Offset));
1868 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1869 X86::GR64RegisterClass);
1870 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1872 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1873 MachinePointerInfo::getFixedStack(
1874 FuncInfo->getRegSaveFrameIndex(), Offset),
1876 MemOps.push_back(Store);
1880 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1881 // Now store the XMM (fp + vector) parameter registers.
1882 SmallVector<SDValue, 11> SaveXMMOps;
1883 SaveXMMOps.push_back(Chain);
1885 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1886 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1887 SaveXMMOps.push_back(ALVal);
1889 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1890 FuncInfo->getRegSaveFrameIndex()));
1891 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1892 FuncInfo->getVarArgsFPOffset()));
1894 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1895 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1896 X86::VR128RegisterClass);
1897 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1898 SaveXMMOps.push_back(Val);
1900 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1902 &SaveXMMOps[0], SaveXMMOps.size()));
1905 if (!MemOps.empty())
1906 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1907 &MemOps[0], MemOps.size());
1911 // Some CCs need callee pop.
1912 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1913 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1915 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1916 // If this is an sret function, the return should pop the hidden pointer.
1917 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1918 FuncInfo->setBytesToPopOnReturn(4);
1922 // RegSaveFrameIndex is X86-64 only.
1923 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1924 if (CallConv == CallingConv::X86_FastCall ||
1925 CallConv == CallingConv::X86_ThisCall)
1926 // fastcc functions can't have varargs.
1927 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1934 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1935 SDValue StackPtr, SDValue Arg,
1936 DebugLoc dl, SelectionDAG &DAG,
1937 const CCValAssign &VA,
1938 ISD::ArgFlagsTy Flags) const {
1939 unsigned LocMemOffset = VA.getLocMemOffset();
1940 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1941 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1942 if (Flags.isByVal())
1943 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1945 return DAG.getStore(Chain, dl, Arg, PtrOff,
1946 MachinePointerInfo::getStack(LocMemOffset),
1950 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1951 /// optimization is performed and it is required.
1953 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1954 SDValue &OutRetAddr, SDValue Chain,
1955 bool IsTailCall, bool Is64Bit,
1956 int FPDiff, DebugLoc dl) const {
1957 // Adjust the Return address stack slot.
1958 EVT VT = getPointerTy();
1959 OutRetAddr = getReturnAddressFrameIndex(DAG);
1961 // Load the "old" Return address.
1962 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1964 return SDValue(OutRetAddr.getNode(), 1);
1967 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1968 /// optimization is performed and it is required (FPDiff!=0).
1970 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1971 SDValue Chain, SDValue RetAddrFrIdx,
1972 bool Is64Bit, int FPDiff, DebugLoc dl) {
1973 // Store the return address to the appropriate stack slot.
1974 if (!FPDiff) return Chain;
1975 // Calculate the new stack slot for the return address.
1976 int SlotSize = Is64Bit ? 8 : 4;
1977 int NewReturnAddrFI =
1978 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1979 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1980 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1981 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1982 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1988 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1989 CallingConv::ID CallConv, bool isVarArg,
1991 const SmallVectorImpl<ISD::OutputArg> &Outs,
1992 const SmallVectorImpl<SDValue> &OutVals,
1993 const SmallVectorImpl<ISD::InputArg> &Ins,
1994 DebugLoc dl, SelectionDAG &DAG,
1995 SmallVectorImpl<SDValue> &InVals) const {
1996 MachineFunction &MF = DAG.getMachineFunction();
1997 bool Is64Bit = Subtarget->is64Bit();
1998 bool IsWin64 = Subtarget->isTargetWin64();
1999 bool IsStructRet = CallIsStructReturn(Outs);
2000 bool IsSibcall = false;
2003 // Check if it's really possible to do a tail call.
2004 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2005 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2006 Outs, OutVals, Ins, DAG);
2008 // Sibcalls are automatically detected tailcalls which do not require
2010 if (!GuaranteedTailCallOpt && isTailCall)
2017 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2018 "Var args not supported with calling convention fastcc or ghc");
2020 // Analyze operands of the call, assigning locations to each operand.
2021 SmallVector<CCValAssign, 16> ArgLocs;
2022 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2023 ArgLocs, *DAG.getContext());
2025 // Allocate shadow area for Win64
2027 CCInfo.AllocateStack(32, 8);
2030 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2032 // Get a count of how many bytes are to be pushed on the stack.
2033 unsigned NumBytes = CCInfo.getNextStackOffset();
2035 // This is a sibcall. The memory operands are available in caller's
2036 // own caller's stack.
2038 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2039 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2042 if (isTailCall && !IsSibcall) {
2043 // Lower arguments at fp - stackoffset + fpdiff.
2044 unsigned NumBytesCallerPushed =
2045 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2046 FPDiff = NumBytesCallerPushed - NumBytes;
2048 // Set the delta of movement of the returnaddr stackslot.
2049 // But only set if delta is greater than previous delta.
2050 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2051 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2055 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2057 SDValue RetAddrFrIdx;
2058 // Load return address for tail calls.
2059 if (isTailCall && FPDiff)
2060 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2061 Is64Bit, FPDiff, dl);
2063 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2064 SmallVector<SDValue, 8> MemOpChains;
2067 // Walk the register/memloc assignments, inserting copies/loads. In the case
2068 // of tail call optimization arguments are handle later.
2069 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2070 CCValAssign &VA = ArgLocs[i];
2071 EVT RegVT = VA.getLocVT();
2072 SDValue Arg = OutVals[i];
2073 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2074 bool isByVal = Flags.isByVal();
2076 // Promote the value if needed.
2077 switch (VA.getLocInfo()) {
2078 default: llvm_unreachable("Unknown loc info!");
2079 case CCValAssign::Full: break;
2080 case CCValAssign::SExt:
2081 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2083 case CCValAssign::ZExt:
2084 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2086 case CCValAssign::AExt:
2087 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2088 // Special case: passing MMX values in XMM registers.
2089 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2090 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2091 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2093 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2095 case CCValAssign::BCvt:
2096 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2098 case CCValAssign::Indirect: {
2099 // Store the argument.
2100 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2101 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2102 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2103 MachinePointerInfo::getFixedStack(FI),
2110 if (VA.isRegLoc()) {
2111 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2112 if (isVarArg && IsWin64) {
2113 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2114 // shadow reg if callee is a varargs function.
2115 unsigned ShadowReg = 0;
2116 switch (VA.getLocReg()) {
2117 case X86::XMM0: ShadowReg = X86::RCX; break;
2118 case X86::XMM1: ShadowReg = X86::RDX; break;
2119 case X86::XMM2: ShadowReg = X86::R8; break;
2120 case X86::XMM3: ShadowReg = X86::R9; break;
2123 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2125 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2126 assert(VA.isMemLoc());
2127 if (StackPtr.getNode() == 0)
2128 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2129 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2130 dl, DAG, VA, Flags));
2134 if (!MemOpChains.empty())
2135 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2136 &MemOpChains[0], MemOpChains.size());
2138 // Build a sequence of copy-to-reg nodes chained together with token chain
2139 // and flag operands which copy the outgoing args into registers.
2141 // Tail call byval lowering might overwrite argument registers so in case of
2142 // tail call optimization the copies to registers are lowered later.
2144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2145 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2146 RegsToPass[i].second, InFlag);
2147 InFlag = Chain.getValue(1);
2150 if (Subtarget->isPICStyleGOT()) {
2151 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2154 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2155 DAG.getNode(X86ISD::GlobalBaseReg,
2156 DebugLoc(), getPointerTy()),
2158 InFlag = Chain.getValue(1);
2160 // If we are tail calling and generating PIC/GOT style code load the
2161 // address of the callee into ECX. The value in ecx is used as target of
2162 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2163 // for tail calls on PIC/GOT architectures. Normally we would just put the
2164 // address of GOT into ebx and then call target@PLT. But for tail calls
2165 // ebx would be restored (since ebx is callee saved) before jumping to the
2168 // Note: The actual moving to ECX is done further down.
2169 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2170 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2171 !G->getGlobal()->hasProtectedVisibility())
2172 Callee = LowerGlobalAddress(Callee, DAG);
2173 else if (isa<ExternalSymbolSDNode>(Callee))
2174 Callee = LowerExternalSymbol(Callee, DAG);
2178 if (Is64Bit && isVarArg && !IsWin64) {
2179 // From AMD64 ABI document:
2180 // For calls that may call functions that use varargs or stdargs
2181 // (prototype-less calls or calls to functions containing ellipsis (...) in
2182 // the declaration) %al is used as hidden argument to specify the number
2183 // of SSE registers used. The contents of %al do not need to match exactly
2184 // the number of registers, but must be an ubound on the number of SSE
2185 // registers used and is in the range 0 - 8 inclusive.
2187 // Count the number of XMM registers allocated.
2188 static const unsigned XMMArgRegs[] = {
2189 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2190 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2192 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2193 assert((Subtarget->hasXMM() || !NumXMMRegs)
2194 && "SSE registers cannot be used when SSE is disabled");
2196 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2197 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2198 InFlag = Chain.getValue(1);
2202 // For tail calls lower the arguments to the 'real' stack slot.
2204 // Force all the incoming stack arguments to be loaded from the stack
2205 // before any new outgoing arguments are stored to the stack, because the
2206 // outgoing stack slots may alias the incoming argument stack slots, and
2207 // the alias isn't otherwise explicit. This is slightly more conservative
2208 // than necessary, because it means that each store effectively depends
2209 // on every argument instead of just those arguments it would clobber.
2210 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2212 SmallVector<SDValue, 8> MemOpChains2;
2215 // Do not flag preceding copytoreg stuff together with the following stuff.
2217 if (GuaranteedTailCallOpt) {
2218 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2219 CCValAssign &VA = ArgLocs[i];
2222 assert(VA.isMemLoc());
2223 SDValue Arg = OutVals[i];
2224 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2225 // Create frame index.
2226 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2227 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2228 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2229 FIN = DAG.getFrameIndex(FI, getPointerTy());
2231 if (Flags.isByVal()) {
2232 // Copy relative to framepointer.
2233 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2234 if (StackPtr.getNode() == 0)
2235 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2237 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2239 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2243 // Store relative to framepointer.
2244 MemOpChains2.push_back(
2245 DAG.getStore(ArgChain, dl, Arg, FIN,
2246 MachinePointerInfo::getFixedStack(FI),
2252 if (!MemOpChains2.empty())
2253 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2254 &MemOpChains2[0], MemOpChains2.size());
2256 // Copy arguments to their registers.
2257 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2258 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2259 RegsToPass[i].second, InFlag);
2260 InFlag = Chain.getValue(1);
2264 // Store the return address to the appropriate stack slot.
2265 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2269 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2270 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2271 // In the 64-bit large code model, we have to make all calls
2272 // through a register, since the call instruction's 32-bit
2273 // pc-relative offset may not be large enough to hold the whole
2275 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2276 // If the callee is a GlobalAddress node (quite common, every direct call
2277 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2280 // We should use extra load for direct calls to dllimported functions in
2282 const GlobalValue *GV = G->getGlobal();
2283 if (!GV->hasDLLImportLinkage()) {
2284 unsigned char OpFlags = 0;
2285 bool ExtraLoad = false;
2286 unsigned WrapperKind = ISD::DELETED_NODE;
2288 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2289 // external symbols most go through the PLT in PIC mode. If the symbol
2290 // has hidden or protected visibility, or if it is static or local, then
2291 // we don't need to use the PLT - we can directly call it.
2292 if (Subtarget->isTargetELF() &&
2293 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2294 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2295 OpFlags = X86II::MO_PLT;
2296 } else if (Subtarget->isPICStyleStubAny() &&
2297 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2298 (!Subtarget->getTargetTriple().isMacOSX() ||
2299 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2300 // PC-relative references to external symbols should go through $stub,
2301 // unless we're building with the leopard linker or later, which
2302 // automatically synthesizes these stubs.
2303 OpFlags = X86II::MO_DARWIN_STUB;
2304 } else if (Subtarget->isPICStyleRIPRel() &&
2305 isa<Function>(GV) &&
2306 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2307 // If the function is marked as non-lazy, generate an indirect call
2308 // which loads from the GOT directly. This avoids runtime overhead
2309 // at the cost of eager binding (and one extra byte of encoding).
2310 OpFlags = X86II::MO_GOTPCREL;
2311 WrapperKind = X86ISD::WrapperRIP;
2315 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2316 G->getOffset(), OpFlags);
2318 // Add a wrapper if needed.
2319 if (WrapperKind != ISD::DELETED_NODE)
2320 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2321 // Add extra indirection if needed.
2323 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2324 MachinePointerInfo::getGOT(),
2327 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2328 unsigned char OpFlags = 0;
2330 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2331 // external symbols should go through the PLT.
2332 if (Subtarget->isTargetELF() &&
2333 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2334 OpFlags = X86II::MO_PLT;
2335 } else if (Subtarget->isPICStyleStubAny() &&
2336 (!Subtarget->getTargetTriple().isMacOSX() ||
2337 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2338 // PC-relative references to external symbols should go through $stub,
2339 // unless we're building with the leopard linker or later, which
2340 // automatically synthesizes these stubs.
2341 OpFlags = X86II::MO_DARWIN_STUB;
2344 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2348 // Returns a chain & a flag for retval copy to use.
2349 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2350 SmallVector<SDValue, 8> Ops;
2352 if (!IsSibcall && isTailCall) {
2353 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2354 DAG.getIntPtrConstant(0, true), InFlag);
2355 InFlag = Chain.getValue(1);
2358 Ops.push_back(Chain);
2359 Ops.push_back(Callee);
2362 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2364 // Add argument registers to the end of the list so that they are known live
2366 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2367 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2368 RegsToPass[i].second.getValueType()));
2370 // Add an implicit use GOT pointer in EBX.
2371 if (!isTailCall && Subtarget->isPICStyleGOT())
2372 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2374 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2375 if (Is64Bit && isVarArg && !IsWin64)
2376 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2378 if (InFlag.getNode())
2379 Ops.push_back(InFlag);
2383 //// If this is the first return lowered for this function, add the regs
2384 //// to the liveout set for the function.
2385 // This isn't right, although it's probably harmless on x86; liveouts
2386 // should be computed from returns not tail calls. Consider a void
2387 // function making a tail call to a function returning int.
2388 return DAG.getNode(X86ISD::TC_RETURN, dl,
2389 NodeTys, &Ops[0], Ops.size());
2392 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2393 InFlag = Chain.getValue(1);
2395 // Create the CALLSEQ_END node.
2396 unsigned NumBytesForCalleeToPush;
2397 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2398 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2399 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2400 // If this is a call to a struct-return function, the callee
2401 // pops the hidden struct pointer, so we have to push it back.
2402 // This is common for Darwin/X86, Linux & Mingw32 targets.
2403 NumBytesForCalleeToPush = 4;
2405 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2407 // Returns a flag for retval copy to use.
2409 Chain = DAG.getCALLSEQ_END(Chain,
2410 DAG.getIntPtrConstant(NumBytes, true),
2411 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2414 InFlag = Chain.getValue(1);
2417 // Handle result values, copying them out of physregs into vregs that we
2419 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2420 Ins, dl, DAG, InVals);
2424 //===----------------------------------------------------------------------===//
2425 // Fast Calling Convention (tail call) implementation
2426 //===----------------------------------------------------------------------===//
2428 // Like std call, callee cleans arguments, convention except that ECX is
2429 // reserved for storing the tail called function address. Only 2 registers are
2430 // free for argument passing (inreg). Tail call optimization is performed
2432 // * tailcallopt is enabled
2433 // * caller/callee are fastcc
2434 // On X86_64 architecture with GOT-style position independent code only local
2435 // (within module) calls are supported at the moment.
2436 // To keep the stack aligned according to platform abi the function
2437 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2438 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2439 // If a tail called function callee has more arguments than the caller the
2440 // caller needs to make sure that there is room to move the RETADDR to. This is
2441 // achieved by reserving an area the size of the argument delta right after the
2442 // original REtADDR, but before the saved framepointer or the spilled registers
2443 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2455 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2456 /// for a 16 byte align requirement.
2458 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2459 SelectionDAG& DAG) const {
2460 MachineFunction &MF = DAG.getMachineFunction();
2461 const TargetMachine &TM = MF.getTarget();
2462 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2463 unsigned StackAlignment = TFI.getStackAlignment();
2464 uint64_t AlignMask = StackAlignment - 1;
2465 int64_t Offset = StackSize;
2466 uint64_t SlotSize = TD->getPointerSize();
2467 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2468 // Number smaller than 12 so just add the difference.
2469 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2471 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2472 Offset = ((~AlignMask) & Offset) + StackAlignment +
2473 (StackAlignment-SlotSize);
2478 /// MatchingStackOffset - Return true if the given stack call argument is
2479 /// already available in the same position (relatively) of the caller's
2480 /// incoming argument stack.
2482 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2483 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2484 const X86InstrInfo *TII) {
2485 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2487 if (Arg.getOpcode() == ISD::CopyFromReg) {
2488 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2489 if (!TargetRegisterInfo::isVirtualRegister(VR))
2491 MachineInstr *Def = MRI->getVRegDef(VR);
2494 if (!Flags.isByVal()) {
2495 if (!TII->isLoadFromStackSlot(Def, FI))
2498 unsigned Opcode = Def->getOpcode();
2499 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2500 Def->getOperand(1).isFI()) {
2501 FI = Def->getOperand(1).getIndex();
2502 Bytes = Flags.getByValSize();
2506 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2507 if (Flags.isByVal())
2508 // ByVal argument is passed in as a pointer but it's now being
2509 // dereferenced. e.g.
2510 // define @foo(%struct.X* %A) {
2511 // tail call @bar(%struct.X* byval %A)
2514 SDValue Ptr = Ld->getBasePtr();
2515 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2518 FI = FINode->getIndex();
2519 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2520 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2521 FI = FINode->getIndex();
2522 Bytes = Flags.getByValSize();
2526 assert(FI != INT_MAX);
2527 if (!MFI->isFixedObjectIndex(FI))
2529 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2532 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2533 /// for tail call optimization. Targets which want to do tail call
2534 /// optimization should implement this function.
2536 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2537 CallingConv::ID CalleeCC,
2539 bool isCalleeStructRet,
2540 bool isCallerStructRet,
2541 const SmallVectorImpl<ISD::OutputArg> &Outs,
2542 const SmallVectorImpl<SDValue> &OutVals,
2543 const SmallVectorImpl<ISD::InputArg> &Ins,
2544 SelectionDAG& DAG) const {
2545 if (!IsTailCallConvention(CalleeCC) &&
2546 CalleeCC != CallingConv::C)
2549 // If -tailcallopt is specified, make fastcc functions tail-callable.
2550 const MachineFunction &MF = DAG.getMachineFunction();
2551 const Function *CallerF = DAG.getMachineFunction().getFunction();
2552 CallingConv::ID CallerCC = CallerF->getCallingConv();
2553 bool CCMatch = CallerCC == CalleeCC;
2555 if (GuaranteedTailCallOpt) {
2556 if (IsTailCallConvention(CalleeCC) && CCMatch)
2561 // Look for obvious safe cases to perform tail call optimization that do not
2562 // require ABI changes. This is what gcc calls sibcall.
2564 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2565 // emit a special epilogue.
2566 if (RegInfo->needsStackRealignment(MF))
2569 // Also avoid sibcall optimization if either caller or callee uses struct
2570 // return semantics.
2571 if (isCalleeStructRet || isCallerStructRet)
2574 // An stdcall caller is expected to clean up its arguments; the callee
2575 // isn't going to do that.
2576 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2579 // Do not sibcall optimize vararg calls unless all arguments are passed via
2581 if (isVarArg && !Outs.empty()) {
2583 // Optimizing for varargs on Win64 is unlikely to be safe without
2584 // additional testing.
2585 if (Subtarget->isTargetWin64())
2588 SmallVector<CCValAssign, 16> ArgLocs;
2589 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2590 getTargetMachine(), ArgLocs, *DAG.getContext());
2592 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2593 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2594 if (!ArgLocs[i].isRegLoc())
2598 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2599 // Therefore if it's not used by the call it is not safe to optimize this into
2601 bool Unused = false;
2602 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2609 SmallVector<CCValAssign, 16> RVLocs;
2610 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2611 getTargetMachine(), RVLocs, *DAG.getContext());
2612 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2613 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2614 CCValAssign &VA = RVLocs[i];
2615 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2620 // If the calling conventions do not match, then we'd better make sure the
2621 // results are returned in the same way as what the caller expects.
2623 SmallVector<CCValAssign, 16> RVLocs1;
2624 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2625 getTargetMachine(), RVLocs1, *DAG.getContext());
2626 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2628 SmallVector<CCValAssign, 16> RVLocs2;
2629 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2630 getTargetMachine(), RVLocs2, *DAG.getContext());
2631 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2633 if (RVLocs1.size() != RVLocs2.size())
2635 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2636 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2638 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2640 if (RVLocs1[i].isRegLoc()) {
2641 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2644 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2650 // If the callee takes no arguments then go on to check the results of the
2652 if (!Outs.empty()) {
2653 // Check if stack adjustment is needed. For now, do not do this if any
2654 // argument is passed on the stack.
2655 SmallVector<CCValAssign, 16> ArgLocs;
2656 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2657 getTargetMachine(), ArgLocs, *DAG.getContext());
2659 // Allocate shadow area for Win64
2660 if (Subtarget->isTargetWin64()) {
2661 CCInfo.AllocateStack(32, 8);
2664 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2665 if (CCInfo.getNextStackOffset()) {
2666 MachineFunction &MF = DAG.getMachineFunction();
2667 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2670 // Check if the arguments are already laid out in the right way as
2671 // the caller's fixed stack objects.
2672 MachineFrameInfo *MFI = MF.getFrameInfo();
2673 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2674 const X86InstrInfo *TII =
2675 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2676 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2677 CCValAssign &VA = ArgLocs[i];
2678 SDValue Arg = OutVals[i];
2679 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2680 if (VA.getLocInfo() == CCValAssign::Indirect)
2682 if (!VA.isRegLoc()) {
2683 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2690 // If the tailcall address may be in a register, then make sure it's
2691 // possible to register allocate for it. In 32-bit, the call address can
2692 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2693 // callee-saved registers are restored. These happen to be the same
2694 // registers used to pass 'inreg' arguments so watch out for those.
2695 if (!Subtarget->is64Bit() &&
2696 !isa<GlobalAddressSDNode>(Callee) &&
2697 !isa<ExternalSymbolSDNode>(Callee)) {
2698 unsigned NumInRegs = 0;
2699 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2700 CCValAssign &VA = ArgLocs[i];
2703 unsigned Reg = VA.getLocReg();
2706 case X86::EAX: case X86::EDX: case X86::ECX:
2707 if (++NumInRegs == 3)
2719 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2720 return X86::createFastISel(funcInfo);
2724 //===----------------------------------------------------------------------===//
2725 // Other Lowering Hooks
2726 //===----------------------------------------------------------------------===//
2728 static bool MayFoldLoad(SDValue Op) {
2729 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2732 static bool MayFoldIntoStore(SDValue Op) {
2733 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2736 static bool isTargetShuffle(unsigned Opcode) {
2738 default: return false;
2739 case X86ISD::PSHUFD:
2740 case X86ISD::PSHUFHW:
2741 case X86ISD::PSHUFLW:
2742 case X86ISD::SHUFPD:
2743 case X86ISD::PALIGN:
2744 case X86ISD::SHUFPS:
2745 case X86ISD::MOVLHPS:
2746 case X86ISD::MOVLHPD:
2747 case X86ISD::MOVHLPS:
2748 case X86ISD::MOVLPS:
2749 case X86ISD::MOVLPD:
2750 case X86ISD::MOVSHDUP:
2751 case X86ISD::MOVSLDUP:
2752 case X86ISD::MOVDDUP:
2755 case X86ISD::UNPCKLPS:
2756 case X86ISD::UNPCKLPD:
2757 case X86ISD::VUNPCKLPSY:
2758 case X86ISD::VUNPCKLPDY:
2759 case X86ISD::PUNPCKLWD:
2760 case X86ISD::PUNPCKLBW:
2761 case X86ISD::PUNPCKLDQ:
2762 case X86ISD::PUNPCKLQDQ:
2763 case X86ISD::UNPCKHPS:
2764 case X86ISD::UNPCKHPD:
2765 case X86ISD::VUNPCKHPSY:
2766 case X86ISD::VUNPCKHPDY:
2767 case X86ISD::PUNPCKHWD:
2768 case X86ISD::PUNPCKHBW:
2769 case X86ISD::PUNPCKHDQ:
2770 case X86ISD::PUNPCKHQDQ:
2771 case X86ISD::VPERMILPS:
2772 case X86ISD::VPERMILPSY:
2773 case X86ISD::VPERMILPD:
2774 case X86ISD::VPERMILPDY:
2775 case X86ISD::VPERM2F128:
2781 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2782 SDValue V1, SelectionDAG &DAG) {
2784 default: llvm_unreachable("Unknown x86 shuffle node");
2785 case X86ISD::MOVSHDUP:
2786 case X86ISD::MOVSLDUP:
2787 case X86ISD::MOVDDUP:
2788 return DAG.getNode(Opc, dl, VT, V1);
2794 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2795 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2797 default: llvm_unreachable("Unknown x86 shuffle node");
2798 case X86ISD::PSHUFD:
2799 case X86ISD::PSHUFHW:
2800 case X86ISD::PSHUFLW:
2801 case X86ISD::VPERMILPS:
2802 case X86ISD::VPERMILPSY:
2803 case X86ISD::VPERMILPD:
2804 case X86ISD::VPERMILPDY:
2805 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2811 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2812 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2814 default: llvm_unreachable("Unknown x86 shuffle node");
2815 case X86ISD::PALIGN:
2816 case X86ISD::SHUFPD:
2817 case X86ISD::SHUFPS:
2818 case X86ISD::VPERM2F128:
2819 return DAG.getNode(Opc, dl, VT, V1, V2,
2820 DAG.getConstant(TargetMask, MVT::i8));
2825 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2826 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2828 default: llvm_unreachable("Unknown x86 shuffle node");
2829 case X86ISD::MOVLHPS:
2830 case X86ISD::MOVLHPD:
2831 case X86ISD::MOVHLPS:
2832 case X86ISD::MOVLPS:
2833 case X86ISD::MOVLPD:
2836 case X86ISD::UNPCKLPS:
2837 case X86ISD::UNPCKLPD:
2838 case X86ISD::VUNPCKLPSY:
2839 case X86ISD::VUNPCKLPDY:
2840 case X86ISD::PUNPCKLWD:
2841 case X86ISD::PUNPCKLBW:
2842 case X86ISD::PUNPCKLDQ:
2843 case X86ISD::PUNPCKLQDQ:
2844 case X86ISD::UNPCKHPS:
2845 case X86ISD::UNPCKHPD:
2846 case X86ISD::VUNPCKHPSY:
2847 case X86ISD::VUNPCKHPDY:
2848 case X86ISD::PUNPCKHWD:
2849 case X86ISD::PUNPCKHBW:
2850 case X86ISD::PUNPCKHDQ:
2851 case X86ISD::PUNPCKHQDQ:
2852 return DAG.getNode(Opc, dl, VT, V1, V2);
2857 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2858 MachineFunction &MF = DAG.getMachineFunction();
2859 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2860 int ReturnAddrIndex = FuncInfo->getRAIndex();
2862 if (ReturnAddrIndex == 0) {
2863 // Set up a frame object for the return address.
2864 uint64_t SlotSize = TD->getPointerSize();
2865 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2867 FuncInfo->setRAIndex(ReturnAddrIndex);
2870 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2874 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2875 bool hasSymbolicDisplacement) {
2876 // Offset should fit into 32 bit immediate field.
2877 if (!isInt<32>(Offset))
2880 // If we don't have a symbolic displacement - we don't have any extra
2882 if (!hasSymbolicDisplacement)
2885 // FIXME: Some tweaks might be needed for medium code model.
2886 if (M != CodeModel::Small && M != CodeModel::Kernel)
2889 // For small code model we assume that latest object is 16MB before end of 31
2890 // bits boundary. We may also accept pretty large negative constants knowing
2891 // that all objects are in the positive half of address space.
2892 if (M == CodeModel::Small && Offset < 16*1024*1024)
2895 // For kernel code model we know that all object resist in the negative half
2896 // of 32bits address space. We may not accept negative offsets, since they may
2897 // be just off and we may accept pretty large positive ones.
2898 if (M == CodeModel::Kernel && Offset > 0)
2904 /// isCalleePop - Determines whether the callee is required to pop its
2905 /// own arguments. Callee pop is necessary to support tail calls.
2906 bool X86::isCalleePop(CallingConv::ID CallingConv,
2907 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2911 switch (CallingConv) {
2914 case CallingConv::X86_StdCall:
2916 case CallingConv::X86_FastCall:
2918 case CallingConv::X86_ThisCall:
2920 case CallingConv::Fast:
2922 case CallingConv::GHC:
2927 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2928 /// specific condition code, returning the condition code and the LHS/RHS of the
2929 /// comparison to make.
2930 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2931 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2933 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2934 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2935 // X > -1 -> X == 0, jump !sign.
2936 RHS = DAG.getConstant(0, RHS.getValueType());
2937 return X86::COND_NS;
2938 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2939 // X < 0 -> X == 0, jump on sign.
2941 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2943 RHS = DAG.getConstant(0, RHS.getValueType());
2944 return X86::COND_LE;
2948 switch (SetCCOpcode) {
2949 default: llvm_unreachable("Invalid integer condition!");
2950 case ISD::SETEQ: return X86::COND_E;
2951 case ISD::SETGT: return X86::COND_G;
2952 case ISD::SETGE: return X86::COND_GE;
2953 case ISD::SETLT: return X86::COND_L;
2954 case ISD::SETLE: return X86::COND_LE;
2955 case ISD::SETNE: return X86::COND_NE;
2956 case ISD::SETULT: return X86::COND_B;
2957 case ISD::SETUGT: return X86::COND_A;
2958 case ISD::SETULE: return X86::COND_BE;
2959 case ISD::SETUGE: return X86::COND_AE;
2963 // First determine if it is required or is profitable to flip the operands.
2965 // If LHS is a foldable load, but RHS is not, flip the condition.
2966 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2967 !ISD::isNON_EXTLoad(RHS.getNode())) {
2968 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2969 std::swap(LHS, RHS);
2972 switch (SetCCOpcode) {
2978 std::swap(LHS, RHS);
2982 // On a floating point condition, the flags are set as follows:
2984 // 0 | 0 | 0 | X > Y
2985 // 0 | 0 | 1 | X < Y
2986 // 1 | 0 | 0 | X == Y
2987 // 1 | 1 | 1 | unordered
2988 switch (SetCCOpcode) {
2989 default: llvm_unreachable("Condcode should be pre-legalized away");
2991 case ISD::SETEQ: return X86::COND_E;
2992 case ISD::SETOLT: // flipped
2994 case ISD::SETGT: return X86::COND_A;
2995 case ISD::SETOLE: // flipped
2997 case ISD::SETGE: return X86::COND_AE;
2998 case ISD::SETUGT: // flipped
3000 case ISD::SETLT: return X86::COND_B;
3001 case ISD::SETUGE: // flipped
3003 case ISD::SETLE: return X86::COND_BE;
3005 case ISD::SETNE: return X86::COND_NE;
3006 case ISD::SETUO: return X86::COND_P;
3007 case ISD::SETO: return X86::COND_NP;
3009 case ISD::SETUNE: return X86::COND_INVALID;
3013 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3014 /// code. Current x86 isa includes the following FP cmov instructions:
3015 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3016 static bool hasFPCMov(unsigned X86CC) {
3032 /// isFPImmLegal - Returns true if the target can instruction select the
3033 /// specified FP immediate natively. If false, the legalizer will
3034 /// materialize the FP immediate as a load from a constant pool.
3035 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3036 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3037 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3043 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3044 /// the specified range (L, H].
3045 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3046 return (Val < 0) || (Val >= Low && Val < Hi);
3049 /// isUndefOrInRange - Return true if every element in Mask, begining
3050 /// from position Pos and ending in Pos+Size, falls within the specified
3051 /// range (L, L+Pos]. or is undef.
3052 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3053 int Pos, int Size, int Low, int Hi) {
3054 for (int i = Pos, e = Pos+Size; i != e; ++i)
3055 if (!isUndefOrInRange(Mask[i], Low, Hi))
3060 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3061 /// specified value.
3062 static bool isUndefOrEqual(int Val, int CmpVal) {
3063 if (Val < 0 || Val == CmpVal)
3068 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3069 /// from position Pos and ending in Pos+Size, falls within the specified
3070 /// sequential range (L, L+Pos]. or is undef.
3071 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3072 int Pos, int Size, int Low) {
3073 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3074 if (!isUndefOrEqual(Mask[i], Low))
3079 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3080 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3081 /// the second operand.
3082 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3083 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3084 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3085 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3086 return (Mask[0] < 2 && Mask[1] < 2);
3090 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3091 SmallVector<int, 8> M;
3093 return ::isPSHUFDMask(M, N->getValueType(0));
3096 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3097 /// is suitable for input to PSHUFHW.
3098 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3099 if (VT != MVT::v8i16)
3102 // Lower quadword copied in order or undef.
3103 for (int i = 0; i != 4; ++i)
3104 if (Mask[i] >= 0 && Mask[i] != i)
3107 // Upper quadword shuffled.
3108 for (int i = 4; i != 8; ++i)
3109 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3115 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3116 SmallVector<int, 8> M;
3118 return ::isPSHUFHWMask(M, N->getValueType(0));
3121 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3122 /// is suitable for input to PSHUFLW.
3123 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3124 if (VT != MVT::v8i16)
3127 // Upper quadword copied in order.
3128 for (int i = 4; i != 8; ++i)
3129 if (Mask[i] >= 0 && Mask[i] != i)
3132 // Lower quadword shuffled.
3133 for (int i = 0; i != 4; ++i)
3140 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3141 SmallVector<int, 8> M;
3143 return ::isPSHUFLWMask(M, N->getValueType(0));
3146 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3147 /// is suitable for input to PALIGNR.
3148 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3150 int i, e = VT.getVectorNumElements();
3151 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3154 // Do not handle v2i64 / v2f64 shuffles with palignr.
3155 if (e < 4 || !hasSSSE3)
3158 for (i = 0; i != e; ++i)
3162 // All undef, not a palignr.
3166 // Make sure we're shifting in the right direction.
3170 int s = Mask[i] - i;
3172 // Check the rest of the elements to see if they are consecutive.
3173 for (++i; i != e; ++i) {
3175 if (m >= 0 && m != s+i)
3181 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3182 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
3183 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3184 int NumElems = VT.getVectorNumElements();
3185 if (NumElems != 2 && NumElems != 4)
3188 int Half = NumElems / 2;
3189 for (int i = 0; i < Half; ++i)
3190 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3192 for (int i = Half; i < NumElems; ++i)
3193 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3199 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3200 SmallVector<int, 8> M;
3202 return ::isSHUFPMask(M, N->getValueType(0));
3205 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3206 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3207 /// half elements to come from vector 1 (which would equal the dest.) and
3208 /// the upper half to come from vector 2.
3209 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3210 int NumElems = VT.getVectorNumElements();
3212 if (NumElems != 2 && NumElems != 4)
3215 int Half = NumElems / 2;
3216 for (int i = 0; i < Half; ++i)
3217 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3219 for (int i = Half; i < NumElems; ++i)
3220 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3225 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3226 SmallVector<int, 8> M;
3228 return isCommutedSHUFPMask(M, N->getValueType(0));
3231 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3232 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3233 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3234 EVT VT = N->getValueType(0);
3235 unsigned NumElems = VT.getVectorNumElements();
3237 if (VT.getSizeInBits() != 128)
3243 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3244 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3245 isUndefOrEqual(N->getMaskElt(1), 7) &&
3246 isUndefOrEqual(N->getMaskElt(2), 2) &&
3247 isUndefOrEqual(N->getMaskElt(3), 3);
3250 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3251 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3253 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3254 EVT VT = N->getValueType(0);
3255 unsigned NumElems = VT.getVectorNumElements();
3257 if (VT.getSizeInBits() != 128)
3263 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3264 isUndefOrEqual(N->getMaskElt(1), 3) &&
3265 isUndefOrEqual(N->getMaskElt(2), 2) &&
3266 isUndefOrEqual(N->getMaskElt(3), 3);
3269 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3270 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3271 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3272 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3274 if (NumElems != 2 && NumElems != 4)
3277 for (unsigned i = 0; i < NumElems/2; ++i)
3278 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3281 for (unsigned i = NumElems/2; i < NumElems; ++i)
3282 if (!isUndefOrEqual(N->getMaskElt(i), i))
3288 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3289 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3290 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3291 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3293 if ((NumElems != 2 && NumElems != 4)
3294 || N->getValueType(0).getSizeInBits() > 128)
3297 for (unsigned i = 0; i < NumElems/2; ++i)
3298 if (!isUndefOrEqual(N->getMaskElt(i), i))
3301 for (unsigned i = 0; i < NumElems/2; ++i)
3302 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3308 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3309 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3310 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3311 bool V2IsSplat = false) {
3312 int NumElts = VT.getVectorNumElements();
3314 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3315 "Unsupported vector type for unpckh");
3317 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3320 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3321 // independently on 128-bit lanes.
3322 unsigned NumLanes = VT.getSizeInBits()/128;
3323 unsigned NumLaneElts = NumElts/NumLanes;
3326 unsigned End = NumLaneElts;
3327 for (unsigned s = 0; s < NumLanes; ++s) {
3328 for (unsigned i = Start, j = s * NumLaneElts;
3332 int BitI1 = Mask[i+1];
3333 if (!isUndefOrEqual(BitI, j))
3336 if (!isUndefOrEqual(BitI1, NumElts))
3339 if (!isUndefOrEqual(BitI1, j + NumElts))
3343 // Process the next 128 bits.
3344 Start += NumLaneElts;
3351 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3352 SmallVector<int, 8> M;
3354 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3357 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3358 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3359 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3360 bool V2IsSplat = false) {
3361 int NumElts = VT.getVectorNumElements();
3363 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3364 "Unsupported vector type for unpckh");
3366 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3369 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3370 // independently on 128-bit lanes.
3371 unsigned NumLanes = VT.getSizeInBits()/128;
3372 unsigned NumLaneElts = NumElts/NumLanes;
3375 unsigned End = NumLaneElts;
3376 for (unsigned l = 0; l != NumLanes; ++l) {
3377 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3378 i != End; i += 2, ++j) {
3380 int BitI1 = Mask[i+1];
3381 if (!isUndefOrEqual(BitI, j))
3384 if (isUndefOrEqual(BitI1, NumElts))
3387 if (!isUndefOrEqual(BitI1, j+NumElts))
3391 // Process the next 128 bits.
3392 Start += NumLaneElts;
3398 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3399 SmallVector<int, 8> M;
3401 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3404 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3405 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3407 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3408 int NumElems = VT.getVectorNumElements();
3409 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3412 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3413 // independently on 128-bit lanes.
3414 unsigned NumLanes = VT.getSizeInBits() / 128;
3415 unsigned NumLaneElts = NumElems / NumLanes;
3417 for (unsigned s = 0; s < NumLanes; ++s) {
3418 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3419 i != NumLaneElts * (s + 1);
3422 int BitI1 = Mask[i+1];
3424 if (!isUndefOrEqual(BitI, j))
3426 if (!isUndefOrEqual(BitI1, j))
3434 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3435 SmallVector<int, 8> M;
3437 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3440 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3441 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3443 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3444 int NumElems = VT.getVectorNumElements();
3445 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3448 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3450 int BitI1 = Mask[i+1];
3451 if (!isUndefOrEqual(BitI, j))
3453 if (!isUndefOrEqual(BitI1, j))
3459 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3460 SmallVector<int, 8> M;
3462 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3465 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3466 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3467 /// MOVSD, and MOVD, i.e. setting the lowest element.
3468 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3469 if (VT.getVectorElementType().getSizeInBits() < 32)
3472 int NumElts = VT.getVectorNumElements();
3474 if (!isUndefOrEqual(Mask[0], NumElts))
3477 for (int i = 1; i < NumElts; ++i)
3478 if (!isUndefOrEqual(Mask[i], i))
3484 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3485 SmallVector<int, 8> M;
3487 return ::isMOVLMask(M, N->getValueType(0));
3490 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3491 /// as permutations between 128-bit chunks or halves. As an example: this
3493 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3494 /// The first half comes from the second half of V1 and the second half from the
3495 /// the second half of V2.
3496 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3497 const X86Subtarget *Subtarget) {
3498 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3501 // The shuffle result is divided into half A and half B. In total the two
3502 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3503 // B must come from C, D, E or F.
3504 int HalfSize = VT.getVectorNumElements()/2;
3505 bool MatchA = false, MatchB = false;
3507 // Check if A comes from one of C, D, E, F.
3508 for (int Half = 0; Half < 4; ++Half) {
3509 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3515 // Check if B comes from one of C, D, E, F.
3516 for (int Half = 0; Half < 4; ++Half) {
3517 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3523 return MatchA && MatchB;
3526 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3527 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3528 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3529 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3530 EVT VT = SVOp->getValueType(0);
3532 int HalfSize = VT.getVectorNumElements()/2;
3534 int FstHalf = 0, SndHalf = 0;
3535 for (int i = 0; i < HalfSize; ++i) {
3536 if (SVOp->getMaskElt(i) > 0) {
3537 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3541 for (int i = HalfSize; i < HalfSize*2; ++i) {
3542 if (SVOp->getMaskElt(i) > 0) {
3543 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3548 return (FstHalf | (SndHalf << 4));
3551 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3552 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3553 /// Note that VPERMIL mask matching is different depending whether theunderlying
3554 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3555 /// to the same elements of the low, but to the higher half of the source.
3556 /// In VPERMILPD the two lanes could be shuffled independently of each other
3557 /// with the same restriction that lanes can't be crossed.
3558 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3559 const X86Subtarget *Subtarget) {
3560 int NumElts = VT.getVectorNumElements();
3561 int NumLanes = VT.getSizeInBits()/128;
3563 if (!Subtarget->hasAVX())
3566 // Match any permutation of 128-bit vector with 64-bit types
3567 if (NumLanes == 1 && NumElts != 2)
3570 // Only match 256-bit with 32 types
3571 if (VT.getSizeInBits() == 256 && NumElts != 4)
3574 // The mask on the high lane is independent of the low. Both can match
3575 // any element in inside its own lane, but can't cross.
3576 int LaneSize = NumElts/NumLanes;
3577 for (int l = 0; l < NumLanes; ++l)
3578 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3579 int LaneStart = l*LaneSize;
3580 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3587 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3588 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3589 /// Note that VPERMIL mask matching is different depending whether theunderlying
3590 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3591 /// to the same elements of the low, but to the higher half of the source.
3592 /// In VPERMILPD the two lanes could be shuffled independently of each other
3593 /// with the same restriction that lanes can't be crossed.
3594 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3595 const X86Subtarget *Subtarget) {
3596 unsigned NumElts = VT.getVectorNumElements();
3597 unsigned NumLanes = VT.getSizeInBits()/128;
3599 if (!Subtarget->hasAVX())
3602 // Match any permutation of 128-bit vector with 32-bit types
3603 if (NumLanes == 1 && NumElts != 4)
3606 // Only match 256-bit with 32 types
3607 if (VT.getSizeInBits() == 256 && NumElts != 8)
3610 // The mask on the high lane should be the same as the low. Actually,
3611 // they can differ if any of the corresponding index in a lane is undef
3612 // and the other stays in range.
3613 int LaneSize = NumElts/NumLanes;
3614 for (int i = 0; i < LaneSize; ++i) {
3615 int HighElt = i+LaneSize;
3616 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3617 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3619 if (!HighValid || !LowValid)
3621 if (Mask[i] < 0 || Mask[HighElt] < 0)
3623 if (Mask[HighElt]-Mask[i] != LaneSize)
3630 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3631 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3632 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3633 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3634 EVT VT = SVOp->getValueType(0);
3636 int NumElts = VT.getVectorNumElements();
3637 int NumLanes = VT.getSizeInBits()/128;
3638 int LaneSize = NumElts/NumLanes;
3640 // Although the mask is equal for both lanes do it twice to get the cases
3641 // where a mask will match because the same mask element is undef on the
3642 // first half but valid on the second. This would get pathological cases
3643 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3645 for (int l = 0; l < NumLanes; ++l) {
3646 for (int i = 0; i < LaneSize; ++i) {
3647 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3650 if (MaskElt >= LaneSize)
3651 MaskElt -= LaneSize;
3652 Mask |= MaskElt << (i*2);
3659 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3660 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3661 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3662 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3663 EVT VT = SVOp->getValueType(0);
3665 int NumElts = VT.getVectorNumElements();
3666 int NumLanes = VT.getSizeInBits()/128;
3669 int LaneSize = NumElts/NumLanes;
3670 for (int l = 0; l < NumLanes; ++l)
3671 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3672 int MaskElt = SVOp->getMaskElt(i);
3675 Mask |= (MaskElt-l*LaneSize) << i;
3681 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3682 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3683 /// element of vector 2 and the other elements to come from vector 1 in order.
3684 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3685 bool V2IsSplat = false, bool V2IsUndef = false) {
3686 int NumOps = VT.getVectorNumElements();
3687 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3690 if (!isUndefOrEqual(Mask[0], 0))
3693 for (int i = 1; i < NumOps; ++i)
3694 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3695 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3696 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3702 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3703 bool V2IsUndef = false) {
3704 SmallVector<int, 8> M;
3706 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3709 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3710 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3711 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3712 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3713 const X86Subtarget *Subtarget) {
3714 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3717 // The second vector must be undef
3718 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3721 EVT VT = N->getValueType(0);
3722 unsigned NumElems = VT.getVectorNumElements();
3724 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3725 (VT.getSizeInBits() == 256 && NumElems != 8))
3728 // "i+1" is the value the indexed mask element must have
3729 for (unsigned i = 0; i < NumElems; i += 2)
3730 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3731 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3737 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3738 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3739 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3740 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3741 const X86Subtarget *Subtarget) {
3742 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3745 // The second vector must be undef
3746 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3749 EVT VT = N->getValueType(0);
3750 unsigned NumElems = VT.getVectorNumElements();
3752 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3753 (VT.getSizeInBits() == 256 && NumElems != 8))
3756 // "i" is the value the indexed mask element must have
3757 for (unsigned i = 0; i < NumElems; i += 2)
3758 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3759 !isUndefOrEqual(N->getMaskElt(i+1), i))
3765 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3766 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3767 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3768 int e = N->getValueType(0).getVectorNumElements() / 2;
3770 for (int i = 0; i < e; ++i)
3771 if (!isUndefOrEqual(N->getMaskElt(i), i))
3773 for (int i = 0; i < e; ++i)
3774 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3779 /// isVEXTRACTF128Index - Return true if the specified
3780 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3781 /// suitable for input to VEXTRACTF128.
3782 bool X86::isVEXTRACTF128Index(SDNode *N) {
3783 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3786 // The index should be aligned on a 128-bit boundary.
3788 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3790 unsigned VL = N->getValueType(0).getVectorNumElements();
3791 unsigned VBits = N->getValueType(0).getSizeInBits();
3792 unsigned ElSize = VBits / VL;
3793 bool Result = (Index * ElSize) % 128 == 0;
3798 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3799 /// operand specifies a subvector insert that is suitable for input to
3801 bool X86::isVINSERTF128Index(SDNode *N) {
3802 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3805 // The index should be aligned on a 128-bit boundary.
3807 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3809 unsigned VL = N->getValueType(0).getVectorNumElements();
3810 unsigned VBits = N->getValueType(0).getSizeInBits();
3811 unsigned ElSize = VBits / VL;
3812 bool Result = (Index * ElSize) % 128 == 0;
3817 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3818 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3819 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3820 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3821 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3823 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3825 for (int i = 0; i < NumOperands; ++i) {
3826 int Val = SVOp->getMaskElt(NumOperands-i-1);
3827 if (Val < 0) Val = 0;
3828 if (Val >= NumOperands) Val -= NumOperands;
3830 if (i != NumOperands - 1)
3836 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3837 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3838 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3839 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3841 // 8 nodes, but we only care about the last 4.
3842 for (unsigned i = 7; i >= 4; --i) {
3843 int Val = SVOp->getMaskElt(i);
3852 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3853 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3854 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3855 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3857 // 8 nodes, but we only care about the first 4.
3858 for (int i = 3; i >= 0; --i) {
3859 int Val = SVOp->getMaskElt(i);
3868 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3869 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3870 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3871 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3872 EVT VVT = N->getValueType(0);
3873 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3877 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3878 Val = SVOp->getMaskElt(i);
3882 assert(Val - i > 0 && "PALIGNR imm should be positive");
3883 return (Val - i) * EltSize;
3886 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3887 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3889 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3890 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3891 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3894 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3896 EVT VecVT = N->getOperand(0).getValueType();
3897 EVT ElVT = VecVT.getVectorElementType();
3899 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3900 return Index / NumElemsPerChunk;
3903 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3904 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3906 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3907 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3908 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3911 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3913 EVT VecVT = N->getValueType(0);
3914 EVT ElVT = VecVT.getVectorElementType();
3916 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3917 return Index / NumElemsPerChunk;
3920 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3922 bool X86::isZeroNode(SDValue Elt) {
3923 return ((isa<ConstantSDNode>(Elt) &&
3924 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3925 (isa<ConstantFPSDNode>(Elt) &&
3926 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3929 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3930 /// their permute mask.
3931 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3932 SelectionDAG &DAG) {
3933 EVT VT = SVOp->getValueType(0);
3934 unsigned NumElems = VT.getVectorNumElements();
3935 SmallVector<int, 8> MaskVec;
3937 for (unsigned i = 0; i != NumElems; ++i) {
3938 int idx = SVOp->getMaskElt(i);
3940 MaskVec.push_back(idx);
3941 else if (idx < (int)NumElems)
3942 MaskVec.push_back(idx + NumElems);
3944 MaskVec.push_back(idx - NumElems);
3946 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3947 SVOp->getOperand(0), &MaskVec[0]);
3950 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3951 /// the two vector operands have swapped position.
3952 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3953 unsigned NumElems = VT.getVectorNumElements();
3954 for (unsigned i = 0; i != NumElems; ++i) {
3958 else if (idx < (int)NumElems)
3959 Mask[i] = idx + NumElems;
3961 Mask[i] = idx - NumElems;
3965 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3966 /// match movhlps. The lower half elements should come from upper half of
3967 /// V1 (and in order), and the upper half elements should come from the upper
3968 /// half of V2 (and in order).
3969 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3970 EVT VT = Op->getValueType(0);
3971 if (VT.getSizeInBits() != 128)
3973 if (VT.getVectorNumElements() != 4)
3975 for (unsigned i = 0, e = 2; i != e; ++i)
3976 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3978 for (unsigned i = 2; i != 4; ++i)
3979 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3984 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3985 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3987 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3988 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3990 N = N->getOperand(0).getNode();
3991 if (!ISD::isNON_EXTLoad(N))
3994 *LD = cast<LoadSDNode>(N);
3998 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3999 /// match movlp{s|d}. The lower half elements should come from lower half of
4000 /// V1 (and in order), and the upper half elements should come from the upper
4001 /// half of V2 (and in order). And since V1 will become the source of the
4002 /// MOVLP, it must be either a vector load or a scalar load to vector.
4003 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4004 ShuffleVectorSDNode *Op) {
4005 EVT VT = Op->getValueType(0);
4006 if (VT.getSizeInBits() != 128)
4009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4011 // Is V2 is a vector load, don't do this transformation. We will try to use
4012 // load folding shufps op.
4013 if (ISD::isNON_EXTLoad(V2))
4016 unsigned NumElems = VT.getVectorNumElements();
4018 if (NumElems != 2 && NumElems != 4)
4020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4021 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4023 for (unsigned i = NumElems/2; i != NumElems; ++i)
4024 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4029 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4031 static bool isSplatVector(SDNode *N) {
4032 if (N->getOpcode() != ISD::BUILD_VECTOR)
4035 SDValue SplatValue = N->getOperand(0);
4036 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4037 if (N->getOperand(i) != SplatValue)
4042 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4043 /// to an zero vector.
4044 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4045 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4046 SDValue V1 = N->getOperand(0);
4047 SDValue V2 = N->getOperand(1);
4048 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4049 for (unsigned i = 0; i != NumElems; ++i) {
4050 int Idx = N->getMaskElt(i);
4051 if (Idx >= (int)NumElems) {
4052 unsigned Opc = V2.getOpcode();
4053 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4055 if (Opc != ISD::BUILD_VECTOR ||
4056 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4058 } else if (Idx >= 0) {
4059 unsigned Opc = V1.getOpcode();
4060 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4062 if (Opc != ISD::BUILD_VECTOR ||
4063 !X86::isZeroNode(V1.getOperand(Idx)))
4070 /// getZeroVector - Returns a vector of specified type with all zero elements.
4072 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
4074 assert(VT.isVector() && "Expected a vector type");
4076 // Always build SSE zero vectors as <4 x i32> bitcasted
4077 // to their dest type. This ensures they get CSE'd.
4079 if (VT.getSizeInBits() == 128) { // SSE
4080 if (HasSSE2) { // SSE2
4081 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4082 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4084 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4087 } else if (VT.getSizeInBits() == 256) { // AVX
4088 // 256-bit logic and arithmetic instructions in AVX are
4089 // all floating-point, no support for integer ops. Default
4090 // to emitting fp zeroed vectors then.
4091 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4092 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4093 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4095 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4098 /// getOnesVector - Returns a vector of specified type with all bits set.
4099 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4100 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4101 /// original type, ensuring they get CSE'd.
4102 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4103 assert(VT.isVector() && "Expected a vector type");
4104 assert((VT.is128BitVector() || VT.is256BitVector())
4105 && "Expected a 128-bit or 256-bit vector type");
4107 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4108 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4109 Cst, Cst, Cst, Cst);
4111 if (VT.is256BitVector()) {
4112 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4113 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4114 Vec = Insert128BitVector(InsV, Vec,
4115 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4118 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4121 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4122 /// that point to V2 points to its first element.
4123 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4124 EVT VT = SVOp->getValueType(0);
4125 unsigned NumElems = VT.getVectorNumElements();
4127 bool Changed = false;
4128 SmallVector<int, 8> MaskVec;
4129 SVOp->getMask(MaskVec);
4131 for (unsigned i = 0; i != NumElems; ++i) {
4132 if (MaskVec[i] > (int)NumElems) {
4133 MaskVec[i] = NumElems;
4138 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4139 SVOp->getOperand(1), &MaskVec[0]);
4140 return SDValue(SVOp, 0);
4143 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4144 /// operation of specified width.
4145 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4147 unsigned NumElems = VT.getVectorNumElements();
4148 SmallVector<int, 8> Mask;
4149 Mask.push_back(NumElems);
4150 for (unsigned i = 1; i != NumElems; ++i)
4152 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4155 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4156 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4158 unsigned NumElems = VT.getVectorNumElements();
4159 SmallVector<int, 8> Mask;
4160 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4162 Mask.push_back(i + NumElems);
4164 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4167 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4168 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4170 unsigned NumElems = VT.getVectorNumElements();
4171 unsigned Half = NumElems/2;
4172 SmallVector<int, 8> Mask;
4173 for (unsigned i = 0; i != Half; ++i) {
4174 Mask.push_back(i + Half);
4175 Mask.push_back(i + NumElems + Half);
4177 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4180 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4181 // a generic shuffle instruction because the target has no such instructions.
4182 // Generate shuffles which repeat i16 and i8 several times until they can be
4183 // represented by v4f32 and then be manipulated by target suported shuffles.
4184 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4185 EVT VT = V.getValueType();
4186 int NumElems = VT.getVectorNumElements();
4187 DebugLoc dl = V.getDebugLoc();
4189 while (NumElems > 4) {
4190 if (EltNo < NumElems/2) {
4191 V = getUnpackl(DAG, dl, VT, V, V);
4193 V = getUnpackh(DAG, dl, VT, V, V);
4194 EltNo -= NumElems/2;
4201 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4202 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4203 EVT VT = V.getValueType();
4204 DebugLoc dl = V.getDebugLoc();
4205 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4206 && "Vector size not supported");
4208 if (VT.getSizeInBits() == 128) {
4209 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4210 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4211 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4214 // To use VPERMILPS to splat scalars, the second half of indicies must
4215 // refer to the higher part, which is a duplication of the lower one,
4216 // because VPERMILPS can only handle in-lane permutations.
4217 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4218 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4220 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4221 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4225 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4228 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4229 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4230 EVT SrcVT = SV->getValueType(0);
4231 SDValue V1 = SV->getOperand(0);
4232 DebugLoc dl = SV->getDebugLoc();
4234 int EltNo = SV->getSplatIndex();
4235 int NumElems = SrcVT.getVectorNumElements();
4236 unsigned Size = SrcVT.getSizeInBits();
4238 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4239 "Unknown how to promote splat for type");
4241 // Extract the 128-bit part containing the splat element and update
4242 // the splat element index when it refers to the higher register.
4244 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4245 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4247 EltNo -= NumElems/2;
4250 // All i16 and i8 vector types can't be used directly by a generic shuffle
4251 // instruction because the target has no such instruction. Generate shuffles
4252 // which repeat i16 and i8 several times until they fit in i32, and then can
4253 // be manipulated by target suported shuffles.
4254 EVT EltVT = SrcVT.getVectorElementType();
4255 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4256 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4258 // Recreate the 256-bit vector and place the same 128-bit vector
4259 // into the low and high part. This is necessary because we want
4260 // to use VPERM* to shuffle the vectors
4262 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4263 DAG.getConstant(0, MVT::i32), DAG, dl);
4264 V1 = Insert128BitVector(InsV, V1,
4265 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4268 return getLegalSplat(DAG, V1, EltNo);
4271 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4272 /// vector of zero or undef vector. This produces a shuffle where the low
4273 /// element of V2 is swizzled into the zero/undef vector, landing at element
4274 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4275 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4276 bool isZero, bool HasSSE2,
4277 SelectionDAG &DAG) {
4278 EVT VT = V2.getValueType();
4280 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4281 unsigned NumElems = VT.getVectorNumElements();
4282 SmallVector<int, 16> MaskVec;
4283 for (unsigned i = 0; i != NumElems; ++i)
4284 // If this is the insertion idx, put the low elt of V2 here.
4285 MaskVec.push_back(i == Idx ? NumElems : i);
4286 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4289 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4290 /// element of the result of the vector shuffle.
4291 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4294 return SDValue(); // Limit search depth.
4296 SDValue V = SDValue(N, 0);
4297 EVT VT = V.getValueType();
4298 unsigned Opcode = V.getOpcode();
4300 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4301 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4302 Index = SV->getMaskElt(Index);
4305 return DAG.getUNDEF(VT.getVectorElementType());
4307 int NumElems = VT.getVectorNumElements();
4308 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4309 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4312 // Recurse into target specific vector shuffles to find scalars.
4313 if (isTargetShuffle(Opcode)) {
4314 int NumElems = VT.getVectorNumElements();
4315 SmallVector<unsigned, 16> ShuffleMask;
4319 case X86ISD::SHUFPS:
4320 case X86ISD::SHUFPD:
4321 ImmN = N->getOperand(N->getNumOperands()-1);
4322 DecodeSHUFPSMask(NumElems,
4323 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4326 case X86ISD::PUNPCKHBW:
4327 case X86ISD::PUNPCKHWD:
4328 case X86ISD::PUNPCKHDQ:
4329 case X86ISD::PUNPCKHQDQ:
4330 DecodePUNPCKHMask(NumElems, ShuffleMask);
4332 case X86ISD::UNPCKHPS:
4333 case X86ISD::UNPCKHPD:
4334 case X86ISD::VUNPCKHPSY:
4335 case X86ISD::VUNPCKHPDY:
4336 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4338 case X86ISD::PUNPCKLBW:
4339 case X86ISD::PUNPCKLWD:
4340 case X86ISD::PUNPCKLDQ:
4341 case X86ISD::PUNPCKLQDQ:
4342 DecodePUNPCKLMask(VT, ShuffleMask);
4344 case X86ISD::UNPCKLPS:
4345 case X86ISD::UNPCKLPD:
4346 case X86ISD::VUNPCKLPSY:
4347 case X86ISD::VUNPCKLPDY:
4348 DecodeUNPCKLPMask(VT, ShuffleMask);
4350 case X86ISD::MOVHLPS:
4351 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4353 case X86ISD::MOVLHPS:
4354 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4356 case X86ISD::PSHUFD:
4357 ImmN = N->getOperand(N->getNumOperands()-1);
4358 DecodePSHUFMask(NumElems,
4359 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4362 case X86ISD::PSHUFHW:
4363 ImmN = N->getOperand(N->getNumOperands()-1);
4364 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4367 case X86ISD::PSHUFLW:
4368 ImmN = N->getOperand(N->getNumOperands()-1);
4369 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4373 case X86ISD::MOVSD: {
4374 // The index 0 always comes from the first element of the second source,
4375 // this is why MOVSS and MOVSD are used in the first place. The other
4376 // elements come from the other positions of the first source vector.
4377 unsigned OpNum = (Index == 0) ? 1 : 0;
4378 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4381 case X86ISD::VPERMILPS:
4382 ImmN = N->getOperand(N->getNumOperands()-1);
4383 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4386 case X86ISD::VPERMILPSY:
4387 ImmN = N->getOperand(N->getNumOperands()-1);
4388 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4391 case X86ISD::VPERMILPD:
4392 ImmN = N->getOperand(N->getNumOperands()-1);
4393 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4396 case X86ISD::VPERMILPDY:
4397 ImmN = N->getOperand(N->getNumOperands()-1);
4398 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4401 case X86ISD::VPERM2F128:
4402 ImmN = N->getOperand(N->getNumOperands()-1);
4403 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4407 assert("not implemented for target shuffle node");
4411 Index = ShuffleMask[Index];
4413 return DAG.getUNDEF(VT.getVectorElementType());
4415 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4416 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4420 // Actual nodes that may contain scalar elements
4421 if (Opcode == ISD::BITCAST) {
4422 V = V.getOperand(0);
4423 EVT SrcVT = V.getValueType();
4424 unsigned NumElems = VT.getVectorNumElements();
4426 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4430 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4431 return (Index == 0) ? V.getOperand(0)
4432 : DAG.getUNDEF(VT.getVectorElementType());
4434 if (V.getOpcode() == ISD::BUILD_VECTOR)
4435 return V.getOperand(Index);
4440 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4441 /// shuffle operation which come from a consecutively from a zero. The
4442 /// search can start in two different directions, from left or right.
4444 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4445 bool ZerosFromLeft, SelectionDAG &DAG) {
4448 while (i < NumElems) {
4449 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4450 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4451 if (!(Elt.getNode() &&
4452 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4460 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4461 /// MaskE correspond consecutively to elements from one of the vector operands,
4462 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4464 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4465 int OpIdx, int NumElems, unsigned &OpNum) {
4466 bool SeenV1 = false;
4467 bool SeenV2 = false;
4469 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4470 int Idx = SVOp->getMaskElt(i);
4471 // Ignore undef indicies
4480 // Only accept consecutive elements from the same vector
4481 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4485 OpNum = SeenV1 ? 0 : 1;
4489 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4490 /// logical left shift of a vector.
4491 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4492 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4493 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4494 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4495 false /* check zeros from right */, DAG);
4501 // Considering the elements in the mask that are not consecutive zeros,
4502 // check if they consecutively come from only one of the source vectors.
4504 // V1 = {X, A, B, C} 0
4506 // vector_shuffle V1, V2 <1, 2, 3, X>
4508 if (!isShuffleMaskConsecutive(SVOp,
4509 0, // Mask Start Index
4510 NumElems-NumZeros-1, // Mask End Index
4511 NumZeros, // Where to start looking in the src vector
4512 NumElems, // Number of elements in vector
4513 OpSrc)) // Which source operand ?
4518 ShVal = SVOp->getOperand(OpSrc);
4522 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4523 /// logical left shift of a vector.
4524 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4525 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4526 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4527 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4528 true /* check zeros from left */, DAG);
4534 // Considering the elements in the mask that are not consecutive zeros,
4535 // check if they consecutively come from only one of the source vectors.
4537 // 0 { A, B, X, X } = V2
4539 // vector_shuffle V1, V2 <X, X, 4, 5>
4541 if (!isShuffleMaskConsecutive(SVOp,
4542 NumZeros, // Mask Start Index
4543 NumElems-1, // Mask End Index
4544 0, // Where to start looking in the src vector
4545 NumElems, // Number of elements in vector
4546 OpSrc)) // Which source operand ?
4551 ShVal = SVOp->getOperand(OpSrc);
4555 /// isVectorShift - Returns true if the shuffle can be implemented as a
4556 /// logical left or right shift of a vector.
4557 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4558 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4559 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4560 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4566 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4568 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4569 unsigned NumNonZero, unsigned NumZero,
4571 const TargetLowering &TLI) {
4575 DebugLoc dl = Op.getDebugLoc();
4578 for (unsigned i = 0; i < 16; ++i) {
4579 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4580 if (ThisIsNonZero && First) {
4582 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4584 V = DAG.getUNDEF(MVT::v8i16);
4589 SDValue ThisElt(0, 0), LastElt(0, 0);
4590 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4591 if (LastIsNonZero) {
4592 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4593 MVT::i16, Op.getOperand(i-1));
4595 if (ThisIsNonZero) {
4596 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4597 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4598 ThisElt, DAG.getConstant(8, MVT::i8));
4600 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4604 if (ThisElt.getNode())
4605 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4606 DAG.getIntPtrConstant(i/2));
4610 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4613 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4615 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4616 unsigned NumNonZero, unsigned NumZero,
4618 const TargetLowering &TLI) {
4622 DebugLoc dl = Op.getDebugLoc();
4625 for (unsigned i = 0; i < 8; ++i) {
4626 bool isNonZero = (NonZeros & (1 << i)) != 0;
4630 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4632 V = DAG.getUNDEF(MVT::v8i16);
4635 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4636 MVT::v8i16, V, Op.getOperand(i),
4637 DAG.getIntPtrConstant(i));
4644 /// getVShift - Return a vector logical shift node.
4646 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4647 unsigned NumBits, SelectionDAG &DAG,
4648 const TargetLowering &TLI, DebugLoc dl) {
4649 EVT ShVT = MVT::v2i64;
4650 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4651 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4652 return DAG.getNode(ISD::BITCAST, dl, VT,
4653 DAG.getNode(Opc, dl, ShVT, SrcOp,
4654 DAG.getConstant(NumBits,
4655 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4659 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4660 SelectionDAG &DAG) const {
4662 // Check if the scalar load can be widened into a vector load. And if
4663 // the address is "base + cst" see if the cst can be "absorbed" into
4664 // the shuffle mask.
4665 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4666 SDValue Ptr = LD->getBasePtr();
4667 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4669 EVT PVT = LD->getValueType(0);
4670 if (PVT != MVT::i32 && PVT != MVT::f32)
4675 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4676 FI = FINode->getIndex();
4678 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4679 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4680 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4681 Offset = Ptr.getConstantOperandVal(1);
4682 Ptr = Ptr.getOperand(0);
4687 // FIXME: 256-bit vector instructions don't require a strict alignment,
4688 // improve this code to support it better.
4689 unsigned RequiredAlign = VT.getSizeInBits()/8;
4690 SDValue Chain = LD->getChain();
4691 // Make sure the stack object alignment is at least 16 or 32.
4692 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4693 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4694 if (MFI->isFixedObjectIndex(FI)) {
4695 // Can't change the alignment. FIXME: It's possible to compute
4696 // the exact stack offset and reference FI + adjust offset instead.
4697 // If someone *really* cares about this. That's the way to implement it.
4700 MFI->setObjectAlignment(FI, RequiredAlign);
4704 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4705 // Ptr + (Offset & ~15).
4708 if ((Offset % RequiredAlign) & 3)
4710 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4712 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4713 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4715 int EltNo = (Offset - StartOffset) >> 2;
4716 int NumElems = VT.getVectorNumElements();
4718 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4719 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4720 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4721 LD->getPointerInfo().getWithOffset(StartOffset),
4724 // Canonicalize it to a v4i32 or v8i32 shuffle.
4725 SmallVector<int, 8> Mask;
4726 for (int i = 0; i < NumElems; ++i)
4727 Mask.push_back(EltNo);
4729 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4730 return DAG.getNode(ISD::BITCAST, dl, NVT,
4731 DAG.getVectorShuffle(CanonVT, dl, V1,
4732 DAG.getUNDEF(CanonVT),&Mask[0]));
4738 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4739 /// vector of type 'VT', see if the elements can be replaced by a single large
4740 /// load which has the same value as a build_vector whose operands are 'elts'.
4742 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4744 /// FIXME: we'd also like to handle the case where the last elements are zero
4745 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4746 /// There's even a handy isZeroNode for that purpose.
4747 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4748 DebugLoc &DL, SelectionDAG &DAG) {
4749 EVT EltVT = VT.getVectorElementType();
4750 unsigned NumElems = Elts.size();
4752 LoadSDNode *LDBase = NULL;
4753 unsigned LastLoadedElt = -1U;
4755 // For each element in the initializer, see if we've found a load or an undef.
4756 // If we don't find an initial load element, or later load elements are
4757 // non-consecutive, bail out.
4758 for (unsigned i = 0; i < NumElems; ++i) {
4759 SDValue Elt = Elts[i];
4761 if (!Elt.getNode() ||
4762 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4765 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4767 LDBase = cast<LoadSDNode>(Elt.getNode());
4771 if (Elt.getOpcode() == ISD::UNDEF)
4774 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4775 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4780 // If we have found an entire vector of loads and undefs, then return a large
4781 // load of the entire vector width starting at the base pointer. If we found
4782 // consecutive loads for the low half, generate a vzext_load node.
4783 if (LastLoadedElt == NumElems - 1) {
4784 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4785 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4786 LDBase->getPointerInfo(),
4787 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4788 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4789 LDBase->getPointerInfo(),
4790 LDBase->isVolatile(), LDBase->isNonTemporal(),
4791 LDBase->getAlignment());
4792 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4793 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4794 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4795 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4796 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4798 LDBase->getMemOperand());
4799 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4805 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4806 DebugLoc dl = Op.getDebugLoc();
4808 EVT VT = Op.getValueType();
4809 EVT ExtVT = VT.getVectorElementType();
4810 unsigned NumElems = Op.getNumOperands();
4812 // Vectors containing all zeros can be matched by pxor and xorps later
4813 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
4814 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
4815 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
4816 if (Op.getValueType() == MVT::v4i32 ||
4817 Op.getValueType() == MVT::v8i32)
4820 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4823 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
4824 // vectors or broken into v4i32 operations on 256-bit vectors.
4825 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
4826 if (Op.getValueType() == MVT::v4i32)
4829 return getOnesVector(Op.getValueType(), DAG, dl);
4832 unsigned EVTBits = ExtVT.getSizeInBits();
4834 unsigned NumZero = 0;
4835 unsigned NumNonZero = 0;
4836 unsigned NonZeros = 0;
4837 bool IsAllConstants = true;
4838 SmallSet<SDValue, 8> Values;
4839 for (unsigned i = 0; i < NumElems; ++i) {
4840 SDValue Elt = Op.getOperand(i);
4841 if (Elt.getOpcode() == ISD::UNDEF)
4844 if (Elt.getOpcode() != ISD::Constant &&
4845 Elt.getOpcode() != ISD::ConstantFP)
4846 IsAllConstants = false;
4847 if (X86::isZeroNode(Elt))
4850 NonZeros |= (1 << i);
4855 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4856 if (NumNonZero == 0)
4857 return DAG.getUNDEF(VT);
4859 // Special case for single non-zero, non-undef, element.
4860 if (NumNonZero == 1) {
4861 unsigned Idx = CountTrailingZeros_32(NonZeros);
4862 SDValue Item = Op.getOperand(Idx);
4864 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4865 // the value are obviously zero, truncate the value to i32 and do the
4866 // insertion that way. Only do this if the value is non-constant or if the
4867 // value is a constant being inserted into element 0. It is cheaper to do
4868 // a constant pool load than it is to do a movd + shuffle.
4869 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4870 (!IsAllConstants || Idx == 0)) {
4871 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4873 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4874 EVT VecVT = MVT::v4i32;
4875 unsigned VecElts = 4;
4877 // Truncate the value (which may itself be a constant) to i32, and
4878 // convert it to a vector with movd (S2V+shuffle to zero extend).
4879 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4881 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4882 Subtarget->hasSSE2(), DAG);
4884 // Now we have our 32-bit value zero extended in the low element of
4885 // a vector. If Idx != 0, swizzle it into place.
4887 SmallVector<int, 4> Mask;
4888 Mask.push_back(Idx);
4889 for (unsigned i = 1; i != VecElts; ++i)
4891 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4892 DAG.getUNDEF(Item.getValueType()),
4895 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4899 // If we have a constant or non-constant insertion into the low element of
4900 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4901 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4902 // depending on what the source datatype is.
4905 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4906 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4907 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4908 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4909 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4910 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4912 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4913 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4914 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4915 EVT MiddleVT = MVT::v4i32;
4916 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4917 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4918 Subtarget->hasSSE2(), DAG);
4919 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4923 // Is it a vector logical left shift?
4924 if (NumElems == 2 && Idx == 1 &&
4925 X86::isZeroNode(Op.getOperand(0)) &&
4926 !X86::isZeroNode(Op.getOperand(1))) {
4927 unsigned NumBits = VT.getSizeInBits();
4928 return getVShift(true, VT,
4929 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4930 VT, Op.getOperand(1)),
4931 NumBits/2, DAG, *this, dl);
4934 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4937 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4938 // is a non-constant being inserted into an element other than the low one,
4939 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4940 // movd/movss) to move this into the low element, then shuffle it into
4942 if (EVTBits == 32) {
4943 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4945 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4946 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4947 Subtarget->hasSSE2(), DAG);
4948 SmallVector<int, 8> MaskVec;
4949 for (unsigned i = 0; i < NumElems; i++)
4950 MaskVec.push_back(i == Idx ? 0 : 1);
4951 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4955 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4956 if (Values.size() == 1) {
4957 if (EVTBits == 32) {
4958 // Instead of a shuffle like this:
4959 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4960 // Check if it's possible to issue this instead.
4961 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4962 unsigned Idx = CountTrailingZeros_32(NonZeros);
4963 SDValue Item = Op.getOperand(Idx);
4964 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4965 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4970 // A vector full of immediates; various special cases are already
4971 // handled, so this is best done with a single constant-pool load.
4975 // For AVX-length vectors, build the individual 128-bit pieces and use
4976 // shuffles to put them in place.
4977 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
4978 SmallVector<SDValue, 32> V;
4979 for (unsigned i = 0; i < NumElems; ++i)
4980 V.push_back(Op.getOperand(i));
4982 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
4984 // Build both the lower and upper subvector.
4985 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
4986 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
4989 // Recreate the wider vector with the lower and upper part.
4990 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
4991 DAG.getConstant(0, MVT::i32), DAG, dl);
4992 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
4996 // Let legalizer expand 2-wide build_vectors.
4997 if (EVTBits == 64) {
4998 if (NumNonZero == 1) {
4999 // One half is zero or undef.
5000 unsigned Idx = CountTrailingZeros_32(NonZeros);
5001 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5002 Op.getOperand(Idx));
5003 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5004 Subtarget->hasSSE2(), DAG);
5009 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5010 if (EVTBits == 8 && NumElems == 16) {
5011 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5013 if (V.getNode()) return V;
5016 if (EVTBits == 16 && NumElems == 8) {
5017 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5019 if (V.getNode()) return V;
5022 // If element VT is == 32 bits, turn it into a number of shuffles.
5023 SmallVector<SDValue, 8> V;
5025 if (NumElems == 4 && NumZero > 0) {
5026 for (unsigned i = 0; i < 4; ++i) {
5027 bool isZero = !(NonZeros & (1 << i));
5029 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5031 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5034 for (unsigned i = 0; i < 2; ++i) {
5035 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5038 V[i] = V[i*2]; // Must be a zero vector.
5041 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5044 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5047 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5052 SmallVector<int, 8> MaskVec;
5053 bool Reverse = (NonZeros & 0x3) == 2;
5054 for (unsigned i = 0; i < 2; ++i)
5055 MaskVec.push_back(Reverse ? 1-i : i);
5056 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5057 for (unsigned i = 0; i < 2; ++i)
5058 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5059 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5062 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5063 // Check for a build vector of consecutive loads.
5064 for (unsigned i = 0; i < NumElems; ++i)
5065 V[i] = Op.getOperand(i);
5067 // Check for elements which are consecutive loads.
5068 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5072 // For SSE 4.1, use insertps to put the high elements into the low element.
5073 if (getSubtarget()->hasSSE41()) {
5075 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5076 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5078 Result = DAG.getUNDEF(VT);
5080 for (unsigned i = 1; i < NumElems; ++i) {
5081 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5082 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5083 Op.getOperand(i), DAG.getIntPtrConstant(i));
5088 // Otherwise, expand into a number of unpckl*, start by extending each of
5089 // our (non-undef) elements to the full vector width with the element in the
5090 // bottom slot of the vector (which generates no code for SSE).
5091 for (unsigned i = 0; i < NumElems; ++i) {
5092 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5093 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5095 V[i] = DAG.getUNDEF(VT);
5098 // Next, we iteratively mix elements, e.g. for v4f32:
5099 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5100 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5101 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5102 unsigned EltStride = NumElems >> 1;
5103 while (EltStride != 0) {
5104 for (unsigned i = 0; i < EltStride; ++i) {
5105 // If V[i+EltStride] is undef and this is the first round of mixing,
5106 // then it is safe to just drop this shuffle: V[i] is already in the
5107 // right place, the one element (since it's the first round) being
5108 // inserted as undef can be dropped. This isn't safe for successive
5109 // rounds because they will permute elements within both vectors.
5110 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5111 EltStride == NumElems/2)
5114 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5123 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5124 // them in a MMX register. This is better than doing a stack convert.
5125 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5126 DebugLoc dl = Op.getDebugLoc();
5127 EVT ResVT = Op.getValueType();
5129 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5130 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5132 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5133 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5134 InVec = Op.getOperand(1);
5135 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5136 unsigned NumElts = ResVT.getVectorNumElements();
5137 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5138 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5139 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5141 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5142 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5143 Mask[0] = 0; Mask[1] = 2;
5144 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5146 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5149 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5150 // to create 256-bit vectors from two other 128-bit ones.
5151 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5152 DebugLoc dl = Op.getDebugLoc();
5153 EVT ResVT = Op.getValueType();
5155 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5157 SDValue V1 = Op.getOperand(0);
5158 SDValue V2 = Op.getOperand(1);
5159 unsigned NumElems = ResVT.getVectorNumElements();
5161 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5162 DAG.getConstant(0, MVT::i32), DAG, dl);
5163 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5168 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5169 EVT ResVT = Op.getValueType();
5171 assert(Op.getNumOperands() == 2);
5172 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5173 "Unsupported CONCAT_VECTORS for value type");
5175 // We support concatenate two MMX registers and place them in a MMX register.
5176 // This is better than doing a stack convert.
5177 if (ResVT.is128BitVector())
5178 return LowerMMXCONCAT_VECTORS(Op, DAG);
5180 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5181 // from two other 128-bit ones.
5182 return LowerAVXCONCAT_VECTORS(Op, DAG);
5185 // v8i16 shuffles - Prefer shuffles in the following order:
5186 // 1. [all] pshuflw, pshufhw, optional move
5187 // 2. [ssse3] 1 x pshufb
5188 // 3. [ssse3] 2 x pshufb + 1 x por
5189 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5191 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5192 SelectionDAG &DAG) const {
5193 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5194 SDValue V1 = SVOp->getOperand(0);
5195 SDValue V2 = SVOp->getOperand(1);
5196 DebugLoc dl = SVOp->getDebugLoc();
5197 SmallVector<int, 8> MaskVals;
5199 // Determine if more than 1 of the words in each of the low and high quadwords
5200 // of the result come from the same quadword of one of the two inputs. Undef
5201 // mask values count as coming from any quadword, for better codegen.
5202 SmallVector<unsigned, 4> LoQuad(4);
5203 SmallVector<unsigned, 4> HiQuad(4);
5204 BitVector InputQuads(4);
5205 for (unsigned i = 0; i < 8; ++i) {
5206 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5207 int EltIdx = SVOp->getMaskElt(i);
5208 MaskVals.push_back(EltIdx);
5217 InputQuads.set(EltIdx / 4);
5220 int BestLoQuad = -1;
5221 unsigned MaxQuad = 1;
5222 for (unsigned i = 0; i < 4; ++i) {
5223 if (LoQuad[i] > MaxQuad) {
5225 MaxQuad = LoQuad[i];
5229 int BestHiQuad = -1;
5231 for (unsigned i = 0; i < 4; ++i) {
5232 if (HiQuad[i] > MaxQuad) {
5234 MaxQuad = HiQuad[i];
5238 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5239 // of the two input vectors, shuffle them into one input vector so only a
5240 // single pshufb instruction is necessary. If There are more than 2 input
5241 // quads, disable the next transformation since it does not help SSSE3.
5242 bool V1Used = InputQuads[0] || InputQuads[1];
5243 bool V2Used = InputQuads[2] || InputQuads[3];
5244 if (Subtarget->hasSSSE3()) {
5245 if (InputQuads.count() == 2 && V1Used && V2Used) {
5246 BestLoQuad = InputQuads.find_first();
5247 BestHiQuad = InputQuads.find_next(BestLoQuad);
5249 if (InputQuads.count() > 2) {
5255 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5256 // the shuffle mask. If a quad is scored as -1, that means that it contains
5257 // words from all 4 input quadwords.
5259 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5260 SmallVector<int, 8> MaskV;
5261 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5262 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5263 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5264 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5265 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5266 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5268 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5269 // source words for the shuffle, to aid later transformations.
5270 bool AllWordsInNewV = true;
5271 bool InOrder[2] = { true, true };
5272 for (unsigned i = 0; i != 8; ++i) {
5273 int idx = MaskVals[i];
5275 InOrder[i/4] = false;
5276 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5278 AllWordsInNewV = false;
5282 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5283 if (AllWordsInNewV) {
5284 for (int i = 0; i != 8; ++i) {
5285 int idx = MaskVals[i];
5288 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5289 if ((idx != i) && idx < 4)
5291 if ((idx != i) && idx > 3)
5300 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5301 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5302 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5303 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5304 unsigned TargetMask = 0;
5305 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5306 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5307 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5308 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5309 V1 = NewV.getOperand(0);
5310 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5314 // If we have SSSE3, and all words of the result are from 1 input vector,
5315 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5316 // is present, fall back to case 4.
5317 if (Subtarget->hasSSSE3()) {
5318 SmallVector<SDValue,16> pshufbMask;
5320 // If we have elements from both input vectors, set the high bit of the
5321 // shuffle mask element to zero out elements that come from V2 in the V1
5322 // mask, and elements that come from V1 in the V2 mask, so that the two
5323 // results can be OR'd together.
5324 bool TwoInputs = V1Used && V2Used;
5325 for (unsigned i = 0; i != 8; ++i) {
5326 int EltIdx = MaskVals[i] * 2;
5327 if (TwoInputs && (EltIdx >= 16)) {
5328 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5329 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5332 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5333 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5335 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5336 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5337 DAG.getNode(ISD::BUILD_VECTOR, dl,
5338 MVT::v16i8, &pshufbMask[0], 16));
5340 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5342 // Calculate the shuffle mask for the second input, shuffle it, and
5343 // OR it with the first shuffled input.
5345 for (unsigned i = 0; i != 8; ++i) {
5346 int EltIdx = MaskVals[i] * 2;
5348 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5349 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5352 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5353 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5355 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5356 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5357 DAG.getNode(ISD::BUILD_VECTOR, dl,
5358 MVT::v16i8, &pshufbMask[0], 16));
5359 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5360 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5363 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5364 // and update MaskVals with new element order.
5365 BitVector InOrder(8);
5366 if (BestLoQuad >= 0) {
5367 SmallVector<int, 8> MaskV;
5368 for (int i = 0; i != 4; ++i) {
5369 int idx = MaskVals[i];
5371 MaskV.push_back(-1);
5373 } else if ((idx / 4) == BestLoQuad) {
5374 MaskV.push_back(idx & 3);
5377 MaskV.push_back(-1);
5380 for (unsigned i = 4; i != 8; ++i)
5382 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5385 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5386 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5388 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5392 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5393 // and update MaskVals with the new element order.
5394 if (BestHiQuad >= 0) {
5395 SmallVector<int, 8> MaskV;
5396 for (unsigned i = 0; i != 4; ++i)
5398 for (unsigned i = 4; i != 8; ++i) {
5399 int idx = MaskVals[i];
5401 MaskV.push_back(-1);
5403 } else if ((idx / 4) == BestHiQuad) {
5404 MaskV.push_back((idx & 3) + 4);
5407 MaskV.push_back(-1);
5410 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5413 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5414 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5416 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5420 // In case BestHi & BestLo were both -1, which means each quadword has a word
5421 // from each of the four input quadwords, calculate the InOrder bitvector now
5422 // before falling through to the insert/extract cleanup.
5423 if (BestLoQuad == -1 && BestHiQuad == -1) {
5425 for (int i = 0; i != 8; ++i)
5426 if (MaskVals[i] < 0 || MaskVals[i] == i)
5430 // The other elements are put in the right place using pextrw and pinsrw.
5431 for (unsigned i = 0; i != 8; ++i) {
5434 int EltIdx = MaskVals[i];
5437 SDValue ExtOp = (EltIdx < 8)
5438 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5439 DAG.getIntPtrConstant(EltIdx))
5440 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5441 DAG.getIntPtrConstant(EltIdx - 8));
5442 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5443 DAG.getIntPtrConstant(i));
5448 // v16i8 shuffles - Prefer shuffles in the following order:
5449 // 1. [ssse3] 1 x pshufb
5450 // 2. [ssse3] 2 x pshufb + 1 x por
5451 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5453 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5455 const X86TargetLowering &TLI) {
5456 SDValue V1 = SVOp->getOperand(0);
5457 SDValue V2 = SVOp->getOperand(1);
5458 DebugLoc dl = SVOp->getDebugLoc();
5459 SmallVector<int, 16> MaskVals;
5460 SVOp->getMask(MaskVals);
5462 // If we have SSSE3, case 1 is generated when all result bytes come from
5463 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5464 // present, fall back to case 3.
5465 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5468 for (unsigned i = 0; i < 16; ++i) {
5469 int EltIdx = MaskVals[i];
5478 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5479 if (TLI.getSubtarget()->hasSSSE3()) {
5480 SmallVector<SDValue,16> pshufbMask;
5482 // If all result elements are from one input vector, then only translate
5483 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5485 // Otherwise, we have elements from both input vectors, and must zero out
5486 // elements that come from V2 in the first mask, and V1 in the second mask
5487 // so that we can OR them together.
5488 bool TwoInputs = !(V1Only || V2Only);
5489 for (unsigned i = 0; i != 16; ++i) {
5490 int EltIdx = MaskVals[i];
5491 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5492 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5495 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5497 // If all the elements are from V2, assign it to V1 and return after
5498 // building the first pshufb.
5501 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5502 DAG.getNode(ISD::BUILD_VECTOR, dl,
5503 MVT::v16i8, &pshufbMask[0], 16));
5507 // Calculate the shuffle mask for the second input, shuffle it, and
5508 // OR it with the first shuffled input.
5510 for (unsigned i = 0; i != 16; ++i) {
5511 int EltIdx = MaskVals[i];
5513 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5516 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5518 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5519 DAG.getNode(ISD::BUILD_VECTOR, dl,
5520 MVT::v16i8, &pshufbMask[0], 16));
5521 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5524 // No SSSE3 - Calculate in place words and then fix all out of place words
5525 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5526 // the 16 different words that comprise the two doublequadword input vectors.
5527 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5528 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5529 SDValue NewV = V2Only ? V2 : V1;
5530 for (int i = 0; i != 8; ++i) {
5531 int Elt0 = MaskVals[i*2];
5532 int Elt1 = MaskVals[i*2+1];
5534 // This word of the result is all undef, skip it.
5535 if (Elt0 < 0 && Elt1 < 0)
5538 // This word of the result is already in the correct place, skip it.
5539 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5541 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5544 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5545 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5548 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5549 // using a single extract together, load it and store it.
5550 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5551 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5552 DAG.getIntPtrConstant(Elt1 / 2));
5553 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5554 DAG.getIntPtrConstant(i));
5558 // If Elt1 is defined, extract it from the appropriate source. If the
5559 // source byte is not also odd, shift the extracted word left 8 bits
5560 // otherwise clear the bottom 8 bits if we need to do an or.
5562 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5563 DAG.getIntPtrConstant(Elt1 / 2));
5564 if ((Elt1 & 1) == 0)
5565 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5567 TLI.getShiftAmountTy(InsElt.getValueType())));
5569 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5570 DAG.getConstant(0xFF00, MVT::i16));
5572 // If Elt0 is defined, extract it from the appropriate source. If the
5573 // source byte is not also even, shift the extracted word right 8 bits. If
5574 // Elt1 was also defined, OR the extracted values together before
5575 // inserting them in the result.
5577 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5578 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5579 if ((Elt0 & 1) != 0)
5580 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5582 TLI.getShiftAmountTy(InsElt0.getValueType())));
5584 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5585 DAG.getConstant(0x00FF, MVT::i16));
5586 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5589 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5590 DAG.getIntPtrConstant(i));
5592 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5595 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5596 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5597 /// done when every pair / quad of shuffle mask elements point to elements in
5598 /// the right sequence. e.g.
5599 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5601 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5602 SelectionDAG &DAG, DebugLoc dl) {
5603 EVT VT = SVOp->getValueType(0);
5604 SDValue V1 = SVOp->getOperand(0);
5605 SDValue V2 = SVOp->getOperand(1);
5606 unsigned NumElems = VT.getVectorNumElements();
5607 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5609 switch (VT.getSimpleVT().SimpleTy) {
5610 default: assert(false && "Unexpected!");
5611 case MVT::v4f32: NewVT = MVT::v2f64; break;
5612 case MVT::v4i32: NewVT = MVT::v2i64; break;
5613 case MVT::v8i16: NewVT = MVT::v4i32; break;
5614 case MVT::v16i8: NewVT = MVT::v4i32; break;
5617 int Scale = NumElems / NewWidth;
5618 SmallVector<int, 8> MaskVec;
5619 for (unsigned i = 0; i < NumElems; i += Scale) {
5621 for (int j = 0; j < Scale; ++j) {
5622 int EltIdx = SVOp->getMaskElt(i+j);
5626 StartIdx = EltIdx - (EltIdx % Scale);
5627 if (EltIdx != StartIdx + j)
5631 MaskVec.push_back(-1);
5633 MaskVec.push_back(StartIdx / Scale);
5636 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5637 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5638 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5641 /// getVZextMovL - Return a zero-extending vector move low node.
5643 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5644 SDValue SrcOp, SelectionDAG &DAG,
5645 const X86Subtarget *Subtarget, DebugLoc dl) {
5646 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5647 LoadSDNode *LD = NULL;
5648 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5649 LD = dyn_cast<LoadSDNode>(SrcOp);
5651 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5653 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5654 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5655 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5656 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5657 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5659 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5660 return DAG.getNode(ISD::BITCAST, dl, VT,
5661 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5662 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5670 return DAG.getNode(ISD::BITCAST, dl, VT,
5671 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5672 DAG.getNode(ISD::BITCAST, dl,
5676 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5677 /// shuffle node referes to only one lane in the sources.
5678 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5679 EVT VT = SVOp->getValueType(0);
5680 int NumElems = VT.getVectorNumElements();
5681 int HalfSize = NumElems/2;
5682 SmallVector<int, 16> M;
5684 bool MatchA = false, MatchB = false;
5686 for (int l = 0; l < NumElems*2; l += HalfSize) {
5687 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5693 for (int l = 0; l < NumElems*2; l += HalfSize) {
5694 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5700 return MatchA && MatchB;
5703 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5704 /// which could not be matched by any known target speficic shuffle
5706 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5707 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5708 // If each half of a vector shuffle node referes to only one lane in the
5709 // source vectors, extract each used 128-bit lane and shuffle them using
5710 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5711 // the work to the legalizer.
5712 DebugLoc dl = SVOp->getDebugLoc();
5713 EVT VT = SVOp->getValueType(0);
5714 int NumElems = VT.getVectorNumElements();
5715 int HalfSize = NumElems/2;
5717 // Extract the reference for each half
5718 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5719 int FstVecOpNum = 0, SndVecOpNum = 0;
5720 for (int i = 0; i < HalfSize; ++i) {
5721 int Elt = SVOp->getMaskElt(i);
5722 if (SVOp->getMaskElt(i) < 0)
5724 FstVecOpNum = Elt/NumElems;
5725 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5728 for (int i = HalfSize; i < NumElems; ++i) {
5729 int Elt = SVOp->getMaskElt(i);
5730 if (SVOp->getMaskElt(i) < 0)
5732 SndVecOpNum = Elt/NumElems;
5733 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5737 // Extract the subvectors
5738 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5739 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5740 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5741 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5743 // Generate 128-bit shuffles
5744 SmallVector<int, 16> MaskV1, MaskV2;
5745 for (int i = 0; i < HalfSize; ++i) {
5746 int Elt = SVOp->getMaskElt(i);
5747 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5749 for (int i = HalfSize; i < NumElems; ++i) {
5750 int Elt = SVOp->getMaskElt(i);
5751 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5754 EVT NVT = V1.getValueType();
5755 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5756 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5758 // Concatenate the result back
5759 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5760 DAG.getConstant(0, MVT::i32), DAG, dl);
5761 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5768 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5769 /// 4 elements, and match them with several different shuffle types.
5771 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5772 SDValue V1 = SVOp->getOperand(0);
5773 SDValue V2 = SVOp->getOperand(1);
5774 DebugLoc dl = SVOp->getDebugLoc();
5775 EVT VT = SVOp->getValueType(0);
5777 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5779 SmallVector<std::pair<int, int>, 8> Locs;
5781 SmallVector<int, 8> Mask1(4U, -1);
5782 SmallVector<int, 8> PermMask;
5783 SVOp->getMask(PermMask);
5787 for (unsigned i = 0; i != 4; ++i) {
5788 int Idx = PermMask[i];
5790 Locs[i] = std::make_pair(-1, -1);
5792 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5794 Locs[i] = std::make_pair(0, NumLo);
5798 Locs[i] = std::make_pair(1, NumHi);
5800 Mask1[2+NumHi] = Idx;
5806 if (NumLo <= 2 && NumHi <= 2) {
5807 // If no more than two elements come from either vector. This can be
5808 // implemented with two shuffles. First shuffle gather the elements.
5809 // The second shuffle, which takes the first shuffle as both of its
5810 // vector operands, put the elements into the right order.
5811 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5813 SmallVector<int, 8> Mask2(4U, -1);
5815 for (unsigned i = 0; i != 4; ++i) {
5816 if (Locs[i].first == -1)
5819 unsigned Idx = (i < 2) ? 0 : 4;
5820 Idx += Locs[i].first * 2 + Locs[i].second;
5825 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5826 } else if (NumLo == 3 || NumHi == 3) {
5827 // Otherwise, we must have three elements from one vector, call it X, and
5828 // one element from the other, call it Y. First, use a shufps to build an
5829 // intermediate vector with the one element from Y and the element from X
5830 // that will be in the same half in the final destination (the indexes don't
5831 // matter). Then, use a shufps to build the final vector, taking the half
5832 // containing the element from Y from the intermediate, and the other half
5835 // Normalize it so the 3 elements come from V1.
5836 CommuteVectorShuffleMask(PermMask, VT);
5840 // Find the element from V2.
5842 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5843 int Val = PermMask[HiIndex];
5850 Mask1[0] = PermMask[HiIndex];
5852 Mask1[2] = PermMask[HiIndex^1];
5854 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5857 Mask1[0] = PermMask[0];
5858 Mask1[1] = PermMask[1];
5859 Mask1[2] = HiIndex & 1 ? 6 : 4;
5860 Mask1[3] = HiIndex & 1 ? 4 : 6;
5861 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5863 Mask1[0] = HiIndex & 1 ? 2 : 0;
5864 Mask1[1] = HiIndex & 1 ? 0 : 2;
5865 Mask1[2] = PermMask[2];
5866 Mask1[3] = PermMask[3];
5871 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5875 // Break it into (shuffle shuffle_hi, shuffle_lo).
5878 SmallVector<int,8> LoMask(4U, -1);
5879 SmallVector<int,8> HiMask(4U, -1);
5881 SmallVector<int,8> *MaskPtr = &LoMask;
5882 unsigned MaskIdx = 0;
5885 for (unsigned i = 0; i != 4; ++i) {
5892 int Idx = PermMask[i];
5894 Locs[i] = std::make_pair(-1, -1);
5895 } else if (Idx < 4) {
5896 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5897 (*MaskPtr)[LoIdx] = Idx;
5900 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5901 (*MaskPtr)[HiIdx] = Idx;
5906 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5907 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5908 SmallVector<int, 8> MaskOps;
5909 for (unsigned i = 0; i != 4; ++i) {
5910 if (Locs[i].first == -1) {
5911 MaskOps.push_back(-1);
5913 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5914 MaskOps.push_back(Idx);
5917 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5920 static bool MayFoldVectorLoad(SDValue V) {
5921 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5922 V = V.getOperand(0);
5923 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5924 V = V.getOperand(0);
5930 // FIXME: the version above should always be used. Since there's
5931 // a bug where several vector shuffles can't be folded because the
5932 // DAG is not updated during lowering and a node claims to have two
5933 // uses while it only has one, use this version, and let isel match
5934 // another instruction if the load really happens to have more than
5935 // one use. Remove this version after this bug get fixed.
5936 // rdar://8434668, PR8156
5937 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5938 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5939 V = V.getOperand(0);
5940 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5941 V = V.getOperand(0);
5942 if (ISD::isNormalLoad(V.getNode()))
5947 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5948 /// a vector extract, and if both can be later optimized into a single load.
5949 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5950 /// here because otherwise a target specific shuffle node is going to be
5951 /// emitted for this shuffle, and the optimization not done.
5952 /// FIXME: This is probably not the best approach, but fix the problem
5953 /// until the right path is decided.
5955 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5956 const TargetLowering &TLI) {
5957 EVT VT = V.getValueType();
5958 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5960 // Be sure that the vector shuffle is present in a pattern like this:
5961 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5965 SDNode *N = *V.getNode()->use_begin();
5966 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5969 SDValue EltNo = N->getOperand(1);
5970 if (!isa<ConstantSDNode>(EltNo))
5973 // If the bit convert changed the number of elements, it is unsafe
5974 // to examine the mask.
5975 bool HasShuffleIntoBitcast = false;
5976 if (V.getOpcode() == ISD::BITCAST) {
5977 EVT SrcVT = V.getOperand(0).getValueType();
5978 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5980 V = V.getOperand(0);
5981 HasShuffleIntoBitcast = true;
5984 // Select the input vector, guarding against out of range extract vector.
5985 unsigned NumElems = VT.getVectorNumElements();
5986 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5987 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5988 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5990 // Skip one more bit_convert if necessary
5991 if (V.getOpcode() == ISD::BITCAST)
5992 V = V.getOperand(0);
5994 if (ISD::isNormalLoad(V.getNode())) {
5995 // Is the original load suitable?
5996 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5998 // FIXME: avoid the multi-use bug that is preventing lots of
5999 // of foldings to be detected, this is still wrong of course, but
6000 // give the temporary desired behavior, and if it happens that
6001 // the load has real more uses, during isel it will not fold, and
6002 // will generate poor code.
6003 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6006 if (!HasShuffleIntoBitcast)
6009 // If there's a bitcast before the shuffle, check if the load type and
6010 // alignment is valid.
6011 unsigned Align = LN0->getAlignment();
6013 TLI.getTargetData()->getABITypeAlignment(
6014 VT.getTypeForEVT(*DAG.getContext()));
6016 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6024 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6025 EVT VT = Op.getValueType();
6027 // Canonizalize to v2f64.
6028 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6029 return DAG.getNode(ISD::BITCAST, dl, VT,
6030 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6035 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6037 SDValue V1 = Op.getOperand(0);
6038 SDValue V2 = Op.getOperand(1);
6039 EVT VT = Op.getValueType();
6041 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6043 if (HasSSE2 && VT == MVT::v2f64)
6044 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6047 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
6051 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6052 SDValue V1 = Op.getOperand(0);
6053 SDValue V2 = Op.getOperand(1);
6054 EVT VT = Op.getValueType();
6056 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6057 "unsupported shuffle type");
6059 if (V2.getOpcode() == ISD::UNDEF)
6063 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6067 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6068 SDValue V1 = Op.getOperand(0);
6069 SDValue V2 = Op.getOperand(1);
6070 EVT VT = Op.getValueType();
6071 unsigned NumElems = VT.getVectorNumElements();
6073 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6074 // operand of these instructions is only memory, so check if there's a
6075 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6077 bool CanFoldLoad = false;
6079 // Trivial case, when V2 comes from a load.
6080 if (MayFoldVectorLoad(V2))
6083 // When V1 is a load, it can be folded later into a store in isel, example:
6084 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6086 // (MOVLPSmr addr:$src1, VR128:$src2)
6087 // So, recognize this potential and also use MOVLPS or MOVLPD
6088 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6091 // Both of them can't be memory operations though.
6092 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6093 CanFoldLoad = false;
6096 if (HasSSE2 && NumElems == 2)
6097 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6100 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6103 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6104 // movl and movlp will both match v2i64, but v2i64 is never matched by
6105 // movl earlier because we make it strict to avoid messing with the movlp load
6106 // folding logic (see the code above getMOVLP call). Match it here then,
6107 // this is horrible, but will stay like this until we move all shuffle
6108 // matching to x86 specific nodes. Note that for the 1st condition all
6109 // types are matched with movsd.
6110 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
6111 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6113 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6116 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6118 // Invert the operand order and use SHUFPS to match it.
6119 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
6120 X86::getShuffleSHUFImmediate(SVOp), DAG);
6123 static inline unsigned getUNPCKLOpcode(EVT VT) {
6124 switch(VT.getSimpleVT().SimpleTy) {
6125 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6126 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6127 case MVT::v4f32: return X86ISD::UNPCKLPS;
6128 case MVT::v2f64: return X86ISD::UNPCKLPD;
6129 case MVT::v8i32: // Use fp unit for int unpack.
6130 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6131 case MVT::v4i64: // Use fp unit for int unpack.
6132 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6133 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6134 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6136 llvm_unreachable("Unknown type for unpckl");
6141 static inline unsigned getUNPCKHOpcode(EVT VT) {
6142 switch(VT.getSimpleVT().SimpleTy) {
6143 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6144 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6145 case MVT::v4f32: return X86ISD::UNPCKHPS;
6146 case MVT::v2f64: return X86ISD::UNPCKHPD;
6147 case MVT::v8i32: // Use fp unit for int unpack.
6148 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6149 case MVT::v4i64: // Use fp unit for int unpack.
6150 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6151 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6152 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6154 llvm_unreachable("Unknown type for unpckh");
6159 static inline unsigned getVPERMILOpcode(EVT VT) {
6160 switch(VT.getSimpleVT().SimpleTy) {
6162 case MVT::v4f32: return X86ISD::VPERMILPS;
6164 case MVT::v2f64: return X86ISD::VPERMILPD;
6166 case MVT::v8f32: return X86ISD::VPERMILPSY;
6168 case MVT::v4f64: return X86ISD::VPERMILPDY;
6170 llvm_unreachable("Unknown type for vpermil");
6175 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6176 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6177 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6178 static bool isVectorBroadcast(SDValue &Op) {
6179 EVT VT = Op.getValueType();
6180 bool Is256 = VT.getSizeInBits() == 256;
6182 assert((VT.getSizeInBits() == 128 || Is256) &&
6183 "Unsupported type for vbroadcast node");
6186 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6187 V = V.getOperand(0);
6189 if (Is256 && !(V.hasOneUse() &&
6190 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6191 V.getOperand(0).getOpcode() == ISD::UNDEF))
6195 V = V.getOperand(1);
6196 if (V.hasOneUse() && V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6199 // Check the source scalar_to_vector type. 256-bit broadcasts are
6200 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6201 // for 32-bit scalars.
6202 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6203 if (ScalarSize != 32 && ScalarSize != 64)
6205 if (!Is256 && ScalarSize == 64)
6208 V = V.getOperand(0);
6209 if (!MayFoldLoad(V))
6212 // Return the load node
6218 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6219 const TargetLowering &TLI,
6220 const X86Subtarget *Subtarget) {
6221 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6222 EVT VT = Op.getValueType();
6223 DebugLoc dl = Op.getDebugLoc();
6224 SDValue V1 = Op.getOperand(0);
6225 SDValue V2 = Op.getOperand(1);
6227 if (isZeroShuffle(SVOp))
6228 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6230 // Handle splat operations
6231 if (SVOp->isSplat()) {
6232 unsigned NumElem = VT.getVectorNumElements();
6233 int Size = VT.getSizeInBits();
6234 // Special case, this is the only place now where it's allowed to return
6235 // a vector_shuffle operation without using a target specific node, because
6236 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6237 // this be moved to DAGCombine instead?
6238 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6241 // Use vbroadcast whenever the splat comes from a foldable load
6242 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6243 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6245 // Handle splats by matching through known shuffle masks
6246 if ((Size == 128 && NumElem <= 4) ||
6247 (Size == 256 && NumElem < 8))
6250 // All remaning splats are promoted to target supported vector shuffles.
6251 return PromoteSplat(SVOp, DAG);
6254 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6256 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6257 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6258 if (NewOp.getNode())
6259 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6260 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6261 // FIXME: Figure out a cleaner way to do this.
6262 // Try to make use of movq to zero out the top part.
6263 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6264 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6265 if (NewOp.getNode()) {
6266 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6267 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6268 DAG, Subtarget, dl);
6270 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6271 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6272 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6273 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6274 DAG, Subtarget, dl);
6281 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6282 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6283 SDValue V1 = Op.getOperand(0);
6284 SDValue V2 = Op.getOperand(1);
6285 EVT VT = Op.getValueType();
6286 DebugLoc dl = Op.getDebugLoc();
6287 unsigned NumElems = VT.getVectorNumElements();
6288 bool isMMX = VT.getSizeInBits() == 64;
6289 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6290 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6291 bool V1IsSplat = false;
6292 bool V2IsSplat = false;
6293 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6294 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6295 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6296 MachineFunction &MF = DAG.getMachineFunction();
6297 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6299 // Shuffle operations on MMX not supported.
6303 // Vector shuffle lowering takes 3 steps:
6305 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6306 // narrowing and commutation of operands should be handled.
6307 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6309 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6310 // so the shuffle can be broken into other shuffles and the legalizer can
6311 // try the lowering again.
6313 // The general ideia is that no vector_shuffle operation should be left to
6314 // be matched during isel, all of them must be converted to a target specific
6317 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6318 // narrowing and commutation of operands should be handled. The actual code
6319 // doesn't include all of those, work in progress...
6320 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6321 if (NewOp.getNode())
6324 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6325 // unpckh_undef). Only use pshufd if speed is more important than size.
6326 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6327 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6328 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6329 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6331 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6332 RelaxedMayFoldVectorLoad(V1))
6333 return getMOVDDup(Op, dl, V1, DAG);
6335 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6336 return getMOVHighToLow(Op, dl, DAG);
6338 // Use to match splats
6339 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6340 (VT == MVT::v2f64 || VT == MVT::v2i64))
6341 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6343 if (X86::isPSHUFDMask(SVOp)) {
6344 // The actual implementation will match the mask in the if above and then
6345 // during isel it can match several different instructions, not only pshufd
6346 // as its name says, sad but true, emulate the behavior for now...
6347 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6348 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6350 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6352 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6353 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6355 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6356 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
6359 if (VT == MVT::v4f32)
6360 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
6364 // Check if this can be converted into a logical shift.
6365 bool isLeft = false;
6368 bool isShift = getSubtarget()->hasSSE2() &&
6369 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6370 if (isShift && ShVal.hasOneUse()) {
6371 // If the shifted value has multiple uses, it may be cheaper to use
6372 // v_set0 + movlhps or movhlps, etc.
6373 EVT EltVT = VT.getVectorElementType();
6374 ShAmt *= EltVT.getSizeInBits();
6375 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6378 if (X86::isMOVLMask(SVOp)) {
6381 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6382 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6383 if (!X86::isMOVLPMask(SVOp)) {
6384 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6385 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6387 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6388 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6392 // FIXME: fold these into legal mask.
6393 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6394 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6396 if (X86::isMOVHLPSMask(SVOp))
6397 return getMOVHighToLow(Op, dl, DAG);
6399 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6400 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6402 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6403 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6405 if (X86::isMOVLPMask(SVOp))
6406 return getMOVLP(Op, dl, DAG, HasSSE2);
6408 if (ShouldXformToMOVHLPS(SVOp) ||
6409 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6410 return CommuteVectorShuffle(SVOp, DAG);
6413 // No better options. Use a vshl / vsrl.
6414 EVT EltVT = VT.getVectorElementType();
6415 ShAmt *= EltVT.getSizeInBits();
6416 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6419 bool Commuted = false;
6420 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6421 // 1,1,1,1 -> v8i16 though.
6422 V1IsSplat = isSplatVector(V1.getNode());
6423 V2IsSplat = isSplatVector(V2.getNode());
6425 // Canonicalize the splat or undef, if present, to be on the RHS.
6426 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6427 Op = CommuteVectorShuffle(SVOp, DAG);
6428 SVOp = cast<ShuffleVectorSDNode>(Op);
6429 V1 = SVOp->getOperand(0);
6430 V2 = SVOp->getOperand(1);
6431 std::swap(V1IsSplat, V2IsSplat);
6432 std::swap(V1IsUndef, V2IsUndef);
6436 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6437 // Shuffling low element of v1 into undef, just return v1.
6440 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6441 // the instruction selector will not match, so get a canonical MOVL with
6442 // swapped operands to undo the commute.
6443 return getMOVL(DAG, dl, VT, V2, V1);
6446 if (X86::isUNPCKLMask(SVOp))
6447 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6449 if (X86::isUNPCKHMask(SVOp))
6450 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6453 // Normalize mask so all entries that point to V2 points to its first
6454 // element then try to match unpck{h|l} again. If match, return a
6455 // new vector_shuffle with the corrected mask.
6456 SDValue NewMask = NormalizeMask(SVOp, DAG);
6457 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6458 if (NSVOp != SVOp) {
6459 if (X86::isUNPCKLMask(NSVOp, true)) {
6461 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6468 // Commute is back and try unpck* again.
6469 // FIXME: this seems wrong.
6470 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6471 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6473 if (X86::isUNPCKLMask(NewSVOp))
6474 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6476 if (X86::isUNPCKHMask(NewSVOp))
6477 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6480 // Normalize the node to match x86 shuffle ops if needed
6481 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6482 return CommuteVectorShuffle(SVOp, DAG);
6484 // The checks below are all present in isShuffleMaskLegal, but they are
6485 // inlined here right now to enable us to directly emit target specific
6486 // nodes, and remove one by one until they don't return Op anymore.
6487 SmallVector<int, 16> M;
6490 if (isPALIGNRMask(M, VT, HasSSSE3))
6491 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6492 X86::getShufflePALIGNRImmediate(SVOp),
6495 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6496 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6497 if (VT == MVT::v2f64)
6498 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6499 if (VT == MVT::v2i64)
6500 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6503 if (isPSHUFHWMask(M, VT))
6504 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6505 X86::getShufflePSHUFHWImmediate(SVOp),
6508 if (isPSHUFLWMask(M, VT))
6509 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6510 X86::getShufflePSHUFLWImmediate(SVOp),
6513 if (isSHUFPMask(M, VT)) {
6514 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6515 if (VT == MVT::v4f32 || VT == MVT::v4i32)
6516 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
6518 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6519 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
6523 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6524 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6525 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6526 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6528 //===--------------------------------------------------------------------===//
6529 // Generate target specific nodes for 128 or 256-bit shuffles only
6530 // supported in the AVX instruction set.
6533 // Handle VPERMILPS* permutations
6534 if (isVPERMILPSMask(M, VT, Subtarget))
6535 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6536 getShuffleVPERMILPSImmediate(SVOp), DAG);
6538 // Handle VPERMILPD* permutations
6539 if (isVPERMILPDMask(M, VT, Subtarget))
6540 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6541 getShuffleVPERMILPDImmediate(SVOp), DAG);
6543 // Handle VPERM2F128 permutations
6544 if (isVPERM2F128Mask(M, VT, Subtarget))
6545 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6546 getShuffleVPERM2F128Immediate(SVOp), DAG);
6548 //===--------------------------------------------------------------------===//
6549 // Since no target specific shuffle was selected for this generic one,
6550 // lower it into other known shuffles. FIXME: this isn't true yet, but
6551 // this is the plan.
6554 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6555 if (VT == MVT::v8i16) {
6556 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6557 if (NewOp.getNode())
6561 if (VT == MVT::v16i8) {
6562 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6563 if (NewOp.getNode())
6567 // Handle all 128-bit wide vectors with 4 elements, and match them with
6568 // several different shuffle types.
6569 if (NumElems == 4 && VT.getSizeInBits() == 128)
6570 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6572 // Handle general 256-bit shuffles
6573 if (VT.is256BitVector())
6574 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6580 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6581 SelectionDAG &DAG) const {
6582 EVT VT = Op.getValueType();
6583 DebugLoc dl = Op.getDebugLoc();
6585 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6588 if (VT.getSizeInBits() == 8) {
6589 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6590 Op.getOperand(0), Op.getOperand(1));
6591 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6592 DAG.getValueType(VT));
6593 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6594 } else if (VT.getSizeInBits() == 16) {
6595 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6596 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6598 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6599 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6600 DAG.getNode(ISD::BITCAST, dl,
6604 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6605 Op.getOperand(0), Op.getOperand(1));
6606 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6607 DAG.getValueType(VT));
6608 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6609 } else if (VT == MVT::f32) {
6610 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6611 // the result back to FR32 register. It's only worth matching if the
6612 // result has a single use which is a store or a bitcast to i32. And in
6613 // the case of a store, it's not worth it if the index is a constant 0,
6614 // because a MOVSSmr can be used instead, which is smaller and faster.
6615 if (!Op.hasOneUse())
6617 SDNode *User = *Op.getNode()->use_begin();
6618 if ((User->getOpcode() != ISD::STORE ||
6619 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6620 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6621 (User->getOpcode() != ISD::BITCAST ||
6622 User->getValueType(0) != MVT::i32))
6624 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6625 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6628 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6629 } else if (VT == MVT::i32) {
6630 // ExtractPS works with constant index.
6631 if (isa<ConstantSDNode>(Op.getOperand(1)))
6639 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6640 SelectionDAG &DAG) const {
6641 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6644 SDValue Vec = Op.getOperand(0);
6645 EVT VecVT = Vec.getValueType();
6647 // If this is a 256-bit vector result, first extract the 128-bit vector and
6648 // then extract the element from the 128-bit vector.
6649 if (VecVT.getSizeInBits() == 256) {
6650 DebugLoc dl = Op.getNode()->getDebugLoc();
6651 unsigned NumElems = VecVT.getVectorNumElements();
6652 SDValue Idx = Op.getOperand(1);
6653 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6655 // Get the 128-bit vector.
6656 bool Upper = IdxVal >= NumElems/2;
6657 Vec = Extract128BitVector(Vec,
6658 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6660 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6661 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6664 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6666 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6667 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6672 EVT VT = Op.getValueType();
6673 DebugLoc dl = Op.getDebugLoc();
6674 // TODO: handle v16i8.
6675 if (VT.getSizeInBits() == 16) {
6676 SDValue Vec = Op.getOperand(0);
6677 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6679 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6680 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6681 DAG.getNode(ISD::BITCAST, dl,
6684 // Transform it so it match pextrw which produces a 32-bit result.
6685 EVT EltVT = MVT::i32;
6686 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6687 Op.getOperand(0), Op.getOperand(1));
6688 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6689 DAG.getValueType(VT));
6690 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6691 } else if (VT.getSizeInBits() == 32) {
6692 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6696 // SHUFPS the element to the lowest double word, then movss.
6697 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6698 EVT VVT = Op.getOperand(0).getValueType();
6699 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6700 DAG.getUNDEF(VVT), Mask);
6701 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6702 DAG.getIntPtrConstant(0));
6703 } else if (VT.getSizeInBits() == 64) {
6704 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6705 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6706 // to match extract_elt for f64.
6707 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6711 // UNPCKHPD the element to the lowest double word, then movsd.
6712 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6713 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6714 int Mask[2] = { 1, -1 };
6715 EVT VVT = Op.getOperand(0).getValueType();
6716 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6717 DAG.getUNDEF(VVT), Mask);
6718 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6719 DAG.getIntPtrConstant(0));
6726 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6727 SelectionDAG &DAG) const {
6728 EVT VT = Op.getValueType();
6729 EVT EltVT = VT.getVectorElementType();
6730 DebugLoc dl = Op.getDebugLoc();
6732 SDValue N0 = Op.getOperand(0);
6733 SDValue N1 = Op.getOperand(1);
6734 SDValue N2 = Op.getOperand(2);
6736 if (VT.getSizeInBits() == 256)
6739 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6740 isa<ConstantSDNode>(N2)) {
6742 if (VT == MVT::v8i16)
6743 Opc = X86ISD::PINSRW;
6744 else if (VT == MVT::v16i8)
6745 Opc = X86ISD::PINSRB;
6747 Opc = X86ISD::PINSRB;
6749 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6751 if (N1.getValueType() != MVT::i32)
6752 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6753 if (N2.getValueType() != MVT::i32)
6754 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6755 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6756 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6757 // Bits [7:6] of the constant are the source select. This will always be
6758 // zero here. The DAG Combiner may combine an extract_elt index into these
6759 // bits. For example (insert (extract, 3), 2) could be matched by putting
6760 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6761 // Bits [5:4] of the constant are the destination select. This is the
6762 // value of the incoming immediate.
6763 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6764 // combine either bitwise AND or insert of float 0.0 to set these bits.
6765 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6766 // Create this as a scalar to vector..
6767 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6768 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6769 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6770 // PINSR* works with constant index.
6777 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6778 EVT VT = Op.getValueType();
6779 EVT EltVT = VT.getVectorElementType();
6781 DebugLoc dl = Op.getDebugLoc();
6782 SDValue N0 = Op.getOperand(0);
6783 SDValue N1 = Op.getOperand(1);
6784 SDValue N2 = Op.getOperand(2);
6786 // If this is a 256-bit vector result, first extract the 128-bit vector,
6787 // insert the element into the extracted half and then place it back.
6788 if (VT.getSizeInBits() == 256) {
6789 if (!isa<ConstantSDNode>(N2))
6792 // Get the desired 128-bit vector half.
6793 unsigned NumElems = VT.getVectorNumElements();
6794 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6795 bool Upper = IdxVal >= NumElems/2;
6796 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6797 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6799 // Insert the element into the desired half.
6800 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6801 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6803 // Insert the changed part back to the 256-bit vector
6804 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6807 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
6808 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6810 if (EltVT == MVT::i8)
6813 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6814 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6815 // as its second argument.
6816 if (N1.getValueType() != MVT::i32)
6817 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6818 if (N2.getValueType() != MVT::i32)
6819 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6820 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6826 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6827 LLVMContext *Context = DAG.getContext();
6828 DebugLoc dl = Op.getDebugLoc();
6829 EVT OpVT = Op.getValueType();
6831 // If this is a 256-bit vector result, first insert into a 128-bit
6832 // vector and then insert into the 256-bit vector.
6833 if (OpVT.getSizeInBits() > 128) {
6834 // Insert into a 128-bit vector.
6835 EVT VT128 = EVT::getVectorVT(*Context,
6836 OpVT.getVectorElementType(),
6837 OpVT.getVectorNumElements() / 2);
6839 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6841 // Insert the 128-bit vector.
6842 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6843 DAG.getConstant(0, MVT::i32),
6847 if (Op.getValueType() == MVT::v1i64 &&
6848 Op.getOperand(0).getValueType() == MVT::i64)
6849 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6851 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6852 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6853 "Expected an SSE type!");
6854 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6855 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6858 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6859 // a simple subregister reference or explicit instructions to grab
6860 // upper bits of a vector.
6862 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6863 if (Subtarget->hasAVX()) {
6864 DebugLoc dl = Op.getNode()->getDebugLoc();
6865 SDValue Vec = Op.getNode()->getOperand(0);
6866 SDValue Idx = Op.getNode()->getOperand(1);
6868 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6869 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6870 return Extract128BitVector(Vec, Idx, DAG, dl);
6876 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6877 // simple superregister reference or explicit instructions to insert
6878 // the upper bits of a vector.
6880 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6881 if (Subtarget->hasAVX()) {
6882 DebugLoc dl = Op.getNode()->getDebugLoc();
6883 SDValue Vec = Op.getNode()->getOperand(0);
6884 SDValue SubVec = Op.getNode()->getOperand(1);
6885 SDValue Idx = Op.getNode()->getOperand(2);
6887 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6888 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6889 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6895 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6896 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6897 // one of the above mentioned nodes. It has to be wrapped because otherwise
6898 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6899 // be used to form addressing mode. These wrapped nodes will be selected
6902 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6903 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6905 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6907 unsigned char OpFlag = 0;
6908 unsigned WrapperKind = X86ISD::Wrapper;
6909 CodeModel::Model M = getTargetMachine().getCodeModel();
6911 if (Subtarget->isPICStyleRIPRel() &&
6912 (M == CodeModel::Small || M == CodeModel::Kernel))
6913 WrapperKind = X86ISD::WrapperRIP;
6914 else if (Subtarget->isPICStyleGOT())
6915 OpFlag = X86II::MO_GOTOFF;
6916 else if (Subtarget->isPICStyleStubPIC())
6917 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6919 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6921 CP->getOffset(), OpFlag);
6922 DebugLoc DL = CP->getDebugLoc();
6923 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6924 // With PIC, the address is actually $g + Offset.
6926 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6927 DAG.getNode(X86ISD::GlobalBaseReg,
6928 DebugLoc(), getPointerTy()),
6935 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6936 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6938 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6940 unsigned char OpFlag = 0;
6941 unsigned WrapperKind = X86ISD::Wrapper;
6942 CodeModel::Model M = getTargetMachine().getCodeModel();
6944 if (Subtarget->isPICStyleRIPRel() &&
6945 (M == CodeModel::Small || M == CodeModel::Kernel))
6946 WrapperKind = X86ISD::WrapperRIP;
6947 else if (Subtarget->isPICStyleGOT())
6948 OpFlag = X86II::MO_GOTOFF;
6949 else if (Subtarget->isPICStyleStubPIC())
6950 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6952 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
6954 DebugLoc DL = JT->getDebugLoc();
6955 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6957 // With PIC, the address is actually $g + Offset.
6959 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6960 DAG.getNode(X86ISD::GlobalBaseReg,
6961 DebugLoc(), getPointerTy()),
6968 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
6969 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
6971 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6973 unsigned char OpFlag = 0;
6974 unsigned WrapperKind = X86ISD::Wrapper;
6975 CodeModel::Model M = getTargetMachine().getCodeModel();
6977 if (Subtarget->isPICStyleRIPRel() &&
6978 (M == CodeModel::Small || M == CodeModel::Kernel)) {
6979 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
6980 OpFlag = X86II::MO_GOTPCREL;
6981 WrapperKind = X86ISD::WrapperRIP;
6982 } else if (Subtarget->isPICStyleGOT()) {
6983 OpFlag = X86II::MO_GOT;
6984 } else if (Subtarget->isPICStyleStubPIC()) {
6985 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
6986 } else if (Subtarget->isPICStyleStubNoDynamic()) {
6987 OpFlag = X86II::MO_DARWIN_NONLAZY;
6990 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
6992 DebugLoc DL = Op.getDebugLoc();
6993 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6996 // With PIC, the address is actually $g + Offset.
6997 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
6998 !Subtarget->is64Bit()) {
6999 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7000 DAG.getNode(X86ISD::GlobalBaseReg,
7001 DebugLoc(), getPointerTy()),
7005 // For symbols that require a load from a stub to get the address, emit the
7007 if (isGlobalStubReference(OpFlag))
7008 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7009 MachinePointerInfo::getGOT(), false, false, 0);
7015 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7016 // Create the TargetBlockAddressAddress node.
7017 unsigned char OpFlags =
7018 Subtarget->ClassifyBlockAddressReference();
7019 CodeModel::Model M = getTargetMachine().getCodeModel();
7020 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7021 DebugLoc dl = Op.getDebugLoc();
7022 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7023 /*isTarget=*/true, OpFlags);
7025 if (Subtarget->isPICStyleRIPRel() &&
7026 (M == CodeModel::Small || M == CodeModel::Kernel))
7027 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7029 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7031 // With PIC, the address is actually $g + Offset.
7032 if (isGlobalRelativeToPICBase(OpFlags)) {
7033 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7034 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7042 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7044 SelectionDAG &DAG) const {
7045 // Create the TargetGlobalAddress node, folding in the constant
7046 // offset if it is legal.
7047 unsigned char OpFlags =
7048 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7049 CodeModel::Model M = getTargetMachine().getCodeModel();
7051 if (OpFlags == X86II::MO_NO_FLAG &&
7052 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7053 // A direct static reference to a global.
7054 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7057 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7060 if (Subtarget->isPICStyleRIPRel() &&
7061 (M == CodeModel::Small || M == CodeModel::Kernel))
7062 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7064 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7066 // With PIC, the address is actually $g + Offset.
7067 if (isGlobalRelativeToPICBase(OpFlags)) {
7068 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7069 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7073 // For globals that require a load from a stub to get the address, emit the
7075 if (isGlobalStubReference(OpFlags))
7076 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7077 MachinePointerInfo::getGOT(), false, false, 0);
7079 // If there was a non-zero offset that we didn't fold, create an explicit
7082 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7083 DAG.getConstant(Offset, getPointerTy()));
7089 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7090 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7091 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7092 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7096 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7097 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7098 unsigned char OperandFlags) {
7099 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7100 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7101 DebugLoc dl = GA->getDebugLoc();
7102 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7103 GA->getValueType(0),
7107 SDValue Ops[] = { Chain, TGA, *InFlag };
7108 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7110 SDValue Ops[] = { Chain, TGA };
7111 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7114 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7115 MFI->setAdjustsStack(true);
7117 SDValue Flag = Chain.getValue(1);
7118 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7121 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7123 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7126 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7127 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7128 DAG.getNode(X86ISD::GlobalBaseReg,
7129 DebugLoc(), PtrVT), InFlag);
7130 InFlag = Chain.getValue(1);
7132 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7135 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7137 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7139 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7140 X86::RAX, X86II::MO_TLSGD);
7143 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7144 // "local exec" model.
7145 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7146 const EVT PtrVT, TLSModel::Model model,
7148 DebugLoc dl = GA->getDebugLoc();
7150 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7151 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7152 is64Bit ? 257 : 256));
7154 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7155 DAG.getIntPtrConstant(0),
7156 MachinePointerInfo(Ptr), false, false, 0);
7158 unsigned char OperandFlags = 0;
7159 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7161 unsigned WrapperKind = X86ISD::Wrapper;
7162 if (model == TLSModel::LocalExec) {
7163 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7164 } else if (is64Bit) {
7165 assert(model == TLSModel::InitialExec);
7166 OperandFlags = X86II::MO_GOTTPOFF;
7167 WrapperKind = X86ISD::WrapperRIP;
7169 assert(model == TLSModel::InitialExec);
7170 OperandFlags = X86II::MO_INDNTPOFF;
7173 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7175 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7176 GA->getValueType(0),
7177 GA->getOffset(), OperandFlags);
7178 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7180 if (model == TLSModel::InitialExec)
7181 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7182 MachinePointerInfo::getGOT(), false, false, 0);
7184 // The address of the thread local variable is the add of the thread
7185 // pointer with the offset of the variable.
7186 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7190 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7192 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7193 const GlobalValue *GV = GA->getGlobal();
7195 if (Subtarget->isTargetELF()) {
7196 // TODO: implement the "local dynamic" model
7197 // TODO: implement the "initial exec"model for pic executables
7199 // If GV is an alias then use the aliasee for determining
7200 // thread-localness.
7201 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7202 GV = GA->resolveAliasedGlobal(false);
7204 TLSModel::Model model
7205 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7208 case TLSModel::GeneralDynamic:
7209 case TLSModel::LocalDynamic: // not implemented
7210 if (Subtarget->is64Bit())
7211 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7212 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7214 case TLSModel::InitialExec:
7215 case TLSModel::LocalExec:
7216 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7217 Subtarget->is64Bit());
7219 } else if (Subtarget->isTargetDarwin()) {
7220 // Darwin only has one model of TLS. Lower to that.
7221 unsigned char OpFlag = 0;
7222 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7223 X86ISD::WrapperRIP : X86ISD::Wrapper;
7225 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7227 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7228 !Subtarget->is64Bit();
7230 OpFlag = X86II::MO_TLVP_PIC_BASE;
7232 OpFlag = X86II::MO_TLVP;
7233 DebugLoc DL = Op.getDebugLoc();
7234 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7235 GA->getValueType(0),
7236 GA->getOffset(), OpFlag);
7237 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7239 // With PIC32, the address is actually $g + Offset.
7241 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7242 DAG.getNode(X86ISD::GlobalBaseReg,
7243 DebugLoc(), getPointerTy()),
7246 // Lowering the machine isd will make sure everything is in the right
7248 SDValue Chain = DAG.getEntryNode();
7249 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7250 SDValue Args[] = { Chain, Offset };
7251 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7253 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7254 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7255 MFI->setAdjustsStack(true);
7257 // And our return value (tls address) is in the standard call return value
7259 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7260 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7264 "TLS not implemented for this target.");
7266 llvm_unreachable("Unreachable");
7271 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7272 /// take a 2 x i32 value to shift plus a shift amount.
7273 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7274 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7275 EVT VT = Op.getValueType();
7276 unsigned VTBits = VT.getSizeInBits();
7277 DebugLoc dl = Op.getDebugLoc();
7278 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7279 SDValue ShOpLo = Op.getOperand(0);
7280 SDValue ShOpHi = Op.getOperand(1);
7281 SDValue ShAmt = Op.getOperand(2);
7282 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7283 DAG.getConstant(VTBits - 1, MVT::i8))
7284 : DAG.getConstant(0, VT);
7287 if (Op.getOpcode() == ISD::SHL_PARTS) {
7288 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7289 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7291 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7292 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7295 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7296 DAG.getConstant(VTBits, MVT::i8));
7297 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7298 AndNode, DAG.getConstant(0, MVT::i8));
7301 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7302 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7303 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7305 if (Op.getOpcode() == ISD::SHL_PARTS) {
7306 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7307 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7309 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7310 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7313 SDValue Ops[2] = { Lo, Hi };
7314 return DAG.getMergeValues(Ops, 2, dl);
7317 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7318 SelectionDAG &DAG) const {
7319 EVT SrcVT = Op.getOperand(0).getValueType();
7321 if (SrcVT.isVector())
7324 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7325 "Unknown SINT_TO_FP to lower!");
7327 // These are really Legal; return the operand so the caller accepts it as
7329 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7331 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7332 Subtarget->is64Bit()) {
7336 DebugLoc dl = Op.getDebugLoc();
7337 unsigned Size = SrcVT.getSizeInBits()/8;
7338 MachineFunction &MF = DAG.getMachineFunction();
7339 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7340 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7341 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7343 MachinePointerInfo::getFixedStack(SSFI),
7345 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7348 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7350 SelectionDAG &DAG) const {
7352 DebugLoc DL = Op.getDebugLoc();
7354 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7356 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7358 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7360 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7362 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7363 MachineMemOperand *MMO;
7365 int SSFI = FI->getIndex();
7367 DAG.getMachineFunction()
7368 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7369 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7371 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7372 StackSlot = StackSlot.getOperand(1);
7374 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7375 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7377 Tys, Ops, array_lengthof(Ops),
7381 Chain = Result.getValue(1);
7382 SDValue InFlag = Result.getValue(2);
7384 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7385 // shouldn't be necessary except that RFP cannot be live across
7386 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7387 MachineFunction &MF = DAG.getMachineFunction();
7388 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7389 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7390 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7391 Tys = DAG.getVTList(MVT::Other);
7393 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7395 MachineMemOperand *MMO =
7396 DAG.getMachineFunction()
7397 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7398 MachineMemOperand::MOStore, SSFISize, SSFISize);
7400 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7401 Ops, array_lengthof(Ops),
7402 Op.getValueType(), MMO);
7403 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7404 MachinePointerInfo::getFixedStack(SSFI),
7411 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7412 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7413 SelectionDAG &DAG) const {
7414 // This algorithm is not obvious. Here it is in C code, more or less:
7416 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7417 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7418 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7420 // Copy ints to xmm registers.
7421 __m128i xh = _mm_cvtsi32_si128( hi );
7422 __m128i xl = _mm_cvtsi32_si128( lo );
7424 // Combine into low half of a single xmm register.
7425 __m128i x = _mm_unpacklo_epi32( xh, xl );
7429 // Merge in appropriate exponents to give the integer bits the right
7431 x = _mm_unpacklo_epi32( x, exp );
7433 // Subtract away the biases to deal with the IEEE-754 double precision
7435 d = _mm_sub_pd( (__m128d) x, bias );
7437 // All conversions up to here are exact. The correctly rounded result is
7438 // calculated using the current rounding mode using the following
7440 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7441 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7442 // store doesn't really need to be here (except
7443 // maybe to zero the other double)
7448 DebugLoc dl = Op.getDebugLoc();
7449 LLVMContext *Context = DAG.getContext();
7451 // Build some magic constants.
7452 std::vector<Constant*> CV0;
7453 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7454 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7455 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7456 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7457 Constant *C0 = ConstantVector::get(CV0);
7458 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7460 std::vector<Constant*> CV1;
7462 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7464 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7465 Constant *C1 = ConstantVector::get(CV1);
7466 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7468 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7469 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7471 DAG.getIntPtrConstant(1)));
7472 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7473 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7475 DAG.getIntPtrConstant(0)));
7476 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7477 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7478 MachinePointerInfo::getConstantPool(),
7480 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7481 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7482 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7483 MachinePointerInfo::getConstantPool(),
7485 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7487 // Add the halves; easiest way is to swap them into another reg first.
7488 int ShufMask[2] = { 1, -1 };
7489 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7490 DAG.getUNDEF(MVT::v2f64), ShufMask);
7491 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7492 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7493 DAG.getIntPtrConstant(0));
7496 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7497 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7498 SelectionDAG &DAG) const {
7499 DebugLoc dl = Op.getDebugLoc();
7500 // FP constant to bias correct the final result.
7501 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7504 // Load the 32-bit value into an XMM register.
7505 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7508 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7509 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7510 DAG.getIntPtrConstant(0));
7512 // Or the load with the bias.
7513 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7514 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7515 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7517 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7518 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7519 MVT::v2f64, Bias)));
7520 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7521 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7522 DAG.getIntPtrConstant(0));
7524 // Subtract the bias.
7525 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7527 // Handle final rounding.
7528 EVT DestVT = Op.getValueType();
7530 if (DestVT.bitsLT(MVT::f64)) {
7531 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7532 DAG.getIntPtrConstant(0));
7533 } else if (DestVT.bitsGT(MVT::f64)) {
7534 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7537 // Handle final rounding.
7541 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7542 SelectionDAG &DAG) const {
7543 SDValue N0 = Op.getOperand(0);
7544 DebugLoc dl = Op.getDebugLoc();
7546 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7547 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7548 // the optimization here.
7549 if (DAG.SignBitIsZero(N0))
7550 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7552 EVT SrcVT = N0.getValueType();
7553 EVT DstVT = Op.getValueType();
7554 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7555 return LowerUINT_TO_FP_i64(Op, DAG);
7556 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7557 return LowerUINT_TO_FP_i32(Op, DAG);
7559 // Make a 64-bit buffer, and use it to build an FILD.
7560 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7561 if (SrcVT == MVT::i32) {
7562 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7563 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7564 getPointerTy(), StackSlot, WordOff);
7565 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7566 StackSlot, MachinePointerInfo(),
7568 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7569 OffsetSlot, MachinePointerInfo(),
7571 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7575 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7576 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7577 StackSlot, MachinePointerInfo(),
7579 // For i64 source, we need to add the appropriate power of 2 if the input
7580 // was negative. This is the same as the optimization in
7581 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7582 // we must be careful to do the computation in x87 extended precision, not
7583 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7584 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7585 MachineMemOperand *MMO =
7586 DAG.getMachineFunction()
7587 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7588 MachineMemOperand::MOLoad, 8, 8);
7590 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7591 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7592 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7595 APInt FF(32, 0x5F800000ULL);
7597 // Check whether the sign bit is set.
7598 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7599 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7602 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7603 SDValue FudgePtr = DAG.getConstantPool(
7604 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7607 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7608 SDValue Zero = DAG.getIntPtrConstant(0);
7609 SDValue Four = DAG.getIntPtrConstant(4);
7610 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7612 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7614 // Load the value out, extending it from f32 to f80.
7615 // FIXME: Avoid the extend by constructing the right constant pool?
7616 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7617 FudgePtr, MachinePointerInfo::getConstantPool(),
7618 MVT::f32, false, false, 4);
7619 // Extend everything to 80 bits to force it to be done on x87.
7620 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7621 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7624 std::pair<SDValue,SDValue> X86TargetLowering::
7625 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7626 DebugLoc DL = Op.getDebugLoc();
7628 EVT DstTy = Op.getValueType();
7631 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7635 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7636 DstTy.getSimpleVT() >= MVT::i16 &&
7637 "Unknown FP_TO_SINT to lower!");
7639 // These are really Legal.
7640 if (DstTy == MVT::i32 &&
7641 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7642 return std::make_pair(SDValue(), SDValue());
7643 if (Subtarget->is64Bit() &&
7644 DstTy == MVT::i64 &&
7645 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7646 return std::make_pair(SDValue(), SDValue());
7648 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7650 MachineFunction &MF = DAG.getMachineFunction();
7651 unsigned MemSize = DstTy.getSizeInBits()/8;
7652 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7653 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7658 switch (DstTy.getSimpleVT().SimpleTy) {
7659 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7660 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7661 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7662 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7665 SDValue Chain = DAG.getEntryNode();
7666 SDValue Value = Op.getOperand(0);
7667 EVT TheVT = Op.getOperand(0).getValueType();
7668 if (isScalarFPTypeInSSEReg(TheVT)) {
7669 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7670 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7671 MachinePointerInfo::getFixedStack(SSFI),
7673 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7675 Chain, StackSlot, DAG.getValueType(TheVT)
7678 MachineMemOperand *MMO =
7679 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7680 MachineMemOperand::MOLoad, MemSize, MemSize);
7681 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7683 Chain = Value.getValue(1);
7684 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7685 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7688 MachineMemOperand *MMO =
7689 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7690 MachineMemOperand::MOStore, MemSize, MemSize);
7692 // Build the FP_TO_INT*_IN_MEM
7693 SDValue Ops[] = { Chain, Value, StackSlot };
7694 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7695 Ops, 3, DstTy, MMO);
7697 return std::make_pair(FIST, StackSlot);
7700 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7701 SelectionDAG &DAG) const {
7702 if (Op.getValueType().isVector())
7705 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7706 SDValue FIST = Vals.first, StackSlot = Vals.second;
7707 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7708 if (FIST.getNode() == 0) return Op;
7711 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7712 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7715 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7716 SelectionDAG &DAG) const {
7717 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7718 SDValue FIST = Vals.first, StackSlot = Vals.second;
7719 assert(FIST.getNode() && "Unexpected failure");
7722 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7723 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7726 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7727 SelectionDAG &DAG) const {
7728 LLVMContext *Context = DAG.getContext();
7729 DebugLoc dl = Op.getDebugLoc();
7730 EVT VT = Op.getValueType();
7733 EltVT = VT.getVectorElementType();
7734 std::vector<Constant*> CV;
7735 if (EltVT == MVT::f64) {
7736 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7740 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7746 Constant *C = ConstantVector::get(CV);
7747 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7748 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7749 MachinePointerInfo::getConstantPool(),
7751 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7754 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7755 LLVMContext *Context = DAG.getContext();
7756 DebugLoc dl = Op.getDebugLoc();
7757 EVT VT = Op.getValueType();
7760 EltVT = VT.getVectorElementType();
7761 std::vector<Constant*> CV;
7762 if (EltVT == MVT::f64) {
7763 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7767 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7773 Constant *C = ConstantVector::get(CV);
7774 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7775 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7776 MachinePointerInfo::getConstantPool(),
7778 if (VT.isVector()) {
7779 return DAG.getNode(ISD::BITCAST, dl, VT,
7780 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
7781 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7783 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
7785 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7789 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7790 LLVMContext *Context = DAG.getContext();
7791 SDValue Op0 = Op.getOperand(0);
7792 SDValue Op1 = Op.getOperand(1);
7793 DebugLoc dl = Op.getDebugLoc();
7794 EVT VT = Op.getValueType();
7795 EVT SrcVT = Op1.getValueType();
7797 // If second operand is smaller, extend it first.
7798 if (SrcVT.bitsLT(VT)) {
7799 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7802 // And if it is bigger, shrink it first.
7803 if (SrcVT.bitsGT(VT)) {
7804 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7808 // At this point the operands and the result should have the same
7809 // type, and that won't be f80 since that is not custom lowered.
7811 // First get the sign bit of second operand.
7812 std::vector<Constant*> CV;
7813 if (SrcVT == MVT::f64) {
7814 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7815 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7817 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7818 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7819 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7820 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7822 Constant *C = ConstantVector::get(CV);
7823 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7824 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7825 MachinePointerInfo::getConstantPool(),
7827 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7829 // Shift sign bit right or left if the two operands have different types.
7830 if (SrcVT.bitsGT(VT)) {
7831 // Op0 is MVT::f32, Op1 is MVT::f64.
7832 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7833 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7834 DAG.getConstant(32, MVT::i32));
7835 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7836 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7837 DAG.getIntPtrConstant(0));
7840 // Clear first operand sign bit.
7842 if (VT == MVT::f64) {
7843 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7844 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7846 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7847 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7848 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7849 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7851 C = ConstantVector::get(CV);
7852 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7853 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7854 MachinePointerInfo::getConstantPool(),
7856 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7858 // Or the value with the sign bit.
7859 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7862 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7863 SDValue N0 = Op.getOperand(0);
7864 DebugLoc dl = Op.getDebugLoc();
7865 EVT VT = Op.getValueType();
7867 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7868 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7869 DAG.getConstant(1, VT));
7870 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7873 /// Emit nodes that will be selected as "test Op0,Op0", or something
7875 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7876 SelectionDAG &DAG) const {
7877 DebugLoc dl = Op.getDebugLoc();
7879 // CF and OF aren't always set the way we want. Determine which
7880 // of these we need.
7881 bool NeedCF = false;
7882 bool NeedOF = false;
7885 case X86::COND_A: case X86::COND_AE:
7886 case X86::COND_B: case X86::COND_BE:
7889 case X86::COND_G: case X86::COND_GE:
7890 case X86::COND_L: case X86::COND_LE:
7891 case X86::COND_O: case X86::COND_NO:
7896 // See if we can use the EFLAGS value from the operand instead of
7897 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
7898 // we prove that the arithmetic won't overflow, we can't use OF or CF.
7899 if (Op.getResNo() != 0 || NeedOF || NeedCF)
7900 // Emit a CMP with 0, which is the TEST pattern.
7901 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7902 DAG.getConstant(0, Op.getValueType()));
7904 unsigned Opcode = 0;
7905 unsigned NumOperands = 0;
7906 switch (Op.getNode()->getOpcode()) {
7908 // Due to an isel shortcoming, be conservative if this add is likely to be
7909 // selected as part of a load-modify-store instruction. When the root node
7910 // in a match is a store, isel doesn't know how to remap non-chain non-flag
7911 // uses of other nodes in the match, such as the ADD in this case. This
7912 // leads to the ADD being left around and reselected, with the result being
7913 // two adds in the output. Alas, even if none our users are stores, that
7914 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
7915 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
7916 // climbing the DAG back to the root, and it doesn't seem to be worth the
7918 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7919 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7920 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
7923 if (ConstantSDNode *C =
7924 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
7925 // An add of one will be selected as an INC.
7926 if (C->getAPIntValue() == 1) {
7927 Opcode = X86ISD::INC;
7932 // An add of negative one (subtract of one) will be selected as a DEC.
7933 if (C->getAPIntValue().isAllOnesValue()) {
7934 Opcode = X86ISD::DEC;
7940 // Otherwise use a regular EFLAGS-setting add.
7941 Opcode = X86ISD::ADD;
7945 // If the primary and result isn't used, don't bother using X86ISD::AND,
7946 // because a TEST instruction will be better.
7947 bool NonFlagUse = false;
7948 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7949 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
7951 unsigned UOpNo = UI.getOperandNo();
7952 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
7953 // Look pass truncate.
7954 UOpNo = User->use_begin().getOperandNo();
7955 User = *User->use_begin();
7958 if (User->getOpcode() != ISD::BRCOND &&
7959 User->getOpcode() != ISD::SETCC &&
7960 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
7973 // Due to the ISEL shortcoming noted above, be conservative if this op is
7974 // likely to be selected as part of a load-modify-store instruction.
7975 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7976 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7977 if (UI->getOpcode() == ISD::STORE)
7980 // Otherwise use a regular EFLAGS-setting instruction.
7981 switch (Op.getNode()->getOpcode()) {
7982 default: llvm_unreachable("unexpected operator!");
7983 case ISD::SUB: Opcode = X86ISD::SUB; break;
7984 case ISD::OR: Opcode = X86ISD::OR; break;
7985 case ISD::XOR: Opcode = X86ISD::XOR; break;
7986 case ISD::AND: Opcode = X86ISD::AND; break;
7998 return SDValue(Op.getNode(), 1);
8005 // Emit a CMP with 0, which is the TEST pattern.
8006 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8007 DAG.getConstant(0, Op.getValueType()));
8009 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8010 SmallVector<SDValue, 4> Ops;
8011 for (unsigned i = 0; i != NumOperands; ++i)
8012 Ops.push_back(Op.getOperand(i));
8014 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8015 DAG.ReplaceAllUsesWith(Op, New);
8016 return SDValue(New.getNode(), 1);
8019 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8021 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8022 SelectionDAG &DAG) const {
8023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8024 if (C->getAPIntValue() == 0)
8025 return EmitTest(Op0, X86CC, DAG);
8027 DebugLoc dl = Op0.getDebugLoc();
8028 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8031 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8032 /// if it's possible.
8033 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8034 DebugLoc dl, SelectionDAG &DAG) const {
8035 SDValue Op0 = And.getOperand(0);
8036 SDValue Op1 = And.getOperand(1);
8037 if (Op0.getOpcode() == ISD::TRUNCATE)
8038 Op0 = Op0.getOperand(0);
8039 if (Op1.getOpcode() == ISD::TRUNCATE)
8040 Op1 = Op1.getOperand(0);
8043 if (Op1.getOpcode() == ISD::SHL)
8044 std::swap(Op0, Op1);
8045 if (Op0.getOpcode() == ISD::SHL) {
8046 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8047 if (And00C->getZExtValue() == 1) {
8048 // If we looked past a truncate, check that it's only truncating away
8050 unsigned BitWidth = Op0.getValueSizeInBits();
8051 unsigned AndBitWidth = And.getValueSizeInBits();
8052 if (BitWidth > AndBitWidth) {
8053 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8054 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8055 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8059 RHS = Op0.getOperand(1);
8061 } else if (Op1.getOpcode() == ISD::Constant) {
8062 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8063 SDValue AndLHS = Op0;
8064 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8065 LHS = AndLHS.getOperand(0);
8066 RHS = AndLHS.getOperand(1);
8070 if (LHS.getNode()) {
8071 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8072 // instruction. Since the shift amount is in-range-or-undefined, we know
8073 // that doing a bittest on the i32 value is ok. We extend to i32 because
8074 // the encoding for the i16 version is larger than the i32 version.
8075 // Also promote i16 to i32 for performance / code size reason.
8076 if (LHS.getValueType() == MVT::i8 ||
8077 LHS.getValueType() == MVT::i16)
8078 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8080 // If the operand types disagree, extend the shift amount to match. Since
8081 // BT ignores high bits (like shifts) we can use anyextend.
8082 if (LHS.getValueType() != RHS.getValueType())
8083 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8085 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8086 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8087 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8088 DAG.getConstant(Cond, MVT::i8), BT);
8094 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8095 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8096 SDValue Op0 = Op.getOperand(0);
8097 SDValue Op1 = Op.getOperand(1);
8098 DebugLoc dl = Op.getDebugLoc();
8099 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8101 // Optimize to BT if possible.
8102 // Lower (X & (1 << N)) == 0 to BT(X, N).
8103 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8104 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8105 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8106 Op1.getOpcode() == ISD::Constant &&
8107 cast<ConstantSDNode>(Op1)->isNullValue() &&
8108 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8109 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8110 if (NewSetCC.getNode())
8114 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8116 if (Op1.getOpcode() == ISD::Constant &&
8117 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8118 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8119 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8121 // If the input is a setcc, then reuse the input setcc or use a new one with
8122 // the inverted condition.
8123 if (Op0.getOpcode() == X86ISD::SETCC) {
8124 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8125 bool Invert = (CC == ISD::SETNE) ^
8126 cast<ConstantSDNode>(Op1)->isNullValue();
8127 if (!Invert) return Op0;
8129 CCode = X86::GetOppositeBranchCondition(CCode);
8130 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8131 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8135 bool isFP = Op1.getValueType().isFloatingPoint();
8136 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8137 if (X86CC == X86::COND_INVALID)
8140 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8141 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8142 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8145 // Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8146 // ones, and then concatenate the result back.
8147 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
8148 EVT VT = Op.getValueType();
8150 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC &&
8151 "Unsupported value type for operation");
8153 int NumElems = VT.getVectorNumElements();
8154 DebugLoc dl = Op.getDebugLoc();
8155 SDValue CC = Op.getOperand(2);
8156 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8157 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8159 // Extract the LHS vectors
8160 SDValue LHS = Op.getOperand(0);
8161 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8162 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8164 // Extract the RHS vectors
8165 SDValue RHS = Op.getOperand(1);
8166 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8167 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8169 // Issue the operation on the smaller types and concatenate the result back
8170 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8171 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8172 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8173 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8174 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8178 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8180 SDValue Op0 = Op.getOperand(0);
8181 SDValue Op1 = Op.getOperand(1);
8182 SDValue CC = Op.getOperand(2);
8183 EVT VT = Op.getValueType();
8184 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8185 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8186 DebugLoc dl = Op.getDebugLoc();
8190 EVT EltVT = Op0.getValueType().getVectorElementType();
8191 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8193 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8196 switch (SetCCOpcode) {
8199 case ISD::SETEQ: SSECC = 0; break;
8201 case ISD::SETGT: Swap = true; // Fallthrough
8203 case ISD::SETOLT: SSECC = 1; break;
8205 case ISD::SETGE: Swap = true; // Fallthrough
8207 case ISD::SETOLE: SSECC = 2; break;
8208 case ISD::SETUO: SSECC = 3; break;
8210 case ISD::SETNE: SSECC = 4; break;
8211 case ISD::SETULE: Swap = true;
8212 case ISD::SETUGE: SSECC = 5; break;
8213 case ISD::SETULT: Swap = true;
8214 case ISD::SETUGT: SSECC = 6; break;
8215 case ISD::SETO: SSECC = 7; break;
8218 std::swap(Op0, Op1);
8220 // In the two special cases we can't handle, emit two comparisons.
8222 if (SetCCOpcode == ISD::SETUEQ) {
8224 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8225 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8226 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8228 else if (SetCCOpcode == ISD::SETONE) {
8230 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8231 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8232 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8234 llvm_unreachable("Illegal FP comparison");
8236 // Handle all other FP comparisons here.
8237 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8240 // Break 256-bit integer vector compare into smaller ones.
8241 if (!isFP && VT.getSizeInBits() == 256)
8242 return Lower256IntVETCC(Op, DAG);
8244 // We are handling one of the integer comparisons here. Since SSE only has
8245 // GT and EQ comparisons for integer, swapping operands and multiple
8246 // operations may be required for some comparisons.
8247 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8248 bool Swap = false, Invert = false, FlipSigns = false;
8250 switch (VT.getSimpleVT().SimpleTy) {
8252 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8253 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8254 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8255 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8258 switch (SetCCOpcode) {
8260 case ISD::SETNE: Invert = true;
8261 case ISD::SETEQ: Opc = EQOpc; break;
8262 case ISD::SETLT: Swap = true;
8263 case ISD::SETGT: Opc = GTOpc; break;
8264 case ISD::SETGE: Swap = true;
8265 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8266 case ISD::SETULT: Swap = true;
8267 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8268 case ISD::SETUGE: Swap = true;
8269 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8272 std::swap(Op0, Op1);
8274 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8275 // bits of the inputs before performing those operations.
8277 EVT EltVT = VT.getVectorElementType();
8278 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8280 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8281 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8283 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8284 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8287 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8289 // If the logical-not of the result is required, perform that now.
8291 Result = DAG.getNOT(dl, Result, VT);
8296 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8297 static bool isX86LogicalCmp(SDValue Op) {
8298 unsigned Opc = Op.getNode()->getOpcode();
8299 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8301 if (Op.getResNo() == 1 &&
8302 (Opc == X86ISD::ADD ||
8303 Opc == X86ISD::SUB ||
8304 Opc == X86ISD::ADC ||
8305 Opc == X86ISD::SBB ||
8306 Opc == X86ISD::SMUL ||
8307 Opc == X86ISD::UMUL ||
8308 Opc == X86ISD::INC ||
8309 Opc == X86ISD::DEC ||
8310 Opc == X86ISD::OR ||
8311 Opc == X86ISD::XOR ||
8312 Opc == X86ISD::AND))
8315 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8321 static bool isZero(SDValue V) {
8322 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8323 return C && C->isNullValue();
8326 static bool isAllOnes(SDValue V) {
8327 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8328 return C && C->isAllOnesValue();
8331 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8332 bool addTest = true;
8333 SDValue Cond = Op.getOperand(0);
8334 SDValue Op1 = Op.getOperand(1);
8335 SDValue Op2 = Op.getOperand(2);
8336 DebugLoc DL = Op.getDebugLoc();
8339 if (Cond.getOpcode() == ISD::SETCC) {
8340 SDValue NewCond = LowerSETCC(Cond, DAG);
8341 if (NewCond.getNode())
8345 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8346 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8347 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8348 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8349 if (Cond.getOpcode() == X86ISD::SETCC &&
8350 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8351 isZero(Cond.getOperand(1).getOperand(1))) {
8352 SDValue Cmp = Cond.getOperand(1);
8354 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8356 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8357 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8358 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8360 SDValue CmpOp0 = Cmp.getOperand(0);
8361 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8362 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8364 SDValue Res = // Res = 0 or -1.
8365 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8366 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8368 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8369 Res = DAG.getNOT(DL, Res, Res.getValueType());
8371 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8372 if (N2C == 0 || !N2C->isNullValue())
8373 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8378 // Look past (and (setcc_carry (cmp ...)), 1).
8379 if (Cond.getOpcode() == ISD::AND &&
8380 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8381 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8382 if (C && C->getAPIntValue() == 1)
8383 Cond = Cond.getOperand(0);
8386 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8387 // setting operand in place of the X86ISD::SETCC.
8388 if (Cond.getOpcode() == X86ISD::SETCC ||
8389 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8390 CC = Cond.getOperand(0);
8392 SDValue Cmp = Cond.getOperand(1);
8393 unsigned Opc = Cmp.getOpcode();
8394 EVT VT = Op.getValueType();
8396 bool IllegalFPCMov = false;
8397 if (VT.isFloatingPoint() && !VT.isVector() &&
8398 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8399 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8401 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8402 Opc == X86ISD::BT) { // FIXME
8409 // Look pass the truncate.
8410 if (Cond.getOpcode() == ISD::TRUNCATE)
8411 Cond = Cond.getOperand(0);
8413 // We know the result of AND is compared against zero. Try to match
8415 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8416 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8417 if (NewSetCC.getNode()) {
8418 CC = NewSetCC.getOperand(0);
8419 Cond = NewSetCC.getOperand(1);
8426 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8427 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8430 // a < b ? -1 : 0 -> RES = ~setcc_carry
8431 // a < b ? 0 : -1 -> RES = setcc_carry
8432 // a >= b ? -1 : 0 -> RES = setcc_carry
8433 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8434 if (Cond.getOpcode() == X86ISD::CMP) {
8435 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8437 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8438 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8439 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8440 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8441 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8442 return DAG.getNOT(DL, Res, Res.getValueType());
8447 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8448 // condition is true.
8449 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8450 SDValue Ops[] = { Op2, Op1, CC, Cond };
8451 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8454 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8455 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8456 // from the AND / OR.
8457 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8458 Opc = Op.getOpcode();
8459 if (Opc != ISD::OR && Opc != ISD::AND)
8461 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8462 Op.getOperand(0).hasOneUse() &&
8463 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8464 Op.getOperand(1).hasOneUse());
8467 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8468 // 1 and that the SETCC node has a single use.
8469 static bool isXor1OfSetCC(SDValue Op) {
8470 if (Op.getOpcode() != ISD::XOR)
8472 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8473 if (N1C && N1C->getAPIntValue() == 1) {
8474 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8475 Op.getOperand(0).hasOneUse();
8480 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8481 bool addTest = true;
8482 SDValue Chain = Op.getOperand(0);
8483 SDValue Cond = Op.getOperand(1);
8484 SDValue Dest = Op.getOperand(2);
8485 DebugLoc dl = Op.getDebugLoc();
8488 if (Cond.getOpcode() == ISD::SETCC) {
8489 SDValue NewCond = LowerSETCC(Cond, DAG);
8490 if (NewCond.getNode())
8494 // FIXME: LowerXALUO doesn't handle these!!
8495 else if (Cond.getOpcode() == X86ISD::ADD ||
8496 Cond.getOpcode() == X86ISD::SUB ||
8497 Cond.getOpcode() == X86ISD::SMUL ||
8498 Cond.getOpcode() == X86ISD::UMUL)
8499 Cond = LowerXALUO(Cond, DAG);
8502 // Look pass (and (setcc_carry (cmp ...)), 1).
8503 if (Cond.getOpcode() == ISD::AND &&
8504 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8505 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8506 if (C && C->getAPIntValue() == 1)
8507 Cond = Cond.getOperand(0);
8510 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8511 // setting operand in place of the X86ISD::SETCC.
8512 if (Cond.getOpcode() == X86ISD::SETCC ||
8513 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8514 CC = Cond.getOperand(0);
8516 SDValue Cmp = Cond.getOperand(1);
8517 unsigned Opc = Cmp.getOpcode();
8518 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8519 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8523 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8527 // These can only come from an arithmetic instruction with overflow,
8528 // e.g. SADDO, UADDO.
8529 Cond = Cond.getNode()->getOperand(1);
8536 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8537 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8538 if (CondOpc == ISD::OR) {
8539 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8540 // two branches instead of an explicit OR instruction with a
8542 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8543 isX86LogicalCmp(Cmp)) {
8544 CC = Cond.getOperand(0).getOperand(0);
8545 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8546 Chain, Dest, CC, Cmp);
8547 CC = Cond.getOperand(1).getOperand(0);
8551 } else { // ISD::AND
8552 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8553 // two branches instead of an explicit AND instruction with a
8554 // separate test. However, we only do this if this block doesn't
8555 // have a fall-through edge, because this requires an explicit
8556 // jmp when the condition is false.
8557 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8558 isX86LogicalCmp(Cmp) &&
8559 Op.getNode()->hasOneUse()) {
8560 X86::CondCode CCode =
8561 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8562 CCode = X86::GetOppositeBranchCondition(CCode);
8563 CC = DAG.getConstant(CCode, MVT::i8);
8564 SDNode *User = *Op.getNode()->use_begin();
8565 // Look for an unconditional branch following this conditional branch.
8566 // We need this because we need to reverse the successors in order
8567 // to implement FCMP_OEQ.
8568 if (User->getOpcode() == ISD::BR) {
8569 SDValue FalseBB = User->getOperand(1);
8571 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8572 assert(NewBR == User);
8576 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8577 Chain, Dest, CC, Cmp);
8578 X86::CondCode CCode =
8579 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8580 CCode = X86::GetOppositeBranchCondition(CCode);
8581 CC = DAG.getConstant(CCode, MVT::i8);
8587 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8588 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8589 // It should be transformed during dag combiner except when the condition
8590 // is set by a arithmetics with overflow node.
8591 X86::CondCode CCode =
8592 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8593 CCode = X86::GetOppositeBranchCondition(CCode);
8594 CC = DAG.getConstant(CCode, MVT::i8);
8595 Cond = Cond.getOperand(0).getOperand(1);
8601 // Look pass the truncate.
8602 if (Cond.getOpcode() == ISD::TRUNCATE)
8603 Cond = Cond.getOperand(0);
8605 // We know the result of AND is compared against zero. Try to match
8607 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8608 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8609 if (NewSetCC.getNode()) {
8610 CC = NewSetCC.getOperand(0);
8611 Cond = NewSetCC.getOperand(1);
8618 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8619 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8621 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8622 Chain, Dest, CC, Cond);
8626 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8627 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8628 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8629 // that the guard pages used by the OS virtual memory manager are allocated in
8630 // correct sequence.
8632 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8633 SelectionDAG &DAG) const {
8634 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
8635 "This should be used only on Windows targets");
8636 assert(!Subtarget->isTargetEnvMacho());
8637 DebugLoc dl = Op.getDebugLoc();
8640 SDValue Chain = Op.getOperand(0);
8641 SDValue Size = Op.getOperand(1);
8642 // FIXME: Ensure alignment here
8646 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
8647 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8649 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8650 Flag = Chain.getValue(1);
8652 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8654 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8655 Flag = Chain.getValue(1);
8657 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8659 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8660 return DAG.getMergeValues(Ops1, 2, dl);
8663 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8664 MachineFunction &MF = DAG.getMachineFunction();
8665 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8667 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8668 DebugLoc DL = Op.getDebugLoc();
8670 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8671 // vastart just stores the address of the VarArgsFrameIndex slot into the
8672 // memory location argument.
8673 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8675 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8676 MachinePointerInfo(SV), false, false, 0);
8680 // gp_offset (0 - 6 * 8)
8681 // fp_offset (48 - 48 + 8 * 16)
8682 // overflow_arg_area (point to parameters coming in memory).
8684 SmallVector<SDValue, 8> MemOps;
8685 SDValue FIN = Op.getOperand(1);
8687 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8688 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8690 FIN, MachinePointerInfo(SV), false, false, 0);
8691 MemOps.push_back(Store);
8694 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8695 FIN, DAG.getIntPtrConstant(4));
8696 Store = DAG.getStore(Op.getOperand(0), DL,
8697 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8699 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8700 MemOps.push_back(Store);
8702 // Store ptr to overflow_arg_area
8703 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8704 FIN, DAG.getIntPtrConstant(4));
8705 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8707 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8708 MachinePointerInfo(SV, 8),
8710 MemOps.push_back(Store);
8712 // Store ptr to reg_save_area.
8713 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8714 FIN, DAG.getIntPtrConstant(8));
8715 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8717 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8718 MachinePointerInfo(SV, 16), false, false, 0);
8719 MemOps.push_back(Store);
8720 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8721 &MemOps[0], MemOps.size());
8724 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8725 assert(Subtarget->is64Bit() &&
8726 "LowerVAARG only handles 64-bit va_arg!");
8727 assert((Subtarget->isTargetLinux() ||
8728 Subtarget->isTargetDarwin()) &&
8729 "Unhandled target in LowerVAARG");
8730 assert(Op.getNode()->getNumOperands() == 4);
8731 SDValue Chain = Op.getOperand(0);
8732 SDValue SrcPtr = Op.getOperand(1);
8733 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8734 unsigned Align = Op.getConstantOperandVal(3);
8735 DebugLoc dl = Op.getDebugLoc();
8737 EVT ArgVT = Op.getNode()->getValueType(0);
8738 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8739 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8742 // Decide which area this value should be read from.
8743 // TODO: Implement the AMD64 ABI in its entirety. This simple
8744 // selection mechanism works only for the basic types.
8745 if (ArgVT == MVT::f80) {
8746 llvm_unreachable("va_arg for f80 not yet implemented");
8747 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8748 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8749 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8750 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8752 llvm_unreachable("Unhandled argument type in LowerVAARG");
8756 // Sanity Check: Make sure using fp_offset makes sense.
8757 assert(!UseSoftFloat &&
8758 !(DAG.getMachineFunction()
8759 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
8760 Subtarget->hasXMM());
8763 // Insert VAARG_64 node into the DAG
8764 // VAARG_64 returns two values: Variable Argument Address, Chain
8765 SmallVector<SDValue, 11> InstOps;
8766 InstOps.push_back(Chain);
8767 InstOps.push_back(SrcPtr);
8768 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
8769 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
8770 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
8771 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
8772 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
8773 VTs, &InstOps[0], InstOps.size(),
8775 MachinePointerInfo(SV),
8780 Chain = VAARG.getValue(1);
8782 // Load the next argument and return it
8783 return DAG.getLoad(ArgVT, dl,
8786 MachinePointerInfo(),
8790 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
8791 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
8792 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
8793 SDValue Chain = Op.getOperand(0);
8794 SDValue DstPtr = Op.getOperand(1);
8795 SDValue SrcPtr = Op.getOperand(2);
8796 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
8797 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8798 DebugLoc DL = Op.getDebugLoc();
8800 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
8801 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
8803 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
8807 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
8808 DebugLoc dl = Op.getDebugLoc();
8809 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8811 default: return SDValue(); // Don't custom lower most intrinsics.
8812 // Comparison intrinsics.
8813 case Intrinsic::x86_sse_comieq_ss:
8814 case Intrinsic::x86_sse_comilt_ss:
8815 case Intrinsic::x86_sse_comile_ss:
8816 case Intrinsic::x86_sse_comigt_ss:
8817 case Intrinsic::x86_sse_comige_ss:
8818 case Intrinsic::x86_sse_comineq_ss:
8819 case Intrinsic::x86_sse_ucomieq_ss:
8820 case Intrinsic::x86_sse_ucomilt_ss:
8821 case Intrinsic::x86_sse_ucomile_ss:
8822 case Intrinsic::x86_sse_ucomigt_ss:
8823 case Intrinsic::x86_sse_ucomige_ss:
8824 case Intrinsic::x86_sse_ucomineq_ss:
8825 case Intrinsic::x86_sse2_comieq_sd:
8826 case Intrinsic::x86_sse2_comilt_sd:
8827 case Intrinsic::x86_sse2_comile_sd:
8828 case Intrinsic::x86_sse2_comigt_sd:
8829 case Intrinsic::x86_sse2_comige_sd:
8830 case Intrinsic::x86_sse2_comineq_sd:
8831 case Intrinsic::x86_sse2_ucomieq_sd:
8832 case Intrinsic::x86_sse2_ucomilt_sd:
8833 case Intrinsic::x86_sse2_ucomile_sd:
8834 case Intrinsic::x86_sse2_ucomigt_sd:
8835 case Intrinsic::x86_sse2_ucomige_sd:
8836 case Intrinsic::x86_sse2_ucomineq_sd: {
8838 ISD::CondCode CC = ISD::SETCC_INVALID;
8841 case Intrinsic::x86_sse_comieq_ss:
8842 case Intrinsic::x86_sse2_comieq_sd:
8846 case Intrinsic::x86_sse_comilt_ss:
8847 case Intrinsic::x86_sse2_comilt_sd:
8851 case Intrinsic::x86_sse_comile_ss:
8852 case Intrinsic::x86_sse2_comile_sd:
8856 case Intrinsic::x86_sse_comigt_ss:
8857 case Intrinsic::x86_sse2_comigt_sd:
8861 case Intrinsic::x86_sse_comige_ss:
8862 case Intrinsic::x86_sse2_comige_sd:
8866 case Intrinsic::x86_sse_comineq_ss:
8867 case Intrinsic::x86_sse2_comineq_sd:
8871 case Intrinsic::x86_sse_ucomieq_ss:
8872 case Intrinsic::x86_sse2_ucomieq_sd:
8873 Opc = X86ISD::UCOMI;
8876 case Intrinsic::x86_sse_ucomilt_ss:
8877 case Intrinsic::x86_sse2_ucomilt_sd:
8878 Opc = X86ISD::UCOMI;
8881 case Intrinsic::x86_sse_ucomile_ss:
8882 case Intrinsic::x86_sse2_ucomile_sd:
8883 Opc = X86ISD::UCOMI;
8886 case Intrinsic::x86_sse_ucomigt_ss:
8887 case Intrinsic::x86_sse2_ucomigt_sd:
8888 Opc = X86ISD::UCOMI;
8891 case Intrinsic::x86_sse_ucomige_ss:
8892 case Intrinsic::x86_sse2_ucomige_sd:
8893 Opc = X86ISD::UCOMI;
8896 case Intrinsic::x86_sse_ucomineq_ss:
8897 case Intrinsic::x86_sse2_ucomineq_sd:
8898 Opc = X86ISD::UCOMI;
8903 SDValue LHS = Op.getOperand(1);
8904 SDValue RHS = Op.getOperand(2);
8905 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
8906 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
8907 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
8908 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8909 DAG.getConstant(X86CC, MVT::i8), Cond);
8910 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8912 // ptest and testp intrinsics. The intrinsic these come from are designed to
8913 // return an integer value, not just an instruction so lower it to the ptest
8914 // or testp pattern and a setcc for the result.
8915 case Intrinsic::x86_sse41_ptestz:
8916 case Intrinsic::x86_sse41_ptestc:
8917 case Intrinsic::x86_sse41_ptestnzc:
8918 case Intrinsic::x86_avx_ptestz_256:
8919 case Intrinsic::x86_avx_ptestc_256:
8920 case Intrinsic::x86_avx_ptestnzc_256:
8921 case Intrinsic::x86_avx_vtestz_ps:
8922 case Intrinsic::x86_avx_vtestc_ps:
8923 case Intrinsic::x86_avx_vtestnzc_ps:
8924 case Intrinsic::x86_avx_vtestz_pd:
8925 case Intrinsic::x86_avx_vtestc_pd:
8926 case Intrinsic::x86_avx_vtestnzc_pd:
8927 case Intrinsic::x86_avx_vtestz_ps_256:
8928 case Intrinsic::x86_avx_vtestc_ps_256:
8929 case Intrinsic::x86_avx_vtestnzc_ps_256:
8930 case Intrinsic::x86_avx_vtestz_pd_256:
8931 case Intrinsic::x86_avx_vtestc_pd_256:
8932 case Intrinsic::x86_avx_vtestnzc_pd_256: {
8933 bool IsTestPacked = false;
8936 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
8937 case Intrinsic::x86_avx_vtestz_ps:
8938 case Intrinsic::x86_avx_vtestz_pd:
8939 case Intrinsic::x86_avx_vtestz_ps_256:
8940 case Intrinsic::x86_avx_vtestz_pd_256:
8941 IsTestPacked = true; // Fallthrough
8942 case Intrinsic::x86_sse41_ptestz:
8943 case Intrinsic::x86_avx_ptestz_256:
8945 X86CC = X86::COND_E;
8947 case Intrinsic::x86_avx_vtestc_ps:
8948 case Intrinsic::x86_avx_vtestc_pd:
8949 case Intrinsic::x86_avx_vtestc_ps_256:
8950 case Intrinsic::x86_avx_vtestc_pd_256:
8951 IsTestPacked = true; // Fallthrough
8952 case Intrinsic::x86_sse41_ptestc:
8953 case Intrinsic::x86_avx_ptestc_256:
8955 X86CC = X86::COND_B;
8957 case Intrinsic::x86_avx_vtestnzc_ps:
8958 case Intrinsic::x86_avx_vtestnzc_pd:
8959 case Intrinsic::x86_avx_vtestnzc_ps_256:
8960 case Intrinsic::x86_avx_vtestnzc_pd_256:
8961 IsTestPacked = true; // Fallthrough
8962 case Intrinsic::x86_sse41_ptestnzc:
8963 case Intrinsic::x86_avx_ptestnzc_256:
8965 X86CC = X86::COND_A;
8969 SDValue LHS = Op.getOperand(1);
8970 SDValue RHS = Op.getOperand(2);
8971 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
8972 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
8973 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
8974 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
8975 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8978 // Fix vector shift instructions where the last operand is a non-immediate
8980 case Intrinsic::x86_sse2_pslli_w:
8981 case Intrinsic::x86_sse2_pslli_d:
8982 case Intrinsic::x86_sse2_pslli_q:
8983 case Intrinsic::x86_sse2_psrli_w:
8984 case Intrinsic::x86_sse2_psrli_d:
8985 case Intrinsic::x86_sse2_psrli_q:
8986 case Intrinsic::x86_sse2_psrai_w:
8987 case Intrinsic::x86_sse2_psrai_d:
8988 case Intrinsic::x86_mmx_pslli_w:
8989 case Intrinsic::x86_mmx_pslli_d:
8990 case Intrinsic::x86_mmx_pslli_q:
8991 case Intrinsic::x86_mmx_psrli_w:
8992 case Intrinsic::x86_mmx_psrli_d:
8993 case Intrinsic::x86_mmx_psrli_q:
8994 case Intrinsic::x86_mmx_psrai_w:
8995 case Intrinsic::x86_mmx_psrai_d: {
8996 SDValue ShAmt = Op.getOperand(2);
8997 if (isa<ConstantSDNode>(ShAmt))
9000 unsigned NewIntNo = 0;
9001 EVT ShAmtVT = MVT::v4i32;
9003 case Intrinsic::x86_sse2_pslli_w:
9004 NewIntNo = Intrinsic::x86_sse2_psll_w;
9006 case Intrinsic::x86_sse2_pslli_d:
9007 NewIntNo = Intrinsic::x86_sse2_psll_d;
9009 case Intrinsic::x86_sse2_pslli_q:
9010 NewIntNo = Intrinsic::x86_sse2_psll_q;
9012 case Intrinsic::x86_sse2_psrli_w:
9013 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9015 case Intrinsic::x86_sse2_psrli_d:
9016 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9018 case Intrinsic::x86_sse2_psrli_q:
9019 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9021 case Intrinsic::x86_sse2_psrai_w:
9022 NewIntNo = Intrinsic::x86_sse2_psra_w;
9024 case Intrinsic::x86_sse2_psrai_d:
9025 NewIntNo = Intrinsic::x86_sse2_psra_d;
9028 ShAmtVT = MVT::v2i32;
9030 case Intrinsic::x86_mmx_pslli_w:
9031 NewIntNo = Intrinsic::x86_mmx_psll_w;
9033 case Intrinsic::x86_mmx_pslli_d:
9034 NewIntNo = Intrinsic::x86_mmx_psll_d;
9036 case Intrinsic::x86_mmx_pslli_q:
9037 NewIntNo = Intrinsic::x86_mmx_psll_q;
9039 case Intrinsic::x86_mmx_psrli_w:
9040 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9042 case Intrinsic::x86_mmx_psrli_d:
9043 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9045 case Intrinsic::x86_mmx_psrli_q:
9046 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9048 case Intrinsic::x86_mmx_psrai_w:
9049 NewIntNo = Intrinsic::x86_mmx_psra_w;
9051 case Intrinsic::x86_mmx_psrai_d:
9052 NewIntNo = Intrinsic::x86_mmx_psra_d;
9054 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9060 // The vector shift intrinsics with scalars uses 32b shift amounts but
9061 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9065 ShOps[1] = DAG.getConstant(0, MVT::i32);
9066 if (ShAmtVT == MVT::v4i32) {
9067 ShOps[2] = DAG.getUNDEF(MVT::i32);
9068 ShOps[3] = DAG.getUNDEF(MVT::i32);
9069 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9071 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9072 // FIXME this must be lowered to get rid of the invalid type.
9075 EVT VT = Op.getValueType();
9076 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9077 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9078 DAG.getConstant(NewIntNo, MVT::i32),
9079 Op.getOperand(1), ShAmt);
9084 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9085 SelectionDAG &DAG) const {
9086 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9087 MFI->setReturnAddressIsTaken(true);
9089 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9090 DebugLoc dl = Op.getDebugLoc();
9093 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9095 DAG.getConstant(TD->getPointerSize(),
9096 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9097 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9098 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9100 MachinePointerInfo(), false, false, 0);
9103 // Just load the return address.
9104 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9105 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9106 RetAddrFI, MachinePointerInfo(), false, false, 0);
9109 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9110 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9111 MFI->setFrameAddressIsTaken(true);
9113 EVT VT = Op.getValueType();
9114 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9115 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9116 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9117 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9119 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9120 MachinePointerInfo(),
9125 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9126 SelectionDAG &DAG) const {
9127 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9130 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9131 MachineFunction &MF = DAG.getMachineFunction();
9132 SDValue Chain = Op.getOperand(0);
9133 SDValue Offset = Op.getOperand(1);
9134 SDValue Handler = Op.getOperand(2);
9135 DebugLoc dl = Op.getDebugLoc();
9137 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9138 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9140 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9142 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9143 DAG.getIntPtrConstant(TD->getPointerSize()));
9144 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9145 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9147 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9148 MF.getRegInfo().addLiveOut(StoreAddrReg);
9150 return DAG.getNode(X86ISD::EH_RETURN, dl,
9152 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9155 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
9156 SelectionDAG &DAG) const {
9157 SDValue Root = Op.getOperand(0);
9158 SDValue Trmp = Op.getOperand(1); // trampoline
9159 SDValue FPtr = Op.getOperand(2); // nested function
9160 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9161 DebugLoc dl = Op.getDebugLoc();
9163 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9165 if (Subtarget->is64Bit()) {
9166 SDValue OutChains[6];
9168 // Large code-model.
9169 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9170 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9172 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9173 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9175 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9177 // Load the pointer to the nested function into R11.
9178 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9179 SDValue Addr = Trmp;
9180 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9181 Addr, MachinePointerInfo(TrmpAddr),
9184 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9185 DAG.getConstant(2, MVT::i64));
9186 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9187 MachinePointerInfo(TrmpAddr, 2),
9190 // Load the 'nest' parameter value into R10.
9191 // R10 is specified in X86CallingConv.td
9192 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9193 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9194 DAG.getConstant(10, MVT::i64));
9195 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9196 Addr, MachinePointerInfo(TrmpAddr, 10),
9199 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9200 DAG.getConstant(12, MVT::i64));
9201 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9202 MachinePointerInfo(TrmpAddr, 12),
9205 // Jump to the nested function.
9206 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9207 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9208 DAG.getConstant(20, MVT::i64));
9209 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9210 Addr, MachinePointerInfo(TrmpAddr, 20),
9213 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9214 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9215 DAG.getConstant(22, MVT::i64));
9216 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9217 MachinePointerInfo(TrmpAddr, 22),
9221 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
9222 return DAG.getMergeValues(Ops, 2, dl);
9224 const Function *Func =
9225 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9226 CallingConv::ID CC = Func->getCallingConv();
9231 llvm_unreachable("Unsupported calling convention");
9232 case CallingConv::C:
9233 case CallingConv::X86_StdCall: {
9234 // Pass 'nest' parameter in ECX.
9235 // Must be kept in sync with X86CallingConv.td
9238 // Check that ECX wasn't needed by an 'inreg' parameter.
9239 FunctionType *FTy = Func->getFunctionType();
9240 const AttrListPtr &Attrs = Func->getAttributes();
9242 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9243 unsigned InRegCount = 0;
9246 for (FunctionType::param_iterator I = FTy->param_begin(),
9247 E = FTy->param_end(); I != E; ++I, ++Idx)
9248 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9249 // FIXME: should only count parameters that are lowered to integers.
9250 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9252 if (InRegCount > 2) {
9253 report_fatal_error("Nest register in use - reduce number of inreg"
9259 case CallingConv::X86_FastCall:
9260 case CallingConv::X86_ThisCall:
9261 case CallingConv::Fast:
9262 // Pass 'nest' parameter in EAX.
9263 // Must be kept in sync with X86CallingConv.td
9268 SDValue OutChains[4];
9271 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9272 DAG.getConstant(10, MVT::i32));
9273 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9275 // This is storing the opcode for MOV32ri.
9276 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9277 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9278 OutChains[0] = DAG.getStore(Root, dl,
9279 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9280 Trmp, MachinePointerInfo(TrmpAddr),
9283 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9284 DAG.getConstant(1, MVT::i32));
9285 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9286 MachinePointerInfo(TrmpAddr, 1),
9289 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9290 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9291 DAG.getConstant(5, MVT::i32));
9292 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9293 MachinePointerInfo(TrmpAddr, 5),
9296 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9297 DAG.getConstant(6, MVT::i32));
9298 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9299 MachinePointerInfo(TrmpAddr, 6),
9303 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
9304 return DAG.getMergeValues(Ops, 2, dl);
9308 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9309 SelectionDAG &DAG) const {
9311 The rounding mode is in bits 11:10 of FPSR, and has the following
9318 FLT_ROUNDS, on the other hand, expects the following:
9325 To perform the conversion, we do:
9326 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9329 MachineFunction &MF = DAG.getMachineFunction();
9330 const TargetMachine &TM = MF.getTarget();
9331 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9332 unsigned StackAlignment = TFI.getStackAlignment();
9333 EVT VT = Op.getValueType();
9334 DebugLoc DL = Op.getDebugLoc();
9336 // Save FP Control Word to stack slot
9337 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9338 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9341 MachineMemOperand *MMO =
9342 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9343 MachineMemOperand::MOStore, 2, 2);
9345 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9346 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9347 DAG.getVTList(MVT::Other),
9348 Ops, 2, MVT::i16, MMO);
9350 // Load FP Control Word from stack slot
9351 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9352 MachinePointerInfo(), false, false, 0);
9354 // Transform as necessary
9356 DAG.getNode(ISD::SRL, DL, MVT::i16,
9357 DAG.getNode(ISD::AND, DL, MVT::i16,
9358 CWD, DAG.getConstant(0x800, MVT::i16)),
9359 DAG.getConstant(11, MVT::i8));
9361 DAG.getNode(ISD::SRL, DL, MVT::i16,
9362 DAG.getNode(ISD::AND, DL, MVT::i16,
9363 CWD, DAG.getConstant(0x400, MVT::i16)),
9364 DAG.getConstant(9, MVT::i8));
9367 DAG.getNode(ISD::AND, DL, MVT::i16,
9368 DAG.getNode(ISD::ADD, DL, MVT::i16,
9369 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9370 DAG.getConstant(1, MVT::i16)),
9371 DAG.getConstant(3, MVT::i16));
9374 return DAG.getNode((VT.getSizeInBits() < 16 ?
9375 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9378 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9379 EVT VT = Op.getValueType();
9381 unsigned NumBits = VT.getSizeInBits();
9382 DebugLoc dl = Op.getDebugLoc();
9384 Op = Op.getOperand(0);
9385 if (VT == MVT::i8) {
9386 // Zero extend to i32 since there is not an i8 bsr.
9388 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9391 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9392 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9393 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9395 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9398 DAG.getConstant(NumBits+NumBits-1, OpVT),
9399 DAG.getConstant(X86::COND_E, MVT::i8),
9402 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9404 // Finally xor with NumBits-1.
9405 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9408 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9412 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9413 EVT VT = Op.getValueType();
9415 unsigned NumBits = VT.getSizeInBits();
9416 DebugLoc dl = Op.getDebugLoc();
9418 Op = Op.getOperand(0);
9419 if (VT == MVT::i8) {
9421 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9424 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9425 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9426 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9428 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9431 DAG.getConstant(NumBits, OpVT),
9432 DAG.getConstant(X86::COND_E, MVT::i8),
9435 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9438 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9442 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9443 // ones, and then concatenate the result back.
9444 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9445 EVT VT = Op.getValueType();
9447 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9448 "Unsupported value type for operation");
9450 int NumElems = VT.getVectorNumElements();
9451 DebugLoc dl = Op.getDebugLoc();
9452 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9453 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9455 // Extract the LHS vectors
9456 SDValue LHS = Op.getOperand(0);
9457 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9458 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9460 // Extract the RHS vectors
9461 SDValue RHS = Op.getOperand(1);
9462 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9463 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9465 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9466 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9468 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9469 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9470 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9473 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9474 assert(Op.getValueType().getSizeInBits() == 256 &&
9475 Op.getValueType().isInteger() &&
9476 "Only handle AVX 256-bit vector integer operation");
9477 return Lower256IntArith(Op, DAG);
9480 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9481 assert(Op.getValueType().getSizeInBits() == 256 &&
9482 Op.getValueType().isInteger() &&
9483 "Only handle AVX 256-bit vector integer operation");
9484 return Lower256IntArith(Op, DAG);
9487 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9488 EVT VT = Op.getValueType();
9490 // Decompose 256-bit ops into smaller 128-bit ops.
9491 if (VT.getSizeInBits() == 256)
9492 return Lower256IntArith(Op, DAG);
9494 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9495 DebugLoc dl = Op.getDebugLoc();
9497 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9498 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9499 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9500 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9501 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9503 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9504 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9505 // return AloBlo + AloBhi + AhiBlo;
9507 SDValue A = Op.getOperand(0);
9508 SDValue B = Op.getOperand(1);
9510 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9511 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9512 A, DAG.getConstant(32, MVT::i32));
9513 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9514 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9515 B, DAG.getConstant(32, MVT::i32));
9516 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9517 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9519 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9520 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9522 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9523 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9525 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9526 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9527 AloBhi, DAG.getConstant(32, MVT::i32));
9528 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9529 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9530 AhiBlo, DAG.getConstant(32, MVT::i32));
9531 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9532 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9536 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9538 EVT VT = Op.getValueType();
9539 DebugLoc dl = Op.getDebugLoc();
9540 SDValue R = Op.getOperand(0);
9541 SDValue Amt = Op.getOperand(1);
9542 LLVMContext *Context = DAG.getContext();
9544 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9547 // Decompose 256-bit shifts into smaller 128-bit shifts.
9548 if (VT.getSizeInBits() == 256) {
9549 int NumElems = VT.getVectorNumElements();
9550 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9551 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9553 // Extract the two vectors
9554 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9555 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9558 // Recreate the shift amount vectors
9560 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9561 // Constant shift amount
9562 SmallVector<SDValue, 4> Amt1Csts;
9563 SmallVector<SDValue, 4> Amt2Csts;
9564 for (int i = 0; i < NumElems/2; ++i)
9565 Amt1Csts.push_back(Amt->getOperand(i));
9566 for (int i = NumElems/2; i < NumElems; ++i)
9567 Amt2Csts.push_back(Amt->getOperand(i));
9569 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9570 &Amt1Csts[0], NumElems/2);
9571 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9572 &Amt2Csts[0], NumElems/2);
9574 // Variable shift amount
9575 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9576 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9580 // Issue new vector shifts for the smaller types
9581 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9582 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9584 // Concatenate the result back
9585 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9588 // Optimize shl/srl/sra with constant shift amount.
9589 if (isSplatVector(Amt.getNode())) {
9590 SDValue SclrAmt = Amt->getOperand(0);
9591 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9592 uint64_t ShiftAmt = C->getZExtValue();
9594 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9595 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9596 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9597 R, DAG.getConstant(ShiftAmt, MVT::i32));
9599 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9600 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9601 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9602 R, DAG.getConstant(ShiftAmt, MVT::i32));
9604 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9605 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9606 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9607 R, DAG.getConstant(ShiftAmt, MVT::i32));
9609 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9610 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9611 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9612 R, DAG.getConstant(ShiftAmt, MVT::i32));
9614 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9615 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9616 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9617 R, DAG.getConstant(ShiftAmt, MVT::i32));
9619 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9620 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9621 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9622 R, DAG.getConstant(ShiftAmt, MVT::i32));
9624 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9625 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9626 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9627 R, DAG.getConstant(ShiftAmt, MVT::i32));
9629 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9630 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9631 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9632 R, DAG.getConstant(ShiftAmt, MVT::i32));
9636 // Lower SHL with variable shift amount.
9637 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9638 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9639 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9640 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9642 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9644 std::vector<Constant*> CV(4, CI);
9645 Constant *C = ConstantVector::get(CV);
9646 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9647 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9648 MachinePointerInfo::getConstantPool(),
9651 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9652 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9653 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9654 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9656 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9658 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9659 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9660 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9662 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9663 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9665 std::vector<Constant*> CVM1(16, CM1);
9666 std::vector<Constant*> CVM2(16, CM2);
9667 Constant *C = ConstantVector::get(CVM1);
9668 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9669 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9670 MachinePointerInfo::getConstantPool(),
9673 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9674 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9675 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9676 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9677 DAG.getConstant(4, MVT::i32));
9678 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9680 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9682 C = ConstantVector::get(CVM2);
9683 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9684 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9685 MachinePointerInfo::getConstantPool(),
9688 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9689 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9690 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9691 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9692 DAG.getConstant(2, MVT::i32));
9693 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9695 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9697 // return pblendv(r, r+r, a);
9698 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9699 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9705 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9706 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
9707 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9708 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9709 // has only one use.
9710 SDNode *N = Op.getNode();
9711 SDValue LHS = N->getOperand(0);
9712 SDValue RHS = N->getOperand(1);
9713 unsigned BaseOp = 0;
9715 DebugLoc DL = Op.getDebugLoc();
9716 switch (Op.getOpcode()) {
9717 default: llvm_unreachable("Unknown ovf instruction!");
9719 // A subtract of one will be selected as a INC. Note that INC doesn't
9720 // set CF, so we can't do this for UADDO.
9721 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9723 BaseOp = X86ISD::INC;
9727 BaseOp = X86ISD::ADD;
9731 BaseOp = X86ISD::ADD;
9735 // A subtract of one will be selected as a DEC. Note that DEC doesn't
9736 // set CF, so we can't do this for USUBO.
9737 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9739 BaseOp = X86ISD::DEC;
9743 BaseOp = X86ISD::SUB;
9747 BaseOp = X86ISD::SUB;
9751 BaseOp = X86ISD::SMUL;
9754 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
9755 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
9757 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
9760 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9761 DAG.getConstant(X86::COND_O, MVT::i32),
9762 SDValue(Sum.getNode(), 2));
9764 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9768 // Also sets EFLAGS.
9769 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
9770 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
9773 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
9774 DAG.getConstant(Cond, MVT::i32),
9775 SDValue(Sum.getNode(), 1));
9777 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9780 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
9781 DebugLoc dl = Op.getDebugLoc();
9782 SDNode* Node = Op.getNode();
9783 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
9784 EVT VT = Node->getValueType(0);
9786 if (Subtarget->hasSSE2() && VT.isVector()) {
9787 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
9788 ExtraVT.getScalarType().getSizeInBits();
9789 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
9791 unsigned SHLIntrinsicsID = 0;
9792 unsigned SRAIntrinsicsID = 0;
9793 switch (VT.getSimpleVT().SimpleTy) {
9797 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
9798 SRAIntrinsicsID = 0;
9802 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
9803 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
9807 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
9808 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
9813 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9814 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
9815 Node->getOperand(0), ShAmt);
9817 // In case of 1 bit sext, no need to shr
9818 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
9820 if (SRAIntrinsicsID) {
9821 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9822 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
9832 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
9833 DebugLoc dl = Op.getDebugLoc();
9835 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
9836 // There isn't any reason to disable it if the target processor supports it.
9837 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
9838 SDValue Chain = Op.getOperand(0);
9839 SDValue Zero = DAG.getConstant(0, MVT::i32);
9841 DAG.getRegister(X86::ESP, MVT::i32), // Base
9842 DAG.getTargetConstant(1, MVT::i8), // Scale
9843 DAG.getRegister(0, MVT::i32), // Index
9844 DAG.getTargetConstant(0, MVT::i32), // Disp
9845 DAG.getRegister(0, MVT::i32), // Segment.
9850 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9851 array_lengthof(Ops));
9852 return SDValue(Res, 0);
9855 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
9857 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9859 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9860 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
9861 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
9862 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
9864 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
9865 if (!Op1 && !Op2 && !Op3 && Op4)
9866 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
9868 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
9869 if (Op1 && !Op2 && !Op3 && !Op4)
9870 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
9872 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
9874 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9877 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
9878 SelectionDAG &DAG) const {
9879 DebugLoc dl = Op.getDebugLoc();
9880 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
9881 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
9882 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
9883 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
9885 // The only fence that needs an instruction is a sequentially-consistent
9886 // cross-thread fence.
9887 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
9888 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
9889 // no-sse2). There isn't any reason to disable it if the target processor
9891 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
9892 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9894 SDValue Chain = Op.getOperand(0);
9895 SDValue Zero = DAG.getConstant(0, MVT::i32);
9897 DAG.getRegister(X86::ESP, MVT::i32), // Base
9898 DAG.getTargetConstant(1, MVT::i8), // Scale
9899 DAG.getRegister(0, MVT::i32), // Index
9900 DAG.getTargetConstant(0, MVT::i32), // Disp
9901 DAG.getRegister(0, MVT::i32), // Segment.
9906 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9907 array_lengthof(Ops));
9908 return SDValue(Res, 0);
9911 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
9912 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9916 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
9917 EVT T = Op.getValueType();
9918 DebugLoc DL = Op.getDebugLoc();
9921 switch(T.getSimpleVT().SimpleTy) {
9923 assert(false && "Invalid value type!");
9924 case MVT::i8: Reg = X86::AL; size = 1; break;
9925 case MVT::i16: Reg = X86::AX; size = 2; break;
9926 case MVT::i32: Reg = X86::EAX; size = 4; break;
9928 assert(Subtarget->is64Bit() && "Node not type legal!");
9929 Reg = X86::RAX; size = 8;
9932 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
9933 Op.getOperand(2), SDValue());
9934 SDValue Ops[] = { cpIn.getValue(0),
9937 DAG.getTargetConstant(size, MVT::i8),
9939 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9940 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
9941 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
9944 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
9948 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
9949 SelectionDAG &DAG) const {
9950 assert(Subtarget->is64Bit() && "Result not type legalized?");
9951 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9952 SDValue TheChain = Op.getOperand(0);
9953 DebugLoc dl = Op.getDebugLoc();
9954 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
9955 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
9956 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
9958 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
9959 DAG.getConstant(32, MVT::i8));
9961 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
9964 return DAG.getMergeValues(Ops, 2, dl);
9967 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
9968 SelectionDAG &DAG) const {
9969 EVT SrcVT = Op.getOperand(0).getValueType();
9970 EVT DstVT = Op.getValueType();
9971 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
9972 Subtarget->hasMMX() && "Unexpected custom BITCAST");
9973 assert((DstVT == MVT::i64 ||
9974 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
9975 "Unexpected custom BITCAST");
9976 // i64 <=> MMX conversions are Legal.
9977 if (SrcVT==MVT::i64 && DstVT.isVector())
9979 if (DstVT==MVT::i64 && SrcVT.isVector())
9981 // MMX <=> MMX conversions are Legal.
9982 if (SrcVT.isVector() && DstVT.isVector())
9984 // All other conversions need to be expanded.
9988 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
9989 SDNode *Node = Op.getNode();
9990 DebugLoc dl = Node->getDebugLoc();
9991 EVT T = Node->getValueType(0);
9992 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
9993 DAG.getConstant(0, T), Node->getOperand(2));
9994 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
9995 cast<AtomicSDNode>(Node)->getMemoryVT(),
9996 Node->getOperand(0),
9997 Node->getOperand(1), negOp,
9998 cast<AtomicSDNode>(Node)->getSrcValue(),
9999 cast<AtomicSDNode>(Node)->getAlignment(),
10000 cast<AtomicSDNode>(Node)->getOrdering(),
10001 cast<AtomicSDNode>(Node)->getSynchScope());
10004 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10005 SDNode *Node = Op.getNode();
10006 DebugLoc dl = Node->getDebugLoc();
10007 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10009 // Convert seq_cst store -> xchg
10010 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10011 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10012 // (The only way to get a 16-byte store is cmpxchg16b)
10013 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10014 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10015 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10016 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10017 cast<AtomicSDNode>(Node)->getMemoryVT(),
10018 Node->getOperand(0),
10019 Node->getOperand(1), Node->getOperand(2),
10020 cast<AtomicSDNode>(Node)->getMemOperand(),
10021 cast<AtomicSDNode>(Node)->getOrdering(),
10022 cast<AtomicSDNode>(Node)->getSynchScope());
10023 return Swap.getValue(1);
10025 // Other atomic stores have a simple pattern.
10029 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10030 EVT VT = Op.getNode()->getValueType(0);
10032 // Let legalize expand this if it isn't a legal type yet.
10033 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10036 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10039 bool ExtraOp = false;
10040 switch (Op.getOpcode()) {
10041 default: assert(0 && "Invalid code");
10042 case ISD::ADDC: Opc = X86ISD::ADD; break;
10043 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10044 case ISD::SUBC: Opc = X86ISD::SUB; break;
10045 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10049 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10051 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10052 Op.getOperand(1), Op.getOperand(2));
10055 /// LowerOperation - Provide custom lowering hooks for some operations.
10057 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10058 switch (Op.getOpcode()) {
10059 default: llvm_unreachable("Should not custom lower this!");
10060 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10061 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10062 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10063 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10064 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10065 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10066 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10067 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10068 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10069 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10070 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10071 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10072 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10073 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10074 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10075 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10076 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10077 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10078 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10079 case ISD::SHL_PARTS:
10080 case ISD::SRA_PARTS:
10081 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10082 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10083 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10084 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10085 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10086 case ISD::FABS: return LowerFABS(Op, DAG);
10087 case ISD::FNEG: return LowerFNEG(Op, DAG);
10088 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10089 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10090 case ISD::SETCC: return LowerSETCC(Op, DAG);
10091 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
10092 case ISD::SELECT: return LowerSELECT(Op, DAG);
10093 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10094 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10095 case ISD::VASTART: return LowerVASTART(Op, DAG);
10096 case ISD::VAARG: return LowerVAARG(Op, DAG);
10097 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10098 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10099 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10100 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10101 case ISD::FRAME_TO_ARGS_OFFSET:
10102 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10103 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10104 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10105 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
10106 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10107 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10108 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10109 case ISD::MUL: return LowerMUL(Op, DAG);
10112 case ISD::SHL: return LowerShift(Op, DAG);
10118 case ISD::UMULO: return LowerXALUO(Op, DAG);
10119 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10120 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10124 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10125 case ISD::ADD: return LowerADD(Op, DAG);
10126 case ISD::SUB: return LowerSUB(Op, DAG);
10130 static void ReplaceATOMIC_LOAD(SDNode *Node,
10131 SmallVectorImpl<SDValue> &Results,
10132 SelectionDAG &DAG) {
10133 DebugLoc dl = Node->getDebugLoc();
10134 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10136 // Convert wide load -> cmpxchg8b/cmpxchg16b
10137 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10138 // (The only way to get a 16-byte load is cmpxchg16b)
10139 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10140 SDValue Zero = DAG.getConstant(0, cast<AtomicSDNode>(Node)->getMemoryVT());
10141 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
10142 cast<AtomicSDNode>(Node)->getMemoryVT(),
10143 Node->getOperand(0),
10144 Node->getOperand(1), Zero, Zero,
10145 cast<AtomicSDNode>(Node)->getMemOperand(),
10146 cast<AtomicSDNode>(Node)->getOrdering(),
10147 cast<AtomicSDNode>(Node)->getSynchScope());
10148 Results.push_back(Swap.getValue(0));
10149 Results.push_back(Swap.getValue(1));
10152 void X86TargetLowering::
10153 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10154 SelectionDAG &DAG, unsigned NewOp) const {
10155 EVT T = Node->getValueType(0);
10156 DebugLoc dl = Node->getDebugLoc();
10157 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10159 SDValue Chain = Node->getOperand(0);
10160 SDValue In1 = Node->getOperand(1);
10161 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10162 Node->getOperand(2), DAG.getIntPtrConstant(0));
10163 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10164 Node->getOperand(2), DAG.getIntPtrConstant(1));
10165 SDValue Ops[] = { Chain, In1, In2L, In2H };
10166 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10168 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10169 cast<MemSDNode>(Node)->getMemOperand());
10170 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10171 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10172 Results.push_back(Result.getValue(2));
10175 /// ReplaceNodeResults - Replace a node with an illegal result type
10176 /// with a new node built out of custom code.
10177 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10178 SmallVectorImpl<SDValue>&Results,
10179 SelectionDAG &DAG) const {
10180 DebugLoc dl = N->getDebugLoc();
10181 switch (N->getOpcode()) {
10183 assert(false && "Do not know how to custom type legalize this operation!");
10185 case ISD::SIGN_EXTEND_INREG:
10190 // We don't want to expand or promote these.
10192 case ISD::FP_TO_SINT: {
10193 std::pair<SDValue,SDValue> Vals =
10194 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10195 SDValue FIST = Vals.first, StackSlot = Vals.second;
10196 if (FIST.getNode() != 0) {
10197 EVT VT = N->getValueType(0);
10198 // Return a load from the stack slot.
10199 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10200 MachinePointerInfo(), false, false, 0));
10204 case ISD::READCYCLECOUNTER: {
10205 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10206 SDValue TheChain = N->getOperand(0);
10207 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10208 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10210 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10212 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10213 SDValue Ops[] = { eax, edx };
10214 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10215 Results.push_back(edx.getValue(1));
10218 case ISD::ATOMIC_CMP_SWAP: {
10219 EVT T = N->getValueType(0);
10220 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
10221 SDValue cpInL, cpInH;
10222 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
10223 DAG.getConstant(0, MVT::i32));
10224 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
10225 DAG.getConstant(1, MVT::i32));
10226 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
10227 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
10228 cpInL.getValue(1));
10229 SDValue swapInL, swapInH;
10230 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
10231 DAG.getConstant(0, MVT::i32));
10232 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
10233 DAG.getConstant(1, MVT::i32));
10234 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
10235 cpInH.getValue(1));
10236 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
10237 swapInL.getValue(1));
10238 SDValue Ops[] = { swapInH.getValue(0),
10240 swapInH.getValue(1) };
10241 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10242 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10243 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
10245 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
10246 MVT::i32, Result.getValue(1));
10247 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
10248 MVT::i32, cpOutL.getValue(2));
10249 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10250 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10251 Results.push_back(cpOutH.getValue(1));
10254 case ISD::ATOMIC_LOAD_ADD:
10255 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10257 case ISD::ATOMIC_LOAD_AND:
10258 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10260 case ISD::ATOMIC_LOAD_NAND:
10261 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10263 case ISD::ATOMIC_LOAD_OR:
10264 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10266 case ISD::ATOMIC_LOAD_SUB:
10267 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10269 case ISD::ATOMIC_LOAD_XOR:
10270 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10272 case ISD::ATOMIC_SWAP:
10273 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10275 case ISD::ATOMIC_LOAD:
10276 ReplaceATOMIC_LOAD(N, Results, DAG);
10280 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10282 default: return NULL;
10283 case X86ISD::BSF: return "X86ISD::BSF";
10284 case X86ISD::BSR: return "X86ISD::BSR";
10285 case X86ISD::SHLD: return "X86ISD::SHLD";
10286 case X86ISD::SHRD: return "X86ISD::SHRD";
10287 case X86ISD::FAND: return "X86ISD::FAND";
10288 case X86ISD::FOR: return "X86ISD::FOR";
10289 case X86ISD::FXOR: return "X86ISD::FXOR";
10290 case X86ISD::FSRL: return "X86ISD::FSRL";
10291 case X86ISD::FILD: return "X86ISD::FILD";
10292 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10293 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10294 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10295 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10296 case X86ISD::FLD: return "X86ISD::FLD";
10297 case X86ISD::FST: return "X86ISD::FST";
10298 case X86ISD::CALL: return "X86ISD::CALL";
10299 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10300 case X86ISD::BT: return "X86ISD::BT";
10301 case X86ISD::CMP: return "X86ISD::CMP";
10302 case X86ISD::COMI: return "X86ISD::COMI";
10303 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10304 case X86ISD::SETCC: return "X86ISD::SETCC";
10305 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10306 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10307 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10308 case X86ISD::CMOV: return "X86ISD::CMOV";
10309 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10310 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10311 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10312 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10313 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10314 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10315 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10316 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10317 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10318 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10319 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10320 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10321 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10322 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10323 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10324 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10325 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10326 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
10327 case X86ISD::FMAX: return "X86ISD::FMAX";
10328 case X86ISD::FMIN: return "X86ISD::FMIN";
10329 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10330 case X86ISD::FRCP: return "X86ISD::FRCP";
10331 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10332 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10333 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10334 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10335 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10336 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10337 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10338 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10339 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10340 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10341 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10342 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10343 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10344 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10345 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10346 case X86ISD::VSHL: return "X86ISD::VSHL";
10347 case X86ISD::VSRL: return "X86ISD::VSRL";
10348 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10349 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10350 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10351 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10352 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10353 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10354 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10355 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10356 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10357 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10358 case X86ISD::ADD: return "X86ISD::ADD";
10359 case X86ISD::SUB: return "X86ISD::SUB";
10360 case X86ISD::ADC: return "X86ISD::ADC";
10361 case X86ISD::SBB: return "X86ISD::SBB";
10362 case X86ISD::SMUL: return "X86ISD::SMUL";
10363 case X86ISD::UMUL: return "X86ISD::UMUL";
10364 case X86ISD::INC: return "X86ISD::INC";
10365 case X86ISD::DEC: return "X86ISD::DEC";
10366 case X86ISD::OR: return "X86ISD::OR";
10367 case X86ISD::XOR: return "X86ISD::XOR";
10368 case X86ISD::AND: return "X86ISD::AND";
10369 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10370 case X86ISD::PTEST: return "X86ISD::PTEST";
10371 case X86ISD::TESTP: return "X86ISD::TESTP";
10372 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10373 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10374 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10375 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10376 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10377 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10378 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10379 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10380 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10381 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10382 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10383 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10384 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10385 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10386 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10387 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10388 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10389 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10390 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10391 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10392 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10393 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10394 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10395 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10396 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10397 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10398 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10399 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10400 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10401 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10402 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10403 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10404 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10405 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10406 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10407 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10408 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10409 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10410 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10411 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10412 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10413 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10414 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10415 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10419 // isLegalAddressingMode - Return true if the addressing mode represented
10420 // by AM is legal for this target, for a load/store of the specified type.
10421 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10423 // X86 supports extremely general addressing modes.
10424 CodeModel::Model M = getTargetMachine().getCodeModel();
10425 Reloc::Model R = getTargetMachine().getRelocationModel();
10427 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10428 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10433 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10435 // If a reference to this global requires an extra load, we can't fold it.
10436 if (isGlobalStubReference(GVFlags))
10439 // If BaseGV requires a register for the PIC base, we cannot also have a
10440 // BaseReg specified.
10441 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10444 // If lower 4G is not available, then we must use rip-relative addressing.
10445 if ((M != CodeModel::Small || R != Reloc::Static) &&
10446 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10450 switch (AM.Scale) {
10456 // These scales always work.
10461 // These scales are formed with basereg+scalereg. Only accept if there is
10466 default: // Other stuff never works.
10474 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10475 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10477 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10478 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10479 if (NumBits1 <= NumBits2)
10484 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10485 if (!VT1.isInteger() || !VT2.isInteger())
10487 unsigned NumBits1 = VT1.getSizeInBits();
10488 unsigned NumBits2 = VT2.getSizeInBits();
10489 if (NumBits1 <= NumBits2)
10494 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10495 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10496 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10499 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10500 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10501 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10504 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10505 // i16 instructions are longer (0x66 prefix) and potentially slower.
10506 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10509 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10510 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10511 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10512 /// are assumed to be legal.
10514 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10516 // Very little shuffling can be done for 64-bit vectors right now.
10517 if (VT.getSizeInBits() == 64)
10518 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10520 // FIXME: pshufb, blends, shifts.
10521 return (VT.getVectorNumElements() == 2 ||
10522 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10523 isMOVLMask(M, VT) ||
10524 isSHUFPMask(M, VT) ||
10525 isPSHUFDMask(M, VT) ||
10526 isPSHUFHWMask(M, VT) ||
10527 isPSHUFLWMask(M, VT) ||
10528 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10529 isUNPCKLMask(M, VT) ||
10530 isUNPCKHMask(M, VT) ||
10531 isUNPCKL_v_undef_Mask(M, VT) ||
10532 isUNPCKH_v_undef_Mask(M, VT));
10536 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10538 unsigned NumElts = VT.getVectorNumElements();
10539 // FIXME: This collection of masks seems suspect.
10542 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10543 return (isMOVLMask(Mask, VT) ||
10544 isCommutedMOVLMask(Mask, VT, true) ||
10545 isSHUFPMask(Mask, VT) ||
10546 isCommutedSHUFPMask(Mask, VT));
10551 //===----------------------------------------------------------------------===//
10552 // X86 Scheduler Hooks
10553 //===----------------------------------------------------------------------===//
10555 // private utility function
10556 MachineBasicBlock *
10557 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10558 MachineBasicBlock *MBB,
10565 TargetRegisterClass *RC,
10566 bool invSrc) const {
10567 // For the atomic bitwise operator, we generate
10570 // ld t1 = [bitinstr.addr]
10571 // op t2 = t1, [bitinstr.val]
10573 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10575 // fallthrough -->nextMBB
10576 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10577 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10578 MachineFunction::iterator MBBIter = MBB;
10581 /// First build the CFG
10582 MachineFunction *F = MBB->getParent();
10583 MachineBasicBlock *thisMBB = MBB;
10584 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10585 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10586 F->insert(MBBIter, newMBB);
10587 F->insert(MBBIter, nextMBB);
10589 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10590 nextMBB->splice(nextMBB->begin(), thisMBB,
10591 llvm::next(MachineBasicBlock::iterator(bInstr)),
10593 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10595 // Update thisMBB to fall through to newMBB
10596 thisMBB->addSuccessor(newMBB);
10598 // newMBB jumps to itself and fall through to nextMBB
10599 newMBB->addSuccessor(nextMBB);
10600 newMBB->addSuccessor(newMBB);
10602 // Insert instructions into newMBB based on incoming instruction
10603 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10604 "unexpected number of operands");
10605 DebugLoc dl = bInstr->getDebugLoc();
10606 MachineOperand& destOper = bInstr->getOperand(0);
10607 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10608 int numArgs = bInstr->getNumOperands() - 1;
10609 for (int i=0; i < numArgs; ++i)
10610 argOpers[i] = &bInstr->getOperand(i+1);
10612 // x86 address has 4 operands: base, index, scale, and displacement
10613 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10614 int valArgIndx = lastAddrIndx + 1;
10616 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10617 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10618 for (int i=0; i <= lastAddrIndx; ++i)
10619 (*MIB).addOperand(*argOpers[i]);
10621 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10623 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10628 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10629 assert((argOpers[valArgIndx]->isReg() ||
10630 argOpers[valArgIndx]->isImm()) &&
10631 "invalid operand");
10632 if (argOpers[valArgIndx]->isReg())
10633 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10635 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10637 (*MIB).addOperand(*argOpers[valArgIndx]);
10639 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10642 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10643 for (int i=0; i <= lastAddrIndx; ++i)
10644 (*MIB).addOperand(*argOpers[i]);
10646 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10647 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10648 bInstr->memoperands_end());
10650 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10651 MIB.addReg(EAXreg);
10654 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10656 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10660 // private utility function: 64 bit atomics on 32 bit host.
10661 MachineBasicBlock *
10662 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10663 MachineBasicBlock *MBB,
10668 bool invSrc) const {
10669 // For the atomic bitwise operator, we generate
10670 // thisMBB (instructions are in pairs, except cmpxchg8b)
10671 // ld t1,t2 = [bitinstr.addr]
10673 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10674 // op t5, t6 <- out1, out2, [bitinstr.val]
10675 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10676 // mov ECX, EBX <- t5, t6
10677 // mov EAX, EDX <- t1, t2
10678 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10679 // mov t3, t4 <- EAX, EDX
10681 // result in out1, out2
10682 // fallthrough -->nextMBB
10684 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10685 const unsigned LoadOpc = X86::MOV32rm;
10686 const unsigned NotOpc = X86::NOT32r;
10687 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10688 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10689 MachineFunction::iterator MBBIter = MBB;
10692 /// First build the CFG
10693 MachineFunction *F = MBB->getParent();
10694 MachineBasicBlock *thisMBB = MBB;
10695 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10696 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10697 F->insert(MBBIter, newMBB);
10698 F->insert(MBBIter, nextMBB);
10700 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10701 nextMBB->splice(nextMBB->begin(), thisMBB,
10702 llvm::next(MachineBasicBlock::iterator(bInstr)),
10704 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10706 // Update thisMBB to fall through to newMBB
10707 thisMBB->addSuccessor(newMBB);
10709 // newMBB jumps to itself and fall through to nextMBB
10710 newMBB->addSuccessor(nextMBB);
10711 newMBB->addSuccessor(newMBB);
10713 DebugLoc dl = bInstr->getDebugLoc();
10714 // Insert instructions into newMBB based on incoming instruction
10715 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
10716 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
10717 "unexpected number of operands");
10718 MachineOperand& dest1Oper = bInstr->getOperand(0);
10719 MachineOperand& dest2Oper = bInstr->getOperand(1);
10720 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10721 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
10722 argOpers[i] = &bInstr->getOperand(i+2);
10724 // We use some of the operands multiple times, so conservatively just
10725 // clear any kill flags that might be present.
10726 if (argOpers[i]->isReg() && argOpers[i]->isUse())
10727 argOpers[i]->setIsKill(false);
10730 // x86 address has 5 operands: base, index, scale, displacement, and segment.
10731 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10733 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10734 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
10735 for (int i=0; i <= lastAddrIndx; ++i)
10736 (*MIB).addOperand(*argOpers[i]);
10737 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10738 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
10739 // add 4 to displacement.
10740 for (int i=0; i <= lastAddrIndx-2; ++i)
10741 (*MIB).addOperand(*argOpers[i]);
10742 MachineOperand newOp3 = *(argOpers[3]);
10743 if (newOp3.isImm())
10744 newOp3.setImm(newOp3.getImm()+4);
10746 newOp3.setOffset(newOp3.getOffset()+4);
10747 (*MIB).addOperand(newOp3);
10748 (*MIB).addOperand(*argOpers[lastAddrIndx]);
10750 // t3/4 are defined later, at the bottom of the loop
10751 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
10752 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
10753 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
10754 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
10755 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
10756 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
10758 // The subsequent operations should be using the destination registers of
10759 //the PHI instructions.
10761 t1 = F->getRegInfo().createVirtualRegister(RC);
10762 t2 = F->getRegInfo().createVirtualRegister(RC);
10763 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
10764 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
10766 t1 = dest1Oper.getReg();
10767 t2 = dest2Oper.getReg();
10770 int valArgIndx = lastAddrIndx + 1;
10771 assert((argOpers[valArgIndx]->isReg() ||
10772 argOpers[valArgIndx]->isImm()) &&
10773 "invalid operand");
10774 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
10775 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
10776 if (argOpers[valArgIndx]->isReg())
10777 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
10779 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
10780 if (regOpcL != X86::MOV32rr)
10782 (*MIB).addOperand(*argOpers[valArgIndx]);
10783 assert(argOpers[valArgIndx + 1]->isReg() ==
10784 argOpers[valArgIndx]->isReg());
10785 assert(argOpers[valArgIndx + 1]->isImm() ==
10786 argOpers[valArgIndx]->isImm());
10787 if (argOpers[valArgIndx + 1]->isReg())
10788 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
10790 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
10791 if (regOpcH != X86::MOV32rr)
10793 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
10795 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10797 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
10800 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
10802 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
10805 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
10806 for (int i=0; i <= lastAddrIndx; ++i)
10807 (*MIB).addOperand(*argOpers[i]);
10809 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10810 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10811 bInstr->memoperands_end());
10813 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
10814 MIB.addReg(X86::EAX);
10815 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
10816 MIB.addReg(X86::EDX);
10819 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10821 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10825 // private utility function
10826 MachineBasicBlock *
10827 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
10828 MachineBasicBlock *MBB,
10829 unsigned cmovOpc) const {
10830 // For the atomic min/max operator, we generate
10833 // ld t1 = [min/max.addr]
10834 // mov t2 = [min/max.val]
10836 // cmov[cond] t2 = t1
10838 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10840 // fallthrough -->nextMBB
10842 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10843 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10844 MachineFunction::iterator MBBIter = MBB;
10847 /// First build the CFG
10848 MachineFunction *F = MBB->getParent();
10849 MachineBasicBlock *thisMBB = MBB;
10850 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10851 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10852 F->insert(MBBIter, newMBB);
10853 F->insert(MBBIter, nextMBB);
10855 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10856 nextMBB->splice(nextMBB->begin(), thisMBB,
10857 llvm::next(MachineBasicBlock::iterator(mInstr)),
10859 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10861 // Update thisMBB to fall through to newMBB
10862 thisMBB->addSuccessor(newMBB);
10864 // newMBB jumps to newMBB and fall through to nextMBB
10865 newMBB->addSuccessor(nextMBB);
10866 newMBB->addSuccessor(newMBB);
10868 DebugLoc dl = mInstr->getDebugLoc();
10869 // Insert instructions into newMBB based on incoming instruction
10870 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10871 "unexpected number of operands");
10872 MachineOperand& destOper = mInstr->getOperand(0);
10873 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10874 int numArgs = mInstr->getNumOperands() - 1;
10875 for (int i=0; i < numArgs; ++i)
10876 argOpers[i] = &mInstr->getOperand(i+1);
10878 // x86 address has 4 operands: base, index, scale, and displacement
10879 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10880 int valArgIndx = lastAddrIndx + 1;
10882 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10883 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
10884 for (int i=0; i <= lastAddrIndx; ++i)
10885 (*MIB).addOperand(*argOpers[i]);
10887 // We only support register and immediate values
10888 assert((argOpers[valArgIndx]->isReg() ||
10889 argOpers[valArgIndx]->isImm()) &&
10890 "invalid operand");
10892 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10893 if (argOpers[valArgIndx]->isReg())
10894 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
10896 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
10897 (*MIB).addOperand(*argOpers[valArgIndx]);
10899 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10902 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
10907 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10908 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
10912 // Cmp and exchange if none has modified the memory location
10913 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
10914 for (int i=0; i <= lastAddrIndx; ++i)
10915 (*MIB).addOperand(*argOpers[i]);
10917 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10918 (*MIB).setMemRefs(mInstr->memoperands_begin(),
10919 mInstr->memoperands_end());
10921 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10922 MIB.addReg(X86::EAX);
10925 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10927 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
10931 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
10932 // or XMM0_V32I8 in AVX all of this code can be replaced with that
10933 // in the .td file.
10934 MachineBasicBlock *
10935 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
10936 unsigned numArgs, bool memArg) const {
10937 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
10938 "Target must have SSE4.2 or AVX features enabled");
10940 DebugLoc dl = MI->getDebugLoc();
10941 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10943 if (!Subtarget->hasAVX()) {
10945 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
10947 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
10950 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
10952 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
10955 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
10956 for (unsigned i = 0; i < numArgs; ++i) {
10957 MachineOperand &Op = MI->getOperand(i+1);
10958 if (!(Op.isReg() && Op.isImplicit()))
10959 MIB.addOperand(Op);
10961 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
10962 .addReg(X86::XMM0);
10964 MI->eraseFromParent();
10968 MachineBasicBlock *
10969 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
10970 DebugLoc dl = MI->getDebugLoc();
10971 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10973 // Address into RAX/EAX, other two args into ECX, EDX.
10974 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
10975 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10976 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
10977 for (int i = 0; i < X86::AddrNumOperands; ++i)
10978 MIB.addOperand(MI->getOperand(i));
10980 unsigned ValOps = X86::AddrNumOperands;
10981 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10982 .addReg(MI->getOperand(ValOps).getReg());
10983 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
10984 .addReg(MI->getOperand(ValOps+1).getReg());
10986 // The instruction doesn't actually take any operands though.
10987 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
10989 MI->eraseFromParent(); // The pseudo is gone now.
10993 MachineBasicBlock *
10994 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
10995 DebugLoc dl = MI->getDebugLoc();
10996 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10998 // First arg in ECX, the second in EAX.
10999 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11000 .addReg(MI->getOperand(0).getReg());
11001 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11002 .addReg(MI->getOperand(1).getReg());
11004 // The instruction doesn't actually take any operands though.
11005 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11007 MI->eraseFromParent(); // The pseudo is gone now.
11011 MachineBasicBlock *
11012 X86TargetLowering::EmitVAARG64WithCustomInserter(
11014 MachineBasicBlock *MBB) const {
11015 // Emit va_arg instruction on X86-64.
11017 // Operands to this pseudo-instruction:
11018 // 0 ) Output : destination address (reg)
11019 // 1-5) Input : va_list address (addr, i64mem)
11020 // 6 ) ArgSize : Size (in bytes) of vararg type
11021 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11022 // 8 ) Align : Alignment of type
11023 // 9 ) EFLAGS (implicit-def)
11025 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11026 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11028 unsigned DestReg = MI->getOperand(0).getReg();
11029 MachineOperand &Base = MI->getOperand(1);
11030 MachineOperand &Scale = MI->getOperand(2);
11031 MachineOperand &Index = MI->getOperand(3);
11032 MachineOperand &Disp = MI->getOperand(4);
11033 MachineOperand &Segment = MI->getOperand(5);
11034 unsigned ArgSize = MI->getOperand(6).getImm();
11035 unsigned ArgMode = MI->getOperand(7).getImm();
11036 unsigned Align = MI->getOperand(8).getImm();
11038 // Memory Reference
11039 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11040 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11041 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11043 // Machine Information
11044 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11045 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11046 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11047 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11048 DebugLoc DL = MI->getDebugLoc();
11050 // struct va_list {
11053 // i64 overflow_area (address)
11054 // i64 reg_save_area (address)
11056 // sizeof(va_list) = 24
11057 // alignment(va_list) = 8
11059 unsigned TotalNumIntRegs = 6;
11060 unsigned TotalNumXMMRegs = 8;
11061 bool UseGPOffset = (ArgMode == 1);
11062 bool UseFPOffset = (ArgMode == 2);
11063 unsigned MaxOffset = TotalNumIntRegs * 8 +
11064 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11066 /* Align ArgSize to a multiple of 8 */
11067 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11068 bool NeedsAlign = (Align > 8);
11070 MachineBasicBlock *thisMBB = MBB;
11071 MachineBasicBlock *overflowMBB;
11072 MachineBasicBlock *offsetMBB;
11073 MachineBasicBlock *endMBB;
11075 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11076 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11077 unsigned OffsetReg = 0;
11079 if (!UseGPOffset && !UseFPOffset) {
11080 // If we only pull from the overflow region, we don't create a branch.
11081 // We don't need to alter control flow.
11082 OffsetDestReg = 0; // unused
11083 OverflowDestReg = DestReg;
11086 overflowMBB = thisMBB;
11089 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11090 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11091 // If not, pull from overflow_area. (branch to overflowMBB)
11096 // offsetMBB overflowMBB
11101 // Registers for the PHI in endMBB
11102 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11103 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11105 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11106 MachineFunction *MF = MBB->getParent();
11107 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11108 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11109 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11111 MachineFunction::iterator MBBIter = MBB;
11114 // Insert the new basic blocks
11115 MF->insert(MBBIter, offsetMBB);
11116 MF->insert(MBBIter, overflowMBB);
11117 MF->insert(MBBIter, endMBB);
11119 // Transfer the remainder of MBB and its successor edges to endMBB.
11120 endMBB->splice(endMBB->begin(), thisMBB,
11121 llvm::next(MachineBasicBlock::iterator(MI)),
11123 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11125 // Make offsetMBB and overflowMBB successors of thisMBB
11126 thisMBB->addSuccessor(offsetMBB);
11127 thisMBB->addSuccessor(overflowMBB);
11129 // endMBB is a successor of both offsetMBB and overflowMBB
11130 offsetMBB->addSuccessor(endMBB);
11131 overflowMBB->addSuccessor(endMBB);
11133 // Load the offset value into a register
11134 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11135 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11139 .addDisp(Disp, UseFPOffset ? 4 : 0)
11140 .addOperand(Segment)
11141 .setMemRefs(MMOBegin, MMOEnd);
11143 // Check if there is enough room left to pull this argument.
11144 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11146 .addImm(MaxOffset + 8 - ArgSizeA8);
11148 // Branch to "overflowMBB" if offset >= max
11149 // Fall through to "offsetMBB" otherwise
11150 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11151 .addMBB(overflowMBB);
11154 // In offsetMBB, emit code to use the reg_save_area.
11156 assert(OffsetReg != 0);
11158 // Read the reg_save_area address.
11159 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11160 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11165 .addOperand(Segment)
11166 .setMemRefs(MMOBegin, MMOEnd);
11168 // Zero-extend the offset
11169 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11170 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11173 .addImm(X86::sub_32bit);
11175 // Add the offset to the reg_save_area to get the final address.
11176 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11177 .addReg(OffsetReg64)
11178 .addReg(RegSaveReg);
11180 // Compute the offset for the next argument
11181 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11182 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11184 .addImm(UseFPOffset ? 16 : 8);
11186 // Store it back into the va_list.
11187 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11191 .addDisp(Disp, UseFPOffset ? 4 : 0)
11192 .addOperand(Segment)
11193 .addReg(NextOffsetReg)
11194 .setMemRefs(MMOBegin, MMOEnd);
11197 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11202 // Emit code to use overflow area
11205 // Load the overflow_area address into a register.
11206 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11207 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11212 .addOperand(Segment)
11213 .setMemRefs(MMOBegin, MMOEnd);
11215 // If we need to align it, do so. Otherwise, just copy the address
11216 // to OverflowDestReg.
11218 // Align the overflow address
11219 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11220 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11222 // aligned_addr = (addr + (align-1)) & ~(align-1)
11223 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11224 .addReg(OverflowAddrReg)
11227 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11229 .addImm(~(uint64_t)(Align-1));
11231 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11232 .addReg(OverflowAddrReg);
11235 // Compute the next overflow address after this argument.
11236 // (the overflow address should be kept 8-byte aligned)
11237 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11238 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11239 .addReg(OverflowDestReg)
11240 .addImm(ArgSizeA8);
11242 // Store the new overflow address.
11243 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11248 .addOperand(Segment)
11249 .addReg(NextAddrReg)
11250 .setMemRefs(MMOBegin, MMOEnd);
11252 // If we branched, emit the PHI to the front of endMBB.
11254 BuildMI(*endMBB, endMBB->begin(), DL,
11255 TII->get(X86::PHI), DestReg)
11256 .addReg(OffsetDestReg).addMBB(offsetMBB)
11257 .addReg(OverflowDestReg).addMBB(overflowMBB);
11260 // Erase the pseudo instruction
11261 MI->eraseFromParent();
11266 MachineBasicBlock *
11267 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11269 MachineBasicBlock *MBB) const {
11270 // Emit code to save XMM registers to the stack. The ABI says that the
11271 // number of registers to save is given in %al, so it's theoretically
11272 // possible to do an indirect jump trick to avoid saving all of them,
11273 // however this code takes a simpler approach and just executes all
11274 // of the stores if %al is non-zero. It's less code, and it's probably
11275 // easier on the hardware branch predictor, and stores aren't all that
11276 // expensive anyway.
11278 // Create the new basic blocks. One block contains all the XMM stores,
11279 // and one block is the final destination regardless of whether any
11280 // stores were performed.
11281 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11282 MachineFunction *F = MBB->getParent();
11283 MachineFunction::iterator MBBIter = MBB;
11285 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11286 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11287 F->insert(MBBIter, XMMSaveMBB);
11288 F->insert(MBBIter, EndMBB);
11290 // Transfer the remainder of MBB and its successor edges to EndMBB.
11291 EndMBB->splice(EndMBB->begin(), MBB,
11292 llvm::next(MachineBasicBlock::iterator(MI)),
11294 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11296 // The original block will now fall through to the XMM save block.
11297 MBB->addSuccessor(XMMSaveMBB);
11298 // The XMMSaveMBB will fall through to the end block.
11299 XMMSaveMBB->addSuccessor(EndMBB);
11301 // Now add the instructions.
11302 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11303 DebugLoc DL = MI->getDebugLoc();
11305 unsigned CountReg = MI->getOperand(0).getReg();
11306 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11307 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11309 if (!Subtarget->isTargetWin64()) {
11310 // If %al is 0, branch around the XMM save block.
11311 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11312 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11313 MBB->addSuccessor(EndMBB);
11316 // In the XMM save block, save all the XMM argument registers.
11317 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11318 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11319 MachineMemOperand *MMO =
11320 F->getMachineMemOperand(
11321 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11322 MachineMemOperand::MOStore,
11323 /*Size=*/16, /*Align=*/16);
11324 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
11325 .addFrameIndex(RegSaveFrameIndex)
11326 .addImm(/*Scale=*/1)
11327 .addReg(/*IndexReg=*/0)
11328 .addImm(/*Disp=*/Offset)
11329 .addReg(/*Segment=*/0)
11330 .addReg(MI->getOperand(i).getReg())
11331 .addMemOperand(MMO);
11334 MI->eraseFromParent(); // The pseudo instruction is gone now.
11339 MachineBasicBlock *
11340 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11341 MachineBasicBlock *BB) const {
11342 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11343 DebugLoc DL = MI->getDebugLoc();
11345 // To "insert" a SELECT_CC instruction, we actually have to insert the
11346 // diamond control-flow pattern. The incoming instruction knows the
11347 // destination vreg to set, the condition code register to branch on, the
11348 // true/false values to select between, and a branch opcode to use.
11349 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11350 MachineFunction::iterator It = BB;
11356 // cmpTY ccX, r1, r2
11358 // fallthrough --> copy0MBB
11359 MachineBasicBlock *thisMBB = BB;
11360 MachineFunction *F = BB->getParent();
11361 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11362 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11363 F->insert(It, copy0MBB);
11364 F->insert(It, sinkMBB);
11366 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11367 // live into the sink and copy blocks.
11368 const MachineFunction *MF = BB->getParent();
11369 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
11370 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
11372 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
11373 const MachineOperand &MO = MI->getOperand(I);
11374 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
11375 unsigned Reg = MO.getReg();
11376 if (Reg != X86::EFLAGS) continue;
11377 copy0MBB->addLiveIn(Reg);
11378 sinkMBB->addLiveIn(Reg);
11381 // Transfer the remainder of BB and its successor edges to sinkMBB.
11382 sinkMBB->splice(sinkMBB->begin(), BB,
11383 llvm::next(MachineBasicBlock::iterator(MI)),
11385 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11387 // Add the true and fallthrough blocks as its successors.
11388 BB->addSuccessor(copy0MBB);
11389 BB->addSuccessor(sinkMBB);
11391 // Create the conditional branch instruction.
11393 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11394 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11397 // %FalseValue = ...
11398 // # fallthrough to sinkMBB
11399 copy0MBB->addSuccessor(sinkMBB);
11402 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11404 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11405 TII->get(X86::PHI), MI->getOperand(0).getReg())
11406 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11407 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11409 MI->eraseFromParent(); // The pseudo instruction is gone now.
11413 MachineBasicBlock *
11414 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11415 MachineBasicBlock *BB) const {
11416 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11417 DebugLoc DL = MI->getDebugLoc();
11419 assert(!Subtarget->isTargetEnvMacho());
11421 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11422 // non-trivial part is impdef of ESP.
11424 if (Subtarget->isTargetWin64()) {
11425 if (Subtarget->isTargetCygMing()) {
11426 // ___chkstk(Mingw64):
11427 // Clobbers R10, R11, RAX and EFLAGS.
11429 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11430 .addExternalSymbol("___chkstk")
11431 .addReg(X86::RAX, RegState::Implicit)
11432 .addReg(X86::RSP, RegState::Implicit)
11433 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11434 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11435 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11437 // __chkstk(MSVCRT): does not update stack pointer.
11438 // Clobbers R10, R11 and EFLAGS.
11439 // FIXME: RAX(allocated size) might be reused and not killed.
11440 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11441 .addExternalSymbol("__chkstk")
11442 .addReg(X86::RAX, RegState::Implicit)
11443 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11444 // RAX has the offset to subtracted from RSP.
11445 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11450 const char *StackProbeSymbol =
11451 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11453 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11454 .addExternalSymbol(StackProbeSymbol)
11455 .addReg(X86::EAX, RegState::Implicit)
11456 .addReg(X86::ESP, RegState::Implicit)
11457 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11458 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11459 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11462 MI->eraseFromParent(); // The pseudo instruction is gone now.
11466 MachineBasicBlock *
11467 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11468 MachineBasicBlock *BB) const {
11469 // This is pretty easy. We're taking the value that we received from
11470 // our load from the relocation, sticking it in either RDI (x86-64)
11471 // or EAX and doing an indirect call. The return value will then
11472 // be in the normal return register.
11473 const X86InstrInfo *TII
11474 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11475 DebugLoc DL = MI->getDebugLoc();
11476 MachineFunction *F = BB->getParent();
11478 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11479 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11481 if (Subtarget->is64Bit()) {
11482 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11483 TII->get(X86::MOV64rm), X86::RDI)
11485 .addImm(0).addReg(0)
11486 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11487 MI->getOperand(3).getTargetFlags())
11489 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11490 addDirectMem(MIB, X86::RDI);
11491 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11492 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11493 TII->get(X86::MOV32rm), X86::EAX)
11495 .addImm(0).addReg(0)
11496 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11497 MI->getOperand(3).getTargetFlags())
11499 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11500 addDirectMem(MIB, X86::EAX);
11502 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11503 TII->get(X86::MOV32rm), X86::EAX)
11504 .addReg(TII->getGlobalBaseReg(F))
11505 .addImm(0).addReg(0)
11506 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11507 MI->getOperand(3).getTargetFlags())
11509 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11510 addDirectMem(MIB, X86::EAX);
11513 MI->eraseFromParent(); // The pseudo instruction is gone now.
11517 MachineBasicBlock *
11518 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11519 MachineBasicBlock *BB) const {
11520 switch (MI->getOpcode()) {
11521 default: assert(false && "Unexpected instr type to insert");
11522 case X86::TAILJMPd64:
11523 case X86::TAILJMPr64:
11524 case X86::TAILJMPm64:
11525 assert(!"TAILJMP64 would not be touched here.");
11526 case X86::TCRETURNdi64:
11527 case X86::TCRETURNri64:
11528 case X86::TCRETURNmi64:
11529 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11530 // On AMD64, additional defs should be added before register allocation.
11531 if (!Subtarget->isTargetWin64()) {
11532 MI->addRegisterDefined(X86::RSI);
11533 MI->addRegisterDefined(X86::RDI);
11534 MI->addRegisterDefined(X86::XMM6);
11535 MI->addRegisterDefined(X86::XMM7);
11536 MI->addRegisterDefined(X86::XMM8);
11537 MI->addRegisterDefined(X86::XMM9);
11538 MI->addRegisterDefined(X86::XMM10);
11539 MI->addRegisterDefined(X86::XMM11);
11540 MI->addRegisterDefined(X86::XMM12);
11541 MI->addRegisterDefined(X86::XMM13);
11542 MI->addRegisterDefined(X86::XMM14);
11543 MI->addRegisterDefined(X86::XMM15);
11546 case X86::WIN_ALLOCA:
11547 return EmitLoweredWinAlloca(MI, BB);
11548 case X86::TLSCall_32:
11549 case X86::TLSCall_64:
11550 return EmitLoweredTLSCall(MI, BB);
11551 case X86::CMOV_GR8:
11552 case X86::CMOV_FR32:
11553 case X86::CMOV_FR64:
11554 case X86::CMOV_V4F32:
11555 case X86::CMOV_V2F64:
11556 case X86::CMOV_V2I64:
11557 case X86::CMOV_V8F32:
11558 case X86::CMOV_V4F64:
11559 case X86::CMOV_V4I64:
11560 case X86::CMOV_GR16:
11561 case X86::CMOV_GR32:
11562 case X86::CMOV_RFP32:
11563 case X86::CMOV_RFP64:
11564 case X86::CMOV_RFP80:
11565 return EmitLoweredSelect(MI, BB);
11567 case X86::FP32_TO_INT16_IN_MEM:
11568 case X86::FP32_TO_INT32_IN_MEM:
11569 case X86::FP32_TO_INT64_IN_MEM:
11570 case X86::FP64_TO_INT16_IN_MEM:
11571 case X86::FP64_TO_INT32_IN_MEM:
11572 case X86::FP64_TO_INT64_IN_MEM:
11573 case X86::FP80_TO_INT16_IN_MEM:
11574 case X86::FP80_TO_INT32_IN_MEM:
11575 case X86::FP80_TO_INT64_IN_MEM: {
11576 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11577 DebugLoc DL = MI->getDebugLoc();
11579 // Change the floating point control register to use "round towards zero"
11580 // mode when truncating to an integer value.
11581 MachineFunction *F = BB->getParent();
11582 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11583 addFrameReference(BuildMI(*BB, MI, DL,
11584 TII->get(X86::FNSTCW16m)), CWFrameIdx);
11586 // Load the old value of the high byte of the control word...
11588 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
11589 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
11592 // Set the high part to be round to zero...
11593 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
11596 // Reload the modified control word now...
11597 addFrameReference(BuildMI(*BB, MI, DL,
11598 TII->get(X86::FLDCW16m)), CWFrameIdx);
11600 // Restore the memory image of control word to original value
11601 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
11604 // Get the X86 opcode to use.
11606 switch (MI->getOpcode()) {
11607 default: llvm_unreachable("illegal opcode!");
11608 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
11609 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
11610 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
11611 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
11612 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
11613 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
11614 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
11615 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
11616 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
11620 MachineOperand &Op = MI->getOperand(0);
11622 AM.BaseType = X86AddressMode::RegBase;
11623 AM.Base.Reg = Op.getReg();
11625 AM.BaseType = X86AddressMode::FrameIndexBase;
11626 AM.Base.FrameIndex = Op.getIndex();
11628 Op = MI->getOperand(1);
11630 AM.Scale = Op.getImm();
11631 Op = MI->getOperand(2);
11633 AM.IndexReg = Op.getImm();
11634 Op = MI->getOperand(3);
11635 if (Op.isGlobal()) {
11636 AM.GV = Op.getGlobal();
11638 AM.Disp = Op.getImm();
11640 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
11641 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
11643 // Reload the original control word now.
11644 addFrameReference(BuildMI(*BB, MI, DL,
11645 TII->get(X86::FLDCW16m)), CWFrameIdx);
11647 MI->eraseFromParent(); // The pseudo instruction is gone now.
11650 // String/text processing lowering.
11651 case X86::PCMPISTRM128REG:
11652 case X86::VPCMPISTRM128REG:
11653 return EmitPCMP(MI, BB, 3, false /* in-mem */);
11654 case X86::PCMPISTRM128MEM:
11655 case X86::VPCMPISTRM128MEM:
11656 return EmitPCMP(MI, BB, 3, true /* in-mem */);
11657 case X86::PCMPESTRM128REG:
11658 case X86::VPCMPESTRM128REG:
11659 return EmitPCMP(MI, BB, 5, false /* in mem */);
11660 case X86::PCMPESTRM128MEM:
11661 case X86::VPCMPESTRM128MEM:
11662 return EmitPCMP(MI, BB, 5, true /* in mem */);
11664 // Thread synchronization.
11666 return EmitMonitor(MI, BB);
11668 return EmitMwait(MI, BB);
11670 // Atomic Lowering.
11671 case X86::ATOMAND32:
11672 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11673 X86::AND32ri, X86::MOV32rm,
11675 X86::NOT32r, X86::EAX,
11676 X86::GR32RegisterClass);
11677 case X86::ATOMOR32:
11678 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
11679 X86::OR32ri, X86::MOV32rm,
11681 X86::NOT32r, X86::EAX,
11682 X86::GR32RegisterClass);
11683 case X86::ATOMXOR32:
11684 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
11685 X86::XOR32ri, X86::MOV32rm,
11687 X86::NOT32r, X86::EAX,
11688 X86::GR32RegisterClass);
11689 case X86::ATOMNAND32:
11690 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11691 X86::AND32ri, X86::MOV32rm,
11693 X86::NOT32r, X86::EAX,
11694 X86::GR32RegisterClass, true);
11695 case X86::ATOMMIN32:
11696 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
11697 case X86::ATOMMAX32:
11698 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
11699 case X86::ATOMUMIN32:
11700 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
11701 case X86::ATOMUMAX32:
11702 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
11704 case X86::ATOMAND16:
11705 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11706 X86::AND16ri, X86::MOV16rm,
11708 X86::NOT16r, X86::AX,
11709 X86::GR16RegisterClass);
11710 case X86::ATOMOR16:
11711 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
11712 X86::OR16ri, X86::MOV16rm,
11714 X86::NOT16r, X86::AX,
11715 X86::GR16RegisterClass);
11716 case X86::ATOMXOR16:
11717 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
11718 X86::XOR16ri, X86::MOV16rm,
11720 X86::NOT16r, X86::AX,
11721 X86::GR16RegisterClass);
11722 case X86::ATOMNAND16:
11723 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11724 X86::AND16ri, X86::MOV16rm,
11726 X86::NOT16r, X86::AX,
11727 X86::GR16RegisterClass, true);
11728 case X86::ATOMMIN16:
11729 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
11730 case X86::ATOMMAX16:
11731 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
11732 case X86::ATOMUMIN16:
11733 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
11734 case X86::ATOMUMAX16:
11735 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
11737 case X86::ATOMAND8:
11738 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11739 X86::AND8ri, X86::MOV8rm,
11741 X86::NOT8r, X86::AL,
11742 X86::GR8RegisterClass);
11744 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
11745 X86::OR8ri, X86::MOV8rm,
11747 X86::NOT8r, X86::AL,
11748 X86::GR8RegisterClass);
11749 case X86::ATOMXOR8:
11750 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
11751 X86::XOR8ri, X86::MOV8rm,
11753 X86::NOT8r, X86::AL,
11754 X86::GR8RegisterClass);
11755 case X86::ATOMNAND8:
11756 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11757 X86::AND8ri, X86::MOV8rm,
11759 X86::NOT8r, X86::AL,
11760 X86::GR8RegisterClass, true);
11761 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
11762 // This group is for 64-bit host.
11763 case X86::ATOMAND64:
11764 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11765 X86::AND64ri32, X86::MOV64rm,
11767 X86::NOT64r, X86::RAX,
11768 X86::GR64RegisterClass);
11769 case X86::ATOMOR64:
11770 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
11771 X86::OR64ri32, X86::MOV64rm,
11773 X86::NOT64r, X86::RAX,
11774 X86::GR64RegisterClass);
11775 case X86::ATOMXOR64:
11776 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
11777 X86::XOR64ri32, X86::MOV64rm,
11779 X86::NOT64r, X86::RAX,
11780 X86::GR64RegisterClass);
11781 case X86::ATOMNAND64:
11782 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11783 X86::AND64ri32, X86::MOV64rm,
11785 X86::NOT64r, X86::RAX,
11786 X86::GR64RegisterClass, true);
11787 case X86::ATOMMIN64:
11788 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
11789 case X86::ATOMMAX64:
11790 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
11791 case X86::ATOMUMIN64:
11792 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
11793 case X86::ATOMUMAX64:
11794 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
11796 // This group does 64-bit operations on a 32-bit host.
11797 case X86::ATOMAND6432:
11798 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11799 X86::AND32rr, X86::AND32rr,
11800 X86::AND32ri, X86::AND32ri,
11802 case X86::ATOMOR6432:
11803 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11804 X86::OR32rr, X86::OR32rr,
11805 X86::OR32ri, X86::OR32ri,
11807 case X86::ATOMXOR6432:
11808 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11809 X86::XOR32rr, X86::XOR32rr,
11810 X86::XOR32ri, X86::XOR32ri,
11812 case X86::ATOMNAND6432:
11813 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11814 X86::AND32rr, X86::AND32rr,
11815 X86::AND32ri, X86::AND32ri,
11817 case X86::ATOMADD6432:
11818 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11819 X86::ADD32rr, X86::ADC32rr,
11820 X86::ADD32ri, X86::ADC32ri,
11822 case X86::ATOMSUB6432:
11823 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11824 X86::SUB32rr, X86::SBB32rr,
11825 X86::SUB32ri, X86::SBB32ri,
11827 case X86::ATOMSWAP6432:
11828 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11829 X86::MOV32rr, X86::MOV32rr,
11830 X86::MOV32ri, X86::MOV32ri,
11832 case X86::VASTART_SAVE_XMM_REGS:
11833 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
11835 case X86::VAARG_64:
11836 return EmitVAARG64WithCustomInserter(MI, BB);
11840 //===----------------------------------------------------------------------===//
11841 // X86 Optimization Hooks
11842 //===----------------------------------------------------------------------===//
11844 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
11848 const SelectionDAG &DAG,
11849 unsigned Depth) const {
11850 unsigned Opc = Op.getOpcode();
11851 assert((Opc >= ISD::BUILTIN_OP_END ||
11852 Opc == ISD::INTRINSIC_WO_CHAIN ||
11853 Opc == ISD::INTRINSIC_W_CHAIN ||
11854 Opc == ISD::INTRINSIC_VOID) &&
11855 "Should use MaskedValueIsZero if you don't know whether Op"
11856 " is a target node!");
11858 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
11872 // These nodes' second result is a boolean.
11873 if (Op.getResNo() == 0)
11876 case X86ISD::SETCC:
11877 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
11878 Mask.getBitWidth() - 1);
11883 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
11884 unsigned Depth) const {
11885 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
11886 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
11887 return Op.getValueType().getScalarType().getSizeInBits();
11893 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
11894 /// node is a GlobalAddress + offset.
11895 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
11896 const GlobalValue* &GA,
11897 int64_t &Offset) const {
11898 if (N->getOpcode() == X86ISD::Wrapper) {
11899 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
11900 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
11901 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
11905 return TargetLowering::isGAPlusOffset(N, GA, Offset);
11908 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
11909 /// same as extracting the high 128-bit part of 256-bit vector and then
11910 /// inserting the result into the low part of a new 256-bit vector
11911 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
11912 EVT VT = SVOp->getValueType(0);
11913 int NumElems = VT.getVectorNumElements();
11915 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
11916 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
11917 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
11918 SVOp->getMaskElt(j) >= 0)
11924 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
11925 /// same as extracting the low 128-bit part of 256-bit vector and then
11926 /// inserting the result into the high part of a new 256-bit vector
11927 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
11928 EVT VT = SVOp->getValueType(0);
11929 int NumElems = VT.getVectorNumElements();
11931 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
11932 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
11933 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
11934 SVOp->getMaskElt(j) >= 0)
11940 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
11941 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
11942 TargetLowering::DAGCombinerInfo &DCI) {
11943 DebugLoc dl = N->getDebugLoc();
11944 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
11945 SDValue V1 = SVOp->getOperand(0);
11946 SDValue V2 = SVOp->getOperand(1);
11947 EVT VT = SVOp->getValueType(0);
11948 int NumElems = VT.getVectorNumElements();
11950 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
11951 V2.getOpcode() == ISD::CONCAT_VECTORS) {
11955 // V UNDEF BUILD_VECTOR UNDEF
11957 // CONCAT_VECTOR CONCAT_VECTOR
11960 // RESULT: V + zero extended
11962 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
11963 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
11964 V1.getOperand(1).getOpcode() != ISD::UNDEF)
11967 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
11970 // To match the shuffle mask, the first half of the mask should
11971 // be exactly the first vector, and all the rest a splat with the
11972 // first element of the second one.
11973 for (int i = 0; i < NumElems/2; ++i)
11974 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
11975 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
11978 // Emit a zeroed vector and insert the desired subvector on its
11980 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
11981 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
11982 DAG.getConstant(0, MVT::i32), DAG, dl);
11983 return DCI.CombineTo(N, InsV);
11986 //===--------------------------------------------------------------------===//
11987 // Combine some shuffles into subvector extracts and inserts:
11990 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
11991 if (isShuffleHigh128VectorInsertLow(SVOp)) {
11992 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
11994 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
11995 V, DAG.getConstant(0, MVT::i32), DAG, dl);
11996 return DCI.CombineTo(N, InsV);
11999 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12000 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12001 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12002 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12003 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12004 return DCI.CombineTo(N, InsV);
12010 /// PerformShuffleCombine - Performs several different shuffle combines.
12011 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12012 TargetLowering::DAGCombinerInfo &DCI,
12013 const X86Subtarget *Subtarget) {
12014 DebugLoc dl = N->getDebugLoc();
12015 EVT VT = N->getValueType(0);
12017 // Don't create instructions with illegal types after legalize types has run.
12018 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12019 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12022 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12023 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12024 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12025 return PerformShuffleCombine256(N, DAG, DCI);
12027 // Only handle 128 wide vector from here on.
12028 if (VT.getSizeInBits() != 128)
12031 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12032 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12033 // consecutive, non-overlapping, and in the right order.
12034 SmallVector<SDValue, 16> Elts;
12035 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12036 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12038 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12041 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12042 /// generation and convert it from being a bunch of shuffles and extracts
12043 /// to a simple store and scalar loads to extract the elements.
12044 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12045 const TargetLowering &TLI) {
12046 SDValue InputVector = N->getOperand(0);
12048 // Only operate on vectors of 4 elements, where the alternative shuffling
12049 // gets to be more expensive.
12050 if (InputVector.getValueType() != MVT::v4i32)
12053 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12054 // single use which is a sign-extend or zero-extend, and all elements are
12056 SmallVector<SDNode *, 4> Uses;
12057 unsigned ExtractedElements = 0;
12058 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12059 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12060 if (UI.getUse().getResNo() != InputVector.getResNo())
12063 SDNode *Extract = *UI;
12064 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12067 if (Extract->getValueType(0) != MVT::i32)
12069 if (!Extract->hasOneUse())
12071 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12072 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12074 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12077 // Record which element was extracted.
12078 ExtractedElements |=
12079 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12081 Uses.push_back(Extract);
12084 // If not all the elements were used, this may not be worthwhile.
12085 if (ExtractedElements != 15)
12088 // Ok, we've now decided to do the transformation.
12089 DebugLoc dl = InputVector.getDebugLoc();
12091 // Store the value to a temporary stack slot.
12092 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12093 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12094 MachinePointerInfo(), false, false, 0);
12096 // Replace each use (extract) with a load of the appropriate element.
12097 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12098 UE = Uses.end(); UI != UE; ++UI) {
12099 SDNode *Extract = *UI;
12101 // cOMpute the element's address.
12102 SDValue Idx = Extract->getOperand(1);
12104 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12105 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12106 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12108 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12109 StackPtr, OffsetVal);
12111 // Load the scalar.
12112 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12113 ScalarAddr, MachinePointerInfo(),
12116 // Replace the exact with the load.
12117 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12120 // The replacement was made in place; don't return anything.
12124 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
12125 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12126 const X86Subtarget *Subtarget) {
12127 DebugLoc DL = N->getDebugLoc();
12128 SDValue Cond = N->getOperand(0);
12129 // Get the LHS/RHS of the select.
12130 SDValue LHS = N->getOperand(1);
12131 SDValue RHS = N->getOperand(2);
12133 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12134 // instructions match the semantics of the common C idiom x<y?x:y but not
12135 // x<=y?x:y, because of how they handle negative zero (which can be
12136 // ignored in unsafe-math mode).
12137 if (Subtarget->hasSSE2() &&
12138 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
12139 Cond.getOpcode() == ISD::SETCC) {
12140 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12142 unsigned Opcode = 0;
12143 // Check for x CC y ? x : y.
12144 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12145 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12149 // Converting this to a min would handle NaNs incorrectly, and swapping
12150 // the operands would cause it to handle comparisons between positive
12151 // and negative zero incorrectly.
12152 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12153 if (!UnsafeFPMath &&
12154 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12156 std::swap(LHS, RHS);
12158 Opcode = X86ISD::FMIN;
12161 // Converting this to a min would handle comparisons between positive
12162 // and negative zero incorrectly.
12163 if (!UnsafeFPMath &&
12164 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12166 Opcode = X86ISD::FMIN;
12169 // Converting this to a min would handle both negative zeros and NaNs
12170 // incorrectly, but we can swap the operands to fix both.
12171 std::swap(LHS, RHS);
12175 Opcode = X86ISD::FMIN;
12179 // Converting this to a max would handle comparisons between positive
12180 // and negative zero incorrectly.
12181 if (!UnsafeFPMath &&
12182 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12184 Opcode = X86ISD::FMAX;
12187 // Converting this to a max would handle NaNs incorrectly, and swapping
12188 // the operands would cause it to handle comparisons between positive
12189 // and negative zero incorrectly.
12190 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12191 if (!UnsafeFPMath &&
12192 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12194 std::swap(LHS, RHS);
12196 Opcode = X86ISD::FMAX;
12199 // Converting this to a max would handle both negative zeros and NaNs
12200 // incorrectly, but we can swap the operands to fix both.
12201 std::swap(LHS, RHS);
12205 Opcode = X86ISD::FMAX;
12208 // Check for x CC y ? y : x -- a min/max with reversed arms.
12209 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12210 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12214 // Converting this to a min would handle comparisons between positive
12215 // and negative zero incorrectly, and swapping the operands would
12216 // cause it to handle NaNs incorrectly.
12217 if (!UnsafeFPMath &&
12218 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12219 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12221 std::swap(LHS, RHS);
12223 Opcode = X86ISD::FMIN;
12226 // Converting this to a min would handle NaNs incorrectly.
12227 if (!UnsafeFPMath &&
12228 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12230 Opcode = X86ISD::FMIN;
12233 // Converting this to a min would handle both negative zeros and NaNs
12234 // incorrectly, but we can swap the operands to fix both.
12235 std::swap(LHS, RHS);
12239 Opcode = X86ISD::FMIN;
12243 // Converting this to a max would handle NaNs incorrectly.
12244 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12246 Opcode = X86ISD::FMAX;
12249 // Converting this to a max would handle comparisons between positive
12250 // and negative zero incorrectly, and swapping the operands would
12251 // cause it to handle NaNs incorrectly.
12252 if (!UnsafeFPMath &&
12253 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12254 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12256 std::swap(LHS, RHS);
12258 Opcode = X86ISD::FMAX;
12261 // Converting this to a max would handle both negative zeros and NaNs
12262 // incorrectly, but we can swap the operands to fix both.
12263 std::swap(LHS, RHS);
12267 Opcode = X86ISD::FMAX;
12273 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12276 // If this is a select between two integer constants, try to do some
12278 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12279 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12280 // Don't do this for crazy integer types.
12281 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12282 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12283 // so that TrueC (the true value) is larger than FalseC.
12284 bool NeedsCondInvert = false;
12286 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12287 // Efficiently invertible.
12288 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12289 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12290 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12291 NeedsCondInvert = true;
12292 std::swap(TrueC, FalseC);
12295 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12296 if (FalseC->getAPIntValue() == 0 &&
12297 TrueC->getAPIntValue().isPowerOf2()) {
12298 if (NeedsCondInvert) // Invert the condition if needed.
12299 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12300 DAG.getConstant(1, Cond.getValueType()));
12302 // Zero extend the condition if needed.
12303 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12305 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12306 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12307 DAG.getConstant(ShAmt, MVT::i8));
12310 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12311 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12312 if (NeedsCondInvert) // Invert the condition if needed.
12313 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12314 DAG.getConstant(1, Cond.getValueType()));
12316 // Zero extend the condition if needed.
12317 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12318 FalseC->getValueType(0), Cond);
12319 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12320 SDValue(FalseC, 0));
12323 // Optimize cases that will turn into an LEA instruction. This requires
12324 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12325 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12326 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12327 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12329 bool isFastMultiplier = false;
12331 switch ((unsigned char)Diff) {
12333 case 1: // result = add base, cond
12334 case 2: // result = lea base( , cond*2)
12335 case 3: // result = lea base(cond, cond*2)
12336 case 4: // result = lea base( , cond*4)
12337 case 5: // result = lea base(cond, cond*4)
12338 case 8: // result = lea base( , cond*8)
12339 case 9: // result = lea base(cond, cond*8)
12340 isFastMultiplier = true;
12345 if (isFastMultiplier) {
12346 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12347 if (NeedsCondInvert) // Invert the condition if needed.
12348 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12349 DAG.getConstant(1, Cond.getValueType()));
12351 // Zero extend the condition if needed.
12352 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12354 // Scale the condition by the difference.
12356 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12357 DAG.getConstant(Diff, Cond.getValueType()));
12359 // Add the base if non-zero.
12360 if (FalseC->getAPIntValue() != 0)
12361 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12362 SDValue(FalseC, 0));
12372 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12373 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12374 TargetLowering::DAGCombinerInfo &DCI) {
12375 DebugLoc DL = N->getDebugLoc();
12377 // If the flag operand isn't dead, don't touch this CMOV.
12378 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12381 SDValue FalseOp = N->getOperand(0);
12382 SDValue TrueOp = N->getOperand(1);
12383 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12384 SDValue Cond = N->getOperand(3);
12385 if (CC == X86::COND_E || CC == X86::COND_NE) {
12386 switch (Cond.getOpcode()) {
12390 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12391 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12392 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12396 // If this is a select between two integer constants, try to do some
12397 // optimizations. Note that the operands are ordered the opposite of SELECT
12399 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12400 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12401 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12402 // larger than FalseC (the false value).
12403 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12404 CC = X86::GetOppositeBranchCondition(CC);
12405 std::swap(TrueC, FalseC);
12408 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12409 // This is efficient for any integer data type (including i8/i16) and
12411 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12412 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12413 DAG.getConstant(CC, MVT::i8), Cond);
12415 // Zero extend the condition if needed.
12416 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12418 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12419 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12420 DAG.getConstant(ShAmt, MVT::i8));
12421 if (N->getNumValues() == 2) // Dead flag value?
12422 return DCI.CombineTo(N, Cond, SDValue());
12426 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12427 // for any integer data type, including i8/i16.
12428 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12429 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12430 DAG.getConstant(CC, MVT::i8), Cond);
12432 // Zero extend the condition if needed.
12433 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12434 FalseC->getValueType(0), Cond);
12435 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12436 SDValue(FalseC, 0));
12438 if (N->getNumValues() == 2) // Dead flag value?
12439 return DCI.CombineTo(N, Cond, SDValue());
12443 // Optimize cases that will turn into an LEA instruction. This requires
12444 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12445 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12446 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12447 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12449 bool isFastMultiplier = false;
12451 switch ((unsigned char)Diff) {
12453 case 1: // result = add base, cond
12454 case 2: // result = lea base( , cond*2)
12455 case 3: // result = lea base(cond, cond*2)
12456 case 4: // result = lea base( , cond*4)
12457 case 5: // result = lea base(cond, cond*4)
12458 case 8: // result = lea base( , cond*8)
12459 case 9: // result = lea base(cond, cond*8)
12460 isFastMultiplier = true;
12465 if (isFastMultiplier) {
12466 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12467 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12468 DAG.getConstant(CC, MVT::i8), Cond);
12469 // Zero extend the condition if needed.
12470 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12472 // Scale the condition by the difference.
12474 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12475 DAG.getConstant(Diff, Cond.getValueType()));
12477 // Add the base if non-zero.
12478 if (FalseC->getAPIntValue() != 0)
12479 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12480 SDValue(FalseC, 0));
12481 if (N->getNumValues() == 2) // Dead flag value?
12482 return DCI.CombineTo(N, Cond, SDValue());
12492 /// PerformMulCombine - Optimize a single multiply with constant into two
12493 /// in order to implement it with two cheaper instructions, e.g.
12494 /// LEA + SHL, LEA + LEA.
12495 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12496 TargetLowering::DAGCombinerInfo &DCI) {
12497 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12500 EVT VT = N->getValueType(0);
12501 if (VT != MVT::i64)
12504 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12507 uint64_t MulAmt = C->getZExtValue();
12508 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12511 uint64_t MulAmt1 = 0;
12512 uint64_t MulAmt2 = 0;
12513 if ((MulAmt % 9) == 0) {
12515 MulAmt2 = MulAmt / 9;
12516 } else if ((MulAmt % 5) == 0) {
12518 MulAmt2 = MulAmt / 5;
12519 } else if ((MulAmt % 3) == 0) {
12521 MulAmt2 = MulAmt / 3;
12524 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12525 DebugLoc DL = N->getDebugLoc();
12527 if (isPowerOf2_64(MulAmt2) &&
12528 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12529 // If second multiplifer is pow2, issue it first. We want the multiply by
12530 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12532 std::swap(MulAmt1, MulAmt2);
12535 if (isPowerOf2_64(MulAmt1))
12536 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12537 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12539 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12540 DAG.getConstant(MulAmt1, VT));
12542 if (isPowerOf2_64(MulAmt2))
12543 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12544 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12546 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12547 DAG.getConstant(MulAmt2, VT));
12549 // Do not add new nodes to DAG combiner worklist.
12550 DCI.CombineTo(N, NewMul, false);
12555 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12556 SDValue N0 = N->getOperand(0);
12557 SDValue N1 = N->getOperand(1);
12558 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12559 EVT VT = N0.getValueType();
12561 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12562 // since the result of setcc_c is all zero's or all ones.
12563 if (N1C && N0.getOpcode() == ISD::AND &&
12564 N0.getOperand(1).getOpcode() == ISD::Constant) {
12565 SDValue N00 = N0.getOperand(0);
12566 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12567 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12568 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12569 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12570 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12571 APInt ShAmt = N1C->getAPIntValue();
12572 Mask = Mask.shl(ShAmt);
12574 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12575 N00, DAG.getConstant(Mask, VT));
12582 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
12584 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
12585 const X86Subtarget *Subtarget) {
12586 EVT VT = N->getValueType(0);
12587 if (!VT.isVector() && VT.isInteger() &&
12588 N->getOpcode() == ISD::SHL)
12589 return PerformSHLCombine(N, DAG);
12591 // On X86 with SSE2 support, we can transform this to a vector shift if
12592 // all elements are shifted by the same amount. We can't do this in legalize
12593 // because the a constant vector is typically transformed to a constant pool
12594 // so we have no knowledge of the shift amount.
12595 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
12598 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
12601 SDValue ShAmtOp = N->getOperand(1);
12602 EVT EltVT = VT.getVectorElementType();
12603 DebugLoc DL = N->getDebugLoc();
12604 SDValue BaseShAmt = SDValue();
12605 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
12606 unsigned NumElts = VT.getVectorNumElements();
12608 for (; i != NumElts; ++i) {
12609 SDValue Arg = ShAmtOp.getOperand(i);
12610 if (Arg.getOpcode() == ISD::UNDEF) continue;
12614 for (; i != NumElts; ++i) {
12615 SDValue Arg = ShAmtOp.getOperand(i);
12616 if (Arg.getOpcode() == ISD::UNDEF) continue;
12617 if (Arg != BaseShAmt) {
12621 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
12622 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
12623 SDValue InVec = ShAmtOp.getOperand(0);
12624 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12625 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12627 for (; i != NumElts; ++i) {
12628 SDValue Arg = InVec.getOperand(i);
12629 if (Arg.getOpcode() == ISD::UNDEF) continue;
12633 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12634 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12635 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
12636 if (C->getZExtValue() == SplatIdx)
12637 BaseShAmt = InVec.getOperand(1);
12640 if (BaseShAmt.getNode() == 0)
12641 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
12642 DAG.getIntPtrConstant(0));
12646 // The shift amount is an i32.
12647 if (EltVT.bitsGT(MVT::i32))
12648 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
12649 else if (EltVT.bitsLT(MVT::i32))
12650 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
12652 // The shift amount is identical so we can do a vector shift.
12653 SDValue ValOp = N->getOperand(0);
12654 switch (N->getOpcode()) {
12656 llvm_unreachable("Unknown shift opcode!");
12659 if (VT == MVT::v2i64)
12660 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12661 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
12663 if (VT == MVT::v4i32)
12664 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12665 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
12667 if (VT == MVT::v8i16)
12668 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12669 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
12673 if (VT == MVT::v4i32)
12674 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12675 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
12677 if (VT == MVT::v8i16)
12678 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12679 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
12683 if (VT == MVT::v2i64)
12684 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12685 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
12687 if (VT == MVT::v4i32)
12688 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12689 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
12691 if (VT == MVT::v8i16)
12692 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12693 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
12701 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
12702 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
12703 // and friends. Likewise for OR -> CMPNEQSS.
12704 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
12705 TargetLowering::DAGCombinerInfo &DCI,
12706 const X86Subtarget *Subtarget) {
12709 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
12710 // we're requiring SSE2 for both.
12711 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
12712 SDValue N0 = N->getOperand(0);
12713 SDValue N1 = N->getOperand(1);
12714 SDValue CMP0 = N0->getOperand(1);
12715 SDValue CMP1 = N1->getOperand(1);
12716 DebugLoc DL = N->getDebugLoc();
12718 // The SETCCs should both refer to the same CMP.
12719 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
12722 SDValue CMP00 = CMP0->getOperand(0);
12723 SDValue CMP01 = CMP0->getOperand(1);
12724 EVT VT = CMP00.getValueType();
12726 if (VT == MVT::f32 || VT == MVT::f64) {
12727 bool ExpectingFlags = false;
12728 // Check for any users that want flags:
12729 for (SDNode::use_iterator UI = N->use_begin(),
12731 !ExpectingFlags && UI != UE; ++UI)
12732 switch (UI->getOpcode()) {
12737 ExpectingFlags = true;
12739 case ISD::CopyToReg:
12740 case ISD::SIGN_EXTEND:
12741 case ISD::ZERO_EXTEND:
12742 case ISD::ANY_EXTEND:
12746 if (!ExpectingFlags) {
12747 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
12748 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
12750 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
12751 X86::CondCode tmp = cc0;
12756 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
12757 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
12758 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
12759 X86ISD::NodeType NTOperator = is64BitFP ?
12760 X86ISD::FSETCCsd : X86ISD::FSETCCss;
12761 // FIXME: need symbolic constants for these magic numbers.
12762 // See X86ATTInstPrinter.cpp:printSSECC().
12763 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
12764 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
12765 DAG.getConstant(x86cc, MVT::i8));
12766 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
12768 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
12769 DAG.getConstant(1, MVT::i32));
12770 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
12771 return OneBitOfTruth;
12779 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
12780 /// so it can be folded inside ANDNP.
12781 static bool CanFoldXORWithAllOnes(const SDNode *N) {
12782 EVT VT = N->getValueType(0);
12784 // Match direct AllOnes for 128 and 256-bit vectors
12785 if (ISD::isBuildVectorAllOnes(N))
12788 // Look through a bit convert.
12789 if (N->getOpcode() == ISD::BITCAST)
12790 N = N->getOperand(0).getNode();
12792 // Sometimes the operand may come from a insert_subvector building a 256-bit
12794 if (VT.getSizeInBits() == 256 &&
12795 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
12796 SDValue V1 = N->getOperand(0);
12797 SDValue V2 = N->getOperand(1);
12799 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
12800 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
12801 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
12802 ISD::isBuildVectorAllOnes(V2.getNode()))
12809 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
12810 TargetLowering::DAGCombinerInfo &DCI,
12811 const X86Subtarget *Subtarget) {
12812 if (DCI.isBeforeLegalizeOps())
12815 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12819 // Want to form ANDNP nodes:
12820 // 1) In the hopes of then easily combining them with OR and AND nodes
12821 // to form PBLEND/PSIGN.
12822 // 2) To match ANDN packed intrinsics
12823 EVT VT = N->getValueType(0);
12824 if (VT != MVT::v2i64 && VT != MVT::v4i64)
12827 SDValue N0 = N->getOperand(0);
12828 SDValue N1 = N->getOperand(1);
12829 DebugLoc DL = N->getDebugLoc();
12831 // Check LHS for vnot
12832 if (N0.getOpcode() == ISD::XOR &&
12833 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
12834 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
12835 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
12837 // Check RHS for vnot
12838 if (N1.getOpcode() == ISD::XOR &&
12839 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
12840 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
12841 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
12846 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
12847 TargetLowering::DAGCombinerInfo &DCI,
12848 const X86Subtarget *Subtarget) {
12849 if (DCI.isBeforeLegalizeOps())
12852 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12856 EVT VT = N->getValueType(0);
12857 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
12860 SDValue N0 = N->getOperand(0);
12861 SDValue N1 = N->getOperand(1);
12863 // look for psign/blend
12864 if (Subtarget->hasSSSE3()) {
12865 if (VT == MVT::v2i64) {
12866 // Canonicalize pandn to RHS
12867 if (N0.getOpcode() == X86ISD::ANDNP)
12869 // or (and (m, x), (pandn m, y))
12870 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
12871 SDValue Mask = N1.getOperand(0);
12872 SDValue X = N1.getOperand(1);
12874 if (N0.getOperand(0) == Mask)
12875 Y = N0.getOperand(1);
12876 if (N0.getOperand(1) == Mask)
12877 Y = N0.getOperand(0);
12879 // Check to see if the mask appeared in both the AND and ANDNP and
12883 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
12884 if (Mask.getOpcode() != ISD::BITCAST ||
12885 X.getOpcode() != ISD::BITCAST ||
12886 Y.getOpcode() != ISD::BITCAST)
12889 // Look through mask bitcast.
12890 Mask = Mask.getOperand(0);
12891 EVT MaskVT = Mask.getValueType();
12893 // Validate that the Mask operand is a vector sra node. The sra node
12894 // will be an intrinsic.
12895 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
12898 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
12899 // there is no psrai.b
12900 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
12901 case Intrinsic::x86_sse2_psrai_w:
12902 case Intrinsic::x86_sse2_psrai_d:
12904 default: return SDValue();
12907 // Check that the SRA is all signbits.
12908 SDValue SraC = Mask.getOperand(2);
12909 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
12910 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
12911 if ((SraAmt + 1) != EltBits)
12914 DebugLoc DL = N->getDebugLoc();
12916 // Now we know we at least have a plendvb with the mask val. See if
12917 // we can form a psignb/w/d.
12918 // psign = x.type == y.type == mask.type && y = sub(0, x);
12919 X = X.getOperand(0);
12920 Y = Y.getOperand(0);
12921 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
12922 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
12923 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
12926 case 8: Opc = X86ISD::PSIGNB; break;
12927 case 16: Opc = X86ISD::PSIGNW; break;
12928 case 32: Opc = X86ISD::PSIGND; break;
12932 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
12933 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
12936 // PBLENDVB only available on SSE 4.1
12937 if (!Subtarget->hasSSE41())
12940 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
12941 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
12942 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
12943 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
12944 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
12949 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
12950 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
12952 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
12954 if (!N0.hasOneUse() || !N1.hasOneUse())
12957 SDValue ShAmt0 = N0.getOperand(1);
12958 if (ShAmt0.getValueType() != MVT::i8)
12960 SDValue ShAmt1 = N1.getOperand(1);
12961 if (ShAmt1.getValueType() != MVT::i8)
12963 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
12964 ShAmt0 = ShAmt0.getOperand(0);
12965 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
12966 ShAmt1 = ShAmt1.getOperand(0);
12968 DebugLoc DL = N->getDebugLoc();
12969 unsigned Opc = X86ISD::SHLD;
12970 SDValue Op0 = N0.getOperand(0);
12971 SDValue Op1 = N1.getOperand(0);
12972 if (ShAmt0.getOpcode() == ISD::SUB) {
12973 Opc = X86ISD::SHRD;
12974 std::swap(Op0, Op1);
12975 std::swap(ShAmt0, ShAmt1);
12978 unsigned Bits = VT.getSizeInBits();
12979 if (ShAmt1.getOpcode() == ISD::SUB) {
12980 SDValue Sum = ShAmt1.getOperand(0);
12981 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
12982 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
12983 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
12984 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
12985 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
12986 return DAG.getNode(Opc, DL, VT,
12988 DAG.getNode(ISD::TRUNCATE, DL,
12991 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
12992 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
12994 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
12995 return DAG.getNode(Opc, DL, VT,
12996 N0.getOperand(0), N1.getOperand(0),
12997 DAG.getNode(ISD::TRUNCATE, DL,
13004 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13005 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13006 const X86Subtarget *Subtarget) {
13007 StoreSDNode *St = cast<StoreSDNode>(N);
13008 EVT VT = St->getValue().getValueType();
13009 EVT StVT = St->getMemoryVT();
13010 DebugLoc dl = St->getDebugLoc();
13011 SDValue StoredVal = St->getOperand(1);
13012 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13014 // If we are saving a concatination of two XMM registers, perform two stores.
13015 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13016 // 128-bit ones. If in the future the cost becomes only one memory access the
13017 // first version would be better.
13018 if (VT.getSizeInBits() == 256 &&
13019 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13020 StoredVal.getNumOperands() == 2) {
13022 SDValue Value0 = StoredVal.getOperand(0);
13023 SDValue Value1 = StoredVal.getOperand(1);
13025 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13026 SDValue Ptr0 = St->getBasePtr();
13027 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13029 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13030 St->getPointerInfo(), St->isVolatile(),
13031 St->isNonTemporal(), St->getAlignment());
13032 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13033 St->getPointerInfo(), St->isVolatile(),
13034 St->isNonTemporal(), St->getAlignment());
13035 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13038 // Optimize trunc store (of multiple scalars) to shuffle and store.
13039 // First, pack all of the elements in one place. Next, store to memory
13040 // in fewer chunks.
13041 if (St->isTruncatingStore() && VT.isVector()) {
13042 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13043 unsigned NumElems = VT.getVectorNumElements();
13044 assert(StVT != VT && "Cannot truncate to the same type");
13045 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13046 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13048 // From, To sizes and ElemCount must be pow of two
13049 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13050 // We are going to use the original vector elt for storing.
13051 // accumulated smaller vector elements must be a multiple of bigger size.
13052 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
13053 unsigned SizeRatio = FromSz / ToSz;
13055 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13057 // Create a type on which we perform the shuffle
13058 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13059 StVT.getScalarType(), NumElems*SizeRatio);
13061 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13063 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13064 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13065 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13067 // Can't shuffle using an illegal type
13068 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13070 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13071 DAG.getUNDEF(WideVec.getValueType()),
13072 ShuffleVec.data());
13073 // At this point all of the data is stored at the bottom of the
13074 // register. We now need to save it to mem.
13076 // Find the largest store unit
13077 MVT StoreType = MVT::i8;
13078 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13079 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13080 MVT Tp = (MVT::SimpleValueType)tp;
13081 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
13085 // Bitcast the original vector into a vector of store-size units
13086 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
13087 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
13088 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
13089 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
13090 SmallVector<SDValue, 8> Chains;
13091 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
13092 TLI.getPointerTy());
13093 SDValue Ptr = St->getBasePtr();
13095 // Perform one or more big stores into memory.
13096 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
13097 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13098 StoreType, ShuffWide,
13099 DAG.getIntPtrConstant(i));
13100 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
13101 St->getPointerInfo(), St->isVolatile(),
13102 St->isNonTemporal(), St->getAlignment());
13103 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13104 Chains.push_back(Ch);
13107 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
13112 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
13113 // the FP state in cases where an emms may be missing.
13114 // A preferable solution to the general problem is to figure out the right
13115 // places to insert EMMS. This qualifies as a quick hack.
13117 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13118 if (VT.getSizeInBits() != 64)
13121 const Function *F = DAG.getMachineFunction().getFunction();
13122 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13123 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13124 && Subtarget->hasSSE2();
13125 if ((VT.isVector() ||
13126 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13127 isa<LoadSDNode>(St->getValue()) &&
13128 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13129 St->getChain().hasOneUse() && !St->isVolatile()) {
13130 SDNode* LdVal = St->getValue().getNode();
13131 LoadSDNode *Ld = 0;
13132 int TokenFactorIndex = -1;
13133 SmallVector<SDValue, 8> Ops;
13134 SDNode* ChainVal = St->getChain().getNode();
13135 // Must be a store of a load. We currently handle two cases: the load
13136 // is a direct child, and it's under an intervening TokenFactor. It is
13137 // possible to dig deeper under nested TokenFactors.
13138 if (ChainVal == LdVal)
13139 Ld = cast<LoadSDNode>(St->getChain());
13140 else if (St->getValue().hasOneUse() &&
13141 ChainVal->getOpcode() == ISD::TokenFactor) {
13142 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13143 if (ChainVal->getOperand(i).getNode() == LdVal) {
13144 TokenFactorIndex = i;
13145 Ld = cast<LoadSDNode>(St->getValue());
13147 Ops.push_back(ChainVal->getOperand(i));
13151 if (!Ld || !ISD::isNormalLoad(Ld))
13154 // If this is not the MMX case, i.e. we are just turning i64 load/store
13155 // into f64 load/store, avoid the transformation if there are multiple
13156 // uses of the loaded value.
13157 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13160 DebugLoc LdDL = Ld->getDebugLoc();
13161 DebugLoc StDL = N->getDebugLoc();
13162 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13163 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13165 if (Subtarget->is64Bit() || F64IsLegal) {
13166 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13167 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13168 Ld->getPointerInfo(), Ld->isVolatile(),
13169 Ld->isNonTemporal(), Ld->getAlignment());
13170 SDValue NewChain = NewLd.getValue(1);
13171 if (TokenFactorIndex != -1) {
13172 Ops.push_back(NewChain);
13173 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13176 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13177 St->getPointerInfo(),
13178 St->isVolatile(), St->isNonTemporal(),
13179 St->getAlignment());
13182 // Otherwise, lower to two pairs of 32-bit loads / stores.
13183 SDValue LoAddr = Ld->getBasePtr();
13184 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13185 DAG.getConstant(4, MVT::i32));
13187 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13188 Ld->getPointerInfo(),
13189 Ld->isVolatile(), Ld->isNonTemporal(),
13190 Ld->getAlignment());
13191 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13192 Ld->getPointerInfo().getWithOffset(4),
13193 Ld->isVolatile(), Ld->isNonTemporal(),
13194 MinAlign(Ld->getAlignment(), 4));
13196 SDValue NewChain = LoLd.getValue(1);
13197 if (TokenFactorIndex != -1) {
13198 Ops.push_back(LoLd);
13199 Ops.push_back(HiLd);
13200 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13204 LoAddr = St->getBasePtr();
13205 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13206 DAG.getConstant(4, MVT::i32));
13208 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13209 St->getPointerInfo(),
13210 St->isVolatile(), St->isNonTemporal(),
13211 St->getAlignment());
13212 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13213 St->getPointerInfo().getWithOffset(4),
13215 St->isNonTemporal(),
13216 MinAlign(St->getAlignment(), 4));
13217 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13222 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13223 /// X86ISD::FXOR nodes.
13224 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13225 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13226 // F[X]OR(0.0, x) -> x
13227 // F[X]OR(x, 0.0) -> x
13228 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13229 if (C->getValueAPF().isPosZero())
13230 return N->getOperand(1);
13231 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13232 if (C->getValueAPF().isPosZero())
13233 return N->getOperand(0);
13237 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13238 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13239 // FAND(0.0, x) -> 0.0
13240 // FAND(x, 0.0) -> 0.0
13241 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13242 if (C->getValueAPF().isPosZero())
13243 return N->getOperand(0);
13244 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13245 if (C->getValueAPF().isPosZero())
13246 return N->getOperand(1);
13250 static SDValue PerformBTCombine(SDNode *N,
13252 TargetLowering::DAGCombinerInfo &DCI) {
13253 // BT ignores high bits in the bit index operand.
13254 SDValue Op1 = N->getOperand(1);
13255 if (Op1.hasOneUse()) {
13256 unsigned BitWidth = Op1.getValueSizeInBits();
13257 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13258 APInt KnownZero, KnownOne;
13259 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13260 !DCI.isBeforeLegalizeOps());
13261 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13262 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13263 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13264 DCI.CommitTargetLoweringOpt(TLO);
13269 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13270 SDValue Op = N->getOperand(0);
13271 if (Op.getOpcode() == ISD::BITCAST)
13272 Op = Op.getOperand(0);
13273 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13274 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13275 VT.getVectorElementType().getSizeInBits() ==
13276 OpVT.getVectorElementType().getSizeInBits()) {
13277 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13282 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13283 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13284 // (and (i32 x86isd::setcc_carry), 1)
13285 // This eliminates the zext. This transformation is necessary because
13286 // ISD::SETCC is always legalized to i8.
13287 DebugLoc dl = N->getDebugLoc();
13288 SDValue N0 = N->getOperand(0);
13289 EVT VT = N->getValueType(0);
13290 if (N0.getOpcode() == ISD::AND &&
13292 N0.getOperand(0).hasOneUse()) {
13293 SDValue N00 = N0.getOperand(0);
13294 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13296 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13297 if (!C || C->getZExtValue() != 1)
13299 return DAG.getNode(ISD::AND, dl, VT,
13300 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13301 N00.getOperand(0), N00.getOperand(1)),
13302 DAG.getConstant(1, VT));
13308 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13309 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13310 unsigned X86CC = N->getConstantOperandVal(0);
13311 SDValue EFLAG = N->getOperand(1);
13312 DebugLoc DL = N->getDebugLoc();
13314 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13315 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13317 if (X86CC == X86::COND_B)
13318 return DAG.getNode(ISD::AND, DL, MVT::i8,
13319 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13320 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13321 DAG.getConstant(1, MVT::i8));
13326 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13327 const X86TargetLowering *XTLI) {
13328 SDValue Op0 = N->getOperand(0);
13329 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13330 // a 32-bit target where SSE doesn't support i64->FP operations.
13331 if (Op0.getOpcode() == ISD::LOAD) {
13332 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13333 EVT VT = Ld->getValueType(0);
13334 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13335 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13336 !XTLI->getSubtarget()->is64Bit() &&
13337 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13338 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13339 Ld->getChain(), Op0, DAG);
13340 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13347 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13348 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13349 X86TargetLowering::DAGCombinerInfo &DCI) {
13350 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13351 // the result is either zero or one (depending on the input carry bit).
13352 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13353 if (X86::isZeroNode(N->getOperand(0)) &&
13354 X86::isZeroNode(N->getOperand(1)) &&
13355 // We don't have a good way to replace an EFLAGS use, so only do this when
13357 SDValue(N, 1).use_empty()) {
13358 DebugLoc DL = N->getDebugLoc();
13359 EVT VT = N->getValueType(0);
13360 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13361 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13362 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13363 DAG.getConstant(X86::COND_B,MVT::i8),
13365 DAG.getConstant(1, VT));
13366 return DCI.CombineTo(N, Res1, CarryOut);
13372 // fold (add Y, (sete X, 0)) -> adc 0, Y
13373 // (add Y, (setne X, 0)) -> sbb -1, Y
13374 // (sub (sete X, 0), Y) -> sbb 0, Y
13375 // (sub (setne X, 0), Y) -> adc -1, Y
13376 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13377 DebugLoc DL = N->getDebugLoc();
13379 // Look through ZExts.
13380 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13381 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13384 SDValue SetCC = Ext.getOperand(0);
13385 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13388 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13389 if (CC != X86::COND_E && CC != X86::COND_NE)
13392 SDValue Cmp = SetCC.getOperand(1);
13393 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13394 !X86::isZeroNode(Cmp.getOperand(1)) ||
13395 !Cmp.getOperand(0).getValueType().isInteger())
13398 SDValue CmpOp0 = Cmp.getOperand(0);
13399 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13400 DAG.getConstant(1, CmpOp0.getValueType()));
13402 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13403 if (CC == X86::COND_NE)
13404 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13405 DL, OtherVal.getValueType(), OtherVal,
13406 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13407 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13408 DL, OtherVal.getValueType(), OtherVal,
13409 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13412 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13413 SDValue Op0 = N->getOperand(0);
13414 SDValue Op1 = N->getOperand(1);
13416 // X86 can't encode an immediate LHS of a sub. See if we can push the
13417 // negation into a preceding instruction.
13418 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13419 // If the RHS of the sub is a XOR with one use and a constant, invert the
13420 // immediate. Then add one to the LHS of the sub so we can turn
13421 // X-Y -> X+~Y+1, saving one register.
13422 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13423 isa<ConstantSDNode>(Op1.getOperand(1))) {
13424 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
13425 EVT VT = Op0.getValueType();
13426 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13428 DAG.getConstant(~XorC, VT));
13429 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13430 DAG.getConstant(C->getAPIntValue()+1, VT));
13434 return OptimizeConditionalInDecrement(N, DAG);
13437 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13438 DAGCombinerInfo &DCI) const {
13439 SelectionDAG &DAG = DCI.DAG;
13440 switch (N->getOpcode()) {
13442 case ISD::EXTRACT_VECTOR_ELT:
13443 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13444 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13445 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13446 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13447 case ISD::SUB: return PerformSubCombine(N, DAG);
13448 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13449 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13452 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13453 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13454 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13455 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13456 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13458 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13459 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13460 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13461 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13462 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13463 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13464 case X86ISD::SHUFPS: // Handle all target specific shuffles
13465 case X86ISD::SHUFPD:
13466 case X86ISD::PALIGN:
13467 case X86ISD::PUNPCKHBW:
13468 case X86ISD::PUNPCKHWD:
13469 case X86ISD::PUNPCKHDQ:
13470 case X86ISD::PUNPCKHQDQ:
13471 case X86ISD::UNPCKHPS:
13472 case X86ISD::UNPCKHPD:
13473 case X86ISD::VUNPCKHPSY:
13474 case X86ISD::VUNPCKHPDY:
13475 case X86ISD::PUNPCKLBW:
13476 case X86ISD::PUNPCKLWD:
13477 case X86ISD::PUNPCKLDQ:
13478 case X86ISD::PUNPCKLQDQ:
13479 case X86ISD::UNPCKLPS:
13480 case X86ISD::UNPCKLPD:
13481 case X86ISD::VUNPCKLPSY:
13482 case X86ISD::VUNPCKLPDY:
13483 case X86ISD::MOVHLPS:
13484 case X86ISD::MOVLHPS:
13485 case X86ISD::PSHUFD:
13486 case X86ISD::PSHUFHW:
13487 case X86ISD::PSHUFLW:
13488 case X86ISD::MOVSS:
13489 case X86ISD::MOVSD:
13490 case X86ISD::VPERMILPS:
13491 case X86ISD::VPERMILPSY:
13492 case X86ISD::VPERMILPD:
13493 case X86ISD::VPERMILPDY:
13494 case X86ISD::VPERM2F128:
13495 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
13501 /// isTypeDesirableForOp - Return true if the target has native support for
13502 /// the specified value type and it is 'desirable' to use the type for the
13503 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13504 /// instruction encodings are longer and some i16 instructions are slow.
13505 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13506 if (!isTypeLegal(VT))
13508 if (VT != MVT::i16)
13515 case ISD::SIGN_EXTEND:
13516 case ISD::ZERO_EXTEND:
13517 case ISD::ANY_EXTEND:
13530 /// IsDesirableToPromoteOp - This method query the target whether it is
13531 /// beneficial for dag combiner to promote the specified node. If true, it
13532 /// should return the desired promotion type by reference.
13533 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13534 EVT VT = Op.getValueType();
13535 if (VT != MVT::i16)
13538 bool Promote = false;
13539 bool Commute = false;
13540 switch (Op.getOpcode()) {
13543 LoadSDNode *LD = cast<LoadSDNode>(Op);
13544 // If the non-extending load has a single use and it's not live out, then it
13545 // might be folded.
13546 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13547 Op.hasOneUse()*/) {
13548 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13549 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13550 // The only case where we'd want to promote LOAD (rather then it being
13551 // promoted as an operand is when it's only use is liveout.
13552 if (UI->getOpcode() != ISD::CopyToReg)
13559 case ISD::SIGN_EXTEND:
13560 case ISD::ZERO_EXTEND:
13561 case ISD::ANY_EXTEND:
13566 SDValue N0 = Op.getOperand(0);
13567 // Look out for (store (shl (load), x)).
13568 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13581 SDValue N0 = Op.getOperand(0);
13582 SDValue N1 = Op.getOperand(1);
13583 if (!Commute && MayFoldLoad(N1))
13585 // Avoid disabling potential load folding opportunities.
13586 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
13588 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
13598 //===----------------------------------------------------------------------===//
13599 // X86 Inline Assembly Support
13600 //===----------------------------------------------------------------------===//
13602 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
13603 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
13605 std::string AsmStr = IA->getAsmString();
13607 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
13608 SmallVector<StringRef, 4> AsmPieces;
13609 SplitString(AsmStr, AsmPieces, ";\n");
13611 switch (AsmPieces.size()) {
13612 default: return false;
13614 AsmStr = AsmPieces[0];
13616 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
13618 // FIXME: this should verify that we are targeting a 486 or better. If not,
13619 // we will turn this bswap into something that will be lowered to logical ops
13620 // instead of emitting the bswap asm. For now, we don't support 486 or lower
13621 // so don't worry about this.
13623 if (AsmPieces.size() == 2 &&
13624 (AsmPieces[0] == "bswap" ||
13625 AsmPieces[0] == "bswapq" ||
13626 AsmPieces[0] == "bswapl") &&
13627 (AsmPieces[1] == "$0" ||
13628 AsmPieces[1] == "${0:q}")) {
13629 // No need to check constraints, nothing other than the equivalent of
13630 // "=r,0" would be valid here.
13631 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13632 if (!Ty || Ty->getBitWidth() % 16 != 0)
13634 return IntrinsicLowering::LowerToByteSwap(CI);
13636 // rorw $$8, ${0:w} --> llvm.bswap.i16
13637 if (CI->getType()->isIntegerTy(16) &&
13638 AsmPieces.size() == 3 &&
13639 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
13640 AsmPieces[1] == "$$8," &&
13641 AsmPieces[2] == "${0:w}" &&
13642 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13644 const std::string &ConstraintsStr = IA->getConstraintString();
13645 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13646 std::sort(AsmPieces.begin(), AsmPieces.end());
13647 if (AsmPieces.size() == 4 &&
13648 AsmPieces[0] == "~{cc}" &&
13649 AsmPieces[1] == "~{dirflag}" &&
13650 AsmPieces[2] == "~{flags}" &&
13651 AsmPieces[3] == "~{fpsr}") {
13652 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13653 if (!Ty || Ty->getBitWidth() % 16 != 0)
13655 return IntrinsicLowering::LowerToByteSwap(CI);
13660 if (CI->getType()->isIntegerTy(32) &&
13661 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13662 SmallVector<StringRef, 4> Words;
13663 SplitString(AsmPieces[0], Words, " \t,");
13664 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13665 Words[2] == "${0:w}") {
13667 SplitString(AsmPieces[1], Words, " \t,");
13668 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
13669 Words[2] == "$0") {
13671 SplitString(AsmPieces[2], Words, " \t,");
13672 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13673 Words[2] == "${0:w}") {
13675 const std::string &ConstraintsStr = IA->getConstraintString();
13676 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13677 std::sort(AsmPieces.begin(), AsmPieces.end());
13678 if (AsmPieces.size() == 4 &&
13679 AsmPieces[0] == "~{cc}" &&
13680 AsmPieces[1] == "~{dirflag}" &&
13681 AsmPieces[2] == "~{flags}" &&
13682 AsmPieces[3] == "~{fpsr}") {
13683 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13684 if (!Ty || Ty->getBitWidth() % 16 != 0)
13686 return IntrinsicLowering::LowerToByteSwap(CI);
13693 if (CI->getType()->isIntegerTy(64)) {
13694 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
13695 if (Constraints.size() >= 2 &&
13696 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
13697 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
13698 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
13699 SmallVector<StringRef, 4> Words;
13700 SplitString(AsmPieces[0], Words, " \t");
13701 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
13703 SplitString(AsmPieces[1], Words, " \t");
13704 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
13706 SplitString(AsmPieces[2], Words, " \t,");
13707 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
13708 Words[2] == "%edx") {
13709 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13710 if (!Ty || Ty->getBitWidth() % 16 != 0)
13712 return IntrinsicLowering::LowerToByteSwap(CI);
13725 /// getConstraintType - Given a constraint letter, return the type of
13726 /// constraint it is for this target.
13727 X86TargetLowering::ConstraintType
13728 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
13729 if (Constraint.size() == 1) {
13730 switch (Constraint[0]) {
13741 return C_RegisterClass;
13765 return TargetLowering::getConstraintType(Constraint);
13768 /// Examine constraint type and operand type and determine a weight value.
13769 /// This object must already have been set up with the operand type
13770 /// and the current alternative constraint selected.
13771 TargetLowering::ConstraintWeight
13772 X86TargetLowering::getSingleConstraintMatchWeight(
13773 AsmOperandInfo &info, const char *constraint) const {
13774 ConstraintWeight weight = CW_Invalid;
13775 Value *CallOperandVal = info.CallOperandVal;
13776 // If we don't have a value, we can't do a match,
13777 // but allow it at the lowest weight.
13778 if (CallOperandVal == NULL)
13780 Type *type = CallOperandVal->getType();
13781 // Look at the constraint type.
13782 switch (*constraint) {
13784 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
13795 if (CallOperandVal->getType()->isIntegerTy())
13796 weight = CW_SpecificReg;
13801 if (type->isFloatingPointTy())
13802 weight = CW_SpecificReg;
13805 if (type->isX86_MMXTy() && Subtarget->hasMMX())
13806 weight = CW_SpecificReg;
13810 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
13811 weight = CW_Register;
13814 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
13815 if (C->getZExtValue() <= 31)
13816 weight = CW_Constant;
13820 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13821 if (C->getZExtValue() <= 63)
13822 weight = CW_Constant;
13826 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13827 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
13828 weight = CW_Constant;
13832 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13833 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
13834 weight = CW_Constant;
13838 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13839 if (C->getZExtValue() <= 3)
13840 weight = CW_Constant;
13844 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13845 if (C->getZExtValue() <= 0xff)
13846 weight = CW_Constant;
13851 if (dyn_cast<ConstantFP>(CallOperandVal)) {
13852 weight = CW_Constant;
13856 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13857 if ((C->getSExtValue() >= -0x80000000LL) &&
13858 (C->getSExtValue() <= 0x7fffffffLL))
13859 weight = CW_Constant;
13863 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13864 if (C->getZExtValue() <= 0xffffffff)
13865 weight = CW_Constant;
13872 /// LowerXConstraint - try to replace an X constraint, which matches anything,
13873 /// with another that has more specific requirements based on the type of the
13874 /// corresponding operand.
13875 const char *X86TargetLowering::
13876 LowerXConstraint(EVT ConstraintVT) const {
13877 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
13878 // 'f' like normal targets.
13879 if (ConstraintVT.isFloatingPoint()) {
13880 if (Subtarget->hasXMMInt())
13882 if (Subtarget->hasXMM())
13886 return TargetLowering::LowerXConstraint(ConstraintVT);
13889 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
13890 /// vector. If it is invalid, don't add anything to Ops.
13891 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
13892 std::string &Constraint,
13893 std::vector<SDValue>&Ops,
13894 SelectionDAG &DAG) const {
13895 SDValue Result(0, 0);
13897 // Only support length 1 constraints for now.
13898 if (Constraint.length() > 1) return;
13900 char ConstraintLetter = Constraint[0];
13901 switch (ConstraintLetter) {
13904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13905 if (C->getZExtValue() <= 31) {
13906 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13912 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13913 if (C->getZExtValue() <= 63) {
13914 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13920 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13921 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
13922 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13928 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13929 if (C->getZExtValue() <= 255) {
13930 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13936 // 32-bit signed value
13937 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13938 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13939 C->getSExtValue())) {
13940 // Widen to 64 bits here to get it sign extended.
13941 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
13944 // FIXME gcc accepts some relocatable values here too, but only in certain
13945 // memory models; it's complicated.
13950 // 32-bit unsigned value
13951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13952 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13953 C->getZExtValue())) {
13954 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13958 // FIXME gcc accepts some relocatable values here too, but only in certain
13959 // memory models; it's complicated.
13963 // Literal immediates are always ok.
13964 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
13965 // Widen to 64 bits here to get it sign extended.
13966 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
13970 // In any sort of PIC mode addresses need to be computed at runtime by
13971 // adding in a register or some sort of table lookup. These can't
13972 // be used as immediates.
13973 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
13976 // If we are in non-pic codegen mode, we allow the address of a global (with
13977 // an optional displacement) to be used with 'i'.
13978 GlobalAddressSDNode *GA = 0;
13979 int64_t Offset = 0;
13981 // Match either (GA), (GA+C), (GA+C1+C2), etc.
13983 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
13984 Offset += GA->getOffset();
13986 } else if (Op.getOpcode() == ISD::ADD) {
13987 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13988 Offset += C->getZExtValue();
13989 Op = Op.getOperand(0);
13992 } else if (Op.getOpcode() == ISD::SUB) {
13993 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13994 Offset += -C->getZExtValue();
13995 Op = Op.getOperand(0);
14000 // Otherwise, this isn't something we can handle, reject it.
14004 const GlobalValue *GV = GA->getGlobal();
14005 // If we require an extra load to get this address, as in PIC mode, we
14006 // can't accept it.
14007 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
14008 getTargetMachine())))
14011 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
14012 GA->getValueType(0), Offset);
14017 if (Result.getNode()) {
14018 Ops.push_back(Result);
14021 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14024 std::pair<unsigned, const TargetRegisterClass*>
14025 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
14027 // First, see if this is a constraint that directly corresponds to an LLVM
14029 if (Constraint.size() == 1) {
14030 // GCC Constraint Letters
14031 switch (Constraint[0]) {
14033 // TODO: Slight differences here in allocation order and leaving
14034 // RIP in the class. Do they matter any more here than they do
14035 // in the normal allocation?
14036 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
14037 if (Subtarget->is64Bit()) {
14038 if (VT == MVT::i32 || VT == MVT::f32)
14039 return std::make_pair(0U, X86::GR32RegisterClass);
14040 else if (VT == MVT::i16)
14041 return std::make_pair(0U, X86::GR16RegisterClass);
14042 else if (VT == MVT::i8 || VT == MVT::i1)
14043 return std::make_pair(0U, X86::GR8RegisterClass);
14044 else if (VT == MVT::i64 || VT == MVT::f64)
14045 return std::make_pair(0U, X86::GR64RegisterClass);
14048 // 32-bit fallthrough
14049 case 'Q': // Q_REGS
14050 if (VT == MVT::i32 || VT == MVT::f32)
14051 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
14052 else if (VT == MVT::i16)
14053 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
14054 else if (VT == MVT::i8 || VT == MVT::i1)
14055 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
14056 else if (VT == MVT::i64)
14057 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
14059 case 'r': // GENERAL_REGS
14060 case 'l': // INDEX_REGS
14061 if (VT == MVT::i8 || VT == MVT::i1)
14062 return std::make_pair(0U, X86::GR8RegisterClass);
14063 if (VT == MVT::i16)
14064 return std::make_pair(0U, X86::GR16RegisterClass);
14065 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
14066 return std::make_pair(0U, X86::GR32RegisterClass);
14067 return std::make_pair(0U, X86::GR64RegisterClass);
14068 case 'R': // LEGACY_REGS
14069 if (VT == MVT::i8 || VT == MVT::i1)
14070 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
14071 if (VT == MVT::i16)
14072 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
14073 if (VT == MVT::i32 || !Subtarget->is64Bit())
14074 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
14075 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
14076 case 'f': // FP Stack registers.
14077 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
14078 // value to the correct fpstack register class.
14079 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
14080 return std::make_pair(0U, X86::RFP32RegisterClass);
14081 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
14082 return std::make_pair(0U, X86::RFP64RegisterClass);
14083 return std::make_pair(0U, X86::RFP80RegisterClass);
14084 case 'y': // MMX_REGS if MMX allowed.
14085 if (!Subtarget->hasMMX()) break;
14086 return std::make_pair(0U, X86::VR64RegisterClass);
14087 case 'Y': // SSE_REGS if SSE2 allowed
14088 if (!Subtarget->hasXMMInt()) break;
14090 case 'x': // SSE_REGS if SSE1 allowed
14091 if (!Subtarget->hasXMM()) break;
14093 switch (VT.getSimpleVT().SimpleTy) {
14095 // Scalar SSE types.
14098 return std::make_pair(0U, X86::FR32RegisterClass);
14101 return std::make_pair(0U, X86::FR64RegisterClass);
14109 return std::make_pair(0U, X86::VR128RegisterClass);
14115 // Use the default implementation in TargetLowering to convert the register
14116 // constraint into a member of a register class.
14117 std::pair<unsigned, const TargetRegisterClass*> Res;
14118 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
14120 // Not found as a standard register?
14121 if (Res.second == 0) {
14122 // Map st(0) -> st(7) -> ST0
14123 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14124 tolower(Constraint[1]) == 's' &&
14125 tolower(Constraint[2]) == 't' &&
14126 Constraint[3] == '(' &&
14127 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14128 Constraint[5] == ')' &&
14129 Constraint[6] == '}') {
14131 Res.first = X86::ST0+Constraint[4]-'0';
14132 Res.second = X86::RFP80RegisterClass;
14136 // GCC allows "st(0)" to be called just plain "st".
14137 if (StringRef("{st}").equals_lower(Constraint)) {
14138 Res.first = X86::ST0;
14139 Res.second = X86::RFP80RegisterClass;
14144 if (StringRef("{flags}").equals_lower(Constraint)) {
14145 Res.first = X86::EFLAGS;
14146 Res.second = X86::CCRRegisterClass;
14150 // 'A' means EAX + EDX.
14151 if (Constraint == "A") {
14152 Res.first = X86::EAX;
14153 Res.second = X86::GR32_ADRegisterClass;
14159 // Otherwise, check to see if this is a register class of the wrong value
14160 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14161 // turn into {ax},{dx}.
14162 if (Res.second->hasType(VT))
14163 return Res; // Correct type already, nothing to do.
14165 // All of the single-register GCC register classes map their values onto
14166 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14167 // really want an 8-bit or 32-bit register, map to the appropriate register
14168 // class and return the appropriate register.
14169 if (Res.second == X86::GR16RegisterClass) {
14170 if (VT == MVT::i8) {
14171 unsigned DestReg = 0;
14172 switch (Res.first) {
14174 case X86::AX: DestReg = X86::AL; break;
14175 case X86::DX: DestReg = X86::DL; break;
14176 case X86::CX: DestReg = X86::CL; break;
14177 case X86::BX: DestReg = X86::BL; break;
14180 Res.first = DestReg;
14181 Res.second = X86::GR8RegisterClass;
14183 } else if (VT == MVT::i32) {
14184 unsigned DestReg = 0;
14185 switch (Res.first) {
14187 case X86::AX: DestReg = X86::EAX; break;
14188 case X86::DX: DestReg = X86::EDX; break;
14189 case X86::CX: DestReg = X86::ECX; break;
14190 case X86::BX: DestReg = X86::EBX; break;
14191 case X86::SI: DestReg = X86::ESI; break;
14192 case X86::DI: DestReg = X86::EDI; break;
14193 case X86::BP: DestReg = X86::EBP; break;
14194 case X86::SP: DestReg = X86::ESP; break;
14197 Res.first = DestReg;
14198 Res.second = X86::GR32RegisterClass;
14200 } else if (VT == MVT::i64) {
14201 unsigned DestReg = 0;
14202 switch (Res.first) {
14204 case X86::AX: DestReg = X86::RAX; break;
14205 case X86::DX: DestReg = X86::RDX; break;
14206 case X86::CX: DestReg = X86::RCX; break;
14207 case X86::BX: DestReg = X86::RBX; break;
14208 case X86::SI: DestReg = X86::RSI; break;
14209 case X86::DI: DestReg = X86::RDI; break;
14210 case X86::BP: DestReg = X86::RBP; break;
14211 case X86::SP: DestReg = X86::RSP; break;
14214 Res.first = DestReg;
14215 Res.second = X86::GR64RegisterClass;
14218 } else if (Res.second == X86::FR32RegisterClass ||
14219 Res.second == X86::FR64RegisterClass ||
14220 Res.second == X86::VR128RegisterClass) {
14221 // Handle references to XMM physical registers that got mapped into the
14222 // wrong class. This can happen with constraints like {xmm0} where the
14223 // target independent register mapper will just pick the first match it can
14224 // find, ignoring the required type.
14225 if (VT == MVT::f32)
14226 Res.second = X86::FR32RegisterClass;
14227 else if (VT == MVT::f64)
14228 Res.second = X86::FR64RegisterClass;
14229 else if (X86::VR128RegisterClass->hasType(VT))
14230 Res.second = X86::VR128RegisterClass;