1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/LLVMContext.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCExpr.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/Dwarf.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
53 using namespace dwarf;
55 STATISTIC(NumTailCalls, "Number of tail calls");
58 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
66 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
68 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
69 if (is64Bit) return new X8664_MachoTargetObjectFile();
70 return new TargetLoweringObjectFileMachO();
71 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
72 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
73 return new X8632_ELFTargetObjectFile(TM);
74 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
75 return new TargetLoweringObjectFileCOFF();
77 llvm_unreachable("unknown subtarget type");
80 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
81 : TargetLowering(TM, createTLOF(TM)) {
82 Subtarget = &TM.getSubtarget<X86Subtarget>();
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
85 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
87 RegInfo = TM.getRegisterInfo();
90 // Set up the TargetLowering object.
92 // X86 is weird, it always uses i8 for shift amounts and setcc results.
93 setShiftAmountType(MVT::i8);
94 setBooleanContents(ZeroOrOneBooleanContent);
95 setSchedulingPreference(Sched::RegPressure);
96 setStackPointerRegisterToSaveRestore(X86StackPtr);
98 if (Subtarget->isTargetDarwin()) {
99 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
100 setUseUnderscoreSetJmp(false);
101 setUseUnderscoreLongJmp(false);
102 } else if (Subtarget->isTargetMingw()) {
103 // MS runtime is weird: it exports _setjmp, but longjmp!
104 setUseUnderscoreSetJmp(true);
105 setUseUnderscoreLongJmp(false);
107 setUseUnderscoreSetJmp(true);
108 setUseUnderscoreLongJmp(true);
111 // Set up the register classes.
112 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
122 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
124 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
125 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
128 // SETOEQ and SETUNE require checking two conditions.
129 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
130 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
131 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
132 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
133 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
136 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
138 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
139 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
140 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
142 if (Subtarget->is64Bit()) {
143 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
144 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
145 } else if (!UseSoftFloat) {
146 // We have an algorithm for SSE2->double, and we turn this into a
147 // 64-bit FILD followed by conditional FADD for other targets.
148 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
149 // We have an algorithm for SSE2, and we turn this into a 64-bit
150 // FILD for other targets.
151 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
154 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
156 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
157 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
160 // SSE has no i16 to fp conversion, only i32
161 if (X86ScalarSSEf32) {
162 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
163 // f32 and f64 cases are Legal, f80 case is not
164 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
166 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
174 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
175 // are Legal, f80 is custom lowered.
176 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
177 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
179 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
181 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
182 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
184 if (X86ScalarSSEf32) {
185 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
186 // f32 and f64 cases are Legal, f80 case is not
187 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
189 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
193 // Handle FP_TO_UINT by promoting the destination to a larger signed
195 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
196 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
197 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
199 if (Subtarget->is64Bit()) {
200 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
202 } else if (!UseSoftFloat) {
203 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
204 // Expand FP_TO_UINT into a select.
205 // FIXME: We would like to use a Custom expander here eventually to do
206 // the optimal thing for SSE vs. the default expansion in the legalizer.
207 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
209 // With SSE3 we can use fisttpll to convert to a signed i64; without
210 // SSE, we're stuck with a fistpll.
211 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
214 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
215 if (!X86ScalarSSEf64) {
216 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
217 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
218 if (Subtarget->is64Bit()) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
220 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
221 if (Subtarget->hasMMX() && !DisableMMX)
222 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
228 // Scalar integer divide and remainder are lowered to use operations that
229 // produce two results, to match the available instructions. This exposes
230 // the two-result form to trivial CSE, which is able to combine x/y and x%y
231 // into a single instruction.
233 // Scalar integer multiply-high is also lowered to use two-result
234 // operations, to match the available instructions. However, plain multiply
235 // (low) operations are left as Legal, as there are single-result
236 // instructions for this in x86. Using the two-result multiply instructions
237 // when both high and low results are needed must be arranged by dagcombine.
238 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
240 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
241 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
242 setOperationAction(ISD::SREM , MVT::i8 , Expand);
243 setOperationAction(ISD::UREM , MVT::i8 , Expand);
244 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
246 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
247 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
248 setOperationAction(ISD::SREM , MVT::i16 , Expand);
249 setOperationAction(ISD::UREM , MVT::i16 , Expand);
250 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
252 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
253 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
254 setOperationAction(ISD::SREM , MVT::i32 , Expand);
255 setOperationAction(ISD::UREM , MVT::i32 , Expand);
256 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
257 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
258 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
259 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
260 setOperationAction(ISD::SREM , MVT::i64 , Expand);
261 setOperationAction(ISD::UREM , MVT::i64 , Expand);
263 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
264 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
265 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
266 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
267 if (Subtarget->is64Bit())
268 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
272 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
273 setOperationAction(ISD::FREM , MVT::f32 , Expand);
274 setOperationAction(ISD::FREM , MVT::f64 , Expand);
275 setOperationAction(ISD::FREM , MVT::f80 , Expand);
276 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
278 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
279 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
280 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
281 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
282 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
283 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
300 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
302 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
303 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
305 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
306 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
308 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
309 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
315 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
318 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
319 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
320 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
321 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
322 if (Subtarget->is64Bit())
323 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
324 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
325 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
328 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
329 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
330 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
333 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
334 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
335 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
336 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
339 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
340 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
343 if (Subtarget->hasSSE1())
344 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
346 // We may not have a libcall for MEMBARRIER so we should lower this.
347 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
349 // On X86 and X86-64, atomic operations are lowered to locked instructions.
350 // Locked instructions, in turn, have implicit fence semantics (all memory
351 // operations are flushed before issuing the locked instruction, and they
352 // are not buffered), so we can fold away the common pattern of
353 // fence-atomic-fence.
354 setShouldFoldAtomicFences(true);
356 // Expand certain atomics
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
367 if (!Subtarget->is64Bit()) {
368 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
374 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
377 // FIXME - use subtarget debug flags
378 if (!Subtarget->isTargetDarwin() &&
379 !Subtarget->isTargetELF() &&
380 !Subtarget->isTargetCygMing()) {
381 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
384 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
385 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
387 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
388 if (Subtarget->is64Bit()) {
389 setExceptionPointerRegister(X86::RAX);
390 setExceptionSelectorRegister(X86::RDX);
392 setExceptionPointerRegister(X86::EAX);
393 setExceptionSelectorRegister(X86::EDX);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
398 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
400 setOperationAction(ISD::TRAP, MVT::Other, Legal);
402 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
403 setOperationAction(ISD::VASTART , MVT::Other, Custom);
404 setOperationAction(ISD::VAEND , MVT::Other, Expand);
405 if (Subtarget->is64Bit()) {
406 setOperationAction(ISD::VAARG , MVT::Other, Custom);
407 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
409 setOperationAction(ISD::VAARG , MVT::Other, Expand);
410 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
413 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
414 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
415 if (Subtarget->is64Bit())
416 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
417 if (Subtarget->isTargetCygMing())
418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
422 if (!UseSoftFloat && X86ScalarSSEf64) {
423 // f32 and f64 use SSE.
424 // Set up the FP register classes.
425 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
426 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
428 // Use ANDPD to simulate FABS.
429 setOperationAction(ISD::FABS , MVT::f64, Custom);
430 setOperationAction(ISD::FABS , MVT::f32, Custom);
432 // Use XORP to simulate FNEG.
433 setOperationAction(ISD::FNEG , MVT::f64, Custom);
434 setOperationAction(ISD::FNEG , MVT::f32, Custom);
436 // Use ANDPD and ORPD to simulate FCOPYSIGN.
437 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
438 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
440 // We don't support sin/cos/fmod
441 setOperationAction(ISD::FSIN , MVT::f64, Expand);
442 setOperationAction(ISD::FCOS , MVT::f64, Expand);
443 setOperationAction(ISD::FSIN , MVT::f32, Expand);
444 setOperationAction(ISD::FCOS , MVT::f32, Expand);
446 // Expand FP immediates into loads from the stack, except for the special
448 addLegalFPImmediate(APFloat(+0.0)); // xorpd
449 addLegalFPImmediate(APFloat(+0.0f)); // xorps
450 } else if (!UseSoftFloat && X86ScalarSSEf32) {
451 // Use SSE for f32, x87 for f64.
452 // Set up the FP register classes.
453 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
454 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
456 // Use ANDPS to simulate FABS.
457 setOperationAction(ISD::FABS , MVT::f32, Custom);
459 // Use XORP to simulate FNEG.
460 setOperationAction(ISD::FNEG , MVT::f32, Custom);
462 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
464 // Use ANDPS and ORPS to simulate FCOPYSIGN.
465 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
466 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
468 // We don't support sin/cos/fmod
469 setOperationAction(ISD::FSIN , MVT::f32, Expand);
470 setOperationAction(ISD::FCOS , MVT::f32, Expand);
472 // Special cases we handle for FP constants.
473 addLegalFPImmediate(APFloat(+0.0f)); // xorps
474 addLegalFPImmediate(APFloat(+0.0)); // FLD0
475 addLegalFPImmediate(APFloat(+1.0)); // FLD1
476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
480 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
481 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
483 } else if (!UseSoftFloat) {
484 // f32 and f64 in x87.
485 // Set up the FP register classes.
486 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
487 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
489 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
490 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
492 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
495 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
496 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
498 addLegalFPImmediate(APFloat(+0.0)); // FLD0
499 addLegalFPImmediate(APFloat(+1.0)); // FLD1
500 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
501 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
502 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
503 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
504 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
505 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
508 // Long double always uses X87.
510 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
511 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
512 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
515 APFloat TmpFlt(+0.0);
516 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
518 addLegalFPImmediate(TmpFlt); // FLD0
520 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
521 APFloat TmpFlt2(+1.0);
522 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
524 addLegalFPImmediate(TmpFlt2); // FLD1
525 TmpFlt2.changeSign();
526 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
530 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
531 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
535 // Always use a library call for pow.
536 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
538 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
540 setOperationAction(ISD::FLOG, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
542 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP, MVT::f80, Expand);
544 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
546 // First set operation action for all vector types to either promote
547 // (for widening) or expand (for scalarization). Then we will selectively
548 // turn on ones that can be effectively codegen'd.
549 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
550 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
551 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
567 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
600 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
604 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
605 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
606 setTruncStoreAction((MVT::SimpleValueType)VT,
607 (MVT::SimpleValueType)InnerVT, Expand);
608 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
609 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
610 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
613 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
614 // with -msoft-float, disable use of MMX as well.
615 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
616 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
617 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
618 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
620 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
622 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
623 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
624 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
625 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
627 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
628 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
629 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
630 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
632 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
633 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
635 setOperationAction(ISD::AND, MVT::v8i8, Promote);
636 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
637 setOperationAction(ISD::AND, MVT::v4i16, Promote);
638 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
639 setOperationAction(ISD::AND, MVT::v2i32, Promote);
640 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
641 setOperationAction(ISD::AND, MVT::v1i64, Legal);
643 setOperationAction(ISD::OR, MVT::v8i8, Promote);
644 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
645 setOperationAction(ISD::OR, MVT::v4i16, Promote);
646 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
647 setOperationAction(ISD::OR, MVT::v2i32, Promote);
648 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
649 setOperationAction(ISD::OR, MVT::v1i64, Legal);
651 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
652 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
653 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
654 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
655 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
656 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
657 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
659 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
660 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
661 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
662 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
663 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
664 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
665 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
667 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
672 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
681 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
683 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
684 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
685 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
686 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
687 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
688 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
689 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
691 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
692 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
693 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
694 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
695 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
699 if (!UseSoftFloat && Subtarget->hasSSE1()) {
700 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
702 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
703 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
704 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
705 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
706 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
707 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
708 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
709 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
712 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
713 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
716 if (!UseSoftFloat && Subtarget->hasSSE2()) {
717 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
719 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
720 // registers cannot be used even for integer operations.
721 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
722 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
723 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
724 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
726 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
727 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
728 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
729 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
730 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
731 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
732 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
733 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
734 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
735 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
736 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
737 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
738 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
739 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
740 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
741 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
743 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
744 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
745 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
746 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
750 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
752 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
754 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
760 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
761 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
762 EVT VT = (MVT::SimpleValueType)i;
763 // Do not attempt to custom lower non-power-of-2 vectors
764 if (!isPowerOf2_32(VT.getVectorNumElements()))
766 // Do not attempt to custom lower non-128-bit vectors
767 if (!VT.is128BitVector())
769 setOperationAction(ISD::BUILD_VECTOR,
770 VT.getSimpleVT().SimpleTy, Custom);
771 setOperationAction(ISD::VECTOR_SHUFFLE,
772 VT.getSimpleVT().SimpleTy, Custom);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
774 VT.getSimpleVT().SimpleTy, Custom);
777 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
778 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
781 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
782 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
784 if (Subtarget->is64Bit()) {
785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
789 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
790 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
791 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
794 // Do not attempt to promote non-128-bit vectors
795 if (!VT.is128BitVector())
798 setOperationAction(ISD::AND, SVT, Promote);
799 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
800 setOperationAction(ISD::OR, SVT, Promote);
801 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
802 setOperationAction(ISD::XOR, SVT, Promote);
803 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
804 setOperationAction(ISD::LOAD, SVT, Promote);
805 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
806 setOperationAction(ISD::SELECT, SVT, Promote);
807 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
810 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
812 // Custom lower v2i64 and v2f64 selects.
813 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
814 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
815 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
816 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
818 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
819 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
820 if (!DisableMMX && Subtarget->hasMMX()) {
821 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
822 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
826 if (Subtarget->hasSSE41()) {
827 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
828 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
829 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
830 setOperationAction(ISD::FRINT, MVT::f32, Legal);
831 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
832 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
833 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
834 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
835 setOperationAction(ISD::FRINT, MVT::f64, Legal);
836 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
838 // FIXME: Do we need to handle scalar-to-vector here?
839 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
841 // i8 and i16 vectors are custom , because the source register and source
842 // source memory operand types are not the same width. f32 vectors are
843 // custom since the immediate controlling the insert encodes additional
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
853 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
855 if (Subtarget->is64Bit()) {
856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
861 if (Subtarget->hasSSE42()) {
862 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
865 if (!UseSoftFloat && Subtarget->hasAVX()) {
866 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
867 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
868 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
869 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
871 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
872 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
873 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
874 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
875 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
876 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
877 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
878 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
879 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
880 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
881 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
882 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
883 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
884 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
885 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
887 // Operations to consider commented out -v16i16 v32i8
888 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
889 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
890 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
891 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
892 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
893 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
894 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
895 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
896 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
897 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
898 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
899 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
900 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
901 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
903 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
904 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
905 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
906 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
908 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
909 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
910 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
914 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
915 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
917 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
922 // Not sure we want to do this since there are no 256-bit integer
925 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
926 // This includes 256-bit vectors
927 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
928 EVT VT = (MVT::SimpleValueType)i;
930 // Do not attempt to custom lower non-power-of-2 vectors
931 if (!isPowerOf2_32(VT.getVectorNumElements()))
934 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
935 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
939 if (Subtarget->is64Bit()) {
940 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
946 // Not sure we want to do this since there are no 256-bit integer
949 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
950 // Including 256-bit vectors
951 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
952 EVT VT = (MVT::SimpleValueType)i;
954 if (!VT.is256BitVector()) {
957 setOperationAction(ISD::AND, VT, Promote);
958 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
959 setOperationAction(ISD::OR, VT, Promote);
960 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
961 setOperationAction(ISD::XOR, VT, Promote);
962 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
963 setOperationAction(ISD::LOAD, VT, Promote);
964 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
965 setOperationAction(ISD::SELECT, VT, Promote);
966 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
969 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
973 // We want to custom lower some of our intrinsics.
974 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
976 // Add/Sub/Mul with overflow operations are custom lowered.
977 setOperationAction(ISD::SADDO, MVT::i32, Custom);
978 setOperationAction(ISD::UADDO, MVT::i32, Custom);
979 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
980 setOperationAction(ISD::USUBO, MVT::i32, Custom);
981 setOperationAction(ISD::SMULO, MVT::i32, Custom);
983 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
984 // handle type legalization for these operations here.
986 // FIXME: We really should do custom legalization for addition and
987 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
988 // than generic legalization for 64-bit multiplication-with-overflow, though.
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::SADDO, MVT::i64, Custom);
991 setOperationAction(ISD::UADDO, MVT::i64, Custom);
992 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
993 setOperationAction(ISD::USUBO, MVT::i64, Custom);
994 setOperationAction(ISD::SMULO, MVT::i64, Custom);
997 if (!Subtarget->is64Bit()) {
998 // These libcalls are not available in 32-bit.
999 setLibcallName(RTLIB::SHL_I128, 0);
1000 setLibcallName(RTLIB::SRL_I128, 0);
1001 setLibcallName(RTLIB::SRA_I128, 0);
1004 // We have target-specific dag combine patterns for the following nodes:
1005 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1006 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1007 setTargetDAGCombine(ISD::BUILD_VECTOR);
1008 setTargetDAGCombine(ISD::SELECT);
1009 setTargetDAGCombine(ISD::SHL);
1010 setTargetDAGCombine(ISD::SRA);
1011 setTargetDAGCombine(ISD::SRL);
1012 setTargetDAGCombine(ISD::OR);
1013 setTargetDAGCombine(ISD::STORE);
1014 setTargetDAGCombine(ISD::ZERO_EXTEND);
1015 if (Subtarget->is64Bit())
1016 setTargetDAGCombine(ISD::MUL);
1018 computeRegisterProperties();
1020 // FIXME: These should be based on subtarget info. Plus, the values should
1021 // be smaller when we are in optimizing for size mode.
1022 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1023 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1024 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1025 setPrefLoopAlignment(16);
1026 benefitFromCodePlacementOpt = true;
1030 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1035 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1036 /// the desired ByVal argument alignment.
1037 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1040 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1041 if (VTy->getBitWidth() == 128)
1043 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1044 unsigned EltAlign = 0;
1045 getMaxByValAlign(ATy->getElementType(), EltAlign);
1046 if (EltAlign > MaxAlign)
1047 MaxAlign = EltAlign;
1048 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1049 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1050 unsigned EltAlign = 0;
1051 getMaxByValAlign(STy->getElementType(i), EltAlign);
1052 if (EltAlign > MaxAlign)
1053 MaxAlign = EltAlign;
1061 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1062 /// function arguments in the caller parameter area. For X86, aggregates
1063 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1064 /// are at 4-byte boundaries.
1065 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1066 if (Subtarget->is64Bit()) {
1067 // Max of 8 and alignment of type.
1068 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1075 if (Subtarget->hasSSE1())
1076 getMaxByValAlign(Ty, Align);
1080 /// getOptimalMemOpType - Returns the target specific optimal type for load
1081 /// and store operations as a result of memset, memcpy, and memmove
1082 /// lowering. If DstAlign is zero that means it's safe to destination
1083 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1084 /// means there isn't a need to check it against alignment requirement,
1085 /// probably because the source does not need to be loaded. If
1086 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1087 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1088 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1089 /// constant so it does not need to be loaded.
1090 /// It returns EVT::Other if the type should be determined using generic
1091 /// target-independent logic.
1093 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1094 unsigned DstAlign, unsigned SrcAlign,
1095 bool NonScalarIntSafe,
1097 MachineFunction &MF) const {
1098 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1099 // linux. This is because the stack realignment code can't handle certain
1100 // cases like PR2962. This should be removed when PR2962 is fixed.
1101 const Function *F = MF.getFunction();
1102 if (NonScalarIntSafe &&
1103 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1105 (Subtarget->isUnalignedMemAccessFast() ||
1106 ((DstAlign == 0 || DstAlign >= 16) &&
1107 (SrcAlign == 0 || SrcAlign >= 16))) &&
1108 Subtarget->getStackAlignment() >= 16) {
1109 if (Subtarget->hasSSE2())
1111 if (Subtarget->hasSSE1())
1113 } else if (!MemcpyStrSrc && Size >= 8 &&
1114 !Subtarget->is64Bit() &&
1115 Subtarget->getStackAlignment() >= 8 &&
1116 Subtarget->hasSSE2()) {
1117 // Do not use f64 to lower memcpy if source is string constant. It's
1118 // better to use i32 to avoid the loads.
1122 if (Subtarget->is64Bit() && Size >= 8)
1127 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1128 /// current function. The returned value is a member of the
1129 /// MachineJumpTableInfo::JTEntryKind enum.
1130 unsigned X86TargetLowering::getJumpTableEncoding() const {
1131 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1133 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1134 Subtarget->isPICStyleGOT())
1135 return MachineJumpTableInfo::EK_Custom32;
1137 // Otherwise, use the normal jump table encoding heuristics.
1138 return TargetLowering::getJumpTableEncoding();
1141 /// getPICBaseSymbol - Return the X86-32 PIC base.
1143 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1144 MCContext &Ctx) const {
1145 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1146 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1147 Twine(MF->getFunctionNumber())+"$pb");
1152 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1153 const MachineBasicBlock *MBB,
1154 unsigned uid,MCContext &Ctx) const{
1155 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1156 Subtarget->isPICStyleGOT());
1157 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1159 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1160 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1163 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1165 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1166 SelectionDAG &DAG) const {
1167 if (!Subtarget->is64Bit())
1168 // This doesn't have DebugLoc associated with it, but is not really the
1169 // same as a Register.
1170 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1174 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1175 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1177 const MCExpr *X86TargetLowering::
1178 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1179 MCContext &Ctx) const {
1180 // X86-64 uses RIP relative addressing based on the jump table label.
1181 if (Subtarget->isPICStyleRIPRel())
1182 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1184 // Otherwise, the reference is relative to the PIC base.
1185 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1188 /// getFunctionAlignment - Return the Log2 alignment of this function.
1189 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1190 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1194 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1195 MachineFunction &MF) const {
1196 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
1197 switch (RC->getID()) {
1200 case X86::GR32RegClassID:
1202 case X86::GR64RegClassID:
1204 case X86::VR128RegClassID:
1205 return Subtarget->is64Bit() ? 10 : 4;
1206 case X86::VR64RegClassID:
1211 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1212 unsigned &Offset) const {
1213 if (!Subtarget->isTargetLinux())
1216 if (Subtarget->is64Bit()) {
1217 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1219 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1232 //===----------------------------------------------------------------------===//
1233 // Return Value Calling Convention Implementation
1234 //===----------------------------------------------------------------------===//
1236 #include "X86GenCallingConv.inc"
1239 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1240 const SmallVectorImpl<ISD::OutputArg> &Outs,
1241 LLVMContext &Context) const {
1242 SmallVector<CCValAssign, 16> RVLocs;
1243 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1245 return CCInfo.CheckReturn(Outs, RetCC_X86);
1249 X86TargetLowering::LowerReturn(SDValue Chain,
1250 CallingConv::ID CallConv, bool isVarArg,
1251 const SmallVectorImpl<ISD::OutputArg> &Outs,
1252 const SmallVectorImpl<SDValue> &OutVals,
1253 DebugLoc dl, SelectionDAG &DAG) const {
1254 MachineFunction &MF = DAG.getMachineFunction();
1255 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1257 SmallVector<CCValAssign, 16> RVLocs;
1258 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1259 RVLocs, *DAG.getContext());
1260 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1262 // Add the regs to the liveout set for the function.
1263 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1264 for (unsigned i = 0; i != RVLocs.size(); ++i)
1265 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1266 MRI.addLiveOut(RVLocs[i].getLocReg());
1270 SmallVector<SDValue, 6> RetOps;
1271 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1272 // Operand #1 = Bytes To Pop
1273 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1276 // Copy the result values into the output registers.
1277 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1278 CCValAssign &VA = RVLocs[i];
1279 assert(VA.isRegLoc() && "Can only return in registers!");
1280 SDValue ValToCopy = OutVals[i];
1281 EVT ValVT = ValToCopy.getValueType();
1283 // If this is x86-64, and we disabled SSE, we can't return FP values
1284 if ((ValVT == MVT::f32 || ValVT == MVT::f64) &&
1285 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1286 report_fatal_error("SSE register return with SSE disabled");
1288 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1289 // llvm-gcc has never done it right and no one has noticed, so this
1290 // should be OK for now.
1291 if (ValVT == MVT::f64 &&
1292 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) {
1293 report_fatal_error("SSE2 register return with SSE2 disabled");
1296 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1297 // the RET instruction and handled by the FP Stackifier.
1298 if (VA.getLocReg() == X86::ST0 ||
1299 VA.getLocReg() == X86::ST1) {
1300 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1301 // change the value to the FP stack register class.
1302 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1303 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1304 RetOps.push_back(ValToCopy);
1305 // Don't emit a copytoreg.
1309 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1310 // which is returned in RAX / RDX.
1311 if (Subtarget->is64Bit()) {
1312 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1313 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1314 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1315 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1320 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1321 Flag = Chain.getValue(1);
1324 // The x86-64 ABI for returning structs by value requires that we copy
1325 // the sret argument into %rax for the return. We saved the argument into
1326 // a virtual register in the entry block, so now we copy the value out
1328 if (Subtarget->is64Bit() &&
1329 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1330 MachineFunction &MF = DAG.getMachineFunction();
1331 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1332 unsigned Reg = FuncInfo->getSRetReturnReg();
1334 "SRetReturnReg should have been set in LowerFormalArguments().");
1335 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1337 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1338 Flag = Chain.getValue(1);
1340 // RAX now acts like a return value.
1341 MRI.addLiveOut(X86::RAX);
1344 RetOps[0] = Chain; // Update chain.
1346 // Add the flag if we have it.
1348 RetOps.push_back(Flag);
1350 return DAG.getNode(X86ISD::RET_FLAG, dl,
1351 MVT::Other, &RetOps[0], RetOps.size());
1354 /// LowerCallResult - Lower the result values of a call into the
1355 /// appropriate copies out of appropriate physical registers.
1358 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1359 CallingConv::ID CallConv, bool isVarArg,
1360 const SmallVectorImpl<ISD::InputArg> &Ins,
1361 DebugLoc dl, SelectionDAG &DAG,
1362 SmallVectorImpl<SDValue> &InVals) const {
1364 // Assign locations to each value returned by this call.
1365 SmallVector<CCValAssign, 16> RVLocs;
1366 bool Is64Bit = Subtarget->is64Bit();
1367 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1368 RVLocs, *DAG.getContext());
1369 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1371 // Copy all of the result registers out of their specified physreg.
1372 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1373 CCValAssign &VA = RVLocs[i];
1374 EVT CopyVT = VA.getValVT();
1376 // If this is x86-64, and we disabled SSE, we can't return FP values
1377 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1378 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1379 report_fatal_error("SSE register return with SSE disabled");
1384 // If this is a call to a function that returns an fp value on the floating
1385 // point stack, we must guarantee the the value is popped from the stack, so
1386 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1387 // if the return value is not used. We use the FpGET_ST0 instructions
1389 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1390 // If we prefer to use the value in xmm registers, copy it out as f80 and
1391 // use a truncate to move it from fp stack reg to xmm reg.
1392 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1393 bool isST0 = VA.getLocReg() == X86::ST0;
1395 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1396 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1397 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1398 SDValue Ops[] = { Chain, InFlag };
1399 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1401 Val = Chain.getValue(0);
1403 // Round the f80 to the right size, which also moves it to the appropriate
1405 if (CopyVT != VA.getValVT())
1406 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1407 // This truncation won't change the value.
1408 DAG.getIntPtrConstant(1));
1409 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1410 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1411 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1412 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1413 MVT::v2i64, InFlag).getValue(1);
1414 Val = Chain.getValue(0);
1415 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1416 Val, DAG.getConstant(0, MVT::i64));
1418 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1419 MVT::i64, InFlag).getValue(1);
1420 Val = Chain.getValue(0);
1422 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1424 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1425 CopyVT, InFlag).getValue(1);
1426 Val = Chain.getValue(0);
1428 InFlag = Chain.getValue(2);
1429 InVals.push_back(Val);
1436 //===----------------------------------------------------------------------===//
1437 // C & StdCall & Fast Calling Convention implementation
1438 //===----------------------------------------------------------------------===//
1439 // StdCall calling convention seems to be standard for many Windows' API
1440 // routines and around. It differs from C calling convention just a little:
1441 // callee should clean up the stack, not caller. Symbols should be also
1442 // decorated in some fancy way :) It doesn't support any vector arguments.
1443 // For info on fast calling convention see Fast Calling Convention (tail call)
1444 // implementation LowerX86_32FastCCCallTo.
1446 /// CallIsStructReturn - Determines whether a call uses struct return
1448 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1452 return Outs[0].Flags.isSRet();
1455 /// ArgsAreStructReturn - Determines whether a function uses struct
1456 /// return semantics.
1458 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1462 return Ins[0].Flags.isSRet();
1465 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1466 /// given CallingConvention value.
1467 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1468 if (Subtarget->is64Bit()) {
1469 if (CC == CallingConv::GHC)
1470 return CC_X86_64_GHC;
1471 else if (Subtarget->isTargetWin64())
1472 return CC_X86_Win64_C;
1477 if (CC == CallingConv::X86_FastCall)
1478 return CC_X86_32_FastCall;
1479 else if (CC == CallingConv::X86_ThisCall)
1480 return CC_X86_32_ThisCall;
1481 else if (CC == CallingConv::Fast)
1482 return CC_X86_32_FastCC;
1483 else if (CC == CallingConv::GHC)
1484 return CC_X86_32_GHC;
1489 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1490 /// by "Src" to address "Dst" with size and alignment information specified by
1491 /// the specific parameter attribute. The copy will be passed as a byval
1492 /// function parameter.
1494 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1495 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1497 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1498 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1499 /*isVolatile*/false, /*AlwaysInline=*/true,
1503 /// IsTailCallConvention - Return true if the calling convention is one that
1504 /// supports tail call optimization.
1505 static bool IsTailCallConvention(CallingConv::ID CC) {
1506 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1509 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1510 /// a tailcall target by changing its ABI.
1511 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1512 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1516 X86TargetLowering::LowerMemArgument(SDValue Chain,
1517 CallingConv::ID CallConv,
1518 const SmallVectorImpl<ISD::InputArg> &Ins,
1519 DebugLoc dl, SelectionDAG &DAG,
1520 const CCValAssign &VA,
1521 MachineFrameInfo *MFI,
1523 // Create the nodes corresponding to a load from this parameter slot.
1524 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1525 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1526 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1529 // If value is passed by pointer we have address passed instead of the value
1531 if (VA.getLocInfo() == CCValAssign::Indirect)
1532 ValVT = VA.getLocVT();
1534 ValVT = VA.getValVT();
1536 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1537 // changed with more analysis.
1538 // In case of tail call optimization mark all arguments mutable. Since they
1539 // could be overwritten by lowering of arguments in case of a tail call.
1540 if (Flags.isByVal()) {
1541 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1542 VA.getLocMemOffset(), isImmutable);
1543 return DAG.getFrameIndex(FI, getPointerTy());
1545 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1546 VA.getLocMemOffset(), isImmutable);
1547 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1548 return DAG.getLoad(ValVT, dl, Chain, FIN,
1549 PseudoSourceValue::getFixedStack(FI), 0,
1555 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1556 CallingConv::ID CallConv,
1558 const SmallVectorImpl<ISD::InputArg> &Ins,
1561 SmallVectorImpl<SDValue> &InVals)
1563 MachineFunction &MF = DAG.getMachineFunction();
1564 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1566 const Function* Fn = MF.getFunction();
1567 if (Fn->hasExternalLinkage() &&
1568 Subtarget->isTargetCygMing() &&
1569 Fn->getName() == "main")
1570 FuncInfo->setForceFramePointer(true);
1572 MachineFrameInfo *MFI = MF.getFrameInfo();
1573 bool Is64Bit = Subtarget->is64Bit();
1574 bool IsWin64 = Subtarget->isTargetWin64();
1576 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1577 "Var args not supported with calling convention fastcc or ghc");
1579 // Assign locations to all of the incoming arguments.
1580 SmallVector<CCValAssign, 16> ArgLocs;
1581 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1582 ArgLocs, *DAG.getContext());
1583 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1585 unsigned LastVal = ~0U;
1587 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1588 CCValAssign &VA = ArgLocs[i];
1589 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1591 assert(VA.getValNo() != LastVal &&
1592 "Don't support value assigned to multiple locs yet");
1593 LastVal = VA.getValNo();
1595 if (VA.isRegLoc()) {
1596 EVT RegVT = VA.getLocVT();
1597 TargetRegisterClass *RC = NULL;
1598 if (RegVT == MVT::i32)
1599 RC = X86::GR32RegisterClass;
1600 else if (Is64Bit && RegVT == MVT::i64)
1601 RC = X86::GR64RegisterClass;
1602 else if (RegVT == MVT::f32)
1603 RC = X86::FR32RegisterClass;
1604 else if (RegVT == MVT::f64)
1605 RC = X86::FR64RegisterClass;
1606 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1607 RC = X86::VR128RegisterClass;
1608 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1609 RC = X86::VR64RegisterClass;
1611 llvm_unreachable("Unknown argument type!");
1613 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1614 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1616 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1617 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1619 if (VA.getLocInfo() == CCValAssign::SExt)
1620 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1621 DAG.getValueType(VA.getValVT()));
1622 else if (VA.getLocInfo() == CCValAssign::ZExt)
1623 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1624 DAG.getValueType(VA.getValVT()));
1625 else if (VA.getLocInfo() == CCValAssign::BCvt)
1626 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1628 if (VA.isExtInLoc()) {
1629 // Handle MMX values passed in XMM regs.
1630 if (RegVT.isVector()) {
1631 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1632 ArgValue, DAG.getConstant(0, MVT::i64));
1633 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1635 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1638 assert(VA.isMemLoc());
1639 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1642 // If value is passed via pointer - do a load.
1643 if (VA.getLocInfo() == CCValAssign::Indirect)
1644 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1647 InVals.push_back(ArgValue);
1650 // The x86-64 ABI for returning structs by value requires that we copy
1651 // the sret argument into %rax for the return. Save the argument into
1652 // a virtual register so that we can access it from the return points.
1653 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1654 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1655 unsigned Reg = FuncInfo->getSRetReturnReg();
1657 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1658 FuncInfo->setSRetReturnReg(Reg);
1660 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1661 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1664 unsigned StackSize = CCInfo.getNextStackOffset();
1665 // Align stack specially for tail calls.
1666 if (FuncIsMadeTailCallSafe(CallConv))
1667 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1669 // If the function takes variable number of arguments, make a frame index for
1670 // the start of the first vararg value... for expansion of llvm.va_start.
1672 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1673 CallConv != CallingConv::X86_ThisCall)) {
1674 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1677 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1679 // FIXME: We should really autogenerate these arrays
1680 static const unsigned GPR64ArgRegsWin64[] = {
1681 X86::RCX, X86::RDX, X86::R8, X86::R9
1683 static const unsigned XMMArgRegsWin64[] = {
1684 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1686 static const unsigned GPR64ArgRegs64Bit[] = {
1687 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1689 static const unsigned XMMArgRegs64Bit[] = {
1690 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1691 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1693 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1696 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1697 GPR64ArgRegs = GPR64ArgRegsWin64;
1698 XMMArgRegs = XMMArgRegsWin64;
1700 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1701 GPR64ArgRegs = GPR64ArgRegs64Bit;
1702 XMMArgRegs = XMMArgRegs64Bit;
1704 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1706 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1709 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1710 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1711 "SSE register cannot be used when SSE is disabled!");
1712 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1713 "SSE register cannot be used when SSE is disabled!");
1714 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1715 // Kernel mode asks for SSE to be disabled, so don't push them
1717 TotalNumXMMRegs = 0;
1719 // For X86-64, if there are vararg parameters that are passed via
1720 // registers, then we must store them to their spots on the stack so they
1721 // may be loaded by deferencing the result of va_next.
1722 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1723 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1724 FuncInfo->setRegSaveFrameIndex(
1725 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1728 // Store the integer parameter registers.
1729 SmallVector<SDValue, 8> MemOps;
1730 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1732 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1733 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1734 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1735 DAG.getIntPtrConstant(Offset));
1736 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1737 X86::GR64RegisterClass);
1738 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1740 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1741 PseudoSourceValue::getFixedStack(
1742 FuncInfo->getRegSaveFrameIndex()),
1743 Offset, false, false, 0);
1744 MemOps.push_back(Store);
1748 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1749 // Now store the XMM (fp + vector) parameter registers.
1750 SmallVector<SDValue, 11> SaveXMMOps;
1751 SaveXMMOps.push_back(Chain);
1753 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1754 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1755 SaveXMMOps.push_back(ALVal);
1757 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1758 FuncInfo->getRegSaveFrameIndex()));
1759 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1760 FuncInfo->getVarArgsFPOffset()));
1762 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1763 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1764 X86::VR128RegisterClass);
1765 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1766 SaveXMMOps.push_back(Val);
1768 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1770 &SaveXMMOps[0], SaveXMMOps.size()));
1773 if (!MemOps.empty())
1774 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1775 &MemOps[0], MemOps.size());
1779 // Some CCs need callee pop.
1780 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1781 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1783 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1784 // If this is an sret function, the return should pop the hidden pointer.
1785 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1786 FuncInfo->setBytesToPopOnReturn(4);
1790 // RegSaveFrameIndex is X86-64 only.
1791 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1792 if (CallConv == CallingConv::X86_FastCall ||
1793 CallConv == CallingConv::X86_ThisCall)
1794 // fastcc functions can't have varargs.
1795 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1802 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1803 SDValue StackPtr, SDValue Arg,
1804 DebugLoc dl, SelectionDAG &DAG,
1805 const CCValAssign &VA,
1806 ISD::ArgFlagsTy Flags) const {
1807 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1808 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1809 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1810 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1811 if (Flags.isByVal()) {
1812 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1814 return DAG.getStore(Chain, dl, Arg, PtrOff,
1815 PseudoSourceValue::getStack(), LocMemOffset,
1819 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1820 /// optimization is performed and it is required.
1822 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1823 SDValue &OutRetAddr, SDValue Chain,
1824 bool IsTailCall, bool Is64Bit,
1825 int FPDiff, DebugLoc dl) const {
1826 // Adjust the Return address stack slot.
1827 EVT VT = getPointerTy();
1828 OutRetAddr = getReturnAddressFrameIndex(DAG);
1830 // Load the "old" Return address.
1831 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1832 return SDValue(OutRetAddr.getNode(), 1);
1835 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1836 /// optimization is performed and it is required (FPDiff!=0).
1838 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1839 SDValue Chain, SDValue RetAddrFrIdx,
1840 bool Is64Bit, int FPDiff, DebugLoc dl) {
1841 // Store the return address to the appropriate stack slot.
1842 if (!FPDiff) return Chain;
1843 // Calculate the new stack slot for the return address.
1844 int SlotSize = Is64Bit ? 8 : 4;
1845 int NewReturnAddrFI =
1846 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1847 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1848 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1849 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1850 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1856 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1857 CallingConv::ID CallConv, bool isVarArg,
1859 const SmallVectorImpl<ISD::OutputArg> &Outs,
1860 const SmallVectorImpl<SDValue> &OutVals,
1861 const SmallVectorImpl<ISD::InputArg> &Ins,
1862 DebugLoc dl, SelectionDAG &DAG,
1863 SmallVectorImpl<SDValue> &InVals) const {
1864 MachineFunction &MF = DAG.getMachineFunction();
1865 bool Is64Bit = Subtarget->is64Bit();
1866 bool IsStructRet = CallIsStructReturn(Outs);
1867 bool IsSibcall = false;
1870 // Check if it's really possible to do a tail call.
1871 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1872 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1873 Outs, OutVals, Ins, DAG);
1875 // Sibcalls are automatically detected tailcalls which do not require
1877 if (!GuaranteedTailCallOpt && isTailCall)
1884 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1885 "Var args not supported with calling convention fastcc or ghc");
1887 // Analyze operands of the call, assigning locations to each operand.
1888 SmallVector<CCValAssign, 16> ArgLocs;
1889 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1890 ArgLocs, *DAG.getContext());
1891 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1893 // Get a count of how many bytes are to be pushed on the stack.
1894 unsigned NumBytes = CCInfo.getNextStackOffset();
1896 // This is a sibcall. The memory operands are available in caller's
1897 // own caller's stack.
1899 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1900 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1903 if (isTailCall && !IsSibcall) {
1904 // Lower arguments at fp - stackoffset + fpdiff.
1905 unsigned NumBytesCallerPushed =
1906 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1907 FPDiff = NumBytesCallerPushed - NumBytes;
1909 // Set the delta of movement of the returnaddr stackslot.
1910 // But only set if delta is greater than previous delta.
1911 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1912 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1916 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1918 SDValue RetAddrFrIdx;
1919 // Load return adress for tail calls.
1920 if (isTailCall && FPDiff)
1921 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1922 Is64Bit, FPDiff, dl);
1924 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1925 SmallVector<SDValue, 8> MemOpChains;
1928 // Walk the register/memloc assignments, inserting copies/loads. In the case
1929 // of tail call optimization arguments are handle later.
1930 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1931 CCValAssign &VA = ArgLocs[i];
1932 EVT RegVT = VA.getLocVT();
1933 SDValue Arg = OutVals[i];
1934 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1935 bool isByVal = Flags.isByVal();
1937 // Promote the value if needed.
1938 switch (VA.getLocInfo()) {
1939 default: llvm_unreachable("Unknown loc info!");
1940 case CCValAssign::Full: break;
1941 case CCValAssign::SExt:
1942 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1944 case CCValAssign::ZExt:
1945 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1947 case CCValAssign::AExt:
1948 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1949 // Special case: passing MMX values in XMM registers.
1950 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1951 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1952 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1954 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1956 case CCValAssign::BCvt:
1957 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1959 case CCValAssign::Indirect: {
1960 // Store the argument.
1961 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1962 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1963 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1964 PseudoSourceValue::getFixedStack(FI), 0,
1971 if (VA.isRegLoc()) {
1972 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1973 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1974 assert(VA.isMemLoc());
1975 if (StackPtr.getNode() == 0)
1976 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1977 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1978 dl, DAG, VA, Flags));
1982 if (!MemOpChains.empty())
1983 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1984 &MemOpChains[0], MemOpChains.size());
1986 // Build a sequence of copy-to-reg nodes chained together with token chain
1987 // and flag operands which copy the outgoing args into registers.
1989 // Tail call byval lowering might overwrite argument registers so in case of
1990 // tail call optimization the copies to registers are lowered later.
1992 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1993 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1994 RegsToPass[i].second, InFlag);
1995 InFlag = Chain.getValue(1);
1998 if (Subtarget->isPICStyleGOT()) {
1999 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2002 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2003 DAG.getNode(X86ISD::GlobalBaseReg,
2004 DebugLoc(), getPointerTy()),
2006 InFlag = Chain.getValue(1);
2008 // If we are tail calling and generating PIC/GOT style code load the
2009 // address of the callee into ECX. The value in ecx is used as target of
2010 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2011 // for tail calls on PIC/GOT architectures. Normally we would just put the
2012 // address of GOT into ebx and then call target@PLT. But for tail calls
2013 // ebx would be restored (since ebx is callee saved) before jumping to the
2016 // Note: The actual moving to ECX is done further down.
2017 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2018 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2019 !G->getGlobal()->hasProtectedVisibility())
2020 Callee = LowerGlobalAddress(Callee, DAG);
2021 else if (isa<ExternalSymbolSDNode>(Callee))
2022 Callee = LowerExternalSymbol(Callee, DAG);
2026 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2027 // From AMD64 ABI document:
2028 // For calls that may call functions that use varargs or stdargs
2029 // (prototype-less calls or calls to functions containing ellipsis (...) in
2030 // the declaration) %al is used as hidden argument to specify the number
2031 // of SSE registers used. The contents of %al do not need to match exactly
2032 // the number of registers, but must be an ubound on the number of SSE
2033 // registers used and is in the range 0 - 8 inclusive.
2035 // Count the number of XMM registers allocated.
2036 static const unsigned XMMArgRegs[] = {
2037 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2038 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2040 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2041 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2042 && "SSE registers cannot be used when SSE is disabled");
2044 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2045 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2046 InFlag = Chain.getValue(1);
2050 // For tail calls lower the arguments to the 'real' stack slot.
2052 // Force all the incoming stack arguments to be loaded from the stack
2053 // before any new outgoing arguments are stored to the stack, because the
2054 // outgoing stack slots may alias the incoming argument stack slots, and
2055 // the alias isn't otherwise explicit. This is slightly more conservative
2056 // than necessary, because it means that each store effectively depends
2057 // on every argument instead of just those arguments it would clobber.
2058 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2060 SmallVector<SDValue, 8> MemOpChains2;
2063 // Do not flag preceeding copytoreg stuff together with the following stuff.
2065 if (GuaranteedTailCallOpt) {
2066 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2067 CCValAssign &VA = ArgLocs[i];
2070 assert(VA.isMemLoc());
2071 SDValue Arg = OutVals[i];
2072 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2073 // Create frame index.
2074 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2075 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2076 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2077 FIN = DAG.getFrameIndex(FI, getPointerTy());
2079 if (Flags.isByVal()) {
2080 // Copy relative to framepointer.
2081 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2082 if (StackPtr.getNode() == 0)
2083 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2085 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2087 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2091 // Store relative to framepointer.
2092 MemOpChains2.push_back(
2093 DAG.getStore(ArgChain, dl, Arg, FIN,
2094 PseudoSourceValue::getFixedStack(FI), 0,
2100 if (!MemOpChains2.empty())
2101 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2102 &MemOpChains2[0], MemOpChains2.size());
2104 // Copy arguments to their registers.
2105 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2106 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2107 RegsToPass[i].second, InFlag);
2108 InFlag = Chain.getValue(1);
2112 // Store the return address to the appropriate stack slot.
2113 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2117 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2118 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2119 // In the 64-bit large code model, we have to make all calls
2120 // through a register, since the call instruction's 32-bit
2121 // pc-relative offset may not be large enough to hold the whole
2123 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2124 // If the callee is a GlobalAddress node (quite common, every direct call
2125 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2128 // We should use extra load for direct calls to dllimported functions in
2130 const GlobalValue *GV = G->getGlobal();
2131 if (!GV->hasDLLImportLinkage()) {
2132 unsigned char OpFlags = 0;
2134 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2135 // external symbols most go through the PLT in PIC mode. If the symbol
2136 // has hidden or protected visibility, or if it is static or local, then
2137 // we don't need to use the PLT - we can directly call it.
2138 if (Subtarget->isTargetELF() &&
2139 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2140 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2141 OpFlags = X86II::MO_PLT;
2142 } else if (Subtarget->isPICStyleStubAny() &&
2143 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2144 Subtarget->getDarwinVers() < 9) {
2145 // PC-relative references to external symbols should go through $stub,
2146 // unless we're building with the leopard linker or later, which
2147 // automatically synthesizes these stubs.
2148 OpFlags = X86II::MO_DARWIN_STUB;
2151 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2152 G->getOffset(), OpFlags);
2154 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2155 unsigned char OpFlags = 0;
2157 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2158 // symbols should go through the PLT.
2159 if (Subtarget->isTargetELF() &&
2160 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2161 OpFlags = X86II::MO_PLT;
2162 } else if (Subtarget->isPICStyleStubAny() &&
2163 Subtarget->getDarwinVers() < 9) {
2164 // PC-relative references to external symbols should go through $stub,
2165 // unless we're building with the leopard linker or later, which
2166 // automatically synthesizes these stubs.
2167 OpFlags = X86II::MO_DARWIN_STUB;
2170 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2174 // Returns a chain & a flag for retval copy to use.
2175 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2176 SmallVector<SDValue, 8> Ops;
2178 if (!IsSibcall && isTailCall) {
2179 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2180 DAG.getIntPtrConstant(0, true), InFlag);
2181 InFlag = Chain.getValue(1);
2184 Ops.push_back(Chain);
2185 Ops.push_back(Callee);
2188 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2190 // Add argument registers to the end of the list so that they are known live
2192 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2193 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2194 RegsToPass[i].second.getValueType()));
2196 // Add an implicit use GOT pointer in EBX.
2197 if (!isTailCall && Subtarget->isPICStyleGOT())
2198 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2200 // Add an implicit use of AL for x86 vararg functions.
2201 if (Is64Bit && isVarArg)
2202 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2204 if (InFlag.getNode())
2205 Ops.push_back(InFlag);
2209 //// If this is the first return lowered for this function, add the regs
2210 //// to the liveout set for the function.
2211 // This isn't right, although it's probably harmless on x86; liveouts
2212 // should be computed from returns not tail calls. Consider a void
2213 // function making a tail call to a function returning int.
2214 return DAG.getNode(X86ISD::TC_RETURN, dl,
2215 NodeTys, &Ops[0], Ops.size());
2218 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2219 InFlag = Chain.getValue(1);
2221 // Create the CALLSEQ_END node.
2222 unsigned NumBytesForCalleeToPush;
2223 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2224 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2225 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2226 // If this is a call to a struct-return function, the callee
2227 // pops the hidden struct pointer, so we have to push it back.
2228 // This is common for Darwin/X86, Linux & Mingw32 targets.
2229 NumBytesForCalleeToPush = 4;
2231 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2233 // Returns a flag for retval copy to use.
2235 Chain = DAG.getCALLSEQ_END(Chain,
2236 DAG.getIntPtrConstant(NumBytes, true),
2237 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2240 InFlag = Chain.getValue(1);
2243 // Handle result values, copying them out of physregs into vregs that we
2245 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2246 Ins, dl, DAG, InVals);
2250 //===----------------------------------------------------------------------===//
2251 // Fast Calling Convention (tail call) implementation
2252 //===----------------------------------------------------------------------===//
2254 // Like std call, callee cleans arguments, convention except that ECX is
2255 // reserved for storing the tail called function address. Only 2 registers are
2256 // free for argument passing (inreg). Tail call optimization is performed
2258 // * tailcallopt is enabled
2259 // * caller/callee are fastcc
2260 // On X86_64 architecture with GOT-style position independent code only local
2261 // (within module) calls are supported at the moment.
2262 // To keep the stack aligned according to platform abi the function
2263 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2264 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2265 // If a tail called function callee has more arguments than the caller the
2266 // caller needs to make sure that there is room to move the RETADDR to. This is
2267 // achieved by reserving an area the size of the argument delta right after the
2268 // original REtADDR, but before the saved framepointer or the spilled registers
2269 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2281 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2282 /// for a 16 byte align requirement.
2284 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2285 SelectionDAG& DAG) const {
2286 MachineFunction &MF = DAG.getMachineFunction();
2287 const TargetMachine &TM = MF.getTarget();
2288 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2289 unsigned StackAlignment = TFI.getStackAlignment();
2290 uint64_t AlignMask = StackAlignment - 1;
2291 int64_t Offset = StackSize;
2292 uint64_t SlotSize = TD->getPointerSize();
2293 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2294 // Number smaller than 12 so just add the difference.
2295 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2297 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2298 Offset = ((~AlignMask) & Offset) + StackAlignment +
2299 (StackAlignment-SlotSize);
2304 /// MatchingStackOffset - Return true if the given stack call argument is
2305 /// already available in the same position (relatively) of the caller's
2306 /// incoming argument stack.
2308 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2309 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2310 const X86InstrInfo *TII) {
2311 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2313 if (Arg.getOpcode() == ISD::CopyFromReg) {
2314 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2315 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2317 MachineInstr *Def = MRI->getVRegDef(VR);
2320 if (!Flags.isByVal()) {
2321 if (!TII->isLoadFromStackSlot(Def, FI))
2324 unsigned Opcode = Def->getOpcode();
2325 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2326 Def->getOperand(1).isFI()) {
2327 FI = Def->getOperand(1).getIndex();
2328 Bytes = Flags.getByValSize();
2332 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2333 if (Flags.isByVal())
2334 // ByVal argument is passed in as a pointer but it's now being
2335 // dereferenced. e.g.
2336 // define @foo(%struct.X* %A) {
2337 // tail call @bar(%struct.X* byval %A)
2340 SDValue Ptr = Ld->getBasePtr();
2341 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2344 FI = FINode->getIndex();
2348 assert(FI != INT_MAX);
2349 if (!MFI->isFixedObjectIndex(FI))
2351 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2354 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2355 /// for tail call optimization. Targets which want to do tail call
2356 /// optimization should implement this function.
2358 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2359 CallingConv::ID CalleeCC,
2361 bool isCalleeStructRet,
2362 bool isCallerStructRet,
2363 const SmallVectorImpl<ISD::OutputArg> &Outs,
2364 const SmallVectorImpl<SDValue> &OutVals,
2365 const SmallVectorImpl<ISD::InputArg> &Ins,
2366 SelectionDAG& DAG) const {
2367 if (!IsTailCallConvention(CalleeCC) &&
2368 CalleeCC != CallingConv::C)
2371 // If -tailcallopt is specified, make fastcc functions tail-callable.
2372 const MachineFunction &MF = DAG.getMachineFunction();
2373 const Function *CallerF = DAG.getMachineFunction().getFunction();
2374 CallingConv::ID CallerCC = CallerF->getCallingConv();
2375 bool CCMatch = CallerCC == CalleeCC;
2377 if (GuaranteedTailCallOpt) {
2378 if (IsTailCallConvention(CalleeCC) && CCMatch)
2383 // Look for obvious safe cases to perform tail call optimization that do not
2384 // require ABI changes. This is what gcc calls sibcall.
2386 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2387 // emit a special epilogue.
2388 if (RegInfo->needsStackRealignment(MF))
2391 // Do not sibcall optimize vararg calls unless the call site is not passing
2393 if (isVarArg && !Outs.empty())
2396 // Also avoid sibcall optimization if either caller or callee uses struct
2397 // return semantics.
2398 if (isCalleeStructRet || isCallerStructRet)
2401 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2402 // Therefore if it's not used by the call it is not safe to optimize this into
2404 bool Unused = false;
2405 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2412 SmallVector<CCValAssign, 16> RVLocs;
2413 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2414 RVLocs, *DAG.getContext());
2415 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2416 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = RVLocs[i];
2418 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2423 // If the calling conventions do not match, then we'd better make sure the
2424 // results are returned in the same way as what the caller expects.
2426 SmallVector<CCValAssign, 16> RVLocs1;
2427 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2428 RVLocs1, *DAG.getContext());
2429 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2431 SmallVector<CCValAssign, 16> RVLocs2;
2432 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2433 RVLocs2, *DAG.getContext());
2434 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2436 if (RVLocs1.size() != RVLocs2.size())
2438 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2439 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2441 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2443 if (RVLocs1[i].isRegLoc()) {
2444 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2447 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2453 // If the callee takes no arguments then go on to check the results of the
2455 if (!Outs.empty()) {
2456 // Check if stack adjustment is needed. For now, do not do this if any
2457 // argument is passed on the stack.
2458 SmallVector<CCValAssign, 16> ArgLocs;
2459 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2460 ArgLocs, *DAG.getContext());
2461 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2462 if (CCInfo.getNextStackOffset()) {
2463 MachineFunction &MF = DAG.getMachineFunction();
2464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2466 if (Subtarget->isTargetWin64())
2467 // Win64 ABI has additional complications.
2470 // Check if the arguments are already laid out in the right way as
2471 // the caller's fixed stack objects.
2472 MachineFrameInfo *MFI = MF.getFrameInfo();
2473 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2474 const X86InstrInfo *TII =
2475 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2476 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2477 CCValAssign &VA = ArgLocs[i];
2478 SDValue Arg = OutVals[i];
2479 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2480 if (VA.getLocInfo() == CCValAssign::Indirect)
2482 if (!VA.isRegLoc()) {
2483 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2490 // If the tailcall address may be in a register, then make sure it's
2491 // possible to register allocate for it. In 32-bit, the call address can
2492 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2493 // callee-saved registers are restored. These happen to be the same
2494 // registers used to pass 'inreg' arguments so watch out for those.
2495 if (!Subtarget->is64Bit() &&
2496 !isa<GlobalAddressSDNode>(Callee) &&
2497 !isa<ExternalSymbolSDNode>(Callee)) {
2498 unsigned NumInRegs = 0;
2499 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2500 CCValAssign &VA = ArgLocs[i];
2503 unsigned Reg = VA.getLocReg();
2506 case X86::EAX: case X86::EDX: case X86::ECX:
2507 if (++NumInRegs == 3)
2519 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2520 return X86::createFastISel(funcInfo);
2524 //===----------------------------------------------------------------------===//
2525 // Other Lowering Hooks
2526 //===----------------------------------------------------------------------===//
2529 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2530 MachineFunction &MF = DAG.getMachineFunction();
2531 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2532 int ReturnAddrIndex = FuncInfo->getRAIndex();
2534 if (ReturnAddrIndex == 0) {
2535 // Set up a frame object for the return address.
2536 uint64_t SlotSize = TD->getPointerSize();
2537 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2539 FuncInfo->setRAIndex(ReturnAddrIndex);
2542 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2546 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2547 bool hasSymbolicDisplacement) {
2548 // Offset should fit into 32 bit immediate field.
2549 if (!isInt<32>(Offset))
2552 // If we don't have a symbolic displacement - we don't have any extra
2554 if (!hasSymbolicDisplacement)
2557 // FIXME: Some tweaks might be needed for medium code model.
2558 if (M != CodeModel::Small && M != CodeModel::Kernel)
2561 // For small code model we assume that latest object is 16MB before end of 31
2562 // bits boundary. We may also accept pretty large negative constants knowing
2563 // that all objects are in the positive half of address space.
2564 if (M == CodeModel::Small && Offset < 16*1024*1024)
2567 // For kernel code model we know that all object resist in the negative half
2568 // of 32bits address space. We may not accept negative offsets, since they may
2569 // be just off and we may accept pretty large positive ones.
2570 if (M == CodeModel::Kernel && Offset > 0)
2576 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2577 /// specific condition code, returning the condition code and the LHS/RHS of the
2578 /// comparison to make.
2579 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2580 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2582 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2583 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2584 // X > -1 -> X == 0, jump !sign.
2585 RHS = DAG.getConstant(0, RHS.getValueType());
2586 return X86::COND_NS;
2587 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2588 // X < 0 -> X == 0, jump on sign.
2590 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2592 RHS = DAG.getConstant(0, RHS.getValueType());
2593 return X86::COND_LE;
2597 switch (SetCCOpcode) {
2598 default: llvm_unreachable("Invalid integer condition!");
2599 case ISD::SETEQ: return X86::COND_E;
2600 case ISD::SETGT: return X86::COND_G;
2601 case ISD::SETGE: return X86::COND_GE;
2602 case ISD::SETLT: return X86::COND_L;
2603 case ISD::SETLE: return X86::COND_LE;
2604 case ISD::SETNE: return X86::COND_NE;
2605 case ISD::SETULT: return X86::COND_B;
2606 case ISD::SETUGT: return X86::COND_A;
2607 case ISD::SETULE: return X86::COND_BE;
2608 case ISD::SETUGE: return X86::COND_AE;
2612 // First determine if it is required or is profitable to flip the operands.
2614 // If LHS is a foldable load, but RHS is not, flip the condition.
2615 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2616 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2617 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2618 std::swap(LHS, RHS);
2621 switch (SetCCOpcode) {
2627 std::swap(LHS, RHS);
2631 // On a floating point condition, the flags are set as follows:
2633 // 0 | 0 | 0 | X > Y
2634 // 0 | 0 | 1 | X < Y
2635 // 1 | 0 | 0 | X == Y
2636 // 1 | 1 | 1 | unordered
2637 switch (SetCCOpcode) {
2638 default: llvm_unreachable("Condcode should be pre-legalized away");
2640 case ISD::SETEQ: return X86::COND_E;
2641 case ISD::SETOLT: // flipped
2643 case ISD::SETGT: return X86::COND_A;
2644 case ISD::SETOLE: // flipped
2646 case ISD::SETGE: return X86::COND_AE;
2647 case ISD::SETUGT: // flipped
2649 case ISD::SETLT: return X86::COND_B;
2650 case ISD::SETUGE: // flipped
2652 case ISD::SETLE: return X86::COND_BE;
2654 case ISD::SETNE: return X86::COND_NE;
2655 case ISD::SETUO: return X86::COND_P;
2656 case ISD::SETO: return X86::COND_NP;
2658 case ISD::SETUNE: return X86::COND_INVALID;
2662 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2663 /// code. Current x86 isa includes the following FP cmov instructions:
2664 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2665 static bool hasFPCMov(unsigned X86CC) {
2681 /// isFPImmLegal - Returns true if the target can instruction select the
2682 /// specified FP immediate natively. If false, the legalizer will
2683 /// materialize the FP immediate as a load from a constant pool.
2684 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2685 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2686 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2692 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2693 /// the specified range (L, H].
2694 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2695 return (Val < 0) || (Val >= Low && Val < Hi);
2698 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2699 /// specified value.
2700 static bool isUndefOrEqual(int Val, int CmpVal) {
2701 if (Val < 0 || Val == CmpVal)
2706 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2707 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2708 /// the second operand.
2709 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2710 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2711 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2712 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2713 return (Mask[0] < 2 && Mask[1] < 2);
2717 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2718 SmallVector<int, 8> M;
2720 return ::isPSHUFDMask(M, N->getValueType(0));
2723 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2724 /// is suitable for input to PSHUFHW.
2725 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2726 if (VT != MVT::v8i16)
2729 // Lower quadword copied in order or undef.
2730 for (int i = 0; i != 4; ++i)
2731 if (Mask[i] >= 0 && Mask[i] != i)
2734 // Upper quadword shuffled.
2735 for (int i = 4; i != 8; ++i)
2736 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2742 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2743 SmallVector<int, 8> M;
2745 return ::isPSHUFHWMask(M, N->getValueType(0));
2748 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2749 /// is suitable for input to PSHUFLW.
2750 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2751 if (VT != MVT::v8i16)
2754 // Upper quadword copied in order.
2755 for (int i = 4; i != 8; ++i)
2756 if (Mask[i] >= 0 && Mask[i] != i)
2759 // Lower quadword shuffled.
2760 for (int i = 0; i != 4; ++i)
2767 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2768 SmallVector<int, 8> M;
2770 return ::isPSHUFLWMask(M, N->getValueType(0));
2773 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2774 /// is suitable for input to PALIGNR.
2775 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2777 int i, e = VT.getVectorNumElements();
2779 // Do not handle v2i64 / v2f64 shuffles with palignr.
2780 if (e < 4 || !hasSSSE3)
2783 for (i = 0; i != e; ++i)
2787 // All undef, not a palignr.
2791 // Determine if it's ok to perform a palignr with only the LHS, since we
2792 // don't have access to the actual shuffle elements to see if RHS is undef.
2793 bool Unary = Mask[i] < (int)e;
2794 bool NeedsUnary = false;
2796 int s = Mask[i] - i;
2798 // Check the rest of the elements to see if they are consecutive.
2799 for (++i; i != e; ++i) {
2804 Unary = Unary && (m < (int)e);
2805 NeedsUnary = NeedsUnary || (m < s);
2807 if (NeedsUnary && !Unary)
2809 if (Unary && m != ((s+i) & (e-1)))
2811 if (!Unary && m != (s+i))
2817 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2818 SmallVector<int, 8> M;
2820 return ::isPALIGNRMask(M, N->getValueType(0), true);
2823 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2824 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2825 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2826 int NumElems = VT.getVectorNumElements();
2827 if (NumElems != 2 && NumElems != 4)
2830 int Half = NumElems / 2;
2831 for (int i = 0; i < Half; ++i)
2832 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2834 for (int i = Half; i < NumElems; ++i)
2835 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2841 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2842 SmallVector<int, 8> M;
2844 return ::isSHUFPMask(M, N->getValueType(0));
2847 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2848 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2849 /// half elements to come from vector 1 (which would equal the dest.) and
2850 /// the upper half to come from vector 2.
2851 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2852 int NumElems = VT.getVectorNumElements();
2854 if (NumElems != 2 && NumElems != 4)
2857 int Half = NumElems / 2;
2858 for (int i = 0; i < Half; ++i)
2859 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2861 for (int i = Half; i < NumElems; ++i)
2862 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2867 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2868 SmallVector<int, 8> M;
2870 return isCommutedSHUFPMask(M, N->getValueType(0));
2873 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2874 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2875 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2876 if (N->getValueType(0).getVectorNumElements() != 4)
2879 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2880 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2881 isUndefOrEqual(N->getMaskElt(1), 7) &&
2882 isUndefOrEqual(N->getMaskElt(2), 2) &&
2883 isUndefOrEqual(N->getMaskElt(3), 3);
2886 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2887 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2889 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2890 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2895 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2896 isUndefOrEqual(N->getMaskElt(1), 3) &&
2897 isUndefOrEqual(N->getMaskElt(2), 2) &&
2898 isUndefOrEqual(N->getMaskElt(3), 3);
2901 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2902 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2903 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2904 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2906 if (NumElems != 2 && NumElems != 4)
2909 for (unsigned i = 0; i < NumElems/2; ++i)
2910 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2913 for (unsigned i = NumElems/2; i < NumElems; ++i)
2914 if (!isUndefOrEqual(N->getMaskElt(i), i))
2920 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2921 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2922 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2923 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2925 if (NumElems != 2 && NumElems != 4)
2928 for (unsigned i = 0; i < NumElems/2; ++i)
2929 if (!isUndefOrEqual(N->getMaskElt(i), i))
2932 for (unsigned i = 0; i < NumElems/2; ++i)
2933 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2939 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2940 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2941 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2942 bool V2IsSplat = false) {
2943 int NumElts = VT.getVectorNumElements();
2944 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2947 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2949 int BitI1 = Mask[i+1];
2950 if (!isUndefOrEqual(BitI, j))
2953 if (!isUndefOrEqual(BitI1, NumElts))
2956 if (!isUndefOrEqual(BitI1, j + NumElts))
2963 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2964 SmallVector<int, 8> M;
2966 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2969 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2970 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2971 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2972 bool V2IsSplat = false) {
2973 int NumElts = VT.getVectorNumElements();
2974 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2977 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2979 int BitI1 = Mask[i+1];
2980 if (!isUndefOrEqual(BitI, j + NumElts/2))
2983 if (isUndefOrEqual(BitI1, NumElts))
2986 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2993 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2994 SmallVector<int, 8> M;
2996 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2999 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3000 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3002 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3003 int NumElems = VT.getVectorNumElements();
3004 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3007 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3009 int BitI1 = Mask[i+1];
3010 if (!isUndefOrEqual(BitI, j))
3012 if (!isUndefOrEqual(BitI1, j))
3018 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3019 SmallVector<int, 8> M;
3021 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3024 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3025 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3027 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3028 int NumElems = VT.getVectorNumElements();
3029 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3032 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3034 int BitI1 = Mask[i+1];
3035 if (!isUndefOrEqual(BitI, j))
3037 if (!isUndefOrEqual(BitI1, j))
3043 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3044 SmallVector<int, 8> M;
3046 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3049 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3050 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3051 /// MOVSD, and MOVD, i.e. setting the lowest element.
3052 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3053 if (VT.getVectorElementType().getSizeInBits() < 32)
3056 int NumElts = VT.getVectorNumElements();
3058 if (!isUndefOrEqual(Mask[0], NumElts))
3061 for (int i = 1; i < NumElts; ++i)
3062 if (!isUndefOrEqual(Mask[i], i))
3068 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3069 SmallVector<int, 8> M;
3071 return ::isMOVLMask(M, N->getValueType(0));
3074 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3075 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3076 /// element of vector 2 and the other elements to come from vector 1 in order.
3077 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3078 bool V2IsSplat = false, bool V2IsUndef = false) {
3079 int NumOps = VT.getVectorNumElements();
3080 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3083 if (!isUndefOrEqual(Mask[0], 0))
3086 for (int i = 1; i < NumOps; ++i)
3087 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3088 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3089 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3095 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3096 bool V2IsUndef = false) {
3097 SmallVector<int, 8> M;
3099 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3102 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3103 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3104 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3105 if (N->getValueType(0).getVectorNumElements() != 4)
3108 // Expect 1, 1, 3, 3
3109 for (unsigned i = 0; i < 2; ++i) {
3110 int Elt = N->getMaskElt(i);
3111 if (Elt >= 0 && Elt != 1)
3116 for (unsigned i = 2; i < 4; ++i) {
3117 int Elt = N->getMaskElt(i);
3118 if (Elt >= 0 && Elt != 3)
3123 // Don't use movshdup if it can be done with a shufps.
3124 // FIXME: verify that matching u, u, 3, 3 is what we want.
3128 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3129 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3130 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3131 if (N->getValueType(0).getVectorNumElements() != 4)
3134 // Expect 0, 0, 2, 2
3135 for (unsigned i = 0; i < 2; ++i)
3136 if (N->getMaskElt(i) > 0)
3140 for (unsigned i = 2; i < 4; ++i) {
3141 int Elt = N->getMaskElt(i);
3142 if (Elt >= 0 && Elt != 2)
3147 // Don't use movsldup if it can be done with a shufps.
3151 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3152 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3153 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3154 int e = N->getValueType(0).getVectorNumElements() / 2;
3156 for (int i = 0; i < e; ++i)
3157 if (!isUndefOrEqual(N->getMaskElt(i), i))
3159 for (int i = 0; i < e; ++i)
3160 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3165 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3166 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3167 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3168 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3169 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3171 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3173 for (int i = 0; i < NumOperands; ++i) {
3174 int Val = SVOp->getMaskElt(NumOperands-i-1);
3175 if (Val < 0) Val = 0;
3176 if (Val >= NumOperands) Val -= NumOperands;
3178 if (i != NumOperands - 1)
3184 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3185 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3186 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3187 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3189 // 8 nodes, but we only care about the last 4.
3190 for (unsigned i = 7; i >= 4; --i) {
3191 int Val = SVOp->getMaskElt(i);
3200 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3201 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3202 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3203 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3205 // 8 nodes, but we only care about the first 4.
3206 for (int i = 3; i >= 0; --i) {
3207 int Val = SVOp->getMaskElt(i);
3216 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3217 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3218 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3219 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3220 EVT VVT = N->getValueType(0);
3221 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3225 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3226 Val = SVOp->getMaskElt(i);
3230 return (Val - i) * EltSize;
3233 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3235 bool X86::isZeroNode(SDValue Elt) {
3236 return ((isa<ConstantSDNode>(Elt) &&
3237 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3238 (isa<ConstantFPSDNode>(Elt) &&
3239 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3242 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3243 /// their permute mask.
3244 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3245 SelectionDAG &DAG) {
3246 EVT VT = SVOp->getValueType(0);
3247 unsigned NumElems = VT.getVectorNumElements();
3248 SmallVector<int, 8> MaskVec;
3250 for (unsigned i = 0; i != NumElems; ++i) {
3251 int idx = SVOp->getMaskElt(i);
3253 MaskVec.push_back(idx);
3254 else if (idx < (int)NumElems)
3255 MaskVec.push_back(idx + NumElems);
3257 MaskVec.push_back(idx - NumElems);
3259 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3260 SVOp->getOperand(0), &MaskVec[0]);
3263 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3264 /// the two vector operands have swapped position.
3265 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3266 unsigned NumElems = VT.getVectorNumElements();
3267 for (unsigned i = 0; i != NumElems; ++i) {
3271 else if (idx < (int)NumElems)
3272 Mask[i] = idx + NumElems;
3274 Mask[i] = idx - NumElems;
3278 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3279 /// match movhlps. The lower half elements should come from upper half of
3280 /// V1 (and in order), and the upper half elements should come from the upper
3281 /// half of V2 (and in order).
3282 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3283 if (Op->getValueType(0).getVectorNumElements() != 4)
3285 for (unsigned i = 0, e = 2; i != e; ++i)
3286 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3288 for (unsigned i = 2; i != 4; ++i)
3289 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3294 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3295 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3297 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3298 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3300 N = N->getOperand(0).getNode();
3301 if (!ISD::isNON_EXTLoad(N))
3304 *LD = cast<LoadSDNode>(N);
3308 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3309 /// match movlp{s|d}. The lower half elements should come from lower half of
3310 /// V1 (and in order), and the upper half elements should come from the upper
3311 /// half of V2 (and in order). And since V1 will become the source of the
3312 /// MOVLP, it must be either a vector load or a scalar load to vector.
3313 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3314 ShuffleVectorSDNode *Op) {
3315 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3317 // Is V2 is a vector load, don't do this transformation. We will try to use
3318 // load folding shufps op.
3319 if (ISD::isNON_EXTLoad(V2))
3322 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3324 if (NumElems != 2 && NumElems != 4)
3326 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3327 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3329 for (unsigned i = NumElems/2; i != NumElems; ++i)
3330 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3335 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3337 static bool isSplatVector(SDNode *N) {
3338 if (N->getOpcode() != ISD::BUILD_VECTOR)
3341 SDValue SplatValue = N->getOperand(0);
3342 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3343 if (N->getOperand(i) != SplatValue)
3348 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3349 /// to an zero vector.
3350 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3351 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3352 SDValue V1 = N->getOperand(0);
3353 SDValue V2 = N->getOperand(1);
3354 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3355 for (unsigned i = 0; i != NumElems; ++i) {
3356 int Idx = N->getMaskElt(i);
3357 if (Idx >= (int)NumElems) {
3358 unsigned Opc = V2.getOpcode();
3359 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3361 if (Opc != ISD::BUILD_VECTOR ||
3362 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3364 } else if (Idx >= 0) {
3365 unsigned Opc = V1.getOpcode();
3366 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3368 if (Opc != ISD::BUILD_VECTOR ||
3369 !X86::isZeroNode(V1.getOperand(Idx)))
3376 /// getZeroVector - Returns a vector of specified type with all zero elements.
3378 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3380 assert(VT.isVector() && "Expected a vector type");
3382 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3383 // type. This ensures they get CSE'd.
3385 if (VT.getSizeInBits() == 64) { // MMX
3386 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3387 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3388 } else if (HasSSE2) { // SSE2
3389 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3390 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3392 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3393 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3395 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3398 /// getOnesVector - Returns a vector of specified type with all bits set.
3400 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3401 assert(VT.isVector() && "Expected a vector type");
3403 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3404 // type. This ensures they get CSE'd.
3405 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3407 if (VT.getSizeInBits() == 64) // MMX
3408 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3410 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3411 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3415 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3416 /// that point to V2 points to its first element.
3417 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3418 EVT VT = SVOp->getValueType(0);
3419 unsigned NumElems = VT.getVectorNumElements();
3421 bool Changed = false;
3422 SmallVector<int, 8> MaskVec;
3423 SVOp->getMask(MaskVec);
3425 for (unsigned i = 0; i != NumElems; ++i) {
3426 if (MaskVec[i] > (int)NumElems) {
3427 MaskVec[i] = NumElems;
3432 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3433 SVOp->getOperand(1), &MaskVec[0]);
3434 return SDValue(SVOp, 0);
3437 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3438 /// operation of specified width.
3439 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3441 unsigned NumElems = VT.getVectorNumElements();
3442 SmallVector<int, 8> Mask;
3443 Mask.push_back(NumElems);
3444 for (unsigned i = 1; i != NumElems; ++i)
3446 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3449 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3450 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3452 unsigned NumElems = VT.getVectorNumElements();
3453 SmallVector<int, 8> Mask;
3454 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3456 Mask.push_back(i + NumElems);
3458 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3461 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3462 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3464 unsigned NumElems = VT.getVectorNumElements();
3465 unsigned Half = NumElems/2;
3466 SmallVector<int, 8> Mask;
3467 for (unsigned i = 0; i != Half; ++i) {
3468 Mask.push_back(i + Half);
3469 Mask.push_back(i + NumElems + Half);
3471 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3474 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3475 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3477 if (SV->getValueType(0).getVectorNumElements() <= 4)
3478 return SDValue(SV, 0);
3480 EVT PVT = MVT::v4f32;
3481 EVT VT = SV->getValueType(0);
3482 DebugLoc dl = SV->getDebugLoc();
3483 SDValue V1 = SV->getOperand(0);
3484 int NumElems = VT.getVectorNumElements();
3485 int EltNo = SV->getSplatIndex();
3487 // unpack elements to the correct location
3488 while (NumElems > 4) {
3489 if (EltNo < NumElems/2) {
3490 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3492 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3493 EltNo -= NumElems/2;
3498 // Perform the splat.
3499 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3500 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3501 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3502 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3505 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3506 /// vector of zero or undef vector. This produces a shuffle where the low
3507 /// element of V2 is swizzled into the zero/undef vector, landing at element
3508 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3509 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3510 bool isZero, bool HasSSE2,
3511 SelectionDAG &DAG) {
3512 EVT VT = V2.getValueType();
3514 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3515 unsigned NumElems = VT.getVectorNumElements();
3516 SmallVector<int, 16> MaskVec;
3517 for (unsigned i = 0; i != NumElems; ++i)
3518 // If this is the insertion idx, put the low elt of V2 here.
3519 MaskVec.push_back(i == Idx ? NumElems : i);
3520 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3523 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3524 /// a shuffle that is zero.
3526 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3527 bool Low, SelectionDAG &DAG) {
3528 unsigned NumZeros = 0;
3529 for (int i = 0; i < NumElems; ++i) {
3530 unsigned Index = Low ? i : NumElems-i-1;
3531 int Idx = SVOp->getMaskElt(Index);
3536 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3537 if (Elt.getNode() && X86::isZeroNode(Elt))
3545 /// isVectorShift - Returns true if the shuffle can be implemented as a
3546 /// logical left or right shift of a vector.
3547 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3548 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3549 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3550 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3553 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3556 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3560 bool SeenV1 = false;
3561 bool SeenV2 = false;
3562 for (unsigned i = NumZeros; i < NumElems; ++i) {
3563 unsigned Val = isLeft ? (i - NumZeros) : i;
3564 int Idx_ = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3567 unsigned Idx = (unsigned) Idx_;
3577 if (SeenV1 && SeenV2)
3580 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3586 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3588 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3589 unsigned NumNonZero, unsigned NumZero,
3591 const TargetLowering &TLI) {
3595 DebugLoc dl = Op.getDebugLoc();
3598 for (unsigned i = 0; i < 16; ++i) {
3599 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3600 if (ThisIsNonZero && First) {
3602 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3604 V = DAG.getUNDEF(MVT::v8i16);
3609 SDValue ThisElt(0, 0), LastElt(0, 0);
3610 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3611 if (LastIsNonZero) {
3612 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3613 MVT::i16, Op.getOperand(i-1));
3615 if (ThisIsNonZero) {
3616 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3617 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3618 ThisElt, DAG.getConstant(8, MVT::i8));
3620 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3624 if (ThisElt.getNode())
3625 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3626 DAG.getIntPtrConstant(i/2));
3630 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3633 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3635 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3636 unsigned NumNonZero, unsigned NumZero,
3638 const TargetLowering &TLI) {
3642 DebugLoc dl = Op.getDebugLoc();
3645 for (unsigned i = 0; i < 8; ++i) {
3646 bool isNonZero = (NonZeros & (1 << i)) != 0;
3650 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3652 V = DAG.getUNDEF(MVT::v8i16);
3655 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3656 MVT::v8i16, V, Op.getOperand(i),
3657 DAG.getIntPtrConstant(i));
3664 /// getVShift - Return a vector logical shift node.
3666 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3667 unsigned NumBits, SelectionDAG &DAG,
3668 const TargetLowering &TLI, DebugLoc dl) {
3669 bool isMMX = VT.getSizeInBits() == 64;
3670 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3671 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3672 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3673 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3674 DAG.getNode(Opc, dl, ShVT, SrcOp,
3675 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3679 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3680 SelectionDAG &DAG) const {
3682 // Check if the scalar load can be widened into a vector load. And if
3683 // the address is "base + cst" see if the cst can be "absorbed" into
3684 // the shuffle mask.
3685 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3686 SDValue Ptr = LD->getBasePtr();
3687 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3689 EVT PVT = LD->getValueType(0);
3690 if (PVT != MVT::i32 && PVT != MVT::f32)
3695 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3696 FI = FINode->getIndex();
3698 } else if (Ptr.getOpcode() == ISD::ADD &&
3699 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3700 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3701 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3702 Offset = Ptr.getConstantOperandVal(1);
3703 Ptr = Ptr.getOperand(0);
3708 SDValue Chain = LD->getChain();
3709 // Make sure the stack object alignment is at least 16.
3710 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3711 if (DAG.InferPtrAlignment(Ptr) < 16) {
3712 if (MFI->isFixedObjectIndex(FI)) {
3713 // Can't change the alignment. FIXME: It's possible to compute
3714 // the exact stack offset and reference FI + adjust offset instead.
3715 // If someone *really* cares about this. That's the way to implement it.
3718 MFI->setObjectAlignment(FI, 16);
3722 // (Offset % 16) must be multiple of 4. Then address is then
3723 // Ptr + (Offset & ~15).
3726 if ((Offset % 16) & 3)
3728 int64_t StartOffset = Offset & ~15;
3730 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3731 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3733 int EltNo = (Offset - StartOffset) >> 2;
3734 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3735 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3736 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3738 // Canonicalize it to a v4i32 shuffle.
3739 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3740 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3741 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3742 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3748 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
3749 /// vector of type 'VT', see if the elements can be replaced by a single large
3750 /// load which has the same value as a build_vector whose operands are 'elts'.
3752 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
3754 /// FIXME: we'd also like to handle the case where the last elements are zero
3755 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
3756 /// There's even a handy isZeroNode for that purpose.
3757 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
3758 DebugLoc &dl, SelectionDAG &DAG) {
3759 EVT EltVT = VT.getVectorElementType();
3760 unsigned NumElems = Elts.size();
3762 LoadSDNode *LDBase = NULL;
3763 unsigned LastLoadedElt = -1U;
3765 // For each element in the initializer, see if we've found a load or an undef.
3766 // If we don't find an initial load element, or later load elements are
3767 // non-consecutive, bail out.
3768 for (unsigned i = 0; i < NumElems; ++i) {
3769 SDValue Elt = Elts[i];
3771 if (!Elt.getNode() ||
3772 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
3775 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
3777 LDBase = cast<LoadSDNode>(Elt.getNode());
3781 if (Elt.getOpcode() == ISD::UNDEF)
3784 LoadSDNode *LD = cast<LoadSDNode>(Elt);
3785 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
3790 // If we have found an entire vector of loads and undefs, then return a large
3791 // load of the entire vector width starting at the base pointer. If we found
3792 // consecutive loads for the low half, generate a vzext_load node.
3793 if (LastLoadedElt == NumElems - 1) {
3794 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
3795 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3796 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3797 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
3798 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3799 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3800 LDBase->isVolatile(), LDBase->isNonTemporal(),
3801 LDBase->getAlignment());
3802 } else if (NumElems == 4 && LastLoadedElt == 1) {
3803 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
3804 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
3805 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
3806 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
3812 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
3813 DebugLoc dl = Op.getDebugLoc();
3814 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3815 if (ISD::isBuildVectorAllZeros(Op.getNode())
3816 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3817 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3818 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3819 // eliminated on x86-32 hosts.
3820 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3823 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3824 return getOnesVector(Op.getValueType(), DAG, dl);
3825 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3828 EVT VT = Op.getValueType();
3829 EVT ExtVT = VT.getVectorElementType();
3830 unsigned EVTBits = ExtVT.getSizeInBits();
3832 unsigned NumElems = Op.getNumOperands();
3833 unsigned NumZero = 0;
3834 unsigned NumNonZero = 0;
3835 unsigned NonZeros = 0;
3836 bool IsAllConstants = true;
3837 SmallSet<SDValue, 8> Values;
3838 for (unsigned i = 0; i < NumElems; ++i) {
3839 SDValue Elt = Op.getOperand(i);
3840 if (Elt.getOpcode() == ISD::UNDEF)
3843 if (Elt.getOpcode() != ISD::Constant &&
3844 Elt.getOpcode() != ISD::ConstantFP)
3845 IsAllConstants = false;
3846 if (X86::isZeroNode(Elt))
3849 NonZeros |= (1 << i);
3854 if (NumNonZero == 0) {
3855 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3856 return DAG.getUNDEF(VT);
3859 // Special case for single non-zero, non-undef, element.
3860 if (NumNonZero == 1) {
3861 unsigned Idx = CountTrailingZeros_32(NonZeros);
3862 SDValue Item = Op.getOperand(Idx);
3864 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3865 // the value are obviously zero, truncate the value to i32 and do the
3866 // insertion that way. Only do this if the value is non-constant or if the
3867 // value is a constant being inserted into element 0. It is cheaper to do
3868 // a constant pool load than it is to do a movd + shuffle.
3869 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3870 (!IsAllConstants || Idx == 0)) {
3871 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3872 // Handle MMX and SSE both.
3873 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3874 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3876 // Truncate the value (which may itself be a constant) to i32, and
3877 // convert it to a vector with movd (S2V+shuffle to zero extend).
3878 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3880 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3881 Subtarget->hasSSE2(), DAG);
3883 // Now we have our 32-bit value zero extended in the low element of
3884 // a vector. If Idx != 0, swizzle it into place.
3886 SmallVector<int, 4> Mask;
3887 Mask.push_back(Idx);
3888 for (unsigned i = 1; i != VecElts; ++i)
3890 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3891 DAG.getUNDEF(Item.getValueType()),
3894 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3898 // If we have a constant or non-constant insertion into the low element of
3899 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3900 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3901 // depending on what the source datatype is.
3904 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3905 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3906 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3907 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3908 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3909 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3911 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3912 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3913 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3914 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3915 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3916 Subtarget->hasSSE2(), DAG);
3917 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3921 // Is it a vector logical left shift?
3922 if (NumElems == 2 && Idx == 1 &&
3923 X86::isZeroNode(Op.getOperand(0)) &&
3924 !X86::isZeroNode(Op.getOperand(1))) {
3925 unsigned NumBits = VT.getSizeInBits();
3926 return getVShift(true, VT,
3927 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3928 VT, Op.getOperand(1)),
3929 NumBits/2, DAG, *this, dl);
3932 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3935 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3936 // is a non-constant being inserted into an element other than the low one,
3937 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3938 // movd/movss) to move this into the low element, then shuffle it into
3940 if (EVTBits == 32) {
3941 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3943 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3944 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3945 Subtarget->hasSSE2(), DAG);
3946 SmallVector<int, 8> MaskVec;
3947 for (unsigned i = 0; i < NumElems; i++)
3948 MaskVec.push_back(i == Idx ? 0 : 1);
3949 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3953 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3954 if (Values.size() == 1) {
3955 if (EVTBits == 32) {
3956 // Instead of a shuffle like this:
3957 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3958 // Check if it's possible to issue this instead.
3959 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3960 unsigned Idx = CountTrailingZeros_32(NonZeros);
3961 SDValue Item = Op.getOperand(Idx);
3962 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3963 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3968 // A vector full of immediates; various special cases are already
3969 // handled, so this is best done with a single constant-pool load.
3973 // Let legalizer expand 2-wide build_vectors.
3974 if (EVTBits == 64) {
3975 if (NumNonZero == 1) {
3976 // One half is zero or undef.
3977 unsigned Idx = CountTrailingZeros_32(NonZeros);
3978 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3979 Op.getOperand(Idx));
3980 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3981 Subtarget->hasSSE2(), DAG);
3986 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3987 if (EVTBits == 8 && NumElems == 16) {
3988 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3990 if (V.getNode()) return V;
3993 if (EVTBits == 16 && NumElems == 8) {
3994 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3996 if (V.getNode()) return V;
3999 // If element VT is == 32 bits, turn it into a number of shuffles.
4000 SmallVector<SDValue, 8> V;
4002 if (NumElems == 4 && NumZero > 0) {
4003 for (unsigned i = 0; i < 4; ++i) {
4004 bool isZero = !(NonZeros & (1 << i));
4006 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4011 for (unsigned i = 0; i < 2; ++i) {
4012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4015 V[i] = V[i*2]; // Must be a zero vector.
4018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4029 SmallVector<int, 8> MaskVec;
4030 bool Reverse = (NonZeros & 0x3) == 2;
4031 for (unsigned i = 0; i < 2; ++i)
4032 MaskVec.push_back(Reverse ? 1-i : i);
4033 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4034 for (unsigned i = 0; i < 2; ++i)
4035 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4036 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4039 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4040 // Check for a build vector of consecutive loads.
4041 for (unsigned i = 0; i < NumElems; ++i)
4042 V[i] = Op.getOperand(i);
4044 // Check for elements which are consecutive loads.
4045 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4049 // For SSE 4.1, use inserts into undef.
4050 if (getSubtarget()->hasSSE41()) {
4051 V[0] = DAG.getUNDEF(VT);
4052 for (unsigned i = 0; i < NumElems; ++i)
4053 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4054 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
4055 Op.getOperand(i), DAG.getIntPtrConstant(i));
4059 // Otherwise, expand into a number of unpckl*
4061 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4062 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4063 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4064 for (unsigned i = 0; i < NumElems; ++i)
4065 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4067 while (NumElems != 0) {
4068 for (unsigned i = 0; i < NumElems; ++i)
4069 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
4078 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4079 // We support concatenate two MMX registers and place them in a MMX
4080 // register. This is better than doing a stack convert.
4081 DebugLoc dl = Op.getDebugLoc();
4082 EVT ResVT = Op.getValueType();
4083 assert(Op.getNumOperands() == 2);
4084 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4085 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4087 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4088 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4089 InVec = Op.getOperand(1);
4090 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4091 unsigned NumElts = ResVT.getVectorNumElements();
4092 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4093 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4094 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4096 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4097 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4098 Mask[0] = 0; Mask[1] = 2;
4099 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4101 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4104 // v8i16 shuffles - Prefer shuffles in the following order:
4105 // 1. [all] pshuflw, pshufhw, optional move
4106 // 2. [ssse3] 1 x pshufb
4107 // 3. [ssse3] 2 x pshufb + 1 x por
4108 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4110 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
4112 const X86TargetLowering &TLI) {
4113 SDValue V1 = SVOp->getOperand(0);
4114 SDValue V2 = SVOp->getOperand(1);
4115 DebugLoc dl = SVOp->getDebugLoc();
4116 SmallVector<int, 8> MaskVals;
4118 // Determine if more than 1 of the words in each of the low and high quadwords
4119 // of the result come from the same quadword of one of the two inputs. Undef
4120 // mask values count as coming from any quadword, for better codegen.
4121 SmallVector<unsigned, 4> LoQuad(4);
4122 SmallVector<unsigned, 4> HiQuad(4);
4123 BitVector InputQuads(4);
4124 for (unsigned i = 0; i < 8; ++i) {
4125 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4126 int EltIdx = SVOp->getMaskElt(i);
4127 MaskVals.push_back(EltIdx);
4136 InputQuads.set(EltIdx / 4);
4139 int BestLoQuad = -1;
4140 unsigned MaxQuad = 1;
4141 for (unsigned i = 0; i < 4; ++i) {
4142 if (LoQuad[i] > MaxQuad) {
4144 MaxQuad = LoQuad[i];
4148 int BestHiQuad = -1;
4150 for (unsigned i = 0; i < 4; ++i) {
4151 if (HiQuad[i] > MaxQuad) {
4153 MaxQuad = HiQuad[i];
4157 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4158 // of the two input vectors, shuffle them into one input vector so only a
4159 // single pshufb instruction is necessary. If There are more than 2 input
4160 // quads, disable the next transformation since it does not help SSSE3.
4161 bool V1Used = InputQuads[0] || InputQuads[1];
4162 bool V2Used = InputQuads[2] || InputQuads[3];
4163 if (TLI.getSubtarget()->hasSSSE3()) {
4164 if (InputQuads.count() == 2 && V1Used && V2Used) {
4165 BestLoQuad = InputQuads.find_first();
4166 BestHiQuad = InputQuads.find_next(BestLoQuad);
4168 if (InputQuads.count() > 2) {
4174 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4175 // the shuffle mask. If a quad is scored as -1, that means that it contains
4176 // words from all 4 input quadwords.
4178 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4179 SmallVector<int, 8> MaskV;
4180 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4181 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4182 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4183 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4184 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4185 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4187 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4188 // source words for the shuffle, to aid later transformations.
4189 bool AllWordsInNewV = true;
4190 bool InOrder[2] = { true, true };
4191 for (unsigned i = 0; i != 8; ++i) {
4192 int idx = MaskVals[i];
4194 InOrder[i/4] = false;
4195 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4197 AllWordsInNewV = false;
4201 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4202 if (AllWordsInNewV) {
4203 for (int i = 0; i != 8; ++i) {
4204 int idx = MaskVals[i];
4207 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4208 if ((idx != i) && idx < 4)
4210 if ((idx != i) && idx > 3)
4219 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4220 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4221 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4222 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4223 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4227 // If we have SSSE3, and all words of the result are from 1 input vector,
4228 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4229 // is present, fall back to case 4.
4230 if (TLI.getSubtarget()->hasSSSE3()) {
4231 SmallVector<SDValue,16> pshufbMask;
4233 // If we have elements from both input vectors, set the high bit of the
4234 // shuffle mask element to zero out elements that come from V2 in the V1
4235 // mask, and elements that come from V1 in the V2 mask, so that the two
4236 // results can be OR'd together.
4237 bool TwoInputs = V1Used && V2Used;
4238 for (unsigned i = 0; i != 8; ++i) {
4239 int EltIdx = MaskVals[i] * 2;
4240 if (TwoInputs && (EltIdx >= 16)) {
4241 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4242 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4245 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4246 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4248 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4249 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4250 DAG.getNode(ISD::BUILD_VECTOR, dl,
4251 MVT::v16i8, &pshufbMask[0], 16));
4253 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4255 // Calculate the shuffle mask for the second input, shuffle it, and
4256 // OR it with the first shuffled input.
4258 for (unsigned i = 0; i != 8; ++i) {
4259 int EltIdx = MaskVals[i] * 2;
4261 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4262 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4265 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4266 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4268 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4269 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4270 DAG.getNode(ISD::BUILD_VECTOR, dl,
4271 MVT::v16i8, &pshufbMask[0], 16));
4272 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4273 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4276 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4277 // and update MaskVals with new element order.
4278 BitVector InOrder(8);
4279 if (BestLoQuad >= 0) {
4280 SmallVector<int, 8> MaskV;
4281 for (int i = 0; i != 4; ++i) {
4282 int idx = MaskVals[i];
4284 MaskV.push_back(-1);
4286 } else if ((idx / 4) == BestLoQuad) {
4287 MaskV.push_back(idx & 3);
4290 MaskV.push_back(-1);
4293 for (unsigned i = 4; i != 8; ++i)
4295 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4299 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4300 // and update MaskVals with the new element order.
4301 if (BestHiQuad >= 0) {
4302 SmallVector<int, 8> MaskV;
4303 for (unsigned i = 0; i != 4; ++i)
4305 for (unsigned i = 4; i != 8; ++i) {
4306 int idx = MaskVals[i];
4308 MaskV.push_back(-1);
4310 } else if ((idx / 4) == BestHiQuad) {
4311 MaskV.push_back((idx & 3) + 4);
4314 MaskV.push_back(-1);
4317 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4321 // In case BestHi & BestLo were both -1, which means each quadword has a word
4322 // from each of the four input quadwords, calculate the InOrder bitvector now
4323 // before falling through to the insert/extract cleanup.
4324 if (BestLoQuad == -1 && BestHiQuad == -1) {
4326 for (int i = 0; i != 8; ++i)
4327 if (MaskVals[i] < 0 || MaskVals[i] == i)
4331 // The other elements are put in the right place using pextrw and pinsrw.
4332 for (unsigned i = 0; i != 8; ++i) {
4335 int EltIdx = MaskVals[i];
4338 SDValue ExtOp = (EltIdx < 8)
4339 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4340 DAG.getIntPtrConstant(EltIdx))
4341 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4342 DAG.getIntPtrConstant(EltIdx - 8));
4343 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4344 DAG.getIntPtrConstant(i));
4349 // v16i8 shuffles - Prefer shuffles in the following order:
4350 // 1. [ssse3] 1 x pshufb
4351 // 2. [ssse3] 2 x pshufb + 1 x por
4352 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4354 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4356 const X86TargetLowering &TLI) {
4357 SDValue V1 = SVOp->getOperand(0);
4358 SDValue V2 = SVOp->getOperand(1);
4359 DebugLoc dl = SVOp->getDebugLoc();
4360 SmallVector<int, 16> MaskVals;
4361 SVOp->getMask(MaskVals);
4363 // If we have SSSE3, case 1 is generated when all result bytes come from
4364 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4365 // present, fall back to case 3.
4366 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4369 for (unsigned i = 0; i < 16; ++i) {
4370 int EltIdx = MaskVals[i];
4379 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4380 if (TLI.getSubtarget()->hasSSSE3()) {
4381 SmallVector<SDValue,16> pshufbMask;
4383 // If all result elements are from one input vector, then only translate
4384 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4386 // Otherwise, we have elements from both input vectors, and must zero out
4387 // elements that come from V2 in the first mask, and V1 in the second mask
4388 // so that we can OR them together.
4389 bool TwoInputs = !(V1Only || V2Only);
4390 for (unsigned i = 0; i != 16; ++i) {
4391 int EltIdx = MaskVals[i];
4392 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4393 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4396 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4398 // If all the elements are from V2, assign it to V1 and return after
4399 // building the first pshufb.
4402 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4403 DAG.getNode(ISD::BUILD_VECTOR, dl,
4404 MVT::v16i8, &pshufbMask[0], 16));
4408 // Calculate the shuffle mask for the second input, shuffle it, and
4409 // OR it with the first shuffled input.
4411 for (unsigned i = 0; i != 16; ++i) {
4412 int EltIdx = MaskVals[i];
4414 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4417 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4419 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4420 DAG.getNode(ISD::BUILD_VECTOR, dl,
4421 MVT::v16i8, &pshufbMask[0], 16));
4422 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4425 // No SSSE3 - Calculate in place words and then fix all out of place words
4426 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4427 // the 16 different words that comprise the two doublequadword input vectors.
4428 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4429 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4430 SDValue NewV = V2Only ? V2 : V1;
4431 for (int i = 0; i != 8; ++i) {
4432 int Elt0 = MaskVals[i*2];
4433 int Elt1 = MaskVals[i*2+1];
4435 // This word of the result is all undef, skip it.
4436 if (Elt0 < 0 && Elt1 < 0)
4439 // This word of the result is already in the correct place, skip it.
4440 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4442 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4445 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4446 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4449 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4450 // using a single extract together, load it and store it.
4451 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4452 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4453 DAG.getIntPtrConstant(Elt1 / 2));
4454 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4455 DAG.getIntPtrConstant(i));
4459 // If Elt1 is defined, extract it from the appropriate source. If the
4460 // source byte is not also odd, shift the extracted word left 8 bits
4461 // otherwise clear the bottom 8 bits if we need to do an or.
4463 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4464 DAG.getIntPtrConstant(Elt1 / 2));
4465 if ((Elt1 & 1) == 0)
4466 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4467 DAG.getConstant(8, TLI.getShiftAmountTy()));
4469 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4470 DAG.getConstant(0xFF00, MVT::i16));
4472 // If Elt0 is defined, extract it from the appropriate source. If the
4473 // source byte is not also even, shift the extracted word right 8 bits. If
4474 // Elt1 was also defined, OR the extracted values together before
4475 // inserting them in the result.
4477 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4478 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4479 if ((Elt0 & 1) != 0)
4480 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4481 DAG.getConstant(8, TLI.getShiftAmountTy()));
4483 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4484 DAG.getConstant(0x00FF, MVT::i16));
4485 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4488 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4489 DAG.getIntPtrConstant(i));
4491 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4494 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4495 /// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be
4496 /// done when every pair / quad of shuffle mask elements point to elements in
4497 /// the right sequence. e.g.
4498 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4500 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4502 const TargetLowering &TLI, DebugLoc dl) {
4503 EVT VT = SVOp->getValueType(0);
4504 SDValue V1 = SVOp->getOperand(0);
4505 SDValue V2 = SVOp->getOperand(1);
4506 unsigned NumElems = VT.getVectorNumElements();
4507 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4508 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4510 switch (VT.getSimpleVT().SimpleTy) {
4511 default: assert(false && "Unexpected!");
4512 case MVT::v4f32: NewVT = MVT::v2f64; break;
4513 case MVT::v4i32: NewVT = MVT::v2i64; break;
4514 case MVT::v8i16: NewVT = MVT::v4i32; break;
4515 case MVT::v16i8: NewVT = MVT::v4i32; break;
4518 if (NewWidth == 2) {
4524 int Scale = NumElems / NewWidth;
4525 SmallVector<int, 8> MaskVec;
4526 for (unsigned i = 0; i < NumElems; i += Scale) {
4528 for (int j = 0; j < Scale; ++j) {
4529 int EltIdx = SVOp->getMaskElt(i+j);
4533 StartIdx = EltIdx - (EltIdx % Scale);
4534 if (EltIdx != StartIdx + j)
4538 MaskVec.push_back(-1);
4540 MaskVec.push_back(StartIdx / Scale);
4543 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4544 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4545 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4548 /// getVZextMovL - Return a zero-extending vector move low node.
4550 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4551 SDValue SrcOp, SelectionDAG &DAG,
4552 const X86Subtarget *Subtarget, DebugLoc dl) {
4553 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4554 LoadSDNode *LD = NULL;
4555 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4556 LD = dyn_cast<LoadSDNode>(SrcOp);
4558 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4560 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4561 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4562 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4563 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4564 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4566 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4567 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4568 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4569 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4577 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4578 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4579 DAG.getNode(ISD::BIT_CONVERT, dl,
4583 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4586 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4587 SDValue V1 = SVOp->getOperand(0);
4588 SDValue V2 = SVOp->getOperand(1);
4589 DebugLoc dl = SVOp->getDebugLoc();
4590 EVT VT = SVOp->getValueType(0);
4592 SmallVector<std::pair<int, int>, 8> Locs;
4594 SmallVector<int, 8> Mask1(4U, -1);
4595 SmallVector<int, 8> PermMask;
4596 SVOp->getMask(PermMask);
4600 for (unsigned i = 0; i != 4; ++i) {
4601 int Idx = PermMask[i];
4603 Locs[i] = std::make_pair(-1, -1);
4605 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4607 Locs[i] = std::make_pair(0, NumLo);
4611 Locs[i] = std::make_pair(1, NumHi);
4613 Mask1[2+NumHi] = Idx;
4619 if (NumLo <= 2 && NumHi <= 2) {
4620 // If no more than two elements come from either vector. This can be
4621 // implemented with two shuffles. First shuffle gather the elements.
4622 // The second shuffle, which takes the first shuffle as both of its
4623 // vector operands, put the elements into the right order.
4624 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4626 SmallVector<int, 8> Mask2(4U, -1);
4628 for (unsigned i = 0; i != 4; ++i) {
4629 if (Locs[i].first == -1)
4632 unsigned Idx = (i < 2) ? 0 : 4;
4633 Idx += Locs[i].first * 2 + Locs[i].second;
4638 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4639 } else if (NumLo == 3 || NumHi == 3) {
4640 // Otherwise, we must have three elements from one vector, call it X, and
4641 // one element from the other, call it Y. First, use a shufps to build an
4642 // intermediate vector with the one element from Y and the element from X
4643 // that will be in the same half in the final destination (the indexes don't
4644 // matter). Then, use a shufps to build the final vector, taking the half
4645 // containing the element from Y from the intermediate, and the other half
4648 // Normalize it so the 3 elements come from V1.
4649 CommuteVectorShuffleMask(PermMask, VT);
4653 // Find the element from V2.
4655 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4656 int Val = PermMask[HiIndex];
4663 Mask1[0] = PermMask[HiIndex];
4665 Mask1[2] = PermMask[HiIndex^1];
4667 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4670 Mask1[0] = PermMask[0];
4671 Mask1[1] = PermMask[1];
4672 Mask1[2] = HiIndex & 1 ? 6 : 4;
4673 Mask1[3] = HiIndex & 1 ? 4 : 6;
4674 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4676 Mask1[0] = HiIndex & 1 ? 2 : 0;
4677 Mask1[1] = HiIndex & 1 ? 0 : 2;
4678 Mask1[2] = PermMask[2];
4679 Mask1[3] = PermMask[3];
4684 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4688 // Break it into (shuffle shuffle_hi, shuffle_lo).
4690 SmallVector<int,8> LoMask(4U, -1);
4691 SmallVector<int,8> HiMask(4U, -1);
4693 SmallVector<int,8> *MaskPtr = &LoMask;
4694 unsigned MaskIdx = 0;
4697 for (unsigned i = 0; i != 4; ++i) {
4704 int Idx = PermMask[i];
4706 Locs[i] = std::make_pair(-1, -1);
4707 } else if (Idx < 4) {
4708 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4709 (*MaskPtr)[LoIdx] = Idx;
4712 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4713 (*MaskPtr)[HiIdx] = Idx;
4718 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4719 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4720 SmallVector<int, 8> MaskOps;
4721 for (unsigned i = 0; i != 4; ++i) {
4722 if (Locs[i].first == -1) {
4723 MaskOps.push_back(-1);
4725 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4726 MaskOps.push_back(Idx);
4729 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4733 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
4734 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4735 SDValue V1 = Op.getOperand(0);
4736 SDValue V2 = Op.getOperand(1);
4737 EVT VT = Op.getValueType();
4738 DebugLoc dl = Op.getDebugLoc();
4739 unsigned NumElems = VT.getVectorNumElements();
4740 bool isMMX = VT.getSizeInBits() == 64;
4741 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4742 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4743 bool V1IsSplat = false;
4744 bool V2IsSplat = false;
4746 if (isZeroShuffle(SVOp))
4747 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4749 // Promote splats to v4f32.
4750 if (SVOp->isSplat()) {
4751 if (isMMX || NumElems < 4)
4753 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4756 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4758 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4759 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4760 if (NewOp.getNode())
4761 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4762 LowerVECTOR_SHUFFLE(NewOp, DAG));
4763 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4764 // FIXME: Figure out a cleaner way to do this.
4765 // Try to make use of movq to zero out the top part.
4766 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4767 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4768 if (NewOp.getNode()) {
4769 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4770 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4771 DAG, Subtarget, dl);
4773 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4774 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4775 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4776 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4777 DAG, Subtarget, dl);
4781 if (X86::isPSHUFDMask(SVOp))
4784 // Check if this can be converted into a logical shift.
4785 bool isLeft = false;
4788 bool isShift = getSubtarget()->hasSSE2() &&
4789 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4790 if (isShift && ShVal.hasOneUse()) {
4791 // If the shifted value has multiple uses, it may be cheaper to use
4792 // v_set0 + movlhps or movhlps, etc.
4793 EVT EltVT = VT.getVectorElementType();
4794 ShAmt *= EltVT.getSizeInBits();
4795 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4798 if (X86::isMOVLMask(SVOp)) {
4801 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4802 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4807 // FIXME: fold these into legal mask.
4808 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4809 X86::isMOVSLDUPMask(SVOp) ||
4810 X86::isMOVHLPSMask(SVOp) ||
4811 X86::isMOVLHPSMask(SVOp) ||
4812 X86::isMOVLPMask(SVOp)))
4815 if (ShouldXformToMOVHLPS(SVOp) ||
4816 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4817 return CommuteVectorShuffle(SVOp, DAG);
4820 // No better options. Use a vshl / vsrl.
4821 EVT EltVT = VT.getVectorElementType();
4822 ShAmt *= EltVT.getSizeInBits();
4823 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4826 bool Commuted = false;
4827 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4828 // 1,1,1,1 -> v8i16 though.
4829 V1IsSplat = isSplatVector(V1.getNode());
4830 V2IsSplat = isSplatVector(V2.getNode());
4832 // Canonicalize the splat or undef, if present, to be on the RHS.
4833 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4834 Op = CommuteVectorShuffle(SVOp, DAG);
4835 SVOp = cast<ShuffleVectorSDNode>(Op);
4836 V1 = SVOp->getOperand(0);
4837 V2 = SVOp->getOperand(1);
4838 std::swap(V1IsSplat, V2IsSplat);
4839 std::swap(V1IsUndef, V2IsUndef);
4843 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4844 // Shuffling low element of v1 into undef, just return v1.
4847 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4848 // the instruction selector will not match, so get a canonical MOVL with
4849 // swapped operands to undo the commute.
4850 return getMOVL(DAG, dl, VT, V2, V1);
4853 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4854 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4855 X86::isUNPCKLMask(SVOp) ||
4856 X86::isUNPCKHMask(SVOp))
4860 // Normalize mask so all entries that point to V2 points to its first
4861 // element then try to match unpck{h|l} again. If match, return a
4862 // new vector_shuffle with the corrected mask.
4863 SDValue NewMask = NormalizeMask(SVOp, DAG);
4864 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4865 if (NSVOp != SVOp) {
4866 if (X86::isUNPCKLMask(NSVOp, true)) {
4868 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4875 // Commute is back and try unpck* again.
4876 // FIXME: this seems wrong.
4877 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4878 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4879 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4880 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4881 X86::isUNPCKLMask(NewSVOp) ||
4882 X86::isUNPCKHMask(NewSVOp))
4886 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4888 // Normalize the node to match x86 shuffle ops if needed
4889 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4890 return CommuteVectorShuffle(SVOp, DAG);
4892 // Check for legal shuffle and return?
4893 SmallVector<int, 16> PermMask;
4894 SVOp->getMask(PermMask);
4895 if (isShuffleMaskLegal(PermMask, VT))
4898 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4899 if (VT == MVT::v8i16) {
4900 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4901 if (NewOp.getNode())
4905 if (VT == MVT::v16i8) {
4906 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4907 if (NewOp.getNode())
4911 // Handle all 4 wide cases with a number of shuffles except for MMX.
4912 if (NumElems == 4 && !isMMX)
4913 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4919 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4920 SelectionDAG &DAG) const {
4921 EVT VT = Op.getValueType();
4922 DebugLoc dl = Op.getDebugLoc();
4923 if (VT.getSizeInBits() == 8) {
4924 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4925 Op.getOperand(0), Op.getOperand(1));
4926 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4927 DAG.getValueType(VT));
4928 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4929 } else if (VT.getSizeInBits() == 16) {
4930 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4931 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4933 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4934 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4935 DAG.getNode(ISD::BIT_CONVERT, dl,
4939 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4940 Op.getOperand(0), Op.getOperand(1));
4941 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4942 DAG.getValueType(VT));
4943 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4944 } else if (VT == MVT::f32) {
4945 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4946 // the result back to FR32 register. It's only worth matching if the
4947 // result has a single use which is a store or a bitcast to i32. And in
4948 // the case of a store, it's not worth it if the index is a constant 0,
4949 // because a MOVSSmr can be used instead, which is smaller and faster.
4950 if (!Op.hasOneUse())
4952 SDNode *User = *Op.getNode()->use_begin();
4953 if ((User->getOpcode() != ISD::STORE ||
4954 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4955 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4956 (User->getOpcode() != ISD::BIT_CONVERT ||
4957 User->getValueType(0) != MVT::i32))
4959 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4960 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4963 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4964 } else if (VT == MVT::i32) {
4965 // ExtractPS works with constant index.
4966 if (isa<ConstantSDNode>(Op.getOperand(1)))
4974 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
4975 SelectionDAG &DAG) const {
4976 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4979 if (Subtarget->hasSSE41()) {
4980 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4985 EVT VT = Op.getValueType();
4986 DebugLoc dl = Op.getDebugLoc();
4987 // TODO: handle v16i8.
4988 if (VT.getSizeInBits() == 16) {
4989 SDValue Vec = Op.getOperand(0);
4990 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4992 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4993 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4994 DAG.getNode(ISD::BIT_CONVERT, dl,
4997 // Transform it so it match pextrw which produces a 32-bit result.
4998 EVT EltVT = MVT::i32;
4999 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5000 Op.getOperand(0), Op.getOperand(1));
5001 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5002 DAG.getValueType(VT));
5003 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5004 } else if (VT.getSizeInBits() == 32) {
5005 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5009 // SHUFPS the element to the lowest double word, then movss.
5010 int Mask[4] = { Idx, -1, -1, -1 };
5011 EVT VVT = Op.getOperand(0).getValueType();
5012 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5013 DAG.getUNDEF(VVT), Mask);
5014 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5015 DAG.getIntPtrConstant(0));
5016 } else if (VT.getSizeInBits() == 64) {
5017 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5018 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5019 // to match extract_elt for f64.
5020 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5024 // UNPCKHPD the element to the lowest double word, then movsd.
5025 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5026 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5027 int Mask[2] = { 1, -1 };
5028 EVT VVT = Op.getOperand(0).getValueType();
5029 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5030 DAG.getUNDEF(VVT), Mask);
5031 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5032 DAG.getIntPtrConstant(0));
5039 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5040 SelectionDAG &DAG) const {
5041 EVT VT = Op.getValueType();
5042 EVT EltVT = VT.getVectorElementType();
5043 DebugLoc dl = Op.getDebugLoc();
5045 SDValue N0 = Op.getOperand(0);
5046 SDValue N1 = Op.getOperand(1);
5047 SDValue N2 = Op.getOperand(2);
5049 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5050 isa<ConstantSDNode>(N2)) {
5052 if (VT == MVT::v8i16)
5053 Opc = X86ISD::PINSRW;
5054 else if (VT == MVT::v4i16)
5055 Opc = X86ISD::MMX_PINSRW;
5056 else if (VT == MVT::v16i8)
5057 Opc = X86ISD::PINSRB;
5059 Opc = X86ISD::PINSRB;
5061 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5063 if (N1.getValueType() != MVT::i32)
5064 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5065 if (N2.getValueType() != MVT::i32)
5066 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5067 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5068 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5069 // Bits [7:6] of the constant are the source select. This will always be
5070 // zero here. The DAG Combiner may combine an extract_elt index into these
5071 // bits. For example (insert (extract, 3), 2) could be matched by putting
5072 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5073 // Bits [5:4] of the constant are the destination select. This is the
5074 // value of the incoming immediate.
5075 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5076 // combine either bitwise AND or insert of float 0.0 to set these bits.
5077 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5078 // Create this as a scalar to vector..
5079 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5080 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5081 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5082 // PINSR* works with constant index.
5089 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5090 EVT VT = Op.getValueType();
5091 EVT EltVT = VT.getVectorElementType();
5093 if (Subtarget->hasSSE41())
5094 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5096 if (EltVT == MVT::i8)
5099 DebugLoc dl = Op.getDebugLoc();
5100 SDValue N0 = Op.getOperand(0);
5101 SDValue N1 = Op.getOperand(1);
5102 SDValue N2 = Op.getOperand(2);
5104 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5105 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5106 // as its second argument.
5107 if (N1.getValueType() != MVT::i32)
5108 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5109 if (N2.getValueType() != MVT::i32)
5110 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5111 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5112 dl, VT, N0, N1, N2);
5118 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5119 DebugLoc dl = Op.getDebugLoc();
5121 if (Op.getValueType() == MVT::v1i64 &&
5122 Op.getOperand(0).getValueType() == MVT::i64)
5123 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5125 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5126 EVT VT = MVT::v2i32;
5127 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5134 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5135 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5138 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5139 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5140 // one of the above mentioned nodes. It has to be wrapped because otherwise
5141 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5142 // be used to form addressing mode. These wrapped nodes will be selected
5145 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5146 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5148 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5150 unsigned char OpFlag = 0;
5151 unsigned WrapperKind = X86ISD::Wrapper;
5152 CodeModel::Model M = getTargetMachine().getCodeModel();
5154 if (Subtarget->isPICStyleRIPRel() &&
5155 (M == CodeModel::Small || M == CodeModel::Kernel))
5156 WrapperKind = X86ISD::WrapperRIP;
5157 else if (Subtarget->isPICStyleGOT())
5158 OpFlag = X86II::MO_GOTOFF;
5159 else if (Subtarget->isPICStyleStubPIC())
5160 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5162 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5164 CP->getOffset(), OpFlag);
5165 DebugLoc DL = CP->getDebugLoc();
5166 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5167 // With PIC, the address is actually $g + Offset.
5169 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5170 DAG.getNode(X86ISD::GlobalBaseReg,
5171 DebugLoc(), getPointerTy()),
5178 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5179 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5181 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5183 unsigned char OpFlag = 0;
5184 unsigned WrapperKind = X86ISD::Wrapper;
5185 CodeModel::Model M = getTargetMachine().getCodeModel();
5187 if (Subtarget->isPICStyleRIPRel() &&
5188 (M == CodeModel::Small || M == CodeModel::Kernel))
5189 WrapperKind = X86ISD::WrapperRIP;
5190 else if (Subtarget->isPICStyleGOT())
5191 OpFlag = X86II::MO_GOTOFF;
5192 else if (Subtarget->isPICStyleStubPIC())
5193 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5195 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5197 DebugLoc DL = JT->getDebugLoc();
5198 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5200 // With PIC, the address is actually $g + Offset.
5202 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5203 DAG.getNode(X86ISD::GlobalBaseReg,
5204 DebugLoc(), getPointerTy()),
5212 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5213 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5215 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5217 unsigned char OpFlag = 0;
5218 unsigned WrapperKind = X86ISD::Wrapper;
5219 CodeModel::Model M = getTargetMachine().getCodeModel();
5221 if (Subtarget->isPICStyleRIPRel() &&
5222 (M == CodeModel::Small || M == CodeModel::Kernel))
5223 WrapperKind = X86ISD::WrapperRIP;
5224 else if (Subtarget->isPICStyleGOT())
5225 OpFlag = X86II::MO_GOTOFF;
5226 else if (Subtarget->isPICStyleStubPIC())
5227 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5229 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5231 DebugLoc DL = Op.getDebugLoc();
5232 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5235 // With PIC, the address is actually $g + Offset.
5236 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5237 !Subtarget->is64Bit()) {
5238 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5239 DAG.getNode(X86ISD::GlobalBaseReg,
5240 DebugLoc(), getPointerTy()),
5248 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5249 // Create the TargetBlockAddressAddress node.
5250 unsigned char OpFlags =
5251 Subtarget->ClassifyBlockAddressReference();
5252 CodeModel::Model M = getTargetMachine().getCodeModel();
5253 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5254 DebugLoc dl = Op.getDebugLoc();
5255 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5256 /*isTarget=*/true, OpFlags);
5258 if (Subtarget->isPICStyleRIPRel() &&
5259 (M == CodeModel::Small || M == CodeModel::Kernel))
5260 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5262 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5264 // With PIC, the address is actually $g + Offset.
5265 if (isGlobalRelativeToPICBase(OpFlags)) {
5266 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5267 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5275 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5277 SelectionDAG &DAG) const {
5278 // Create the TargetGlobalAddress node, folding in the constant
5279 // offset if it is legal.
5280 unsigned char OpFlags =
5281 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5282 CodeModel::Model M = getTargetMachine().getCodeModel();
5284 if (OpFlags == X86II::MO_NO_FLAG &&
5285 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5286 // A direct static reference to a global.
5287 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5290 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
5293 if (Subtarget->isPICStyleRIPRel() &&
5294 (M == CodeModel::Small || M == CodeModel::Kernel))
5295 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5297 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5299 // With PIC, the address is actually $g + Offset.
5300 if (isGlobalRelativeToPICBase(OpFlags)) {
5301 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5302 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5306 // For globals that require a load from a stub to get the address, emit the
5308 if (isGlobalStubReference(OpFlags))
5309 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5310 PseudoSourceValue::getGOT(), 0, false, false, 0);
5312 // If there was a non-zero offset that we didn't fold, create an explicit
5315 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5316 DAG.getConstant(Offset, getPointerTy()));
5322 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
5323 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5324 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5325 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5329 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5330 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5331 unsigned char OperandFlags) {
5332 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5333 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5334 DebugLoc dl = GA->getDebugLoc();
5335 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5336 GA->getValueType(0),
5340 SDValue Ops[] = { Chain, TGA, *InFlag };
5341 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5343 SDValue Ops[] = { Chain, TGA };
5344 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5347 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5348 MFI->setAdjustsStack(true);
5350 SDValue Flag = Chain.getValue(1);
5351 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5354 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5356 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5359 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5360 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5361 DAG.getNode(X86ISD::GlobalBaseReg,
5362 DebugLoc(), PtrVT), InFlag);
5363 InFlag = Chain.getValue(1);
5365 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5368 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5370 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5372 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5373 X86::RAX, X86II::MO_TLSGD);
5376 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5377 // "local exec" model.
5378 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5379 const EVT PtrVT, TLSModel::Model model,
5381 DebugLoc dl = GA->getDebugLoc();
5382 // Get the Thread Pointer
5383 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5385 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5388 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5389 NULL, 0, false, false, 0);
5391 unsigned char OperandFlags = 0;
5392 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5394 unsigned WrapperKind = X86ISD::Wrapper;
5395 if (model == TLSModel::LocalExec) {
5396 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5397 } else if (is64Bit) {
5398 assert(model == TLSModel::InitialExec);
5399 OperandFlags = X86II::MO_GOTTPOFF;
5400 WrapperKind = X86ISD::WrapperRIP;
5402 assert(model == TLSModel::InitialExec);
5403 OperandFlags = X86II::MO_INDNTPOFF;
5406 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5408 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5409 GA->getValueType(0),
5410 GA->getOffset(), OperandFlags);
5411 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5413 if (model == TLSModel::InitialExec)
5414 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5415 PseudoSourceValue::getGOT(), 0, false, false, 0);
5417 // The address of the thread local variable is the add of the thread
5418 // pointer with the offset of the variable.
5419 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5423 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
5425 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5426 const GlobalValue *GV = GA->getGlobal();
5428 if (Subtarget->isTargetELF()) {
5429 // TODO: implement the "local dynamic" model
5430 // TODO: implement the "initial exec"model for pic executables
5432 // If GV is an alias then use the aliasee for determining
5433 // thread-localness.
5434 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5435 GV = GA->resolveAliasedGlobal(false);
5437 TLSModel::Model model
5438 = getTLSModel(GV, getTargetMachine().getRelocationModel());
5441 case TLSModel::GeneralDynamic:
5442 case TLSModel::LocalDynamic: // not implemented
5443 if (Subtarget->is64Bit())
5444 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5445 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5447 case TLSModel::InitialExec:
5448 case TLSModel::LocalExec:
5449 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5450 Subtarget->is64Bit());
5452 } else if (Subtarget->isTargetDarwin()) {
5453 // Darwin only has one model of TLS. Lower to that.
5454 unsigned char OpFlag = 0;
5455 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
5456 X86ISD::WrapperRIP : X86ISD::Wrapper;
5458 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5460 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
5461 !Subtarget->is64Bit();
5463 OpFlag = X86II::MO_TLVP_PIC_BASE;
5465 OpFlag = X86II::MO_TLVP;
5466 DebugLoc DL = Op.getDebugLoc();
5467 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
5469 GA->getOffset(), OpFlag);
5470 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5472 // With PIC32, the address is actually $g + Offset.
5474 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5475 DAG.getNode(X86ISD::GlobalBaseReg,
5476 DebugLoc(), getPointerTy()),
5479 // Lowering the machine isd will make sure everything is in the right
5481 SDValue Args[] = { Offset };
5482 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
5484 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
5485 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5486 MFI->setAdjustsStack(true);
5488 // And our return value (tls address) is in the standard call return value
5490 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
5491 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
5495 "TLS not implemented for this target.");
5497 llvm_unreachable("Unreachable");
5502 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5503 /// take a 2 x i32 value to shift plus a shift amount.
5504 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
5505 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5506 EVT VT = Op.getValueType();
5507 unsigned VTBits = VT.getSizeInBits();
5508 DebugLoc dl = Op.getDebugLoc();
5509 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5510 SDValue ShOpLo = Op.getOperand(0);
5511 SDValue ShOpHi = Op.getOperand(1);
5512 SDValue ShAmt = Op.getOperand(2);
5513 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5514 DAG.getConstant(VTBits - 1, MVT::i8))
5515 : DAG.getConstant(0, VT);
5518 if (Op.getOpcode() == ISD::SHL_PARTS) {
5519 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5520 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5522 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5523 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5526 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5527 DAG.getConstant(VTBits, MVT::i8));
5528 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5529 AndNode, DAG.getConstant(0, MVT::i8));
5532 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5533 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5534 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5536 if (Op.getOpcode() == ISD::SHL_PARTS) {
5537 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5538 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5540 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5541 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5544 SDValue Ops[2] = { Lo, Hi };
5545 return DAG.getMergeValues(Ops, 2, dl);
5548 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
5549 SelectionDAG &DAG) const {
5550 EVT SrcVT = Op.getOperand(0).getValueType();
5552 if (SrcVT.isVector()) {
5553 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5559 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5560 "Unknown SINT_TO_FP to lower!");
5562 // These are really Legal; return the operand so the caller accepts it as
5564 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5566 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5567 Subtarget->is64Bit()) {
5571 DebugLoc dl = Op.getDebugLoc();
5572 unsigned Size = SrcVT.getSizeInBits()/8;
5573 MachineFunction &MF = DAG.getMachineFunction();
5574 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5575 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5576 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5578 PseudoSourceValue::getFixedStack(SSFI), 0,
5580 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5583 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5585 SelectionDAG &DAG) const {
5587 DebugLoc dl = Op.getDebugLoc();
5589 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5591 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5593 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5594 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5595 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5596 Tys, Ops, array_lengthof(Ops));
5599 Chain = Result.getValue(1);
5600 SDValue InFlag = Result.getValue(2);
5602 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5603 // shouldn't be necessary except that RFP cannot be live across
5604 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5605 MachineFunction &MF = DAG.getMachineFunction();
5606 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5607 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5608 Tys = DAG.getVTList(MVT::Other);
5610 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5612 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5613 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5614 PseudoSourceValue::getFixedStack(SSFI), 0,
5621 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5622 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
5623 SelectionDAG &DAG) const {
5624 // This algorithm is not obvious. Here it is in C code, more or less:
5626 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5627 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5628 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5630 // Copy ints to xmm registers.
5631 __m128i xh = _mm_cvtsi32_si128( hi );
5632 __m128i xl = _mm_cvtsi32_si128( lo );
5634 // Combine into low half of a single xmm register.
5635 __m128i x = _mm_unpacklo_epi32( xh, xl );
5639 // Merge in appropriate exponents to give the integer bits the right
5641 x = _mm_unpacklo_epi32( x, exp );
5643 // Subtract away the biases to deal with the IEEE-754 double precision
5645 d = _mm_sub_pd( (__m128d) x, bias );
5647 // All conversions up to here are exact. The correctly rounded result is
5648 // calculated using the current rounding mode using the following
5650 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5651 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5652 // store doesn't really need to be here (except
5653 // maybe to zero the other double)
5658 DebugLoc dl = Op.getDebugLoc();
5659 LLVMContext *Context = DAG.getContext();
5661 // Build some magic constants.
5662 std::vector<Constant*> CV0;
5663 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5664 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5665 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5666 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5667 Constant *C0 = ConstantVector::get(CV0);
5668 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5670 std::vector<Constant*> CV1;
5672 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5674 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5675 Constant *C1 = ConstantVector::get(CV1);
5676 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5678 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5679 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5681 DAG.getIntPtrConstant(1)));
5682 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5683 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5685 DAG.getIntPtrConstant(0)));
5686 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5687 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5688 PseudoSourceValue::getConstantPool(), 0,
5690 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5691 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5692 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5693 PseudoSourceValue::getConstantPool(), 0,
5695 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5697 // Add the halves; easiest way is to swap them into another reg first.
5698 int ShufMask[2] = { 1, -1 };
5699 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5700 DAG.getUNDEF(MVT::v2f64), ShufMask);
5701 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5702 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5703 DAG.getIntPtrConstant(0));
5706 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5707 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
5708 SelectionDAG &DAG) const {
5709 DebugLoc dl = Op.getDebugLoc();
5710 // FP constant to bias correct the final result.
5711 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5714 // Load the 32-bit value into an XMM register.
5715 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5716 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5718 DAG.getIntPtrConstant(0)));
5720 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5721 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5722 DAG.getIntPtrConstant(0));
5724 // Or the load with the bias.
5725 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5726 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5727 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5729 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5730 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5731 MVT::v2f64, Bias)));
5732 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5733 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5734 DAG.getIntPtrConstant(0));
5736 // Subtract the bias.
5737 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5739 // Handle final rounding.
5740 EVT DestVT = Op.getValueType();
5742 if (DestVT.bitsLT(MVT::f64)) {
5743 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5744 DAG.getIntPtrConstant(0));
5745 } else if (DestVT.bitsGT(MVT::f64)) {
5746 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5749 // Handle final rounding.
5753 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
5754 SelectionDAG &DAG) const {
5755 SDValue N0 = Op.getOperand(0);
5756 DebugLoc dl = Op.getDebugLoc();
5758 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
5759 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5760 // the optimization here.
5761 if (DAG.SignBitIsZero(N0))
5762 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5764 EVT SrcVT = N0.getValueType();
5765 EVT DstVT = Op.getValueType();
5766 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
5767 return LowerUINT_TO_FP_i64(Op, DAG);
5768 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
5769 return LowerUINT_TO_FP_i32(Op, DAG);
5771 // Make a 64-bit buffer, and use it to build an FILD.
5772 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5773 if (SrcVT == MVT::i32) {
5774 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5775 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5776 getPointerTy(), StackSlot, WordOff);
5777 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5778 StackSlot, NULL, 0, false, false, 0);
5779 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5780 OffsetSlot, NULL, 0, false, false, 0);
5781 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5785 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
5786 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5787 StackSlot, NULL, 0, false, false, 0);
5788 // For i64 source, we need to add the appropriate power of 2 if the input
5789 // was negative. This is the same as the optimization in
5790 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
5791 // we must be careful to do the computation in x87 extended precision, not
5792 // in SSE. (The generic code can't know it's OK to do this, or how to.)
5793 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
5794 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
5795 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
5797 APInt FF(32, 0x5F800000ULL);
5799 // Check whether the sign bit is set.
5800 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
5801 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
5804 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
5805 SDValue FudgePtr = DAG.getConstantPool(
5806 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
5809 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
5810 SDValue Zero = DAG.getIntPtrConstant(0);
5811 SDValue Four = DAG.getIntPtrConstant(4);
5812 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
5814 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
5816 // Load the value out, extending it from f32 to f80.
5817 // FIXME: Avoid the extend by constructing the right constant pool?
5818 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
5819 FudgePtr, PseudoSourceValue::getConstantPool(),
5820 0, MVT::f32, false, false, 4);
5821 // Extend everything to 80 bits to force it to be done on x87.
5822 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
5823 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
5826 std::pair<SDValue,SDValue> X86TargetLowering::
5827 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
5828 DebugLoc dl = Op.getDebugLoc();
5830 EVT DstTy = Op.getValueType();
5833 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5837 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5838 DstTy.getSimpleVT() >= MVT::i16 &&
5839 "Unknown FP_TO_SINT to lower!");
5841 // These are really Legal.
5842 if (DstTy == MVT::i32 &&
5843 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5844 return std::make_pair(SDValue(), SDValue());
5845 if (Subtarget->is64Bit() &&
5846 DstTy == MVT::i64 &&
5847 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5848 return std::make_pair(SDValue(), SDValue());
5850 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5852 MachineFunction &MF = DAG.getMachineFunction();
5853 unsigned MemSize = DstTy.getSizeInBits()/8;
5854 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5855 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5858 switch (DstTy.getSimpleVT().SimpleTy) {
5859 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5860 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5861 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5862 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5865 SDValue Chain = DAG.getEntryNode();
5866 SDValue Value = Op.getOperand(0);
5867 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5868 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5869 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5870 PseudoSourceValue::getFixedStack(SSFI), 0,
5872 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5874 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5876 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5877 Chain = Value.getValue(1);
5878 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5879 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5882 // Build the FP_TO_INT*_IN_MEM
5883 SDValue Ops[] = { Chain, Value, StackSlot };
5884 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5886 return std::make_pair(FIST, StackSlot);
5889 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
5890 SelectionDAG &DAG) const {
5891 if (Op.getValueType().isVector()) {
5892 if (Op.getValueType() == MVT::v2i32 &&
5893 Op.getOperand(0).getValueType() == MVT::v2f64) {
5899 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5900 SDValue FIST = Vals.first, StackSlot = Vals.second;
5901 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5902 if (FIST.getNode() == 0) return Op;
5905 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5906 FIST, StackSlot, NULL, 0, false, false, 0);
5909 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
5910 SelectionDAG &DAG) const {
5911 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5912 SDValue FIST = Vals.first, StackSlot = Vals.second;
5913 assert(FIST.getNode() && "Unexpected failure");
5916 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5917 FIST, StackSlot, NULL, 0, false, false, 0);
5920 SDValue X86TargetLowering::LowerFABS(SDValue Op,
5921 SelectionDAG &DAG) const {
5922 LLVMContext *Context = DAG.getContext();
5923 DebugLoc dl = Op.getDebugLoc();
5924 EVT VT = Op.getValueType();
5927 EltVT = VT.getVectorElementType();
5928 std::vector<Constant*> CV;
5929 if (EltVT == MVT::f64) {
5930 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5934 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5940 Constant *C = ConstantVector::get(CV);
5941 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5942 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5943 PseudoSourceValue::getConstantPool(), 0,
5945 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5948 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
5949 LLVMContext *Context = DAG.getContext();
5950 DebugLoc dl = Op.getDebugLoc();
5951 EVT VT = Op.getValueType();
5954 EltVT = VT.getVectorElementType();
5955 std::vector<Constant*> CV;
5956 if (EltVT == MVT::f64) {
5957 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5961 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5967 Constant *C = ConstantVector::get(CV);
5968 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5969 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5970 PseudoSourceValue::getConstantPool(), 0,
5972 if (VT.isVector()) {
5973 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5974 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5975 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5977 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5979 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5983 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5984 LLVMContext *Context = DAG.getContext();
5985 SDValue Op0 = Op.getOperand(0);
5986 SDValue Op1 = Op.getOperand(1);
5987 DebugLoc dl = Op.getDebugLoc();
5988 EVT VT = Op.getValueType();
5989 EVT SrcVT = Op1.getValueType();
5991 // If second operand is smaller, extend it first.
5992 if (SrcVT.bitsLT(VT)) {
5993 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5996 // And if it is bigger, shrink it first.
5997 if (SrcVT.bitsGT(VT)) {
5998 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6002 // At this point the operands and the result should have the same
6003 // type, and that won't be f80 since that is not custom lowered.
6005 // First get the sign bit of second operand.
6006 std::vector<Constant*> CV;
6007 if (SrcVT == MVT::f64) {
6008 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6009 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6011 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6012 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6013 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6014 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6016 Constant *C = ConstantVector::get(CV);
6017 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6018 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6019 PseudoSourceValue::getConstantPool(), 0,
6021 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6023 // Shift sign bit right or left if the two operands have different types.
6024 if (SrcVT.bitsGT(VT)) {
6025 // Op0 is MVT::f32, Op1 is MVT::f64.
6026 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6027 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6028 DAG.getConstant(32, MVT::i32));
6029 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
6030 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6031 DAG.getIntPtrConstant(0));
6034 // Clear first operand sign bit.
6036 if (VT == MVT::f64) {
6037 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6038 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6040 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6041 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6042 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6043 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6045 C = ConstantVector::get(CV);
6046 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6047 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6048 PseudoSourceValue::getConstantPool(), 0,
6050 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6052 // Or the value with the sign bit.
6053 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6056 /// Emit nodes that will be selected as "test Op0,Op0", or something
6058 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6059 SelectionDAG &DAG) const {
6060 DebugLoc dl = Op.getDebugLoc();
6062 // CF and OF aren't always set the way we want. Determine which
6063 // of these we need.
6064 bool NeedCF = false;
6065 bool NeedOF = false;
6068 case X86::COND_A: case X86::COND_AE:
6069 case X86::COND_B: case X86::COND_BE:
6072 case X86::COND_G: case X86::COND_GE:
6073 case X86::COND_L: case X86::COND_LE:
6074 case X86::COND_O: case X86::COND_NO:
6079 // See if we can use the EFLAGS value from the operand instead of
6080 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6081 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6082 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6083 // Emit a CMP with 0, which is the TEST pattern.
6084 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6085 DAG.getConstant(0, Op.getValueType()));
6087 unsigned Opcode = 0;
6088 unsigned NumOperands = 0;
6089 switch (Op.getNode()->getOpcode()) {
6091 // Due to an isel shortcoming, be conservative if this add is likely to be
6092 // selected as part of a load-modify-store instruction. When the root node
6093 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6094 // uses of other nodes in the match, such as the ADD in this case. This
6095 // leads to the ADD being left around and reselected, with the result being
6096 // two adds in the output. Alas, even if none our users are stores, that
6097 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6098 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6099 // climbing the DAG back to the root, and it doesn't seem to be worth the
6101 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6102 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6103 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6106 if (ConstantSDNode *C =
6107 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6108 // An add of one will be selected as an INC.
6109 if (C->getAPIntValue() == 1) {
6110 Opcode = X86ISD::INC;
6115 // An add of negative one (subtract of one) will be selected as a DEC.
6116 if (C->getAPIntValue().isAllOnesValue()) {
6117 Opcode = X86ISD::DEC;
6123 // Otherwise use a regular EFLAGS-setting add.
6124 Opcode = X86ISD::ADD;
6128 // If the primary and result isn't used, don't bother using X86ISD::AND,
6129 // because a TEST instruction will be better.
6130 bool NonFlagUse = false;
6131 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6132 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6134 unsigned UOpNo = UI.getOperandNo();
6135 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6136 // Look pass truncate.
6137 UOpNo = User->use_begin().getOperandNo();
6138 User = *User->use_begin();
6141 if (User->getOpcode() != ISD::BRCOND &&
6142 User->getOpcode() != ISD::SETCC &&
6143 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6156 // Due to the ISEL shortcoming noted above, be conservative if this op is
6157 // likely to be selected as part of a load-modify-store instruction.
6158 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6159 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6160 if (UI->getOpcode() == ISD::STORE)
6163 // Otherwise use a regular EFLAGS-setting instruction.
6164 switch (Op.getNode()->getOpcode()) {
6165 default: llvm_unreachable("unexpected operator!");
6166 case ISD::SUB: Opcode = X86ISD::SUB; break;
6167 case ISD::OR: Opcode = X86ISD::OR; break;
6168 case ISD::XOR: Opcode = X86ISD::XOR; break;
6169 case ISD::AND: Opcode = X86ISD::AND; break;
6181 return SDValue(Op.getNode(), 1);
6188 // Emit a CMP with 0, which is the TEST pattern.
6189 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6190 DAG.getConstant(0, Op.getValueType()));
6192 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6193 SmallVector<SDValue, 4> Ops;
6194 for (unsigned i = 0; i != NumOperands; ++i)
6195 Ops.push_back(Op.getOperand(i));
6197 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6198 DAG.ReplaceAllUsesWith(Op, New);
6199 return SDValue(New.getNode(), 1);
6202 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6204 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6205 SelectionDAG &DAG) const {
6206 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6207 if (C->getAPIntValue() == 0)
6208 return EmitTest(Op0, X86CC, DAG);
6210 DebugLoc dl = Op0.getDebugLoc();
6211 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6214 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6215 /// if it's possible.
6216 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6217 DebugLoc dl, SelectionDAG &DAG) const {
6218 SDValue Op0 = And.getOperand(0);
6219 SDValue Op1 = And.getOperand(1);
6220 if (Op0.getOpcode() == ISD::TRUNCATE)
6221 Op0 = Op0.getOperand(0);
6222 if (Op1.getOpcode() == ISD::TRUNCATE)
6223 Op1 = Op1.getOperand(0);
6226 if (Op1.getOpcode() == ISD::SHL)
6227 std::swap(Op0, Op1);
6228 if (Op0.getOpcode() == ISD::SHL) {
6229 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6230 if (And00C->getZExtValue() == 1) {
6231 // If we looked past a truncate, check that it's only truncating away
6233 unsigned BitWidth = Op0.getValueSizeInBits();
6234 unsigned AndBitWidth = And.getValueSizeInBits();
6235 if (BitWidth > AndBitWidth) {
6236 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6237 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6238 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6242 RHS = Op0.getOperand(1);
6244 } else if (Op1.getOpcode() == ISD::Constant) {
6245 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6246 SDValue AndLHS = Op0;
6247 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6248 LHS = AndLHS.getOperand(0);
6249 RHS = AndLHS.getOperand(1);
6253 if (LHS.getNode()) {
6254 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6255 // instruction. Since the shift amount is in-range-or-undefined, we know
6256 // that doing a bittest on the i32 value is ok. We extend to i32 because
6257 // the encoding for the i16 version is larger than the i32 version.
6258 // Also promote i16 to i32 for performance / code size reason.
6259 if (LHS.getValueType() == MVT::i8 ||
6260 LHS.getValueType() == MVT::i16)
6261 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6263 // If the operand types disagree, extend the shift amount to match. Since
6264 // BT ignores high bits (like shifts) we can use anyextend.
6265 if (LHS.getValueType() != RHS.getValueType())
6266 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6268 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6269 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6270 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6271 DAG.getConstant(Cond, MVT::i8), BT);
6277 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6278 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6279 SDValue Op0 = Op.getOperand(0);
6280 SDValue Op1 = Op.getOperand(1);
6281 DebugLoc dl = Op.getDebugLoc();
6282 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6284 // Optimize to BT if possible.
6285 // Lower (X & (1 << N)) == 0 to BT(X, N).
6286 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
6287 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
6288 if (Op0.getOpcode() == ISD::AND &&
6290 Op1.getOpcode() == ISD::Constant &&
6291 cast<ConstantSDNode>(Op1)->isNullValue() &&
6292 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6293 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
6294 if (NewSetCC.getNode())
6298 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
6299 if (Op0.getOpcode() == X86ISD::SETCC &&
6300 Op1.getOpcode() == ISD::Constant &&
6301 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
6302 cast<ConstantSDNode>(Op1)->isNullValue()) &&
6303 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6304 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
6305 bool Invert = (CC == ISD::SETNE) ^
6306 cast<ConstantSDNode>(Op1)->isNullValue();
6308 CCode = X86::GetOppositeBranchCondition(CCode);
6309 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6310 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
6313 bool isFP = Op1.getValueType().isFloatingPoint();
6314 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
6315 if (X86CC == X86::COND_INVALID)
6318 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
6320 // Use sbb x, x to materialize carry bit into a GPR.
6321 if (X86CC == X86::COND_B)
6322 return DAG.getNode(ISD::AND, dl, MVT::i8,
6323 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6324 DAG.getConstant(X86CC, MVT::i8), Cond),
6325 DAG.getConstant(1, MVT::i8));
6327 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6328 DAG.getConstant(X86CC, MVT::i8), Cond);
6331 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
6333 SDValue Op0 = Op.getOperand(0);
6334 SDValue Op1 = Op.getOperand(1);
6335 SDValue CC = Op.getOperand(2);
6336 EVT VT = Op.getValueType();
6337 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6338 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6339 DebugLoc dl = Op.getDebugLoc();
6343 EVT VT0 = Op0.getValueType();
6344 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6345 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6348 switch (SetCCOpcode) {
6351 case ISD::SETEQ: SSECC = 0; break;
6353 case ISD::SETGT: Swap = true; // Fallthrough
6355 case ISD::SETOLT: SSECC = 1; break;
6357 case ISD::SETGE: Swap = true; // Fallthrough
6359 case ISD::SETOLE: SSECC = 2; break;
6360 case ISD::SETUO: SSECC = 3; break;
6362 case ISD::SETNE: SSECC = 4; break;
6363 case ISD::SETULE: Swap = true;
6364 case ISD::SETUGE: SSECC = 5; break;
6365 case ISD::SETULT: Swap = true;
6366 case ISD::SETUGT: SSECC = 6; break;
6367 case ISD::SETO: SSECC = 7; break;
6370 std::swap(Op0, Op1);
6372 // In the two special cases we can't handle, emit two comparisons.
6374 if (SetCCOpcode == ISD::SETUEQ) {
6376 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6377 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6378 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6380 else if (SetCCOpcode == ISD::SETONE) {
6382 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6383 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6384 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6386 llvm_unreachable("Illegal FP comparison");
6388 // Handle all other FP comparisons here.
6389 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6392 // We are handling one of the integer comparisons here. Since SSE only has
6393 // GT and EQ comparisons for integer, swapping operands and multiple
6394 // operations may be required for some comparisons.
6395 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6396 bool Swap = false, Invert = false, FlipSigns = false;
6398 switch (VT.getSimpleVT().SimpleTy) {
6401 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6403 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6405 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6406 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6409 switch (SetCCOpcode) {
6411 case ISD::SETNE: Invert = true;
6412 case ISD::SETEQ: Opc = EQOpc; break;
6413 case ISD::SETLT: Swap = true;
6414 case ISD::SETGT: Opc = GTOpc; break;
6415 case ISD::SETGE: Swap = true;
6416 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6417 case ISD::SETULT: Swap = true;
6418 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6419 case ISD::SETUGE: Swap = true;
6420 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6423 std::swap(Op0, Op1);
6425 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6426 // bits of the inputs before performing those operations.
6428 EVT EltVT = VT.getVectorElementType();
6429 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6431 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6432 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6434 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6435 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6438 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6440 // If the logical-not of the result is required, perform that now.
6442 Result = DAG.getNOT(dl, Result, VT);
6447 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6448 static bool isX86LogicalCmp(SDValue Op) {
6449 unsigned Opc = Op.getNode()->getOpcode();
6450 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6452 if (Op.getResNo() == 1 &&
6453 (Opc == X86ISD::ADD ||
6454 Opc == X86ISD::SUB ||
6455 Opc == X86ISD::SMUL ||
6456 Opc == X86ISD::UMUL ||
6457 Opc == X86ISD::INC ||
6458 Opc == X86ISD::DEC ||
6459 Opc == X86ISD::OR ||
6460 Opc == X86ISD::XOR ||
6461 Opc == X86ISD::AND))
6467 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
6468 bool addTest = true;
6469 SDValue Cond = Op.getOperand(0);
6470 DebugLoc dl = Op.getDebugLoc();
6473 if (Cond.getOpcode() == ISD::SETCC) {
6474 SDValue NewCond = LowerSETCC(Cond, DAG);
6475 if (NewCond.getNode())
6479 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6480 SDValue Op1 = Op.getOperand(1);
6481 SDValue Op2 = Op.getOperand(2);
6482 if (Cond.getOpcode() == X86ISD::SETCC &&
6483 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6484 SDValue Cmp = Cond.getOperand(1);
6485 if (Cmp.getOpcode() == X86ISD::CMP) {
6486 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6487 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6488 ConstantSDNode *RHSC =
6489 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6490 if (N1C && N1C->isAllOnesValue() &&
6491 N2C && N2C->isNullValue() &&
6492 RHSC && RHSC->isNullValue()) {
6493 SDValue CmpOp0 = Cmp.getOperand(0);
6494 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6495 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6496 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6497 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6502 // Look pass (and (setcc_carry (cmp ...)), 1).
6503 if (Cond.getOpcode() == ISD::AND &&
6504 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6505 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6506 if (C && C->getAPIntValue() == 1)
6507 Cond = Cond.getOperand(0);
6510 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6511 // setting operand in place of the X86ISD::SETCC.
6512 if (Cond.getOpcode() == X86ISD::SETCC ||
6513 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6514 CC = Cond.getOperand(0);
6516 SDValue Cmp = Cond.getOperand(1);
6517 unsigned Opc = Cmp.getOpcode();
6518 EVT VT = Op.getValueType();
6520 bool IllegalFPCMov = false;
6521 if (VT.isFloatingPoint() && !VT.isVector() &&
6522 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6523 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6525 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6526 Opc == X86ISD::BT) { // FIXME
6533 // Look pass the truncate.
6534 if (Cond.getOpcode() == ISD::TRUNCATE)
6535 Cond = Cond.getOperand(0);
6537 // We know the result of AND is compared against zero. Try to match
6539 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6540 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6541 if (NewSetCC.getNode()) {
6542 CC = NewSetCC.getOperand(0);
6543 Cond = NewSetCC.getOperand(1);
6550 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6551 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6554 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6555 // condition is true.
6556 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6557 SDValue Ops[] = { Op2, Op1, CC, Cond };
6558 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6561 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6562 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6563 // from the AND / OR.
6564 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6565 Opc = Op.getOpcode();
6566 if (Opc != ISD::OR && Opc != ISD::AND)
6568 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6569 Op.getOperand(0).hasOneUse() &&
6570 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6571 Op.getOperand(1).hasOneUse());
6574 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6575 // 1 and that the SETCC node has a single use.
6576 static bool isXor1OfSetCC(SDValue Op) {
6577 if (Op.getOpcode() != ISD::XOR)
6579 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6580 if (N1C && N1C->getAPIntValue() == 1) {
6581 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6582 Op.getOperand(0).hasOneUse();
6587 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
6588 bool addTest = true;
6589 SDValue Chain = Op.getOperand(0);
6590 SDValue Cond = Op.getOperand(1);
6591 SDValue Dest = Op.getOperand(2);
6592 DebugLoc dl = Op.getDebugLoc();
6595 if (Cond.getOpcode() == ISD::SETCC) {
6596 SDValue NewCond = LowerSETCC(Cond, DAG);
6597 if (NewCond.getNode())
6601 // FIXME: LowerXALUO doesn't handle these!!
6602 else if (Cond.getOpcode() == X86ISD::ADD ||
6603 Cond.getOpcode() == X86ISD::SUB ||
6604 Cond.getOpcode() == X86ISD::SMUL ||
6605 Cond.getOpcode() == X86ISD::UMUL)
6606 Cond = LowerXALUO(Cond, DAG);
6609 // Look pass (and (setcc_carry (cmp ...)), 1).
6610 if (Cond.getOpcode() == ISD::AND &&
6611 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6612 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6613 if (C && C->getAPIntValue() == 1)
6614 Cond = Cond.getOperand(0);
6617 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6618 // setting operand in place of the X86ISD::SETCC.
6619 if (Cond.getOpcode() == X86ISD::SETCC ||
6620 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6621 CC = Cond.getOperand(0);
6623 SDValue Cmp = Cond.getOperand(1);
6624 unsigned Opc = Cmp.getOpcode();
6625 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6626 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6630 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6634 // These can only come from an arithmetic instruction with overflow,
6635 // e.g. SADDO, UADDO.
6636 Cond = Cond.getNode()->getOperand(1);
6643 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6644 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6645 if (CondOpc == ISD::OR) {
6646 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6647 // two branches instead of an explicit OR instruction with a
6649 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6650 isX86LogicalCmp(Cmp)) {
6651 CC = Cond.getOperand(0).getOperand(0);
6652 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6653 Chain, Dest, CC, Cmp);
6654 CC = Cond.getOperand(1).getOperand(0);
6658 } else { // ISD::AND
6659 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6660 // two branches instead of an explicit AND instruction with a
6661 // separate test. However, we only do this if this block doesn't
6662 // have a fall-through edge, because this requires an explicit
6663 // jmp when the condition is false.
6664 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6665 isX86LogicalCmp(Cmp) &&
6666 Op.getNode()->hasOneUse()) {
6667 X86::CondCode CCode =
6668 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6669 CCode = X86::GetOppositeBranchCondition(CCode);
6670 CC = DAG.getConstant(CCode, MVT::i8);
6671 SDNode *User = *Op.getNode()->use_begin();
6672 // Look for an unconditional branch following this conditional branch.
6673 // We need this because we need to reverse the successors in order
6674 // to implement FCMP_OEQ.
6675 if (User->getOpcode() == ISD::BR) {
6676 SDValue FalseBB = User->getOperand(1);
6678 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
6679 assert(NewBR == User);
6683 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6684 Chain, Dest, CC, Cmp);
6685 X86::CondCode CCode =
6686 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6687 CCode = X86::GetOppositeBranchCondition(CCode);
6688 CC = DAG.getConstant(CCode, MVT::i8);
6694 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6695 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6696 // It should be transformed during dag combiner except when the condition
6697 // is set by a arithmetics with overflow node.
6698 X86::CondCode CCode =
6699 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6700 CCode = X86::GetOppositeBranchCondition(CCode);
6701 CC = DAG.getConstant(CCode, MVT::i8);
6702 Cond = Cond.getOperand(0).getOperand(1);
6708 // Look pass the truncate.
6709 if (Cond.getOpcode() == ISD::TRUNCATE)
6710 Cond = Cond.getOperand(0);
6712 // We know the result of AND is compared against zero. Try to match
6714 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6715 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6716 if (NewSetCC.getNode()) {
6717 CC = NewSetCC.getOperand(0);
6718 Cond = NewSetCC.getOperand(1);
6725 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6726 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6728 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6729 Chain, Dest, CC, Cond);
6733 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6734 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6735 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6736 // that the guard pages used by the OS virtual memory manager are allocated in
6737 // correct sequence.
6739 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6740 SelectionDAG &DAG) const {
6741 assert(Subtarget->isTargetCygMing() &&
6742 "This should be used only on Cygwin/Mingw targets");
6743 DebugLoc dl = Op.getDebugLoc();
6746 SDValue Chain = Op.getOperand(0);
6747 SDValue Size = Op.getOperand(1);
6748 // FIXME: Ensure alignment here
6752 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6754 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6755 Flag = Chain.getValue(1);
6757 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6759 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6760 Flag = Chain.getValue(1);
6762 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6764 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6765 return DAG.getMergeValues(Ops1, 2, dl);
6768 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
6769 MachineFunction &MF = DAG.getMachineFunction();
6770 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
6772 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6773 DebugLoc dl = Op.getDebugLoc();
6775 if (!Subtarget->is64Bit()) {
6776 // vastart just stores the address of the VarArgsFrameIndex slot into the
6777 // memory location argument.
6778 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6780 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6785 // gp_offset (0 - 6 * 8)
6786 // fp_offset (48 - 48 + 8 * 16)
6787 // overflow_arg_area (point to parameters coming in memory).
6789 SmallVector<SDValue, 8> MemOps;
6790 SDValue FIN = Op.getOperand(1);
6792 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6793 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
6795 FIN, SV, 0, false, false, 0);
6796 MemOps.push_back(Store);
6799 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6800 FIN, DAG.getIntPtrConstant(4));
6801 Store = DAG.getStore(Op.getOperand(0), dl,
6802 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
6804 FIN, SV, 4, false, false, 0);
6805 MemOps.push_back(Store);
6807 // Store ptr to overflow_arg_area
6808 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6809 FIN, DAG.getIntPtrConstant(4));
6810 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6812 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8,
6814 MemOps.push_back(Store);
6816 // Store ptr to reg_save_area.
6817 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6818 FIN, DAG.getIntPtrConstant(8));
6819 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
6821 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16,
6823 MemOps.push_back(Store);
6824 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6825 &MemOps[0], MemOps.size());
6828 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
6829 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6830 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6832 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
6836 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
6837 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6838 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6839 SDValue Chain = Op.getOperand(0);
6840 SDValue DstPtr = Op.getOperand(1);
6841 SDValue SrcPtr = Op.getOperand(2);
6842 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6843 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6844 DebugLoc dl = Op.getDebugLoc();
6846 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6847 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
6848 false, DstSV, 0, SrcSV, 0);
6852 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
6853 DebugLoc dl = Op.getDebugLoc();
6854 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6856 default: return SDValue(); // Don't custom lower most intrinsics.
6857 // Comparison intrinsics.
6858 case Intrinsic::x86_sse_comieq_ss:
6859 case Intrinsic::x86_sse_comilt_ss:
6860 case Intrinsic::x86_sse_comile_ss:
6861 case Intrinsic::x86_sse_comigt_ss:
6862 case Intrinsic::x86_sse_comige_ss:
6863 case Intrinsic::x86_sse_comineq_ss:
6864 case Intrinsic::x86_sse_ucomieq_ss:
6865 case Intrinsic::x86_sse_ucomilt_ss:
6866 case Intrinsic::x86_sse_ucomile_ss:
6867 case Intrinsic::x86_sse_ucomigt_ss:
6868 case Intrinsic::x86_sse_ucomige_ss:
6869 case Intrinsic::x86_sse_ucomineq_ss:
6870 case Intrinsic::x86_sse2_comieq_sd:
6871 case Intrinsic::x86_sse2_comilt_sd:
6872 case Intrinsic::x86_sse2_comile_sd:
6873 case Intrinsic::x86_sse2_comigt_sd:
6874 case Intrinsic::x86_sse2_comige_sd:
6875 case Intrinsic::x86_sse2_comineq_sd:
6876 case Intrinsic::x86_sse2_ucomieq_sd:
6877 case Intrinsic::x86_sse2_ucomilt_sd:
6878 case Intrinsic::x86_sse2_ucomile_sd:
6879 case Intrinsic::x86_sse2_ucomigt_sd:
6880 case Intrinsic::x86_sse2_ucomige_sd:
6881 case Intrinsic::x86_sse2_ucomineq_sd: {
6883 ISD::CondCode CC = ISD::SETCC_INVALID;
6886 case Intrinsic::x86_sse_comieq_ss:
6887 case Intrinsic::x86_sse2_comieq_sd:
6891 case Intrinsic::x86_sse_comilt_ss:
6892 case Intrinsic::x86_sse2_comilt_sd:
6896 case Intrinsic::x86_sse_comile_ss:
6897 case Intrinsic::x86_sse2_comile_sd:
6901 case Intrinsic::x86_sse_comigt_ss:
6902 case Intrinsic::x86_sse2_comigt_sd:
6906 case Intrinsic::x86_sse_comige_ss:
6907 case Intrinsic::x86_sse2_comige_sd:
6911 case Intrinsic::x86_sse_comineq_ss:
6912 case Intrinsic::x86_sse2_comineq_sd:
6916 case Intrinsic::x86_sse_ucomieq_ss:
6917 case Intrinsic::x86_sse2_ucomieq_sd:
6918 Opc = X86ISD::UCOMI;
6921 case Intrinsic::x86_sse_ucomilt_ss:
6922 case Intrinsic::x86_sse2_ucomilt_sd:
6923 Opc = X86ISD::UCOMI;
6926 case Intrinsic::x86_sse_ucomile_ss:
6927 case Intrinsic::x86_sse2_ucomile_sd:
6928 Opc = X86ISD::UCOMI;
6931 case Intrinsic::x86_sse_ucomigt_ss:
6932 case Intrinsic::x86_sse2_ucomigt_sd:
6933 Opc = X86ISD::UCOMI;
6936 case Intrinsic::x86_sse_ucomige_ss:
6937 case Intrinsic::x86_sse2_ucomige_sd:
6938 Opc = X86ISD::UCOMI;
6941 case Intrinsic::x86_sse_ucomineq_ss:
6942 case Intrinsic::x86_sse2_ucomineq_sd:
6943 Opc = X86ISD::UCOMI;
6948 SDValue LHS = Op.getOperand(1);
6949 SDValue RHS = Op.getOperand(2);
6950 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6951 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6952 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6953 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6954 DAG.getConstant(X86CC, MVT::i8), Cond);
6955 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6957 // ptest intrinsics. The intrinsic these come from are designed to return
6958 // an integer value, not just an instruction so lower it to the ptest
6959 // pattern and a setcc for the result.
6960 case Intrinsic::x86_sse41_ptestz:
6961 case Intrinsic::x86_sse41_ptestc:
6962 case Intrinsic::x86_sse41_ptestnzc:{
6965 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6966 case Intrinsic::x86_sse41_ptestz:
6968 X86CC = X86::COND_E;
6970 case Intrinsic::x86_sse41_ptestc:
6972 X86CC = X86::COND_B;
6974 case Intrinsic::x86_sse41_ptestnzc:
6976 X86CC = X86::COND_A;
6980 SDValue LHS = Op.getOperand(1);
6981 SDValue RHS = Op.getOperand(2);
6982 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6983 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6984 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6985 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6988 // Fix vector shift instructions where the last operand is a non-immediate
6990 case Intrinsic::x86_sse2_pslli_w:
6991 case Intrinsic::x86_sse2_pslli_d:
6992 case Intrinsic::x86_sse2_pslli_q:
6993 case Intrinsic::x86_sse2_psrli_w:
6994 case Intrinsic::x86_sse2_psrli_d:
6995 case Intrinsic::x86_sse2_psrli_q:
6996 case Intrinsic::x86_sse2_psrai_w:
6997 case Intrinsic::x86_sse2_psrai_d:
6998 case Intrinsic::x86_mmx_pslli_w:
6999 case Intrinsic::x86_mmx_pslli_d:
7000 case Intrinsic::x86_mmx_pslli_q:
7001 case Intrinsic::x86_mmx_psrli_w:
7002 case Intrinsic::x86_mmx_psrli_d:
7003 case Intrinsic::x86_mmx_psrli_q:
7004 case Intrinsic::x86_mmx_psrai_w:
7005 case Intrinsic::x86_mmx_psrai_d: {
7006 SDValue ShAmt = Op.getOperand(2);
7007 if (isa<ConstantSDNode>(ShAmt))
7010 unsigned NewIntNo = 0;
7011 EVT ShAmtVT = MVT::v4i32;
7013 case Intrinsic::x86_sse2_pslli_w:
7014 NewIntNo = Intrinsic::x86_sse2_psll_w;
7016 case Intrinsic::x86_sse2_pslli_d:
7017 NewIntNo = Intrinsic::x86_sse2_psll_d;
7019 case Intrinsic::x86_sse2_pslli_q:
7020 NewIntNo = Intrinsic::x86_sse2_psll_q;
7022 case Intrinsic::x86_sse2_psrli_w:
7023 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7025 case Intrinsic::x86_sse2_psrli_d:
7026 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7028 case Intrinsic::x86_sse2_psrli_q:
7029 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7031 case Intrinsic::x86_sse2_psrai_w:
7032 NewIntNo = Intrinsic::x86_sse2_psra_w;
7034 case Intrinsic::x86_sse2_psrai_d:
7035 NewIntNo = Intrinsic::x86_sse2_psra_d;
7038 ShAmtVT = MVT::v2i32;
7040 case Intrinsic::x86_mmx_pslli_w:
7041 NewIntNo = Intrinsic::x86_mmx_psll_w;
7043 case Intrinsic::x86_mmx_pslli_d:
7044 NewIntNo = Intrinsic::x86_mmx_psll_d;
7046 case Intrinsic::x86_mmx_pslli_q:
7047 NewIntNo = Intrinsic::x86_mmx_psll_q;
7049 case Intrinsic::x86_mmx_psrli_w:
7050 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7052 case Intrinsic::x86_mmx_psrli_d:
7053 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7055 case Intrinsic::x86_mmx_psrli_q:
7056 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7058 case Intrinsic::x86_mmx_psrai_w:
7059 NewIntNo = Intrinsic::x86_mmx_psra_w;
7061 case Intrinsic::x86_mmx_psrai_d:
7062 NewIntNo = Intrinsic::x86_mmx_psra_d;
7064 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7070 // The vector shift intrinsics with scalars uses 32b shift amounts but
7071 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7075 ShOps[1] = DAG.getConstant(0, MVT::i32);
7076 if (ShAmtVT == MVT::v4i32) {
7077 ShOps[2] = DAG.getUNDEF(MVT::i32);
7078 ShOps[3] = DAG.getUNDEF(MVT::i32);
7079 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7081 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7084 EVT VT = Op.getValueType();
7085 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7086 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7087 DAG.getConstant(NewIntNo, MVT::i32),
7088 Op.getOperand(1), ShAmt);
7093 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7094 SelectionDAG &DAG) const {
7095 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7096 MFI->setReturnAddressIsTaken(true);
7098 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7099 DebugLoc dl = Op.getDebugLoc();
7102 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7104 DAG.getConstant(TD->getPointerSize(),
7105 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7106 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7107 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7109 NULL, 0, false, false, 0);
7112 // Just load the return address.
7113 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7114 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7115 RetAddrFI, NULL, 0, false, false, 0);
7118 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7119 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7120 MFI->setFrameAddressIsTaken(true);
7122 EVT VT = Op.getValueType();
7123 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7124 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7125 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7126 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7128 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7133 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7134 SelectionDAG &DAG) const {
7135 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7138 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7139 MachineFunction &MF = DAG.getMachineFunction();
7140 SDValue Chain = Op.getOperand(0);
7141 SDValue Offset = Op.getOperand(1);
7142 SDValue Handler = Op.getOperand(2);
7143 DebugLoc dl = Op.getDebugLoc();
7145 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7147 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7149 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7150 DAG.getIntPtrConstant(-TD->getPointerSize()));
7151 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7152 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7153 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7154 MF.getRegInfo().addLiveOut(StoreAddrReg);
7156 return DAG.getNode(X86ISD::EH_RETURN, dl,
7158 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7161 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7162 SelectionDAG &DAG) const {
7163 SDValue Root = Op.getOperand(0);
7164 SDValue Trmp = Op.getOperand(1); // trampoline
7165 SDValue FPtr = Op.getOperand(2); // nested function
7166 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7167 DebugLoc dl = Op.getDebugLoc();
7169 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7171 if (Subtarget->is64Bit()) {
7172 SDValue OutChains[6];
7174 // Large code-model.
7175 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7176 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7178 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7179 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7181 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7183 // Load the pointer to the nested function into R11.
7184 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7185 SDValue Addr = Trmp;
7186 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7187 Addr, TrmpAddr, 0, false, false, 0);
7189 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7190 DAG.getConstant(2, MVT::i64));
7191 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7194 // Load the 'nest' parameter value into R10.
7195 // R10 is specified in X86CallingConv.td
7196 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7197 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7198 DAG.getConstant(10, MVT::i64));
7199 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7200 Addr, TrmpAddr, 10, false, false, 0);
7202 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7203 DAG.getConstant(12, MVT::i64));
7204 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7207 // Jump to the nested function.
7208 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7209 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7210 DAG.getConstant(20, MVT::i64));
7211 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7212 Addr, TrmpAddr, 20, false, false, 0);
7214 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7215 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7216 DAG.getConstant(22, MVT::i64));
7217 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7218 TrmpAddr, 22, false, false, 0);
7221 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7222 return DAG.getMergeValues(Ops, 2, dl);
7224 const Function *Func =
7225 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7226 CallingConv::ID CC = Func->getCallingConv();
7231 llvm_unreachable("Unsupported calling convention");
7232 case CallingConv::C:
7233 case CallingConv::X86_StdCall: {
7234 // Pass 'nest' parameter in ECX.
7235 // Must be kept in sync with X86CallingConv.td
7238 // Check that ECX wasn't needed by an 'inreg' parameter.
7239 const FunctionType *FTy = Func->getFunctionType();
7240 const AttrListPtr &Attrs = Func->getAttributes();
7242 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7243 unsigned InRegCount = 0;
7246 for (FunctionType::param_iterator I = FTy->param_begin(),
7247 E = FTy->param_end(); I != E; ++I, ++Idx)
7248 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7249 // FIXME: should only count parameters that are lowered to integers.
7250 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7252 if (InRegCount > 2) {
7253 report_fatal_error("Nest register in use - reduce number of inreg"
7259 case CallingConv::X86_FastCall:
7260 case CallingConv::X86_ThisCall:
7261 case CallingConv::Fast:
7262 // Pass 'nest' parameter in EAX.
7263 // Must be kept in sync with X86CallingConv.td
7268 SDValue OutChains[4];
7271 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7272 DAG.getConstant(10, MVT::i32));
7273 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7275 // This is storing the opcode for MOV32ri.
7276 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7277 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7278 OutChains[0] = DAG.getStore(Root, dl,
7279 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7280 Trmp, TrmpAddr, 0, false, false, 0);
7282 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7283 DAG.getConstant(1, MVT::i32));
7284 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7287 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7288 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7289 DAG.getConstant(5, MVT::i32));
7290 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7291 TrmpAddr, 5, false, false, 1);
7293 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7294 DAG.getConstant(6, MVT::i32));
7295 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7299 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7300 return DAG.getMergeValues(Ops, 2, dl);
7304 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7305 SelectionDAG &DAG) const {
7307 The rounding mode is in bits 11:10 of FPSR, and has the following
7314 FLT_ROUNDS, on the other hand, expects the following:
7321 To perform the conversion, we do:
7322 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7325 MachineFunction &MF = DAG.getMachineFunction();
7326 const TargetMachine &TM = MF.getTarget();
7327 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7328 unsigned StackAlignment = TFI.getStackAlignment();
7329 EVT VT = Op.getValueType();
7330 DebugLoc dl = Op.getDebugLoc();
7332 // Save FP Control Word to stack slot
7333 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7334 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7336 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7337 DAG.getEntryNode(), StackSlot);
7339 // Load FP Control Word from stack slot
7340 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7343 // Transform as necessary
7345 DAG.getNode(ISD::SRL, dl, MVT::i16,
7346 DAG.getNode(ISD::AND, dl, MVT::i16,
7347 CWD, DAG.getConstant(0x800, MVT::i16)),
7348 DAG.getConstant(11, MVT::i8));
7350 DAG.getNode(ISD::SRL, dl, MVT::i16,
7351 DAG.getNode(ISD::AND, dl, MVT::i16,
7352 CWD, DAG.getConstant(0x400, MVT::i16)),
7353 DAG.getConstant(9, MVT::i8));
7356 DAG.getNode(ISD::AND, dl, MVT::i16,
7357 DAG.getNode(ISD::ADD, dl, MVT::i16,
7358 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7359 DAG.getConstant(1, MVT::i16)),
7360 DAG.getConstant(3, MVT::i16));
7363 return DAG.getNode((VT.getSizeInBits() < 16 ?
7364 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7367 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
7368 EVT VT = Op.getValueType();
7370 unsigned NumBits = VT.getSizeInBits();
7371 DebugLoc dl = Op.getDebugLoc();
7373 Op = Op.getOperand(0);
7374 if (VT == MVT::i8) {
7375 // Zero extend to i32 since there is not an i8 bsr.
7377 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7380 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7381 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7382 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7384 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7387 DAG.getConstant(NumBits+NumBits-1, OpVT),
7388 DAG.getConstant(X86::COND_E, MVT::i8),
7391 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7393 // Finally xor with NumBits-1.
7394 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7397 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7401 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
7402 EVT VT = Op.getValueType();
7404 unsigned NumBits = VT.getSizeInBits();
7405 DebugLoc dl = Op.getDebugLoc();
7407 Op = Op.getOperand(0);
7408 if (VT == MVT::i8) {
7410 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7413 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7414 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7415 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7417 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7420 DAG.getConstant(NumBits, OpVT),
7421 DAG.getConstant(X86::COND_E, MVT::i8),
7424 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7427 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7431 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
7432 EVT VT = Op.getValueType();
7433 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7434 DebugLoc dl = Op.getDebugLoc();
7436 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7437 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7438 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7439 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7440 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7442 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7443 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7444 // return AloBlo + AloBhi + AhiBlo;
7446 SDValue A = Op.getOperand(0);
7447 SDValue B = Op.getOperand(1);
7449 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7450 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7451 A, DAG.getConstant(32, MVT::i32));
7452 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7453 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7454 B, DAG.getConstant(32, MVT::i32));
7455 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7456 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7458 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7459 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7461 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7462 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7464 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7465 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7466 AloBhi, DAG.getConstant(32, MVT::i32));
7467 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7468 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7469 AhiBlo, DAG.getConstant(32, MVT::i32));
7470 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7471 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7476 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
7477 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7478 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7479 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7480 // has only one use.
7481 SDNode *N = Op.getNode();
7482 SDValue LHS = N->getOperand(0);
7483 SDValue RHS = N->getOperand(1);
7484 unsigned BaseOp = 0;
7486 DebugLoc dl = Op.getDebugLoc();
7488 switch (Op.getOpcode()) {
7489 default: llvm_unreachable("Unknown ovf instruction!");
7491 // A subtract of one will be selected as a INC. Note that INC doesn't
7492 // set CF, so we can't do this for UADDO.
7493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7494 if (C->getAPIntValue() == 1) {
7495 BaseOp = X86ISD::INC;
7499 BaseOp = X86ISD::ADD;
7503 BaseOp = X86ISD::ADD;
7507 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7508 // set CF, so we can't do this for USUBO.
7509 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7510 if (C->getAPIntValue() == 1) {
7511 BaseOp = X86ISD::DEC;
7515 BaseOp = X86ISD::SUB;
7519 BaseOp = X86ISD::SUB;
7523 BaseOp = X86ISD::SMUL;
7527 BaseOp = X86ISD::UMUL;
7532 // Also sets EFLAGS.
7533 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7534 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7537 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7538 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7540 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7544 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
7545 DebugLoc dl = Op.getDebugLoc();
7547 if (!Subtarget->hasSSE2())
7548 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
7549 DAG.getConstant(0, MVT::i32));
7551 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
7553 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
7555 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7556 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
7557 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
7558 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
7560 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
7561 if (!Op1 && !Op2 && !Op3 && Op4)
7562 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
7564 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
7565 if (Op1 && !Op2 && !Op3 && !Op4)
7566 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
7568 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
7570 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
7574 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
7575 EVT T = Op.getValueType();
7576 DebugLoc dl = Op.getDebugLoc();
7579 switch(T.getSimpleVT().SimpleTy) {
7581 assert(false && "Invalid value type!");
7582 case MVT::i8: Reg = X86::AL; size = 1; break;
7583 case MVT::i16: Reg = X86::AX; size = 2; break;
7584 case MVT::i32: Reg = X86::EAX; size = 4; break;
7586 assert(Subtarget->is64Bit() && "Node not type legal!");
7587 Reg = X86::RAX; size = 8;
7590 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7591 Op.getOperand(2), SDValue());
7592 SDValue Ops[] = { cpIn.getValue(0),
7595 DAG.getTargetConstant(size, MVT::i8),
7597 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7598 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7600 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7604 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7605 SelectionDAG &DAG) const {
7606 assert(Subtarget->is64Bit() && "Result not type legalized?");
7607 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7608 SDValue TheChain = Op.getOperand(0);
7609 DebugLoc dl = Op.getDebugLoc();
7610 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7611 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7612 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7614 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7615 DAG.getConstant(32, MVT::i8));
7617 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7620 return DAG.getMergeValues(Ops, 2, dl);
7623 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
7624 SelectionDAG &DAG) const {
7625 EVT SrcVT = Op.getOperand(0).getValueType();
7626 EVT DstVT = Op.getValueType();
7627 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
7628 Subtarget->hasMMX() && !DisableMMX) &&
7629 "Unexpected custom BIT_CONVERT");
7630 assert((DstVT == MVT::i64 ||
7631 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
7632 "Unexpected custom BIT_CONVERT");
7633 // i64 <=> MMX conversions are Legal.
7634 if (SrcVT==MVT::i64 && DstVT.isVector())
7636 if (DstVT==MVT::i64 && SrcVT.isVector())
7638 // MMX <=> MMX conversions are Legal.
7639 if (SrcVT.isVector() && DstVT.isVector())
7641 // All other conversions need to be expanded.
7644 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
7645 SDNode *Node = Op.getNode();
7646 DebugLoc dl = Node->getDebugLoc();
7647 EVT T = Node->getValueType(0);
7648 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7649 DAG.getConstant(0, T), Node->getOperand(2));
7650 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7651 cast<AtomicSDNode>(Node)->getMemoryVT(),
7652 Node->getOperand(0),
7653 Node->getOperand(1), negOp,
7654 cast<AtomicSDNode>(Node)->getSrcValue(),
7655 cast<AtomicSDNode>(Node)->getAlignment());
7658 /// LowerOperation - Provide custom lowering hooks for some operations.
7660 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7661 switch (Op.getOpcode()) {
7662 default: llvm_unreachable("Should not custom lower this!");
7663 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
7664 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7665 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7666 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7667 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7668 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7669 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7670 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7671 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7672 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7673 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7674 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7675 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7676 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7677 case ISD::SHL_PARTS:
7678 case ISD::SRA_PARTS:
7679 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7680 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7681 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7682 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7683 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7684 case ISD::FABS: return LowerFABS(Op, DAG);
7685 case ISD::FNEG: return LowerFNEG(Op, DAG);
7686 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7687 case ISD::SETCC: return LowerSETCC(Op, DAG);
7688 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7689 case ISD::SELECT: return LowerSELECT(Op, DAG);
7690 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7691 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7692 case ISD::VASTART: return LowerVASTART(Op, DAG);
7693 case ISD::VAARG: return LowerVAARG(Op, DAG);
7694 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7695 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7696 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7697 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7698 case ISD::FRAME_TO_ARGS_OFFSET:
7699 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7700 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7701 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7702 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7703 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7704 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7705 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7706 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7712 case ISD::UMULO: return LowerXALUO(Op, DAG);
7713 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7714 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
7718 void X86TargetLowering::
7719 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7720 SelectionDAG &DAG, unsigned NewOp) const {
7721 EVT T = Node->getValueType(0);
7722 DebugLoc dl = Node->getDebugLoc();
7723 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7725 SDValue Chain = Node->getOperand(0);
7726 SDValue In1 = Node->getOperand(1);
7727 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7728 Node->getOperand(2), DAG.getIntPtrConstant(0));
7729 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7730 Node->getOperand(2), DAG.getIntPtrConstant(1));
7731 SDValue Ops[] = { Chain, In1, In2L, In2H };
7732 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7734 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7735 cast<MemSDNode>(Node)->getMemOperand());
7736 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7737 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7738 Results.push_back(Result.getValue(2));
7741 /// ReplaceNodeResults - Replace a node with an illegal result type
7742 /// with a new node built out of custom code.
7743 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7744 SmallVectorImpl<SDValue>&Results,
7745 SelectionDAG &DAG) const {
7746 DebugLoc dl = N->getDebugLoc();
7747 switch (N->getOpcode()) {
7749 assert(false && "Do not know how to custom type legalize this operation!");
7751 case ISD::FP_TO_SINT: {
7752 std::pair<SDValue,SDValue> Vals =
7753 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7754 SDValue FIST = Vals.first, StackSlot = Vals.second;
7755 if (FIST.getNode() != 0) {
7756 EVT VT = N->getValueType(0);
7757 // Return a load from the stack slot.
7758 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7763 case ISD::READCYCLECOUNTER: {
7764 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7765 SDValue TheChain = N->getOperand(0);
7766 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7767 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7769 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7771 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7772 SDValue Ops[] = { eax, edx };
7773 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7774 Results.push_back(edx.getValue(1));
7777 case ISD::ATOMIC_CMP_SWAP: {
7778 EVT T = N->getValueType(0);
7779 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7780 SDValue cpInL, cpInH;
7781 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7782 DAG.getConstant(0, MVT::i32));
7783 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7784 DAG.getConstant(1, MVT::i32));
7785 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7786 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7788 SDValue swapInL, swapInH;
7789 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7790 DAG.getConstant(0, MVT::i32));
7791 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7792 DAG.getConstant(1, MVT::i32));
7793 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7795 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7796 swapInL.getValue(1));
7797 SDValue Ops[] = { swapInH.getValue(0),
7799 swapInH.getValue(1) };
7800 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7801 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7802 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7803 MVT::i32, Result.getValue(1));
7804 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7805 MVT::i32, cpOutL.getValue(2));
7806 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7807 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7808 Results.push_back(cpOutH.getValue(1));
7811 case ISD::ATOMIC_LOAD_ADD:
7812 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7814 case ISD::ATOMIC_LOAD_AND:
7815 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7817 case ISD::ATOMIC_LOAD_NAND:
7818 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7820 case ISD::ATOMIC_LOAD_OR:
7821 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7823 case ISD::ATOMIC_LOAD_SUB:
7824 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7826 case ISD::ATOMIC_LOAD_XOR:
7827 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7829 case ISD::ATOMIC_SWAP:
7830 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7835 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7837 default: return NULL;
7838 case X86ISD::BSF: return "X86ISD::BSF";
7839 case X86ISD::BSR: return "X86ISD::BSR";
7840 case X86ISD::SHLD: return "X86ISD::SHLD";
7841 case X86ISD::SHRD: return "X86ISD::SHRD";
7842 case X86ISD::FAND: return "X86ISD::FAND";
7843 case X86ISD::FOR: return "X86ISD::FOR";
7844 case X86ISD::FXOR: return "X86ISD::FXOR";
7845 case X86ISD::FSRL: return "X86ISD::FSRL";
7846 case X86ISD::FILD: return "X86ISD::FILD";
7847 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7848 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7849 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7850 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7851 case X86ISD::FLD: return "X86ISD::FLD";
7852 case X86ISD::FST: return "X86ISD::FST";
7853 case X86ISD::CALL: return "X86ISD::CALL";
7854 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7855 case X86ISD::BT: return "X86ISD::BT";
7856 case X86ISD::CMP: return "X86ISD::CMP";
7857 case X86ISD::COMI: return "X86ISD::COMI";
7858 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7859 case X86ISD::SETCC: return "X86ISD::SETCC";
7860 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7861 case X86ISD::CMOV: return "X86ISD::CMOV";
7862 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7863 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7864 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7865 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7866 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7867 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7868 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7869 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7870 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7871 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7872 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7873 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7874 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7875 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7876 case X86ISD::FMAX: return "X86ISD::FMAX";
7877 case X86ISD::FMIN: return "X86ISD::FMIN";
7878 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7879 case X86ISD::FRCP: return "X86ISD::FRCP";
7880 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7881 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
7882 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7883 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7884 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7885 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7886 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7887 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7888 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7889 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7890 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7891 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7892 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7893 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7894 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7895 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7896 case X86ISD::VSHL: return "X86ISD::VSHL";
7897 case X86ISD::VSRL: return "X86ISD::VSRL";
7898 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7899 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7900 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7901 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7902 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7903 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7904 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7905 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7906 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7907 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7908 case X86ISD::ADD: return "X86ISD::ADD";
7909 case X86ISD::SUB: return "X86ISD::SUB";
7910 case X86ISD::SMUL: return "X86ISD::SMUL";
7911 case X86ISD::UMUL: return "X86ISD::UMUL";
7912 case X86ISD::INC: return "X86ISD::INC";
7913 case X86ISD::DEC: return "X86ISD::DEC";
7914 case X86ISD::OR: return "X86ISD::OR";
7915 case X86ISD::XOR: return "X86ISD::XOR";
7916 case X86ISD::AND: return "X86ISD::AND";
7917 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7918 case X86ISD::PTEST: return "X86ISD::PTEST";
7919 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7920 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7924 // isLegalAddressingMode - Return true if the addressing mode represented
7925 // by AM is legal for this target, for a load/store of the specified type.
7926 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7927 const Type *Ty) const {
7928 // X86 supports extremely general addressing modes.
7929 CodeModel::Model M = getTargetMachine().getCodeModel();
7931 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7932 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7937 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7939 // If a reference to this global requires an extra load, we can't fold it.
7940 if (isGlobalStubReference(GVFlags))
7943 // If BaseGV requires a register for the PIC base, we cannot also have a
7944 // BaseReg specified.
7945 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7948 // If lower 4G is not available, then we must use rip-relative addressing.
7949 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7959 // These scales always work.
7964 // These scales are formed with basereg+scalereg. Only accept if there is
7969 default: // Other stuff never works.
7977 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7978 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7980 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7981 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7982 if (NumBits1 <= NumBits2)
7987 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7988 if (!VT1.isInteger() || !VT2.isInteger())
7990 unsigned NumBits1 = VT1.getSizeInBits();
7991 unsigned NumBits2 = VT2.getSizeInBits();
7992 if (NumBits1 <= NumBits2)
7997 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7998 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7999 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
8002 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
8003 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8004 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
8007 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
8008 // i16 instructions are longer (0x66 prefix) and potentially slower.
8009 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
8012 /// isShuffleMaskLegal - Targets can use this to indicate that they only
8013 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
8014 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
8015 /// are assumed to be legal.
8017 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
8019 // Very little shuffling can be done for 64-bit vectors right now.
8020 if (VT.getSizeInBits() == 64)
8021 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
8023 // FIXME: pshufb, blends, shifts.
8024 return (VT.getVectorNumElements() == 2 ||
8025 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
8026 isMOVLMask(M, VT) ||
8027 isSHUFPMask(M, VT) ||
8028 isPSHUFDMask(M, VT) ||
8029 isPSHUFHWMask(M, VT) ||
8030 isPSHUFLWMask(M, VT) ||
8031 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
8032 isUNPCKLMask(M, VT) ||
8033 isUNPCKHMask(M, VT) ||
8034 isUNPCKL_v_undef_Mask(M, VT) ||
8035 isUNPCKH_v_undef_Mask(M, VT));
8039 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
8041 unsigned NumElts = VT.getVectorNumElements();
8042 // FIXME: This collection of masks seems suspect.
8045 if (NumElts == 4 && VT.getSizeInBits() == 128) {
8046 return (isMOVLMask(Mask, VT) ||
8047 isCommutedMOVLMask(Mask, VT, true) ||
8048 isSHUFPMask(Mask, VT) ||
8049 isCommutedSHUFPMask(Mask, VT));
8054 //===----------------------------------------------------------------------===//
8055 // X86 Scheduler Hooks
8056 //===----------------------------------------------------------------------===//
8058 // private utility function
8060 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
8061 MachineBasicBlock *MBB,
8068 TargetRegisterClass *RC,
8069 bool invSrc) const {
8070 // For the atomic bitwise operator, we generate
8073 // ld t1 = [bitinstr.addr]
8074 // op t2 = t1, [bitinstr.val]
8076 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8078 // fallthrough -->nextMBB
8079 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8080 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8081 MachineFunction::iterator MBBIter = MBB;
8084 /// First build the CFG
8085 MachineFunction *F = MBB->getParent();
8086 MachineBasicBlock *thisMBB = MBB;
8087 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8088 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8089 F->insert(MBBIter, newMBB);
8090 F->insert(MBBIter, nextMBB);
8092 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8093 nextMBB->splice(nextMBB->begin(), thisMBB,
8094 llvm::next(MachineBasicBlock::iterator(bInstr)),
8096 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8098 // Update thisMBB to fall through to newMBB
8099 thisMBB->addSuccessor(newMBB);
8101 // newMBB jumps to itself and fall through to nextMBB
8102 newMBB->addSuccessor(nextMBB);
8103 newMBB->addSuccessor(newMBB);
8105 // Insert instructions into newMBB based on incoming instruction
8106 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8107 "unexpected number of operands");
8108 DebugLoc dl = bInstr->getDebugLoc();
8109 MachineOperand& destOper = bInstr->getOperand(0);
8110 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8111 int numArgs = bInstr->getNumOperands() - 1;
8112 for (int i=0; i < numArgs; ++i)
8113 argOpers[i] = &bInstr->getOperand(i+1);
8115 // x86 address has 4 operands: base, index, scale, and displacement
8116 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8117 int valArgIndx = lastAddrIndx + 1;
8119 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8120 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
8121 for (int i=0; i <= lastAddrIndx; ++i)
8122 (*MIB).addOperand(*argOpers[i]);
8124 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
8126 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
8131 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8132 assert((argOpers[valArgIndx]->isReg() ||
8133 argOpers[valArgIndx]->isImm()) &&
8135 if (argOpers[valArgIndx]->isReg())
8136 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
8138 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
8140 (*MIB).addOperand(*argOpers[valArgIndx]);
8142 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
8145 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
8146 for (int i=0; i <= lastAddrIndx; ++i)
8147 (*MIB).addOperand(*argOpers[i]);
8149 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8150 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8151 bInstr->memoperands_end());
8153 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
8157 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8159 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8163 // private utility function: 64 bit atomics on 32 bit host.
8165 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
8166 MachineBasicBlock *MBB,
8171 bool invSrc) const {
8172 // For the atomic bitwise operator, we generate
8173 // thisMBB (instructions are in pairs, except cmpxchg8b)
8174 // ld t1,t2 = [bitinstr.addr]
8176 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8177 // op t5, t6 <- out1, out2, [bitinstr.val]
8178 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8179 // mov ECX, EBX <- t5, t6
8180 // mov EAX, EDX <- t1, t2
8181 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8182 // mov t3, t4 <- EAX, EDX
8184 // result in out1, out2
8185 // fallthrough -->nextMBB
8187 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8188 const unsigned LoadOpc = X86::MOV32rm;
8189 const unsigned NotOpc = X86::NOT32r;
8190 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8191 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8192 MachineFunction::iterator MBBIter = MBB;
8195 /// First build the CFG
8196 MachineFunction *F = MBB->getParent();
8197 MachineBasicBlock *thisMBB = MBB;
8198 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8199 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8200 F->insert(MBBIter, newMBB);
8201 F->insert(MBBIter, nextMBB);
8203 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8204 nextMBB->splice(nextMBB->begin(), thisMBB,
8205 llvm::next(MachineBasicBlock::iterator(bInstr)),
8207 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8209 // Update thisMBB to fall through to newMBB
8210 thisMBB->addSuccessor(newMBB);
8212 // newMBB jumps to itself and fall through to nextMBB
8213 newMBB->addSuccessor(nextMBB);
8214 newMBB->addSuccessor(newMBB);
8216 DebugLoc dl = bInstr->getDebugLoc();
8217 // Insert instructions into newMBB based on incoming instruction
8218 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8219 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
8220 "unexpected number of operands");
8221 MachineOperand& dest1Oper = bInstr->getOperand(0);
8222 MachineOperand& dest2Oper = bInstr->getOperand(1);
8223 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8224 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
8225 argOpers[i] = &bInstr->getOperand(i+2);
8227 // We use some of the operands multiple times, so conservatively just
8228 // clear any kill flags that might be present.
8229 if (argOpers[i]->isReg() && argOpers[i]->isUse())
8230 argOpers[i]->setIsKill(false);
8233 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8234 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8236 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8237 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8238 for (int i=0; i <= lastAddrIndx; ++i)
8239 (*MIB).addOperand(*argOpers[i]);
8240 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8241 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8242 // add 4 to displacement.
8243 for (int i=0; i <= lastAddrIndx-2; ++i)
8244 (*MIB).addOperand(*argOpers[i]);
8245 MachineOperand newOp3 = *(argOpers[3]);
8247 newOp3.setImm(newOp3.getImm()+4);
8249 newOp3.setOffset(newOp3.getOffset()+4);
8250 (*MIB).addOperand(newOp3);
8251 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8253 // t3/4 are defined later, at the bottom of the loop
8254 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8255 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8256 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8257 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8258 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8259 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8261 // The subsequent operations should be using the destination registers of
8262 //the PHI instructions.
8264 t1 = F->getRegInfo().createVirtualRegister(RC);
8265 t2 = F->getRegInfo().createVirtualRegister(RC);
8266 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8267 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8269 t1 = dest1Oper.getReg();
8270 t2 = dest2Oper.getReg();
8273 int valArgIndx = lastAddrIndx + 1;
8274 assert((argOpers[valArgIndx]->isReg() ||
8275 argOpers[valArgIndx]->isImm()) &&
8277 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8278 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8279 if (argOpers[valArgIndx]->isReg())
8280 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8282 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8283 if (regOpcL != X86::MOV32rr)
8285 (*MIB).addOperand(*argOpers[valArgIndx]);
8286 assert(argOpers[valArgIndx + 1]->isReg() ==
8287 argOpers[valArgIndx]->isReg());
8288 assert(argOpers[valArgIndx + 1]->isImm() ==
8289 argOpers[valArgIndx]->isImm());
8290 if (argOpers[valArgIndx + 1]->isReg())
8291 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8293 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8294 if (regOpcH != X86::MOV32rr)
8296 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8298 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
8300 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
8303 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
8305 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
8308 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8309 for (int i=0; i <= lastAddrIndx; ++i)
8310 (*MIB).addOperand(*argOpers[i]);
8312 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8313 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8314 bInstr->memoperands_end());
8316 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
8317 MIB.addReg(X86::EAX);
8318 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
8319 MIB.addReg(X86::EDX);
8322 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8324 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8328 // private utility function
8330 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8331 MachineBasicBlock *MBB,
8332 unsigned cmovOpc) const {
8333 // For the atomic min/max operator, we generate
8336 // ld t1 = [min/max.addr]
8337 // mov t2 = [min/max.val]
8339 // cmov[cond] t2 = t1
8341 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8343 // fallthrough -->nextMBB
8345 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8346 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8347 MachineFunction::iterator MBBIter = MBB;
8350 /// First build the CFG
8351 MachineFunction *F = MBB->getParent();
8352 MachineBasicBlock *thisMBB = MBB;
8353 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8354 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8355 F->insert(MBBIter, newMBB);
8356 F->insert(MBBIter, nextMBB);
8358 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8359 nextMBB->splice(nextMBB->begin(), thisMBB,
8360 llvm::next(MachineBasicBlock::iterator(mInstr)),
8362 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8364 // Update thisMBB to fall through to newMBB
8365 thisMBB->addSuccessor(newMBB);
8367 // newMBB jumps to newMBB and fall through to nextMBB
8368 newMBB->addSuccessor(nextMBB);
8369 newMBB->addSuccessor(newMBB);
8371 DebugLoc dl = mInstr->getDebugLoc();
8372 // Insert instructions into newMBB based on incoming instruction
8373 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8374 "unexpected number of operands");
8375 MachineOperand& destOper = mInstr->getOperand(0);
8376 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8377 int numArgs = mInstr->getNumOperands() - 1;
8378 for (int i=0; i < numArgs; ++i)
8379 argOpers[i] = &mInstr->getOperand(i+1);
8381 // x86 address has 4 operands: base, index, scale, and displacement
8382 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8383 int valArgIndx = lastAddrIndx + 1;
8385 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8386 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8387 for (int i=0; i <= lastAddrIndx; ++i)
8388 (*MIB).addOperand(*argOpers[i]);
8390 // We only support register and immediate values
8391 assert((argOpers[valArgIndx]->isReg() ||
8392 argOpers[valArgIndx]->isImm()) &&
8395 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8396 if (argOpers[valArgIndx]->isReg())
8397 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
8399 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8400 (*MIB).addOperand(*argOpers[valArgIndx]);
8402 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
8405 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8410 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8411 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8415 // Cmp and exchange if none has modified the memory location
8416 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8417 for (int i=0; i <= lastAddrIndx; ++i)
8418 (*MIB).addOperand(*argOpers[i]);
8420 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8421 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8422 mInstr->memoperands_end());
8424 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
8425 MIB.addReg(X86::EAX);
8428 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8430 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
8434 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8435 // all of this code can be replaced with that in the .td file.
8437 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8438 unsigned numArgs, bool memArg) const {
8440 DebugLoc dl = MI->getDebugLoc();
8441 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8445 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8447 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8449 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8451 for (unsigned i = 0; i < numArgs; ++i) {
8452 MachineOperand &Op = MI->getOperand(i+1);
8454 if (!(Op.isReg() && Op.isImplicit()))
8458 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8461 MI->eraseFromParent();
8467 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8469 MachineBasicBlock *MBB) const {
8470 // Emit code to save XMM registers to the stack. The ABI says that the
8471 // number of registers to save is given in %al, so it's theoretically
8472 // possible to do an indirect jump trick to avoid saving all of them,
8473 // however this code takes a simpler approach and just executes all
8474 // of the stores if %al is non-zero. It's less code, and it's probably
8475 // easier on the hardware branch predictor, and stores aren't all that
8476 // expensive anyway.
8478 // Create the new basic blocks. One block contains all the XMM stores,
8479 // and one block is the final destination regardless of whether any
8480 // stores were performed.
8481 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8482 MachineFunction *F = MBB->getParent();
8483 MachineFunction::iterator MBBIter = MBB;
8485 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8486 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8487 F->insert(MBBIter, XMMSaveMBB);
8488 F->insert(MBBIter, EndMBB);
8490 // Transfer the remainder of MBB and its successor edges to EndMBB.
8491 EndMBB->splice(EndMBB->begin(), MBB,
8492 llvm::next(MachineBasicBlock::iterator(MI)),
8494 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
8496 // The original block will now fall through to the XMM save block.
8497 MBB->addSuccessor(XMMSaveMBB);
8498 // The XMMSaveMBB will fall through to the end block.
8499 XMMSaveMBB->addSuccessor(EndMBB);
8501 // Now add the instructions.
8502 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8503 DebugLoc DL = MI->getDebugLoc();
8505 unsigned CountReg = MI->getOperand(0).getReg();
8506 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8507 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8509 if (!Subtarget->isTargetWin64()) {
8510 // If %al is 0, branch around the XMM save block.
8511 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8512 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8513 MBB->addSuccessor(EndMBB);
8516 // In the XMM save block, save all the XMM argument registers.
8517 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8518 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8519 MachineMemOperand *MMO =
8520 F->getMachineMemOperand(
8521 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8522 MachineMemOperand::MOStore, Offset,
8523 /*Size=*/16, /*Align=*/16);
8524 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8525 .addFrameIndex(RegSaveFrameIndex)
8526 .addImm(/*Scale=*/1)
8527 .addReg(/*IndexReg=*/0)
8528 .addImm(/*Disp=*/Offset)
8529 .addReg(/*Segment=*/0)
8530 .addReg(MI->getOperand(i).getReg())
8531 .addMemOperand(MMO);
8534 MI->eraseFromParent(); // The pseudo instruction is gone now.
8540 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8541 MachineBasicBlock *BB) const {
8542 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8543 DebugLoc DL = MI->getDebugLoc();
8545 // To "insert" a SELECT_CC instruction, we actually have to insert the
8546 // diamond control-flow pattern. The incoming instruction knows the
8547 // destination vreg to set, the condition code register to branch on, the
8548 // true/false values to select between, and a branch opcode to use.
8549 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8550 MachineFunction::iterator It = BB;
8556 // cmpTY ccX, r1, r2
8558 // fallthrough --> copy0MBB
8559 MachineBasicBlock *thisMBB = BB;
8560 MachineFunction *F = BB->getParent();
8561 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8562 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8563 F->insert(It, copy0MBB);
8564 F->insert(It, sinkMBB);
8566 // If the EFLAGS register isn't dead in the terminator, then claim that it's
8567 // live into the sink and copy blocks.
8568 const MachineFunction *MF = BB->getParent();
8569 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
8570 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
8572 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
8573 const MachineOperand &MO = MI->getOperand(I);
8574 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
8575 unsigned Reg = MO.getReg();
8576 if (Reg != X86::EFLAGS) continue;
8577 copy0MBB->addLiveIn(Reg);
8578 sinkMBB->addLiveIn(Reg);
8581 // Transfer the remainder of BB and its successor edges to sinkMBB.
8582 sinkMBB->splice(sinkMBB->begin(), BB,
8583 llvm::next(MachineBasicBlock::iterator(MI)),
8585 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8587 // Add the true and fallthrough blocks as its successors.
8588 BB->addSuccessor(copy0MBB);
8589 BB->addSuccessor(sinkMBB);
8591 // Create the conditional branch instruction.
8593 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8594 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8597 // %FalseValue = ...
8598 // # fallthrough to sinkMBB
8599 copy0MBB->addSuccessor(sinkMBB);
8602 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8604 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8605 TII->get(X86::PHI), MI->getOperand(0).getReg())
8606 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8607 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8609 MI->eraseFromParent(); // The pseudo instruction is gone now.
8614 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8615 MachineBasicBlock *BB) const {
8616 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8617 DebugLoc DL = MI->getDebugLoc();
8619 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8620 // non-trivial part is impdef of ESP.
8621 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8624 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
8625 .addExternalSymbol("_alloca")
8626 .addReg(X86::EAX, RegState::Implicit)
8627 .addReg(X86::ESP, RegState::Implicit)
8628 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8629 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8631 MI->eraseFromParent(); // The pseudo instruction is gone now.
8636 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
8637 MachineBasicBlock *BB) const {
8638 // This is pretty easy. We're taking the value that we received from
8639 // our load from the relocation, sticking it in either RDI (x86-64)
8640 // or EAX and doing an indirect call. The return value will then
8641 // be in the normal return register.
8642 const X86InstrInfo *TII
8643 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
8644 DebugLoc DL = MI->getDebugLoc();
8645 MachineFunction *F = BB->getParent();
8647 assert(MI->getOperand(3).isGlobal() && "This should be a global");
8649 if (Subtarget->is64Bit()) {
8650 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8651 TII->get(X86::MOV64rm), X86::RDI)
8653 .addImm(0).addReg(0)
8654 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8655 MI->getOperand(3).getTargetFlags())
8657 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
8658 addDirectMem(MIB, X86::RDI);
8659 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
8660 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8661 TII->get(X86::MOV32rm), X86::EAX)
8663 .addImm(0).addReg(0)
8664 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8665 MI->getOperand(3).getTargetFlags())
8667 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8668 addDirectMem(MIB, X86::EAX);
8670 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8671 TII->get(X86::MOV32rm), X86::EAX)
8672 .addReg(TII->getGlobalBaseReg(F))
8673 .addImm(0).addReg(0)
8674 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8675 MI->getOperand(3).getTargetFlags())
8677 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8678 addDirectMem(MIB, X86::EAX);
8681 MI->eraseFromParent(); // The pseudo instruction is gone now.
8686 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8687 MachineBasicBlock *BB) const {
8688 switch (MI->getOpcode()) {
8689 default: assert(false && "Unexpected instr type to insert");
8690 case X86::MINGW_ALLOCA:
8691 return EmitLoweredMingwAlloca(MI, BB);
8692 case X86::TLSCall_32:
8693 case X86::TLSCall_64:
8694 return EmitLoweredTLSCall(MI, BB);
8696 case X86::CMOV_V1I64:
8697 case X86::CMOV_FR32:
8698 case X86::CMOV_FR64:
8699 case X86::CMOV_V4F32:
8700 case X86::CMOV_V2F64:
8701 case X86::CMOV_V2I64:
8702 case X86::CMOV_GR16:
8703 case X86::CMOV_GR32:
8704 case X86::CMOV_RFP32:
8705 case X86::CMOV_RFP64:
8706 case X86::CMOV_RFP80:
8707 return EmitLoweredSelect(MI, BB);
8709 case X86::FP32_TO_INT16_IN_MEM:
8710 case X86::FP32_TO_INT32_IN_MEM:
8711 case X86::FP32_TO_INT64_IN_MEM:
8712 case X86::FP64_TO_INT16_IN_MEM:
8713 case X86::FP64_TO_INT32_IN_MEM:
8714 case X86::FP64_TO_INT64_IN_MEM:
8715 case X86::FP80_TO_INT16_IN_MEM:
8716 case X86::FP80_TO_INT32_IN_MEM:
8717 case X86::FP80_TO_INT64_IN_MEM: {
8718 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8719 DebugLoc DL = MI->getDebugLoc();
8721 // Change the floating point control register to use "round towards zero"
8722 // mode when truncating to an integer value.
8723 MachineFunction *F = BB->getParent();
8724 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8725 addFrameReference(BuildMI(*BB, MI, DL,
8726 TII->get(X86::FNSTCW16m)), CWFrameIdx);
8728 // Load the old value of the high byte of the control word...
8730 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8731 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
8734 // Set the high part to be round to zero...
8735 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8738 // Reload the modified control word now...
8739 addFrameReference(BuildMI(*BB, MI, DL,
8740 TII->get(X86::FLDCW16m)), CWFrameIdx);
8742 // Restore the memory image of control word to original value
8743 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8746 // Get the X86 opcode to use.
8748 switch (MI->getOpcode()) {
8749 default: llvm_unreachable("illegal opcode!");
8750 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8751 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8752 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8753 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8754 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8755 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8756 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8757 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8758 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8762 MachineOperand &Op = MI->getOperand(0);
8764 AM.BaseType = X86AddressMode::RegBase;
8765 AM.Base.Reg = Op.getReg();
8767 AM.BaseType = X86AddressMode::FrameIndexBase;
8768 AM.Base.FrameIndex = Op.getIndex();
8770 Op = MI->getOperand(1);
8772 AM.Scale = Op.getImm();
8773 Op = MI->getOperand(2);
8775 AM.IndexReg = Op.getImm();
8776 Op = MI->getOperand(3);
8777 if (Op.isGlobal()) {
8778 AM.GV = Op.getGlobal();
8780 AM.Disp = Op.getImm();
8782 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
8783 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
8785 // Reload the original control word now.
8786 addFrameReference(BuildMI(*BB, MI, DL,
8787 TII->get(X86::FLDCW16m)), CWFrameIdx);
8789 MI->eraseFromParent(); // The pseudo instruction is gone now.
8792 // String/text processing lowering.
8793 case X86::PCMPISTRM128REG:
8794 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8795 case X86::PCMPISTRM128MEM:
8796 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8797 case X86::PCMPESTRM128REG:
8798 return EmitPCMP(MI, BB, 5, false /* in mem */);
8799 case X86::PCMPESTRM128MEM:
8800 return EmitPCMP(MI, BB, 5, true /* in mem */);
8803 case X86::ATOMAND32:
8804 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8805 X86::AND32ri, X86::MOV32rm,
8807 X86::NOT32r, X86::EAX,
8808 X86::GR32RegisterClass);
8810 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8811 X86::OR32ri, X86::MOV32rm,
8813 X86::NOT32r, X86::EAX,
8814 X86::GR32RegisterClass);
8815 case X86::ATOMXOR32:
8816 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8817 X86::XOR32ri, X86::MOV32rm,
8819 X86::NOT32r, X86::EAX,
8820 X86::GR32RegisterClass);
8821 case X86::ATOMNAND32:
8822 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8823 X86::AND32ri, X86::MOV32rm,
8825 X86::NOT32r, X86::EAX,
8826 X86::GR32RegisterClass, true);
8827 case X86::ATOMMIN32:
8828 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8829 case X86::ATOMMAX32:
8830 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8831 case X86::ATOMUMIN32:
8832 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8833 case X86::ATOMUMAX32:
8834 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8836 case X86::ATOMAND16:
8837 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8838 X86::AND16ri, X86::MOV16rm,
8840 X86::NOT16r, X86::AX,
8841 X86::GR16RegisterClass);
8843 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8844 X86::OR16ri, X86::MOV16rm,
8846 X86::NOT16r, X86::AX,
8847 X86::GR16RegisterClass);
8848 case X86::ATOMXOR16:
8849 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8850 X86::XOR16ri, X86::MOV16rm,
8852 X86::NOT16r, X86::AX,
8853 X86::GR16RegisterClass);
8854 case X86::ATOMNAND16:
8855 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8856 X86::AND16ri, X86::MOV16rm,
8858 X86::NOT16r, X86::AX,
8859 X86::GR16RegisterClass, true);
8860 case X86::ATOMMIN16:
8861 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8862 case X86::ATOMMAX16:
8863 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8864 case X86::ATOMUMIN16:
8865 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8866 case X86::ATOMUMAX16:
8867 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8870 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8871 X86::AND8ri, X86::MOV8rm,
8873 X86::NOT8r, X86::AL,
8874 X86::GR8RegisterClass);
8876 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8877 X86::OR8ri, X86::MOV8rm,
8879 X86::NOT8r, X86::AL,
8880 X86::GR8RegisterClass);
8882 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8883 X86::XOR8ri, X86::MOV8rm,
8885 X86::NOT8r, X86::AL,
8886 X86::GR8RegisterClass);
8887 case X86::ATOMNAND8:
8888 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8889 X86::AND8ri, X86::MOV8rm,
8891 X86::NOT8r, X86::AL,
8892 X86::GR8RegisterClass, true);
8893 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8894 // This group is for 64-bit host.
8895 case X86::ATOMAND64:
8896 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8897 X86::AND64ri32, X86::MOV64rm,
8899 X86::NOT64r, X86::RAX,
8900 X86::GR64RegisterClass);
8902 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8903 X86::OR64ri32, X86::MOV64rm,
8905 X86::NOT64r, X86::RAX,
8906 X86::GR64RegisterClass);
8907 case X86::ATOMXOR64:
8908 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8909 X86::XOR64ri32, X86::MOV64rm,
8911 X86::NOT64r, X86::RAX,
8912 X86::GR64RegisterClass);
8913 case X86::ATOMNAND64:
8914 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8915 X86::AND64ri32, X86::MOV64rm,
8917 X86::NOT64r, X86::RAX,
8918 X86::GR64RegisterClass, true);
8919 case X86::ATOMMIN64:
8920 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8921 case X86::ATOMMAX64:
8922 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8923 case X86::ATOMUMIN64:
8924 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8925 case X86::ATOMUMAX64:
8926 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8928 // This group does 64-bit operations on a 32-bit host.
8929 case X86::ATOMAND6432:
8930 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8931 X86::AND32rr, X86::AND32rr,
8932 X86::AND32ri, X86::AND32ri,
8934 case X86::ATOMOR6432:
8935 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8936 X86::OR32rr, X86::OR32rr,
8937 X86::OR32ri, X86::OR32ri,
8939 case X86::ATOMXOR6432:
8940 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8941 X86::XOR32rr, X86::XOR32rr,
8942 X86::XOR32ri, X86::XOR32ri,
8944 case X86::ATOMNAND6432:
8945 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8946 X86::AND32rr, X86::AND32rr,
8947 X86::AND32ri, X86::AND32ri,
8949 case X86::ATOMADD6432:
8950 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8951 X86::ADD32rr, X86::ADC32rr,
8952 X86::ADD32ri, X86::ADC32ri,
8954 case X86::ATOMSUB6432:
8955 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8956 X86::SUB32rr, X86::SBB32rr,
8957 X86::SUB32ri, X86::SBB32ri,
8959 case X86::ATOMSWAP6432:
8960 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8961 X86::MOV32rr, X86::MOV32rr,
8962 X86::MOV32ri, X86::MOV32ri,
8964 case X86::VASTART_SAVE_XMM_REGS:
8965 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8969 //===----------------------------------------------------------------------===//
8970 // X86 Optimization Hooks
8971 //===----------------------------------------------------------------------===//
8973 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8977 const SelectionDAG &DAG,
8978 unsigned Depth) const {
8979 unsigned Opc = Op.getOpcode();
8980 assert((Opc >= ISD::BUILTIN_OP_END ||
8981 Opc == ISD::INTRINSIC_WO_CHAIN ||
8982 Opc == ISD::INTRINSIC_W_CHAIN ||
8983 Opc == ISD::INTRINSIC_VOID) &&
8984 "Should use MaskedValueIsZero if you don't know whether Op"
8985 " is a target node!");
8987 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8999 // These nodes' second result is a boolean.
9000 if (Op.getResNo() == 0)
9004 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
9005 Mask.getBitWidth() - 1);
9010 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
9011 /// node is a GlobalAddress + offset.
9012 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
9013 const GlobalValue* &GA,
9014 int64_t &Offset) const {
9015 if (N->getOpcode() == X86ISD::Wrapper) {
9016 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
9017 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
9018 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
9022 return TargetLowering::isGAPlusOffset(N, GA, Offset);
9025 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
9026 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
9027 /// if the load addresses are consecutive, non-overlapping, and in the right
9029 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
9030 const TargetLowering &TLI) {
9031 DebugLoc dl = N->getDebugLoc();
9032 EVT VT = N->getValueType(0);
9033 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9035 if (VT.getSizeInBits() != 128)
9038 SmallVector<SDValue, 16> Elts;
9039 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
9040 Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
9042 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
9045 /// PerformShuffleCombine - Detect vector gather/scatter index generation
9046 /// and convert it from being a bunch of shuffles and extracts to a simple
9047 /// store and scalar loads to extract the elements.
9048 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
9049 const TargetLowering &TLI) {
9050 SDValue InputVector = N->getOperand(0);
9052 // Only operate on vectors of 4 elements, where the alternative shuffling
9053 // gets to be more expensive.
9054 if (InputVector.getValueType() != MVT::v4i32)
9057 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
9058 // single use which is a sign-extend or zero-extend, and all elements are
9060 SmallVector<SDNode *, 4> Uses;
9061 unsigned ExtractedElements = 0;
9062 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
9063 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
9064 if (UI.getUse().getResNo() != InputVector.getResNo())
9067 SDNode *Extract = *UI;
9068 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9071 if (Extract->getValueType(0) != MVT::i32)
9073 if (!Extract->hasOneUse())
9075 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
9076 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
9078 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
9081 // Record which element was extracted.
9082 ExtractedElements |=
9083 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
9085 Uses.push_back(Extract);
9088 // If not all the elements were used, this may not be worthwhile.
9089 if (ExtractedElements != 15)
9092 // Ok, we've now decided to do the transformation.
9093 DebugLoc dl = InputVector.getDebugLoc();
9095 // Store the value to a temporary stack slot.
9096 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
9097 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL,
9098 0, false, false, 0);
9100 // Replace each use (extract) with a load of the appropriate element.
9101 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
9102 UE = Uses.end(); UI != UE; ++UI) {
9103 SDNode *Extract = *UI;
9105 // Compute the element's address.
9106 SDValue Idx = Extract->getOperand(1);
9108 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
9109 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
9110 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
9112 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
9113 OffsetVal, StackPtr);
9116 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
9117 ScalarAddr, NULL, 0, false, false, 0);
9119 // Replace the exact with the load.
9120 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
9123 // The replacement was made in place; don't return anything.
9127 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
9128 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
9129 const X86Subtarget *Subtarget) {
9130 DebugLoc DL = N->getDebugLoc();
9131 SDValue Cond = N->getOperand(0);
9132 // Get the LHS/RHS of the select.
9133 SDValue LHS = N->getOperand(1);
9134 SDValue RHS = N->getOperand(2);
9136 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
9137 // instructions match the semantics of the common C idiom x<y?x:y but not
9138 // x<=y?x:y, because of how they handle negative zero (which can be
9139 // ignored in unsafe-math mode).
9140 if (Subtarget->hasSSE2() &&
9141 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
9142 Cond.getOpcode() == ISD::SETCC) {
9143 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
9145 unsigned Opcode = 0;
9146 // Check for x CC y ? x : y.
9147 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
9148 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
9152 // Converting this to a min would handle NaNs incorrectly, and swapping
9153 // the operands would cause it to handle comparisons between positive
9154 // and negative zero incorrectly.
9155 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
9156 if (!UnsafeFPMath &&
9157 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9159 std::swap(LHS, RHS);
9161 Opcode = X86ISD::FMIN;
9164 // Converting this to a min would handle comparisons between positive
9165 // and negative zero incorrectly.
9166 if (!UnsafeFPMath &&
9167 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
9169 Opcode = X86ISD::FMIN;
9172 // Converting this to a min would handle both negative zeros and NaNs
9173 // incorrectly, but we can swap the operands to fix both.
9174 std::swap(LHS, RHS);
9178 Opcode = X86ISD::FMIN;
9182 // Converting this to a max would handle comparisons between positive
9183 // and negative zero incorrectly.
9184 if (!UnsafeFPMath &&
9185 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
9187 Opcode = X86ISD::FMAX;
9190 // Converting this to a max would handle NaNs incorrectly, and swapping
9191 // the operands would cause it to handle comparisons between positive
9192 // and negative zero incorrectly.
9193 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
9194 if (!UnsafeFPMath &&
9195 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9197 std::swap(LHS, RHS);
9199 Opcode = X86ISD::FMAX;
9202 // Converting this to a max would handle both negative zeros and NaNs
9203 // incorrectly, but we can swap the operands to fix both.
9204 std::swap(LHS, RHS);
9208 Opcode = X86ISD::FMAX;
9211 // Check for x CC y ? y : x -- a min/max with reversed arms.
9212 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
9213 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
9217 // Converting this to a min would handle comparisons between positive
9218 // and negative zero incorrectly, and swapping the operands would
9219 // cause it to handle NaNs incorrectly.
9220 if (!UnsafeFPMath &&
9221 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
9222 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9224 std::swap(LHS, RHS);
9226 Opcode = X86ISD::FMIN;
9229 // Converting this to a min would handle NaNs incorrectly.
9230 if (!UnsafeFPMath &&
9231 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9233 Opcode = X86ISD::FMIN;
9236 // Converting this to a min would handle both negative zeros and NaNs
9237 // incorrectly, but we can swap the operands to fix both.
9238 std::swap(LHS, RHS);
9242 Opcode = X86ISD::FMIN;
9246 // Converting this to a max would handle NaNs incorrectly.
9247 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9249 Opcode = X86ISD::FMAX;
9252 // Converting this to a max would handle comparisons between positive
9253 // and negative zero incorrectly, and swapping the operands would
9254 // cause it to handle NaNs incorrectly.
9255 if (!UnsafeFPMath &&
9256 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
9257 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9259 std::swap(LHS, RHS);
9261 Opcode = X86ISD::FMAX;
9264 // Converting this to a max would handle both negative zeros and NaNs
9265 // incorrectly, but we can swap the operands to fix both.
9266 std::swap(LHS, RHS);
9270 Opcode = X86ISD::FMAX;
9276 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9279 // If this is a select between two integer constants, try to do some
9281 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9282 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9283 // Don't do this for crazy integer types.
9284 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9285 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9286 // so that TrueC (the true value) is larger than FalseC.
9287 bool NeedsCondInvert = false;
9289 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9290 // Efficiently invertible.
9291 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9292 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9293 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9294 NeedsCondInvert = true;
9295 std::swap(TrueC, FalseC);
9298 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9299 if (FalseC->getAPIntValue() == 0 &&
9300 TrueC->getAPIntValue().isPowerOf2()) {
9301 if (NeedsCondInvert) // Invert the condition if needed.
9302 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9303 DAG.getConstant(1, Cond.getValueType()));
9305 // Zero extend the condition if needed.
9306 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9308 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9309 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9310 DAG.getConstant(ShAmt, MVT::i8));
9313 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9314 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9315 if (NeedsCondInvert) // Invert the condition if needed.
9316 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9317 DAG.getConstant(1, Cond.getValueType()));
9319 // Zero extend the condition if needed.
9320 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9321 FalseC->getValueType(0), Cond);
9322 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9323 SDValue(FalseC, 0));
9326 // Optimize cases that will turn into an LEA instruction. This requires
9327 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9328 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9329 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9330 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9332 bool isFastMultiplier = false;
9334 switch ((unsigned char)Diff) {
9336 case 1: // result = add base, cond
9337 case 2: // result = lea base( , cond*2)
9338 case 3: // result = lea base(cond, cond*2)
9339 case 4: // result = lea base( , cond*4)
9340 case 5: // result = lea base(cond, cond*4)
9341 case 8: // result = lea base( , cond*8)
9342 case 9: // result = lea base(cond, cond*8)
9343 isFastMultiplier = true;
9348 if (isFastMultiplier) {
9349 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9350 if (NeedsCondInvert) // Invert the condition if needed.
9351 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9352 DAG.getConstant(1, Cond.getValueType()));
9354 // Zero extend the condition if needed.
9355 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9357 // Scale the condition by the difference.
9359 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9360 DAG.getConstant(Diff, Cond.getValueType()));
9362 // Add the base if non-zero.
9363 if (FalseC->getAPIntValue() != 0)
9364 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9365 SDValue(FalseC, 0));
9375 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9376 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9377 TargetLowering::DAGCombinerInfo &DCI) {
9378 DebugLoc DL = N->getDebugLoc();
9380 // If the flag operand isn't dead, don't touch this CMOV.
9381 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9384 // If this is a select between two integer constants, try to do some
9385 // optimizations. Note that the operands are ordered the opposite of SELECT
9387 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9388 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9389 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9390 // larger than FalseC (the false value).
9391 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9393 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9394 CC = X86::GetOppositeBranchCondition(CC);
9395 std::swap(TrueC, FalseC);
9398 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9399 // This is efficient for any integer data type (including i8/i16) and
9401 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9402 SDValue Cond = N->getOperand(3);
9403 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9404 DAG.getConstant(CC, MVT::i8), Cond);
9406 // Zero extend the condition if needed.
9407 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9409 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9410 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9411 DAG.getConstant(ShAmt, MVT::i8));
9412 if (N->getNumValues() == 2) // Dead flag value?
9413 return DCI.CombineTo(N, Cond, SDValue());
9417 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9418 // for any integer data type, including i8/i16.
9419 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9420 SDValue Cond = N->getOperand(3);
9421 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9422 DAG.getConstant(CC, MVT::i8), Cond);
9424 // Zero extend the condition if needed.
9425 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9426 FalseC->getValueType(0), Cond);
9427 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9428 SDValue(FalseC, 0));
9430 if (N->getNumValues() == 2) // Dead flag value?
9431 return DCI.CombineTo(N, Cond, SDValue());
9435 // Optimize cases that will turn into an LEA instruction. This requires
9436 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9437 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9438 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9439 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9441 bool isFastMultiplier = false;
9443 switch ((unsigned char)Diff) {
9445 case 1: // result = add base, cond
9446 case 2: // result = lea base( , cond*2)
9447 case 3: // result = lea base(cond, cond*2)
9448 case 4: // result = lea base( , cond*4)
9449 case 5: // result = lea base(cond, cond*4)
9450 case 8: // result = lea base( , cond*8)
9451 case 9: // result = lea base(cond, cond*8)
9452 isFastMultiplier = true;
9457 if (isFastMultiplier) {
9458 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9459 SDValue Cond = N->getOperand(3);
9460 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9461 DAG.getConstant(CC, MVT::i8), Cond);
9462 // Zero extend the condition if needed.
9463 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9465 // Scale the condition by the difference.
9467 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9468 DAG.getConstant(Diff, Cond.getValueType()));
9470 // Add the base if non-zero.
9471 if (FalseC->getAPIntValue() != 0)
9472 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9473 SDValue(FalseC, 0));
9474 if (N->getNumValues() == 2) // Dead flag value?
9475 return DCI.CombineTo(N, Cond, SDValue());
9485 /// PerformMulCombine - Optimize a single multiply with constant into two
9486 /// in order to implement it with two cheaper instructions, e.g.
9487 /// LEA + SHL, LEA + LEA.
9488 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9489 TargetLowering::DAGCombinerInfo &DCI) {
9490 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9493 EVT VT = N->getValueType(0);
9497 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9500 uint64_t MulAmt = C->getZExtValue();
9501 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9504 uint64_t MulAmt1 = 0;
9505 uint64_t MulAmt2 = 0;
9506 if ((MulAmt % 9) == 0) {
9508 MulAmt2 = MulAmt / 9;
9509 } else if ((MulAmt % 5) == 0) {
9511 MulAmt2 = MulAmt / 5;
9512 } else if ((MulAmt % 3) == 0) {
9514 MulAmt2 = MulAmt / 3;
9517 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9518 DebugLoc DL = N->getDebugLoc();
9520 if (isPowerOf2_64(MulAmt2) &&
9521 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9522 // If second multiplifer is pow2, issue it first. We want the multiply by
9523 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9525 std::swap(MulAmt1, MulAmt2);
9528 if (isPowerOf2_64(MulAmt1))
9529 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9530 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9532 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9533 DAG.getConstant(MulAmt1, VT));
9535 if (isPowerOf2_64(MulAmt2))
9536 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9537 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9539 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9540 DAG.getConstant(MulAmt2, VT));
9542 // Do not add new nodes to DAG combiner worklist.
9543 DCI.CombineTo(N, NewMul, false);
9548 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9549 SDValue N0 = N->getOperand(0);
9550 SDValue N1 = N->getOperand(1);
9551 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9552 EVT VT = N0.getValueType();
9554 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9555 // since the result of setcc_c is all zero's or all ones.
9556 if (N1C && N0.getOpcode() == ISD::AND &&
9557 N0.getOperand(1).getOpcode() == ISD::Constant) {
9558 SDValue N00 = N0.getOperand(0);
9559 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9560 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9561 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9562 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9563 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9564 APInt ShAmt = N1C->getAPIntValue();
9565 Mask = Mask.shl(ShAmt);
9567 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9568 N00, DAG.getConstant(Mask, VT));
9575 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9577 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9578 const X86Subtarget *Subtarget) {
9579 EVT VT = N->getValueType(0);
9580 if (!VT.isVector() && VT.isInteger() &&
9581 N->getOpcode() == ISD::SHL)
9582 return PerformSHLCombine(N, DAG);
9584 // On X86 with SSE2 support, we can transform this to a vector shift if
9585 // all elements are shifted by the same amount. We can't do this in legalize
9586 // because the a constant vector is typically transformed to a constant pool
9587 // so we have no knowledge of the shift amount.
9588 if (!Subtarget->hasSSE2())
9591 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9594 SDValue ShAmtOp = N->getOperand(1);
9595 EVT EltVT = VT.getVectorElementType();
9596 DebugLoc DL = N->getDebugLoc();
9597 SDValue BaseShAmt = SDValue();
9598 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9599 unsigned NumElts = VT.getVectorNumElements();
9601 for (; i != NumElts; ++i) {
9602 SDValue Arg = ShAmtOp.getOperand(i);
9603 if (Arg.getOpcode() == ISD::UNDEF) continue;
9607 for (; i != NumElts; ++i) {
9608 SDValue Arg = ShAmtOp.getOperand(i);
9609 if (Arg.getOpcode() == ISD::UNDEF) continue;
9610 if (Arg != BaseShAmt) {
9614 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9615 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9616 SDValue InVec = ShAmtOp.getOperand(0);
9617 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9618 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9620 for (; i != NumElts; ++i) {
9621 SDValue Arg = InVec.getOperand(i);
9622 if (Arg.getOpcode() == ISD::UNDEF) continue;
9626 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9627 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9628 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9629 if (C->getZExtValue() == SplatIdx)
9630 BaseShAmt = InVec.getOperand(1);
9633 if (BaseShAmt.getNode() == 0)
9634 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9635 DAG.getIntPtrConstant(0));
9639 // The shift amount is an i32.
9640 if (EltVT.bitsGT(MVT::i32))
9641 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9642 else if (EltVT.bitsLT(MVT::i32))
9643 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9645 // The shift amount is identical so we can do a vector shift.
9646 SDValue ValOp = N->getOperand(0);
9647 switch (N->getOpcode()) {
9649 llvm_unreachable("Unknown shift opcode!");
9652 if (VT == MVT::v2i64)
9653 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9654 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9656 if (VT == MVT::v4i32)
9657 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9658 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9660 if (VT == MVT::v8i16)
9661 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9662 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9666 if (VT == MVT::v4i32)
9667 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9668 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9670 if (VT == MVT::v8i16)
9671 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9672 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9676 if (VT == MVT::v2i64)
9677 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9678 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9680 if (VT == MVT::v4i32)
9681 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9682 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9684 if (VT == MVT::v8i16)
9685 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9686 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9693 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9694 TargetLowering::DAGCombinerInfo &DCI,
9695 const X86Subtarget *Subtarget) {
9696 if (DCI.isBeforeLegalizeOps())
9699 EVT VT = N->getValueType(0);
9700 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
9703 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9704 SDValue N0 = N->getOperand(0);
9705 SDValue N1 = N->getOperand(1);
9706 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9708 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9710 if (!N0.hasOneUse() || !N1.hasOneUse())
9713 SDValue ShAmt0 = N0.getOperand(1);
9714 if (ShAmt0.getValueType() != MVT::i8)
9716 SDValue ShAmt1 = N1.getOperand(1);
9717 if (ShAmt1.getValueType() != MVT::i8)
9719 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9720 ShAmt0 = ShAmt0.getOperand(0);
9721 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9722 ShAmt1 = ShAmt1.getOperand(0);
9724 DebugLoc DL = N->getDebugLoc();
9725 unsigned Opc = X86ISD::SHLD;
9726 SDValue Op0 = N0.getOperand(0);
9727 SDValue Op1 = N1.getOperand(0);
9728 if (ShAmt0.getOpcode() == ISD::SUB) {
9730 std::swap(Op0, Op1);
9731 std::swap(ShAmt0, ShAmt1);
9734 unsigned Bits = VT.getSizeInBits();
9735 if (ShAmt1.getOpcode() == ISD::SUB) {
9736 SDValue Sum = ShAmt1.getOperand(0);
9737 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9738 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
9739 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
9740 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
9741 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
9742 return DAG.getNode(Opc, DL, VT,
9744 DAG.getNode(ISD::TRUNCATE, DL,
9747 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9748 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9750 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
9751 return DAG.getNode(Opc, DL, VT,
9752 N0.getOperand(0), N1.getOperand(0),
9753 DAG.getNode(ISD::TRUNCATE, DL,
9760 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9761 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9762 const X86Subtarget *Subtarget) {
9763 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9764 // the FP state in cases where an emms may be missing.
9765 // A preferable solution to the general problem is to figure out the right
9766 // places to insert EMMS. This qualifies as a quick hack.
9768 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9769 StoreSDNode *St = cast<StoreSDNode>(N);
9770 EVT VT = St->getValue().getValueType();
9771 if (VT.getSizeInBits() != 64)
9774 const Function *F = DAG.getMachineFunction().getFunction();
9775 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9776 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9777 && Subtarget->hasSSE2();
9778 if ((VT.isVector() ||
9779 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9780 isa<LoadSDNode>(St->getValue()) &&
9781 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9782 St->getChain().hasOneUse() && !St->isVolatile()) {
9783 SDNode* LdVal = St->getValue().getNode();
9785 int TokenFactorIndex = -1;
9786 SmallVector<SDValue, 8> Ops;
9787 SDNode* ChainVal = St->getChain().getNode();
9788 // Must be a store of a load. We currently handle two cases: the load
9789 // is a direct child, and it's under an intervening TokenFactor. It is
9790 // possible to dig deeper under nested TokenFactors.
9791 if (ChainVal == LdVal)
9792 Ld = cast<LoadSDNode>(St->getChain());
9793 else if (St->getValue().hasOneUse() &&
9794 ChainVal->getOpcode() == ISD::TokenFactor) {
9795 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9796 if (ChainVal->getOperand(i).getNode() == LdVal) {
9797 TokenFactorIndex = i;
9798 Ld = cast<LoadSDNode>(St->getValue());
9800 Ops.push_back(ChainVal->getOperand(i));
9804 if (!Ld || !ISD::isNormalLoad(Ld))
9807 // If this is not the MMX case, i.e. we are just turning i64 load/store
9808 // into f64 load/store, avoid the transformation if there are multiple
9809 // uses of the loaded value.
9810 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9813 DebugLoc LdDL = Ld->getDebugLoc();
9814 DebugLoc StDL = N->getDebugLoc();
9815 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9816 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9818 if (Subtarget->is64Bit() || F64IsLegal) {
9819 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9820 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9821 Ld->getBasePtr(), Ld->getSrcValue(),
9822 Ld->getSrcValueOffset(), Ld->isVolatile(),
9823 Ld->isNonTemporal(), Ld->getAlignment());
9824 SDValue NewChain = NewLd.getValue(1);
9825 if (TokenFactorIndex != -1) {
9826 Ops.push_back(NewChain);
9827 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9830 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9831 St->getSrcValue(), St->getSrcValueOffset(),
9832 St->isVolatile(), St->isNonTemporal(),
9833 St->getAlignment());
9836 // Otherwise, lower to two pairs of 32-bit loads / stores.
9837 SDValue LoAddr = Ld->getBasePtr();
9838 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9839 DAG.getConstant(4, MVT::i32));
9841 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9842 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9843 Ld->isVolatile(), Ld->isNonTemporal(),
9844 Ld->getAlignment());
9845 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9846 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9847 Ld->isVolatile(), Ld->isNonTemporal(),
9848 MinAlign(Ld->getAlignment(), 4));
9850 SDValue NewChain = LoLd.getValue(1);
9851 if (TokenFactorIndex != -1) {
9852 Ops.push_back(LoLd);
9853 Ops.push_back(HiLd);
9854 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9858 LoAddr = St->getBasePtr();
9859 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9860 DAG.getConstant(4, MVT::i32));
9862 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9863 St->getSrcValue(), St->getSrcValueOffset(),
9864 St->isVolatile(), St->isNonTemporal(),
9865 St->getAlignment());
9866 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9868 St->getSrcValueOffset() + 4,
9870 St->isNonTemporal(),
9871 MinAlign(St->getAlignment(), 4));
9872 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9877 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9878 /// X86ISD::FXOR nodes.
9879 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9880 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9881 // F[X]OR(0.0, x) -> x
9882 // F[X]OR(x, 0.0) -> x
9883 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9884 if (C->getValueAPF().isPosZero())
9885 return N->getOperand(1);
9886 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9887 if (C->getValueAPF().isPosZero())
9888 return N->getOperand(0);
9892 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9893 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9894 // FAND(0.0, x) -> 0.0
9895 // FAND(x, 0.0) -> 0.0
9896 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9897 if (C->getValueAPF().isPosZero())
9898 return N->getOperand(0);
9899 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9900 if (C->getValueAPF().isPosZero())
9901 return N->getOperand(1);
9905 static SDValue PerformBTCombine(SDNode *N,
9907 TargetLowering::DAGCombinerInfo &DCI) {
9908 // BT ignores high bits in the bit index operand.
9909 SDValue Op1 = N->getOperand(1);
9910 if (Op1.hasOneUse()) {
9911 unsigned BitWidth = Op1.getValueSizeInBits();
9912 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9913 APInt KnownZero, KnownOne;
9914 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
9915 !DCI.isBeforeLegalizeOps());
9916 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9917 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9918 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9919 DCI.CommitTargetLoweringOpt(TLO);
9924 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9925 SDValue Op = N->getOperand(0);
9926 if (Op.getOpcode() == ISD::BIT_CONVERT)
9927 Op = Op.getOperand(0);
9928 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9929 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9930 VT.getVectorElementType().getSizeInBits() ==
9931 OpVT.getVectorElementType().getSizeInBits()) {
9932 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9937 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9938 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9939 // (and (i32 x86isd::setcc_carry), 1)
9940 // This eliminates the zext. This transformation is necessary because
9941 // ISD::SETCC is always legalized to i8.
9942 DebugLoc dl = N->getDebugLoc();
9943 SDValue N0 = N->getOperand(0);
9944 EVT VT = N->getValueType(0);
9945 if (N0.getOpcode() == ISD::AND &&
9947 N0.getOperand(0).hasOneUse()) {
9948 SDValue N00 = N0.getOperand(0);
9949 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9951 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9952 if (!C || C->getZExtValue() != 1)
9954 return DAG.getNode(ISD::AND, dl, VT,
9955 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9956 N00.getOperand(0), N00.getOperand(1)),
9957 DAG.getConstant(1, VT));
9963 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9964 DAGCombinerInfo &DCI) const {
9965 SelectionDAG &DAG = DCI.DAG;
9966 switch (N->getOpcode()) {
9968 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9969 case ISD::EXTRACT_VECTOR_ELT:
9970 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
9971 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9972 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9973 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9976 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9977 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
9978 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9980 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9981 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9982 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9983 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9984 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9990 /// isTypeDesirableForOp - Return true if the target has native support for
9991 /// the specified value type and it is 'desirable' to use the type for the
9992 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
9993 /// instruction encodings are longer and some i16 instructions are slow.
9994 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
9995 if (!isTypeLegal(VT))
10004 case ISD::SIGN_EXTEND:
10005 case ISD::ZERO_EXTEND:
10006 case ISD::ANY_EXTEND:
10019 static bool MayFoldLoad(SDValue Op) {
10020 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
10023 static bool MayFoldIntoStore(SDValue Op) {
10024 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
10027 /// IsDesirableToPromoteOp - This method query the target whether it is
10028 /// beneficial for dag combiner to promote the specified node. If true, it
10029 /// should return the desired promotion type by reference.
10030 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
10031 EVT VT = Op.getValueType();
10032 if (VT != MVT::i16)
10035 bool Promote = false;
10036 bool Commute = false;
10037 switch (Op.getOpcode()) {
10040 LoadSDNode *LD = cast<LoadSDNode>(Op);
10041 // If the non-extending load has a single use and it's not live out, then it
10042 // might be folded.
10043 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
10044 Op.hasOneUse()*/) {
10045 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
10046 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
10047 // The only case where we'd want to promote LOAD (rather then it being
10048 // promoted as an operand is when it's only use is liveout.
10049 if (UI->getOpcode() != ISD::CopyToReg)
10056 case ISD::SIGN_EXTEND:
10057 case ISD::ZERO_EXTEND:
10058 case ISD::ANY_EXTEND:
10063 SDValue N0 = Op.getOperand(0);
10064 // Look out for (store (shl (load), x)).
10065 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
10078 SDValue N0 = Op.getOperand(0);
10079 SDValue N1 = Op.getOperand(1);
10080 if (!Commute && MayFoldLoad(N1))
10082 // Avoid disabling potential load folding opportunities.
10083 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
10085 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
10095 //===----------------------------------------------------------------------===//
10096 // X86 Inline Assembly Support
10097 //===----------------------------------------------------------------------===//
10099 static bool LowerToBSwap(CallInst *CI) {
10100 // FIXME: this should verify that we are targetting a 486 or better. If not,
10101 // we will turn this bswap into something that will be lowered to logical ops
10102 // instead of emitting the bswap asm. For now, we don't support 486 or lower
10103 // so don't worry about this.
10105 // Verify this is a simple bswap.
10106 if (CI->getNumArgOperands() != 1 ||
10107 CI->getType() != CI->getArgOperand(0)->getType() ||
10108 !CI->getType()->isIntegerTy())
10111 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10112 if (!Ty || Ty->getBitWidth() % 16 != 0)
10115 // Okay, we can do this xform, do so now.
10116 const Type *Tys[] = { Ty };
10117 Module *M = CI->getParent()->getParent()->getParent();
10118 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
10120 Value *Op = CI->getArgOperand(0);
10121 Op = CallInst::Create(Int, Op, CI->getName(), CI);
10123 CI->replaceAllUsesWith(Op);
10124 CI->eraseFromParent();
10128 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
10129 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10130 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
10132 std::string AsmStr = IA->getAsmString();
10134 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
10135 SmallVector<StringRef, 4> AsmPieces;
10136 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
10138 switch (AsmPieces.size()) {
10139 default: return false;
10141 AsmStr = AsmPieces[0];
10143 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
10146 if (AsmPieces.size() == 2 &&
10147 (AsmPieces[0] == "bswap" ||
10148 AsmPieces[0] == "bswapq" ||
10149 AsmPieces[0] == "bswapl") &&
10150 (AsmPieces[1] == "$0" ||
10151 AsmPieces[1] == "${0:q}")) {
10152 // No need to check constraints, nothing other than the equivalent of
10153 // "=r,0" would be valid here.
10154 return LowerToBSwap(CI);
10156 // rorw $$8, ${0:w} --> llvm.bswap.i16
10157 if (CI->getType()->isIntegerTy(16) &&
10158 AsmPieces.size() == 3 &&
10159 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
10160 AsmPieces[1] == "$$8," &&
10161 AsmPieces[2] == "${0:w}" &&
10162 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
10164 const std::string &Constraints = IA->getConstraintString();
10165 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
10166 std::sort(AsmPieces.begin(), AsmPieces.end());
10167 if (AsmPieces.size() == 4 &&
10168 AsmPieces[0] == "~{cc}" &&
10169 AsmPieces[1] == "~{dirflag}" &&
10170 AsmPieces[2] == "~{flags}" &&
10171 AsmPieces[3] == "~{fpsr}") {
10172 return LowerToBSwap(CI);
10177 if (CI->getType()->isIntegerTy(64) &&
10178 Constraints.size() >= 2 &&
10179 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
10180 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
10181 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
10182 SmallVector<StringRef, 4> Words;
10183 SplitString(AsmPieces[0], Words, " \t");
10184 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
10186 SplitString(AsmPieces[1], Words, " \t");
10187 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
10189 SplitString(AsmPieces[2], Words, " \t,");
10190 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
10191 Words[2] == "%edx") {
10192 return LowerToBSwap(CI);
10204 /// getConstraintType - Given a constraint letter, return the type of
10205 /// constraint it is for this target.
10206 X86TargetLowering::ConstraintType
10207 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
10208 if (Constraint.size() == 1) {
10209 switch (Constraint[0]) {
10221 return C_RegisterClass;
10229 return TargetLowering::getConstraintType(Constraint);
10232 /// LowerXConstraint - try to replace an X constraint, which matches anything,
10233 /// with another that has more specific requirements based on the type of the
10234 /// corresponding operand.
10235 const char *X86TargetLowering::
10236 LowerXConstraint(EVT ConstraintVT) const {
10237 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
10238 // 'f' like normal targets.
10239 if (ConstraintVT.isFloatingPoint()) {
10240 if (Subtarget->hasSSE2())
10242 if (Subtarget->hasSSE1())
10246 return TargetLowering::LowerXConstraint(ConstraintVT);
10249 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10250 /// vector. If it is invalid, don't add anything to Ops.
10251 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10253 std::vector<SDValue>&Ops,
10254 SelectionDAG &DAG) const {
10255 SDValue Result(0, 0);
10257 switch (Constraint) {
10260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10261 if (C->getZExtValue() <= 31) {
10262 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10268 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10269 if (C->getZExtValue() <= 63) {
10270 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10276 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10277 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
10278 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10285 if (C->getZExtValue() <= 255) {
10286 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10292 // 32-bit signed value
10293 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10294 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10295 C->getSExtValue())) {
10296 // Widen to 64 bits here to get it sign extended.
10297 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
10300 // FIXME gcc accepts some relocatable values here too, but only in certain
10301 // memory models; it's complicated.
10306 // 32-bit unsigned value
10307 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10308 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10309 C->getZExtValue())) {
10310 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10314 // FIXME gcc accepts some relocatable values here too, but only in certain
10315 // memory models; it's complicated.
10319 // Literal immediates are always ok.
10320 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
10321 // Widen to 64 bits here to get it sign extended.
10322 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10326 // In any sort of PIC mode addresses need to be computed at runtime by
10327 // adding in a register or some sort of table lookup. These can't
10328 // be used as immediates.
10329 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
10332 // If we are in non-pic codegen mode, we allow the address of a global (with
10333 // an optional displacement) to be used with 'i'.
10334 GlobalAddressSDNode *GA = 0;
10335 int64_t Offset = 0;
10337 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10339 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10340 Offset += GA->getOffset();
10342 } else if (Op.getOpcode() == ISD::ADD) {
10343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10344 Offset += C->getZExtValue();
10345 Op = Op.getOperand(0);
10348 } else if (Op.getOpcode() == ISD::SUB) {
10349 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10350 Offset += -C->getZExtValue();
10351 Op = Op.getOperand(0);
10356 // Otherwise, this isn't something we can handle, reject it.
10360 const GlobalValue *GV = GA->getGlobal();
10361 // If we require an extra load to get this address, as in PIC mode, we
10362 // can't accept it.
10363 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10364 getTargetMachine())))
10367 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
10368 GA->getValueType(0), Offset);
10373 if (Result.getNode()) {
10374 Ops.push_back(Result);
10377 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10380 std::vector<unsigned> X86TargetLowering::
10381 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10383 if (Constraint.size() == 1) {
10384 // FIXME: not handling fp-stack yet!
10385 switch (Constraint[0]) { // GCC X86 Constraint Letters
10386 default: break; // Unknown constraint letter
10387 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10388 if (Subtarget->is64Bit()) {
10389 if (VT == MVT::i32)
10390 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10391 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10392 X86::R10D,X86::R11D,X86::R12D,
10393 X86::R13D,X86::R14D,X86::R15D,
10394 X86::EBP, X86::ESP, 0);
10395 else if (VT == MVT::i16)
10396 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10397 X86::SI, X86::DI, X86::R8W,X86::R9W,
10398 X86::R10W,X86::R11W,X86::R12W,
10399 X86::R13W,X86::R14W,X86::R15W,
10400 X86::BP, X86::SP, 0);
10401 else if (VT == MVT::i8)
10402 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10403 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10404 X86::R10B,X86::R11B,X86::R12B,
10405 X86::R13B,X86::R14B,X86::R15B,
10406 X86::BPL, X86::SPL, 0);
10408 else if (VT == MVT::i64)
10409 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10410 X86::RSI, X86::RDI, X86::R8, X86::R9,
10411 X86::R10, X86::R11, X86::R12,
10412 X86::R13, X86::R14, X86::R15,
10413 X86::RBP, X86::RSP, 0);
10417 // 32-bit fallthrough
10418 case 'Q': // Q_REGS
10419 if (VT == MVT::i32)
10420 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10421 else if (VT == MVT::i16)
10422 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10423 else if (VT == MVT::i8)
10424 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10425 else if (VT == MVT::i64)
10426 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10431 return std::vector<unsigned>();
10434 std::pair<unsigned, const TargetRegisterClass*>
10435 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10437 // First, see if this is a constraint that directly corresponds to an LLVM
10439 if (Constraint.size() == 1) {
10440 // GCC Constraint Letters
10441 switch (Constraint[0]) {
10443 case 'r': // GENERAL_REGS
10444 case 'l': // INDEX_REGS
10446 return std::make_pair(0U, X86::GR8RegisterClass);
10447 if (VT == MVT::i16)
10448 return std::make_pair(0U, X86::GR16RegisterClass);
10449 if (VT == MVT::i32 || !Subtarget->is64Bit())
10450 return std::make_pair(0U, X86::GR32RegisterClass);
10451 return std::make_pair(0U, X86::GR64RegisterClass);
10452 case 'R': // LEGACY_REGS
10454 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10455 if (VT == MVT::i16)
10456 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10457 if (VT == MVT::i32 || !Subtarget->is64Bit())
10458 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10459 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10460 case 'f': // FP Stack registers.
10461 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10462 // value to the correct fpstack register class.
10463 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10464 return std::make_pair(0U, X86::RFP32RegisterClass);
10465 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10466 return std::make_pair(0U, X86::RFP64RegisterClass);
10467 return std::make_pair(0U, X86::RFP80RegisterClass);
10468 case 'y': // MMX_REGS if MMX allowed.
10469 if (!Subtarget->hasMMX()) break;
10470 return std::make_pair(0U, X86::VR64RegisterClass);
10471 case 'Y': // SSE_REGS if SSE2 allowed
10472 if (!Subtarget->hasSSE2()) break;
10474 case 'x': // SSE_REGS if SSE1 allowed
10475 if (!Subtarget->hasSSE1()) break;
10477 switch (VT.getSimpleVT().SimpleTy) {
10479 // Scalar SSE types.
10482 return std::make_pair(0U, X86::FR32RegisterClass);
10485 return std::make_pair(0U, X86::FR64RegisterClass);
10493 return std::make_pair(0U, X86::VR128RegisterClass);
10499 // Use the default implementation in TargetLowering to convert the register
10500 // constraint into a member of a register class.
10501 std::pair<unsigned, const TargetRegisterClass*> Res;
10502 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10504 // Not found as a standard register?
10505 if (Res.second == 0) {
10506 // Map st(0) -> st(7) -> ST0
10507 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10508 tolower(Constraint[1]) == 's' &&
10509 tolower(Constraint[2]) == 't' &&
10510 Constraint[3] == '(' &&
10511 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10512 Constraint[5] == ')' &&
10513 Constraint[6] == '}') {
10515 Res.first = X86::ST0+Constraint[4]-'0';
10516 Res.second = X86::RFP80RegisterClass;
10520 // GCC allows "st(0)" to be called just plain "st".
10521 if (StringRef("{st}").equals_lower(Constraint)) {
10522 Res.first = X86::ST0;
10523 Res.second = X86::RFP80RegisterClass;
10528 if (StringRef("{flags}").equals_lower(Constraint)) {
10529 Res.first = X86::EFLAGS;
10530 Res.second = X86::CCRRegisterClass;
10534 // 'A' means EAX + EDX.
10535 if (Constraint == "A") {
10536 Res.first = X86::EAX;
10537 Res.second = X86::GR32_ADRegisterClass;
10543 // Otherwise, check to see if this is a register class of the wrong value
10544 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10545 // turn into {ax},{dx}.
10546 if (Res.second->hasType(VT))
10547 return Res; // Correct type already, nothing to do.
10549 // All of the single-register GCC register classes map their values onto
10550 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10551 // really want an 8-bit or 32-bit register, map to the appropriate register
10552 // class and return the appropriate register.
10553 if (Res.second == X86::GR16RegisterClass) {
10554 if (VT == MVT::i8) {
10555 unsigned DestReg = 0;
10556 switch (Res.first) {
10558 case X86::AX: DestReg = X86::AL; break;
10559 case X86::DX: DestReg = X86::DL; break;
10560 case X86::CX: DestReg = X86::CL; break;
10561 case X86::BX: DestReg = X86::BL; break;
10564 Res.first = DestReg;
10565 Res.second = X86::GR8RegisterClass;
10567 } else if (VT == MVT::i32) {
10568 unsigned DestReg = 0;
10569 switch (Res.first) {
10571 case X86::AX: DestReg = X86::EAX; break;
10572 case X86::DX: DestReg = X86::EDX; break;
10573 case X86::CX: DestReg = X86::ECX; break;
10574 case X86::BX: DestReg = X86::EBX; break;
10575 case X86::SI: DestReg = X86::ESI; break;
10576 case X86::DI: DestReg = X86::EDI; break;
10577 case X86::BP: DestReg = X86::EBP; break;
10578 case X86::SP: DestReg = X86::ESP; break;
10581 Res.first = DestReg;
10582 Res.second = X86::GR32RegisterClass;
10584 } else if (VT == MVT::i64) {
10585 unsigned DestReg = 0;
10586 switch (Res.first) {
10588 case X86::AX: DestReg = X86::RAX; break;
10589 case X86::DX: DestReg = X86::RDX; break;
10590 case X86::CX: DestReg = X86::RCX; break;
10591 case X86::BX: DestReg = X86::RBX; break;
10592 case X86::SI: DestReg = X86::RSI; break;
10593 case X86::DI: DestReg = X86::RDI; break;
10594 case X86::BP: DestReg = X86::RBP; break;
10595 case X86::SP: DestReg = X86::RSP; break;
10598 Res.first = DestReg;
10599 Res.second = X86::GR64RegisterClass;
10602 } else if (Res.second == X86::FR32RegisterClass ||
10603 Res.second == X86::FR64RegisterClass ||
10604 Res.second == X86::VR128RegisterClass) {
10605 // Handle references to XMM physical registers that got mapped into the
10606 // wrong class. This can happen with constraints like {xmm0} where the
10607 // target independent register mapper will just pick the first match it can
10608 // find, ignoring the required type.
10609 if (VT == MVT::f32)
10610 Res.second = X86::FR32RegisterClass;
10611 else if (VT == MVT::f64)
10612 Res.second = X86::FR64RegisterClass;
10613 else if (X86::VR128RegisterClass->hasType(VT))
10614 Res.second = X86::VR128RegisterClass;