1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 EVT VT = Vec.getValueType();
103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
105 EVT ElVT = VT.getVectorElementType();
106 EVT ResultVT = Result.getValueType();
108 // Insert the relevant 128 bits.
109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
111 // This is the index of the first element of the 128-bit chunk
113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
122 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
123 /// instructions. This is used because creating CONCAT_VECTOR nodes of
124 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
125 /// large BUILD_VECTORS.
126 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
127 unsigned NumElems, SelectionDAG &DAG,
129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
133 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
135 bool is64Bit = Subtarget->is64Bit();
137 if (Subtarget->isTargetEnvMacho()) {
139 return new X8664_MachoTargetObjectFile();
140 return new TargetLoweringObjectFileMachO();
143 if (Subtarget->isTargetELF())
144 return new TargetLoweringObjectFileELF();
145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
146 return new TargetLoweringObjectFileCOFF();
147 llvm_unreachable("unknown subtarget type");
150 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
151 : TargetLowering(TM, createTLOF(TM)) {
152 Subtarget = &TM.getSubtarget<X86Subtarget>();
153 X86ScalarSSEf64 = Subtarget->hasSSE2();
154 X86ScalarSSEf32 = Subtarget->hasSSE1();
155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
157 RegInfo = TM.getRegisterInfo();
158 TD = getTargetData();
160 // Set up the TargetLowering object.
161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
163 // X86 is weird, it always uses i8 for shift amounts and setcc results.
164 setBooleanContents(ZeroOrOneBooleanContent);
165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
168 // For 64-bit since we have so many registers use the ILP scheduler, for
169 // 32-bit code use the register pressure specific scheduling.
170 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
171 if (Subtarget->is64Bit())
172 setSchedulingPreference(Sched::ILP);
173 else if (Subtarget->isAtom())
174 setSchedulingPreference(Sched::Hybrid);
176 setSchedulingPreference(Sched::RegPressure);
177 setStackPointerRegisterToSaveRestore(X86StackPtr);
179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
180 // Setup Windows compiler runtime calls.
181 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
183 setLibcallName(RTLIB::SREM_I64, "_allrem");
184 setLibcallName(RTLIB::UREM_I64, "_aullrem");
185 setLibcallName(RTLIB::MUL_I64, "_allmul");
186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
192 // The _ftol2 runtime function has an unusual calling conv, which
193 // is modeled by a special pseudo-instruction.
194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
200 if (Subtarget->isTargetDarwin()) {
201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
202 setUseUnderscoreSetJmp(false);
203 setUseUnderscoreLongJmp(false);
204 } else if (Subtarget->isTargetMingw()) {
205 // MS runtime is weird: it exports _setjmp, but longjmp!
206 setUseUnderscoreSetJmp(true);
207 setUseUnderscoreLongJmp(false);
209 setUseUnderscoreSetJmp(true);
210 setUseUnderscoreLongJmp(true);
213 // Set up the register classes.
214 addRegisterClass(MVT::i8, &X86::GR8RegClass);
215 addRegisterClass(MVT::i16, &X86::GR16RegClass);
216 addRegisterClass(MVT::i32, &X86::GR32RegClass);
217 if (Subtarget->is64Bit())
218 addRegisterClass(MVT::i64, &X86::GR64RegClass);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
222 // We don't accept any truncstore of integer registers.
223 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
224 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
226 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
228 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
230 // SETOEQ and SETUNE require checking two conditions.
231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
247 } else if (!TM.Options.UseSoftFloat) {
248 // We have an algorithm for SSE2->double, and we turn this into a
249 // 64-bit FILD followed by conditional FADD for other targets.
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 // We have an algorithm for SSE2, and we turn this into a 64-bit
252 // FILD for other targets.
253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
261 if (!TM.Options.UseSoftFloat) {
262 // SSE has no i16 to fp conversion, only i32
263 if (X86ScalarSSEf32) {
264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
265 // f32 and f64 cases are Legal, f80 case is not
266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
277 // are Legal, f80 is custom lowered.
278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
286 if (X86ScalarSSEf32) {
287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
288 // f32 and f64 cases are Legal, f80 case is not
289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 // Handle FP_TO_UINT by promoting the destination to a larger signed
297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
301 if (Subtarget->is64Bit()) {
302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
304 } else if (!TM.Options.UseSoftFloat) {
305 // Since AVX is a superset of SSE3, only check for SSE here.
306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
307 // Expand FP_TO_UINT into a select.
308 // FIXME: We would like to use a Custom expander here eventually to do
309 // the optimal thing for SSE vs. the default expansion in the legalizer.
310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
312 // With SSE3 we can use fisttpll to convert to a signed i64; without
313 // SSE, we're stuck with a fistpll.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
317 if (isTargetFTOL()) {
318 // Use the _ftol2 runtime function, which has a pseudo-instruction
319 // to handle its weird calling convention.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
323 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
324 if (!X86ScalarSSEf64) {
325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
329 // Without SSE, i64->f64 goes through memory.
330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
334 // Scalar integer divide and remainder are lowered to use operations that
335 // produce two results, to match the available instructions. This exposes
336 // the two-result form to trivial CSE, which is able to combine x/y and x%y
337 // into a single instruction.
339 // Scalar integer multiply-high is also lowered to use two-result
340 // operations, to match the available instructions. However, plain multiply
341 // (low) operations are left as Legal, as there are single-result
342 // instructions for this in x86. Using the two-result multiply instructions
343 // when both high and low results are needed must be arranged by dagcombine.
344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
346 setOperationAction(ISD::MULHS, VT, Expand);
347 setOperationAction(ISD::MULHU, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
354 setOperationAction(ISD::ADDC, VT, Custom);
355 setOperationAction(ISD::ADDE, VT, Custom);
356 setOperationAction(ISD::SUBC, VT, Custom);
357 setOperationAction(ISD::SUBE, VT, Custom);
360 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
361 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
362 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
364 if (Subtarget->is64Bit())
365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
370 setOperationAction(ISD::FREM , MVT::f32 , Expand);
371 setOperationAction(ISD::FREM , MVT::f64 , Expand);
372 setOperationAction(ISD::FREM , MVT::f80 , Expand);
373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
375 // Promote the i8 variants and force them on up to i32 which has a shorter
377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
381 if (Subtarget->hasBMI()) {
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
393 if (Subtarget->hasLZCNT()) {
394 // When promoting the i8 variants, force them to i32 for a shorter
396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
417 if (Subtarget->hasPOPCNT()) {
418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
430 // These should be promoted to a larger select which is supported.
431 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
432 // X86 wants to expand cmov itself.
433 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
434 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
435 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
436 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
437 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
438 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
440 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
441 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
442 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
443 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
444 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
445 if (Subtarget->is64Bit()) {
446 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
460 if (Subtarget->is64Bit()) {
461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
471 if (Subtarget->is64Bit()) {
472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
477 if (Subtarget->hasSSE1())
478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
483 // On X86 and X86-64, atomic operations are lowered to locked instructions.
484 // Locked instructions, in turn, have implicit fence semantics (all memory
485 // operations are flushed before issuing the locked instruction, and they
486 // are not buffered), so we can fold away the common pattern of
487 // fence-atomic-fence.
488 setShouldFoldAtomicFences(true);
490 // Expand certain atomics
491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
498 if (!Subtarget->is64Bit()) {
499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
509 if (Subtarget->hasCmpxchg16b()) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
513 // FIXME - use subtarget debug flags
514 if (!Subtarget->isTargetDarwin() &&
515 !Subtarget->isTargetELF() &&
516 !Subtarget->isTargetCygMing()) {
517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
524 if (Subtarget->is64Bit()) {
525 setExceptionPointerRegister(X86::RAX);
526 setExceptionSelectorRegister(X86::RDX);
528 setExceptionPointerRegister(X86::EAX);
529 setExceptionSelectorRegister(X86::EDX);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
537 setOperationAction(ISD::TRAP, MVT::Other, Legal);
539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
540 setOperationAction(ISD::VASTART , MVT::Other, Custom);
541 setOperationAction(ISD::VAEND , MVT::Other, Expand);
542 if (Subtarget->is64Bit()) {
543 setOperationAction(ISD::VAARG , MVT::Other, Custom);
544 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
546 setOperationAction(ISD::VAARG , MVT::Other, Expand);
547 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
555 MVT::i64 : MVT::i32, Custom);
556 else if (TM.Options.EnableSegmentedStacks)
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Expand);
563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
564 // f32 and f64 use SSE.
565 // Set up the FP register classes.
566 addRegisterClass(MVT::f32, &X86::FR32RegClass);
567 addRegisterClass(MVT::f64, &X86::FR64RegClass);
569 // Use ANDPD to simulate FABS.
570 setOperationAction(ISD::FABS , MVT::f64, Custom);
571 setOperationAction(ISD::FABS , MVT::f32, Custom);
573 // Use XORP to simulate FNEG.
574 setOperationAction(ISD::FNEG , MVT::f64, Custom);
575 setOperationAction(ISD::FNEG , MVT::f32, Custom);
577 // Use ANDPD and ORPD to simulate FCOPYSIGN.
578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
581 // Lower this to FGETSIGNx86 plus an AND.
582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
585 // We don't support sin/cos/fmod
586 setOperationAction(ISD::FSIN , MVT::f64, Expand);
587 setOperationAction(ISD::FCOS , MVT::f64, Expand);
588 setOperationAction(ISD::FSIN , MVT::f32, Expand);
589 setOperationAction(ISD::FCOS , MVT::f32, Expand);
591 // Expand FP immediates into loads from the stack, except for the special
593 addLegalFPImmediate(APFloat(+0.0)); // xorpd
594 addLegalFPImmediate(APFloat(+0.0f)); // xorps
595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
596 // Use SSE for f32, x87 for f64.
597 // Set up the FP register classes.
598 addRegisterClass(MVT::f32, &X86::FR32RegClass);
599 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
601 // Use ANDPS to simulate FABS.
602 setOperationAction(ISD::FABS , MVT::f32, Custom);
604 // Use XORP to simulate FNEG.
605 setOperationAction(ISD::FNEG , MVT::f32, Custom);
607 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
609 // Use ANDPS and ORPS to simulate FCOPYSIGN.
610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
613 // We don't support sin/cos/fmod
614 setOperationAction(ISD::FSIN , MVT::f32, Expand);
615 setOperationAction(ISD::FCOS , MVT::f32, Expand);
617 // Special cases we handle for FP constants.
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 addLegalFPImmediate(APFloat(+0.0)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
624 if (!TM.Options.UnsafeFPMath) {
625 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
626 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
628 } else if (!TM.Options.UseSoftFloat) {
629 // f32 and f64 in x87.
630 // Set up the FP register classes.
631 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
632 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
634 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
635 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
639 if (!TM.Options.UnsafeFPMath) {
640 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
643 addLegalFPImmediate(APFloat(+0.0)); // FLD0
644 addLegalFPImmediate(APFloat(+1.0)); // FLD1
645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
653 // We don't support FMA.
654 setOperationAction(ISD::FMA, MVT::f64, Expand);
655 setOperationAction(ISD::FMA, MVT::f32, Expand);
657 // Long double always uses X87.
658 if (!TM.Options.UseSoftFloat) {
659 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
660 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
664 addLegalFPImmediate(TmpFlt); // FLD0
666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
669 APFloat TmpFlt2(+1.0);
670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
672 addLegalFPImmediate(TmpFlt2); // FLD1
673 TmpFlt2.changeSign();
674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
677 if (!TM.Options.UnsafeFPMath) {
678 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
679 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
683 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
685 setOperationAction(ISD::FRINT, MVT::f80, Expand);
686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
687 setOperationAction(ISD::FMA, MVT::f80, Expand);
690 // Always use a library call for pow.
691 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
692 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
693 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
695 setOperationAction(ISD::FLOG, MVT::f80, Expand);
696 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
697 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
698 setOperationAction(ISD::FEXP, MVT::f80, Expand);
699 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
701 // First set operation action for all vector types to either promote
702 // (for widening) or expand (for scalarization). Then we will selectively
703 // turn on ones that can be effectively codegen'd.
704 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
705 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
763 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
764 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
765 setTruncStoreAction((MVT::SimpleValueType)VT,
766 (MVT::SimpleValueType)InnerVT, Expand);
767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
773 // with -msoft-float, disable use of MMX as well.
774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
776 // No operations on x86mmx supported, everything uses intrinsics.
779 // MMX-sized vectors (other than x86mmx) are expected to be expanded
780 // into smaller operations.
781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
785 setOperationAction(ISD::AND, MVT::v8i8, Expand);
786 setOperationAction(ISD::AND, MVT::v4i16, Expand);
787 setOperationAction(ISD::AND, MVT::v2i32, Expand);
788 setOperationAction(ISD::AND, MVT::v1i64, Expand);
789 setOperationAction(ISD::OR, MVT::v8i8, Expand);
790 setOperationAction(ISD::OR, MVT::v4i16, Expand);
791 setOperationAction(ISD::OR, MVT::v2i32, Expand);
792 setOperationAction(ISD::OR, MVT::v1i64, Expand);
793 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
794 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
795 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
796 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
814 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
832 // registers cannot be used even for integer operations.
833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
838 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
839 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
840 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
841 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
842 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
843 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
844 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
845 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
846 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
848 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
874 EVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR,
882 VT.getSimpleVT().SimpleTy, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE,
884 VT.getSimpleVT().SimpleTy, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
886 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
902 for (int i = MVT::v16i8; i != MVT::v2i64; i++) {
903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
906 // Do not attempt to promote non-128-bit vectors
907 if (!VT.is128BitVector())
910 setOperationAction(ISD::AND, SVT, Promote);
911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
912 setOperationAction(ISD::OR, SVT, Promote);
913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
914 setOperationAction(ISD::XOR, SVT, Promote);
915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
916 setOperationAction(ISD::LOAD, SVT, Promote);
917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
918 setOperationAction(ISD::SELECT, SVT, Promote);
919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
922 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
924 // Custom lower v2i64 and v2f64 selects.
925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
934 if (Subtarget->hasSSE41()) {
935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
936 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
938 setOperationAction(ISD::FRINT, MVT::f32, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
943 setOperationAction(ISD::FRINT, MVT::f64, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
946 // FIXME: Do we need to handle scalar-to-vector here?
947 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
955 // i8 and i16 vectors are custom , because the source register and source
956 // source memory operand types are not the same width. f32 vectors are
957 // custom since the immediate controlling the insert encodes additional
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
969 // FIXME: these should be Legal but thats only for the case where
970 // the index is constant. For now custom expand to deal with that.
971 if (Subtarget->is64Bit()) {
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
977 if (Subtarget->hasSSE2()) {
978 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
981 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
985 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
987 if (Subtarget->hasAVX2()) {
988 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
989 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
991 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
996 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
997 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
999 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1006 if (Subtarget->hasSSE42())
1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1069 if (Subtarget->hasAVX2()) {
1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1083 // Don't lower v32i8 because there is no 128-bit byte mul
1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1108 // Don't lower v32i8 because there is no 128-bit byte mul
1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1119 // Custom lower several nodes for 256-bit types.
1120 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1121 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1125 // Extract subvector is special because the value type
1126 // (result) is 128-bit but the source is 256-bit wide.
1127 if (VT.is128BitVector())
1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1130 // Do not attempt to custom lower other non-256-bit vectors
1131 if (!VT.is256BitVector())
1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1143 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1147 // Do not attempt to promote non-256-bit vectors
1148 if (!VT.is256BitVector())
1151 setOperationAction(ISD::AND, SVT, Promote);
1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1153 setOperationAction(ISD::OR, SVT, Promote);
1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1155 setOperationAction(ISD::XOR, SVT, Promote);
1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1157 setOperationAction(ISD::LOAD, SVT, Promote);
1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1159 setOperationAction(ISD::SELECT, SVT, Promote);
1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1165 // of this type with custom code.
1166 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1167 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1172 // We want to custom lower some of our intrinsics.
1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1177 // handle type legalization for these operations here.
1179 // FIXME: We really should do custom legalization for addition and
1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1181 // than generic legalization for 64-bit multiplication-with-overflow, though.
1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1183 // Add/Sub/Mul with overflow operations are custom lowered.
1185 setOperationAction(ISD::SADDO, VT, Custom);
1186 setOperationAction(ISD::UADDO, VT, Custom);
1187 setOperationAction(ISD::SSUBO, VT, Custom);
1188 setOperationAction(ISD::USUBO, VT, Custom);
1189 setOperationAction(ISD::SMULO, VT, Custom);
1190 setOperationAction(ISD::UMULO, VT, Custom);
1193 // There are no 8-bit 3-address imul/mul instructions
1194 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1195 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1197 if (!Subtarget->is64Bit()) {
1198 // These libcalls are not available in 32-bit.
1199 setLibcallName(RTLIB::SHL_I128, 0);
1200 setLibcallName(RTLIB::SRL_I128, 0);
1201 setLibcallName(RTLIB::SRA_I128, 0);
1204 // We have target-specific dag combine patterns for the following nodes:
1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1207 setTargetDAGCombine(ISD::VSELECT);
1208 setTargetDAGCombine(ISD::SELECT);
1209 setTargetDAGCombine(ISD::SHL);
1210 setTargetDAGCombine(ISD::SRA);
1211 setTargetDAGCombine(ISD::SRL);
1212 setTargetDAGCombine(ISD::OR);
1213 setTargetDAGCombine(ISD::AND);
1214 setTargetDAGCombine(ISD::ADD);
1215 setTargetDAGCombine(ISD::FADD);
1216 setTargetDAGCombine(ISD::FSUB);
1217 setTargetDAGCombine(ISD::SUB);
1218 setTargetDAGCombine(ISD::LOAD);
1219 setTargetDAGCombine(ISD::STORE);
1220 setTargetDAGCombine(ISD::ZERO_EXTEND);
1221 setTargetDAGCombine(ISD::ANY_EXTEND);
1222 setTargetDAGCombine(ISD::SIGN_EXTEND);
1223 setTargetDAGCombine(ISD::TRUNCATE);
1224 setTargetDAGCombine(ISD::UINT_TO_FP);
1225 setTargetDAGCombine(ISD::SINT_TO_FP);
1226 setTargetDAGCombine(ISD::SETCC);
1227 setTargetDAGCombine(ISD::FP_TO_SINT);
1228 if (Subtarget->is64Bit())
1229 setTargetDAGCombine(ISD::MUL);
1230 if (Subtarget->hasBMI())
1231 setTargetDAGCombine(ISD::XOR);
1233 computeRegisterProperties();
1235 // On Darwin, -Os means optimize for size without hurting performance,
1236 // do not reduce the limit.
1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1243 setPrefLoopAlignment(4); // 2^4 bytes.
1244 benefitFromCodePlacementOpt = true;
1246 setPrefFunctionAlignment(4); // 2^4 bytes.
1250 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1251 if (!VT.isVector()) return MVT::i8;
1252 return VT.changeVectorElementTypeToInteger();
1256 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1257 /// the desired ByVal argument alignment.
1258 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262 if (VTy->getBitWidth() == 128)
1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1265 unsigned EltAlign = 0;
1266 getMaxByValAlign(ATy->getElementType(), EltAlign);
1267 if (EltAlign > MaxAlign)
1268 MaxAlign = EltAlign;
1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1271 unsigned EltAlign = 0;
1272 getMaxByValAlign(STy->getElementType(i), EltAlign);
1273 if (EltAlign > MaxAlign)
1274 MaxAlign = EltAlign;
1281 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1282 /// function arguments in the caller parameter area. For X86, aggregates
1283 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1284 /// are at 4-byte boundaries.
1285 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1286 if (Subtarget->is64Bit()) {
1287 // Max of 8 and alignment of type.
1288 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1295 if (Subtarget->hasSSE1())
1296 getMaxByValAlign(Ty, Align);
1300 /// getOptimalMemOpType - Returns the target specific optimal type for load
1301 /// and store operations as a result of memset, memcpy, and memmove
1302 /// lowering. If DstAlign is zero that means it's safe to destination
1303 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1304 /// means there isn't a need to check it against alignment requirement,
1305 /// probably because the source does not need to be loaded. If
1306 /// 'IsZeroVal' is true, that means it's safe to return a
1307 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1308 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1309 /// constant so it does not need to be loaded.
1310 /// It returns EVT::Other if the type should be determined using generic
1311 /// target-independent logic.
1313 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1314 unsigned DstAlign, unsigned SrcAlign,
1317 MachineFunction &MF) const {
1318 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1319 // linux. This is because the stack realignment code can't handle certain
1320 // cases like PR2962. This should be removed when PR2962 is fixed.
1321 const Function *F = MF.getFunction();
1323 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1325 (Subtarget->isUnalignedMemAccessFast() ||
1326 ((DstAlign == 0 || DstAlign >= 16) &&
1327 (SrcAlign == 0 || SrcAlign >= 16))) &&
1328 Subtarget->getStackAlignment() >= 16) {
1329 if (Subtarget->getStackAlignment() >= 32) {
1330 if (Subtarget->hasAVX2())
1332 if (Subtarget->hasAVX())
1335 if (Subtarget->hasSSE2())
1337 if (Subtarget->hasSSE1())
1339 } else if (!MemcpyStrSrc && Size >= 8 &&
1340 !Subtarget->is64Bit() &&
1341 Subtarget->getStackAlignment() >= 8 &&
1342 Subtarget->hasSSE2()) {
1343 // Do not use f64 to lower memcpy if source is string constant. It's
1344 // better to use i32 to avoid the loads.
1348 if (Subtarget->is64Bit() && Size >= 8)
1353 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1354 /// current function. The returned value is a member of the
1355 /// MachineJumpTableInfo::JTEntryKind enum.
1356 unsigned X86TargetLowering::getJumpTableEncoding() const {
1357 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1359 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1360 Subtarget->isPICStyleGOT())
1361 return MachineJumpTableInfo::EK_Custom32;
1363 // Otherwise, use the normal jump table encoding heuristics.
1364 return TargetLowering::getJumpTableEncoding();
1368 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1369 const MachineBasicBlock *MBB,
1370 unsigned uid,MCContext &Ctx) const{
1371 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1372 Subtarget->isPICStyleGOT());
1373 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1375 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1376 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1379 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1381 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1382 SelectionDAG &DAG) const {
1383 if (!Subtarget->is64Bit())
1384 // This doesn't have DebugLoc associated with it, but is not really the
1385 // same as a Register.
1386 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1390 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1391 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1393 const MCExpr *X86TargetLowering::
1394 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1395 MCContext &Ctx) const {
1396 // X86-64 uses RIP relative addressing based on the jump table label.
1397 if (Subtarget->isPICStyleRIPRel())
1398 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1400 // Otherwise, the reference is relative to the PIC base.
1401 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1404 // FIXME: Why this routine is here? Move to RegInfo!
1405 std::pair<const TargetRegisterClass*, uint8_t>
1406 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1407 const TargetRegisterClass *RRC = 0;
1409 switch (VT.getSimpleVT().SimpleTy) {
1411 return TargetLowering::findRepresentativeClass(VT);
1412 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1413 RRC = Subtarget->is64Bit() ?
1414 (const TargetRegisterClass*)&X86::GR64RegClass :
1415 (const TargetRegisterClass*)&X86::GR32RegClass;
1418 RRC = &X86::VR64RegClass;
1420 case MVT::f32: case MVT::f64:
1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1422 case MVT::v4f32: case MVT::v2f64:
1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1425 RRC = &X86::VR128RegClass;
1428 return std::make_pair(RRC, Cost);
1431 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1432 unsigned &Offset) const {
1433 if (!Subtarget->isTargetLinux())
1436 if (Subtarget->is64Bit()) {
1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1452 //===----------------------------------------------------------------------===//
1453 // Return Value Calling Convention Implementation
1454 //===----------------------------------------------------------------------===//
1456 #include "X86GenCallingConv.inc"
1459 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1460 MachineFunction &MF, bool isVarArg,
1461 const SmallVectorImpl<ISD::OutputArg> &Outs,
1462 LLVMContext &Context) const {
1463 SmallVector<CCValAssign, 16> RVLocs;
1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1466 return CCInfo.CheckReturn(Outs, RetCC_X86);
1470 X86TargetLowering::LowerReturn(SDValue Chain,
1471 CallingConv::ID CallConv, bool isVarArg,
1472 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<SDValue> &OutVals,
1474 DebugLoc dl, SelectionDAG &DAG) const {
1475 MachineFunction &MF = DAG.getMachineFunction();
1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1478 SmallVector<CCValAssign, 16> RVLocs;
1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1480 RVLocs, *DAG.getContext());
1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1483 // Add the regs to the liveout set for the function.
1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1485 for (unsigned i = 0; i != RVLocs.size(); ++i)
1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1487 MRI.addLiveOut(RVLocs[i].getLocReg());
1491 SmallVector<SDValue, 6> RetOps;
1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1493 // Operand #1 = Bytes To Pop
1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1497 // Copy the result values into the output registers.
1498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1499 CCValAssign &VA = RVLocs[i];
1500 assert(VA.isRegLoc() && "Can only return in registers!");
1501 SDValue ValToCopy = OutVals[i];
1502 EVT ValVT = ValToCopy.getValueType();
1504 // If this is x86-64, and we disabled SSE, we can't return FP values,
1505 // or SSE or MMX vectors.
1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1509 report_fatal_error("SSE register return with SSE disabled");
1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1512 // llvm-gcc has never done it right and no one has noticed, so this
1513 // should be OK for now.
1514 if (ValVT == MVT::f64 &&
1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1516 report_fatal_error("SSE2 register return with SSE2 disabled");
1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1519 // the RET instruction and handled by the FP Stackifier.
1520 if (VA.getLocReg() == X86::ST0 ||
1521 VA.getLocReg() == X86::ST1) {
1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1523 // change the value to the FP stack register class.
1524 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1526 RetOps.push_back(ValToCopy);
1527 // Don't emit a copytoreg.
1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1532 // which is returned in RAX / RDX.
1533 if (Subtarget->is64Bit()) {
1534 if (ValVT == MVT::x86mmx) {
1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1539 // If we don't have SSE2 available, convert to v4f32 so the generated
1540 // register is legal.
1541 if (!Subtarget->hasSSE2())
1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1548 Flag = Chain.getValue(1);
1551 // The x86-64 ABI for returning structs by value requires that we copy
1552 // the sret argument into %rax for the return. We saved the argument into
1553 // a virtual register in the entry block, so now we copy the value out
1555 if (Subtarget->is64Bit() &&
1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1559 unsigned Reg = FuncInfo->getSRetReturnReg();
1561 "SRetReturnReg should have been set in LowerFormalArguments().");
1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1565 Flag = Chain.getValue(1);
1567 // RAX now acts like a return value.
1568 MRI.addLiveOut(X86::RAX);
1571 RetOps[0] = Chain; // Update chain.
1573 // Add the flag if we have it.
1575 RetOps.push_back(Flag);
1577 return DAG.getNode(X86ISD::RET_FLAG, dl,
1578 MVT::Other, &RetOps[0], RetOps.size());
1581 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1582 if (N->getNumValues() != 1)
1584 if (!N->hasNUsesOfValue(1, 0))
1587 SDValue TCChain = Chain;
1588 SDNode *Copy = *N->use_begin();
1589 if (Copy->getOpcode() == ISD::CopyToReg) {
1590 // If the copy has a glue operand, we conservatively assume it isn't safe to
1591 // perform a tail call.
1592 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1594 TCChain = Copy->getOperand(0);
1595 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1598 bool HasRet = false;
1599 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1601 if (UI->getOpcode() != X86ISD::RET_FLAG)
1614 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1615 ISD::NodeType ExtendKind) const {
1617 // TODO: Is this also valid on 32-bit?
1618 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1619 ReturnMVT = MVT::i8;
1621 ReturnMVT = MVT::i32;
1623 EVT MinVT = getRegisterType(Context, ReturnMVT);
1624 return VT.bitsLT(MinVT) ? MinVT : VT;
1627 /// LowerCallResult - Lower the result values of a call into the
1628 /// appropriate copies out of appropriate physical registers.
1631 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1632 CallingConv::ID CallConv, bool isVarArg,
1633 const SmallVectorImpl<ISD::InputArg> &Ins,
1634 DebugLoc dl, SelectionDAG &DAG,
1635 SmallVectorImpl<SDValue> &InVals) const {
1637 // Assign locations to each value returned by this call.
1638 SmallVector<CCValAssign, 16> RVLocs;
1639 bool Is64Bit = Subtarget->is64Bit();
1640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1641 getTargetMachine(), RVLocs, *DAG.getContext());
1642 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1644 // Copy all of the result registers out of their specified physreg.
1645 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1646 CCValAssign &VA = RVLocs[i];
1647 EVT CopyVT = VA.getValVT();
1649 // If this is x86-64, and we disabled SSE, we can't return FP values
1650 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1651 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1652 report_fatal_error("SSE register return with SSE disabled");
1657 // If this is a call to a function that returns an fp value on the floating
1658 // point stack, we must guarantee the the value is popped from the stack, so
1659 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1660 // if the return value is not used. We use the FpPOP_RETVAL instruction
1662 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1663 // If we prefer to use the value in xmm registers, copy it out as f80 and
1664 // use a truncate to move it from fp stack reg to xmm reg.
1665 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1666 SDValue Ops[] = { Chain, InFlag };
1667 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1668 MVT::Other, MVT::Glue, Ops, 2), 1);
1669 Val = Chain.getValue(0);
1671 // Round the f80 to the right size, which also moves it to the appropriate
1673 if (CopyVT != VA.getValVT())
1674 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1675 // This truncation won't change the value.
1676 DAG.getIntPtrConstant(1));
1678 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1679 CopyVT, InFlag).getValue(1);
1680 Val = Chain.getValue(0);
1682 InFlag = Chain.getValue(2);
1683 InVals.push_back(Val);
1690 //===----------------------------------------------------------------------===//
1691 // C & StdCall & Fast Calling Convention implementation
1692 //===----------------------------------------------------------------------===//
1693 // StdCall calling convention seems to be standard for many Windows' API
1694 // routines and around. It differs from C calling convention just a little:
1695 // callee should clean up the stack, not caller. Symbols should be also
1696 // decorated in some fancy way :) It doesn't support any vector arguments.
1697 // For info on fast calling convention see Fast Calling Convention (tail call)
1698 // implementation LowerX86_32FastCCCallTo.
1700 /// CallIsStructReturn - Determines whether a call uses struct return
1702 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1706 return Outs[0].Flags.isSRet();
1709 /// ArgsAreStructReturn - Determines whether a function uses struct
1710 /// return semantics.
1712 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1716 return Ins[0].Flags.isSRet();
1719 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1720 /// by "Src" to address "Dst" with size and alignment information specified by
1721 /// the specific parameter attribute. The copy will be passed as a byval
1722 /// function parameter.
1724 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1725 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1727 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1729 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1730 /*isVolatile*/false, /*AlwaysInline=*/true,
1731 MachinePointerInfo(), MachinePointerInfo());
1734 /// IsTailCallConvention - Return true if the calling convention is one that
1735 /// supports tail call optimization.
1736 static bool IsTailCallConvention(CallingConv::ID CC) {
1737 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1740 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1741 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1745 CallingConv::ID CalleeCC = CS.getCallingConv();
1746 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1752 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1753 /// a tailcall target by changing its ABI.
1754 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1755 bool GuaranteedTailCallOpt) {
1756 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1760 X86TargetLowering::LowerMemArgument(SDValue Chain,
1761 CallingConv::ID CallConv,
1762 const SmallVectorImpl<ISD::InputArg> &Ins,
1763 DebugLoc dl, SelectionDAG &DAG,
1764 const CCValAssign &VA,
1765 MachineFrameInfo *MFI,
1767 // Create the nodes corresponding to a load from this parameter slot.
1768 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1769 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1770 getTargetMachine().Options.GuaranteedTailCallOpt);
1771 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1774 // If value is passed by pointer we have address passed instead of the value
1776 if (VA.getLocInfo() == CCValAssign::Indirect)
1777 ValVT = VA.getLocVT();
1779 ValVT = VA.getValVT();
1781 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1782 // changed with more analysis.
1783 // In case of tail call optimization mark all arguments mutable. Since they
1784 // could be overwritten by lowering of arguments in case of a tail call.
1785 if (Flags.isByVal()) {
1786 unsigned Bytes = Flags.getByValSize();
1787 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1788 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1789 return DAG.getFrameIndex(FI, getPointerTy());
1791 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1792 VA.getLocMemOffset(), isImmutable);
1793 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1794 return DAG.getLoad(ValVT, dl, Chain, FIN,
1795 MachinePointerInfo::getFixedStack(FI),
1796 false, false, false, 0);
1801 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1802 CallingConv::ID CallConv,
1804 const SmallVectorImpl<ISD::InputArg> &Ins,
1807 SmallVectorImpl<SDValue> &InVals)
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1812 const Function* Fn = MF.getFunction();
1813 if (Fn->hasExternalLinkage() &&
1814 Subtarget->isTargetCygMing() &&
1815 Fn->getName() == "main")
1816 FuncInfo->setForceFramePointer(true);
1818 MachineFrameInfo *MFI = MF.getFrameInfo();
1819 bool Is64Bit = Subtarget->is64Bit();
1820 bool IsWindows = Subtarget->isTargetWindows();
1821 bool IsWin64 = Subtarget->isTargetWin64();
1823 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1824 "Var args not supported with calling convention fastcc or ghc");
1826 // Assign locations to all of the incoming arguments.
1827 SmallVector<CCValAssign, 16> ArgLocs;
1828 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1829 ArgLocs, *DAG.getContext());
1831 // Allocate shadow area for Win64
1833 CCInfo.AllocateStack(32, 8);
1836 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1838 unsigned LastVal = ~0U;
1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1841 CCValAssign &VA = ArgLocs[i];
1842 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1844 assert(VA.getValNo() != LastVal &&
1845 "Don't support value assigned to multiple locs yet");
1847 LastVal = VA.getValNo();
1849 if (VA.isRegLoc()) {
1850 EVT RegVT = VA.getLocVT();
1851 const TargetRegisterClass *RC;
1852 if (RegVT == MVT::i32)
1853 RC = &X86::GR32RegClass;
1854 else if (Is64Bit && RegVT == MVT::i64)
1855 RC = &X86::GR64RegClass;
1856 else if (RegVT == MVT::f32)
1857 RC = &X86::FR32RegClass;
1858 else if (RegVT == MVT::f64)
1859 RC = &X86::FR64RegClass;
1860 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1861 RC = &X86::VR256RegClass;
1862 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1863 RC = &X86::VR128RegClass;
1864 else if (RegVT == MVT::x86mmx)
1865 RC = &X86::VR64RegClass;
1867 llvm_unreachable("Unknown argument type!");
1869 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1870 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1872 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1873 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1875 if (VA.getLocInfo() == CCValAssign::SExt)
1876 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1877 DAG.getValueType(VA.getValVT()));
1878 else if (VA.getLocInfo() == CCValAssign::ZExt)
1879 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1880 DAG.getValueType(VA.getValVT()));
1881 else if (VA.getLocInfo() == CCValAssign::BCvt)
1882 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1884 if (VA.isExtInLoc()) {
1885 // Handle MMX values passed in XMM regs.
1886 if (RegVT.isVector()) {
1887 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1890 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1893 assert(VA.isMemLoc());
1894 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1897 // If value is passed via pointer - do a load.
1898 if (VA.getLocInfo() == CCValAssign::Indirect)
1899 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1900 MachinePointerInfo(), false, false, false, 0);
1902 InVals.push_back(ArgValue);
1905 // The x86-64 ABI for returning structs by value requires that we copy
1906 // the sret argument into %rax for the return. Save the argument into
1907 // a virtual register so that we can access it from the return points.
1908 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1909 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1910 unsigned Reg = FuncInfo->getSRetReturnReg();
1912 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1913 FuncInfo->setSRetReturnReg(Reg);
1915 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1919 unsigned StackSize = CCInfo.getNextStackOffset();
1920 // Align stack specially for tail calls.
1921 if (FuncIsMadeTailCallSafe(CallConv,
1922 MF.getTarget().Options.GuaranteedTailCallOpt))
1923 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1925 // If the function takes variable number of arguments, make a frame index for
1926 // the start of the first vararg value... for expansion of llvm.va_start.
1928 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1929 CallConv != CallingConv::X86_ThisCall)) {
1930 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1933 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1935 // FIXME: We should really autogenerate these arrays
1936 static const uint16_t GPR64ArgRegsWin64[] = {
1937 X86::RCX, X86::RDX, X86::R8, X86::R9
1939 static const uint16_t GPR64ArgRegs64Bit[] = {
1940 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1942 static const uint16_t XMMArgRegs64Bit[] = {
1943 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1944 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1946 const uint16_t *GPR64ArgRegs;
1947 unsigned NumXMMRegs = 0;
1950 // The XMM registers which might contain var arg parameters are shadowed
1951 // in their paired GPR. So we only need to save the GPR to their home
1953 TotalNumIntRegs = 4;
1954 GPR64ArgRegs = GPR64ArgRegsWin64;
1956 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1957 GPR64ArgRegs = GPR64ArgRegs64Bit;
1959 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1962 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1965 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1966 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1967 "SSE register cannot be used when SSE is disabled!");
1968 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1969 NoImplicitFloatOps) &&
1970 "SSE register cannot be used when SSE is disabled!");
1971 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1972 !Subtarget->hasSSE1())
1973 // Kernel mode asks for SSE to be disabled, so don't push them
1975 TotalNumXMMRegs = 0;
1978 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1979 // Get to the caller-allocated home save location. Add 8 to account
1980 // for the return address.
1981 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1982 FuncInfo->setRegSaveFrameIndex(
1983 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1984 // Fixup to set vararg frame on shadow area (4 x i64).
1986 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1988 // For X86-64, if there are vararg parameters that are passed via
1989 // registers, then we must store them to their spots on the stack so
1990 // they may be loaded by deferencing the result of va_next.
1991 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1992 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1993 FuncInfo->setRegSaveFrameIndex(
1994 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1998 // Store the integer parameter registers.
1999 SmallVector<SDValue, 8> MemOps;
2000 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2002 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2003 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2004 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2005 DAG.getIntPtrConstant(Offset));
2006 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2007 &X86::GR64RegClass);
2008 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2010 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2011 MachinePointerInfo::getFixedStack(
2012 FuncInfo->getRegSaveFrameIndex(), Offset),
2014 MemOps.push_back(Store);
2018 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2019 // Now store the XMM (fp + vector) parameter registers.
2020 SmallVector<SDValue, 11> SaveXMMOps;
2021 SaveXMMOps.push_back(Chain);
2023 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2024 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2025 SaveXMMOps.push_back(ALVal);
2027 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2028 FuncInfo->getRegSaveFrameIndex()));
2029 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2030 FuncInfo->getVarArgsFPOffset()));
2032 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2033 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2034 &X86::VR128RegClass);
2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2036 SaveXMMOps.push_back(Val);
2038 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2040 &SaveXMMOps[0], SaveXMMOps.size()));
2043 if (!MemOps.empty())
2044 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2045 &MemOps[0], MemOps.size());
2049 // Some CCs need callee pop.
2050 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2051 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2052 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2054 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2055 // If this is an sret function, the return should pop the hidden pointer.
2056 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2057 ArgsAreStructReturn(Ins))
2058 FuncInfo->setBytesToPopOnReturn(4);
2062 // RegSaveFrameIndex is X86-64 only.
2063 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2064 if (CallConv == CallingConv::X86_FastCall ||
2065 CallConv == CallingConv::X86_ThisCall)
2066 // fastcc functions can't have varargs.
2067 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2070 FuncInfo->setArgumentStackSize(StackSize);
2076 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2077 SDValue StackPtr, SDValue Arg,
2078 DebugLoc dl, SelectionDAG &DAG,
2079 const CCValAssign &VA,
2080 ISD::ArgFlagsTy Flags) const {
2081 unsigned LocMemOffset = VA.getLocMemOffset();
2082 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2083 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2084 if (Flags.isByVal())
2085 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2087 return DAG.getStore(Chain, dl, Arg, PtrOff,
2088 MachinePointerInfo::getStack(LocMemOffset),
2092 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2093 /// optimization is performed and it is required.
2095 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2096 SDValue &OutRetAddr, SDValue Chain,
2097 bool IsTailCall, bool Is64Bit,
2098 int FPDiff, DebugLoc dl) const {
2099 // Adjust the Return address stack slot.
2100 EVT VT = getPointerTy();
2101 OutRetAddr = getReturnAddressFrameIndex(DAG);
2103 // Load the "old" Return address.
2104 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2105 false, false, false, 0);
2106 return SDValue(OutRetAddr.getNode(), 1);
2109 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2110 /// optimization is performed and it is required (FPDiff!=0).
2112 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2113 SDValue Chain, SDValue RetAddrFrIdx,
2114 bool Is64Bit, int FPDiff, DebugLoc dl) {
2115 // Store the return address to the appropriate stack slot.
2116 if (!FPDiff) return Chain;
2117 // Calculate the new stack slot for the return address.
2118 int SlotSize = Is64Bit ? 8 : 4;
2119 int NewReturnAddrFI =
2120 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2121 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2122 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2123 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2124 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2130 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2131 CallingConv::ID CallConv, bool isVarArg,
2132 bool doesNotRet, bool &isTailCall,
2133 const SmallVectorImpl<ISD::OutputArg> &Outs,
2134 const SmallVectorImpl<SDValue> &OutVals,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2136 DebugLoc dl, SelectionDAG &DAG,
2137 SmallVectorImpl<SDValue> &InVals) const {
2138 MachineFunction &MF = DAG.getMachineFunction();
2139 bool Is64Bit = Subtarget->is64Bit();
2140 bool IsWin64 = Subtarget->isTargetWin64();
2141 bool IsWindows = Subtarget->isTargetWindows();
2142 bool IsStructRet = CallIsStructReturn(Outs);
2143 bool IsSibcall = false;
2145 if (MF.getTarget().Options.DisableTailCalls)
2149 // Check if it's really possible to do a tail call.
2150 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2151 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2152 Outs, OutVals, Ins, DAG);
2154 // Sibcalls are automatically detected tailcalls which do not require
2156 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2163 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2164 "Var args not supported with calling convention fastcc or ghc");
2166 // Analyze operands of the call, assigning locations to each operand.
2167 SmallVector<CCValAssign, 16> ArgLocs;
2168 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2169 ArgLocs, *DAG.getContext());
2171 // Allocate shadow area for Win64
2173 CCInfo.AllocateStack(32, 8);
2176 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2178 // Get a count of how many bytes are to be pushed on the stack.
2179 unsigned NumBytes = CCInfo.getNextStackOffset();
2181 // This is a sibcall. The memory operands are available in caller's
2182 // own caller's stack.
2184 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2185 IsTailCallConvention(CallConv))
2186 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2189 if (isTailCall && !IsSibcall) {
2190 // Lower arguments at fp - stackoffset + fpdiff.
2191 unsigned NumBytesCallerPushed =
2192 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2193 FPDiff = NumBytesCallerPushed - NumBytes;
2195 // Set the delta of movement of the returnaddr stackslot.
2196 // But only set if delta is greater than previous delta.
2197 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2198 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2202 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2204 SDValue RetAddrFrIdx;
2205 // Load return address for tail calls.
2206 if (isTailCall && FPDiff)
2207 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2208 Is64Bit, FPDiff, dl);
2210 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2211 SmallVector<SDValue, 8> MemOpChains;
2214 // Walk the register/memloc assignments, inserting copies/loads. In the case
2215 // of tail call optimization arguments are handle later.
2216 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2217 CCValAssign &VA = ArgLocs[i];
2218 EVT RegVT = VA.getLocVT();
2219 SDValue Arg = OutVals[i];
2220 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2221 bool isByVal = Flags.isByVal();
2223 // Promote the value if needed.
2224 switch (VA.getLocInfo()) {
2225 default: llvm_unreachable("Unknown loc info!");
2226 case CCValAssign::Full: break;
2227 case CCValAssign::SExt:
2228 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2230 case CCValAssign::ZExt:
2231 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2233 case CCValAssign::AExt:
2234 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2235 // Special case: passing MMX values in XMM registers.
2236 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2237 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2238 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2240 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2242 case CCValAssign::BCvt:
2243 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2245 case CCValAssign::Indirect: {
2246 // Store the argument.
2247 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2248 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2249 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2250 MachinePointerInfo::getFixedStack(FI),
2257 if (VA.isRegLoc()) {
2258 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2259 if (isVarArg && IsWin64) {
2260 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2261 // shadow reg if callee is a varargs function.
2262 unsigned ShadowReg = 0;
2263 switch (VA.getLocReg()) {
2264 case X86::XMM0: ShadowReg = X86::RCX; break;
2265 case X86::XMM1: ShadowReg = X86::RDX; break;
2266 case X86::XMM2: ShadowReg = X86::R8; break;
2267 case X86::XMM3: ShadowReg = X86::R9; break;
2270 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2272 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2273 assert(VA.isMemLoc());
2274 if (StackPtr.getNode() == 0)
2275 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2276 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2277 dl, DAG, VA, Flags));
2281 if (!MemOpChains.empty())
2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2283 &MemOpChains[0], MemOpChains.size());
2285 // Build a sequence of copy-to-reg nodes chained together with token chain
2286 // and flag operands which copy the outgoing args into registers.
2288 // Tail call byval lowering might overwrite argument registers so in case of
2289 // tail call optimization the copies to registers are lowered later.
2291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2293 RegsToPass[i].second, InFlag);
2294 InFlag = Chain.getValue(1);
2297 if (Subtarget->isPICStyleGOT()) {
2298 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2301 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2302 DAG.getNode(X86ISD::GlobalBaseReg,
2303 DebugLoc(), getPointerTy()),
2305 InFlag = Chain.getValue(1);
2307 // If we are tail calling and generating PIC/GOT style code load the
2308 // address of the callee into ECX. The value in ecx is used as target of
2309 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2310 // for tail calls on PIC/GOT architectures. Normally we would just put the
2311 // address of GOT into ebx and then call target@PLT. But for tail calls
2312 // ebx would be restored (since ebx is callee saved) before jumping to the
2315 // Note: The actual moving to ECX is done further down.
2316 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2317 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2318 !G->getGlobal()->hasProtectedVisibility())
2319 Callee = LowerGlobalAddress(Callee, DAG);
2320 else if (isa<ExternalSymbolSDNode>(Callee))
2321 Callee = LowerExternalSymbol(Callee, DAG);
2325 if (Is64Bit && isVarArg && !IsWin64) {
2326 // From AMD64 ABI document:
2327 // For calls that may call functions that use varargs or stdargs
2328 // (prototype-less calls or calls to functions containing ellipsis (...) in
2329 // the declaration) %al is used as hidden argument to specify the number
2330 // of SSE registers used. The contents of %al do not need to match exactly
2331 // the number of registers, but must be an ubound on the number of SSE
2332 // registers used and is in the range 0 - 8 inclusive.
2334 // Count the number of XMM registers allocated.
2335 static const uint16_t XMMArgRegs[] = {
2336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2337 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2339 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2340 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2341 && "SSE registers cannot be used when SSE is disabled");
2343 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2344 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2345 InFlag = Chain.getValue(1);
2349 // For tail calls lower the arguments to the 'real' stack slot.
2351 // Force all the incoming stack arguments to be loaded from the stack
2352 // before any new outgoing arguments are stored to the stack, because the
2353 // outgoing stack slots may alias the incoming argument stack slots, and
2354 // the alias isn't otherwise explicit. This is slightly more conservative
2355 // than necessary, because it means that each store effectively depends
2356 // on every argument instead of just those arguments it would clobber.
2357 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2359 SmallVector<SDValue, 8> MemOpChains2;
2362 // Do not flag preceding copytoreg stuff together with the following stuff.
2364 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2366 CCValAssign &VA = ArgLocs[i];
2369 assert(VA.isMemLoc());
2370 SDValue Arg = OutVals[i];
2371 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2372 // Create frame index.
2373 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2374 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2375 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2376 FIN = DAG.getFrameIndex(FI, getPointerTy());
2378 if (Flags.isByVal()) {
2379 // Copy relative to framepointer.
2380 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2381 if (StackPtr.getNode() == 0)
2382 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2384 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2386 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2390 // Store relative to framepointer.
2391 MemOpChains2.push_back(
2392 DAG.getStore(ArgChain, dl, Arg, FIN,
2393 MachinePointerInfo::getFixedStack(FI),
2399 if (!MemOpChains2.empty())
2400 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2401 &MemOpChains2[0], MemOpChains2.size());
2403 // Copy arguments to their registers.
2404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2405 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2406 RegsToPass[i].second, InFlag);
2407 InFlag = Chain.getValue(1);
2411 // Store the return address to the appropriate stack slot.
2412 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2416 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2417 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2418 // In the 64-bit large code model, we have to make all calls
2419 // through a register, since the call instruction's 32-bit
2420 // pc-relative offset may not be large enough to hold the whole
2422 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2423 // If the callee is a GlobalAddress node (quite common, every direct call
2424 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2427 // We should use extra load for direct calls to dllimported functions in
2429 const GlobalValue *GV = G->getGlobal();
2430 if (!GV->hasDLLImportLinkage()) {
2431 unsigned char OpFlags = 0;
2432 bool ExtraLoad = false;
2433 unsigned WrapperKind = ISD::DELETED_NODE;
2435 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2436 // external symbols most go through the PLT in PIC mode. If the symbol
2437 // has hidden or protected visibility, or if it is static or local, then
2438 // we don't need to use the PLT - we can directly call it.
2439 if (Subtarget->isTargetELF() &&
2440 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2441 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2442 OpFlags = X86II::MO_PLT;
2443 } else if (Subtarget->isPICStyleStubAny() &&
2444 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2445 (!Subtarget->getTargetTriple().isMacOSX() ||
2446 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2447 // PC-relative references to external symbols should go through $stub,
2448 // unless we're building with the leopard linker or later, which
2449 // automatically synthesizes these stubs.
2450 OpFlags = X86II::MO_DARWIN_STUB;
2451 } else if (Subtarget->isPICStyleRIPRel() &&
2452 isa<Function>(GV) &&
2453 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2454 // If the function is marked as non-lazy, generate an indirect call
2455 // which loads from the GOT directly. This avoids runtime overhead
2456 // at the cost of eager binding (and one extra byte of encoding).
2457 OpFlags = X86II::MO_GOTPCREL;
2458 WrapperKind = X86ISD::WrapperRIP;
2462 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2463 G->getOffset(), OpFlags);
2465 // Add a wrapper if needed.
2466 if (WrapperKind != ISD::DELETED_NODE)
2467 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2468 // Add extra indirection if needed.
2470 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2471 MachinePointerInfo::getGOT(),
2472 false, false, false, 0);
2474 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2475 unsigned char OpFlags = 0;
2477 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2478 // external symbols should go through the PLT.
2479 if (Subtarget->isTargetELF() &&
2480 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2481 OpFlags = X86II::MO_PLT;
2482 } else if (Subtarget->isPICStyleStubAny() &&
2483 (!Subtarget->getTargetTriple().isMacOSX() ||
2484 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2485 // PC-relative references to external symbols should go through $stub,
2486 // unless we're building with the leopard linker or later, which
2487 // automatically synthesizes these stubs.
2488 OpFlags = X86II::MO_DARWIN_STUB;
2491 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2495 // Returns a chain & a flag for retval copy to use.
2496 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2497 SmallVector<SDValue, 8> Ops;
2499 if (!IsSibcall && isTailCall) {
2500 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2501 DAG.getIntPtrConstant(0, true), InFlag);
2502 InFlag = Chain.getValue(1);
2505 Ops.push_back(Chain);
2506 Ops.push_back(Callee);
2509 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2511 // Add argument registers to the end of the list so that they are known live
2513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2514 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2515 RegsToPass[i].second.getValueType()));
2517 // Add an implicit use GOT pointer in EBX.
2518 if (!isTailCall && Subtarget->isPICStyleGOT())
2519 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2521 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2522 if (Is64Bit && isVarArg && !IsWin64)
2523 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2525 // Add a register mask operand representing the call-preserved registers.
2526 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2527 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2528 assert(Mask && "Missing call preserved mask for calling convention");
2529 Ops.push_back(DAG.getRegisterMask(Mask));
2531 if (InFlag.getNode())
2532 Ops.push_back(InFlag);
2536 //// If this is the first return lowered for this function, add the regs
2537 //// to the liveout set for the function.
2538 // This isn't right, although it's probably harmless on x86; liveouts
2539 // should be computed from returns not tail calls. Consider a void
2540 // function making a tail call to a function returning int.
2541 return DAG.getNode(X86ISD::TC_RETURN, dl,
2542 NodeTys, &Ops[0], Ops.size());
2545 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2546 InFlag = Chain.getValue(1);
2548 // Create the CALLSEQ_END node.
2549 unsigned NumBytesForCalleeToPush;
2550 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2551 getTargetMachine().Options.GuaranteedTailCallOpt))
2552 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2553 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2555 // If this is a call to a struct-return function, the callee
2556 // pops the hidden struct pointer, so we have to push it back.
2557 // This is common for Darwin/X86, Linux & Mingw32 targets.
2558 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2559 NumBytesForCalleeToPush = 4;
2561 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2563 // Returns a flag for retval copy to use.
2565 Chain = DAG.getCALLSEQ_END(Chain,
2566 DAG.getIntPtrConstant(NumBytes, true),
2567 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2570 InFlag = Chain.getValue(1);
2573 // Handle result values, copying them out of physregs into vregs that we
2575 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2576 Ins, dl, DAG, InVals);
2580 //===----------------------------------------------------------------------===//
2581 // Fast Calling Convention (tail call) implementation
2582 //===----------------------------------------------------------------------===//
2584 // Like std call, callee cleans arguments, convention except that ECX is
2585 // reserved for storing the tail called function address. Only 2 registers are
2586 // free for argument passing (inreg). Tail call optimization is performed
2588 // * tailcallopt is enabled
2589 // * caller/callee are fastcc
2590 // On X86_64 architecture with GOT-style position independent code only local
2591 // (within module) calls are supported at the moment.
2592 // To keep the stack aligned according to platform abi the function
2593 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2594 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2595 // If a tail called function callee has more arguments than the caller the
2596 // caller needs to make sure that there is room to move the RETADDR to. This is
2597 // achieved by reserving an area the size of the argument delta right after the
2598 // original REtADDR, but before the saved framepointer or the spilled registers
2599 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2611 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2612 /// for a 16 byte align requirement.
2614 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2615 SelectionDAG& DAG) const {
2616 MachineFunction &MF = DAG.getMachineFunction();
2617 const TargetMachine &TM = MF.getTarget();
2618 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2619 unsigned StackAlignment = TFI.getStackAlignment();
2620 uint64_t AlignMask = StackAlignment - 1;
2621 int64_t Offset = StackSize;
2622 uint64_t SlotSize = TD->getPointerSize();
2623 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2624 // Number smaller than 12 so just add the difference.
2625 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2627 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2628 Offset = ((~AlignMask) & Offset) + StackAlignment +
2629 (StackAlignment-SlotSize);
2634 /// MatchingStackOffset - Return true if the given stack call argument is
2635 /// already available in the same position (relatively) of the caller's
2636 /// incoming argument stack.
2638 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2639 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2640 const X86InstrInfo *TII) {
2641 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2643 if (Arg.getOpcode() == ISD::CopyFromReg) {
2644 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2645 if (!TargetRegisterInfo::isVirtualRegister(VR))
2647 MachineInstr *Def = MRI->getVRegDef(VR);
2650 if (!Flags.isByVal()) {
2651 if (!TII->isLoadFromStackSlot(Def, FI))
2654 unsigned Opcode = Def->getOpcode();
2655 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2656 Def->getOperand(1).isFI()) {
2657 FI = Def->getOperand(1).getIndex();
2658 Bytes = Flags.getByValSize();
2662 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2663 if (Flags.isByVal())
2664 // ByVal argument is passed in as a pointer but it's now being
2665 // dereferenced. e.g.
2666 // define @foo(%struct.X* %A) {
2667 // tail call @bar(%struct.X* byval %A)
2670 SDValue Ptr = Ld->getBasePtr();
2671 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2674 FI = FINode->getIndex();
2675 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2676 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2677 FI = FINode->getIndex();
2678 Bytes = Flags.getByValSize();
2682 assert(FI != INT_MAX);
2683 if (!MFI->isFixedObjectIndex(FI))
2685 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2688 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2689 /// for tail call optimization. Targets which want to do tail call
2690 /// optimization should implement this function.
2692 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2693 CallingConv::ID CalleeCC,
2695 bool isCalleeStructRet,
2696 bool isCallerStructRet,
2697 const SmallVectorImpl<ISD::OutputArg> &Outs,
2698 const SmallVectorImpl<SDValue> &OutVals,
2699 const SmallVectorImpl<ISD::InputArg> &Ins,
2700 SelectionDAG& DAG) const {
2701 if (!IsTailCallConvention(CalleeCC) &&
2702 CalleeCC != CallingConv::C)
2705 // If -tailcallopt is specified, make fastcc functions tail-callable.
2706 const MachineFunction &MF = DAG.getMachineFunction();
2707 const Function *CallerF = DAG.getMachineFunction().getFunction();
2708 CallingConv::ID CallerCC = CallerF->getCallingConv();
2709 bool CCMatch = CallerCC == CalleeCC;
2711 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2712 if (IsTailCallConvention(CalleeCC) && CCMatch)
2717 // Look for obvious safe cases to perform tail call optimization that do not
2718 // require ABI changes. This is what gcc calls sibcall.
2720 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2721 // emit a special epilogue.
2722 if (RegInfo->needsStackRealignment(MF))
2725 // Also avoid sibcall optimization if either caller or callee uses struct
2726 // return semantics.
2727 if (isCalleeStructRet || isCallerStructRet)
2730 // An stdcall caller is expected to clean up its arguments; the callee
2731 // isn't going to do that.
2732 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2735 // Do not sibcall optimize vararg calls unless all arguments are passed via
2737 if (isVarArg && !Outs.empty()) {
2739 // Optimizing for varargs on Win64 is unlikely to be safe without
2740 // additional testing.
2741 if (Subtarget->isTargetWin64())
2744 SmallVector<CCValAssign, 16> ArgLocs;
2745 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2746 getTargetMachine(), ArgLocs, *DAG.getContext());
2748 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2750 if (!ArgLocs[i].isRegLoc())
2754 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2755 // stack. Therefore, if it's not used by the call it is not safe to optimize
2756 // this into a sibcall.
2757 bool Unused = false;
2758 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2765 SmallVector<CCValAssign, 16> RVLocs;
2766 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2767 getTargetMachine(), RVLocs, *DAG.getContext());
2768 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2769 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2770 CCValAssign &VA = RVLocs[i];
2771 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2776 // If the calling conventions do not match, then we'd better make sure the
2777 // results are returned in the same way as what the caller expects.
2779 SmallVector<CCValAssign, 16> RVLocs1;
2780 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2781 getTargetMachine(), RVLocs1, *DAG.getContext());
2782 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2784 SmallVector<CCValAssign, 16> RVLocs2;
2785 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2786 getTargetMachine(), RVLocs2, *DAG.getContext());
2787 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2789 if (RVLocs1.size() != RVLocs2.size())
2791 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2792 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2794 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2796 if (RVLocs1[i].isRegLoc()) {
2797 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2800 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2806 // If the callee takes no arguments then go on to check the results of the
2808 if (!Outs.empty()) {
2809 // Check if stack adjustment is needed. For now, do not do this if any
2810 // argument is passed on the stack.
2811 SmallVector<CCValAssign, 16> ArgLocs;
2812 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2813 getTargetMachine(), ArgLocs, *DAG.getContext());
2815 // Allocate shadow area for Win64
2816 if (Subtarget->isTargetWin64()) {
2817 CCInfo.AllocateStack(32, 8);
2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2821 if (CCInfo.getNextStackOffset()) {
2822 MachineFunction &MF = DAG.getMachineFunction();
2823 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2826 // Check if the arguments are already laid out in the right way as
2827 // the caller's fixed stack objects.
2828 MachineFrameInfo *MFI = MF.getFrameInfo();
2829 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2830 const X86InstrInfo *TII =
2831 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2832 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2833 CCValAssign &VA = ArgLocs[i];
2834 SDValue Arg = OutVals[i];
2835 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2836 if (VA.getLocInfo() == CCValAssign::Indirect)
2838 if (!VA.isRegLoc()) {
2839 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2846 // If the tailcall address may be in a register, then make sure it's
2847 // possible to register allocate for it. In 32-bit, the call address can
2848 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2849 // callee-saved registers are restored. These happen to be the same
2850 // registers used to pass 'inreg' arguments so watch out for those.
2851 if (!Subtarget->is64Bit() &&
2852 !isa<GlobalAddressSDNode>(Callee) &&
2853 !isa<ExternalSymbolSDNode>(Callee)) {
2854 unsigned NumInRegs = 0;
2855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2856 CCValAssign &VA = ArgLocs[i];
2859 unsigned Reg = VA.getLocReg();
2862 case X86::EAX: case X86::EDX: case X86::ECX:
2863 if (++NumInRegs == 3)
2875 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2876 return X86::createFastISel(funcInfo);
2880 //===----------------------------------------------------------------------===//
2881 // Other Lowering Hooks
2882 //===----------------------------------------------------------------------===//
2884 static bool MayFoldLoad(SDValue Op) {
2885 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2888 static bool MayFoldIntoStore(SDValue Op) {
2889 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2892 static bool isTargetShuffle(unsigned Opcode) {
2894 default: return false;
2895 case X86ISD::PSHUFD:
2896 case X86ISD::PSHUFHW:
2897 case X86ISD::PSHUFLW:
2899 case X86ISD::PALIGN:
2900 case X86ISD::MOVLHPS:
2901 case X86ISD::MOVLHPD:
2902 case X86ISD::MOVHLPS:
2903 case X86ISD::MOVLPS:
2904 case X86ISD::MOVLPD:
2905 case X86ISD::MOVSHDUP:
2906 case X86ISD::MOVSLDUP:
2907 case X86ISD::MOVDDUP:
2910 case X86ISD::UNPCKL:
2911 case X86ISD::UNPCKH:
2912 case X86ISD::VPERMILP:
2913 case X86ISD::VPERM2X128:
2918 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2919 SDValue V1, SelectionDAG &DAG) {
2921 default: llvm_unreachable("Unknown x86 shuffle node");
2922 case X86ISD::MOVSHDUP:
2923 case X86ISD::MOVSLDUP:
2924 case X86ISD::MOVDDUP:
2925 return DAG.getNode(Opc, dl, VT, V1);
2929 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2930 SDValue V1, unsigned TargetMask,
2931 SelectionDAG &DAG) {
2933 default: llvm_unreachable("Unknown x86 shuffle node");
2934 case X86ISD::PSHUFD:
2935 case X86ISD::PSHUFHW:
2936 case X86ISD::PSHUFLW:
2937 case X86ISD::VPERMILP:
2938 case X86ISD::VPERMI:
2939 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2943 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2944 SDValue V1, SDValue V2, unsigned TargetMask,
2945 SelectionDAG &DAG) {
2947 default: llvm_unreachable("Unknown x86 shuffle node");
2948 case X86ISD::PALIGN:
2950 case X86ISD::VPERM2X128:
2951 return DAG.getNode(Opc, dl, VT, V1, V2,
2952 DAG.getConstant(TargetMask, MVT::i8));
2956 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2957 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2959 default: llvm_unreachable("Unknown x86 shuffle node");
2960 case X86ISD::MOVLHPS:
2961 case X86ISD::MOVLHPD:
2962 case X86ISD::MOVHLPS:
2963 case X86ISD::MOVLPS:
2964 case X86ISD::MOVLPD:
2967 case X86ISD::UNPCKL:
2968 case X86ISD::UNPCKH:
2969 return DAG.getNode(Opc, dl, VT, V1, V2);
2973 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2974 MachineFunction &MF = DAG.getMachineFunction();
2975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2976 int ReturnAddrIndex = FuncInfo->getRAIndex();
2978 if (ReturnAddrIndex == 0) {
2979 // Set up a frame object for the return address.
2980 uint64_t SlotSize = TD->getPointerSize();
2981 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2983 FuncInfo->setRAIndex(ReturnAddrIndex);
2986 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2990 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2991 bool hasSymbolicDisplacement) {
2992 // Offset should fit into 32 bit immediate field.
2993 if (!isInt<32>(Offset))
2996 // If we don't have a symbolic displacement - we don't have any extra
2998 if (!hasSymbolicDisplacement)
3001 // FIXME: Some tweaks might be needed for medium code model.
3002 if (M != CodeModel::Small && M != CodeModel::Kernel)
3005 // For small code model we assume that latest object is 16MB before end of 31
3006 // bits boundary. We may also accept pretty large negative constants knowing
3007 // that all objects are in the positive half of address space.
3008 if (M == CodeModel::Small && Offset < 16*1024*1024)
3011 // For kernel code model we know that all object resist in the negative half
3012 // of 32bits address space. We may not accept negative offsets, since they may
3013 // be just off and we may accept pretty large positive ones.
3014 if (M == CodeModel::Kernel && Offset > 0)
3020 /// isCalleePop - Determines whether the callee is required to pop its
3021 /// own arguments. Callee pop is necessary to support tail calls.
3022 bool X86::isCalleePop(CallingConv::ID CallingConv,
3023 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3027 switch (CallingConv) {
3030 case CallingConv::X86_StdCall:
3032 case CallingConv::X86_FastCall:
3034 case CallingConv::X86_ThisCall:
3036 case CallingConv::Fast:
3038 case CallingConv::GHC:
3043 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3044 /// specific condition code, returning the condition code and the LHS/RHS of the
3045 /// comparison to make.
3046 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3047 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3050 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3051 // X > -1 -> X == 0, jump !sign.
3052 RHS = DAG.getConstant(0, RHS.getValueType());
3053 return X86::COND_NS;
3055 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3056 // X < 0 -> X == 0, jump on sign.
3059 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3061 RHS = DAG.getConstant(0, RHS.getValueType());
3062 return X86::COND_LE;
3066 switch (SetCCOpcode) {
3067 default: llvm_unreachable("Invalid integer condition!");
3068 case ISD::SETEQ: return X86::COND_E;
3069 case ISD::SETGT: return X86::COND_G;
3070 case ISD::SETGE: return X86::COND_GE;
3071 case ISD::SETLT: return X86::COND_L;
3072 case ISD::SETLE: return X86::COND_LE;
3073 case ISD::SETNE: return X86::COND_NE;
3074 case ISD::SETULT: return X86::COND_B;
3075 case ISD::SETUGT: return X86::COND_A;
3076 case ISD::SETULE: return X86::COND_BE;
3077 case ISD::SETUGE: return X86::COND_AE;
3081 // First determine if it is required or is profitable to flip the operands.
3083 // If LHS is a foldable load, but RHS is not, flip the condition.
3084 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3085 !ISD::isNON_EXTLoad(RHS.getNode())) {
3086 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3087 std::swap(LHS, RHS);
3090 switch (SetCCOpcode) {
3096 std::swap(LHS, RHS);
3100 // On a floating point condition, the flags are set as follows:
3102 // 0 | 0 | 0 | X > Y
3103 // 0 | 0 | 1 | X < Y
3104 // 1 | 0 | 0 | X == Y
3105 // 1 | 1 | 1 | unordered
3106 switch (SetCCOpcode) {
3107 default: llvm_unreachable("Condcode should be pre-legalized away");
3109 case ISD::SETEQ: return X86::COND_E;
3110 case ISD::SETOLT: // flipped
3112 case ISD::SETGT: return X86::COND_A;
3113 case ISD::SETOLE: // flipped
3115 case ISD::SETGE: return X86::COND_AE;
3116 case ISD::SETUGT: // flipped
3118 case ISD::SETLT: return X86::COND_B;
3119 case ISD::SETUGE: // flipped
3121 case ISD::SETLE: return X86::COND_BE;
3123 case ISD::SETNE: return X86::COND_NE;
3124 case ISD::SETUO: return X86::COND_P;
3125 case ISD::SETO: return X86::COND_NP;
3127 case ISD::SETUNE: return X86::COND_INVALID;
3131 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3132 /// code. Current x86 isa includes the following FP cmov instructions:
3133 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3134 static bool hasFPCMov(unsigned X86CC) {
3150 /// isFPImmLegal - Returns true if the target can instruction select the
3151 /// specified FP immediate natively. If false, the legalizer will
3152 /// materialize the FP immediate as a load from a constant pool.
3153 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3154 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3155 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3161 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3162 /// the specified range (L, H].
3163 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3164 return (Val < 0) || (Val >= Low && Val < Hi);
3167 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3168 /// specified value.
3169 static bool isUndefOrEqual(int Val, int CmpVal) {
3170 if (Val < 0 || Val == CmpVal)
3175 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3176 /// from position Pos and ending in Pos+Size, falls within the specified
3177 /// sequential range (L, L+Pos]. or is undef.
3178 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3179 int Pos, int Size, int Low) {
3180 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3181 if (!isUndefOrEqual(Mask[i], Low))
3186 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3187 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3188 /// the second operand.
3189 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3190 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3191 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3192 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3193 return (Mask[0] < 2 && Mask[1] < 2);
3197 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3198 /// is suitable for input to PSHUFHW.
3199 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3200 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3203 // Lower quadword copied in order or undef.
3204 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3207 // Upper quadword shuffled.
3208 for (unsigned i = 4; i != 8; ++i)
3209 if (!isUndefOrInRange(Mask[i], 4, 8))
3212 if (VT == MVT::v16i16) {
3213 // Lower quadword copied in order or undef.
3214 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3217 // Upper quadword shuffled.
3218 for (unsigned i = 12; i != 16; ++i)
3219 if (!isUndefOrInRange(Mask[i], 12, 16))
3226 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3227 /// is suitable for input to PSHUFLW.
3228 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3229 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3232 // Upper quadword copied in order.
3233 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3236 // Lower quadword shuffled.
3237 for (unsigned i = 0; i != 4; ++i)
3238 if (!isUndefOrInRange(Mask[i], 0, 4))
3241 if (VT == MVT::v16i16) {
3242 // Upper quadword copied in order.
3243 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3246 // Lower quadword shuffled.
3247 for (unsigned i = 8; i != 12; ++i)
3248 if (!isUndefOrInRange(Mask[i], 8, 12))
3255 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3256 /// is suitable for input to PALIGNR.
3257 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3258 const X86Subtarget *Subtarget) {
3259 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3260 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3263 unsigned NumElts = VT.getVectorNumElements();
3264 unsigned NumLanes = VT.getSizeInBits()/128;
3265 unsigned NumLaneElts = NumElts/NumLanes;
3267 // Do not handle 64-bit element shuffles with palignr.
3268 if (NumLaneElts == 2)
3271 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3273 for (i = 0; i != NumLaneElts; ++i) {
3278 // Lane is all undef, go to next lane
3279 if (i == NumLaneElts)
3282 int Start = Mask[i+l];
3284 // Make sure its in this lane in one of the sources
3285 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3286 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3289 // If not lane 0, then we must match lane 0
3290 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3293 // Correct second source to be contiguous with first source
3294 if (Start >= (int)NumElts)
3295 Start -= NumElts - NumLaneElts;
3297 // Make sure we're shifting in the right direction.
3298 if (Start <= (int)(i+l))
3303 // Check the rest of the elements to see if they are consecutive.
3304 for (++i; i != NumLaneElts; ++i) {
3305 int Idx = Mask[i+l];
3307 // Make sure its in this lane
3308 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3309 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3312 // If not lane 0, then we must match lane 0
3313 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3316 if (Idx >= (int)NumElts)
3317 Idx -= NumElts - NumLaneElts;
3319 if (!isUndefOrEqual(Idx, Start+i))
3328 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3329 /// the two vector operands have swapped position.
3330 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3331 unsigned NumElems) {
3332 for (unsigned i = 0; i != NumElems; ++i) {
3336 else if (idx < (int)NumElems)
3337 Mask[i] = idx + NumElems;
3339 Mask[i] = idx - NumElems;
3343 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3344 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3345 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3346 /// reverse of what x86 shuffles want.
3347 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3348 bool Commuted = false) {
3349 if (!HasAVX && VT.getSizeInBits() == 256)
3352 unsigned NumElems = VT.getVectorNumElements();
3353 unsigned NumLanes = VT.getSizeInBits()/128;
3354 unsigned NumLaneElems = NumElems/NumLanes;
3356 if (NumLaneElems != 2 && NumLaneElems != 4)
3359 // VSHUFPSY divides the resulting vector into 4 chunks.
3360 // The sources are also splitted into 4 chunks, and each destination
3361 // chunk must come from a different source chunk.
3363 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3364 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3366 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3367 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3369 // VSHUFPDY divides the resulting vector into 4 chunks.
3370 // The sources are also splitted into 4 chunks, and each destination
3371 // chunk must come from a different source chunk.
3373 // SRC1 => X3 X2 X1 X0
3374 // SRC2 => Y3 Y2 Y1 Y0
3376 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3378 unsigned HalfLaneElems = NumLaneElems/2;
3379 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3380 for (unsigned i = 0; i != NumLaneElems; ++i) {
3381 int Idx = Mask[i+l];
3382 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3383 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3385 // For VSHUFPSY, the mask of the second half must be the same as the
3386 // first but with the appropriate offsets. This works in the same way as
3387 // VPERMILPS works with masks.
3388 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3390 if (!isUndefOrEqual(Idx, Mask[i]+l))
3398 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3399 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3400 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3401 unsigned NumElems = VT.getVectorNumElements();
3403 if (VT.getSizeInBits() != 128)
3409 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3410 return isUndefOrEqual(Mask[0], 6) &&
3411 isUndefOrEqual(Mask[1], 7) &&
3412 isUndefOrEqual(Mask[2], 2) &&
3413 isUndefOrEqual(Mask[3], 3);
3416 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3417 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3419 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3420 unsigned NumElems = VT.getVectorNumElements();
3422 if (VT.getSizeInBits() != 128)
3428 return isUndefOrEqual(Mask[0], 2) &&
3429 isUndefOrEqual(Mask[1], 3) &&
3430 isUndefOrEqual(Mask[2], 2) &&
3431 isUndefOrEqual(Mask[3], 3);
3434 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3435 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3436 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3437 if (VT.getSizeInBits() != 128)
3440 unsigned NumElems = VT.getVectorNumElements();
3442 if (NumElems != 2 && NumElems != 4)
3445 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3446 if (!isUndefOrEqual(Mask[i], i + NumElems))
3449 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3450 if (!isUndefOrEqual(Mask[i], i))
3456 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3457 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3458 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3459 unsigned NumElems = VT.getVectorNumElements();
3461 if ((NumElems != 2 && NumElems != 4)
3462 || VT.getSizeInBits() > 128)
3465 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3466 if (!isUndefOrEqual(Mask[i], i))
3469 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3470 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3476 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3477 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3478 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3479 bool HasAVX2, bool V2IsSplat = false) {
3480 unsigned NumElts = VT.getVectorNumElements();
3482 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3483 "Unsupported vector type for unpckh");
3485 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3486 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3489 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3490 // independently on 128-bit lanes.
3491 unsigned NumLanes = VT.getSizeInBits()/128;
3492 unsigned NumLaneElts = NumElts/NumLanes;
3494 for (unsigned l = 0; l != NumLanes; ++l) {
3495 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3496 i != (l+1)*NumLaneElts;
3499 int BitI1 = Mask[i+1];
3500 if (!isUndefOrEqual(BitI, j))
3503 if (!isUndefOrEqual(BitI1, NumElts))
3506 if (!isUndefOrEqual(BitI1, j + NumElts))
3515 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3516 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3517 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3518 bool HasAVX2, bool V2IsSplat = false) {
3519 unsigned NumElts = VT.getVectorNumElements();
3521 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3522 "Unsupported vector type for unpckh");
3524 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3525 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3528 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3529 // independently on 128-bit lanes.
3530 unsigned NumLanes = VT.getSizeInBits()/128;
3531 unsigned NumLaneElts = NumElts/NumLanes;
3533 for (unsigned l = 0; l != NumLanes; ++l) {
3534 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3535 i != (l+1)*NumLaneElts; i += 2, ++j) {
3537 int BitI1 = Mask[i+1];
3538 if (!isUndefOrEqual(BitI, j))
3541 if (isUndefOrEqual(BitI1, NumElts))
3544 if (!isUndefOrEqual(BitI1, j+NumElts))
3552 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3553 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3555 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3557 unsigned NumElts = VT.getVectorNumElements();
3559 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3560 "Unsupported vector type for unpckh");
3562 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3563 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3566 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3567 // FIXME: Need a better way to get rid of this, there's no latency difference
3568 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3569 // the former later. We should also remove the "_undef" special mask.
3570 if (NumElts == 4 && VT.getSizeInBits() == 256)
3573 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3574 // independently on 128-bit lanes.
3575 unsigned NumLanes = VT.getSizeInBits()/128;
3576 unsigned NumLaneElts = NumElts/NumLanes;
3578 for (unsigned l = 0; l != NumLanes; ++l) {
3579 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3580 i != (l+1)*NumLaneElts;
3583 int BitI1 = Mask[i+1];
3585 if (!isUndefOrEqual(BitI, j))
3587 if (!isUndefOrEqual(BitI1, j))
3595 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3596 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3598 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3599 unsigned NumElts = VT.getVectorNumElements();
3601 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3602 "Unsupported vector type for unpckh");
3604 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3605 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3608 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3609 // independently on 128-bit lanes.
3610 unsigned NumLanes = VT.getSizeInBits()/128;
3611 unsigned NumLaneElts = NumElts/NumLanes;
3613 for (unsigned l = 0; l != NumLanes; ++l) {
3614 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3615 i != (l+1)*NumLaneElts; i += 2, ++j) {
3617 int BitI1 = Mask[i+1];
3618 if (!isUndefOrEqual(BitI, j))
3620 if (!isUndefOrEqual(BitI1, j))
3627 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3628 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3629 /// MOVSD, and MOVD, i.e. setting the lowest element.
3630 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3631 if (VT.getVectorElementType().getSizeInBits() < 32)
3633 if (VT.getSizeInBits() == 256)
3636 unsigned NumElts = VT.getVectorNumElements();
3638 if (!isUndefOrEqual(Mask[0], NumElts))
3641 for (unsigned i = 1; i != NumElts; ++i)
3642 if (!isUndefOrEqual(Mask[i], i))
3648 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3649 /// as permutations between 128-bit chunks or halves. As an example: this
3651 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3652 /// The first half comes from the second half of V1 and the second half from the
3653 /// the second half of V2.
3654 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3655 if (!HasAVX || VT.getSizeInBits() != 256)
3658 // The shuffle result is divided into half A and half B. In total the two
3659 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3660 // B must come from C, D, E or F.
3661 unsigned HalfSize = VT.getVectorNumElements()/2;
3662 bool MatchA = false, MatchB = false;
3664 // Check if A comes from one of C, D, E, F.
3665 for (unsigned Half = 0; Half != 4; ++Half) {
3666 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3672 // Check if B comes from one of C, D, E, F.
3673 for (unsigned Half = 0; Half != 4; ++Half) {
3674 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3680 return MatchA && MatchB;
3683 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3684 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3685 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3686 EVT VT = SVOp->getValueType(0);
3688 unsigned HalfSize = VT.getVectorNumElements()/2;
3690 unsigned FstHalf = 0, SndHalf = 0;
3691 for (unsigned i = 0; i < HalfSize; ++i) {
3692 if (SVOp->getMaskElt(i) > 0) {
3693 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3697 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3698 if (SVOp->getMaskElt(i) > 0) {
3699 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3704 return (FstHalf | (SndHalf << 4));
3707 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3708 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3709 /// Note that VPERMIL mask matching is different depending whether theunderlying
3710 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3711 /// to the same elements of the low, but to the higher half of the source.
3712 /// In VPERMILPD the two lanes could be shuffled independently of each other
3713 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3714 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3718 unsigned NumElts = VT.getVectorNumElements();
3719 // Only match 256-bit with 32/64-bit types
3720 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3723 unsigned NumLanes = VT.getSizeInBits()/128;
3724 unsigned LaneSize = NumElts/NumLanes;
3725 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3726 for (unsigned i = 0; i != LaneSize; ++i) {
3727 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3729 if (NumElts != 8 || l == 0)
3731 // VPERMILPS handling
3734 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3742 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3743 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3744 /// element of vector 2 and the other elements to come from vector 1 in order.
3745 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3746 bool V2IsSplat = false, bool V2IsUndef = false) {
3747 unsigned NumOps = VT.getVectorNumElements();
3748 if (VT.getSizeInBits() == 256)
3750 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3753 if (!isUndefOrEqual(Mask[0], 0))
3756 for (unsigned i = 1; i != NumOps; ++i)
3757 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3758 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3759 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3765 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3766 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3767 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3768 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3769 const X86Subtarget *Subtarget) {
3770 if (!Subtarget->hasSSE3())
3773 unsigned NumElems = VT.getVectorNumElements();
3775 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3776 (VT.getSizeInBits() == 256 && NumElems != 8))
3779 // "i+1" is the value the indexed mask element must have
3780 for (unsigned i = 0; i != NumElems; i += 2)
3781 if (!isUndefOrEqual(Mask[i], i+1) ||
3782 !isUndefOrEqual(Mask[i+1], i+1))
3788 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3789 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3790 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3791 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3792 const X86Subtarget *Subtarget) {
3793 if (!Subtarget->hasSSE3())
3796 unsigned NumElems = VT.getVectorNumElements();
3798 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3799 (VT.getSizeInBits() == 256 && NumElems != 8))
3802 // "i" is the value the indexed mask element must have
3803 for (unsigned i = 0; i != NumElems; i += 2)
3804 if (!isUndefOrEqual(Mask[i], i) ||
3805 !isUndefOrEqual(Mask[i+1], i))
3811 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3812 /// specifies a shuffle of elements that is suitable for input to 256-bit
3813 /// version of MOVDDUP.
3814 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3815 unsigned NumElts = VT.getVectorNumElements();
3817 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3820 for (unsigned i = 0; i != NumElts/2; ++i)
3821 if (!isUndefOrEqual(Mask[i], 0))
3823 for (unsigned i = NumElts/2; i != NumElts; ++i)
3824 if (!isUndefOrEqual(Mask[i], NumElts/2))
3829 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3830 /// specifies a shuffle of elements that is suitable for input to 128-bit
3831 /// version of MOVDDUP.
3832 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3833 if (VT.getSizeInBits() != 128)
3836 unsigned e = VT.getVectorNumElements() / 2;
3837 for (unsigned i = 0; i != e; ++i)
3838 if (!isUndefOrEqual(Mask[i], i))
3840 for (unsigned i = 0; i != e; ++i)
3841 if (!isUndefOrEqual(Mask[e+i], i))
3846 /// isVEXTRACTF128Index - Return true if the specified
3847 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3848 /// suitable for input to VEXTRACTF128.
3849 bool X86::isVEXTRACTF128Index(SDNode *N) {
3850 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3853 // The index should be aligned on a 128-bit boundary.
3855 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3857 unsigned VL = N->getValueType(0).getVectorNumElements();
3858 unsigned VBits = N->getValueType(0).getSizeInBits();
3859 unsigned ElSize = VBits / VL;
3860 bool Result = (Index * ElSize) % 128 == 0;
3865 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3866 /// operand specifies a subvector insert that is suitable for input to
3868 bool X86::isVINSERTF128Index(SDNode *N) {
3869 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3872 // The index should be aligned on a 128-bit boundary.
3874 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3876 unsigned VL = N->getValueType(0).getVectorNumElements();
3877 unsigned VBits = N->getValueType(0).getSizeInBits();
3878 unsigned ElSize = VBits / VL;
3879 bool Result = (Index * ElSize) % 128 == 0;
3884 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3885 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3886 /// Handles 128-bit and 256-bit.
3887 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3888 EVT VT = N->getValueType(0);
3890 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3891 "Unsupported vector type for PSHUF/SHUFP");
3893 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3894 // independently on 128-bit lanes.
3895 unsigned NumElts = VT.getVectorNumElements();
3896 unsigned NumLanes = VT.getSizeInBits()/128;
3897 unsigned NumLaneElts = NumElts/NumLanes;
3899 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3900 "Only supports 2 or 4 elements per lane");
3902 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3904 for (unsigned i = 0; i != NumElts; ++i) {
3905 int Elt = N->getMaskElt(i);
3906 if (Elt < 0) continue;
3908 unsigned ShAmt = i << Shift;
3909 if (ShAmt >= 8) ShAmt -= 8;
3910 Mask |= Elt << ShAmt;
3916 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3917 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3918 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3920 // 8 nodes, but we only care about the last 4.
3921 for (unsigned i = 7; i >= 4; --i) {
3922 int Val = N->getMaskElt(i);
3931 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3932 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3933 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3935 // 8 nodes, but we only care about the first 4.
3936 for (int i = 3; i >= 0; --i) {
3937 int Val = N->getMaskElt(i);
3946 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3947 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3948 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3949 EVT VT = SVOp->getValueType(0);
3950 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3952 unsigned NumElts = VT.getVectorNumElements();
3953 unsigned NumLanes = VT.getSizeInBits()/128;
3954 unsigned NumLaneElts = NumElts/NumLanes;
3958 for (i = 0; i != NumElts; ++i) {
3959 Val = SVOp->getMaskElt(i);
3963 if (Val >= (int)NumElts)
3964 Val -= NumElts - NumLaneElts;
3966 assert(Val - i > 0 && "PALIGNR imm should be positive");
3967 return (Val - i) * EltSize;
3970 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3971 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3973 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3974 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3975 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3978 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3980 EVT VecVT = N->getOperand(0).getValueType();
3981 EVT ElVT = VecVT.getVectorElementType();
3983 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3984 return Index / NumElemsPerChunk;
3987 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3988 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3990 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3991 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3992 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3995 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3997 EVT VecVT = N->getValueType(0);
3998 EVT ElVT = VecVT.getVectorElementType();
4000 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4001 return Index / NumElemsPerChunk;
4004 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4005 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4006 /// Handles 256-bit.
4007 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4008 EVT VT = N->getValueType(0);
4010 unsigned NumElts = VT.getVectorNumElements();
4012 assert((VT.is256BitVector() && NumElts == 4) &&
4013 "Unsupported vector type for VPERMQ/VPERMPD");
4016 for (unsigned i = 0; i != NumElts; ++i) {
4017 int Elt = N->getMaskElt(i);
4020 Mask |= Elt << (i*2);
4025 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4027 bool X86::isZeroNode(SDValue Elt) {
4028 return ((isa<ConstantSDNode>(Elt) &&
4029 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4030 (isa<ConstantFPSDNode>(Elt) &&
4031 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4034 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4035 /// their permute mask.
4036 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4037 SelectionDAG &DAG) {
4038 EVT VT = SVOp->getValueType(0);
4039 unsigned NumElems = VT.getVectorNumElements();
4040 SmallVector<int, 8> MaskVec;
4042 for (unsigned i = 0; i != NumElems; ++i) {
4043 int idx = SVOp->getMaskElt(i);
4045 MaskVec.push_back(idx);
4046 else if (idx < (int)NumElems)
4047 MaskVec.push_back(idx + NumElems);
4049 MaskVec.push_back(idx - NumElems);
4051 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4052 SVOp->getOperand(0), &MaskVec[0]);
4055 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4056 /// match movhlps. The lower half elements should come from upper half of
4057 /// V1 (and in order), and the upper half elements should come from the upper
4058 /// half of V2 (and in order).
4059 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4060 if (VT.getSizeInBits() != 128)
4062 if (VT.getVectorNumElements() != 4)
4064 for (unsigned i = 0, e = 2; i != e; ++i)
4065 if (!isUndefOrEqual(Mask[i], i+2))
4067 for (unsigned i = 2; i != 4; ++i)
4068 if (!isUndefOrEqual(Mask[i], i+4))
4073 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4074 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4076 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4077 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4079 N = N->getOperand(0).getNode();
4080 if (!ISD::isNON_EXTLoad(N))
4083 *LD = cast<LoadSDNode>(N);
4087 // Test whether the given value is a vector value which will be legalized
4089 static bool WillBeConstantPoolLoad(SDNode *N) {
4090 if (N->getOpcode() != ISD::BUILD_VECTOR)
4093 // Check for any non-constant elements.
4094 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4095 switch (N->getOperand(i).getNode()->getOpcode()) {
4097 case ISD::ConstantFP:
4104 // Vectors of all-zeros and all-ones are materialized with special
4105 // instructions rather than being loaded.
4106 return !ISD::isBuildVectorAllZeros(N) &&
4107 !ISD::isBuildVectorAllOnes(N);
4110 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4111 /// match movlp{s|d}. The lower half elements should come from lower half of
4112 /// V1 (and in order), and the upper half elements should come from the upper
4113 /// half of V2 (and in order). And since V1 will become the source of the
4114 /// MOVLP, it must be either a vector load or a scalar load to vector.
4115 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4116 ArrayRef<int> Mask, EVT VT) {
4117 if (VT.getSizeInBits() != 128)
4120 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4122 // Is V2 is a vector load, don't do this transformation. We will try to use
4123 // load folding shufps op.
4124 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4127 unsigned NumElems = VT.getVectorNumElements();
4129 if (NumElems != 2 && NumElems != 4)
4131 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4132 if (!isUndefOrEqual(Mask[i], i))
4134 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4135 if (!isUndefOrEqual(Mask[i], i+NumElems))
4140 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4142 static bool isSplatVector(SDNode *N) {
4143 if (N->getOpcode() != ISD::BUILD_VECTOR)
4146 SDValue SplatValue = N->getOperand(0);
4147 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4148 if (N->getOperand(i) != SplatValue)
4153 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4154 /// to an zero vector.
4155 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4156 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4157 SDValue V1 = N->getOperand(0);
4158 SDValue V2 = N->getOperand(1);
4159 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4160 for (unsigned i = 0; i != NumElems; ++i) {
4161 int Idx = N->getMaskElt(i);
4162 if (Idx >= (int)NumElems) {
4163 unsigned Opc = V2.getOpcode();
4164 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4166 if (Opc != ISD::BUILD_VECTOR ||
4167 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4169 } else if (Idx >= 0) {
4170 unsigned Opc = V1.getOpcode();
4171 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4173 if (Opc != ISD::BUILD_VECTOR ||
4174 !X86::isZeroNode(V1.getOperand(Idx)))
4181 /// getZeroVector - Returns a vector of specified type with all zero elements.
4183 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4184 SelectionDAG &DAG, DebugLoc dl) {
4185 assert(VT.isVector() && "Expected a vector type");
4186 unsigned Size = VT.getSizeInBits();
4188 // Always build SSE zero vectors as <4 x i32> bitcasted
4189 // to their dest type. This ensures they get CSE'd.
4191 if (Size == 128) { // SSE
4192 if (Subtarget->hasSSE2()) { // SSE2
4193 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4194 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4196 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4197 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4199 } else if (Size == 256) { // AVX
4200 if (Subtarget->hasAVX2()) { // AVX2
4201 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4202 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4203 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4205 // 256-bit logic and arithmetic instructions in AVX are all
4206 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4207 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4208 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4209 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4212 llvm_unreachable("Unexpected vector type");
4214 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4217 /// getOnesVector - Returns a vector of specified type with all bits set.
4218 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4219 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4220 /// Then bitcast to their original type, ensuring they get CSE'd.
4221 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4223 assert(VT.isVector() && "Expected a vector type");
4224 unsigned Size = VT.getSizeInBits();
4226 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4229 if (HasAVX2) { // AVX2
4230 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4231 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4233 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4234 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4236 } else if (Size == 128) {
4237 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4239 llvm_unreachable("Unexpected vector type");
4241 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4244 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4245 /// that point to V2 points to its first element.
4246 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4247 for (unsigned i = 0; i != NumElems; ++i) {
4248 if (Mask[i] > (int)NumElems) {
4254 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4255 /// operation of specified width.
4256 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4258 unsigned NumElems = VT.getVectorNumElements();
4259 SmallVector<int, 8> Mask;
4260 Mask.push_back(NumElems);
4261 for (unsigned i = 1; i != NumElems; ++i)
4263 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4266 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4267 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4269 unsigned NumElems = VT.getVectorNumElements();
4270 SmallVector<int, 8> Mask;
4271 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4273 Mask.push_back(i + NumElems);
4275 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4278 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4279 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4281 unsigned NumElems = VT.getVectorNumElements();
4282 SmallVector<int, 8> Mask;
4283 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4284 Mask.push_back(i + Half);
4285 Mask.push_back(i + NumElems + Half);
4287 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4290 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4291 // a generic shuffle instruction because the target has no such instructions.
4292 // Generate shuffles which repeat i16 and i8 several times until they can be
4293 // represented by v4f32 and then be manipulated by target suported shuffles.
4294 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4295 EVT VT = V.getValueType();
4296 int NumElems = VT.getVectorNumElements();
4297 DebugLoc dl = V.getDebugLoc();
4299 while (NumElems > 4) {
4300 if (EltNo < NumElems/2) {
4301 V = getUnpackl(DAG, dl, VT, V, V);
4303 V = getUnpackh(DAG, dl, VT, V, V);
4304 EltNo -= NumElems/2;
4311 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4312 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4313 EVT VT = V.getValueType();
4314 DebugLoc dl = V.getDebugLoc();
4315 unsigned Size = VT.getSizeInBits();
4318 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4319 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4320 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4322 } else if (Size == 256) {
4323 // To use VPERMILPS to splat scalars, the second half of indicies must
4324 // refer to the higher part, which is a duplication of the lower one,
4325 // because VPERMILPS can only handle in-lane permutations.
4326 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4327 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4329 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4330 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4333 llvm_unreachable("Vector size not supported");
4335 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4338 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4339 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4340 EVT SrcVT = SV->getValueType(0);
4341 SDValue V1 = SV->getOperand(0);
4342 DebugLoc dl = SV->getDebugLoc();
4344 int EltNo = SV->getSplatIndex();
4345 int NumElems = SrcVT.getVectorNumElements();
4346 unsigned Size = SrcVT.getSizeInBits();
4348 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4349 "Unknown how to promote splat for type");
4351 // Extract the 128-bit part containing the splat element and update
4352 // the splat element index when it refers to the higher register.
4354 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4355 if (EltNo >= NumElems/2)
4356 EltNo -= NumElems/2;
4359 // All i16 and i8 vector types can't be used directly by a generic shuffle
4360 // instruction because the target has no such instruction. Generate shuffles
4361 // which repeat i16 and i8 several times until they fit in i32, and then can
4362 // be manipulated by target suported shuffles.
4363 EVT EltVT = SrcVT.getVectorElementType();
4364 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4365 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4367 // Recreate the 256-bit vector and place the same 128-bit vector
4368 // into the low and high part. This is necessary because we want
4369 // to use VPERM* to shuffle the vectors
4371 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4374 return getLegalSplat(DAG, V1, EltNo);
4377 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4378 /// vector of zero or undef vector. This produces a shuffle where the low
4379 /// element of V2 is swizzled into the zero/undef vector, landing at element
4380 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4381 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4383 const X86Subtarget *Subtarget,
4384 SelectionDAG &DAG) {
4385 EVT VT = V2.getValueType();
4387 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4388 unsigned NumElems = VT.getVectorNumElements();
4389 SmallVector<int, 16> MaskVec;
4390 for (unsigned i = 0; i != NumElems; ++i)
4391 // If this is the insertion idx, put the low elt of V2 here.
4392 MaskVec.push_back(i == Idx ? NumElems : i);
4393 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4396 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4397 /// target specific opcode. Returns true if the Mask could be calculated.
4398 /// Sets IsUnary to true if only uses one source.
4399 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4400 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4401 unsigned NumElems = VT.getVectorNumElements();
4405 switch(N->getOpcode()) {
4407 ImmN = N->getOperand(N->getNumOperands()-1);
4408 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4410 case X86ISD::UNPCKH:
4411 DecodeUNPCKHMask(VT, Mask);
4413 case X86ISD::UNPCKL:
4414 DecodeUNPCKLMask(VT, Mask);
4416 case X86ISD::MOVHLPS:
4417 DecodeMOVHLPSMask(NumElems, Mask);
4419 case X86ISD::MOVLHPS:
4420 DecodeMOVLHPSMask(NumElems, Mask);
4422 case X86ISD::PSHUFD:
4423 case X86ISD::VPERMILP:
4424 ImmN = N->getOperand(N->getNumOperands()-1);
4425 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4428 case X86ISD::PSHUFHW:
4429 ImmN = N->getOperand(N->getNumOperands()-1);
4430 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4433 case X86ISD::PSHUFLW:
4434 ImmN = N->getOperand(N->getNumOperands()-1);
4435 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4439 case X86ISD::MOVSD: {
4440 // The index 0 always comes from the first element of the second source,
4441 // this is why MOVSS and MOVSD are used in the first place. The other
4442 // elements come from the other positions of the first source vector
4443 Mask.push_back(NumElems);
4444 for (unsigned i = 1; i != NumElems; ++i) {
4449 case X86ISD::VPERM2X128:
4450 ImmN = N->getOperand(N->getNumOperands()-1);
4451 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4452 if (Mask.empty()) return false;
4454 case X86ISD::MOVDDUP:
4455 case X86ISD::MOVLHPD:
4456 case X86ISD::MOVLPD:
4457 case X86ISD::MOVLPS:
4458 case X86ISD::MOVSHDUP:
4459 case X86ISD::MOVSLDUP:
4460 case X86ISD::PALIGN:
4461 // Not yet implemented
4463 default: llvm_unreachable("unknown target shuffle node");
4469 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4470 /// element of the result of the vector shuffle.
4471 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4474 return SDValue(); // Limit search depth.
4476 SDValue V = SDValue(N, 0);
4477 EVT VT = V.getValueType();
4478 unsigned Opcode = V.getOpcode();
4480 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4481 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4482 int Elt = SV->getMaskElt(Index);
4485 return DAG.getUNDEF(VT.getVectorElementType());
4487 unsigned NumElems = VT.getVectorNumElements();
4488 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4489 : SV->getOperand(1);
4490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4493 // Recurse into target specific vector shuffles to find scalars.
4494 if (isTargetShuffle(Opcode)) {
4495 unsigned NumElems = VT.getVectorNumElements();
4496 SmallVector<int, 16> ShuffleMask;
4500 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4503 int Elt = ShuffleMask[Index];
4505 return DAG.getUNDEF(VT.getVectorElementType());
4507 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4509 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4513 // Actual nodes that may contain scalar elements
4514 if (Opcode == ISD::BITCAST) {
4515 V = V.getOperand(0);
4516 EVT SrcVT = V.getValueType();
4517 unsigned NumElems = VT.getVectorNumElements();
4519 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4523 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4524 return (Index == 0) ? V.getOperand(0)
4525 : DAG.getUNDEF(VT.getVectorElementType());
4527 if (V.getOpcode() == ISD::BUILD_VECTOR)
4528 return V.getOperand(Index);
4533 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4534 /// shuffle operation which come from a consecutively from a zero. The
4535 /// search can start in two different directions, from left or right.
4537 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4538 bool ZerosFromLeft, SelectionDAG &DAG) {
4540 for (i = 0; i != NumElems; ++i) {
4541 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4542 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4543 if (!(Elt.getNode() &&
4544 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4551 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4552 /// correspond consecutively to elements from one of the vector operands,
4553 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4555 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4556 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4557 unsigned NumElems, unsigned &OpNum) {
4558 bool SeenV1 = false;
4559 bool SeenV2 = false;
4561 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4562 int Idx = SVOp->getMaskElt(i);
4563 // Ignore undef indicies
4567 if (Idx < (int)NumElems)
4572 // Only accept consecutive elements from the same vector
4573 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4577 OpNum = SeenV1 ? 0 : 1;
4581 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4582 /// logical left shift of a vector.
4583 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4584 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4585 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4586 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4587 false /* check zeros from right */, DAG);
4593 // Considering the elements in the mask that are not consecutive zeros,
4594 // check if they consecutively come from only one of the source vectors.
4596 // V1 = {X, A, B, C} 0
4598 // vector_shuffle V1, V2 <1, 2, 3, X>
4600 if (!isShuffleMaskConsecutive(SVOp,
4601 0, // Mask Start Index
4602 NumElems-NumZeros, // Mask End Index(exclusive)
4603 NumZeros, // Where to start looking in the src vector
4604 NumElems, // Number of elements in vector
4605 OpSrc)) // Which source operand ?
4610 ShVal = SVOp->getOperand(OpSrc);
4614 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4615 /// logical left shift of a vector.
4616 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4617 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4618 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4619 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4620 true /* check zeros from left */, DAG);
4626 // Considering the elements in the mask that are not consecutive zeros,
4627 // check if they consecutively come from only one of the source vectors.
4629 // 0 { A, B, X, X } = V2
4631 // vector_shuffle V1, V2 <X, X, 4, 5>
4633 if (!isShuffleMaskConsecutive(SVOp,
4634 NumZeros, // Mask Start Index
4635 NumElems, // Mask End Index(exclusive)
4636 0, // Where to start looking in the src vector
4637 NumElems, // Number of elements in vector
4638 OpSrc)) // Which source operand ?
4643 ShVal = SVOp->getOperand(OpSrc);
4647 /// isVectorShift - Returns true if the shuffle can be implemented as a
4648 /// logical left or right shift of a vector.
4649 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4650 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4651 // Although the logic below support any bitwidth size, there are no
4652 // shift instructions which handle more than 128-bit vectors.
4653 if (SVOp->getValueType(0).getSizeInBits() > 128)
4656 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4657 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4663 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4665 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4666 unsigned NumNonZero, unsigned NumZero,
4668 const X86Subtarget* Subtarget,
4669 const TargetLowering &TLI) {
4673 DebugLoc dl = Op.getDebugLoc();
4676 for (unsigned i = 0; i < 16; ++i) {
4677 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4678 if (ThisIsNonZero && First) {
4680 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4682 V = DAG.getUNDEF(MVT::v8i16);
4687 SDValue ThisElt(0, 0), LastElt(0, 0);
4688 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4689 if (LastIsNonZero) {
4690 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4691 MVT::i16, Op.getOperand(i-1));
4693 if (ThisIsNonZero) {
4694 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4695 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4696 ThisElt, DAG.getConstant(8, MVT::i8));
4698 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4702 if (ThisElt.getNode())
4703 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4704 DAG.getIntPtrConstant(i/2));
4708 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4711 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4713 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4714 unsigned NumNonZero, unsigned NumZero,
4716 const X86Subtarget* Subtarget,
4717 const TargetLowering &TLI) {
4721 DebugLoc dl = Op.getDebugLoc();
4724 for (unsigned i = 0; i < 8; ++i) {
4725 bool isNonZero = (NonZeros & (1 << i)) != 0;
4729 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4731 V = DAG.getUNDEF(MVT::v8i16);
4734 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4735 MVT::v8i16, V, Op.getOperand(i),
4736 DAG.getIntPtrConstant(i));
4743 /// getVShift - Return a vector logical shift node.
4745 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4746 unsigned NumBits, SelectionDAG &DAG,
4747 const TargetLowering &TLI, DebugLoc dl) {
4748 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4749 EVT ShVT = MVT::v2i64;
4750 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4751 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4752 return DAG.getNode(ISD::BITCAST, dl, VT,
4753 DAG.getNode(Opc, dl, ShVT, SrcOp,
4754 DAG.getConstant(NumBits,
4755 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4759 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4760 SelectionDAG &DAG) const {
4762 // Check if the scalar load can be widened into a vector load. And if
4763 // the address is "base + cst" see if the cst can be "absorbed" into
4764 // the shuffle mask.
4765 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4766 SDValue Ptr = LD->getBasePtr();
4767 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4769 EVT PVT = LD->getValueType(0);
4770 if (PVT != MVT::i32 && PVT != MVT::f32)
4775 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4776 FI = FINode->getIndex();
4778 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4779 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4780 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4781 Offset = Ptr.getConstantOperandVal(1);
4782 Ptr = Ptr.getOperand(0);
4787 // FIXME: 256-bit vector instructions don't require a strict alignment,
4788 // improve this code to support it better.
4789 unsigned RequiredAlign = VT.getSizeInBits()/8;
4790 SDValue Chain = LD->getChain();
4791 // Make sure the stack object alignment is at least 16 or 32.
4792 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4793 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4794 if (MFI->isFixedObjectIndex(FI)) {
4795 // Can't change the alignment. FIXME: It's possible to compute
4796 // the exact stack offset and reference FI + adjust offset instead.
4797 // If someone *really* cares about this. That's the way to implement it.
4800 MFI->setObjectAlignment(FI, RequiredAlign);
4804 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4805 // Ptr + (Offset & ~15).
4808 if ((Offset % RequiredAlign) & 3)
4810 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4812 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4813 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4815 int EltNo = (Offset - StartOffset) >> 2;
4816 unsigned NumElems = VT.getVectorNumElements();
4818 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4819 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4820 LD->getPointerInfo().getWithOffset(StartOffset),
4821 false, false, false, 0);
4823 SmallVector<int, 8> Mask;
4824 for (unsigned i = 0; i != NumElems; ++i)
4825 Mask.push_back(EltNo);
4827 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4833 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4834 /// vector of type 'VT', see if the elements can be replaced by a single large
4835 /// load which has the same value as a build_vector whose operands are 'elts'.
4837 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4839 /// FIXME: we'd also like to handle the case where the last elements are zero
4840 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4841 /// There's even a handy isZeroNode for that purpose.
4842 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4843 DebugLoc &DL, SelectionDAG &DAG) {
4844 EVT EltVT = VT.getVectorElementType();
4845 unsigned NumElems = Elts.size();
4847 LoadSDNode *LDBase = NULL;
4848 unsigned LastLoadedElt = -1U;
4850 // For each element in the initializer, see if we've found a load or an undef.
4851 // If we don't find an initial load element, or later load elements are
4852 // non-consecutive, bail out.
4853 for (unsigned i = 0; i < NumElems; ++i) {
4854 SDValue Elt = Elts[i];
4856 if (!Elt.getNode() ||
4857 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4860 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4862 LDBase = cast<LoadSDNode>(Elt.getNode());
4866 if (Elt.getOpcode() == ISD::UNDEF)
4869 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4870 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4875 // If we have found an entire vector of loads and undefs, then return a large
4876 // load of the entire vector width starting at the base pointer. If we found
4877 // consecutive loads for the low half, generate a vzext_load node.
4878 if (LastLoadedElt == NumElems - 1) {
4879 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4880 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4881 LDBase->getPointerInfo(),
4882 LDBase->isVolatile(), LDBase->isNonTemporal(),
4883 LDBase->isInvariant(), 0);
4884 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4885 LDBase->getPointerInfo(),
4886 LDBase->isVolatile(), LDBase->isNonTemporal(),
4887 LDBase->isInvariant(), LDBase->getAlignment());
4889 if (NumElems == 4 && LastLoadedElt == 1 &&
4890 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4891 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4892 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4894 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4895 LDBase->getPointerInfo(),
4896 LDBase->getAlignment(),
4897 false/*isVolatile*/, true/*ReadMem*/,
4899 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4904 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4905 /// to generate a splat value for the following cases:
4906 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4907 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4908 /// a scalar load, or a constant.
4909 /// The VBROADCAST node is returned when a pattern is found,
4910 /// or SDValue() otherwise.
4912 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4913 if (!Subtarget->hasAVX())
4916 EVT VT = Op.getValueType();
4917 DebugLoc dl = Op.getDebugLoc();
4922 switch (Op.getOpcode()) {
4924 // Unknown pattern found.
4927 case ISD::BUILD_VECTOR: {
4928 // The BUILD_VECTOR node must be a splat.
4929 if (!isSplatVector(Op.getNode()))
4932 Ld = Op.getOperand(0);
4933 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4934 Ld.getOpcode() == ISD::ConstantFP);
4936 // The suspected load node has several users. Make sure that all
4937 // of its users are from the BUILD_VECTOR node.
4938 // Constants may have multiple users.
4939 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4944 case ISD::VECTOR_SHUFFLE: {
4945 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4947 // Shuffles must have a splat mask where the first element is
4949 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4952 SDValue Sc = Op.getOperand(0);
4953 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4956 Ld = Sc.getOperand(0);
4957 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4958 Ld.getOpcode() == ISD::ConstantFP);
4960 // The scalar_to_vector node and the suspected
4961 // load node must have exactly one user.
4962 // Constants may have multiple users.
4963 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
4969 bool Is256 = VT.getSizeInBits() == 256;
4970 bool Is128 = VT.getSizeInBits() == 128;
4972 // Handle the broadcasting a single constant scalar from the constant pool
4973 // into a vector. On Sandybridge it is still better to load a constant vector
4974 // from the constant pool and not to broadcast it from a scalar.
4975 if (ConstSplatVal && Subtarget->hasAVX2()) {
4976 EVT CVT = Ld.getValueType();
4977 assert(!CVT.isVector() && "Must not broadcast a vector type");
4978 unsigned ScalarSize = CVT.getSizeInBits();
4980 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) ||
4981 (Is128 && (ScalarSize == 32))) {
4983 const Constant *C = 0;
4984 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4985 C = CI->getConstantIntValue();
4986 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4987 C = CF->getConstantFPValue();
4989 assert(C && "Invalid constant type");
4991 SDValue CP = DAG.getConstantPool(C, getPointerTy());
4992 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4993 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4994 MachinePointerInfo::getConstantPool(),
4995 false, false, false, Alignment);
4997 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5001 // The scalar source must be a normal load.
5002 if (!ISD::isNormalLoad(Ld.getNode()))
5005 // Reject loads that have uses of the chain result
5006 if (Ld->hasAnyUseOfValue(1))
5009 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5011 // VBroadcast to YMM
5012 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5013 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5015 // VBroadcast to XMM
5016 if (Is128 && (ScalarSize == 32))
5017 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5019 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5020 // double since there is vbroadcastsd xmm
5021 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5022 // VBroadcast to YMM
5023 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5024 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5026 // VBroadcast to XMM
5027 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5028 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5031 // Unsupported broadcast.
5036 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5037 DebugLoc dl = Op.getDebugLoc();
5039 EVT VT = Op.getValueType();
5040 EVT ExtVT = VT.getVectorElementType();
5041 unsigned NumElems = Op.getNumOperands();
5043 // Vectors containing all zeros can be matched by pxor and xorps later
5044 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5045 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5046 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5047 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5050 return getZeroVector(VT, Subtarget, DAG, dl);
5053 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5054 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5055 // vpcmpeqd on 256-bit vectors.
5056 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5057 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5060 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5063 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5064 if (Broadcast.getNode())
5067 unsigned EVTBits = ExtVT.getSizeInBits();
5069 unsigned NumZero = 0;
5070 unsigned NumNonZero = 0;
5071 unsigned NonZeros = 0;
5072 bool IsAllConstants = true;
5073 SmallSet<SDValue, 8> Values;
5074 for (unsigned i = 0; i < NumElems; ++i) {
5075 SDValue Elt = Op.getOperand(i);
5076 if (Elt.getOpcode() == ISD::UNDEF)
5079 if (Elt.getOpcode() != ISD::Constant &&
5080 Elt.getOpcode() != ISD::ConstantFP)
5081 IsAllConstants = false;
5082 if (X86::isZeroNode(Elt))
5085 NonZeros |= (1 << i);
5090 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5091 if (NumNonZero == 0)
5092 return DAG.getUNDEF(VT);
5094 // Special case for single non-zero, non-undef, element.
5095 if (NumNonZero == 1) {
5096 unsigned Idx = CountTrailingZeros_32(NonZeros);
5097 SDValue Item = Op.getOperand(Idx);
5099 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5100 // the value are obviously zero, truncate the value to i32 and do the
5101 // insertion that way. Only do this if the value is non-constant or if the
5102 // value is a constant being inserted into element 0. It is cheaper to do
5103 // a constant pool load than it is to do a movd + shuffle.
5104 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5105 (!IsAllConstants || Idx == 0)) {
5106 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5108 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5109 EVT VecVT = MVT::v4i32;
5110 unsigned VecElts = 4;
5112 // Truncate the value (which may itself be a constant) to i32, and
5113 // convert it to a vector with movd (S2V+shuffle to zero extend).
5114 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5115 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5116 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5118 // Now we have our 32-bit value zero extended in the low element of
5119 // a vector. If Idx != 0, swizzle it into place.
5121 SmallVector<int, 4> Mask;
5122 Mask.push_back(Idx);
5123 for (unsigned i = 1; i != VecElts; ++i)
5125 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5128 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5132 // If we have a constant or non-constant insertion into the low element of
5133 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5134 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5135 // depending on what the source datatype is.
5138 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5140 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5141 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5142 if (VT.getSizeInBits() == 256) {
5143 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5144 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5145 Item, DAG.getIntPtrConstant(0));
5147 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5148 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5149 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5150 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5153 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5154 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5155 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5156 if (VT.getSizeInBits() == 256) {
5157 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5158 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5160 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5161 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5163 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5167 // Is it a vector logical left shift?
5168 if (NumElems == 2 && Idx == 1 &&
5169 X86::isZeroNode(Op.getOperand(0)) &&
5170 !X86::isZeroNode(Op.getOperand(1))) {
5171 unsigned NumBits = VT.getSizeInBits();
5172 return getVShift(true, VT,
5173 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5174 VT, Op.getOperand(1)),
5175 NumBits/2, DAG, *this, dl);
5178 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5181 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5182 // is a non-constant being inserted into an element other than the low one,
5183 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5184 // movd/movss) to move this into the low element, then shuffle it into
5186 if (EVTBits == 32) {
5187 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5189 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5190 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5191 SmallVector<int, 8> MaskVec;
5192 for (unsigned i = 0; i < NumElems; i++)
5193 MaskVec.push_back(i == Idx ? 0 : 1);
5194 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5198 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5199 if (Values.size() == 1) {
5200 if (EVTBits == 32) {
5201 // Instead of a shuffle like this:
5202 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5203 // Check if it's possible to issue this instead.
5204 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5205 unsigned Idx = CountTrailingZeros_32(NonZeros);
5206 SDValue Item = Op.getOperand(Idx);
5207 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5208 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5213 // A vector full of immediates; various special cases are already
5214 // handled, so this is best done with a single constant-pool load.
5218 // For AVX-length vectors, build the individual 128-bit pieces and use
5219 // shuffles to put them in place.
5220 if (VT.getSizeInBits() == 256) {
5221 SmallVector<SDValue, 32> V;
5222 for (unsigned i = 0; i != NumElems; ++i)
5223 V.push_back(Op.getOperand(i));
5225 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5227 // Build both the lower and upper subvector.
5228 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5229 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5232 // Recreate the wider vector with the lower and upper part.
5233 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5236 // Let legalizer expand 2-wide build_vectors.
5237 if (EVTBits == 64) {
5238 if (NumNonZero == 1) {
5239 // One half is zero or undef.
5240 unsigned Idx = CountTrailingZeros_32(NonZeros);
5241 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5242 Op.getOperand(Idx));
5243 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5248 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5249 if (EVTBits == 8 && NumElems == 16) {
5250 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5252 if (V.getNode()) return V;
5255 if (EVTBits == 16 && NumElems == 8) {
5256 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5258 if (V.getNode()) return V;
5261 // If element VT is == 32 bits, turn it into a number of shuffles.
5262 SmallVector<SDValue, 8> V(NumElems);
5263 if (NumElems == 4 && NumZero > 0) {
5264 for (unsigned i = 0; i < 4; ++i) {
5265 bool isZero = !(NonZeros & (1 << i));
5267 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5269 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5272 for (unsigned i = 0; i < 2; ++i) {
5273 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5276 V[i] = V[i*2]; // Must be a zero vector.
5279 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5282 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5285 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5290 bool Reverse1 = (NonZeros & 0x3) == 2;
5291 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5295 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5296 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5298 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5301 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5302 // Check for a build vector of consecutive loads.
5303 for (unsigned i = 0; i < NumElems; ++i)
5304 V[i] = Op.getOperand(i);
5306 // Check for elements which are consecutive loads.
5307 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5311 // For SSE 4.1, use insertps to put the high elements into the low element.
5312 if (getSubtarget()->hasSSE41()) {
5314 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5315 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5317 Result = DAG.getUNDEF(VT);
5319 for (unsigned i = 1; i < NumElems; ++i) {
5320 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5321 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5322 Op.getOperand(i), DAG.getIntPtrConstant(i));
5327 // Otherwise, expand into a number of unpckl*, start by extending each of
5328 // our (non-undef) elements to the full vector width with the element in the
5329 // bottom slot of the vector (which generates no code for SSE).
5330 for (unsigned i = 0; i < NumElems; ++i) {
5331 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5332 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5334 V[i] = DAG.getUNDEF(VT);
5337 // Next, we iteratively mix elements, e.g. for v4f32:
5338 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5339 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5340 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5341 unsigned EltStride = NumElems >> 1;
5342 while (EltStride != 0) {
5343 for (unsigned i = 0; i < EltStride; ++i) {
5344 // If V[i+EltStride] is undef and this is the first round of mixing,
5345 // then it is safe to just drop this shuffle: V[i] is already in the
5346 // right place, the one element (since it's the first round) being
5347 // inserted as undef can be dropped. This isn't safe for successive
5348 // rounds because they will permute elements within both vectors.
5349 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5350 EltStride == NumElems/2)
5353 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5362 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5363 // them in a MMX register. This is better than doing a stack convert.
5364 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5365 DebugLoc dl = Op.getDebugLoc();
5366 EVT ResVT = Op.getValueType();
5368 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5369 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5371 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5372 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5373 InVec = Op.getOperand(1);
5374 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5375 unsigned NumElts = ResVT.getVectorNumElements();
5376 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5377 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5378 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5380 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5381 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5382 Mask[0] = 0; Mask[1] = 2;
5383 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5385 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5388 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5389 // to create 256-bit vectors from two other 128-bit ones.
5390 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5391 DebugLoc dl = Op.getDebugLoc();
5392 EVT ResVT = Op.getValueType();
5394 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5396 SDValue V1 = Op.getOperand(0);
5397 SDValue V2 = Op.getOperand(1);
5398 unsigned NumElems = ResVT.getVectorNumElements();
5400 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5404 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5405 EVT ResVT = Op.getValueType();
5407 assert(Op.getNumOperands() == 2);
5408 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5409 "Unsupported CONCAT_VECTORS for value type");
5411 // We support concatenate two MMX registers and place them in a MMX register.
5412 // This is better than doing a stack convert.
5413 if (ResVT.is128BitVector())
5414 return LowerMMXCONCAT_VECTORS(Op, DAG);
5416 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5417 // from two other 128-bit ones.
5418 return LowerAVXCONCAT_VECTORS(Op, DAG);
5421 // Try to lower a shuffle node into a simple blend instruction.
5422 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5423 const X86Subtarget *Subtarget,
5424 SelectionDAG &DAG) {
5425 SDValue V1 = SVOp->getOperand(0);
5426 SDValue V2 = SVOp->getOperand(1);
5427 DebugLoc dl = SVOp->getDebugLoc();
5428 MVT VT = SVOp->getValueType(0).getSimpleVT();
5429 unsigned NumElems = VT.getVectorNumElements();
5431 if (!Subtarget->hasSSE41())
5437 switch (VT.SimpleTy) {
5438 default: return SDValue();
5440 ISDNo = X86ISD::BLENDPW;
5445 ISDNo = X86ISD::BLENDPS;
5450 ISDNo = X86ISD::BLENDPD;
5455 if (!Subtarget->hasAVX())
5457 ISDNo = X86ISD::BLENDPS;
5462 if (!Subtarget->hasAVX())
5464 ISDNo = X86ISD::BLENDPD;
5468 assert(ISDNo && "Invalid Op Number");
5470 unsigned MaskVals = 0;
5472 for (unsigned i = 0; i != NumElems; ++i) {
5473 int EltIdx = SVOp->getMaskElt(i);
5474 if (EltIdx == (int)i || EltIdx < 0)
5476 else if (EltIdx == (int)(i + NumElems))
5477 continue; // Bit is set to zero;
5482 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5483 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5484 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5485 DAG.getConstant(MaskVals, MVT::i32));
5486 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5489 // v8i16 shuffles - Prefer shuffles in the following order:
5490 // 1. [all] pshuflw, pshufhw, optional move
5491 // 2. [ssse3] 1 x pshufb
5492 // 3. [ssse3] 2 x pshufb + 1 x por
5493 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5495 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5496 SelectionDAG &DAG) const {
5497 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5498 SDValue V1 = SVOp->getOperand(0);
5499 SDValue V2 = SVOp->getOperand(1);
5500 DebugLoc dl = SVOp->getDebugLoc();
5501 SmallVector<int, 8> MaskVals;
5503 // Determine if more than 1 of the words in each of the low and high quadwords
5504 // of the result come from the same quadword of one of the two inputs. Undef
5505 // mask values count as coming from any quadword, for better codegen.
5506 unsigned LoQuad[] = { 0, 0, 0, 0 };
5507 unsigned HiQuad[] = { 0, 0, 0, 0 };
5508 std::bitset<4> InputQuads;
5509 for (unsigned i = 0; i < 8; ++i) {
5510 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5511 int EltIdx = SVOp->getMaskElt(i);
5512 MaskVals.push_back(EltIdx);
5521 InputQuads.set(EltIdx / 4);
5524 int BestLoQuad = -1;
5525 unsigned MaxQuad = 1;
5526 for (unsigned i = 0; i < 4; ++i) {
5527 if (LoQuad[i] > MaxQuad) {
5529 MaxQuad = LoQuad[i];
5533 int BestHiQuad = -1;
5535 for (unsigned i = 0; i < 4; ++i) {
5536 if (HiQuad[i] > MaxQuad) {
5538 MaxQuad = HiQuad[i];
5542 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5543 // of the two input vectors, shuffle them into one input vector so only a
5544 // single pshufb instruction is necessary. If There are more than 2 input
5545 // quads, disable the next transformation since it does not help SSSE3.
5546 bool V1Used = InputQuads[0] || InputQuads[1];
5547 bool V2Used = InputQuads[2] || InputQuads[3];
5548 if (Subtarget->hasSSSE3()) {
5549 if (InputQuads.count() == 2 && V1Used && V2Used) {
5550 BestLoQuad = InputQuads[0] ? 0 : 1;
5551 BestHiQuad = InputQuads[2] ? 2 : 3;
5553 if (InputQuads.count() > 2) {
5559 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5560 // the shuffle mask. If a quad is scored as -1, that means that it contains
5561 // words from all 4 input quadwords.
5563 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5565 BestLoQuad < 0 ? 0 : BestLoQuad,
5566 BestHiQuad < 0 ? 1 : BestHiQuad
5568 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5569 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5570 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5571 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5573 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5574 // source words for the shuffle, to aid later transformations.
5575 bool AllWordsInNewV = true;
5576 bool InOrder[2] = { true, true };
5577 for (unsigned i = 0; i != 8; ++i) {
5578 int idx = MaskVals[i];
5580 InOrder[i/4] = false;
5581 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5583 AllWordsInNewV = false;
5587 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5588 if (AllWordsInNewV) {
5589 for (int i = 0; i != 8; ++i) {
5590 int idx = MaskVals[i];
5593 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5594 if ((idx != i) && idx < 4)
5596 if ((idx != i) && idx > 3)
5605 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5606 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5607 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5608 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5609 unsigned TargetMask = 0;
5610 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5611 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5612 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5613 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5614 getShufflePSHUFLWImmediate(SVOp);
5615 V1 = NewV.getOperand(0);
5616 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5620 // If we have SSSE3, and all words of the result are from 1 input vector,
5621 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5622 // is present, fall back to case 4.
5623 if (Subtarget->hasSSSE3()) {
5624 SmallVector<SDValue,16> pshufbMask;
5626 // If we have elements from both input vectors, set the high bit of the
5627 // shuffle mask element to zero out elements that come from V2 in the V1
5628 // mask, and elements that come from V1 in the V2 mask, so that the two
5629 // results can be OR'd together.
5630 bool TwoInputs = V1Used && V2Used;
5631 for (unsigned i = 0; i != 8; ++i) {
5632 int EltIdx = MaskVals[i] * 2;
5633 if (TwoInputs && (EltIdx >= 16)) {
5634 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5635 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5638 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5639 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5641 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5642 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5643 DAG.getNode(ISD::BUILD_VECTOR, dl,
5644 MVT::v16i8, &pshufbMask[0], 16));
5646 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5648 // Calculate the shuffle mask for the second input, shuffle it, and
5649 // OR it with the first shuffled input.
5651 for (unsigned i = 0; i != 8; ++i) {
5652 int EltIdx = MaskVals[i] * 2;
5654 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5655 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5658 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5659 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5661 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5662 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5663 DAG.getNode(ISD::BUILD_VECTOR, dl,
5664 MVT::v16i8, &pshufbMask[0], 16));
5665 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5666 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5669 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5670 // and update MaskVals with new element order.
5671 std::bitset<8> InOrder;
5672 if (BestLoQuad >= 0) {
5673 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5674 for (int i = 0; i != 4; ++i) {
5675 int idx = MaskVals[i];
5678 } else if ((idx / 4) == BestLoQuad) {
5683 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5686 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5687 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5688 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5690 getShufflePSHUFLWImmediate(SVOp), DAG);
5694 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5695 // and update MaskVals with the new element order.
5696 if (BestHiQuad >= 0) {
5697 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5698 for (unsigned i = 4; i != 8; ++i) {
5699 int idx = MaskVals[i];
5702 } else if ((idx / 4) == BestHiQuad) {
5703 MaskV[i] = (idx & 3) + 4;
5707 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5710 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5711 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5712 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5714 getShufflePSHUFHWImmediate(SVOp), DAG);
5718 // In case BestHi & BestLo were both -1, which means each quadword has a word
5719 // from each of the four input quadwords, calculate the InOrder bitvector now
5720 // before falling through to the insert/extract cleanup.
5721 if (BestLoQuad == -1 && BestHiQuad == -1) {
5723 for (int i = 0; i != 8; ++i)
5724 if (MaskVals[i] < 0 || MaskVals[i] == i)
5728 // The other elements are put in the right place using pextrw and pinsrw.
5729 for (unsigned i = 0; i != 8; ++i) {
5732 int EltIdx = MaskVals[i];
5735 SDValue ExtOp = (EltIdx < 8)
5736 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5737 DAG.getIntPtrConstant(EltIdx))
5738 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5739 DAG.getIntPtrConstant(EltIdx - 8));
5740 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5741 DAG.getIntPtrConstant(i));
5746 // v16i8 shuffles - Prefer shuffles in the following order:
5747 // 1. [ssse3] 1 x pshufb
5748 // 2. [ssse3] 2 x pshufb + 1 x por
5749 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5751 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5753 const X86TargetLowering &TLI) {
5754 SDValue V1 = SVOp->getOperand(0);
5755 SDValue V2 = SVOp->getOperand(1);
5756 DebugLoc dl = SVOp->getDebugLoc();
5757 ArrayRef<int> MaskVals = SVOp->getMask();
5759 // If we have SSSE3, case 1 is generated when all result bytes come from
5760 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5761 // present, fall back to case 3.
5762 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5765 for (unsigned i = 0; i < 16; ++i) {
5766 int EltIdx = MaskVals[i];
5775 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5776 if (TLI.getSubtarget()->hasSSSE3()) {
5777 SmallVector<SDValue,16> pshufbMask;
5779 // If all result elements are from one input vector, then only translate
5780 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5782 // Otherwise, we have elements from both input vectors, and must zero out
5783 // elements that come from V2 in the first mask, and V1 in the second mask
5784 // so that we can OR them together.
5785 bool TwoInputs = !(V1Only || V2Only);
5786 for (unsigned i = 0; i != 16; ++i) {
5787 int EltIdx = MaskVals[i];
5788 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5789 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5792 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5794 // If all the elements are from V2, assign it to V1 and return after
5795 // building the first pshufb.
5798 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5799 DAG.getNode(ISD::BUILD_VECTOR, dl,
5800 MVT::v16i8, &pshufbMask[0], 16));
5804 // Calculate the shuffle mask for the second input, shuffle it, and
5805 // OR it with the first shuffled input.
5807 for (unsigned i = 0; i != 16; ++i) {
5808 int EltIdx = MaskVals[i];
5810 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5813 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5815 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5816 DAG.getNode(ISD::BUILD_VECTOR, dl,
5817 MVT::v16i8, &pshufbMask[0], 16));
5818 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5821 // No SSSE3 - Calculate in place words and then fix all out of place words
5822 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5823 // the 16 different words that comprise the two doublequadword input vectors.
5824 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5825 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5826 SDValue NewV = V2Only ? V2 : V1;
5827 for (int i = 0; i != 8; ++i) {
5828 int Elt0 = MaskVals[i*2];
5829 int Elt1 = MaskVals[i*2+1];
5831 // This word of the result is all undef, skip it.
5832 if (Elt0 < 0 && Elt1 < 0)
5835 // This word of the result is already in the correct place, skip it.
5836 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5838 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5841 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5842 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5845 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5846 // using a single extract together, load it and store it.
5847 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5848 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5849 DAG.getIntPtrConstant(Elt1 / 2));
5850 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5851 DAG.getIntPtrConstant(i));
5855 // If Elt1 is defined, extract it from the appropriate source. If the
5856 // source byte is not also odd, shift the extracted word left 8 bits
5857 // otherwise clear the bottom 8 bits if we need to do an or.
5859 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5860 DAG.getIntPtrConstant(Elt1 / 2));
5861 if ((Elt1 & 1) == 0)
5862 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5864 TLI.getShiftAmountTy(InsElt.getValueType())));
5866 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5867 DAG.getConstant(0xFF00, MVT::i16));
5869 // If Elt0 is defined, extract it from the appropriate source. If the
5870 // source byte is not also even, shift the extracted word right 8 bits. If
5871 // Elt1 was also defined, OR the extracted values together before
5872 // inserting them in the result.
5874 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5875 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5876 if ((Elt0 & 1) != 0)
5877 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5879 TLI.getShiftAmountTy(InsElt0.getValueType())));
5881 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5882 DAG.getConstant(0x00FF, MVT::i16));
5883 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5886 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5887 DAG.getIntPtrConstant(i));
5889 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5892 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5893 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5894 /// done when every pair / quad of shuffle mask elements point to elements in
5895 /// the right sequence. e.g.
5896 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5898 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5899 SelectionDAG &DAG, DebugLoc dl) {
5900 EVT VT = SVOp->getValueType(0);
5901 SDValue V1 = SVOp->getOperand(0);
5902 SDValue V2 = SVOp->getOperand(1);
5903 unsigned NumElems = VT.getVectorNumElements();
5904 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5906 switch (VT.getSimpleVT().SimpleTy) {
5907 default: llvm_unreachable("Unexpected!");
5908 case MVT::v4f32: NewVT = MVT::v2f64; break;
5909 case MVT::v4i32: NewVT = MVT::v2i64; break;
5910 case MVT::v8i16: NewVT = MVT::v4i32; break;
5911 case MVT::v16i8: NewVT = MVT::v4i32; break;
5914 int Scale = NumElems / NewWidth;
5915 SmallVector<int, 8> MaskVec;
5916 for (unsigned i = 0; i < NumElems; i += Scale) {
5918 for (int j = 0; j < Scale; ++j) {
5919 int EltIdx = SVOp->getMaskElt(i+j);
5923 StartIdx = EltIdx - (EltIdx % Scale);
5924 if (EltIdx != StartIdx + j)
5928 MaskVec.push_back(-1);
5930 MaskVec.push_back(StartIdx / Scale);
5933 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5934 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5935 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5938 /// getVZextMovL - Return a zero-extending vector move low node.
5940 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5941 SDValue SrcOp, SelectionDAG &DAG,
5942 const X86Subtarget *Subtarget, DebugLoc dl) {
5943 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5944 LoadSDNode *LD = NULL;
5945 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5946 LD = dyn_cast<LoadSDNode>(SrcOp);
5948 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5950 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5951 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5952 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5953 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5954 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5956 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5957 return DAG.getNode(ISD::BITCAST, dl, VT,
5958 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5959 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5967 return DAG.getNode(ISD::BITCAST, dl, VT,
5968 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5969 DAG.getNode(ISD::BITCAST, dl,
5973 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5974 /// which could not be matched by any known target speficic shuffle
5976 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5977 EVT VT = SVOp->getValueType(0);
5979 unsigned NumElems = VT.getVectorNumElements();
5980 unsigned NumLaneElems = NumElems / 2;
5982 DebugLoc dl = SVOp->getDebugLoc();
5983 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5984 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5987 SmallVector<int, 16> Mask;
5988 for (unsigned l = 0; l < 2; ++l) {
5989 // Build a shuffle mask for the output, discovering on the fly which
5990 // input vectors to use as shuffle operands (recorded in InputUsed).
5991 // If building a suitable shuffle vector proves too hard, then bail
5992 // out with useBuildVector set.
5993 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5994 unsigned LaneStart = l * NumLaneElems;
5995 for (unsigned i = 0; i != NumLaneElems; ++i) {
5996 // The mask element. This indexes into the input.
5997 int Idx = SVOp->getMaskElt(i+LaneStart);
5999 // the mask element does not index into any input vector.
6004 // The input vector this mask element indexes into.
6005 int Input = Idx / NumLaneElems;
6007 // Turn the index into an offset from the start of the input vector.
6008 Idx -= Input * NumLaneElems;
6010 // Find or create a shuffle vector operand to hold this input.
6012 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6013 if (InputUsed[OpNo] == Input)
6014 // This input vector is already an operand.
6016 if (InputUsed[OpNo] < 0) {
6017 // Create a new operand for this input vector.
6018 InputUsed[OpNo] = Input;
6023 if (OpNo >= array_lengthof(InputUsed)) {
6024 // More than two input vectors used! Give up.
6028 // Add the mask index for the new shuffle vector.
6029 Mask.push_back(Idx + OpNo * NumLaneElems);
6032 if (InputUsed[0] < 0) {
6033 // No input vectors were used! The result is undefined.
6034 Shufs[l] = DAG.getUNDEF(NVT);
6036 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6037 (InputUsed[0] % 2) * NumLaneElems,
6039 // If only one input was used, use an undefined vector for the other.
6040 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6041 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6042 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6043 // At least one input vector was used. Create a new shuffle vector.
6044 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6050 // Concatenate the result back
6051 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]);
6054 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6055 /// 4 elements, and match them with several different shuffle types.
6057 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6058 SDValue V1 = SVOp->getOperand(0);
6059 SDValue V2 = SVOp->getOperand(1);
6060 DebugLoc dl = SVOp->getDebugLoc();
6061 EVT VT = SVOp->getValueType(0);
6063 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6065 std::pair<int, int> Locs[4];
6066 int Mask1[] = { -1, -1, -1, -1 };
6067 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6071 for (unsigned i = 0; i != 4; ++i) {
6072 int Idx = PermMask[i];
6074 Locs[i] = std::make_pair(-1, -1);
6076 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6078 Locs[i] = std::make_pair(0, NumLo);
6082 Locs[i] = std::make_pair(1, NumHi);
6084 Mask1[2+NumHi] = Idx;
6090 if (NumLo <= 2 && NumHi <= 2) {
6091 // If no more than two elements come from either vector. This can be
6092 // implemented with two shuffles. First shuffle gather the elements.
6093 // The second shuffle, which takes the first shuffle as both of its
6094 // vector operands, put the elements into the right order.
6095 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6097 int Mask2[] = { -1, -1, -1, -1 };
6099 for (unsigned i = 0; i != 4; ++i)
6100 if (Locs[i].first != -1) {
6101 unsigned Idx = (i < 2) ? 0 : 4;
6102 Idx += Locs[i].first * 2 + Locs[i].second;
6106 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6109 if (NumLo == 3 || NumHi == 3) {
6110 // Otherwise, we must have three elements from one vector, call it X, and
6111 // one element from the other, call it Y. First, use a shufps to build an
6112 // intermediate vector with the one element from Y and the element from X
6113 // that will be in the same half in the final destination (the indexes don't
6114 // matter). Then, use a shufps to build the final vector, taking the half
6115 // containing the element from Y from the intermediate, and the other half
6118 // Normalize it so the 3 elements come from V1.
6119 CommuteVectorShuffleMask(PermMask, 4);
6123 // Find the element from V2.
6125 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6126 int Val = PermMask[HiIndex];
6133 Mask1[0] = PermMask[HiIndex];
6135 Mask1[2] = PermMask[HiIndex^1];
6137 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6140 Mask1[0] = PermMask[0];
6141 Mask1[1] = PermMask[1];
6142 Mask1[2] = HiIndex & 1 ? 6 : 4;
6143 Mask1[3] = HiIndex & 1 ? 4 : 6;
6144 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6147 Mask1[0] = HiIndex & 1 ? 2 : 0;
6148 Mask1[1] = HiIndex & 1 ? 0 : 2;
6149 Mask1[2] = PermMask[2];
6150 Mask1[3] = PermMask[3];
6155 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6158 // Break it into (shuffle shuffle_hi, shuffle_lo).
6159 int LoMask[] = { -1, -1, -1, -1 };
6160 int HiMask[] = { -1, -1, -1, -1 };
6162 int *MaskPtr = LoMask;
6163 unsigned MaskIdx = 0;
6166 for (unsigned i = 0; i != 4; ++i) {
6173 int Idx = PermMask[i];
6175 Locs[i] = std::make_pair(-1, -1);
6176 } else if (Idx < 4) {
6177 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6178 MaskPtr[LoIdx] = Idx;
6181 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6182 MaskPtr[HiIdx] = Idx;
6187 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6188 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6189 int MaskOps[] = { -1, -1, -1, -1 };
6190 for (unsigned i = 0; i != 4; ++i)
6191 if (Locs[i].first != -1)
6192 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6193 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6196 static bool MayFoldVectorLoad(SDValue V) {
6197 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6198 V = V.getOperand(0);
6199 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6200 V = V.getOperand(0);
6201 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6202 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6203 // BUILD_VECTOR (load), undef
6204 V = V.getOperand(0);
6210 // FIXME: the version above should always be used. Since there's
6211 // a bug where several vector shuffles can't be folded because the
6212 // DAG is not updated during lowering and a node claims to have two
6213 // uses while it only has one, use this version, and let isel match
6214 // another instruction if the load really happens to have more than
6215 // one use. Remove this version after this bug get fixed.
6216 // rdar://8434668, PR8156
6217 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6218 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6219 V = V.getOperand(0);
6220 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6221 V = V.getOperand(0);
6222 if (ISD::isNormalLoad(V.getNode()))
6228 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6229 EVT VT = Op.getValueType();
6231 // Canonizalize to v2f64.
6232 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6233 return DAG.getNode(ISD::BITCAST, dl, VT,
6234 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6239 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6241 SDValue V1 = Op.getOperand(0);
6242 SDValue V2 = Op.getOperand(1);
6243 EVT VT = Op.getValueType();
6245 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6247 if (HasSSE2 && VT == MVT::v2f64)
6248 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6250 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6251 return DAG.getNode(ISD::BITCAST, dl, VT,
6252 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6253 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6254 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6258 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6259 SDValue V1 = Op.getOperand(0);
6260 SDValue V2 = Op.getOperand(1);
6261 EVT VT = Op.getValueType();
6263 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6264 "unsupported shuffle type");
6266 if (V2.getOpcode() == ISD::UNDEF)
6270 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6274 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6275 SDValue V1 = Op.getOperand(0);
6276 SDValue V2 = Op.getOperand(1);
6277 EVT VT = Op.getValueType();
6278 unsigned NumElems = VT.getVectorNumElements();
6280 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6281 // operand of these instructions is only memory, so check if there's a
6282 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6284 bool CanFoldLoad = false;
6286 // Trivial case, when V2 comes from a load.
6287 if (MayFoldVectorLoad(V2))
6290 // When V1 is a load, it can be folded later into a store in isel, example:
6291 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6293 // (MOVLPSmr addr:$src1, VR128:$src2)
6294 // So, recognize this potential and also use MOVLPS or MOVLPD
6295 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6298 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6300 if (HasSSE2 && NumElems == 2)
6301 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6304 // If we don't care about the second element, procede to use movss.
6305 if (SVOp->getMaskElt(1) != -1)
6306 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6309 // movl and movlp will both match v2i64, but v2i64 is never matched by
6310 // movl earlier because we make it strict to avoid messing with the movlp load
6311 // folding logic (see the code above getMOVLP call). Match it here then,
6312 // this is horrible, but will stay like this until we move all shuffle
6313 // matching to x86 specific nodes. Note that for the 1st condition all
6314 // types are matched with movsd.
6316 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6317 // as to remove this logic from here, as much as possible
6318 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6319 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6320 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6323 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6325 // Invert the operand order and use SHUFPS to match it.
6326 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6327 getShuffleSHUFImmediate(SVOp), DAG);
6331 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6333 EVT VT = Op.getValueType();
6334 DebugLoc dl = Op.getDebugLoc();
6335 SDValue V1 = Op.getOperand(0);
6336 SDValue V2 = Op.getOperand(1);
6338 if (isZeroShuffle(SVOp))
6339 return getZeroVector(VT, Subtarget, DAG, dl);
6341 // Handle splat operations
6342 if (SVOp->isSplat()) {
6343 unsigned NumElem = VT.getVectorNumElements();
6344 int Size = VT.getSizeInBits();
6346 // Use vbroadcast whenever the splat comes from a foldable load
6347 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6348 if (Broadcast.getNode())
6351 // Handle splats by matching through known shuffle masks
6352 if ((Size == 128 && NumElem <= 4) ||
6353 (Size == 256 && NumElem < 8))
6356 // All remaning splats are promoted to target supported vector shuffles.
6357 return PromoteSplat(SVOp, DAG);
6360 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6362 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6363 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6364 if (NewOp.getNode())
6365 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6366 } else if ((VT == MVT::v4i32 ||
6367 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6368 // FIXME: Figure out a cleaner way to do this.
6369 // Try to make use of movq to zero out the top part.
6370 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6371 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6372 if (NewOp.getNode()) {
6373 EVT NewVT = NewOp.getValueType();
6374 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6375 NewVT, true, false))
6376 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6377 DAG, Subtarget, dl);
6379 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6380 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6381 if (NewOp.getNode()) {
6382 EVT NewVT = NewOp.getValueType();
6383 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6384 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6385 DAG, Subtarget, dl);
6393 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6395 SDValue V1 = Op.getOperand(0);
6396 SDValue V2 = Op.getOperand(1);
6397 EVT VT = Op.getValueType();
6398 DebugLoc dl = Op.getDebugLoc();
6399 unsigned NumElems = VT.getVectorNumElements();
6400 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6401 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6402 bool V1IsSplat = false;
6403 bool V2IsSplat = false;
6404 bool HasSSE2 = Subtarget->hasSSE2();
6405 bool HasAVX = Subtarget->hasAVX();
6406 bool HasAVX2 = Subtarget->hasAVX2();
6407 MachineFunction &MF = DAG.getMachineFunction();
6408 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6410 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6412 if (V1IsUndef && V2IsUndef)
6413 return DAG.getUNDEF(VT);
6415 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6417 // Vector shuffle lowering takes 3 steps:
6419 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6420 // narrowing and commutation of operands should be handled.
6421 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6423 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6424 // so the shuffle can be broken into other shuffles and the legalizer can
6425 // try the lowering again.
6427 // The general idea is that no vector_shuffle operation should be left to
6428 // be matched during isel, all of them must be converted to a target specific
6431 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6432 // narrowing and commutation of operands should be handled. The actual code
6433 // doesn't include all of those, work in progress...
6434 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6435 if (NewOp.getNode())
6438 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6440 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6441 // unpckh_undef). Only use pshufd if speed is more important than size.
6442 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6443 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6444 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6445 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6447 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6448 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6449 return getMOVDDup(Op, dl, V1, DAG);
6451 if (isMOVHLPS_v_undef_Mask(M, VT))
6452 return getMOVHighToLow(Op, dl, DAG);
6454 // Use to match splats
6455 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6456 (VT == MVT::v2f64 || VT == MVT::v2i64))
6457 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6459 if (isPSHUFDMask(M, VT)) {
6460 // The actual implementation will match the mask in the if above and then
6461 // during isel it can match several different instructions, not only pshufd
6462 // as its name says, sad but true, emulate the behavior for now...
6463 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6464 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6466 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6468 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6469 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6471 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6472 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6474 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6478 // Check if this can be converted into a logical shift.
6479 bool isLeft = false;
6482 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6483 if (isShift && ShVal.hasOneUse()) {
6484 // If the shifted value has multiple uses, it may be cheaper to use
6485 // v_set0 + movlhps or movhlps, etc.
6486 EVT EltVT = VT.getVectorElementType();
6487 ShAmt *= EltVT.getSizeInBits();
6488 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6491 if (isMOVLMask(M, VT)) {
6492 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6493 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6494 if (!isMOVLPMask(M, VT)) {
6495 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6496 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6498 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6499 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6503 // FIXME: fold these into legal mask.
6504 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6505 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6507 if (isMOVHLPSMask(M, VT))
6508 return getMOVHighToLow(Op, dl, DAG);
6510 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6511 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6513 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6514 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6516 if (isMOVLPMask(M, VT))
6517 return getMOVLP(Op, dl, DAG, HasSSE2);
6519 if (ShouldXformToMOVHLPS(M, VT) ||
6520 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6521 return CommuteVectorShuffle(SVOp, DAG);
6524 // No better options. Use a vshldq / vsrldq.
6525 EVT EltVT = VT.getVectorElementType();
6526 ShAmt *= EltVT.getSizeInBits();
6527 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6530 bool Commuted = false;
6531 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6532 // 1,1,1,1 -> v8i16 though.
6533 V1IsSplat = isSplatVector(V1.getNode());
6534 V2IsSplat = isSplatVector(V2.getNode());
6536 // Canonicalize the splat or undef, if present, to be on the RHS.
6537 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6538 CommuteVectorShuffleMask(M, NumElems);
6540 std::swap(V1IsSplat, V2IsSplat);
6544 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6545 // Shuffling low element of v1 into undef, just return v1.
6548 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6549 // the instruction selector will not match, so get a canonical MOVL with
6550 // swapped operands to undo the commute.
6551 return getMOVL(DAG, dl, VT, V2, V1);
6554 if (isUNPCKLMask(M, VT, HasAVX2))
6555 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6557 if (isUNPCKHMask(M, VT, HasAVX2))
6558 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6561 // Normalize mask so all entries that point to V2 points to its first
6562 // element then try to match unpck{h|l} again. If match, return a
6563 // new vector_shuffle with the corrected mask.p
6564 SmallVector<int, 8> NewMask(M.begin(), M.end());
6565 NormalizeMask(NewMask, NumElems);
6566 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6567 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6568 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6569 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6573 // Commute is back and try unpck* again.
6574 // FIXME: this seems wrong.
6575 CommuteVectorShuffleMask(M, NumElems);
6577 std::swap(V1IsSplat, V2IsSplat);
6580 if (isUNPCKLMask(M, VT, HasAVX2))
6581 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6583 if (isUNPCKHMask(M, VT, HasAVX2))
6584 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6587 // Normalize the node to match x86 shuffle ops if needed
6588 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6589 return CommuteVectorShuffle(SVOp, DAG);
6591 // The checks below are all present in isShuffleMaskLegal, but they are
6592 // inlined here right now to enable us to directly emit target specific
6593 // nodes, and remove one by one until they don't return Op anymore.
6595 if (isPALIGNRMask(M, VT, Subtarget))
6596 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6597 getShufflePALIGNRImmediate(SVOp),
6600 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6601 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6602 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6603 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6606 if (isPSHUFHWMask(M, VT, HasAVX2))
6607 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6608 getShufflePSHUFHWImmediate(SVOp),
6611 if (isPSHUFLWMask(M, VT, HasAVX2))
6612 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6613 getShufflePSHUFLWImmediate(SVOp),
6616 if (isSHUFPMask(M, VT, HasAVX))
6617 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6618 getShuffleSHUFImmediate(SVOp), DAG);
6620 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6621 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6622 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6623 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6625 //===--------------------------------------------------------------------===//
6626 // Generate target specific nodes for 128 or 256-bit shuffles only
6627 // supported in the AVX instruction set.
6630 // Handle VMOVDDUPY permutations
6631 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6632 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6634 // Handle VPERMILPS/D* permutations
6635 if (isVPERMILPMask(M, VT, HasAVX)) {
6636 if (HasAVX2 && VT == MVT::v8i32)
6637 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6638 getShuffleSHUFImmediate(SVOp), DAG);
6639 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6640 getShuffleSHUFImmediate(SVOp), DAG);
6643 // Handle VPERM2F128/VPERM2I128 permutations
6644 if (isVPERM2X128Mask(M, VT, HasAVX))
6645 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6646 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6648 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6649 if (BlendOp.getNode())
6652 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6653 SmallVector<SDValue, 8> permclMask;
6654 for (unsigned i = 0; i != 8; ++i) {
6655 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6657 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6659 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6660 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6661 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6664 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6665 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6666 getShuffleCLImmediate(SVOp), DAG);
6669 //===--------------------------------------------------------------------===//
6670 // Since no target specific shuffle was selected for this generic one,
6671 // lower it into other known shuffles. FIXME: this isn't true yet, but
6672 // this is the plan.
6675 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6676 if (VT == MVT::v8i16) {
6677 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6678 if (NewOp.getNode())
6682 if (VT == MVT::v16i8) {
6683 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6684 if (NewOp.getNode())
6688 // Handle all 128-bit wide vectors with 4 elements, and match them with
6689 // several different shuffle types.
6690 if (NumElems == 4 && VT.getSizeInBits() == 128)
6691 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6693 // Handle general 256-bit shuffles
6694 if (VT.is256BitVector())
6695 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6701 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6702 SelectionDAG &DAG) const {
6703 EVT VT = Op.getValueType();
6704 DebugLoc dl = Op.getDebugLoc();
6706 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6709 if (VT.getSizeInBits() == 8) {
6710 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6711 Op.getOperand(0), Op.getOperand(1));
6712 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6713 DAG.getValueType(VT));
6714 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6717 if (VT.getSizeInBits() == 16) {
6718 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6719 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6721 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6722 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6723 DAG.getNode(ISD::BITCAST, dl,
6727 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6728 Op.getOperand(0), Op.getOperand(1));
6729 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6730 DAG.getValueType(VT));
6731 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6734 if (VT == MVT::f32) {
6735 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6736 // the result back to FR32 register. It's only worth matching if the
6737 // result has a single use which is a store or a bitcast to i32. And in
6738 // the case of a store, it's not worth it if the index is a constant 0,
6739 // because a MOVSSmr can be used instead, which is smaller and faster.
6740 if (!Op.hasOneUse())
6742 SDNode *User = *Op.getNode()->use_begin();
6743 if ((User->getOpcode() != ISD::STORE ||
6744 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6745 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6746 (User->getOpcode() != ISD::BITCAST ||
6747 User->getValueType(0) != MVT::i32))
6749 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6750 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6753 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6756 if (VT == MVT::i32 || VT == MVT::i64) {
6757 // ExtractPS/pextrq works with constant index.
6758 if (isa<ConstantSDNode>(Op.getOperand(1)))
6766 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6767 SelectionDAG &DAG) const {
6768 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6771 SDValue Vec = Op.getOperand(0);
6772 EVT VecVT = Vec.getValueType();
6774 // If this is a 256-bit vector result, first extract the 128-bit vector and
6775 // then extract the element from the 128-bit vector.
6776 if (VecVT.getSizeInBits() == 256) {
6777 DebugLoc dl = Op.getNode()->getDebugLoc();
6778 unsigned NumElems = VecVT.getVectorNumElements();
6779 SDValue Idx = Op.getOperand(1);
6780 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6782 // Get the 128-bit vector.
6783 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6785 if (IdxVal >= NumElems/2)
6786 IdxVal -= NumElems/2;
6787 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6788 DAG.getConstant(IdxVal, MVT::i32));
6791 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6793 if (Subtarget->hasSSE41()) {
6794 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6799 EVT VT = Op.getValueType();
6800 DebugLoc dl = Op.getDebugLoc();
6801 // TODO: handle v16i8.
6802 if (VT.getSizeInBits() == 16) {
6803 SDValue Vec = Op.getOperand(0);
6804 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6806 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6807 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6808 DAG.getNode(ISD::BITCAST, dl,
6811 // Transform it so it match pextrw which produces a 32-bit result.
6812 EVT EltVT = MVT::i32;
6813 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6814 Op.getOperand(0), Op.getOperand(1));
6815 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6816 DAG.getValueType(VT));
6817 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6820 if (VT.getSizeInBits() == 32) {
6821 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6825 // SHUFPS the element to the lowest double word, then movss.
6826 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6827 EVT VVT = Op.getOperand(0).getValueType();
6828 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6829 DAG.getUNDEF(VVT), Mask);
6830 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6831 DAG.getIntPtrConstant(0));
6834 if (VT.getSizeInBits() == 64) {
6835 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6836 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6837 // to match extract_elt for f64.
6838 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6842 // UNPCKHPD the element to the lowest double word, then movsd.
6843 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6844 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6845 int Mask[2] = { 1, -1 };
6846 EVT VVT = Op.getOperand(0).getValueType();
6847 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6848 DAG.getUNDEF(VVT), Mask);
6849 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6850 DAG.getIntPtrConstant(0));
6857 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6858 SelectionDAG &DAG) const {
6859 EVT VT = Op.getValueType();
6860 EVT EltVT = VT.getVectorElementType();
6861 DebugLoc dl = Op.getDebugLoc();
6863 SDValue N0 = Op.getOperand(0);
6864 SDValue N1 = Op.getOperand(1);
6865 SDValue N2 = Op.getOperand(2);
6867 if (VT.getSizeInBits() == 256)
6870 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6871 isa<ConstantSDNode>(N2)) {
6873 if (VT == MVT::v8i16)
6874 Opc = X86ISD::PINSRW;
6875 else if (VT == MVT::v16i8)
6876 Opc = X86ISD::PINSRB;
6878 Opc = X86ISD::PINSRB;
6880 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6882 if (N1.getValueType() != MVT::i32)
6883 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6884 if (N2.getValueType() != MVT::i32)
6885 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6886 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6889 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6890 // Bits [7:6] of the constant are the source select. This will always be
6891 // zero here. The DAG Combiner may combine an extract_elt index into these
6892 // bits. For example (insert (extract, 3), 2) could be matched by putting
6893 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6894 // Bits [5:4] of the constant are the destination select. This is the
6895 // value of the incoming immediate.
6896 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6897 // combine either bitwise AND or insert of float 0.0 to set these bits.
6898 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6899 // Create this as a scalar to vector..
6900 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6901 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6904 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6905 // PINSR* works with constant index.
6912 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6913 EVT VT = Op.getValueType();
6914 EVT EltVT = VT.getVectorElementType();
6916 DebugLoc dl = Op.getDebugLoc();
6917 SDValue N0 = Op.getOperand(0);
6918 SDValue N1 = Op.getOperand(1);
6919 SDValue N2 = Op.getOperand(2);
6921 // If this is a 256-bit vector result, first extract the 128-bit vector,
6922 // insert the element into the extracted half and then place it back.
6923 if (VT.getSizeInBits() == 256) {
6924 if (!isa<ConstantSDNode>(N2))
6927 // Get the desired 128-bit vector half.
6928 unsigned NumElems = VT.getVectorNumElements();
6929 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6930 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
6932 // Insert the element into the desired half.
6933 bool Upper = IdxVal >= NumElems/2;
6934 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
6935 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
6937 // Insert the changed part back to the 256-bit vector
6938 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
6941 if (Subtarget->hasSSE41())
6942 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6944 if (EltVT == MVT::i8)
6947 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6948 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6949 // as its second argument.
6950 if (N1.getValueType() != MVT::i32)
6951 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6952 if (N2.getValueType() != MVT::i32)
6953 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6954 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6960 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6961 LLVMContext *Context = DAG.getContext();
6962 DebugLoc dl = Op.getDebugLoc();
6963 EVT OpVT = Op.getValueType();
6965 // If this is a 256-bit vector result, first insert into a 128-bit
6966 // vector and then insert into the 256-bit vector.
6967 if (OpVT.getSizeInBits() > 128) {
6968 // Insert into a 128-bit vector.
6969 EVT VT128 = EVT::getVectorVT(*Context,
6970 OpVT.getVectorElementType(),
6971 OpVT.getVectorNumElements() / 2);
6973 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6975 // Insert the 128-bit vector.
6976 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
6979 if (OpVT == MVT::v1i64 &&
6980 Op.getOperand(0).getValueType() == MVT::i64)
6981 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6983 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6984 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!");
6985 return DAG.getNode(ISD::BITCAST, dl, OpVT,
6986 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6989 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6990 // a simple subregister reference or explicit instructions to grab
6991 // upper bits of a vector.
6993 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6994 if (Subtarget->hasAVX()) {
6995 DebugLoc dl = Op.getNode()->getDebugLoc();
6996 SDValue Vec = Op.getNode()->getOperand(0);
6997 SDValue Idx = Op.getNode()->getOperand(1);
6999 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
7000 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
7001 isa<ConstantSDNode>(Idx)) {
7002 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7003 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7009 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7010 // simple superregister reference or explicit instructions to insert
7011 // the upper bits of a vector.
7013 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7014 if (Subtarget->hasAVX()) {
7015 DebugLoc dl = Op.getNode()->getDebugLoc();
7016 SDValue Vec = Op.getNode()->getOperand(0);
7017 SDValue SubVec = Op.getNode()->getOperand(1);
7018 SDValue Idx = Op.getNode()->getOperand(2);
7020 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
7021 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7022 isa<ConstantSDNode>(Idx)) {
7023 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7024 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7030 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7031 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7032 // one of the above mentioned nodes. It has to be wrapped because otherwise
7033 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7034 // be used to form addressing mode. These wrapped nodes will be selected
7037 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7038 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7040 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7042 unsigned char OpFlag = 0;
7043 unsigned WrapperKind = X86ISD::Wrapper;
7044 CodeModel::Model M = getTargetMachine().getCodeModel();
7046 if (Subtarget->isPICStyleRIPRel() &&
7047 (M == CodeModel::Small || M == CodeModel::Kernel))
7048 WrapperKind = X86ISD::WrapperRIP;
7049 else if (Subtarget->isPICStyleGOT())
7050 OpFlag = X86II::MO_GOTOFF;
7051 else if (Subtarget->isPICStyleStubPIC())
7052 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7054 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7056 CP->getOffset(), OpFlag);
7057 DebugLoc DL = CP->getDebugLoc();
7058 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7059 // With PIC, the address is actually $g + Offset.
7061 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7062 DAG.getNode(X86ISD::GlobalBaseReg,
7063 DebugLoc(), getPointerTy()),
7070 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7071 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7073 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7075 unsigned char OpFlag = 0;
7076 unsigned WrapperKind = X86ISD::Wrapper;
7077 CodeModel::Model M = getTargetMachine().getCodeModel();
7079 if (Subtarget->isPICStyleRIPRel() &&
7080 (M == CodeModel::Small || M == CodeModel::Kernel))
7081 WrapperKind = X86ISD::WrapperRIP;
7082 else if (Subtarget->isPICStyleGOT())
7083 OpFlag = X86II::MO_GOTOFF;
7084 else if (Subtarget->isPICStyleStubPIC())
7085 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7087 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7089 DebugLoc DL = JT->getDebugLoc();
7090 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7092 // With PIC, the address is actually $g + Offset.
7094 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7095 DAG.getNode(X86ISD::GlobalBaseReg,
7096 DebugLoc(), getPointerTy()),
7103 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7104 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7106 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7108 unsigned char OpFlag = 0;
7109 unsigned WrapperKind = X86ISD::Wrapper;
7110 CodeModel::Model M = getTargetMachine().getCodeModel();
7112 if (Subtarget->isPICStyleRIPRel() &&
7113 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7114 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7115 OpFlag = X86II::MO_GOTPCREL;
7116 WrapperKind = X86ISD::WrapperRIP;
7117 } else if (Subtarget->isPICStyleGOT()) {
7118 OpFlag = X86II::MO_GOT;
7119 } else if (Subtarget->isPICStyleStubPIC()) {
7120 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7121 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7122 OpFlag = X86II::MO_DARWIN_NONLAZY;
7125 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7127 DebugLoc DL = Op.getDebugLoc();
7128 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7131 // With PIC, the address is actually $g + Offset.
7132 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7133 !Subtarget->is64Bit()) {
7134 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7135 DAG.getNode(X86ISD::GlobalBaseReg,
7136 DebugLoc(), getPointerTy()),
7140 // For symbols that require a load from a stub to get the address, emit the
7142 if (isGlobalStubReference(OpFlag))
7143 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7144 MachinePointerInfo::getGOT(), false, false, false, 0);
7150 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7151 // Create the TargetBlockAddressAddress node.
7152 unsigned char OpFlags =
7153 Subtarget->ClassifyBlockAddressReference();
7154 CodeModel::Model M = getTargetMachine().getCodeModel();
7155 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7156 DebugLoc dl = Op.getDebugLoc();
7157 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7158 /*isTarget=*/true, OpFlags);
7160 if (Subtarget->isPICStyleRIPRel() &&
7161 (M == CodeModel::Small || M == CodeModel::Kernel))
7162 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7164 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7166 // With PIC, the address is actually $g + Offset.
7167 if (isGlobalRelativeToPICBase(OpFlags)) {
7168 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7169 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7177 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7179 SelectionDAG &DAG) const {
7180 // Create the TargetGlobalAddress node, folding in the constant
7181 // offset if it is legal.
7182 unsigned char OpFlags =
7183 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7184 CodeModel::Model M = getTargetMachine().getCodeModel();
7186 if (OpFlags == X86II::MO_NO_FLAG &&
7187 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7188 // A direct static reference to a global.
7189 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7192 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7195 if (Subtarget->isPICStyleRIPRel() &&
7196 (M == CodeModel::Small || M == CodeModel::Kernel))
7197 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7199 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7201 // With PIC, the address is actually $g + Offset.
7202 if (isGlobalRelativeToPICBase(OpFlags)) {
7203 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7204 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7208 // For globals that require a load from a stub to get the address, emit the
7210 if (isGlobalStubReference(OpFlags))
7211 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7212 MachinePointerInfo::getGOT(), false, false, false, 0);
7214 // If there was a non-zero offset that we didn't fold, create an explicit
7217 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7218 DAG.getConstant(Offset, getPointerTy()));
7224 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7225 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7226 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7227 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7231 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7232 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7233 unsigned char OperandFlags) {
7234 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7235 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7236 DebugLoc dl = GA->getDebugLoc();
7237 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7238 GA->getValueType(0),
7242 SDValue Ops[] = { Chain, TGA, *InFlag };
7243 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7245 SDValue Ops[] = { Chain, TGA };
7246 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7249 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7250 MFI->setAdjustsStack(true);
7252 SDValue Flag = Chain.getValue(1);
7253 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7256 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7258 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7261 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7262 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7263 DAG.getNode(X86ISD::GlobalBaseReg,
7264 DebugLoc(), PtrVT), InFlag);
7265 InFlag = Chain.getValue(1);
7267 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7270 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7272 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7274 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7275 X86::RAX, X86II::MO_TLSGD);
7278 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7279 // "local exec" model.
7280 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7281 const EVT PtrVT, TLSModel::Model model,
7283 DebugLoc dl = GA->getDebugLoc();
7285 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7286 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7287 is64Bit ? 257 : 256));
7289 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7290 DAG.getIntPtrConstant(0),
7291 MachinePointerInfo(Ptr),
7292 false, false, false, 0);
7294 unsigned char OperandFlags = 0;
7295 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7297 unsigned WrapperKind = X86ISD::Wrapper;
7298 if (model == TLSModel::LocalExec) {
7299 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7300 } else if (is64Bit) {
7301 assert(model == TLSModel::InitialExec);
7302 OperandFlags = X86II::MO_GOTTPOFF;
7303 WrapperKind = X86ISD::WrapperRIP;
7305 assert(model == TLSModel::InitialExec);
7306 OperandFlags = X86II::MO_INDNTPOFF;
7309 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7311 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7312 GA->getValueType(0),
7313 GA->getOffset(), OperandFlags);
7314 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7316 if (model == TLSModel::InitialExec)
7317 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7318 MachinePointerInfo::getGOT(), false, false, false, 0);
7320 // The address of the thread local variable is the add of the thread
7321 // pointer with the offset of the variable.
7322 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7326 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7328 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7329 const GlobalValue *GV = GA->getGlobal();
7331 if (Subtarget->isTargetELF()) {
7332 // TODO: implement the "local dynamic" model
7333 // TODO: implement the "initial exec"model for pic executables
7335 // If GV is an alias then use the aliasee for determining
7336 // thread-localness.
7337 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7338 GV = GA->resolveAliasedGlobal(false);
7340 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7343 case TLSModel::GeneralDynamic:
7344 case TLSModel::LocalDynamic: // not implemented
7345 if (Subtarget->is64Bit())
7346 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7347 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7349 case TLSModel::InitialExec:
7350 case TLSModel::LocalExec:
7351 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7352 Subtarget->is64Bit());
7354 llvm_unreachable("Unknown TLS model.");
7357 if (Subtarget->isTargetDarwin()) {
7358 // Darwin only has one model of TLS. Lower to that.
7359 unsigned char OpFlag = 0;
7360 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7361 X86ISD::WrapperRIP : X86ISD::Wrapper;
7363 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7365 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7366 !Subtarget->is64Bit();
7368 OpFlag = X86II::MO_TLVP_PIC_BASE;
7370 OpFlag = X86II::MO_TLVP;
7371 DebugLoc DL = Op.getDebugLoc();
7372 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7373 GA->getValueType(0),
7374 GA->getOffset(), OpFlag);
7375 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7377 // With PIC32, the address is actually $g + Offset.
7379 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7380 DAG.getNode(X86ISD::GlobalBaseReg,
7381 DebugLoc(), getPointerTy()),
7384 // Lowering the machine isd will make sure everything is in the right
7386 SDValue Chain = DAG.getEntryNode();
7387 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7388 SDValue Args[] = { Chain, Offset };
7389 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7391 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7392 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7393 MFI->setAdjustsStack(true);
7395 // And our return value (tls address) is in the standard call return value
7397 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7398 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7402 if (Subtarget->isTargetWindows()) {
7403 // Just use the implicit TLS architecture
7404 // Need to generate someting similar to:
7405 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7407 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7408 // mov rcx, qword [rdx+rcx*8]
7409 // mov eax, .tls$:tlsvar
7410 // [rax+rcx] contains the address
7411 // Windows 64bit: gs:0x58
7412 // Windows 32bit: fs:__tls_array
7414 // If GV is an alias then use the aliasee for determining
7415 // thread-localness.
7416 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7417 GV = GA->resolveAliasedGlobal(false);
7418 DebugLoc dl = GA->getDebugLoc();
7419 SDValue Chain = DAG.getEntryNode();
7421 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7422 // %gs:0x58 (64-bit).
7423 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7424 ? Type::getInt8PtrTy(*DAG.getContext(),
7426 : Type::getInt32PtrTy(*DAG.getContext(),
7429 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7430 Subtarget->is64Bit()
7431 ? DAG.getIntPtrConstant(0x58)
7432 : DAG.getExternalSymbol("_tls_array",
7434 MachinePointerInfo(Ptr),
7435 false, false, false, 0);
7437 // Load the _tls_index variable
7438 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7439 if (Subtarget->is64Bit())
7440 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7441 IDX, MachinePointerInfo(), MVT::i32,
7444 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7445 false, false, false, 0);
7447 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7449 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7451 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7452 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7453 false, false, false, 0);
7455 // Get the offset of start of .tls section
7456 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7457 GA->getValueType(0),
7458 GA->getOffset(), X86II::MO_SECREL);
7459 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7461 // The address of the thread local variable is the add of the thread
7462 // pointer with the offset of the variable.
7463 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7466 llvm_unreachable("TLS not implemented for this target.");
7470 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7471 /// and take a 2 x i32 value to shift plus a shift amount.
7472 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7473 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7474 EVT VT = Op.getValueType();
7475 unsigned VTBits = VT.getSizeInBits();
7476 DebugLoc dl = Op.getDebugLoc();
7477 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7478 SDValue ShOpLo = Op.getOperand(0);
7479 SDValue ShOpHi = Op.getOperand(1);
7480 SDValue ShAmt = Op.getOperand(2);
7481 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7482 DAG.getConstant(VTBits - 1, MVT::i8))
7483 : DAG.getConstant(0, VT);
7486 if (Op.getOpcode() == ISD::SHL_PARTS) {
7487 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7488 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7490 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7491 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7494 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7495 DAG.getConstant(VTBits, MVT::i8));
7496 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7497 AndNode, DAG.getConstant(0, MVT::i8));
7500 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7501 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7502 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7504 if (Op.getOpcode() == ISD::SHL_PARTS) {
7505 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7506 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7508 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7509 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7512 SDValue Ops[2] = { Lo, Hi };
7513 return DAG.getMergeValues(Ops, 2, dl);
7516 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7517 SelectionDAG &DAG) const {
7518 EVT SrcVT = Op.getOperand(0).getValueType();
7520 if (SrcVT.isVector())
7523 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7524 "Unknown SINT_TO_FP to lower!");
7526 // These are really Legal; return the operand so the caller accepts it as
7528 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7530 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7531 Subtarget->is64Bit()) {
7535 DebugLoc dl = Op.getDebugLoc();
7536 unsigned Size = SrcVT.getSizeInBits()/8;
7537 MachineFunction &MF = DAG.getMachineFunction();
7538 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7539 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7540 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7542 MachinePointerInfo::getFixedStack(SSFI),
7544 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7547 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7549 SelectionDAG &DAG) const {
7551 DebugLoc DL = Op.getDebugLoc();
7553 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7555 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7557 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7559 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7561 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7562 MachineMemOperand *MMO;
7564 int SSFI = FI->getIndex();
7566 DAG.getMachineFunction()
7567 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7568 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7570 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7571 StackSlot = StackSlot.getOperand(1);
7573 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7574 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7576 Tys, Ops, array_lengthof(Ops),
7580 Chain = Result.getValue(1);
7581 SDValue InFlag = Result.getValue(2);
7583 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7584 // shouldn't be necessary except that RFP cannot be live across
7585 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7586 MachineFunction &MF = DAG.getMachineFunction();
7587 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7588 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7589 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7590 Tys = DAG.getVTList(MVT::Other);
7592 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7594 MachineMemOperand *MMO =
7595 DAG.getMachineFunction()
7596 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7597 MachineMemOperand::MOStore, SSFISize, SSFISize);
7599 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7600 Ops, array_lengthof(Ops),
7601 Op.getValueType(), MMO);
7602 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7603 MachinePointerInfo::getFixedStack(SSFI),
7604 false, false, false, 0);
7610 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7611 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7612 SelectionDAG &DAG) const {
7613 // This algorithm is not obvious. Here it is what we're trying to output:
7616 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7617 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7621 pshufd $0x4e, %xmm0, %xmm1
7626 DebugLoc dl = Op.getDebugLoc();
7627 LLVMContext *Context = DAG.getContext();
7629 // Build some magic constants.
7630 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7631 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7632 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7634 SmallVector<Constant*,2> CV1;
7636 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7638 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7639 Constant *C1 = ConstantVector::get(CV1);
7640 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7642 // Load the 64-bit value into an XMM register.
7643 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7645 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7646 MachinePointerInfo::getConstantPool(),
7647 false, false, false, 16);
7648 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7649 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7652 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7653 MachinePointerInfo::getConstantPool(),
7654 false, false, false, 16);
7655 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7656 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7659 if (Subtarget->hasSSE3()) {
7660 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7661 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7663 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7664 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7666 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7667 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7671 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7672 DAG.getIntPtrConstant(0));
7675 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7676 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7677 SelectionDAG &DAG) const {
7678 DebugLoc dl = Op.getDebugLoc();
7679 // FP constant to bias correct the final result.
7680 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7683 // Load the 32-bit value into an XMM register.
7684 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7687 // Zero out the upper parts of the register.
7688 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7690 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7691 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7692 DAG.getIntPtrConstant(0));
7694 // Or the load with the bias.
7695 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7696 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7697 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7699 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7700 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7701 MVT::v2f64, Bias)));
7702 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7703 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7704 DAG.getIntPtrConstant(0));
7706 // Subtract the bias.
7707 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7709 // Handle final rounding.
7710 EVT DestVT = Op.getValueType();
7712 if (DestVT.bitsLT(MVT::f64))
7713 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7714 DAG.getIntPtrConstant(0));
7715 if (DestVT.bitsGT(MVT::f64))
7716 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7718 // Handle final rounding.
7722 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7723 SelectionDAG &DAG) const {
7724 SDValue N0 = Op.getOperand(0);
7725 DebugLoc dl = Op.getDebugLoc();
7727 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7728 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7729 // the optimization here.
7730 if (DAG.SignBitIsZero(N0))
7731 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7733 EVT SrcVT = N0.getValueType();
7734 EVT DstVT = Op.getValueType();
7735 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7736 return LowerUINT_TO_FP_i64(Op, DAG);
7737 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7738 return LowerUINT_TO_FP_i32(Op, DAG);
7739 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7742 // Make a 64-bit buffer, and use it to build an FILD.
7743 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7744 if (SrcVT == MVT::i32) {
7745 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7746 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7747 getPointerTy(), StackSlot, WordOff);
7748 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7749 StackSlot, MachinePointerInfo(),
7751 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7752 OffsetSlot, MachinePointerInfo(),
7754 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7758 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7759 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7760 StackSlot, MachinePointerInfo(),
7762 // For i64 source, we need to add the appropriate power of 2 if the input
7763 // was negative. This is the same as the optimization in
7764 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7765 // we must be careful to do the computation in x87 extended precision, not
7766 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7767 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7768 MachineMemOperand *MMO =
7769 DAG.getMachineFunction()
7770 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7771 MachineMemOperand::MOLoad, 8, 8);
7773 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7774 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7775 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7778 APInt FF(32, 0x5F800000ULL);
7780 // Check whether the sign bit is set.
7781 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7782 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7785 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7786 SDValue FudgePtr = DAG.getConstantPool(
7787 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7790 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7791 SDValue Zero = DAG.getIntPtrConstant(0);
7792 SDValue Four = DAG.getIntPtrConstant(4);
7793 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7795 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7797 // Load the value out, extending it from f32 to f80.
7798 // FIXME: Avoid the extend by constructing the right constant pool?
7799 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7800 FudgePtr, MachinePointerInfo::getConstantPool(),
7801 MVT::f32, false, false, 4);
7802 // Extend everything to 80 bits to force it to be done on x87.
7803 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7804 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7807 std::pair<SDValue,SDValue> X86TargetLowering::
7808 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7809 DebugLoc DL = Op.getDebugLoc();
7811 EVT DstTy = Op.getValueType();
7813 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7814 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7818 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7819 DstTy.getSimpleVT() >= MVT::i16 &&
7820 "Unknown FP_TO_INT to lower!");
7822 // These are really Legal.
7823 if (DstTy == MVT::i32 &&
7824 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7825 return std::make_pair(SDValue(), SDValue());
7826 if (Subtarget->is64Bit() &&
7827 DstTy == MVT::i64 &&
7828 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7829 return std::make_pair(SDValue(), SDValue());
7831 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7832 // stack slot, or into the FTOL runtime function.
7833 MachineFunction &MF = DAG.getMachineFunction();
7834 unsigned MemSize = DstTy.getSizeInBits()/8;
7835 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7836 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7839 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7840 Opc = X86ISD::WIN_FTOL;
7842 switch (DstTy.getSimpleVT().SimpleTy) {
7843 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7844 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7845 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7846 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7849 SDValue Chain = DAG.getEntryNode();
7850 SDValue Value = Op.getOperand(0);
7851 EVT TheVT = Op.getOperand(0).getValueType();
7852 // FIXME This causes a redundant load/store if the SSE-class value is already
7853 // in memory, such as if it is on the callstack.
7854 if (isScalarFPTypeInSSEReg(TheVT)) {
7855 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7856 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7857 MachinePointerInfo::getFixedStack(SSFI),
7859 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7861 Chain, StackSlot, DAG.getValueType(TheVT)
7864 MachineMemOperand *MMO =
7865 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7866 MachineMemOperand::MOLoad, MemSize, MemSize);
7867 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7869 Chain = Value.getValue(1);
7870 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7871 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7874 MachineMemOperand *MMO =
7875 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7876 MachineMemOperand::MOStore, MemSize, MemSize);
7878 if (Opc != X86ISD::WIN_FTOL) {
7879 // Build the FP_TO_INT*_IN_MEM
7880 SDValue Ops[] = { Chain, Value, StackSlot };
7881 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7882 Ops, 3, DstTy, MMO);
7883 return std::make_pair(FIST, StackSlot);
7885 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7886 DAG.getVTList(MVT::Other, MVT::Glue),
7888 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7889 MVT::i32, ftol.getValue(1));
7890 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7891 MVT::i32, eax.getValue(2));
7892 SDValue Ops[] = { eax, edx };
7893 SDValue pair = IsReplace
7894 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7895 : DAG.getMergeValues(Ops, 2, DL);
7896 return std::make_pair(pair, SDValue());
7900 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7901 SelectionDAG &DAG) const {
7902 if (Op.getValueType().isVector())
7905 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7906 /*IsSigned=*/ true, /*IsReplace=*/ false);
7907 SDValue FIST = Vals.first, StackSlot = Vals.second;
7908 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7909 if (FIST.getNode() == 0) return Op;
7911 if (StackSlot.getNode())
7913 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7914 FIST, StackSlot, MachinePointerInfo(),
7915 false, false, false, 0);
7917 // The node is the result.
7921 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7922 SelectionDAG &DAG) const {
7923 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7924 /*IsSigned=*/ false, /*IsReplace=*/ false);
7925 SDValue FIST = Vals.first, StackSlot = Vals.second;
7926 assert(FIST.getNode() && "Unexpected failure");
7928 if (StackSlot.getNode())
7930 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7931 FIST, StackSlot, MachinePointerInfo(),
7932 false, false, false, 0);
7934 // The node is the result.
7938 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7939 SelectionDAG &DAG) const {
7940 LLVMContext *Context = DAG.getContext();
7941 DebugLoc dl = Op.getDebugLoc();
7942 EVT VT = Op.getValueType();
7945 EltVT = VT.getVectorElementType();
7947 if (EltVT == MVT::f64) {
7948 C = ConstantVector::getSplat(2,
7949 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7951 C = ConstantVector::getSplat(4,
7952 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7954 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7955 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7956 MachinePointerInfo::getConstantPool(),
7957 false, false, false, 16);
7958 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7961 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7962 LLVMContext *Context = DAG.getContext();
7963 DebugLoc dl = Op.getDebugLoc();
7964 EVT VT = Op.getValueType();
7966 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7967 if (VT.isVector()) {
7968 EltVT = VT.getVectorElementType();
7969 NumElts = VT.getVectorNumElements();
7972 if (EltVT == MVT::f64)
7973 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7975 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7976 C = ConstantVector::getSplat(NumElts, C);
7977 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7978 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7979 MachinePointerInfo::getConstantPool(),
7980 false, false, false, 16);
7981 if (VT.isVector()) {
7982 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7983 return DAG.getNode(ISD::BITCAST, dl, VT,
7984 DAG.getNode(ISD::XOR, dl, XORVT,
7985 DAG.getNode(ISD::BITCAST, dl, XORVT,
7987 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7990 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7993 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7994 LLVMContext *Context = DAG.getContext();
7995 SDValue Op0 = Op.getOperand(0);
7996 SDValue Op1 = Op.getOperand(1);
7997 DebugLoc dl = Op.getDebugLoc();
7998 EVT VT = Op.getValueType();
7999 EVT SrcVT = Op1.getValueType();
8001 // If second operand is smaller, extend it first.
8002 if (SrcVT.bitsLT(VT)) {
8003 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8006 // And if it is bigger, shrink it first.
8007 if (SrcVT.bitsGT(VT)) {
8008 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8012 // At this point the operands and the result should have the same
8013 // type, and that won't be f80 since that is not custom lowered.
8015 // First get the sign bit of second operand.
8016 SmallVector<Constant*,4> CV;
8017 if (SrcVT == MVT::f64) {
8018 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8019 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8021 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8022 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8023 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8024 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8026 Constant *C = ConstantVector::get(CV);
8027 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8028 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8029 MachinePointerInfo::getConstantPool(),
8030 false, false, false, 16);
8031 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8033 // Shift sign bit right or left if the two operands have different types.
8034 if (SrcVT.bitsGT(VT)) {
8035 // Op0 is MVT::f32, Op1 is MVT::f64.
8036 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8037 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8038 DAG.getConstant(32, MVT::i32));
8039 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8040 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8041 DAG.getIntPtrConstant(0));
8044 // Clear first operand sign bit.
8046 if (VT == MVT::f64) {
8047 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8048 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8050 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8051 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8052 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8053 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8055 C = ConstantVector::get(CV);
8056 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8057 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8058 MachinePointerInfo::getConstantPool(),
8059 false, false, false, 16);
8060 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8062 // Or the value with the sign bit.
8063 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8066 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8067 SDValue N0 = Op.getOperand(0);
8068 DebugLoc dl = Op.getDebugLoc();
8069 EVT VT = Op.getValueType();
8071 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8072 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8073 DAG.getConstant(1, VT));
8074 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8077 /// Emit nodes that will be selected as "test Op0,Op0", or something
8079 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8080 SelectionDAG &DAG) const {
8081 DebugLoc dl = Op.getDebugLoc();
8083 // CF and OF aren't always set the way we want. Determine which
8084 // of these we need.
8085 bool NeedCF = false;
8086 bool NeedOF = false;
8089 case X86::COND_A: case X86::COND_AE:
8090 case X86::COND_B: case X86::COND_BE:
8093 case X86::COND_G: case X86::COND_GE:
8094 case X86::COND_L: case X86::COND_LE:
8095 case X86::COND_O: case X86::COND_NO:
8100 // See if we can use the EFLAGS value from the operand instead of
8101 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8102 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8103 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8104 // Emit a CMP with 0, which is the TEST pattern.
8105 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8106 DAG.getConstant(0, Op.getValueType()));
8108 unsigned Opcode = 0;
8109 unsigned NumOperands = 0;
8110 switch (Op.getNode()->getOpcode()) {
8112 // Due to an isel shortcoming, be conservative if this add is likely to be
8113 // selected as part of a load-modify-store instruction. When the root node
8114 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8115 // uses of other nodes in the match, such as the ADD in this case. This
8116 // leads to the ADD being left around and reselected, with the result being
8117 // two adds in the output. Alas, even if none our users are stores, that
8118 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8119 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8120 // climbing the DAG back to the root, and it doesn't seem to be worth the
8122 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8123 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8124 if (UI->getOpcode() != ISD::CopyToReg &&
8125 UI->getOpcode() != ISD::SETCC &&
8126 UI->getOpcode() != ISD::STORE)
8129 if (ConstantSDNode *C =
8130 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8131 // An add of one will be selected as an INC.
8132 if (C->getAPIntValue() == 1) {
8133 Opcode = X86ISD::INC;
8138 // An add of negative one (subtract of one) will be selected as a DEC.
8139 if (C->getAPIntValue().isAllOnesValue()) {
8140 Opcode = X86ISD::DEC;
8146 // Otherwise use a regular EFLAGS-setting add.
8147 Opcode = X86ISD::ADD;
8151 // If the primary and result isn't used, don't bother using X86ISD::AND,
8152 // because a TEST instruction will be better.
8153 bool NonFlagUse = false;
8154 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8155 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8157 unsigned UOpNo = UI.getOperandNo();
8158 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8159 // Look pass truncate.
8160 UOpNo = User->use_begin().getOperandNo();
8161 User = *User->use_begin();
8164 if (User->getOpcode() != ISD::BRCOND &&
8165 User->getOpcode() != ISD::SETCC &&
8166 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8179 // Due to the ISEL shortcoming noted above, be conservative if this op is
8180 // likely to be selected as part of a load-modify-store instruction.
8181 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8182 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8183 if (UI->getOpcode() == ISD::STORE)
8186 // Otherwise use a regular EFLAGS-setting instruction.
8187 switch (Op.getNode()->getOpcode()) {
8188 default: llvm_unreachable("unexpected operator!");
8189 case ISD::SUB: Opcode = X86ISD::SUB; break;
8190 case ISD::OR: Opcode = X86ISD::OR; break;
8191 case ISD::XOR: Opcode = X86ISD::XOR; break;
8192 case ISD::AND: Opcode = X86ISD::AND; break;
8204 return SDValue(Op.getNode(), 1);
8211 // Emit a CMP with 0, which is the TEST pattern.
8212 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8213 DAG.getConstant(0, Op.getValueType()));
8215 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8216 SmallVector<SDValue, 4> Ops;
8217 for (unsigned i = 0; i != NumOperands; ++i)
8218 Ops.push_back(Op.getOperand(i));
8220 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8221 DAG.ReplaceAllUsesWith(Op, New);
8222 return SDValue(New.getNode(), 1);
8225 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8227 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8228 SelectionDAG &DAG) const {
8229 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8230 if (C->getAPIntValue() == 0)
8231 return EmitTest(Op0, X86CC, DAG);
8233 DebugLoc dl = Op0.getDebugLoc();
8234 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8237 /// Convert a comparison if required by the subtarget.
8238 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8239 SelectionDAG &DAG) const {
8240 // If the subtarget does not support the FUCOMI instruction, floating-point
8241 // comparisons have to be converted.
8242 if (Subtarget->hasCMov() ||
8243 Cmp.getOpcode() != X86ISD::CMP ||
8244 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8245 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8248 // The instruction selector will select an FUCOM instruction instead of
8249 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8250 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8251 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8252 DebugLoc dl = Cmp.getDebugLoc();
8253 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8254 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8255 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8256 DAG.getConstant(8, MVT::i8));
8257 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8258 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8261 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8262 /// if it's possible.
8263 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8264 DebugLoc dl, SelectionDAG &DAG) const {
8265 SDValue Op0 = And.getOperand(0);
8266 SDValue Op1 = And.getOperand(1);
8267 if (Op0.getOpcode() == ISD::TRUNCATE)
8268 Op0 = Op0.getOperand(0);
8269 if (Op1.getOpcode() == ISD::TRUNCATE)
8270 Op1 = Op1.getOperand(0);
8273 if (Op1.getOpcode() == ISD::SHL)
8274 std::swap(Op0, Op1);
8275 if (Op0.getOpcode() == ISD::SHL) {
8276 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8277 if (And00C->getZExtValue() == 1) {
8278 // If we looked past a truncate, check that it's only truncating away
8280 unsigned BitWidth = Op0.getValueSizeInBits();
8281 unsigned AndBitWidth = And.getValueSizeInBits();
8282 if (BitWidth > AndBitWidth) {
8284 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8285 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8289 RHS = Op0.getOperand(1);
8291 } else if (Op1.getOpcode() == ISD::Constant) {
8292 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8293 uint64_t AndRHSVal = AndRHS->getZExtValue();
8294 SDValue AndLHS = Op0;
8296 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8297 LHS = AndLHS.getOperand(0);
8298 RHS = AndLHS.getOperand(1);
8301 // Use BT if the immediate can't be encoded in a TEST instruction.
8302 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8304 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8308 if (LHS.getNode()) {
8309 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8310 // instruction. Since the shift amount is in-range-or-undefined, we know
8311 // that doing a bittest on the i32 value is ok. We extend to i32 because
8312 // the encoding for the i16 version is larger than the i32 version.
8313 // Also promote i16 to i32 for performance / code size reason.
8314 if (LHS.getValueType() == MVT::i8 ||
8315 LHS.getValueType() == MVT::i16)
8316 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8318 // If the operand types disagree, extend the shift amount to match. Since
8319 // BT ignores high bits (like shifts) we can use anyextend.
8320 if (LHS.getValueType() != RHS.getValueType())
8321 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8323 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8324 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8325 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8326 DAG.getConstant(Cond, MVT::i8), BT);
8332 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8334 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8336 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8337 SDValue Op0 = Op.getOperand(0);
8338 SDValue Op1 = Op.getOperand(1);
8339 DebugLoc dl = Op.getDebugLoc();
8340 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8342 // Optimize to BT if possible.
8343 // Lower (X & (1 << N)) == 0 to BT(X, N).
8344 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8345 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8346 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8347 Op1.getOpcode() == ISD::Constant &&
8348 cast<ConstantSDNode>(Op1)->isNullValue() &&
8349 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8350 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8351 if (NewSetCC.getNode())
8355 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8357 if (Op1.getOpcode() == ISD::Constant &&
8358 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8359 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8360 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8362 // If the input is a setcc, then reuse the input setcc or use a new one with
8363 // the inverted condition.
8364 if (Op0.getOpcode() == X86ISD::SETCC) {
8365 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8366 bool Invert = (CC == ISD::SETNE) ^
8367 cast<ConstantSDNode>(Op1)->isNullValue();
8368 if (!Invert) return Op0;
8370 CCode = X86::GetOppositeBranchCondition(CCode);
8371 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8372 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8376 bool isFP = Op1.getValueType().isFloatingPoint();
8377 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8378 if (X86CC == X86::COND_INVALID)
8381 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8382 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8383 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8384 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8387 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8388 // ones, and then concatenate the result back.
8389 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8390 EVT VT = Op.getValueType();
8392 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8393 "Unsupported value type for operation");
8395 unsigned NumElems = VT.getVectorNumElements();
8396 DebugLoc dl = Op.getDebugLoc();
8397 SDValue CC = Op.getOperand(2);
8399 // Extract the LHS vectors
8400 SDValue LHS = Op.getOperand(0);
8401 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8402 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8404 // Extract the RHS vectors
8405 SDValue RHS = Op.getOperand(1);
8406 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8407 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8409 // Issue the operation on the smaller types and concatenate the result back
8410 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8411 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8412 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8413 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8414 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8418 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8420 SDValue Op0 = Op.getOperand(0);
8421 SDValue Op1 = Op.getOperand(1);
8422 SDValue CC = Op.getOperand(2);
8423 EVT VT = Op.getValueType();
8424 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8425 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8426 DebugLoc dl = Op.getDebugLoc();
8430 EVT EltVT = Op0.getValueType().getVectorElementType();
8431 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8435 // SSE Condition code mapping:
8444 switch (SetCCOpcode) {
8447 case ISD::SETEQ: SSECC = 0; break;
8449 case ISD::SETGT: Swap = true; // Fallthrough
8451 case ISD::SETOLT: SSECC = 1; break;
8453 case ISD::SETGE: Swap = true; // Fallthrough
8455 case ISD::SETOLE: SSECC = 2; break;
8456 case ISD::SETUO: SSECC = 3; break;
8458 case ISD::SETNE: SSECC = 4; break;
8459 case ISD::SETULE: Swap = true;
8460 case ISD::SETUGE: SSECC = 5; break;
8461 case ISD::SETULT: Swap = true;
8462 case ISD::SETUGT: SSECC = 6; break;
8463 case ISD::SETO: SSECC = 7; break;
8466 std::swap(Op0, Op1);
8468 // In the two special cases we can't handle, emit two comparisons.
8470 if (SetCCOpcode == ISD::SETUEQ) {
8472 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8473 DAG.getConstant(3, MVT::i8));
8474 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8475 DAG.getConstant(0, MVT::i8));
8476 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8478 if (SetCCOpcode == ISD::SETONE) {
8480 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8481 DAG.getConstant(7, MVT::i8));
8482 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8483 DAG.getConstant(4, MVT::i8));
8484 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8486 llvm_unreachable("Illegal FP comparison");
8488 // Handle all other FP comparisons here.
8489 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8490 DAG.getConstant(SSECC, MVT::i8));
8493 // Break 256-bit integer vector compare into smaller ones.
8494 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8495 return Lower256IntVSETCC(Op, DAG);
8497 // We are handling one of the integer comparisons here. Since SSE only has
8498 // GT and EQ comparisons for integer, swapping operands and multiple
8499 // operations may be required for some comparisons.
8501 bool Swap = false, Invert = false, FlipSigns = false;
8503 switch (SetCCOpcode) {
8505 case ISD::SETNE: Invert = true;
8506 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8507 case ISD::SETLT: Swap = true;
8508 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8509 case ISD::SETGE: Swap = true;
8510 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8511 case ISD::SETULT: Swap = true;
8512 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8513 case ISD::SETUGE: Swap = true;
8514 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8517 std::swap(Op0, Op1);
8519 // Check that the operation in question is available (most are plain SSE2,
8520 // but PCMPGTQ and PCMPEQQ have different requirements).
8521 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8523 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8526 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8527 // bits of the inputs before performing those operations.
8529 EVT EltVT = VT.getVectorElementType();
8530 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8532 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8533 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8535 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8536 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8539 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8541 // If the logical-not of the result is required, perform that now.
8543 Result = DAG.getNOT(dl, Result, VT);
8548 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8549 static bool isX86LogicalCmp(SDValue Op) {
8550 unsigned Opc = Op.getNode()->getOpcode();
8551 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8552 Opc == X86ISD::SAHF)
8554 if (Op.getResNo() == 1 &&
8555 (Opc == X86ISD::ADD ||
8556 Opc == X86ISD::SUB ||
8557 Opc == X86ISD::ADC ||
8558 Opc == X86ISD::SBB ||
8559 Opc == X86ISD::SMUL ||
8560 Opc == X86ISD::UMUL ||
8561 Opc == X86ISD::INC ||
8562 Opc == X86ISD::DEC ||
8563 Opc == X86ISD::OR ||
8564 Opc == X86ISD::XOR ||
8565 Opc == X86ISD::AND))
8568 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8574 static bool isZero(SDValue V) {
8575 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8576 return C && C->isNullValue();
8579 static bool isAllOnes(SDValue V) {
8580 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8581 return C && C->isAllOnesValue();
8584 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8585 bool addTest = true;
8586 SDValue Cond = Op.getOperand(0);
8587 SDValue Op1 = Op.getOperand(1);
8588 SDValue Op2 = Op.getOperand(2);
8589 DebugLoc DL = Op.getDebugLoc();
8592 if (Cond.getOpcode() == ISD::SETCC) {
8593 SDValue NewCond = LowerSETCC(Cond, DAG);
8594 if (NewCond.getNode())
8598 // Handle the following cases related to max and min:
8599 // (a > b) ? (a-b) : 0
8600 // (a >= b) ? (a-b) : 0
8601 // (b < a) ? (a-b) : 0
8602 // (b <= a) ? (a-b) : 0
8603 // Comparison is removed to use EFLAGS from SUB.
8604 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2))
8605 if (Cond.getOpcode() == X86ISD::SETCC &&
8606 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8607 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) &&
8608 C->getAPIntValue() == 0) {
8609 SDValue Cmp = Cond.getOperand(1);
8610 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8611 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) &&
8612 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) &&
8613 (CC == X86::COND_G || CC == X86::COND_GE ||
8614 CC == X86::COND_A || CC == X86::COND_AE)) ||
8615 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) &&
8616 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) &&
8617 (CC == X86::COND_L || CC == X86::COND_LE ||
8618 CC == X86::COND_B || CC == X86::COND_BE))) {
8620 if (Op1.getOpcode() == ISD::SUB) {
8621 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32);
8622 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs,
8623 Op1.getOperand(0), Op1.getOperand(1));
8624 DAG.ReplaceAllUsesWith(Op1, New);
8628 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8629 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE ||
8630 CC == X86::COND_L ||
8631 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE;
8632 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8),
8633 SDValue(Op1.getNode(), 1) };
8634 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8638 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8639 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8640 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8641 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8642 if (Cond.getOpcode() == X86ISD::SETCC &&
8643 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8644 isZero(Cond.getOperand(1).getOperand(1))) {
8645 SDValue Cmp = Cond.getOperand(1);
8647 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8649 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8650 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8651 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8653 SDValue CmpOp0 = Cmp.getOperand(0);
8654 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8655 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8656 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8658 SDValue Res = // Res = 0 or -1.
8659 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8660 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8662 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8663 Res = DAG.getNOT(DL, Res, Res.getValueType());
8665 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8666 if (N2C == 0 || !N2C->isNullValue())
8667 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8672 // Look past (and (setcc_carry (cmp ...)), 1).
8673 if (Cond.getOpcode() == ISD::AND &&
8674 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8675 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8676 if (C && C->getAPIntValue() == 1)
8677 Cond = Cond.getOperand(0);
8680 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8681 // setting operand in place of the X86ISD::SETCC.
8682 unsigned CondOpcode = Cond.getOpcode();
8683 if (CondOpcode == X86ISD::SETCC ||
8684 CondOpcode == X86ISD::SETCC_CARRY) {
8685 CC = Cond.getOperand(0);
8687 SDValue Cmp = Cond.getOperand(1);
8688 unsigned Opc = Cmp.getOpcode();
8689 EVT VT = Op.getValueType();
8691 bool IllegalFPCMov = false;
8692 if (VT.isFloatingPoint() && !VT.isVector() &&
8693 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8694 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8696 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8697 Opc == X86ISD::BT) { // FIXME
8701 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8702 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8703 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8704 Cond.getOperand(0).getValueType() != MVT::i8)) {
8705 SDValue LHS = Cond.getOperand(0);
8706 SDValue RHS = Cond.getOperand(1);
8710 switch (CondOpcode) {
8711 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8712 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8713 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8714 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8715 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8716 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8717 default: llvm_unreachable("unexpected overflowing operator");
8719 if (CondOpcode == ISD::UMULO)
8720 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8723 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8725 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8727 if (CondOpcode == ISD::UMULO)
8728 Cond = X86Op.getValue(2);
8730 Cond = X86Op.getValue(1);
8732 CC = DAG.getConstant(X86Cond, MVT::i8);
8737 // Look pass the truncate.
8738 if (Cond.getOpcode() == ISD::TRUNCATE)
8739 Cond = Cond.getOperand(0);
8741 // We know the result of AND is compared against zero. Try to match
8743 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8744 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8745 if (NewSetCC.getNode()) {
8746 CC = NewSetCC.getOperand(0);
8747 Cond = NewSetCC.getOperand(1);
8754 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8755 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8758 // a < b ? -1 : 0 -> RES = ~setcc_carry
8759 // a < b ? 0 : -1 -> RES = setcc_carry
8760 // a >= b ? -1 : 0 -> RES = setcc_carry
8761 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8762 if (Cond.getOpcode() == X86ISD::CMP) {
8763 Cond = ConvertCmpIfNecessary(Cond, DAG);
8764 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8766 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8767 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8768 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8769 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8770 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8771 return DAG.getNOT(DL, Res, Res.getValueType());
8776 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8777 // condition is true.
8778 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8779 SDValue Ops[] = { Op2, Op1, CC, Cond };
8780 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8783 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8784 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8785 // from the AND / OR.
8786 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8787 Opc = Op.getOpcode();
8788 if (Opc != ISD::OR && Opc != ISD::AND)
8790 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8791 Op.getOperand(0).hasOneUse() &&
8792 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8793 Op.getOperand(1).hasOneUse());
8796 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8797 // 1 and that the SETCC node has a single use.
8798 static bool isXor1OfSetCC(SDValue Op) {
8799 if (Op.getOpcode() != ISD::XOR)
8801 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8802 if (N1C && N1C->getAPIntValue() == 1) {
8803 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8804 Op.getOperand(0).hasOneUse();
8809 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8810 bool addTest = true;
8811 SDValue Chain = Op.getOperand(0);
8812 SDValue Cond = Op.getOperand(1);
8813 SDValue Dest = Op.getOperand(2);
8814 DebugLoc dl = Op.getDebugLoc();
8816 bool Inverted = false;
8818 if (Cond.getOpcode() == ISD::SETCC) {
8819 // Check for setcc([su]{add,sub,mul}o == 0).
8820 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8821 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8822 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8823 Cond.getOperand(0).getResNo() == 1 &&
8824 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8825 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8826 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8827 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8828 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8829 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8831 Cond = Cond.getOperand(0);
8833 SDValue NewCond = LowerSETCC(Cond, DAG);
8834 if (NewCond.getNode())
8839 // FIXME: LowerXALUO doesn't handle these!!
8840 else if (Cond.getOpcode() == X86ISD::ADD ||
8841 Cond.getOpcode() == X86ISD::SUB ||
8842 Cond.getOpcode() == X86ISD::SMUL ||
8843 Cond.getOpcode() == X86ISD::UMUL)
8844 Cond = LowerXALUO(Cond, DAG);
8847 // Look pass (and (setcc_carry (cmp ...)), 1).
8848 if (Cond.getOpcode() == ISD::AND &&
8849 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8850 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8851 if (C && C->getAPIntValue() == 1)
8852 Cond = Cond.getOperand(0);
8855 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8856 // setting operand in place of the X86ISD::SETCC.
8857 unsigned CondOpcode = Cond.getOpcode();
8858 if (CondOpcode == X86ISD::SETCC ||
8859 CondOpcode == X86ISD::SETCC_CARRY) {
8860 CC = Cond.getOperand(0);
8862 SDValue Cmp = Cond.getOperand(1);
8863 unsigned Opc = Cmp.getOpcode();
8864 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8865 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8869 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8873 // These can only come from an arithmetic instruction with overflow,
8874 // e.g. SADDO, UADDO.
8875 Cond = Cond.getNode()->getOperand(1);
8881 CondOpcode = Cond.getOpcode();
8882 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8883 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8884 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8885 Cond.getOperand(0).getValueType() != MVT::i8)) {
8886 SDValue LHS = Cond.getOperand(0);
8887 SDValue RHS = Cond.getOperand(1);
8891 switch (CondOpcode) {
8892 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8893 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8894 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8895 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8896 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8897 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8898 default: llvm_unreachable("unexpected overflowing operator");
8901 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8902 if (CondOpcode == ISD::UMULO)
8903 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8906 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8908 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8910 if (CondOpcode == ISD::UMULO)
8911 Cond = X86Op.getValue(2);
8913 Cond = X86Op.getValue(1);
8915 CC = DAG.getConstant(X86Cond, MVT::i8);
8919 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8920 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8921 if (CondOpc == ISD::OR) {
8922 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8923 // two branches instead of an explicit OR instruction with a
8925 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8926 isX86LogicalCmp(Cmp)) {
8927 CC = Cond.getOperand(0).getOperand(0);
8928 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8929 Chain, Dest, CC, Cmp);
8930 CC = Cond.getOperand(1).getOperand(0);
8934 } else { // ISD::AND
8935 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8936 // two branches instead of an explicit AND instruction with a
8937 // separate test. However, we only do this if this block doesn't
8938 // have a fall-through edge, because this requires an explicit
8939 // jmp when the condition is false.
8940 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8941 isX86LogicalCmp(Cmp) &&
8942 Op.getNode()->hasOneUse()) {
8943 X86::CondCode CCode =
8944 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8945 CCode = X86::GetOppositeBranchCondition(CCode);
8946 CC = DAG.getConstant(CCode, MVT::i8);
8947 SDNode *User = *Op.getNode()->use_begin();
8948 // Look for an unconditional branch following this conditional branch.
8949 // We need this because we need to reverse the successors in order
8950 // to implement FCMP_OEQ.
8951 if (User->getOpcode() == ISD::BR) {
8952 SDValue FalseBB = User->getOperand(1);
8954 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8955 assert(NewBR == User);
8959 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8960 Chain, Dest, CC, Cmp);
8961 X86::CondCode CCode =
8962 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8963 CCode = X86::GetOppositeBranchCondition(CCode);
8964 CC = DAG.getConstant(CCode, MVT::i8);
8970 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8971 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8972 // It should be transformed during dag combiner except when the condition
8973 // is set by a arithmetics with overflow node.
8974 X86::CondCode CCode =
8975 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8976 CCode = X86::GetOppositeBranchCondition(CCode);
8977 CC = DAG.getConstant(CCode, MVT::i8);
8978 Cond = Cond.getOperand(0).getOperand(1);
8980 } else if (Cond.getOpcode() == ISD::SETCC &&
8981 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8982 // For FCMP_OEQ, we can emit
8983 // two branches instead of an explicit AND instruction with a
8984 // separate test. However, we only do this if this block doesn't
8985 // have a fall-through edge, because this requires an explicit
8986 // jmp when the condition is false.
8987 if (Op.getNode()->hasOneUse()) {
8988 SDNode *User = *Op.getNode()->use_begin();
8989 // Look for an unconditional branch following this conditional branch.
8990 // We need this because we need to reverse the successors in order
8991 // to implement FCMP_OEQ.
8992 if (User->getOpcode() == ISD::BR) {
8993 SDValue FalseBB = User->getOperand(1);
8995 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8996 assert(NewBR == User);
9000 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9001 Cond.getOperand(0), Cond.getOperand(1));
9002 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9003 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9004 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9005 Chain, Dest, CC, Cmp);
9006 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9011 } else if (Cond.getOpcode() == ISD::SETCC &&
9012 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9013 // For FCMP_UNE, we can emit
9014 // two branches instead of an explicit AND instruction with a
9015 // separate test. However, we only do this if this block doesn't
9016 // have a fall-through edge, because this requires an explicit
9017 // jmp when the condition is false.
9018 if (Op.getNode()->hasOneUse()) {
9019 SDNode *User = *Op.getNode()->use_begin();
9020 // Look for an unconditional branch following this conditional branch.
9021 // We need this because we need to reverse the successors in order
9022 // to implement FCMP_UNE.
9023 if (User->getOpcode() == ISD::BR) {
9024 SDValue FalseBB = User->getOperand(1);
9026 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9027 assert(NewBR == User);
9030 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9031 Cond.getOperand(0), Cond.getOperand(1));
9032 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9033 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9034 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9035 Chain, Dest, CC, Cmp);
9036 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9046 // Look pass the truncate.
9047 if (Cond.getOpcode() == ISD::TRUNCATE)
9048 Cond = Cond.getOperand(0);
9050 // We know the result of AND is compared against zero. Try to match
9052 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9053 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9054 if (NewSetCC.getNode()) {
9055 CC = NewSetCC.getOperand(0);
9056 Cond = NewSetCC.getOperand(1);
9063 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9064 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9066 Cond = ConvertCmpIfNecessary(Cond, DAG);
9067 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9068 Chain, Dest, CC, Cond);
9072 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9073 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9074 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9075 // that the guard pages used by the OS virtual memory manager are allocated in
9076 // correct sequence.
9078 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9079 SelectionDAG &DAG) const {
9080 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9081 getTargetMachine().Options.EnableSegmentedStacks) &&
9082 "This should be used only on Windows targets or when segmented stacks "
9084 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9085 DebugLoc dl = Op.getDebugLoc();
9088 SDValue Chain = Op.getOperand(0);
9089 SDValue Size = Op.getOperand(1);
9090 // FIXME: Ensure alignment here
9092 bool Is64Bit = Subtarget->is64Bit();
9093 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9095 if (getTargetMachine().Options.EnableSegmentedStacks) {
9096 MachineFunction &MF = DAG.getMachineFunction();
9097 MachineRegisterInfo &MRI = MF.getRegInfo();
9100 // The 64 bit implementation of segmented stacks needs to clobber both r10
9101 // r11. This makes it impossible to use it along with nested parameters.
9102 const Function *F = MF.getFunction();
9104 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9106 if (I->hasNestAttr())
9107 report_fatal_error("Cannot use segmented stacks with functions that "
9108 "have nested arguments.");
9111 const TargetRegisterClass *AddrRegClass =
9112 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9113 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9114 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9115 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9116 DAG.getRegister(Vreg, SPTy));
9117 SDValue Ops1[2] = { Value, Chain };
9118 return DAG.getMergeValues(Ops1, 2, dl);
9121 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9123 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9124 Flag = Chain.getValue(1);
9125 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9127 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9128 Flag = Chain.getValue(1);
9130 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9132 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9133 return DAG.getMergeValues(Ops1, 2, dl);
9137 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9138 MachineFunction &MF = DAG.getMachineFunction();
9139 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9141 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9142 DebugLoc DL = Op.getDebugLoc();
9144 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9145 // vastart just stores the address of the VarArgsFrameIndex slot into the
9146 // memory location argument.
9147 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9149 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9150 MachinePointerInfo(SV), false, false, 0);
9154 // gp_offset (0 - 6 * 8)
9155 // fp_offset (48 - 48 + 8 * 16)
9156 // overflow_arg_area (point to parameters coming in memory).
9158 SmallVector<SDValue, 8> MemOps;
9159 SDValue FIN = Op.getOperand(1);
9161 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9162 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9164 FIN, MachinePointerInfo(SV), false, false, 0);
9165 MemOps.push_back(Store);
9168 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9169 FIN, DAG.getIntPtrConstant(4));
9170 Store = DAG.getStore(Op.getOperand(0), DL,
9171 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9173 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9174 MemOps.push_back(Store);
9176 // Store ptr to overflow_arg_area
9177 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9178 FIN, DAG.getIntPtrConstant(4));
9179 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9181 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9182 MachinePointerInfo(SV, 8),
9184 MemOps.push_back(Store);
9186 // Store ptr to reg_save_area.
9187 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9188 FIN, DAG.getIntPtrConstant(8));
9189 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9191 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9192 MachinePointerInfo(SV, 16), false, false, 0);
9193 MemOps.push_back(Store);
9194 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9195 &MemOps[0], MemOps.size());
9198 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9199 assert(Subtarget->is64Bit() &&
9200 "LowerVAARG only handles 64-bit va_arg!");
9201 assert((Subtarget->isTargetLinux() ||
9202 Subtarget->isTargetDarwin()) &&
9203 "Unhandled target in LowerVAARG");
9204 assert(Op.getNode()->getNumOperands() == 4);
9205 SDValue Chain = Op.getOperand(0);
9206 SDValue SrcPtr = Op.getOperand(1);
9207 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9208 unsigned Align = Op.getConstantOperandVal(3);
9209 DebugLoc dl = Op.getDebugLoc();
9211 EVT ArgVT = Op.getNode()->getValueType(0);
9212 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9213 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9216 // Decide which area this value should be read from.
9217 // TODO: Implement the AMD64 ABI in its entirety. This simple
9218 // selection mechanism works only for the basic types.
9219 if (ArgVT == MVT::f80) {
9220 llvm_unreachable("va_arg for f80 not yet implemented");
9221 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9222 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9223 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9224 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9226 llvm_unreachable("Unhandled argument type in LowerVAARG");
9230 // Sanity Check: Make sure using fp_offset makes sense.
9231 assert(!getTargetMachine().Options.UseSoftFloat &&
9232 !(DAG.getMachineFunction()
9233 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9234 Subtarget->hasSSE1());
9237 // Insert VAARG_64 node into the DAG
9238 // VAARG_64 returns two values: Variable Argument Address, Chain
9239 SmallVector<SDValue, 11> InstOps;
9240 InstOps.push_back(Chain);
9241 InstOps.push_back(SrcPtr);
9242 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9243 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9244 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9245 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9246 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9247 VTs, &InstOps[0], InstOps.size(),
9249 MachinePointerInfo(SV),
9254 Chain = VAARG.getValue(1);
9256 // Load the next argument and return it
9257 return DAG.getLoad(ArgVT, dl,
9260 MachinePointerInfo(),
9261 false, false, false, 0);
9264 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9265 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9266 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9267 SDValue Chain = Op.getOperand(0);
9268 SDValue DstPtr = Op.getOperand(1);
9269 SDValue SrcPtr = Op.getOperand(2);
9270 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9271 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9272 DebugLoc DL = Op.getDebugLoc();
9274 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9275 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9277 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9280 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9281 // may or may not be a constant. Takes immediate version of shift as input.
9282 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9283 SDValue SrcOp, SDValue ShAmt,
9284 SelectionDAG &DAG) {
9285 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9287 if (isa<ConstantSDNode>(ShAmt)) {
9289 default: llvm_unreachable("Unknown target vector shift node");
9293 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9297 // Change opcode to non-immediate version
9299 default: llvm_unreachable("Unknown target vector shift node");
9300 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9301 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9302 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9305 // Need to build a vector containing shift amount
9306 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9309 ShOps[1] = DAG.getConstant(0, MVT::i32);
9310 ShOps[2] = DAG.getUNDEF(MVT::i32);
9311 ShOps[3] = DAG.getUNDEF(MVT::i32);
9312 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9313 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9314 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9318 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9319 DebugLoc dl = Op.getDebugLoc();
9320 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9322 default: return SDValue(); // Don't custom lower most intrinsics.
9323 // Comparison intrinsics.
9324 case Intrinsic::x86_sse_comieq_ss:
9325 case Intrinsic::x86_sse_comilt_ss:
9326 case Intrinsic::x86_sse_comile_ss:
9327 case Intrinsic::x86_sse_comigt_ss:
9328 case Intrinsic::x86_sse_comige_ss:
9329 case Intrinsic::x86_sse_comineq_ss:
9330 case Intrinsic::x86_sse_ucomieq_ss:
9331 case Intrinsic::x86_sse_ucomilt_ss:
9332 case Intrinsic::x86_sse_ucomile_ss:
9333 case Intrinsic::x86_sse_ucomigt_ss:
9334 case Intrinsic::x86_sse_ucomige_ss:
9335 case Intrinsic::x86_sse_ucomineq_ss:
9336 case Intrinsic::x86_sse2_comieq_sd:
9337 case Intrinsic::x86_sse2_comilt_sd:
9338 case Intrinsic::x86_sse2_comile_sd:
9339 case Intrinsic::x86_sse2_comigt_sd:
9340 case Intrinsic::x86_sse2_comige_sd:
9341 case Intrinsic::x86_sse2_comineq_sd:
9342 case Intrinsic::x86_sse2_ucomieq_sd:
9343 case Intrinsic::x86_sse2_ucomilt_sd:
9344 case Intrinsic::x86_sse2_ucomile_sd:
9345 case Intrinsic::x86_sse2_ucomigt_sd:
9346 case Intrinsic::x86_sse2_ucomige_sd:
9347 case Intrinsic::x86_sse2_ucomineq_sd: {
9349 ISD::CondCode CC = ISD::SETCC_INVALID;
9351 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9352 case Intrinsic::x86_sse_comieq_ss:
9353 case Intrinsic::x86_sse2_comieq_sd:
9357 case Intrinsic::x86_sse_comilt_ss:
9358 case Intrinsic::x86_sse2_comilt_sd:
9362 case Intrinsic::x86_sse_comile_ss:
9363 case Intrinsic::x86_sse2_comile_sd:
9367 case Intrinsic::x86_sse_comigt_ss:
9368 case Intrinsic::x86_sse2_comigt_sd:
9372 case Intrinsic::x86_sse_comige_ss:
9373 case Intrinsic::x86_sse2_comige_sd:
9377 case Intrinsic::x86_sse_comineq_ss:
9378 case Intrinsic::x86_sse2_comineq_sd:
9382 case Intrinsic::x86_sse_ucomieq_ss:
9383 case Intrinsic::x86_sse2_ucomieq_sd:
9384 Opc = X86ISD::UCOMI;
9387 case Intrinsic::x86_sse_ucomilt_ss:
9388 case Intrinsic::x86_sse2_ucomilt_sd:
9389 Opc = X86ISD::UCOMI;
9392 case Intrinsic::x86_sse_ucomile_ss:
9393 case Intrinsic::x86_sse2_ucomile_sd:
9394 Opc = X86ISD::UCOMI;
9397 case Intrinsic::x86_sse_ucomigt_ss:
9398 case Intrinsic::x86_sse2_ucomigt_sd:
9399 Opc = X86ISD::UCOMI;
9402 case Intrinsic::x86_sse_ucomige_ss:
9403 case Intrinsic::x86_sse2_ucomige_sd:
9404 Opc = X86ISD::UCOMI;
9407 case Intrinsic::x86_sse_ucomineq_ss:
9408 case Intrinsic::x86_sse2_ucomineq_sd:
9409 Opc = X86ISD::UCOMI;
9414 SDValue LHS = Op.getOperand(1);
9415 SDValue RHS = Op.getOperand(2);
9416 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9417 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9418 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9419 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9420 DAG.getConstant(X86CC, MVT::i8), Cond);
9421 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9423 // XOP comparison intrinsics
9424 case Intrinsic::x86_xop_vpcomltb:
9425 case Intrinsic::x86_xop_vpcomltw:
9426 case Intrinsic::x86_xop_vpcomltd:
9427 case Intrinsic::x86_xop_vpcomltq:
9428 case Intrinsic::x86_xop_vpcomltub:
9429 case Intrinsic::x86_xop_vpcomltuw:
9430 case Intrinsic::x86_xop_vpcomltud:
9431 case Intrinsic::x86_xop_vpcomltuq:
9432 case Intrinsic::x86_xop_vpcomleb:
9433 case Intrinsic::x86_xop_vpcomlew:
9434 case Intrinsic::x86_xop_vpcomled:
9435 case Intrinsic::x86_xop_vpcomleq:
9436 case Intrinsic::x86_xop_vpcomleub:
9437 case Intrinsic::x86_xop_vpcomleuw:
9438 case Intrinsic::x86_xop_vpcomleud:
9439 case Intrinsic::x86_xop_vpcomleuq:
9440 case Intrinsic::x86_xop_vpcomgtb:
9441 case Intrinsic::x86_xop_vpcomgtw:
9442 case Intrinsic::x86_xop_vpcomgtd:
9443 case Intrinsic::x86_xop_vpcomgtq:
9444 case Intrinsic::x86_xop_vpcomgtub:
9445 case Intrinsic::x86_xop_vpcomgtuw:
9446 case Intrinsic::x86_xop_vpcomgtud:
9447 case Intrinsic::x86_xop_vpcomgtuq:
9448 case Intrinsic::x86_xop_vpcomgeb:
9449 case Intrinsic::x86_xop_vpcomgew:
9450 case Intrinsic::x86_xop_vpcomged:
9451 case Intrinsic::x86_xop_vpcomgeq:
9452 case Intrinsic::x86_xop_vpcomgeub:
9453 case Intrinsic::x86_xop_vpcomgeuw:
9454 case Intrinsic::x86_xop_vpcomgeud:
9455 case Intrinsic::x86_xop_vpcomgeuq:
9456 case Intrinsic::x86_xop_vpcomeqb:
9457 case Intrinsic::x86_xop_vpcomeqw:
9458 case Intrinsic::x86_xop_vpcomeqd:
9459 case Intrinsic::x86_xop_vpcomeqq:
9460 case Intrinsic::x86_xop_vpcomequb:
9461 case Intrinsic::x86_xop_vpcomequw:
9462 case Intrinsic::x86_xop_vpcomequd:
9463 case Intrinsic::x86_xop_vpcomequq:
9464 case Intrinsic::x86_xop_vpcomneb:
9465 case Intrinsic::x86_xop_vpcomnew:
9466 case Intrinsic::x86_xop_vpcomned:
9467 case Intrinsic::x86_xop_vpcomneq:
9468 case Intrinsic::x86_xop_vpcomneub:
9469 case Intrinsic::x86_xop_vpcomneuw:
9470 case Intrinsic::x86_xop_vpcomneud:
9471 case Intrinsic::x86_xop_vpcomneuq:
9472 case Intrinsic::x86_xop_vpcomfalseb:
9473 case Intrinsic::x86_xop_vpcomfalsew:
9474 case Intrinsic::x86_xop_vpcomfalsed:
9475 case Intrinsic::x86_xop_vpcomfalseq:
9476 case Intrinsic::x86_xop_vpcomfalseub:
9477 case Intrinsic::x86_xop_vpcomfalseuw:
9478 case Intrinsic::x86_xop_vpcomfalseud:
9479 case Intrinsic::x86_xop_vpcomfalseuq:
9480 case Intrinsic::x86_xop_vpcomtrueb:
9481 case Intrinsic::x86_xop_vpcomtruew:
9482 case Intrinsic::x86_xop_vpcomtrued:
9483 case Intrinsic::x86_xop_vpcomtrueq:
9484 case Intrinsic::x86_xop_vpcomtrueub:
9485 case Intrinsic::x86_xop_vpcomtrueuw:
9486 case Intrinsic::x86_xop_vpcomtrueud:
9487 case Intrinsic::x86_xop_vpcomtrueuq: {
9492 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9493 case Intrinsic::x86_xop_vpcomltb:
9494 case Intrinsic::x86_xop_vpcomltw:
9495 case Intrinsic::x86_xop_vpcomltd:
9496 case Intrinsic::x86_xop_vpcomltq:
9498 Opc = X86ISD::VPCOM;
9500 case Intrinsic::x86_xop_vpcomltub:
9501 case Intrinsic::x86_xop_vpcomltuw:
9502 case Intrinsic::x86_xop_vpcomltud:
9503 case Intrinsic::x86_xop_vpcomltuq:
9505 Opc = X86ISD::VPCOMU;
9507 case Intrinsic::x86_xop_vpcomleb:
9508 case Intrinsic::x86_xop_vpcomlew:
9509 case Intrinsic::x86_xop_vpcomled:
9510 case Intrinsic::x86_xop_vpcomleq:
9512 Opc = X86ISD::VPCOM;
9514 case Intrinsic::x86_xop_vpcomleub:
9515 case Intrinsic::x86_xop_vpcomleuw:
9516 case Intrinsic::x86_xop_vpcomleud:
9517 case Intrinsic::x86_xop_vpcomleuq:
9519 Opc = X86ISD::VPCOMU;
9521 case Intrinsic::x86_xop_vpcomgtb:
9522 case Intrinsic::x86_xop_vpcomgtw:
9523 case Intrinsic::x86_xop_vpcomgtd:
9524 case Intrinsic::x86_xop_vpcomgtq:
9526 Opc = X86ISD::VPCOM;
9528 case Intrinsic::x86_xop_vpcomgtub:
9529 case Intrinsic::x86_xop_vpcomgtuw:
9530 case Intrinsic::x86_xop_vpcomgtud:
9531 case Intrinsic::x86_xop_vpcomgtuq:
9533 Opc = X86ISD::VPCOMU;
9535 case Intrinsic::x86_xop_vpcomgeb:
9536 case Intrinsic::x86_xop_vpcomgew:
9537 case Intrinsic::x86_xop_vpcomged:
9538 case Intrinsic::x86_xop_vpcomgeq:
9540 Opc = X86ISD::VPCOM;
9542 case Intrinsic::x86_xop_vpcomgeub:
9543 case Intrinsic::x86_xop_vpcomgeuw:
9544 case Intrinsic::x86_xop_vpcomgeud:
9545 case Intrinsic::x86_xop_vpcomgeuq:
9547 Opc = X86ISD::VPCOMU;
9549 case Intrinsic::x86_xop_vpcomeqb:
9550 case Intrinsic::x86_xop_vpcomeqw:
9551 case Intrinsic::x86_xop_vpcomeqd:
9552 case Intrinsic::x86_xop_vpcomeqq:
9554 Opc = X86ISD::VPCOM;
9556 case Intrinsic::x86_xop_vpcomequb:
9557 case Intrinsic::x86_xop_vpcomequw:
9558 case Intrinsic::x86_xop_vpcomequd:
9559 case Intrinsic::x86_xop_vpcomequq:
9561 Opc = X86ISD::VPCOMU;
9563 case Intrinsic::x86_xop_vpcomneb:
9564 case Intrinsic::x86_xop_vpcomnew:
9565 case Intrinsic::x86_xop_vpcomned:
9566 case Intrinsic::x86_xop_vpcomneq:
9568 Opc = X86ISD::VPCOM;
9570 case Intrinsic::x86_xop_vpcomneub:
9571 case Intrinsic::x86_xop_vpcomneuw:
9572 case Intrinsic::x86_xop_vpcomneud:
9573 case Intrinsic::x86_xop_vpcomneuq:
9575 Opc = X86ISD::VPCOMU;
9577 case Intrinsic::x86_xop_vpcomfalseb:
9578 case Intrinsic::x86_xop_vpcomfalsew:
9579 case Intrinsic::x86_xop_vpcomfalsed:
9580 case Intrinsic::x86_xop_vpcomfalseq:
9582 Opc = X86ISD::VPCOM;
9584 case Intrinsic::x86_xop_vpcomfalseub:
9585 case Intrinsic::x86_xop_vpcomfalseuw:
9586 case Intrinsic::x86_xop_vpcomfalseud:
9587 case Intrinsic::x86_xop_vpcomfalseuq:
9589 Opc = X86ISD::VPCOMU;
9591 case Intrinsic::x86_xop_vpcomtrueb:
9592 case Intrinsic::x86_xop_vpcomtruew:
9593 case Intrinsic::x86_xop_vpcomtrued:
9594 case Intrinsic::x86_xop_vpcomtrueq:
9596 Opc = X86ISD::VPCOM;
9598 case Intrinsic::x86_xop_vpcomtrueub:
9599 case Intrinsic::x86_xop_vpcomtrueuw:
9600 case Intrinsic::x86_xop_vpcomtrueud:
9601 case Intrinsic::x86_xop_vpcomtrueuq:
9603 Opc = X86ISD::VPCOMU;
9607 SDValue LHS = Op.getOperand(1);
9608 SDValue RHS = Op.getOperand(2);
9609 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9610 DAG.getConstant(CC, MVT::i8));
9613 // Arithmetic intrinsics.
9614 case Intrinsic::x86_sse2_pmulu_dq:
9615 case Intrinsic::x86_avx2_pmulu_dq:
9616 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9617 Op.getOperand(1), Op.getOperand(2));
9618 case Intrinsic::x86_sse3_hadd_ps:
9619 case Intrinsic::x86_sse3_hadd_pd:
9620 case Intrinsic::x86_avx_hadd_ps_256:
9621 case Intrinsic::x86_avx_hadd_pd_256:
9622 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9623 Op.getOperand(1), Op.getOperand(2));
9624 case Intrinsic::x86_sse3_hsub_ps:
9625 case Intrinsic::x86_sse3_hsub_pd:
9626 case Intrinsic::x86_avx_hsub_ps_256:
9627 case Intrinsic::x86_avx_hsub_pd_256:
9628 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9629 Op.getOperand(1), Op.getOperand(2));
9630 case Intrinsic::x86_ssse3_phadd_w_128:
9631 case Intrinsic::x86_ssse3_phadd_d_128:
9632 case Intrinsic::x86_avx2_phadd_w:
9633 case Intrinsic::x86_avx2_phadd_d:
9634 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9635 Op.getOperand(1), Op.getOperand(2));
9636 case Intrinsic::x86_ssse3_phsub_w_128:
9637 case Intrinsic::x86_ssse3_phsub_d_128:
9638 case Intrinsic::x86_avx2_phsub_w:
9639 case Intrinsic::x86_avx2_phsub_d:
9640 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9641 Op.getOperand(1), Op.getOperand(2));
9642 case Intrinsic::x86_avx2_psllv_d:
9643 case Intrinsic::x86_avx2_psllv_q:
9644 case Intrinsic::x86_avx2_psllv_d_256:
9645 case Intrinsic::x86_avx2_psllv_q_256:
9646 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9647 Op.getOperand(1), Op.getOperand(2));
9648 case Intrinsic::x86_avx2_psrlv_d:
9649 case Intrinsic::x86_avx2_psrlv_q:
9650 case Intrinsic::x86_avx2_psrlv_d_256:
9651 case Intrinsic::x86_avx2_psrlv_q_256:
9652 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9653 Op.getOperand(1), Op.getOperand(2));
9654 case Intrinsic::x86_avx2_psrav_d:
9655 case Intrinsic::x86_avx2_psrav_d_256:
9656 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9657 Op.getOperand(1), Op.getOperand(2));
9658 case Intrinsic::x86_ssse3_pshuf_b_128:
9659 case Intrinsic::x86_avx2_pshuf_b:
9660 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9661 Op.getOperand(1), Op.getOperand(2));
9662 case Intrinsic::x86_ssse3_psign_b_128:
9663 case Intrinsic::x86_ssse3_psign_w_128:
9664 case Intrinsic::x86_ssse3_psign_d_128:
9665 case Intrinsic::x86_avx2_psign_b:
9666 case Intrinsic::x86_avx2_psign_w:
9667 case Intrinsic::x86_avx2_psign_d:
9668 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9669 Op.getOperand(1), Op.getOperand(2));
9670 case Intrinsic::x86_sse41_insertps:
9671 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9672 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9673 case Intrinsic::x86_avx_vperm2f128_ps_256:
9674 case Intrinsic::x86_avx_vperm2f128_pd_256:
9675 case Intrinsic::x86_avx_vperm2f128_si_256:
9676 case Intrinsic::x86_avx2_vperm2i128:
9677 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9678 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9679 case Intrinsic::x86_avx2_permd:
9680 case Intrinsic::x86_avx2_permps:
9681 // Operands intentionally swapped. Mask is last operand to intrinsic,
9682 // but second operand for node/intruction.
9683 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9684 Op.getOperand(2), Op.getOperand(1));
9686 // ptest and testp intrinsics. The intrinsic these come from are designed to
9687 // return an integer value, not just an instruction so lower it to the ptest
9688 // or testp pattern and a setcc for the result.
9689 case Intrinsic::x86_sse41_ptestz:
9690 case Intrinsic::x86_sse41_ptestc:
9691 case Intrinsic::x86_sse41_ptestnzc:
9692 case Intrinsic::x86_avx_ptestz_256:
9693 case Intrinsic::x86_avx_ptestc_256:
9694 case Intrinsic::x86_avx_ptestnzc_256:
9695 case Intrinsic::x86_avx_vtestz_ps:
9696 case Intrinsic::x86_avx_vtestc_ps:
9697 case Intrinsic::x86_avx_vtestnzc_ps:
9698 case Intrinsic::x86_avx_vtestz_pd:
9699 case Intrinsic::x86_avx_vtestc_pd:
9700 case Intrinsic::x86_avx_vtestnzc_pd:
9701 case Intrinsic::x86_avx_vtestz_ps_256:
9702 case Intrinsic::x86_avx_vtestc_ps_256:
9703 case Intrinsic::x86_avx_vtestnzc_ps_256:
9704 case Intrinsic::x86_avx_vtestz_pd_256:
9705 case Intrinsic::x86_avx_vtestc_pd_256:
9706 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9707 bool IsTestPacked = false;
9710 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9711 case Intrinsic::x86_avx_vtestz_ps:
9712 case Intrinsic::x86_avx_vtestz_pd:
9713 case Intrinsic::x86_avx_vtestz_ps_256:
9714 case Intrinsic::x86_avx_vtestz_pd_256:
9715 IsTestPacked = true; // Fallthrough
9716 case Intrinsic::x86_sse41_ptestz:
9717 case Intrinsic::x86_avx_ptestz_256:
9719 X86CC = X86::COND_E;
9721 case Intrinsic::x86_avx_vtestc_ps:
9722 case Intrinsic::x86_avx_vtestc_pd:
9723 case Intrinsic::x86_avx_vtestc_ps_256:
9724 case Intrinsic::x86_avx_vtestc_pd_256:
9725 IsTestPacked = true; // Fallthrough
9726 case Intrinsic::x86_sse41_ptestc:
9727 case Intrinsic::x86_avx_ptestc_256:
9729 X86CC = X86::COND_B;
9731 case Intrinsic::x86_avx_vtestnzc_ps:
9732 case Intrinsic::x86_avx_vtestnzc_pd:
9733 case Intrinsic::x86_avx_vtestnzc_ps_256:
9734 case Intrinsic::x86_avx_vtestnzc_pd_256:
9735 IsTestPacked = true; // Fallthrough
9736 case Intrinsic::x86_sse41_ptestnzc:
9737 case Intrinsic::x86_avx_ptestnzc_256:
9739 X86CC = X86::COND_A;
9743 SDValue LHS = Op.getOperand(1);
9744 SDValue RHS = Op.getOperand(2);
9745 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9746 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9747 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9748 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9749 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9752 // SSE/AVX shift intrinsics
9753 case Intrinsic::x86_sse2_psll_w:
9754 case Intrinsic::x86_sse2_psll_d:
9755 case Intrinsic::x86_sse2_psll_q:
9756 case Intrinsic::x86_avx2_psll_w:
9757 case Intrinsic::x86_avx2_psll_d:
9758 case Intrinsic::x86_avx2_psll_q:
9759 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9760 Op.getOperand(1), Op.getOperand(2));
9761 case Intrinsic::x86_sse2_psrl_w:
9762 case Intrinsic::x86_sse2_psrl_d:
9763 case Intrinsic::x86_sse2_psrl_q:
9764 case Intrinsic::x86_avx2_psrl_w:
9765 case Intrinsic::x86_avx2_psrl_d:
9766 case Intrinsic::x86_avx2_psrl_q:
9767 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9768 Op.getOperand(1), Op.getOperand(2));
9769 case Intrinsic::x86_sse2_psra_w:
9770 case Intrinsic::x86_sse2_psra_d:
9771 case Intrinsic::x86_avx2_psra_w:
9772 case Intrinsic::x86_avx2_psra_d:
9773 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9774 Op.getOperand(1), Op.getOperand(2));
9775 case Intrinsic::x86_sse2_pslli_w:
9776 case Intrinsic::x86_sse2_pslli_d:
9777 case Intrinsic::x86_sse2_pslli_q:
9778 case Intrinsic::x86_avx2_pslli_w:
9779 case Intrinsic::x86_avx2_pslli_d:
9780 case Intrinsic::x86_avx2_pslli_q:
9781 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9782 Op.getOperand(1), Op.getOperand(2), DAG);
9783 case Intrinsic::x86_sse2_psrli_w:
9784 case Intrinsic::x86_sse2_psrli_d:
9785 case Intrinsic::x86_sse2_psrli_q:
9786 case Intrinsic::x86_avx2_psrli_w:
9787 case Intrinsic::x86_avx2_psrli_d:
9788 case Intrinsic::x86_avx2_psrli_q:
9789 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9790 Op.getOperand(1), Op.getOperand(2), DAG);
9791 case Intrinsic::x86_sse2_psrai_w:
9792 case Intrinsic::x86_sse2_psrai_d:
9793 case Intrinsic::x86_avx2_psrai_w:
9794 case Intrinsic::x86_avx2_psrai_d:
9795 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9796 Op.getOperand(1), Op.getOperand(2), DAG);
9797 // Fix vector shift instructions where the last operand is a non-immediate
9799 case Intrinsic::x86_mmx_pslli_w:
9800 case Intrinsic::x86_mmx_pslli_d:
9801 case Intrinsic::x86_mmx_pslli_q:
9802 case Intrinsic::x86_mmx_psrli_w:
9803 case Intrinsic::x86_mmx_psrli_d:
9804 case Intrinsic::x86_mmx_psrli_q:
9805 case Intrinsic::x86_mmx_psrai_w:
9806 case Intrinsic::x86_mmx_psrai_d: {
9807 SDValue ShAmt = Op.getOperand(2);
9808 if (isa<ConstantSDNode>(ShAmt))
9811 unsigned NewIntNo = 0;
9813 case Intrinsic::x86_mmx_pslli_w:
9814 NewIntNo = Intrinsic::x86_mmx_psll_w;
9816 case Intrinsic::x86_mmx_pslli_d:
9817 NewIntNo = Intrinsic::x86_mmx_psll_d;
9819 case Intrinsic::x86_mmx_pslli_q:
9820 NewIntNo = Intrinsic::x86_mmx_psll_q;
9822 case Intrinsic::x86_mmx_psrli_w:
9823 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9825 case Intrinsic::x86_mmx_psrli_d:
9826 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9828 case Intrinsic::x86_mmx_psrli_q:
9829 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9831 case Intrinsic::x86_mmx_psrai_w:
9832 NewIntNo = Intrinsic::x86_mmx_psra_w;
9834 case Intrinsic::x86_mmx_psrai_d:
9835 NewIntNo = Intrinsic::x86_mmx_psra_d;
9837 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9840 // The vector shift intrinsics with scalars uses 32b shift amounts but
9841 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9843 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9844 DAG.getConstant(0, MVT::i32));
9845 // FIXME this must be lowered to get rid of the invalid type.
9847 EVT VT = Op.getValueType();
9848 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9849 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9850 DAG.getConstant(NewIntNo, MVT::i32),
9851 Op.getOperand(1), ShAmt);
9856 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9857 SelectionDAG &DAG) const {
9858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9859 MFI->setReturnAddressIsTaken(true);
9861 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9862 DebugLoc dl = Op.getDebugLoc();
9865 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9867 DAG.getConstant(TD->getPointerSize(),
9868 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9869 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9870 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9872 MachinePointerInfo(), false, false, false, 0);
9875 // Just load the return address.
9876 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9877 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9878 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9881 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9882 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9883 MFI->setFrameAddressIsTaken(true);
9885 EVT VT = Op.getValueType();
9886 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9887 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9888 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9889 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9891 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9892 MachinePointerInfo(),
9893 false, false, false, 0);
9897 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9898 SelectionDAG &DAG) const {
9899 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9902 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9903 MachineFunction &MF = DAG.getMachineFunction();
9904 SDValue Chain = Op.getOperand(0);
9905 SDValue Offset = Op.getOperand(1);
9906 SDValue Handler = Op.getOperand(2);
9907 DebugLoc dl = Op.getDebugLoc();
9909 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9910 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9912 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9914 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9915 DAG.getIntPtrConstant(TD->getPointerSize()));
9916 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9917 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9919 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9920 MF.getRegInfo().addLiveOut(StoreAddrReg);
9922 return DAG.getNode(X86ISD::EH_RETURN, dl,
9924 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9927 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9928 SelectionDAG &DAG) const {
9929 return Op.getOperand(0);
9932 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9933 SelectionDAG &DAG) const {
9934 SDValue Root = Op.getOperand(0);
9935 SDValue Trmp = Op.getOperand(1); // trampoline
9936 SDValue FPtr = Op.getOperand(2); // nested function
9937 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9938 DebugLoc dl = Op.getDebugLoc();
9940 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9942 if (Subtarget->is64Bit()) {
9943 SDValue OutChains[6];
9945 // Large code-model.
9946 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9947 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9949 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9950 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9952 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9954 // Load the pointer to the nested function into R11.
9955 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9956 SDValue Addr = Trmp;
9957 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9958 Addr, MachinePointerInfo(TrmpAddr),
9961 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9962 DAG.getConstant(2, MVT::i64));
9963 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9964 MachinePointerInfo(TrmpAddr, 2),
9967 // Load the 'nest' parameter value into R10.
9968 // R10 is specified in X86CallingConv.td
9969 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9970 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9971 DAG.getConstant(10, MVT::i64));
9972 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9973 Addr, MachinePointerInfo(TrmpAddr, 10),
9976 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9977 DAG.getConstant(12, MVT::i64));
9978 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9979 MachinePointerInfo(TrmpAddr, 12),
9982 // Jump to the nested function.
9983 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9984 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9985 DAG.getConstant(20, MVT::i64));
9986 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9987 Addr, MachinePointerInfo(TrmpAddr, 20),
9990 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9991 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9992 DAG.getConstant(22, MVT::i64));
9993 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9994 MachinePointerInfo(TrmpAddr, 22),
9997 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9999 const Function *Func =
10000 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
10001 CallingConv::ID CC = Func->getCallingConv();
10006 llvm_unreachable("Unsupported calling convention");
10007 case CallingConv::C:
10008 case CallingConv::X86_StdCall: {
10009 // Pass 'nest' parameter in ECX.
10010 // Must be kept in sync with X86CallingConv.td
10011 NestReg = X86::ECX;
10013 // Check that ECX wasn't needed by an 'inreg' parameter.
10014 FunctionType *FTy = Func->getFunctionType();
10015 const AttrListPtr &Attrs = Func->getAttributes();
10017 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10018 unsigned InRegCount = 0;
10021 for (FunctionType::param_iterator I = FTy->param_begin(),
10022 E = FTy->param_end(); I != E; ++I, ++Idx)
10023 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
10024 // FIXME: should only count parameters that are lowered to integers.
10025 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10027 if (InRegCount > 2) {
10028 report_fatal_error("Nest register in use - reduce number of inreg"
10034 case CallingConv::X86_FastCall:
10035 case CallingConv::X86_ThisCall:
10036 case CallingConv::Fast:
10037 // Pass 'nest' parameter in EAX.
10038 // Must be kept in sync with X86CallingConv.td
10039 NestReg = X86::EAX;
10043 SDValue OutChains[4];
10044 SDValue Addr, Disp;
10046 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10047 DAG.getConstant(10, MVT::i32));
10048 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10050 // This is storing the opcode for MOV32ri.
10051 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10052 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10053 OutChains[0] = DAG.getStore(Root, dl,
10054 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10055 Trmp, MachinePointerInfo(TrmpAddr),
10058 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10059 DAG.getConstant(1, MVT::i32));
10060 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10061 MachinePointerInfo(TrmpAddr, 1),
10064 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10065 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10066 DAG.getConstant(5, MVT::i32));
10067 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10068 MachinePointerInfo(TrmpAddr, 5),
10071 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10072 DAG.getConstant(6, MVT::i32));
10073 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10074 MachinePointerInfo(TrmpAddr, 6),
10077 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10081 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10082 SelectionDAG &DAG) const {
10084 The rounding mode is in bits 11:10 of FPSR, and has the following
10086 00 Round to nearest
10091 FLT_ROUNDS, on the other hand, expects the following:
10098 To perform the conversion, we do:
10099 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10102 MachineFunction &MF = DAG.getMachineFunction();
10103 const TargetMachine &TM = MF.getTarget();
10104 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10105 unsigned StackAlignment = TFI.getStackAlignment();
10106 EVT VT = Op.getValueType();
10107 DebugLoc DL = Op.getDebugLoc();
10109 // Save FP Control Word to stack slot
10110 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10111 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10114 MachineMemOperand *MMO =
10115 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10116 MachineMemOperand::MOStore, 2, 2);
10118 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10119 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10120 DAG.getVTList(MVT::Other),
10121 Ops, 2, MVT::i16, MMO);
10123 // Load FP Control Word from stack slot
10124 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10125 MachinePointerInfo(), false, false, false, 0);
10127 // Transform as necessary
10129 DAG.getNode(ISD::SRL, DL, MVT::i16,
10130 DAG.getNode(ISD::AND, DL, MVT::i16,
10131 CWD, DAG.getConstant(0x800, MVT::i16)),
10132 DAG.getConstant(11, MVT::i8));
10134 DAG.getNode(ISD::SRL, DL, MVT::i16,
10135 DAG.getNode(ISD::AND, DL, MVT::i16,
10136 CWD, DAG.getConstant(0x400, MVT::i16)),
10137 DAG.getConstant(9, MVT::i8));
10140 DAG.getNode(ISD::AND, DL, MVT::i16,
10141 DAG.getNode(ISD::ADD, DL, MVT::i16,
10142 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10143 DAG.getConstant(1, MVT::i16)),
10144 DAG.getConstant(3, MVT::i16));
10147 return DAG.getNode((VT.getSizeInBits() < 16 ?
10148 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10151 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10152 EVT VT = Op.getValueType();
10154 unsigned NumBits = VT.getSizeInBits();
10155 DebugLoc dl = Op.getDebugLoc();
10157 Op = Op.getOperand(0);
10158 if (VT == MVT::i8) {
10159 // Zero extend to i32 since there is not an i8 bsr.
10161 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10164 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10165 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10166 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10168 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10171 DAG.getConstant(NumBits+NumBits-1, OpVT),
10172 DAG.getConstant(X86::COND_E, MVT::i8),
10175 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10177 // Finally xor with NumBits-1.
10178 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10181 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10185 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10186 SelectionDAG &DAG) const {
10187 EVT VT = Op.getValueType();
10189 unsigned NumBits = VT.getSizeInBits();
10190 DebugLoc dl = Op.getDebugLoc();
10192 Op = Op.getOperand(0);
10193 if (VT == MVT::i8) {
10194 // Zero extend to i32 since there is not an i8 bsr.
10196 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10199 // Issue a bsr (scan bits in reverse).
10200 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10201 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10203 // And xor with NumBits-1.
10204 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10207 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10211 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10212 EVT VT = Op.getValueType();
10213 unsigned NumBits = VT.getSizeInBits();
10214 DebugLoc dl = Op.getDebugLoc();
10215 Op = Op.getOperand(0);
10217 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10218 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10219 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10221 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10224 DAG.getConstant(NumBits, VT),
10225 DAG.getConstant(X86::COND_E, MVT::i8),
10228 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10231 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10232 // ones, and then concatenate the result back.
10233 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10234 EVT VT = Op.getValueType();
10236 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10237 "Unsupported value type for operation");
10239 unsigned NumElems = VT.getVectorNumElements();
10240 DebugLoc dl = Op.getDebugLoc();
10242 // Extract the LHS vectors
10243 SDValue LHS = Op.getOperand(0);
10244 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10245 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10247 // Extract the RHS vectors
10248 SDValue RHS = Op.getOperand(1);
10249 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10250 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10252 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10253 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10255 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10256 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10257 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10260 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10261 assert(Op.getValueType().getSizeInBits() == 256 &&
10262 Op.getValueType().isInteger() &&
10263 "Only handle AVX 256-bit vector integer operation");
10264 return Lower256IntArith(Op, DAG);
10267 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10268 assert(Op.getValueType().getSizeInBits() == 256 &&
10269 Op.getValueType().isInteger() &&
10270 "Only handle AVX 256-bit vector integer operation");
10271 return Lower256IntArith(Op, DAG);
10274 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10275 EVT VT = Op.getValueType();
10277 // Decompose 256-bit ops into smaller 128-bit ops.
10278 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10279 return Lower256IntArith(Op, DAG);
10281 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10282 "Only know how to lower V2I64/V4I64 multiply");
10284 DebugLoc dl = Op.getDebugLoc();
10286 // Ahi = psrlqi(a, 32);
10287 // Bhi = psrlqi(b, 32);
10289 // AloBlo = pmuludq(a, b);
10290 // AloBhi = pmuludq(a, Bhi);
10291 // AhiBlo = pmuludq(Ahi, b);
10293 // AloBhi = psllqi(AloBhi, 32);
10294 // AhiBlo = psllqi(AhiBlo, 32);
10295 // return AloBlo + AloBhi + AhiBlo;
10297 SDValue A = Op.getOperand(0);
10298 SDValue B = Op.getOperand(1);
10300 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10302 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10303 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10305 // Bit cast to 32-bit vectors for MULUDQ
10306 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10307 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10308 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10309 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10310 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10312 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10313 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10314 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10316 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10317 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10319 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10320 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10323 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10325 EVT VT = Op.getValueType();
10326 DebugLoc dl = Op.getDebugLoc();
10327 SDValue R = Op.getOperand(0);
10328 SDValue Amt = Op.getOperand(1);
10329 LLVMContext *Context = DAG.getContext();
10331 if (!Subtarget->hasSSE2())
10334 // Optimize shl/srl/sra with constant shift amount.
10335 if (isSplatVector(Amt.getNode())) {
10336 SDValue SclrAmt = Amt->getOperand(0);
10337 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10338 uint64_t ShiftAmt = C->getZExtValue();
10340 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10341 (Subtarget->hasAVX2() &&
10342 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10343 if (Op.getOpcode() == ISD::SHL)
10344 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10345 DAG.getConstant(ShiftAmt, MVT::i32));
10346 if (Op.getOpcode() == ISD::SRL)
10347 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10348 DAG.getConstant(ShiftAmt, MVT::i32));
10349 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10350 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10351 DAG.getConstant(ShiftAmt, MVT::i32));
10354 if (VT == MVT::v16i8) {
10355 if (Op.getOpcode() == ISD::SHL) {
10356 // Make a large shift.
10357 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10358 DAG.getConstant(ShiftAmt, MVT::i32));
10359 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10360 // Zero out the rightmost bits.
10361 SmallVector<SDValue, 16> V(16,
10362 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10364 return DAG.getNode(ISD::AND, dl, VT, SHL,
10365 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10367 if (Op.getOpcode() == ISD::SRL) {
10368 // Make a large shift.
10369 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10370 DAG.getConstant(ShiftAmt, MVT::i32));
10371 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10372 // Zero out the leftmost bits.
10373 SmallVector<SDValue, 16> V(16,
10374 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10376 return DAG.getNode(ISD::AND, dl, VT, SRL,
10377 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10379 if (Op.getOpcode() == ISD::SRA) {
10380 if (ShiftAmt == 7) {
10381 // R s>> 7 === R s< 0
10382 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10383 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10386 // R s>> a === ((R u>> a) ^ m) - m
10387 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10388 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10390 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10391 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10392 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10395 llvm_unreachable("Unknown shift opcode.");
10398 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10399 if (Op.getOpcode() == ISD::SHL) {
10400 // Make a large shift.
10401 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10402 DAG.getConstant(ShiftAmt, MVT::i32));
10403 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10404 // Zero out the rightmost bits.
10405 SmallVector<SDValue, 32> V(32,
10406 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10408 return DAG.getNode(ISD::AND, dl, VT, SHL,
10409 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10411 if (Op.getOpcode() == ISD::SRL) {
10412 // Make a large shift.
10413 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10414 DAG.getConstant(ShiftAmt, MVT::i32));
10415 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10416 // Zero out the leftmost bits.
10417 SmallVector<SDValue, 32> V(32,
10418 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10420 return DAG.getNode(ISD::AND, dl, VT, SRL,
10421 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10423 if (Op.getOpcode() == ISD::SRA) {
10424 if (ShiftAmt == 7) {
10425 // R s>> 7 === R s< 0
10426 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10427 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10430 // R s>> a === ((R u>> a) ^ m) - m
10431 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10432 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10434 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10435 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10436 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10439 llvm_unreachable("Unknown shift opcode.");
10444 // Lower SHL with variable shift amount.
10445 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10446 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10447 DAG.getConstant(23, MVT::i32));
10449 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10450 Constant *C = ConstantDataVector::get(*Context, CV);
10451 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10452 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10453 MachinePointerInfo::getConstantPool(),
10454 false, false, false, 16);
10456 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10457 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10458 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10459 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10461 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10462 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10465 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10466 DAG.getConstant(5, MVT::i32));
10467 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10469 // Turn 'a' into a mask suitable for VSELECT
10470 SDValue VSelM = DAG.getConstant(0x80, VT);
10471 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10472 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10474 SDValue CM1 = DAG.getConstant(0x0f, VT);
10475 SDValue CM2 = DAG.getConstant(0x3f, VT);
10477 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10478 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10479 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10480 DAG.getConstant(4, MVT::i32), DAG);
10481 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10482 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10485 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10486 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10487 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10489 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10490 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10491 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10492 DAG.getConstant(2, MVT::i32), DAG);
10493 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10494 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10497 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10498 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10499 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10501 // return VSELECT(r, r+r, a);
10502 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10503 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10507 // Decompose 256-bit shifts into smaller 128-bit shifts.
10508 if (VT.getSizeInBits() == 256) {
10509 unsigned NumElems = VT.getVectorNumElements();
10510 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10511 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10513 // Extract the two vectors
10514 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10515 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10517 // Recreate the shift amount vectors
10518 SDValue Amt1, Amt2;
10519 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10520 // Constant shift amount
10521 SmallVector<SDValue, 4> Amt1Csts;
10522 SmallVector<SDValue, 4> Amt2Csts;
10523 for (unsigned i = 0; i != NumElems/2; ++i)
10524 Amt1Csts.push_back(Amt->getOperand(i));
10525 for (unsigned i = NumElems/2; i != NumElems; ++i)
10526 Amt2Csts.push_back(Amt->getOperand(i));
10528 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10529 &Amt1Csts[0], NumElems/2);
10530 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10531 &Amt2Csts[0], NumElems/2);
10533 // Variable shift amount
10534 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10535 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10538 // Issue new vector shifts for the smaller types
10539 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10540 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10542 // Concatenate the result back
10543 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10549 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10550 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10551 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10552 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10553 // has only one use.
10554 SDNode *N = Op.getNode();
10555 SDValue LHS = N->getOperand(0);
10556 SDValue RHS = N->getOperand(1);
10557 unsigned BaseOp = 0;
10559 DebugLoc DL = Op.getDebugLoc();
10560 switch (Op.getOpcode()) {
10561 default: llvm_unreachable("Unknown ovf instruction!");
10563 // A subtract of one will be selected as a INC. Note that INC doesn't
10564 // set CF, so we can't do this for UADDO.
10565 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10567 BaseOp = X86ISD::INC;
10568 Cond = X86::COND_O;
10571 BaseOp = X86ISD::ADD;
10572 Cond = X86::COND_O;
10575 BaseOp = X86ISD::ADD;
10576 Cond = X86::COND_B;
10579 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10580 // set CF, so we can't do this for USUBO.
10581 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10583 BaseOp = X86ISD::DEC;
10584 Cond = X86::COND_O;
10587 BaseOp = X86ISD::SUB;
10588 Cond = X86::COND_O;
10591 BaseOp = X86ISD::SUB;
10592 Cond = X86::COND_B;
10595 BaseOp = X86ISD::SMUL;
10596 Cond = X86::COND_O;
10598 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10599 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10601 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10604 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10605 DAG.getConstant(X86::COND_O, MVT::i32),
10606 SDValue(Sum.getNode(), 2));
10608 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10612 // Also sets EFLAGS.
10613 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10614 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10617 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10618 DAG.getConstant(Cond, MVT::i32),
10619 SDValue(Sum.getNode(), 1));
10621 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10624 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10625 SelectionDAG &DAG) const {
10626 DebugLoc dl = Op.getDebugLoc();
10627 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10628 EVT VT = Op.getValueType();
10630 if (!Subtarget->hasSSE2() || !VT.isVector())
10633 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10634 ExtraVT.getScalarType().getSizeInBits();
10635 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10637 switch (VT.getSimpleVT().SimpleTy) {
10638 default: return SDValue();
10641 if (!Subtarget->hasAVX())
10643 if (!Subtarget->hasAVX2()) {
10644 // needs to be split
10645 unsigned NumElems = VT.getVectorNumElements();
10647 // Extract the LHS vectors
10648 SDValue LHS = Op.getOperand(0);
10649 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10650 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10652 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10653 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10655 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10656 int ExtraNumElems = ExtraVT.getVectorNumElements();
10657 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10659 SDValue Extra = DAG.getValueType(ExtraVT);
10661 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10662 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10664 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10669 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10670 Op.getOperand(0), ShAmt, DAG);
10671 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10677 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10678 DebugLoc dl = Op.getDebugLoc();
10680 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10681 // There isn't any reason to disable it if the target processor supports it.
10682 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10683 SDValue Chain = Op.getOperand(0);
10684 SDValue Zero = DAG.getConstant(0, MVT::i32);
10686 DAG.getRegister(X86::ESP, MVT::i32), // Base
10687 DAG.getTargetConstant(1, MVT::i8), // Scale
10688 DAG.getRegister(0, MVT::i32), // Index
10689 DAG.getTargetConstant(0, MVT::i32), // Disp
10690 DAG.getRegister(0, MVT::i32), // Segment.
10695 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10696 array_lengthof(Ops));
10697 return SDValue(Res, 0);
10700 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10702 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10704 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10705 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10706 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10707 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10709 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10710 if (!Op1 && !Op2 && !Op3 && Op4)
10711 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10713 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10714 if (Op1 && !Op2 && !Op3 && !Op4)
10715 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10717 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10719 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10722 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10723 SelectionDAG &DAG) const {
10724 DebugLoc dl = Op.getDebugLoc();
10725 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10726 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10727 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10728 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10730 // The only fence that needs an instruction is a sequentially-consistent
10731 // cross-thread fence.
10732 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10733 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10734 // no-sse2). There isn't any reason to disable it if the target processor
10736 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10737 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10739 SDValue Chain = Op.getOperand(0);
10740 SDValue Zero = DAG.getConstant(0, MVT::i32);
10742 DAG.getRegister(X86::ESP, MVT::i32), // Base
10743 DAG.getTargetConstant(1, MVT::i8), // Scale
10744 DAG.getRegister(0, MVT::i32), // Index
10745 DAG.getTargetConstant(0, MVT::i32), // Disp
10746 DAG.getRegister(0, MVT::i32), // Segment.
10751 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10752 array_lengthof(Ops));
10753 return SDValue(Res, 0);
10756 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10757 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10761 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10762 EVT T = Op.getValueType();
10763 DebugLoc DL = Op.getDebugLoc();
10766 switch(T.getSimpleVT().SimpleTy) {
10767 default: llvm_unreachable("Invalid value type!");
10768 case MVT::i8: Reg = X86::AL; size = 1; break;
10769 case MVT::i16: Reg = X86::AX; size = 2; break;
10770 case MVT::i32: Reg = X86::EAX; size = 4; break;
10772 assert(Subtarget->is64Bit() && "Node not type legal!");
10773 Reg = X86::RAX; size = 8;
10776 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10777 Op.getOperand(2), SDValue());
10778 SDValue Ops[] = { cpIn.getValue(0),
10781 DAG.getTargetConstant(size, MVT::i8),
10782 cpIn.getValue(1) };
10783 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10784 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10785 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10788 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10792 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10793 SelectionDAG &DAG) const {
10794 assert(Subtarget->is64Bit() && "Result not type legalized?");
10795 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10796 SDValue TheChain = Op.getOperand(0);
10797 DebugLoc dl = Op.getDebugLoc();
10798 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10799 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10800 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10802 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10803 DAG.getConstant(32, MVT::i8));
10805 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10808 return DAG.getMergeValues(Ops, 2, dl);
10811 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10812 SelectionDAG &DAG) const {
10813 EVT SrcVT = Op.getOperand(0).getValueType();
10814 EVT DstVT = Op.getValueType();
10815 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10816 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10817 assert((DstVT == MVT::i64 ||
10818 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10819 "Unexpected custom BITCAST");
10820 // i64 <=> MMX conversions are Legal.
10821 if (SrcVT==MVT::i64 && DstVT.isVector())
10823 if (DstVT==MVT::i64 && SrcVT.isVector())
10825 // MMX <=> MMX conversions are Legal.
10826 if (SrcVT.isVector() && DstVT.isVector())
10828 // All other conversions need to be expanded.
10832 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10833 SDNode *Node = Op.getNode();
10834 DebugLoc dl = Node->getDebugLoc();
10835 EVT T = Node->getValueType(0);
10836 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10837 DAG.getConstant(0, T), Node->getOperand(2));
10838 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10839 cast<AtomicSDNode>(Node)->getMemoryVT(),
10840 Node->getOperand(0),
10841 Node->getOperand(1), negOp,
10842 cast<AtomicSDNode>(Node)->getSrcValue(),
10843 cast<AtomicSDNode>(Node)->getAlignment(),
10844 cast<AtomicSDNode>(Node)->getOrdering(),
10845 cast<AtomicSDNode>(Node)->getSynchScope());
10848 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10849 SDNode *Node = Op.getNode();
10850 DebugLoc dl = Node->getDebugLoc();
10851 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10853 // Convert seq_cst store -> xchg
10854 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10855 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10856 // (The only way to get a 16-byte store is cmpxchg16b)
10857 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10858 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10859 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10860 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10861 cast<AtomicSDNode>(Node)->getMemoryVT(),
10862 Node->getOperand(0),
10863 Node->getOperand(1), Node->getOperand(2),
10864 cast<AtomicSDNode>(Node)->getMemOperand(),
10865 cast<AtomicSDNode>(Node)->getOrdering(),
10866 cast<AtomicSDNode>(Node)->getSynchScope());
10867 return Swap.getValue(1);
10869 // Other atomic stores have a simple pattern.
10873 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10874 EVT VT = Op.getNode()->getValueType(0);
10876 // Let legalize expand this if it isn't a legal type yet.
10877 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10880 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10883 bool ExtraOp = false;
10884 switch (Op.getOpcode()) {
10885 default: llvm_unreachable("Invalid code");
10886 case ISD::ADDC: Opc = X86ISD::ADD; break;
10887 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10888 case ISD::SUBC: Opc = X86ISD::SUB; break;
10889 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10893 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10895 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10896 Op.getOperand(1), Op.getOperand(2));
10899 /// LowerOperation - Provide custom lowering hooks for some operations.
10901 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10902 switch (Op.getOpcode()) {
10903 default: llvm_unreachable("Should not custom lower this!");
10904 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10905 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10906 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10907 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10908 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10909 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10910 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10911 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10912 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10913 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10914 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10915 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10916 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10917 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10918 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10919 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10920 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10921 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10922 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10923 case ISD::SHL_PARTS:
10924 case ISD::SRA_PARTS:
10925 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10926 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10927 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10928 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10929 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10930 case ISD::FABS: return LowerFABS(Op, DAG);
10931 case ISD::FNEG: return LowerFNEG(Op, DAG);
10932 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10933 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10934 case ISD::SETCC: return LowerSETCC(Op, DAG);
10935 case ISD::SELECT: return LowerSELECT(Op, DAG);
10936 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10937 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10938 case ISD::VASTART: return LowerVASTART(Op, DAG);
10939 case ISD::VAARG: return LowerVAARG(Op, DAG);
10940 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10941 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10942 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10943 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10944 case ISD::FRAME_TO_ARGS_OFFSET:
10945 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10946 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10947 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10948 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10949 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10950 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10951 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10952 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10953 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10954 case ISD::MUL: return LowerMUL(Op, DAG);
10957 case ISD::SHL: return LowerShift(Op, DAG);
10963 case ISD::UMULO: return LowerXALUO(Op, DAG);
10964 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10965 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10969 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10970 case ISD::ADD: return LowerADD(Op, DAG);
10971 case ISD::SUB: return LowerSUB(Op, DAG);
10975 static void ReplaceATOMIC_LOAD(SDNode *Node,
10976 SmallVectorImpl<SDValue> &Results,
10977 SelectionDAG &DAG) {
10978 DebugLoc dl = Node->getDebugLoc();
10979 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10981 // Convert wide load -> cmpxchg8b/cmpxchg16b
10982 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10983 // (The only way to get a 16-byte load is cmpxchg16b)
10984 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10985 SDValue Zero = DAG.getConstant(0, VT);
10986 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10987 Node->getOperand(0),
10988 Node->getOperand(1), Zero, Zero,
10989 cast<AtomicSDNode>(Node)->getMemOperand(),
10990 cast<AtomicSDNode>(Node)->getOrdering(),
10991 cast<AtomicSDNode>(Node)->getSynchScope());
10992 Results.push_back(Swap.getValue(0));
10993 Results.push_back(Swap.getValue(1));
10996 void X86TargetLowering::
10997 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10998 SelectionDAG &DAG, unsigned NewOp) const {
10999 DebugLoc dl = Node->getDebugLoc();
11000 assert (Node->getValueType(0) == MVT::i64 &&
11001 "Only know how to expand i64 atomics");
11003 SDValue Chain = Node->getOperand(0);
11004 SDValue In1 = Node->getOperand(1);
11005 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11006 Node->getOperand(2), DAG.getIntPtrConstant(0));
11007 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11008 Node->getOperand(2), DAG.getIntPtrConstant(1));
11009 SDValue Ops[] = { Chain, In1, In2L, In2H };
11010 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11012 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11013 cast<MemSDNode>(Node)->getMemOperand());
11014 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11015 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11016 Results.push_back(Result.getValue(2));
11019 /// ReplaceNodeResults - Replace a node with an illegal result type
11020 /// with a new node built out of custom code.
11021 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11022 SmallVectorImpl<SDValue>&Results,
11023 SelectionDAG &DAG) const {
11024 DebugLoc dl = N->getDebugLoc();
11025 switch (N->getOpcode()) {
11027 llvm_unreachable("Do not know how to custom type legalize this operation!");
11028 case ISD::SIGN_EXTEND_INREG:
11033 // We don't want to expand or promote these.
11035 case ISD::FP_TO_SINT:
11036 case ISD::FP_TO_UINT: {
11037 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11039 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11042 std::pair<SDValue,SDValue> Vals =
11043 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11044 SDValue FIST = Vals.first, StackSlot = Vals.second;
11045 if (FIST.getNode() != 0) {
11046 EVT VT = N->getValueType(0);
11047 // Return a load from the stack slot.
11048 if (StackSlot.getNode() != 0)
11049 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11050 MachinePointerInfo(),
11051 false, false, false, 0));
11053 Results.push_back(FIST);
11057 case ISD::READCYCLECOUNTER: {
11058 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11059 SDValue TheChain = N->getOperand(0);
11060 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11061 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11063 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11065 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11066 SDValue Ops[] = { eax, edx };
11067 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11068 Results.push_back(edx.getValue(1));
11071 case ISD::ATOMIC_CMP_SWAP: {
11072 EVT T = N->getValueType(0);
11073 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11074 bool Regs64bit = T == MVT::i128;
11075 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11076 SDValue cpInL, cpInH;
11077 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11078 DAG.getConstant(0, HalfT));
11079 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11080 DAG.getConstant(1, HalfT));
11081 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11082 Regs64bit ? X86::RAX : X86::EAX,
11084 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11085 Regs64bit ? X86::RDX : X86::EDX,
11086 cpInH, cpInL.getValue(1));
11087 SDValue swapInL, swapInH;
11088 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11089 DAG.getConstant(0, HalfT));
11090 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11091 DAG.getConstant(1, HalfT));
11092 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11093 Regs64bit ? X86::RBX : X86::EBX,
11094 swapInL, cpInH.getValue(1));
11095 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11096 Regs64bit ? X86::RCX : X86::ECX,
11097 swapInH, swapInL.getValue(1));
11098 SDValue Ops[] = { swapInH.getValue(0),
11100 swapInH.getValue(1) };
11101 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11102 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11103 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11104 X86ISD::LCMPXCHG8_DAG;
11105 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11107 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11108 Regs64bit ? X86::RAX : X86::EAX,
11109 HalfT, Result.getValue(1));
11110 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11111 Regs64bit ? X86::RDX : X86::EDX,
11112 HalfT, cpOutL.getValue(2));
11113 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11114 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11115 Results.push_back(cpOutH.getValue(1));
11118 case ISD::ATOMIC_LOAD_ADD:
11119 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11121 case ISD::ATOMIC_LOAD_AND:
11122 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11124 case ISD::ATOMIC_LOAD_NAND:
11125 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11127 case ISD::ATOMIC_LOAD_OR:
11128 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11130 case ISD::ATOMIC_LOAD_SUB:
11131 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11133 case ISD::ATOMIC_LOAD_XOR:
11134 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11136 case ISD::ATOMIC_SWAP:
11137 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11139 case ISD::ATOMIC_LOAD:
11140 ReplaceATOMIC_LOAD(N, Results, DAG);
11144 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11146 default: return NULL;
11147 case X86ISD::BSF: return "X86ISD::BSF";
11148 case X86ISD::BSR: return "X86ISD::BSR";
11149 case X86ISD::SHLD: return "X86ISD::SHLD";
11150 case X86ISD::SHRD: return "X86ISD::SHRD";
11151 case X86ISD::FAND: return "X86ISD::FAND";
11152 case X86ISD::FOR: return "X86ISD::FOR";
11153 case X86ISD::FXOR: return "X86ISD::FXOR";
11154 case X86ISD::FSRL: return "X86ISD::FSRL";
11155 case X86ISD::FILD: return "X86ISD::FILD";
11156 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11157 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11158 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11159 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11160 case X86ISD::FLD: return "X86ISD::FLD";
11161 case X86ISD::FST: return "X86ISD::FST";
11162 case X86ISD::CALL: return "X86ISD::CALL";
11163 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11164 case X86ISD::BT: return "X86ISD::BT";
11165 case X86ISD::CMP: return "X86ISD::CMP";
11166 case X86ISD::COMI: return "X86ISD::COMI";
11167 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11168 case X86ISD::SETCC: return "X86ISD::SETCC";
11169 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11170 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11171 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11172 case X86ISD::CMOV: return "X86ISD::CMOV";
11173 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11174 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11175 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11176 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11177 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11178 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11179 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11180 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11181 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11182 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11183 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11184 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11185 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11186 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11187 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11188 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11189 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11190 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11191 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11192 case X86ISD::HADD: return "X86ISD::HADD";
11193 case X86ISD::HSUB: return "X86ISD::HSUB";
11194 case X86ISD::FHADD: return "X86ISD::FHADD";
11195 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11196 case X86ISD::FMAX: return "X86ISD::FMAX";
11197 case X86ISD::FMIN: return "X86ISD::FMIN";
11198 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11199 case X86ISD::FRCP: return "X86ISD::FRCP";
11200 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11201 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11202 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11203 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11204 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11205 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11206 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11207 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11208 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11209 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11210 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11211 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11212 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11213 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11214 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11215 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11216 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11217 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11218 case X86ISD::VSHL: return "X86ISD::VSHL";
11219 case X86ISD::VSRL: return "X86ISD::VSRL";
11220 case X86ISD::VSRA: return "X86ISD::VSRA";
11221 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11222 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11223 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11224 case X86ISD::CMPP: return "X86ISD::CMPP";
11225 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11226 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11227 case X86ISD::ADD: return "X86ISD::ADD";
11228 case X86ISD::SUB: return "X86ISD::SUB";
11229 case X86ISD::ADC: return "X86ISD::ADC";
11230 case X86ISD::SBB: return "X86ISD::SBB";
11231 case X86ISD::SMUL: return "X86ISD::SMUL";
11232 case X86ISD::UMUL: return "X86ISD::UMUL";
11233 case X86ISD::INC: return "X86ISD::INC";
11234 case X86ISD::DEC: return "X86ISD::DEC";
11235 case X86ISD::OR: return "X86ISD::OR";
11236 case X86ISD::XOR: return "X86ISD::XOR";
11237 case X86ISD::AND: return "X86ISD::AND";
11238 case X86ISD::ANDN: return "X86ISD::ANDN";
11239 case X86ISD::BLSI: return "X86ISD::BLSI";
11240 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11241 case X86ISD::BLSR: return "X86ISD::BLSR";
11242 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11243 case X86ISD::PTEST: return "X86ISD::PTEST";
11244 case X86ISD::TESTP: return "X86ISD::TESTP";
11245 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11246 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11247 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11248 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11249 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11250 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11251 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11252 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11253 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11254 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11255 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11256 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11257 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11258 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11259 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11260 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11261 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11262 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11263 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11264 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11265 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11266 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11267 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11268 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11269 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11270 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11271 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11272 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11273 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11274 case X86ISD::SAHF: return "X86ISD::SAHF";
11278 // isLegalAddressingMode - Return true if the addressing mode represented
11279 // by AM is legal for this target, for a load/store of the specified type.
11280 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11282 // X86 supports extremely general addressing modes.
11283 CodeModel::Model M = getTargetMachine().getCodeModel();
11284 Reloc::Model R = getTargetMachine().getRelocationModel();
11286 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11287 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11292 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11294 // If a reference to this global requires an extra load, we can't fold it.
11295 if (isGlobalStubReference(GVFlags))
11298 // If BaseGV requires a register for the PIC base, we cannot also have a
11299 // BaseReg specified.
11300 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11303 // If lower 4G is not available, then we must use rip-relative addressing.
11304 if ((M != CodeModel::Small || R != Reloc::Static) &&
11305 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11309 switch (AM.Scale) {
11315 // These scales always work.
11320 // These scales are formed with basereg+scalereg. Only accept if there is
11325 default: // Other stuff never works.
11333 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11334 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11336 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11337 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11338 if (NumBits1 <= NumBits2)
11343 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11344 if (!VT1.isInteger() || !VT2.isInteger())
11346 unsigned NumBits1 = VT1.getSizeInBits();
11347 unsigned NumBits2 = VT2.getSizeInBits();
11348 if (NumBits1 <= NumBits2)
11353 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11354 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11355 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11358 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11359 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11360 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11363 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11364 // i16 instructions are longer (0x66 prefix) and potentially slower.
11365 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11368 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11369 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11370 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11371 /// are assumed to be legal.
11373 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11375 // Very little shuffling can be done for 64-bit vectors right now.
11376 if (VT.getSizeInBits() == 64)
11379 // FIXME: pshufb, blends, shifts.
11380 return (VT.getVectorNumElements() == 2 ||
11381 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11382 isMOVLMask(M, VT) ||
11383 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11384 isPSHUFDMask(M, VT) ||
11385 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11386 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11387 isPALIGNRMask(M, VT, Subtarget) ||
11388 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11389 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11390 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11391 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11395 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11397 unsigned NumElts = VT.getVectorNumElements();
11398 // FIXME: This collection of masks seems suspect.
11401 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11402 return (isMOVLMask(Mask, VT) ||
11403 isCommutedMOVLMask(Mask, VT, true) ||
11404 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11405 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11410 //===----------------------------------------------------------------------===//
11411 // X86 Scheduler Hooks
11412 //===----------------------------------------------------------------------===//
11414 // private utility function
11415 MachineBasicBlock *
11416 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11417 MachineBasicBlock *MBB,
11424 const TargetRegisterClass *RC,
11425 bool Invert) const {
11426 // For the atomic bitwise operator, we generate
11429 // ld t1 = [bitinstr.addr]
11430 // op t2 = t1, [bitinstr.val]
11431 // not t3 = t2 (if Invert)
11433 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11435 // fallthrough -->nextMBB
11436 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11437 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11438 MachineFunction::iterator MBBIter = MBB;
11441 /// First build the CFG
11442 MachineFunction *F = MBB->getParent();
11443 MachineBasicBlock *thisMBB = MBB;
11444 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11445 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11446 F->insert(MBBIter, newMBB);
11447 F->insert(MBBIter, nextMBB);
11449 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11450 nextMBB->splice(nextMBB->begin(), thisMBB,
11451 llvm::next(MachineBasicBlock::iterator(bInstr)),
11453 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11455 // Update thisMBB to fall through to newMBB
11456 thisMBB->addSuccessor(newMBB);
11458 // newMBB jumps to itself and fall through to nextMBB
11459 newMBB->addSuccessor(nextMBB);
11460 newMBB->addSuccessor(newMBB);
11462 // Insert instructions into newMBB based on incoming instruction
11463 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11464 "unexpected number of operands");
11465 DebugLoc dl = bInstr->getDebugLoc();
11466 MachineOperand& destOper = bInstr->getOperand(0);
11467 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11468 int numArgs = bInstr->getNumOperands() - 1;
11469 for (int i=0; i < numArgs; ++i)
11470 argOpers[i] = &bInstr->getOperand(i+1);
11472 // x86 address has 4 operands: base, index, scale, and displacement
11473 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11474 int valArgIndx = lastAddrIndx + 1;
11476 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11477 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11478 for (int i=0; i <= lastAddrIndx; ++i)
11479 (*MIB).addOperand(*argOpers[i]);
11481 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11482 assert((argOpers[valArgIndx]->isReg() ||
11483 argOpers[valArgIndx]->isImm()) &&
11484 "invalid operand");
11485 if (argOpers[valArgIndx]->isReg())
11486 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11488 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11490 (*MIB).addOperand(*argOpers[valArgIndx]);
11492 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11494 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11499 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11502 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11503 for (int i=0; i <= lastAddrIndx; ++i)
11504 (*MIB).addOperand(*argOpers[i]);
11506 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11507 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11508 bInstr->memoperands_end());
11510 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11511 MIB.addReg(EAXreg);
11514 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11516 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11520 // private utility function: 64 bit atomics on 32 bit host.
11521 MachineBasicBlock *
11522 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11523 MachineBasicBlock *MBB,
11528 bool Invert) const {
11529 // For the atomic bitwise operator, we generate
11530 // thisMBB (instructions are in pairs, except cmpxchg8b)
11531 // ld t1,t2 = [bitinstr.addr]
11533 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11534 // op t5, t6 <- out1, out2, [bitinstr.val]
11535 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11536 // neg t7, t8 < t5, t6 (if Invert)
11537 // mov ECX, EBX <- t5, t6
11538 // mov EAX, EDX <- t1, t2
11539 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11540 // mov t3, t4 <- EAX, EDX
11542 // result in out1, out2
11543 // fallthrough -->nextMBB
11545 const TargetRegisterClass *RC = &X86::GR32RegClass;
11546 const unsigned LoadOpc = X86::MOV32rm;
11547 const unsigned NotOpc = X86::NOT32r;
11548 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11549 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11550 MachineFunction::iterator MBBIter = MBB;
11553 /// First build the CFG
11554 MachineFunction *F = MBB->getParent();
11555 MachineBasicBlock *thisMBB = MBB;
11556 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11557 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11558 F->insert(MBBIter, newMBB);
11559 F->insert(MBBIter, nextMBB);
11561 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11562 nextMBB->splice(nextMBB->begin(), thisMBB,
11563 llvm::next(MachineBasicBlock::iterator(bInstr)),
11565 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11567 // Update thisMBB to fall through to newMBB
11568 thisMBB->addSuccessor(newMBB);
11570 // newMBB jumps to itself and fall through to nextMBB
11571 newMBB->addSuccessor(nextMBB);
11572 newMBB->addSuccessor(newMBB);
11574 DebugLoc dl = bInstr->getDebugLoc();
11575 // Insert instructions into newMBB based on incoming instruction
11576 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11577 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11578 "unexpected number of operands");
11579 MachineOperand& dest1Oper = bInstr->getOperand(0);
11580 MachineOperand& dest2Oper = bInstr->getOperand(1);
11581 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11582 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11583 argOpers[i] = &bInstr->getOperand(i+2);
11585 // We use some of the operands multiple times, so conservatively just
11586 // clear any kill flags that might be present.
11587 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11588 argOpers[i]->setIsKill(false);
11591 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11592 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11594 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11595 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11596 for (int i=0; i <= lastAddrIndx; ++i)
11597 (*MIB).addOperand(*argOpers[i]);
11598 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11599 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11600 // add 4 to displacement.
11601 for (int i=0; i <= lastAddrIndx-2; ++i)
11602 (*MIB).addOperand(*argOpers[i]);
11603 MachineOperand newOp3 = *(argOpers[3]);
11604 if (newOp3.isImm())
11605 newOp3.setImm(newOp3.getImm()+4);
11607 newOp3.setOffset(newOp3.getOffset()+4);
11608 (*MIB).addOperand(newOp3);
11609 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11611 // t3/4 are defined later, at the bottom of the loop
11612 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11613 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11614 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11615 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11616 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11617 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11619 // The subsequent operations should be using the destination registers of
11620 // the PHI instructions.
11621 t1 = dest1Oper.getReg();
11622 t2 = dest2Oper.getReg();
11624 int valArgIndx = lastAddrIndx + 1;
11625 assert((argOpers[valArgIndx]->isReg() ||
11626 argOpers[valArgIndx]->isImm()) &&
11627 "invalid operand");
11628 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11629 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11630 if (argOpers[valArgIndx]->isReg())
11631 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11633 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11634 if (regOpcL != X86::MOV32rr)
11636 (*MIB).addOperand(*argOpers[valArgIndx]);
11637 assert(argOpers[valArgIndx + 1]->isReg() ==
11638 argOpers[valArgIndx]->isReg());
11639 assert(argOpers[valArgIndx + 1]->isImm() ==
11640 argOpers[valArgIndx]->isImm());
11641 if (argOpers[valArgIndx + 1]->isReg())
11642 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11644 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11645 if (regOpcH != X86::MOV32rr)
11647 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11651 t7 = F->getRegInfo().createVirtualRegister(RC);
11652 t8 = F->getRegInfo().createVirtualRegister(RC);
11653 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11654 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11660 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11662 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11665 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11667 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11670 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11671 for (int i=0; i <= lastAddrIndx; ++i)
11672 (*MIB).addOperand(*argOpers[i]);
11674 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11675 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11676 bInstr->memoperands_end());
11678 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11679 MIB.addReg(X86::EAX);
11680 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11681 MIB.addReg(X86::EDX);
11684 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11686 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11690 // private utility function
11691 MachineBasicBlock *
11692 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11693 MachineBasicBlock *MBB,
11694 unsigned cmovOpc) const {
11695 // For the atomic min/max operator, we generate
11698 // ld t1 = [min/max.addr]
11699 // mov t2 = [min/max.val]
11701 // cmov[cond] t2 = t1
11703 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11705 // fallthrough -->nextMBB
11707 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11708 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11709 MachineFunction::iterator MBBIter = MBB;
11712 /// First build the CFG
11713 MachineFunction *F = MBB->getParent();
11714 MachineBasicBlock *thisMBB = MBB;
11715 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11716 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11717 F->insert(MBBIter, newMBB);
11718 F->insert(MBBIter, nextMBB);
11720 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11721 nextMBB->splice(nextMBB->begin(), thisMBB,
11722 llvm::next(MachineBasicBlock::iterator(mInstr)),
11724 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11726 // Update thisMBB to fall through to newMBB
11727 thisMBB->addSuccessor(newMBB);
11729 // newMBB jumps to newMBB and fall through to nextMBB
11730 newMBB->addSuccessor(nextMBB);
11731 newMBB->addSuccessor(newMBB);
11733 DebugLoc dl = mInstr->getDebugLoc();
11734 // Insert instructions into newMBB based on incoming instruction
11735 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11736 "unexpected number of operands");
11737 MachineOperand& destOper = mInstr->getOperand(0);
11738 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11739 int numArgs = mInstr->getNumOperands() - 1;
11740 for (int i=0; i < numArgs; ++i)
11741 argOpers[i] = &mInstr->getOperand(i+1);
11743 // x86 address has 4 operands: base, index, scale, and displacement
11744 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11745 int valArgIndx = lastAddrIndx + 1;
11747 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11748 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11749 for (int i=0; i <= lastAddrIndx; ++i)
11750 (*MIB).addOperand(*argOpers[i]);
11752 // We only support register and immediate values
11753 assert((argOpers[valArgIndx]->isReg() ||
11754 argOpers[valArgIndx]->isImm()) &&
11755 "invalid operand");
11757 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11758 if (argOpers[valArgIndx]->isReg())
11759 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11761 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11762 (*MIB).addOperand(*argOpers[valArgIndx]);
11764 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11767 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11772 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11773 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11777 // Cmp and exchange if none has modified the memory location
11778 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11779 for (int i=0; i <= lastAddrIndx; ++i)
11780 (*MIB).addOperand(*argOpers[i]);
11782 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11783 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11784 mInstr->memoperands_end());
11786 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11787 MIB.addReg(X86::EAX);
11790 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11792 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11796 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11797 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11798 // in the .td file.
11799 MachineBasicBlock *
11800 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11801 unsigned numArgs, bool memArg) const {
11802 assert(Subtarget->hasSSE42() &&
11803 "Target must have SSE4.2 or AVX features enabled");
11805 DebugLoc dl = MI->getDebugLoc();
11806 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11808 if (!Subtarget->hasAVX()) {
11810 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11812 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11815 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11817 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11820 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11821 for (unsigned i = 0; i < numArgs; ++i) {
11822 MachineOperand &Op = MI->getOperand(i+1);
11823 if (!(Op.isReg() && Op.isImplicit()))
11824 MIB.addOperand(Op);
11826 BuildMI(*BB, MI, dl,
11827 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11828 MI->getOperand(0).getReg())
11829 .addReg(X86::XMM0);
11831 MI->eraseFromParent();
11835 MachineBasicBlock *
11836 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11837 DebugLoc dl = MI->getDebugLoc();
11838 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11840 // Address into RAX/EAX, other two args into ECX, EDX.
11841 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11842 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11843 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11844 for (int i = 0; i < X86::AddrNumOperands; ++i)
11845 MIB.addOperand(MI->getOperand(i));
11847 unsigned ValOps = X86::AddrNumOperands;
11848 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11849 .addReg(MI->getOperand(ValOps).getReg());
11850 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11851 .addReg(MI->getOperand(ValOps+1).getReg());
11853 // The instruction doesn't actually take any operands though.
11854 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11856 MI->eraseFromParent(); // The pseudo is gone now.
11860 MachineBasicBlock *
11861 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11862 DebugLoc dl = MI->getDebugLoc();
11863 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11865 // First arg in ECX, the second in EAX.
11866 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11867 .addReg(MI->getOperand(0).getReg());
11868 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11869 .addReg(MI->getOperand(1).getReg());
11871 // The instruction doesn't actually take any operands though.
11872 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11874 MI->eraseFromParent(); // The pseudo is gone now.
11878 MachineBasicBlock *
11879 X86TargetLowering::EmitVAARG64WithCustomInserter(
11881 MachineBasicBlock *MBB) const {
11882 // Emit va_arg instruction on X86-64.
11884 // Operands to this pseudo-instruction:
11885 // 0 ) Output : destination address (reg)
11886 // 1-5) Input : va_list address (addr, i64mem)
11887 // 6 ) ArgSize : Size (in bytes) of vararg type
11888 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11889 // 8 ) Align : Alignment of type
11890 // 9 ) EFLAGS (implicit-def)
11892 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11893 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11895 unsigned DestReg = MI->getOperand(0).getReg();
11896 MachineOperand &Base = MI->getOperand(1);
11897 MachineOperand &Scale = MI->getOperand(2);
11898 MachineOperand &Index = MI->getOperand(3);
11899 MachineOperand &Disp = MI->getOperand(4);
11900 MachineOperand &Segment = MI->getOperand(5);
11901 unsigned ArgSize = MI->getOperand(6).getImm();
11902 unsigned ArgMode = MI->getOperand(7).getImm();
11903 unsigned Align = MI->getOperand(8).getImm();
11905 // Memory Reference
11906 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11907 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11908 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11910 // Machine Information
11911 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11912 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11913 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11914 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11915 DebugLoc DL = MI->getDebugLoc();
11917 // struct va_list {
11920 // i64 overflow_area (address)
11921 // i64 reg_save_area (address)
11923 // sizeof(va_list) = 24
11924 // alignment(va_list) = 8
11926 unsigned TotalNumIntRegs = 6;
11927 unsigned TotalNumXMMRegs = 8;
11928 bool UseGPOffset = (ArgMode == 1);
11929 bool UseFPOffset = (ArgMode == 2);
11930 unsigned MaxOffset = TotalNumIntRegs * 8 +
11931 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11933 /* Align ArgSize to a multiple of 8 */
11934 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11935 bool NeedsAlign = (Align > 8);
11937 MachineBasicBlock *thisMBB = MBB;
11938 MachineBasicBlock *overflowMBB;
11939 MachineBasicBlock *offsetMBB;
11940 MachineBasicBlock *endMBB;
11942 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11943 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11944 unsigned OffsetReg = 0;
11946 if (!UseGPOffset && !UseFPOffset) {
11947 // If we only pull from the overflow region, we don't create a branch.
11948 // We don't need to alter control flow.
11949 OffsetDestReg = 0; // unused
11950 OverflowDestReg = DestReg;
11953 overflowMBB = thisMBB;
11956 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11957 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11958 // If not, pull from overflow_area. (branch to overflowMBB)
11963 // offsetMBB overflowMBB
11968 // Registers for the PHI in endMBB
11969 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11970 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11972 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11973 MachineFunction *MF = MBB->getParent();
11974 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11975 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11976 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11978 MachineFunction::iterator MBBIter = MBB;
11981 // Insert the new basic blocks
11982 MF->insert(MBBIter, offsetMBB);
11983 MF->insert(MBBIter, overflowMBB);
11984 MF->insert(MBBIter, endMBB);
11986 // Transfer the remainder of MBB and its successor edges to endMBB.
11987 endMBB->splice(endMBB->begin(), thisMBB,
11988 llvm::next(MachineBasicBlock::iterator(MI)),
11990 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11992 // Make offsetMBB and overflowMBB successors of thisMBB
11993 thisMBB->addSuccessor(offsetMBB);
11994 thisMBB->addSuccessor(overflowMBB);
11996 // endMBB is a successor of both offsetMBB and overflowMBB
11997 offsetMBB->addSuccessor(endMBB);
11998 overflowMBB->addSuccessor(endMBB);
12000 // Load the offset value into a register
12001 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12002 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
12006 .addDisp(Disp, UseFPOffset ? 4 : 0)
12007 .addOperand(Segment)
12008 .setMemRefs(MMOBegin, MMOEnd);
12010 // Check if there is enough room left to pull this argument.
12011 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
12013 .addImm(MaxOffset + 8 - ArgSizeA8);
12015 // Branch to "overflowMBB" if offset >= max
12016 // Fall through to "offsetMBB" otherwise
12017 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
12018 .addMBB(overflowMBB);
12021 // In offsetMBB, emit code to use the reg_save_area.
12023 assert(OffsetReg != 0);
12025 // Read the reg_save_area address.
12026 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12027 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12032 .addOperand(Segment)
12033 .setMemRefs(MMOBegin, MMOEnd);
12035 // Zero-extend the offset
12036 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12037 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12040 .addImm(X86::sub_32bit);
12042 // Add the offset to the reg_save_area to get the final address.
12043 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12044 .addReg(OffsetReg64)
12045 .addReg(RegSaveReg);
12047 // Compute the offset for the next argument
12048 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12049 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12051 .addImm(UseFPOffset ? 16 : 8);
12053 // Store it back into the va_list.
12054 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12058 .addDisp(Disp, UseFPOffset ? 4 : 0)
12059 .addOperand(Segment)
12060 .addReg(NextOffsetReg)
12061 .setMemRefs(MMOBegin, MMOEnd);
12064 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12069 // Emit code to use overflow area
12072 // Load the overflow_area address into a register.
12073 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12074 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12079 .addOperand(Segment)
12080 .setMemRefs(MMOBegin, MMOEnd);
12082 // If we need to align it, do so. Otherwise, just copy the address
12083 // to OverflowDestReg.
12085 // Align the overflow address
12086 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12087 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12089 // aligned_addr = (addr + (align-1)) & ~(align-1)
12090 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12091 .addReg(OverflowAddrReg)
12094 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12096 .addImm(~(uint64_t)(Align-1));
12098 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12099 .addReg(OverflowAddrReg);
12102 // Compute the next overflow address after this argument.
12103 // (the overflow address should be kept 8-byte aligned)
12104 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12105 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12106 .addReg(OverflowDestReg)
12107 .addImm(ArgSizeA8);
12109 // Store the new overflow address.
12110 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12115 .addOperand(Segment)
12116 .addReg(NextAddrReg)
12117 .setMemRefs(MMOBegin, MMOEnd);
12119 // If we branched, emit the PHI to the front of endMBB.
12121 BuildMI(*endMBB, endMBB->begin(), DL,
12122 TII->get(X86::PHI), DestReg)
12123 .addReg(OffsetDestReg).addMBB(offsetMBB)
12124 .addReg(OverflowDestReg).addMBB(overflowMBB);
12127 // Erase the pseudo instruction
12128 MI->eraseFromParent();
12133 MachineBasicBlock *
12134 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12136 MachineBasicBlock *MBB) const {
12137 // Emit code to save XMM registers to the stack. The ABI says that the
12138 // number of registers to save is given in %al, so it's theoretically
12139 // possible to do an indirect jump trick to avoid saving all of them,
12140 // however this code takes a simpler approach and just executes all
12141 // of the stores if %al is non-zero. It's less code, and it's probably
12142 // easier on the hardware branch predictor, and stores aren't all that
12143 // expensive anyway.
12145 // Create the new basic blocks. One block contains all the XMM stores,
12146 // and one block is the final destination regardless of whether any
12147 // stores were performed.
12148 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12149 MachineFunction *F = MBB->getParent();
12150 MachineFunction::iterator MBBIter = MBB;
12152 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12153 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12154 F->insert(MBBIter, XMMSaveMBB);
12155 F->insert(MBBIter, EndMBB);
12157 // Transfer the remainder of MBB and its successor edges to EndMBB.
12158 EndMBB->splice(EndMBB->begin(), MBB,
12159 llvm::next(MachineBasicBlock::iterator(MI)),
12161 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12163 // The original block will now fall through to the XMM save block.
12164 MBB->addSuccessor(XMMSaveMBB);
12165 // The XMMSaveMBB will fall through to the end block.
12166 XMMSaveMBB->addSuccessor(EndMBB);
12168 // Now add the instructions.
12169 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12170 DebugLoc DL = MI->getDebugLoc();
12172 unsigned CountReg = MI->getOperand(0).getReg();
12173 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12174 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12176 if (!Subtarget->isTargetWin64()) {
12177 // If %al is 0, branch around the XMM save block.
12178 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12179 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12180 MBB->addSuccessor(EndMBB);
12183 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12184 // In the XMM save block, save all the XMM argument registers.
12185 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12186 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12187 MachineMemOperand *MMO =
12188 F->getMachineMemOperand(
12189 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12190 MachineMemOperand::MOStore,
12191 /*Size=*/16, /*Align=*/16);
12192 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12193 .addFrameIndex(RegSaveFrameIndex)
12194 .addImm(/*Scale=*/1)
12195 .addReg(/*IndexReg=*/0)
12196 .addImm(/*Disp=*/Offset)
12197 .addReg(/*Segment=*/0)
12198 .addReg(MI->getOperand(i).getReg())
12199 .addMemOperand(MMO);
12202 MI->eraseFromParent(); // The pseudo instruction is gone now.
12207 // The EFLAGS operand of SelectItr might be missing a kill marker
12208 // because there were multiple uses of EFLAGS, and ISel didn't know
12209 // which to mark. Figure out whether SelectItr should have had a
12210 // kill marker, and set it if it should. Returns the correct kill
12212 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12213 MachineBasicBlock* BB,
12214 const TargetRegisterInfo* TRI) {
12215 // Scan forward through BB for a use/def of EFLAGS.
12216 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12217 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12218 const MachineInstr& mi = *miI;
12219 if (mi.readsRegister(X86::EFLAGS))
12221 if (mi.definesRegister(X86::EFLAGS))
12222 break; // Should have kill-flag - update below.
12225 // If we hit the end of the block, check whether EFLAGS is live into a
12227 if (miI == BB->end()) {
12228 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12229 sEnd = BB->succ_end();
12230 sItr != sEnd; ++sItr) {
12231 MachineBasicBlock* succ = *sItr;
12232 if (succ->isLiveIn(X86::EFLAGS))
12237 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12238 // out. SelectMI should have a kill flag on EFLAGS.
12239 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12243 MachineBasicBlock *
12244 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12245 MachineBasicBlock *BB) const {
12246 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12247 DebugLoc DL = MI->getDebugLoc();
12249 // To "insert" a SELECT_CC instruction, we actually have to insert the
12250 // diamond control-flow pattern. The incoming instruction knows the
12251 // destination vreg to set, the condition code register to branch on, the
12252 // true/false values to select between, and a branch opcode to use.
12253 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12254 MachineFunction::iterator It = BB;
12260 // cmpTY ccX, r1, r2
12262 // fallthrough --> copy0MBB
12263 MachineBasicBlock *thisMBB = BB;
12264 MachineFunction *F = BB->getParent();
12265 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12266 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12267 F->insert(It, copy0MBB);
12268 F->insert(It, sinkMBB);
12270 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12271 // live into the sink and copy blocks.
12272 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12273 if (!MI->killsRegister(X86::EFLAGS) &&
12274 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12275 copy0MBB->addLiveIn(X86::EFLAGS);
12276 sinkMBB->addLiveIn(X86::EFLAGS);
12279 // Transfer the remainder of BB and its successor edges to sinkMBB.
12280 sinkMBB->splice(sinkMBB->begin(), BB,
12281 llvm::next(MachineBasicBlock::iterator(MI)),
12283 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12285 // Add the true and fallthrough blocks as its successors.
12286 BB->addSuccessor(copy0MBB);
12287 BB->addSuccessor(sinkMBB);
12289 // Create the conditional branch instruction.
12291 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12292 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12295 // %FalseValue = ...
12296 // # fallthrough to sinkMBB
12297 copy0MBB->addSuccessor(sinkMBB);
12300 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12302 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12303 TII->get(X86::PHI), MI->getOperand(0).getReg())
12304 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12305 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12307 MI->eraseFromParent(); // The pseudo instruction is gone now.
12311 MachineBasicBlock *
12312 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12313 bool Is64Bit) const {
12314 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12315 DebugLoc DL = MI->getDebugLoc();
12316 MachineFunction *MF = BB->getParent();
12317 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12319 assert(getTargetMachine().Options.EnableSegmentedStacks);
12321 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12322 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12325 // ... [Till the alloca]
12326 // If stacklet is not large enough, jump to mallocMBB
12329 // Allocate by subtracting from RSP
12330 // Jump to continueMBB
12333 // Allocate by call to runtime
12337 // [rest of original BB]
12340 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12341 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12342 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12344 MachineRegisterInfo &MRI = MF->getRegInfo();
12345 const TargetRegisterClass *AddrRegClass =
12346 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12348 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12349 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12350 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12351 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12352 sizeVReg = MI->getOperand(1).getReg(),
12353 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12355 MachineFunction::iterator MBBIter = BB;
12358 MF->insert(MBBIter, bumpMBB);
12359 MF->insert(MBBIter, mallocMBB);
12360 MF->insert(MBBIter, continueMBB);
12362 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12363 (MachineBasicBlock::iterator(MI)), BB->end());
12364 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12366 // Add code to the main basic block to check if the stack limit has been hit,
12367 // and if so, jump to mallocMBB otherwise to bumpMBB.
12368 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12369 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12370 .addReg(tmpSPVReg).addReg(sizeVReg);
12371 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12372 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12373 .addReg(SPLimitVReg);
12374 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12376 // bumpMBB simply decreases the stack pointer, since we know the current
12377 // stacklet has enough space.
12378 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12379 .addReg(SPLimitVReg);
12380 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12381 .addReg(SPLimitVReg);
12382 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12384 // Calls into a routine in libgcc to allocate more space from the heap.
12385 const uint32_t *RegMask =
12386 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12388 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12390 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12391 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12392 .addRegMask(RegMask)
12393 .addReg(X86::RAX, RegState::ImplicitDefine);
12395 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12397 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12398 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12399 .addExternalSymbol("__morestack_allocate_stack_space")
12400 .addRegMask(RegMask)
12401 .addReg(X86::EAX, RegState::ImplicitDefine);
12405 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12408 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12409 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12410 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12412 // Set up the CFG correctly.
12413 BB->addSuccessor(bumpMBB);
12414 BB->addSuccessor(mallocMBB);
12415 mallocMBB->addSuccessor(continueMBB);
12416 bumpMBB->addSuccessor(continueMBB);
12418 // Take care of the PHI nodes.
12419 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12420 MI->getOperand(0).getReg())
12421 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12422 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12424 // Delete the original pseudo instruction.
12425 MI->eraseFromParent();
12428 return continueMBB;
12431 MachineBasicBlock *
12432 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12433 MachineBasicBlock *BB) const {
12434 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12435 DebugLoc DL = MI->getDebugLoc();
12437 assert(!Subtarget->isTargetEnvMacho());
12439 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12440 // non-trivial part is impdef of ESP.
12442 if (Subtarget->isTargetWin64()) {
12443 if (Subtarget->isTargetCygMing()) {
12444 // ___chkstk(Mingw64):
12445 // Clobbers R10, R11, RAX and EFLAGS.
12447 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12448 .addExternalSymbol("___chkstk")
12449 .addReg(X86::RAX, RegState::Implicit)
12450 .addReg(X86::RSP, RegState::Implicit)
12451 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12452 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12453 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12455 // __chkstk(MSVCRT): does not update stack pointer.
12456 // Clobbers R10, R11 and EFLAGS.
12457 // FIXME: RAX(allocated size) might be reused and not killed.
12458 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12459 .addExternalSymbol("__chkstk")
12460 .addReg(X86::RAX, RegState::Implicit)
12461 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12462 // RAX has the offset to subtracted from RSP.
12463 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12468 const char *StackProbeSymbol =
12469 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12471 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12472 .addExternalSymbol(StackProbeSymbol)
12473 .addReg(X86::EAX, RegState::Implicit)
12474 .addReg(X86::ESP, RegState::Implicit)
12475 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12476 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12477 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12480 MI->eraseFromParent(); // The pseudo instruction is gone now.
12484 MachineBasicBlock *
12485 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12486 MachineBasicBlock *BB) const {
12487 // This is pretty easy. We're taking the value that we received from
12488 // our load from the relocation, sticking it in either RDI (x86-64)
12489 // or EAX and doing an indirect call. The return value will then
12490 // be in the normal return register.
12491 const X86InstrInfo *TII
12492 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12493 DebugLoc DL = MI->getDebugLoc();
12494 MachineFunction *F = BB->getParent();
12496 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12497 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12499 // Get a register mask for the lowered call.
12500 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12501 // proper register mask.
12502 const uint32_t *RegMask =
12503 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12504 if (Subtarget->is64Bit()) {
12505 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12506 TII->get(X86::MOV64rm), X86::RDI)
12508 .addImm(0).addReg(0)
12509 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12510 MI->getOperand(3).getTargetFlags())
12512 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12513 addDirectMem(MIB, X86::RDI);
12514 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12515 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12516 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12517 TII->get(X86::MOV32rm), X86::EAX)
12519 .addImm(0).addReg(0)
12520 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12521 MI->getOperand(3).getTargetFlags())
12523 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12524 addDirectMem(MIB, X86::EAX);
12525 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12527 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12528 TII->get(X86::MOV32rm), X86::EAX)
12529 .addReg(TII->getGlobalBaseReg(F))
12530 .addImm(0).addReg(0)
12531 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12532 MI->getOperand(3).getTargetFlags())
12534 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12535 addDirectMem(MIB, X86::EAX);
12536 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12539 MI->eraseFromParent(); // The pseudo instruction is gone now.
12543 MachineBasicBlock *
12544 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12545 MachineBasicBlock *BB) const {
12546 switch (MI->getOpcode()) {
12547 default: llvm_unreachable("Unexpected instr type to insert");
12548 case X86::TAILJMPd64:
12549 case X86::TAILJMPr64:
12550 case X86::TAILJMPm64:
12551 llvm_unreachable("TAILJMP64 would not be touched here.");
12552 case X86::TCRETURNdi64:
12553 case X86::TCRETURNri64:
12554 case X86::TCRETURNmi64:
12556 case X86::WIN_ALLOCA:
12557 return EmitLoweredWinAlloca(MI, BB);
12558 case X86::SEG_ALLOCA_32:
12559 return EmitLoweredSegAlloca(MI, BB, false);
12560 case X86::SEG_ALLOCA_64:
12561 return EmitLoweredSegAlloca(MI, BB, true);
12562 case X86::TLSCall_32:
12563 case X86::TLSCall_64:
12564 return EmitLoweredTLSCall(MI, BB);
12565 case X86::CMOV_GR8:
12566 case X86::CMOV_FR32:
12567 case X86::CMOV_FR64:
12568 case X86::CMOV_V4F32:
12569 case X86::CMOV_V2F64:
12570 case X86::CMOV_V2I64:
12571 case X86::CMOV_V8F32:
12572 case X86::CMOV_V4F64:
12573 case X86::CMOV_V4I64:
12574 case X86::CMOV_GR16:
12575 case X86::CMOV_GR32:
12576 case X86::CMOV_RFP32:
12577 case X86::CMOV_RFP64:
12578 case X86::CMOV_RFP80:
12579 return EmitLoweredSelect(MI, BB);
12581 case X86::FP32_TO_INT16_IN_MEM:
12582 case X86::FP32_TO_INT32_IN_MEM:
12583 case X86::FP32_TO_INT64_IN_MEM:
12584 case X86::FP64_TO_INT16_IN_MEM:
12585 case X86::FP64_TO_INT32_IN_MEM:
12586 case X86::FP64_TO_INT64_IN_MEM:
12587 case X86::FP80_TO_INT16_IN_MEM:
12588 case X86::FP80_TO_INT32_IN_MEM:
12589 case X86::FP80_TO_INT64_IN_MEM: {
12590 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12591 DebugLoc DL = MI->getDebugLoc();
12593 // Change the floating point control register to use "round towards zero"
12594 // mode when truncating to an integer value.
12595 MachineFunction *F = BB->getParent();
12596 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12597 addFrameReference(BuildMI(*BB, MI, DL,
12598 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12600 // Load the old value of the high byte of the control word...
12602 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12603 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12606 // Set the high part to be round to zero...
12607 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12610 // Reload the modified control word now...
12611 addFrameReference(BuildMI(*BB, MI, DL,
12612 TII->get(X86::FLDCW16m)), CWFrameIdx);
12614 // Restore the memory image of control word to original value
12615 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12618 // Get the X86 opcode to use.
12620 switch (MI->getOpcode()) {
12621 default: llvm_unreachable("illegal opcode!");
12622 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12623 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12624 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12625 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12626 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12627 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12628 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12629 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12630 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12634 MachineOperand &Op = MI->getOperand(0);
12636 AM.BaseType = X86AddressMode::RegBase;
12637 AM.Base.Reg = Op.getReg();
12639 AM.BaseType = X86AddressMode::FrameIndexBase;
12640 AM.Base.FrameIndex = Op.getIndex();
12642 Op = MI->getOperand(1);
12644 AM.Scale = Op.getImm();
12645 Op = MI->getOperand(2);
12647 AM.IndexReg = Op.getImm();
12648 Op = MI->getOperand(3);
12649 if (Op.isGlobal()) {
12650 AM.GV = Op.getGlobal();
12652 AM.Disp = Op.getImm();
12654 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12655 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12657 // Reload the original control word now.
12658 addFrameReference(BuildMI(*BB, MI, DL,
12659 TII->get(X86::FLDCW16m)), CWFrameIdx);
12661 MI->eraseFromParent(); // The pseudo instruction is gone now.
12664 // String/text processing lowering.
12665 case X86::PCMPISTRM128REG:
12666 case X86::VPCMPISTRM128REG:
12667 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12668 case X86::PCMPISTRM128MEM:
12669 case X86::VPCMPISTRM128MEM:
12670 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12671 case X86::PCMPESTRM128REG:
12672 case X86::VPCMPESTRM128REG:
12673 return EmitPCMP(MI, BB, 5, false /* in mem */);
12674 case X86::PCMPESTRM128MEM:
12675 case X86::VPCMPESTRM128MEM:
12676 return EmitPCMP(MI, BB, 5, true /* in mem */);
12678 // Thread synchronization.
12680 return EmitMonitor(MI, BB);
12682 return EmitMwait(MI, BB);
12684 // Atomic Lowering.
12685 case X86::ATOMAND32:
12686 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12687 X86::AND32ri, X86::MOV32rm,
12689 X86::NOT32r, X86::EAX,
12690 &X86::GR32RegClass);
12691 case X86::ATOMOR32:
12692 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12693 X86::OR32ri, X86::MOV32rm,
12695 X86::NOT32r, X86::EAX,
12696 &X86::GR32RegClass);
12697 case X86::ATOMXOR32:
12698 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12699 X86::XOR32ri, X86::MOV32rm,
12701 X86::NOT32r, X86::EAX,
12702 &X86::GR32RegClass);
12703 case X86::ATOMNAND32:
12704 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12705 X86::AND32ri, X86::MOV32rm,
12707 X86::NOT32r, X86::EAX,
12708 &X86::GR32RegClass, true);
12709 case X86::ATOMMIN32:
12710 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12711 case X86::ATOMMAX32:
12712 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12713 case X86::ATOMUMIN32:
12714 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12715 case X86::ATOMUMAX32:
12716 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12718 case X86::ATOMAND16:
12719 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12720 X86::AND16ri, X86::MOV16rm,
12722 X86::NOT16r, X86::AX,
12723 &X86::GR16RegClass);
12724 case X86::ATOMOR16:
12725 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12726 X86::OR16ri, X86::MOV16rm,
12728 X86::NOT16r, X86::AX,
12729 &X86::GR16RegClass);
12730 case X86::ATOMXOR16:
12731 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12732 X86::XOR16ri, X86::MOV16rm,
12734 X86::NOT16r, X86::AX,
12735 &X86::GR16RegClass);
12736 case X86::ATOMNAND16:
12737 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12738 X86::AND16ri, X86::MOV16rm,
12740 X86::NOT16r, X86::AX,
12741 &X86::GR16RegClass, true);
12742 case X86::ATOMMIN16:
12743 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12744 case X86::ATOMMAX16:
12745 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12746 case X86::ATOMUMIN16:
12747 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12748 case X86::ATOMUMAX16:
12749 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12751 case X86::ATOMAND8:
12752 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12753 X86::AND8ri, X86::MOV8rm,
12755 X86::NOT8r, X86::AL,
12756 &X86::GR8RegClass);
12758 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12759 X86::OR8ri, X86::MOV8rm,
12761 X86::NOT8r, X86::AL,
12762 &X86::GR8RegClass);
12763 case X86::ATOMXOR8:
12764 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12765 X86::XOR8ri, X86::MOV8rm,
12767 X86::NOT8r, X86::AL,
12768 &X86::GR8RegClass);
12769 case X86::ATOMNAND8:
12770 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12771 X86::AND8ri, X86::MOV8rm,
12773 X86::NOT8r, X86::AL,
12774 &X86::GR8RegClass, true);
12775 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12776 // This group is for 64-bit host.
12777 case X86::ATOMAND64:
12778 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12779 X86::AND64ri32, X86::MOV64rm,
12781 X86::NOT64r, X86::RAX,
12782 &X86::GR64RegClass);
12783 case X86::ATOMOR64:
12784 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12785 X86::OR64ri32, X86::MOV64rm,
12787 X86::NOT64r, X86::RAX,
12788 &X86::GR64RegClass);
12789 case X86::ATOMXOR64:
12790 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12791 X86::XOR64ri32, X86::MOV64rm,
12793 X86::NOT64r, X86::RAX,
12794 &X86::GR64RegClass);
12795 case X86::ATOMNAND64:
12796 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12797 X86::AND64ri32, X86::MOV64rm,
12799 X86::NOT64r, X86::RAX,
12800 &X86::GR64RegClass, true);
12801 case X86::ATOMMIN64:
12802 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12803 case X86::ATOMMAX64:
12804 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12805 case X86::ATOMUMIN64:
12806 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12807 case X86::ATOMUMAX64:
12808 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12810 // This group does 64-bit operations on a 32-bit host.
12811 case X86::ATOMAND6432:
12812 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12813 X86::AND32rr, X86::AND32rr,
12814 X86::AND32ri, X86::AND32ri,
12816 case X86::ATOMOR6432:
12817 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12818 X86::OR32rr, X86::OR32rr,
12819 X86::OR32ri, X86::OR32ri,
12821 case X86::ATOMXOR6432:
12822 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12823 X86::XOR32rr, X86::XOR32rr,
12824 X86::XOR32ri, X86::XOR32ri,
12826 case X86::ATOMNAND6432:
12827 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12828 X86::AND32rr, X86::AND32rr,
12829 X86::AND32ri, X86::AND32ri,
12831 case X86::ATOMADD6432:
12832 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12833 X86::ADD32rr, X86::ADC32rr,
12834 X86::ADD32ri, X86::ADC32ri,
12836 case X86::ATOMSUB6432:
12837 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12838 X86::SUB32rr, X86::SBB32rr,
12839 X86::SUB32ri, X86::SBB32ri,
12841 case X86::ATOMSWAP6432:
12842 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12843 X86::MOV32rr, X86::MOV32rr,
12844 X86::MOV32ri, X86::MOV32ri,
12846 case X86::VASTART_SAVE_XMM_REGS:
12847 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12849 case X86::VAARG_64:
12850 return EmitVAARG64WithCustomInserter(MI, BB);
12854 //===----------------------------------------------------------------------===//
12855 // X86 Optimization Hooks
12856 //===----------------------------------------------------------------------===//
12858 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12861 const SelectionDAG &DAG,
12862 unsigned Depth) const {
12863 unsigned BitWidth = KnownZero.getBitWidth();
12864 unsigned Opc = Op.getOpcode();
12865 assert((Opc >= ISD::BUILTIN_OP_END ||
12866 Opc == ISD::INTRINSIC_WO_CHAIN ||
12867 Opc == ISD::INTRINSIC_W_CHAIN ||
12868 Opc == ISD::INTRINSIC_VOID) &&
12869 "Should use MaskedValueIsZero if you don't know whether Op"
12870 " is a target node!");
12872 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12886 // These nodes' second result is a boolean.
12887 if (Op.getResNo() == 0)
12890 case X86ISD::SETCC:
12891 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12893 case ISD::INTRINSIC_WO_CHAIN: {
12894 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12895 unsigned NumLoBits = 0;
12898 case Intrinsic::x86_sse_movmsk_ps:
12899 case Intrinsic::x86_avx_movmsk_ps_256:
12900 case Intrinsic::x86_sse2_movmsk_pd:
12901 case Intrinsic::x86_avx_movmsk_pd_256:
12902 case Intrinsic::x86_mmx_pmovmskb:
12903 case Intrinsic::x86_sse2_pmovmskb_128:
12904 case Intrinsic::x86_avx2_pmovmskb: {
12905 // High bits of movmskp{s|d}, pmovmskb are known zero.
12907 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12908 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12909 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12910 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12911 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12912 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12913 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12914 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12916 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12925 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12926 unsigned Depth) const {
12927 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12928 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12929 return Op.getValueType().getScalarType().getSizeInBits();
12935 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12936 /// node is a GlobalAddress + offset.
12937 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12938 const GlobalValue* &GA,
12939 int64_t &Offset) const {
12940 if (N->getOpcode() == X86ISD::Wrapper) {
12941 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12942 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12943 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12947 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12950 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12951 /// same as extracting the high 128-bit part of 256-bit vector and then
12952 /// inserting the result into the low part of a new 256-bit vector
12953 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12954 EVT VT = SVOp->getValueType(0);
12955 unsigned NumElems = VT.getVectorNumElements();
12957 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12958 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
12959 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12960 SVOp->getMaskElt(j) >= 0)
12966 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12967 /// same as extracting the low 128-bit part of 256-bit vector and then
12968 /// inserting the result into the high part of a new 256-bit vector
12969 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12970 EVT VT = SVOp->getValueType(0);
12971 unsigned NumElems = VT.getVectorNumElements();
12973 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12974 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
12975 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12976 SVOp->getMaskElt(j) >= 0)
12982 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12983 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12984 TargetLowering::DAGCombinerInfo &DCI,
12985 const X86Subtarget* Subtarget) {
12986 DebugLoc dl = N->getDebugLoc();
12987 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12988 SDValue V1 = SVOp->getOperand(0);
12989 SDValue V2 = SVOp->getOperand(1);
12990 EVT VT = SVOp->getValueType(0);
12991 unsigned NumElems = VT.getVectorNumElements();
12993 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12994 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12998 // V UNDEF BUILD_VECTOR UNDEF
13000 // CONCAT_VECTOR CONCAT_VECTOR
13003 // RESULT: V + zero extended
13005 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13006 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
13007 V1.getOperand(1).getOpcode() != ISD::UNDEF)
13010 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
13013 // To match the shuffle mask, the first half of the mask should
13014 // be exactly the first vector, and all the rest a splat with the
13015 // first element of the second one.
13016 for (unsigned i = 0; i != NumElems/2; ++i)
13017 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
13018 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
13021 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
13022 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
13023 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
13024 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13026 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13028 Ld->getPointerInfo(),
13029 Ld->getAlignment(),
13030 false/*isVolatile*/, true/*ReadMem*/,
13031 false/*WriteMem*/);
13032 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13035 // Emit a zeroed vector and insert the desired subvector on its
13037 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13038 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13039 return DCI.CombineTo(N, InsV);
13042 //===--------------------------------------------------------------------===//
13043 // Combine some shuffles into subvector extracts and inserts:
13046 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13047 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13048 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13049 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13050 return DCI.CombineTo(N, InsV);
13053 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13054 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13055 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13056 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13057 return DCI.CombineTo(N, InsV);
13063 /// PerformShuffleCombine - Performs several different shuffle combines.
13064 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13065 TargetLowering::DAGCombinerInfo &DCI,
13066 const X86Subtarget *Subtarget) {
13067 DebugLoc dl = N->getDebugLoc();
13068 EVT VT = N->getValueType(0);
13070 // Don't create instructions with illegal types after legalize types has run.
13071 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13072 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13075 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13076 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
13077 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13078 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13080 // Only handle 128 wide vector from here on.
13081 if (VT.getSizeInBits() != 128)
13084 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13085 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13086 // consecutive, non-overlapping, and in the right order.
13087 SmallVector<SDValue, 16> Elts;
13088 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13089 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13091 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13095 /// DCI, PerformTruncateCombine - Converts truncate operation to
13096 /// a sequence of vector shuffle operations.
13097 /// It is possible when we truncate 256-bit vector to 128-bit vector
13099 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13100 DAGCombinerInfo &DCI) const {
13101 if (!DCI.isBeforeLegalizeOps())
13104 if (!Subtarget->hasAVX())
13107 EVT VT = N->getValueType(0);
13108 SDValue Op = N->getOperand(0);
13109 EVT OpVT = Op.getValueType();
13110 DebugLoc dl = N->getDebugLoc();
13112 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13114 if (Subtarget->hasAVX2()) {
13115 // AVX2: v4i64 -> v4i32
13118 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13120 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13121 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13124 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13125 DAG.getIntPtrConstant(0));
13128 // AVX: v4i64 -> v4i32
13129 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13130 DAG.getIntPtrConstant(0));
13132 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13133 DAG.getIntPtrConstant(2));
13135 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13136 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13139 static const int ShufMask1[] = {0, 2, 0, 0};
13141 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13142 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13145 static const int ShufMask2[] = {0, 1, 4, 5};
13147 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13150 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13152 if (Subtarget->hasAVX2()) {
13153 // AVX2: v8i32 -> v8i16
13155 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13158 SmallVector<SDValue,32> pshufbMask;
13159 for (unsigned i = 0; i < 2; ++i) {
13160 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13161 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13162 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13163 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13164 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13165 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13166 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13167 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13168 for (unsigned j = 0; j < 8; ++j)
13169 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13171 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13172 &pshufbMask[0], 32);
13173 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13175 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13177 static const int ShufMask[] = {0, 2, -1, -1};
13178 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13181 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13182 DAG.getIntPtrConstant(0));
13184 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13187 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13188 DAG.getIntPtrConstant(0));
13190 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13191 DAG.getIntPtrConstant(4));
13193 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13194 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13197 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13198 -1, -1, -1, -1, -1, -1, -1, -1};
13200 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13202 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13205 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13206 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13209 static const int ShufMask2[] = {0, 1, 4, 5};
13211 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13212 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13218 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13219 /// specific shuffle of a load can be folded into a single element load.
13220 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13221 /// shuffles have been customed lowered so we need to handle those here.
13222 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13223 TargetLowering::DAGCombinerInfo &DCI) {
13224 if (DCI.isBeforeLegalizeOps())
13227 SDValue InVec = N->getOperand(0);
13228 SDValue EltNo = N->getOperand(1);
13230 if (!isa<ConstantSDNode>(EltNo))
13233 EVT VT = InVec.getValueType();
13235 bool HasShuffleIntoBitcast = false;
13236 if (InVec.getOpcode() == ISD::BITCAST) {
13237 // Don't duplicate a load with other uses.
13238 if (!InVec.hasOneUse())
13240 EVT BCVT = InVec.getOperand(0).getValueType();
13241 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13243 InVec = InVec.getOperand(0);
13244 HasShuffleIntoBitcast = true;
13247 if (!isTargetShuffle(InVec.getOpcode()))
13250 // Don't duplicate a load with other uses.
13251 if (!InVec.hasOneUse())
13254 SmallVector<int, 16> ShuffleMask;
13256 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
13259 // Select the input vector, guarding against out of range extract vector.
13260 unsigned NumElems = VT.getVectorNumElements();
13261 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13262 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13263 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13264 : InVec.getOperand(1);
13266 // If inputs to shuffle are the same for both ops, then allow 2 uses
13267 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13269 if (LdNode.getOpcode() == ISD::BITCAST) {
13270 // Don't duplicate a load with other uses.
13271 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13274 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13275 LdNode = LdNode.getOperand(0);
13278 if (!ISD::isNormalLoad(LdNode.getNode()))
13281 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13283 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13286 if (HasShuffleIntoBitcast) {
13287 // If there's a bitcast before the shuffle, check if the load type and
13288 // alignment is valid.
13289 unsigned Align = LN0->getAlignment();
13290 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13291 unsigned NewAlign = TLI.getTargetData()->
13292 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13294 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13298 // All checks match so transform back to vector_shuffle so that DAG combiner
13299 // can finish the job
13300 DebugLoc dl = N->getDebugLoc();
13302 // Create shuffle node taking into account the case that its a unary shuffle
13303 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13304 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13305 InVec.getOperand(0), Shuffle,
13307 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13308 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13312 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13313 /// generation and convert it from being a bunch of shuffles and extracts
13314 /// to a simple store and scalar loads to extract the elements.
13315 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13316 TargetLowering::DAGCombinerInfo &DCI) {
13317 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13318 if (NewOp.getNode())
13321 SDValue InputVector = N->getOperand(0);
13323 // Only operate on vectors of 4 elements, where the alternative shuffling
13324 // gets to be more expensive.
13325 if (InputVector.getValueType() != MVT::v4i32)
13328 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13329 // single use which is a sign-extend or zero-extend, and all elements are
13331 SmallVector<SDNode *, 4> Uses;
13332 unsigned ExtractedElements = 0;
13333 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13334 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13335 if (UI.getUse().getResNo() != InputVector.getResNo())
13338 SDNode *Extract = *UI;
13339 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13342 if (Extract->getValueType(0) != MVT::i32)
13344 if (!Extract->hasOneUse())
13346 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13347 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13349 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13352 // Record which element was extracted.
13353 ExtractedElements |=
13354 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13356 Uses.push_back(Extract);
13359 // If not all the elements were used, this may not be worthwhile.
13360 if (ExtractedElements != 15)
13363 // Ok, we've now decided to do the transformation.
13364 DebugLoc dl = InputVector.getDebugLoc();
13366 // Store the value to a temporary stack slot.
13367 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13368 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13369 MachinePointerInfo(), false, false, 0);
13371 // Replace each use (extract) with a load of the appropriate element.
13372 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13373 UE = Uses.end(); UI != UE; ++UI) {
13374 SDNode *Extract = *UI;
13376 // cOMpute the element's address.
13377 SDValue Idx = Extract->getOperand(1);
13379 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13380 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13381 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13382 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13384 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13385 StackPtr, OffsetVal);
13387 // Load the scalar.
13388 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13389 ScalarAddr, MachinePointerInfo(),
13390 false, false, false, 0);
13392 // Replace the exact with the load.
13393 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13396 // The replacement was made in place; don't return anything.
13400 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13402 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13403 TargetLowering::DAGCombinerInfo &DCI,
13404 const X86Subtarget *Subtarget) {
13407 DebugLoc DL = N->getDebugLoc();
13408 SDValue Cond = N->getOperand(0);
13409 // Get the LHS/RHS of the select.
13410 SDValue LHS = N->getOperand(1);
13411 SDValue RHS = N->getOperand(2);
13412 EVT VT = LHS.getValueType();
13414 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13415 // instructions match the semantics of the common C idiom x<y?x:y but not
13416 // x<=y?x:y, because of how they handle negative zero (which can be
13417 // ignored in unsafe-math mode).
13418 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13419 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13420 (Subtarget->hasSSE2() ||
13421 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13422 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13424 unsigned Opcode = 0;
13425 // Check for x CC y ? x : y.
13426 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13427 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13431 // Converting this to a min would handle NaNs incorrectly, and swapping
13432 // the operands would cause it to handle comparisons between positive
13433 // and negative zero incorrectly.
13434 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13435 if (!DAG.getTarget().Options.UnsafeFPMath &&
13436 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13438 std::swap(LHS, RHS);
13440 Opcode = X86ISD::FMIN;
13443 // Converting this to a min would handle comparisons between positive
13444 // and negative zero incorrectly.
13445 if (!DAG.getTarget().Options.UnsafeFPMath &&
13446 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13448 Opcode = X86ISD::FMIN;
13451 // Converting this to a min would handle both negative zeros and NaNs
13452 // incorrectly, but we can swap the operands to fix both.
13453 std::swap(LHS, RHS);
13457 Opcode = X86ISD::FMIN;
13461 // Converting this to a max would handle comparisons between positive
13462 // and negative zero incorrectly.
13463 if (!DAG.getTarget().Options.UnsafeFPMath &&
13464 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13466 Opcode = X86ISD::FMAX;
13469 // Converting this to a max would handle NaNs incorrectly, and swapping
13470 // the operands would cause it to handle comparisons between positive
13471 // and negative zero incorrectly.
13472 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13473 if (!DAG.getTarget().Options.UnsafeFPMath &&
13474 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13476 std::swap(LHS, RHS);
13478 Opcode = X86ISD::FMAX;
13481 // Converting this to a max would handle both negative zeros and NaNs
13482 // incorrectly, but we can swap the operands to fix both.
13483 std::swap(LHS, RHS);
13487 Opcode = X86ISD::FMAX;
13490 // Check for x CC y ? y : x -- a min/max with reversed arms.
13491 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13492 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13496 // Converting this to a min would handle comparisons between positive
13497 // and negative zero incorrectly, and swapping the operands would
13498 // cause it to handle NaNs incorrectly.
13499 if (!DAG.getTarget().Options.UnsafeFPMath &&
13500 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13501 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13503 std::swap(LHS, RHS);
13505 Opcode = X86ISD::FMIN;
13508 // Converting this to a min would handle NaNs incorrectly.
13509 if (!DAG.getTarget().Options.UnsafeFPMath &&
13510 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13512 Opcode = X86ISD::FMIN;
13515 // Converting this to a min would handle both negative zeros and NaNs
13516 // incorrectly, but we can swap the operands to fix both.
13517 std::swap(LHS, RHS);
13521 Opcode = X86ISD::FMIN;
13525 // Converting this to a max would handle NaNs incorrectly.
13526 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13528 Opcode = X86ISD::FMAX;
13531 // Converting this to a max would handle comparisons between positive
13532 // and negative zero incorrectly, and swapping the operands would
13533 // cause it to handle NaNs incorrectly.
13534 if (!DAG.getTarget().Options.UnsafeFPMath &&
13535 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13536 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13538 std::swap(LHS, RHS);
13540 Opcode = X86ISD::FMAX;
13543 // Converting this to a max would handle both negative zeros and NaNs
13544 // incorrectly, but we can swap the operands to fix both.
13545 std::swap(LHS, RHS);
13549 Opcode = X86ISD::FMAX;
13555 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13558 // If this is a select between two integer constants, try to do some
13560 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13561 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13562 // Don't do this for crazy integer types.
13563 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13564 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13565 // so that TrueC (the true value) is larger than FalseC.
13566 bool NeedsCondInvert = false;
13568 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13569 // Efficiently invertible.
13570 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13571 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13572 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13573 NeedsCondInvert = true;
13574 std::swap(TrueC, FalseC);
13577 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13578 if (FalseC->getAPIntValue() == 0 &&
13579 TrueC->getAPIntValue().isPowerOf2()) {
13580 if (NeedsCondInvert) // Invert the condition if needed.
13581 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13582 DAG.getConstant(1, Cond.getValueType()));
13584 // Zero extend the condition if needed.
13585 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13587 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13588 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13589 DAG.getConstant(ShAmt, MVT::i8));
13592 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13593 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13594 if (NeedsCondInvert) // Invert the condition if needed.
13595 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13596 DAG.getConstant(1, Cond.getValueType()));
13598 // Zero extend the condition if needed.
13599 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13600 FalseC->getValueType(0), Cond);
13601 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13602 SDValue(FalseC, 0));
13605 // Optimize cases that will turn into an LEA instruction. This requires
13606 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13607 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13608 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13609 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13611 bool isFastMultiplier = false;
13613 switch ((unsigned char)Diff) {
13615 case 1: // result = add base, cond
13616 case 2: // result = lea base( , cond*2)
13617 case 3: // result = lea base(cond, cond*2)
13618 case 4: // result = lea base( , cond*4)
13619 case 5: // result = lea base(cond, cond*4)
13620 case 8: // result = lea base( , cond*8)
13621 case 9: // result = lea base(cond, cond*8)
13622 isFastMultiplier = true;
13627 if (isFastMultiplier) {
13628 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13629 if (NeedsCondInvert) // Invert the condition if needed.
13630 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13631 DAG.getConstant(1, Cond.getValueType()));
13633 // Zero extend the condition if needed.
13634 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13636 // Scale the condition by the difference.
13638 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13639 DAG.getConstant(Diff, Cond.getValueType()));
13641 // Add the base if non-zero.
13642 if (FalseC->getAPIntValue() != 0)
13643 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13644 SDValue(FalseC, 0));
13651 // Canonicalize max and min:
13652 // (x > y) ? x : y -> (x >= y) ? x : y
13653 // (x < y) ? x : y -> (x <= y) ? x : y
13654 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13655 // the need for an extra compare
13656 // against zero. e.g.
13657 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13659 // testl %edi, %edi
13661 // cmovgl %edi, %eax
13665 // cmovsl %eax, %edi
13666 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13667 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13668 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13669 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13674 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13675 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13676 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13677 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13682 // If we know that this node is legal then we know that it is going to be
13683 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13684 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13685 // to simplify previous instructions.
13686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13687 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13688 !DCI.isBeforeLegalize() &&
13689 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13690 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13691 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13692 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13694 APInt KnownZero, KnownOne;
13695 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13696 DCI.isBeforeLegalizeOps());
13697 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13698 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13699 DCI.CommitTargetLoweringOpt(TLO);
13705 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13706 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13707 TargetLowering::DAGCombinerInfo &DCI) {
13708 DebugLoc DL = N->getDebugLoc();
13710 // If the flag operand isn't dead, don't touch this CMOV.
13711 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13714 SDValue FalseOp = N->getOperand(0);
13715 SDValue TrueOp = N->getOperand(1);
13716 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13717 SDValue Cond = N->getOperand(3);
13718 if (CC == X86::COND_E || CC == X86::COND_NE) {
13719 switch (Cond.getOpcode()) {
13723 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13724 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13725 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13729 // If this is a select between two integer constants, try to do some
13730 // optimizations. Note that the operands are ordered the opposite of SELECT
13732 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13733 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13734 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13735 // larger than FalseC (the false value).
13736 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13737 CC = X86::GetOppositeBranchCondition(CC);
13738 std::swap(TrueC, FalseC);
13741 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13742 // This is efficient for any integer data type (including i8/i16) and
13744 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13745 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13746 DAG.getConstant(CC, MVT::i8), Cond);
13748 // Zero extend the condition if needed.
13749 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13751 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13752 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13753 DAG.getConstant(ShAmt, MVT::i8));
13754 if (N->getNumValues() == 2) // Dead flag value?
13755 return DCI.CombineTo(N, Cond, SDValue());
13759 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13760 // for any integer data type, including i8/i16.
13761 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13762 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13763 DAG.getConstant(CC, MVT::i8), Cond);
13765 // Zero extend the condition if needed.
13766 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13767 FalseC->getValueType(0), Cond);
13768 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13769 SDValue(FalseC, 0));
13771 if (N->getNumValues() == 2) // Dead flag value?
13772 return DCI.CombineTo(N, Cond, SDValue());
13776 // Optimize cases that will turn into an LEA instruction. This requires
13777 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13778 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13779 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13780 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13782 bool isFastMultiplier = false;
13784 switch ((unsigned char)Diff) {
13786 case 1: // result = add base, cond
13787 case 2: // result = lea base( , cond*2)
13788 case 3: // result = lea base(cond, cond*2)
13789 case 4: // result = lea base( , cond*4)
13790 case 5: // result = lea base(cond, cond*4)
13791 case 8: // result = lea base( , cond*8)
13792 case 9: // result = lea base(cond, cond*8)
13793 isFastMultiplier = true;
13798 if (isFastMultiplier) {
13799 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13800 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13801 DAG.getConstant(CC, MVT::i8), Cond);
13802 // Zero extend the condition if needed.
13803 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13805 // Scale the condition by the difference.
13807 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13808 DAG.getConstant(Diff, Cond.getValueType()));
13810 // Add the base if non-zero.
13811 if (FalseC->getAPIntValue() != 0)
13812 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13813 SDValue(FalseC, 0));
13814 if (N->getNumValues() == 2) // Dead flag value?
13815 return DCI.CombineTo(N, Cond, SDValue());
13825 /// PerformMulCombine - Optimize a single multiply with constant into two
13826 /// in order to implement it with two cheaper instructions, e.g.
13827 /// LEA + SHL, LEA + LEA.
13828 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13829 TargetLowering::DAGCombinerInfo &DCI) {
13830 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13833 EVT VT = N->getValueType(0);
13834 if (VT != MVT::i64)
13837 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13840 uint64_t MulAmt = C->getZExtValue();
13841 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13844 uint64_t MulAmt1 = 0;
13845 uint64_t MulAmt2 = 0;
13846 if ((MulAmt % 9) == 0) {
13848 MulAmt2 = MulAmt / 9;
13849 } else if ((MulAmt % 5) == 0) {
13851 MulAmt2 = MulAmt / 5;
13852 } else if ((MulAmt % 3) == 0) {
13854 MulAmt2 = MulAmt / 3;
13857 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13858 DebugLoc DL = N->getDebugLoc();
13860 if (isPowerOf2_64(MulAmt2) &&
13861 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13862 // If second multiplifer is pow2, issue it first. We want the multiply by
13863 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13865 std::swap(MulAmt1, MulAmt2);
13868 if (isPowerOf2_64(MulAmt1))
13869 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13870 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13872 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13873 DAG.getConstant(MulAmt1, VT));
13875 if (isPowerOf2_64(MulAmt2))
13876 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13877 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13879 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13880 DAG.getConstant(MulAmt2, VT));
13882 // Do not add new nodes to DAG combiner worklist.
13883 DCI.CombineTo(N, NewMul, false);
13888 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13889 SDValue N0 = N->getOperand(0);
13890 SDValue N1 = N->getOperand(1);
13891 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13892 EVT VT = N0.getValueType();
13894 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13895 // since the result of setcc_c is all zero's or all ones.
13896 if (VT.isInteger() && !VT.isVector() &&
13897 N1C && N0.getOpcode() == ISD::AND &&
13898 N0.getOperand(1).getOpcode() == ISD::Constant) {
13899 SDValue N00 = N0.getOperand(0);
13900 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13901 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13902 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13903 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13904 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13905 APInt ShAmt = N1C->getAPIntValue();
13906 Mask = Mask.shl(ShAmt);
13908 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13909 N00, DAG.getConstant(Mask, VT));
13914 // Hardware support for vector shifts is sparse which makes us scalarize the
13915 // vector operations in many cases. Also, on sandybridge ADD is faster than
13917 // (shl V, 1) -> add V,V
13918 if (isSplatVector(N1.getNode())) {
13919 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13920 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13921 // We shift all of the values by one. In many cases we do not have
13922 // hardware support for this operation. This is better expressed as an ADD
13924 if (N1C && (1 == N1C->getZExtValue())) {
13925 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13932 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13934 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13935 TargetLowering::DAGCombinerInfo &DCI,
13936 const X86Subtarget *Subtarget) {
13937 EVT VT = N->getValueType(0);
13938 if (N->getOpcode() == ISD::SHL) {
13939 SDValue V = PerformSHLCombine(N, DAG);
13940 if (V.getNode()) return V;
13943 // On X86 with SSE2 support, we can transform this to a vector shift if
13944 // all elements are shifted by the same amount. We can't do this in legalize
13945 // because the a constant vector is typically transformed to a constant pool
13946 // so we have no knowledge of the shift amount.
13947 if (!Subtarget->hasSSE2())
13950 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13951 (!Subtarget->hasAVX2() ||
13952 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13955 SDValue ShAmtOp = N->getOperand(1);
13956 EVT EltVT = VT.getVectorElementType();
13957 DebugLoc DL = N->getDebugLoc();
13958 SDValue BaseShAmt = SDValue();
13959 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13960 unsigned NumElts = VT.getVectorNumElements();
13962 for (; i != NumElts; ++i) {
13963 SDValue Arg = ShAmtOp.getOperand(i);
13964 if (Arg.getOpcode() == ISD::UNDEF) continue;
13968 // Handle the case where the build_vector is all undef
13969 // FIXME: Should DAG allow this?
13973 for (; i != NumElts; ++i) {
13974 SDValue Arg = ShAmtOp.getOperand(i);
13975 if (Arg.getOpcode() == ISD::UNDEF) continue;
13976 if (Arg != BaseShAmt) {
13980 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13981 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13982 SDValue InVec = ShAmtOp.getOperand(0);
13983 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13984 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13986 for (; i != NumElts; ++i) {
13987 SDValue Arg = InVec.getOperand(i);
13988 if (Arg.getOpcode() == ISD::UNDEF) continue;
13992 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13993 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13994 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13995 if (C->getZExtValue() == SplatIdx)
13996 BaseShAmt = InVec.getOperand(1);
13999 if (BaseShAmt.getNode() == 0) {
14000 // Don't create instructions with illegal types after legalize
14002 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
14003 !DCI.isBeforeLegalize())
14006 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14007 DAG.getIntPtrConstant(0));
14012 // The shift amount is an i32.
14013 if (EltVT.bitsGT(MVT::i32))
14014 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
14015 else if (EltVT.bitsLT(MVT::i32))
14016 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
14018 // The shift amount is identical so we can do a vector shift.
14019 SDValue ValOp = N->getOperand(0);
14020 switch (N->getOpcode()) {
14022 llvm_unreachable("Unknown shift opcode!");
14024 switch (VT.getSimpleVT().SimpleTy) {
14025 default: return SDValue();
14032 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14035 switch (VT.getSimpleVT().SimpleTy) {
14036 default: return SDValue();
14041 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14044 switch (VT.getSimpleVT().SimpleTy) {
14045 default: return SDValue();
14052 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14058 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14059 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14060 // and friends. Likewise for OR -> CMPNEQSS.
14061 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14062 TargetLowering::DAGCombinerInfo &DCI,
14063 const X86Subtarget *Subtarget) {
14066 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14067 // we're requiring SSE2 for both.
14068 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14069 SDValue N0 = N->getOperand(0);
14070 SDValue N1 = N->getOperand(1);
14071 SDValue CMP0 = N0->getOperand(1);
14072 SDValue CMP1 = N1->getOperand(1);
14073 DebugLoc DL = N->getDebugLoc();
14075 // The SETCCs should both refer to the same CMP.
14076 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14079 SDValue CMP00 = CMP0->getOperand(0);
14080 SDValue CMP01 = CMP0->getOperand(1);
14081 EVT VT = CMP00.getValueType();
14083 if (VT == MVT::f32 || VT == MVT::f64) {
14084 bool ExpectingFlags = false;
14085 // Check for any users that want flags:
14086 for (SDNode::use_iterator UI = N->use_begin(),
14088 !ExpectingFlags && UI != UE; ++UI)
14089 switch (UI->getOpcode()) {
14094 ExpectingFlags = true;
14096 case ISD::CopyToReg:
14097 case ISD::SIGN_EXTEND:
14098 case ISD::ZERO_EXTEND:
14099 case ISD::ANY_EXTEND:
14103 if (!ExpectingFlags) {
14104 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14105 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14107 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14108 X86::CondCode tmp = cc0;
14113 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14114 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14115 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14116 X86ISD::NodeType NTOperator = is64BitFP ?
14117 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14118 // FIXME: need symbolic constants for these magic numbers.
14119 // See X86ATTInstPrinter.cpp:printSSECC().
14120 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14121 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14122 DAG.getConstant(x86cc, MVT::i8));
14123 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14125 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14126 DAG.getConstant(1, MVT::i32));
14127 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14128 return OneBitOfTruth;
14136 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14137 /// so it can be folded inside ANDNP.
14138 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14139 EVT VT = N->getValueType(0);
14141 // Match direct AllOnes for 128 and 256-bit vectors
14142 if (ISD::isBuildVectorAllOnes(N))
14145 // Look through a bit convert.
14146 if (N->getOpcode() == ISD::BITCAST)
14147 N = N->getOperand(0).getNode();
14149 // Sometimes the operand may come from a insert_subvector building a 256-bit
14151 if (VT.getSizeInBits() == 256 &&
14152 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14153 SDValue V1 = N->getOperand(0);
14154 SDValue V2 = N->getOperand(1);
14156 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14157 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14158 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14159 ISD::isBuildVectorAllOnes(V2.getNode()))
14166 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14167 TargetLowering::DAGCombinerInfo &DCI,
14168 const X86Subtarget *Subtarget) {
14169 if (DCI.isBeforeLegalizeOps())
14172 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14176 EVT VT = N->getValueType(0);
14178 // Create ANDN, BLSI, and BLSR instructions
14179 // BLSI is X & (-X)
14180 // BLSR is X & (X-1)
14181 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14182 SDValue N0 = N->getOperand(0);
14183 SDValue N1 = N->getOperand(1);
14184 DebugLoc DL = N->getDebugLoc();
14186 // Check LHS for not
14187 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14188 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14189 // Check RHS for not
14190 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14191 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14193 // Check LHS for neg
14194 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14195 isZero(N0.getOperand(0)))
14196 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14198 // Check RHS for neg
14199 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14200 isZero(N1.getOperand(0)))
14201 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14203 // Check LHS for X-1
14204 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14205 isAllOnes(N0.getOperand(1)))
14206 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14208 // Check RHS for X-1
14209 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14210 isAllOnes(N1.getOperand(1)))
14211 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14216 // Want to form ANDNP nodes:
14217 // 1) In the hopes of then easily combining them with OR and AND nodes
14218 // to form PBLEND/PSIGN.
14219 // 2) To match ANDN packed intrinsics
14220 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14223 SDValue N0 = N->getOperand(0);
14224 SDValue N1 = N->getOperand(1);
14225 DebugLoc DL = N->getDebugLoc();
14227 // Check LHS for vnot
14228 if (N0.getOpcode() == ISD::XOR &&
14229 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14230 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14231 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14233 // Check RHS for vnot
14234 if (N1.getOpcode() == ISD::XOR &&
14235 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14236 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14237 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14242 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14243 TargetLowering::DAGCombinerInfo &DCI,
14244 const X86Subtarget *Subtarget) {
14245 if (DCI.isBeforeLegalizeOps())
14248 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14252 EVT VT = N->getValueType(0);
14254 SDValue N0 = N->getOperand(0);
14255 SDValue N1 = N->getOperand(1);
14257 // look for psign/blend
14258 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14259 if (!Subtarget->hasSSSE3() ||
14260 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14263 // Canonicalize pandn to RHS
14264 if (N0.getOpcode() == X86ISD::ANDNP)
14266 // or (and (m, y), (pandn m, x))
14267 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14268 SDValue Mask = N1.getOperand(0);
14269 SDValue X = N1.getOperand(1);
14271 if (N0.getOperand(0) == Mask)
14272 Y = N0.getOperand(1);
14273 if (N0.getOperand(1) == Mask)
14274 Y = N0.getOperand(0);
14276 // Check to see if the mask appeared in both the AND and ANDNP and
14280 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14281 // Look through mask bitcast.
14282 if (Mask.getOpcode() == ISD::BITCAST)
14283 Mask = Mask.getOperand(0);
14284 if (X.getOpcode() == ISD::BITCAST)
14285 X = X.getOperand(0);
14286 if (Y.getOpcode() == ISD::BITCAST)
14287 Y = Y.getOperand(0);
14289 EVT MaskVT = Mask.getValueType();
14291 // Validate that the Mask operand is a vector sra node.
14292 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14293 // there is no psrai.b
14294 if (Mask.getOpcode() != X86ISD::VSRAI)
14297 // Check that the SRA is all signbits.
14298 SDValue SraC = Mask.getOperand(1);
14299 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14300 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14301 if ((SraAmt + 1) != EltBits)
14304 DebugLoc DL = N->getDebugLoc();
14306 // Now we know we at least have a plendvb with the mask val. See if
14307 // we can form a psignb/w/d.
14308 // psign = x.type == y.type == mask.type && y = sub(0, x);
14309 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14310 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14311 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14312 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14313 "Unsupported VT for PSIGN");
14314 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14315 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14317 // PBLENDVB only available on SSE 4.1
14318 if (!Subtarget->hasSSE41())
14321 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14323 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14324 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14325 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14326 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14327 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14331 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14334 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14335 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14337 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14339 if (!N0.hasOneUse() || !N1.hasOneUse())
14342 SDValue ShAmt0 = N0.getOperand(1);
14343 if (ShAmt0.getValueType() != MVT::i8)
14345 SDValue ShAmt1 = N1.getOperand(1);
14346 if (ShAmt1.getValueType() != MVT::i8)
14348 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14349 ShAmt0 = ShAmt0.getOperand(0);
14350 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14351 ShAmt1 = ShAmt1.getOperand(0);
14353 DebugLoc DL = N->getDebugLoc();
14354 unsigned Opc = X86ISD::SHLD;
14355 SDValue Op0 = N0.getOperand(0);
14356 SDValue Op1 = N1.getOperand(0);
14357 if (ShAmt0.getOpcode() == ISD::SUB) {
14358 Opc = X86ISD::SHRD;
14359 std::swap(Op0, Op1);
14360 std::swap(ShAmt0, ShAmt1);
14363 unsigned Bits = VT.getSizeInBits();
14364 if (ShAmt1.getOpcode() == ISD::SUB) {
14365 SDValue Sum = ShAmt1.getOperand(0);
14366 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14367 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14368 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14369 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14370 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14371 return DAG.getNode(Opc, DL, VT,
14373 DAG.getNode(ISD::TRUNCATE, DL,
14376 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14377 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14379 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14380 return DAG.getNode(Opc, DL, VT,
14381 N0.getOperand(0), N1.getOperand(0),
14382 DAG.getNode(ISD::TRUNCATE, DL,
14389 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14390 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14391 TargetLowering::DAGCombinerInfo &DCI,
14392 const X86Subtarget *Subtarget) {
14393 if (DCI.isBeforeLegalizeOps())
14396 EVT VT = N->getValueType(0);
14398 if (VT != MVT::i32 && VT != MVT::i64)
14401 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14403 // Create BLSMSK instructions by finding X ^ (X-1)
14404 SDValue N0 = N->getOperand(0);
14405 SDValue N1 = N->getOperand(1);
14406 DebugLoc DL = N->getDebugLoc();
14408 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14409 isAllOnes(N0.getOperand(1)))
14410 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14412 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14413 isAllOnes(N1.getOperand(1)))
14414 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14419 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14420 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14421 const X86Subtarget *Subtarget) {
14422 LoadSDNode *Ld = cast<LoadSDNode>(N);
14423 EVT RegVT = Ld->getValueType(0);
14424 EVT MemVT = Ld->getMemoryVT();
14425 DebugLoc dl = Ld->getDebugLoc();
14426 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14428 ISD::LoadExtType Ext = Ld->getExtensionType();
14430 // If this is a vector EXT Load then attempt to optimize it using a
14431 // shuffle. We need SSE4 for the shuffles.
14432 // TODO: It is possible to support ZExt by zeroing the undef values
14433 // during the shuffle phase or after the shuffle.
14434 if (RegVT.isVector() && RegVT.isInteger() &&
14435 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14436 assert(MemVT != RegVT && "Cannot extend to the same type");
14437 assert(MemVT.isVector() && "Must load a vector from memory");
14439 unsigned NumElems = RegVT.getVectorNumElements();
14440 unsigned RegSz = RegVT.getSizeInBits();
14441 unsigned MemSz = MemVT.getSizeInBits();
14442 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14443 // All sizes must be a power of two
14444 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14446 // Attempt to load the original value using a single load op.
14447 // Find a scalar type which is equal to the loaded word size.
14448 MVT SclrLoadTy = MVT::i8;
14449 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14450 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14451 MVT Tp = (MVT::SimpleValueType)tp;
14452 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14458 // Proceed if a load word is found.
14459 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14461 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14462 RegSz/SclrLoadTy.getSizeInBits());
14464 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14465 RegSz/MemVT.getScalarType().getSizeInBits());
14466 // Can't shuffle using an illegal type.
14467 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14469 // Perform a single load.
14470 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14472 Ld->getPointerInfo(), Ld->isVolatile(),
14473 Ld->isNonTemporal(), Ld->isInvariant(),
14474 Ld->getAlignment());
14476 // Insert the word loaded into a vector.
14477 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14478 LoadUnitVecVT, ScalarLoad);
14480 // Bitcast the loaded value to a vector of the original element type, in
14481 // the size of the target vector type.
14482 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14484 unsigned SizeRatio = RegSz/MemSz;
14486 // Redistribute the loaded elements into the different locations.
14487 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14488 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14490 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14491 DAG.getUNDEF(WideVecVT),
14494 // Bitcast to the requested type.
14495 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14496 // Replace the original load with the new sequence
14497 // and return the new chain.
14498 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14499 return SDValue(ScalarLoad.getNode(), 1);
14505 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14506 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14507 const X86Subtarget *Subtarget) {
14508 StoreSDNode *St = cast<StoreSDNode>(N);
14509 EVT VT = St->getValue().getValueType();
14510 EVT StVT = St->getMemoryVT();
14511 DebugLoc dl = St->getDebugLoc();
14512 SDValue StoredVal = St->getOperand(1);
14513 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14515 // If we are saving a concatenation of two XMM registers, perform two stores.
14516 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14517 // 128-bit ones. If in the future the cost becomes only one memory access the
14518 // first version would be better.
14519 if (VT.getSizeInBits() == 256 &&
14520 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14521 StoredVal.getNumOperands() == 2) {
14523 SDValue Value0 = StoredVal.getOperand(0);
14524 SDValue Value1 = StoredVal.getOperand(1);
14526 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14527 SDValue Ptr0 = St->getBasePtr();
14528 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14530 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14531 St->getPointerInfo(), St->isVolatile(),
14532 St->isNonTemporal(), St->getAlignment());
14533 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14534 St->getPointerInfo(), St->isVolatile(),
14535 St->isNonTemporal(), St->getAlignment());
14536 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14539 // Optimize trunc store (of multiple scalars) to shuffle and store.
14540 // First, pack all of the elements in one place. Next, store to memory
14541 // in fewer chunks.
14542 if (St->isTruncatingStore() && VT.isVector()) {
14543 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14544 unsigned NumElems = VT.getVectorNumElements();
14545 assert(StVT != VT && "Cannot truncate to the same type");
14546 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14547 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14549 // From, To sizes and ElemCount must be pow of two
14550 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14551 // We are going to use the original vector elt for storing.
14552 // Accumulated smaller vector elements must be a multiple of the store size.
14553 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14555 unsigned SizeRatio = FromSz / ToSz;
14557 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14559 // Create a type on which we perform the shuffle
14560 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14561 StVT.getScalarType(), NumElems*SizeRatio);
14563 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14565 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14566 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14567 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14569 // Can't shuffle using an illegal type
14570 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14572 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14573 DAG.getUNDEF(WideVecVT),
14575 // At this point all of the data is stored at the bottom of the
14576 // register. We now need to save it to mem.
14578 // Find the largest store unit
14579 MVT StoreType = MVT::i8;
14580 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14581 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14582 MVT Tp = (MVT::SimpleValueType)tp;
14583 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14587 // Bitcast the original vector into a vector of store-size units
14588 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14589 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14590 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14591 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14592 SmallVector<SDValue, 8> Chains;
14593 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14594 TLI.getPointerTy());
14595 SDValue Ptr = St->getBasePtr();
14597 // Perform one or more big stores into memory.
14598 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14599 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14600 StoreType, ShuffWide,
14601 DAG.getIntPtrConstant(i));
14602 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14603 St->getPointerInfo(), St->isVolatile(),
14604 St->isNonTemporal(), St->getAlignment());
14605 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14606 Chains.push_back(Ch);
14609 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14614 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14615 // the FP state in cases where an emms may be missing.
14616 // A preferable solution to the general problem is to figure out the right
14617 // places to insert EMMS. This qualifies as a quick hack.
14619 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14620 if (VT.getSizeInBits() != 64)
14623 const Function *F = DAG.getMachineFunction().getFunction();
14624 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14625 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14626 && Subtarget->hasSSE2();
14627 if ((VT.isVector() ||
14628 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14629 isa<LoadSDNode>(St->getValue()) &&
14630 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14631 St->getChain().hasOneUse() && !St->isVolatile()) {
14632 SDNode* LdVal = St->getValue().getNode();
14633 LoadSDNode *Ld = 0;
14634 int TokenFactorIndex = -1;
14635 SmallVector<SDValue, 8> Ops;
14636 SDNode* ChainVal = St->getChain().getNode();
14637 // Must be a store of a load. We currently handle two cases: the load
14638 // is a direct child, and it's under an intervening TokenFactor. It is
14639 // possible to dig deeper under nested TokenFactors.
14640 if (ChainVal == LdVal)
14641 Ld = cast<LoadSDNode>(St->getChain());
14642 else if (St->getValue().hasOneUse() &&
14643 ChainVal->getOpcode() == ISD::TokenFactor) {
14644 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14645 if (ChainVal->getOperand(i).getNode() == LdVal) {
14646 TokenFactorIndex = i;
14647 Ld = cast<LoadSDNode>(St->getValue());
14649 Ops.push_back(ChainVal->getOperand(i));
14653 if (!Ld || !ISD::isNormalLoad(Ld))
14656 // If this is not the MMX case, i.e. we are just turning i64 load/store
14657 // into f64 load/store, avoid the transformation if there are multiple
14658 // uses of the loaded value.
14659 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14662 DebugLoc LdDL = Ld->getDebugLoc();
14663 DebugLoc StDL = N->getDebugLoc();
14664 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14665 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14667 if (Subtarget->is64Bit() || F64IsLegal) {
14668 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14669 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14670 Ld->getPointerInfo(), Ld->isVolatile(),
14671 Ld->isNonTemporal(), Ld->isInvariant(),
14672 Ld->getAlignment());
14673 SDValue NewChain = NewLd.getValue(1);
14674 if (TokenFactorIndex != -1) {
14675 Ops.push_back(NewChain);
14676 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14679 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14680 St->getPointerInfo(),
14681 St->isVolatile(), St->isNonTemporal(),
14682 St->getAlignment());
14685 // Otherwise, lower to two pairs of 32-bit loads / stores.
14686 SDValue LoAddr = Ld->getBasePtr();
14687 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14688 DAG.getConstant(4, MVT::i32));
14690 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14691 Ld->getPointerInfo(),
14692 Ld->isVolatile(), Ld->isNonTemporal(),
14693 Ld->isInvariant(), Ld->getAlignment());
14694 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14695 Ld->getPointerInfo().getWithOffset(4),
14696 Ld->isVolatile(), Ld->isNonTemporal(),
14698 MinAlign(Ld->getAlignment(), 4));
14700 SDValue NewChain = LoLd.getValue(1);
14701 if (TokenFactorIndex != -1) {
14702 Ops.push_back(LoLd);
14703 Ops.push_back(HiLd);
14704 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14708 LoAddr = St->getBasePtr();
14709 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14710 DAG.getConstant(4, MVT::i32));
14712 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14713 St->getPointerInfo(),
14714 St->isVolatile(), St->isNonTemporal(),
14715 St->getAlignment());
14716 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14717 St->getPointerInfo().getWithOffset(4),
14719 St->isNonTemporal(),
14720 MinAlign(St->getAlignment(), 4));
14721 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14726 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14727 /// and return the operands for the horizontal operation in LHS and RHS. A
14728 /// horizontal operation performs the binary operation on successive elements
14729 /// of its first operand, then on successive elements of its second operand,
14730 /// returning the resulting values in a vector. For example, if
14731 /// A = < float a0, float a1, float a2, float a3 >
14733 /// B = < float b0, float b1, float b2, float b3 >
14734 /// then the result of doing a horizontal operation on A and B is
14735 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14736 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14737 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14738 /// set to A, RHS to B, and the routine returns 'true'.
14739 /// Note that the binary operation should have the property that if one of the
14740 /// operands is UNDEF then the result is UNDEF.
14741 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14742 // Look for the following pattern: if
14743 // A = < float a0, float a1, float a2, float a3 >
14744 // B = < float b0, float b1, float b2, float b3 >
14746 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14747 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14748 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14749 // which is A horizontal-op B.
14751 // At least one of the operands should be a vector shuffle.
14752 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14753 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14756 EVT VT = LHS.getValueType();
14758 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14759 "Unsupported vector type for horizontal add/sub");
14761 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14762 // operate independently on 128-bit lanes.
14763 unsigned NumElts = VT.getVectorNumElements();
14764 unsigned NumLanes = VT.getSizeInBits()/128;
14765 unsigned NumLaneElts = NumElts / NumLanes;
14766 assert((NumLaneElts % 2 == 0) &&
14767 "Vector type should have an even number of elements in each lane");
14768 unsigned HalfLaneElts = NumLaneElts/2;
14770 // View LHS in the form
14771 // LHS = VECTOR_SHUFFLE A, B, LMask
14772 // If LHS is not a shuffle then pretend it is the shuffle
14773 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14774 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14777 SmallVector<int, 16> LMask(NumElts);
14778 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14779 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14780 A = LHS.getOperand(0);
14781 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14782 B = LHS.getOperand(1);
14783 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14784 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14786 if (LHS.getOpcode() != ISD::UNDEF)
14788 for (unsigned i = 0; i != NumElts; ++i)
14792 // Likewise, view RHS in the form
14793 // RHS = VECTOR_SHUFFLE C, D, RMask
14795 SmallVector<int, 16> RMask(NumElts);
14796 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14797 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14798 C = RHS.getOperand(0);
14799 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14800 D = RHS.getOperand(1);
14801 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14802 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14804 if (RHS.getOpcode() != ISD::UNDEF)
14806 for (unsigned i = 0; i != NumElts; ++i)
14810 // Check that the shuffles are both shuffling the same vectors.
14811 if (!(A == C && B == D) && !(A == D && B == C))
14814 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14815 if (!A.getNode() && !B.getNode())
14818 // If A and B occur in reverse order in RHS, then "swap" them (which means
14819 // rewriting the mask).
14821 CommuteVectorShuffleMask(RMask, NumElts);
14823 // At this point LHS and RHS are equivalent to
14824 // LHS = VECTOR_SHUFFLE A, B, LMask
14825 // RHS = VECTOR_SHUFFLE A, B, RMask
14826 // Check that the masks correspond to performing a horizontal operation.
14827 for (unsigned i = 0; i != NumElts; ++i) {
14828 int LIdx = LMask[i], RIdx = RMask[i];
14830 // Ignore any UNDEF components.
14831 if (LIdx < 0 || RIdx < 0 ||
14832 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14833 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14836 // Check that successive elements are being operated on. If not, this is
14837 // not a horizontal operation.
14838 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14839 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14840 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14841 if (!(LIdx == Index && RIdx == Index + 1) &&
14842 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14846 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14847 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14851 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14852 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14853 const X86Subtarget *Subtarget) {
14854 EVT VT = N->getValueType(0);
14855 SDValue LHS = N->getOperand(0);
14856 SDValue RHS = N->getOperand(1);
14858 // Try to synthesize horizontal adds from adds of shuffles.
14859 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14860 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14861 isHorizontalBinOp(LHS, RHS, true))
14862 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14866 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14867 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14868 const X86Subtarget *Subtarget) {
14869 EVT VT = N->getValueType(0);
14870 SDValue LHS = N->getOperand(0);
14871 SDValue RHS = N->getOperand(1);
14873 // Try to synthesize horizontal subs from subs of shuffles.
14874 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14875 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14876 isHorizontalBinOp(LHS, RHS, false))
14877 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14881 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14882 /// X86ISD::FXOR nodes.
14883 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14884 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14885 // F[X]OR(0.0, x) -> x
14886 // F[X]OR(x, 0.0) -> x
14887 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14888 if (C->getValueAPF().isPosZero())
14889 return N->getOperand(1);
14890 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14891 if (C->getValueAPF().isPosZero())
14892 return N->getOperand(0);
14896 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14897 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14898 // FAND(0.0, x) -> 0.0
14899 // FAND(x, 0.0) -> 0.0
14900 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14901 if (C->getValueAPF().isPosZero())
14902 return N->getOperand(0);
14903 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14904 if (C->getValueAPF().isPosZero())
14905 return N->getOperand(1);
14909 static SDValue PerformBTCombine(SDNode *N,
14911 TargetLowering::DAGCombinerInfo &DCI) {
14912 // BT ignores high bits in the bit index operand.
14913 SDValue Op1 = N->getOperand(1);
14914 if (Op1.hasOneUse()) {
14915 unsigned BitWidth = Op1.getValueSizeInBits();
14916 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14917 APInt KnownZero, KnownOne;
14918 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14919 !DCI.isBeforeLegalizeOps());
14920 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14921 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14922 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14923 DCI.CommitTargetLoweringOpt(TLO);
14928 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14929 SDValue Op = N->getOperand(0);
14930 if (Op.getOpcode() == ISD::BITCAST)
14931 Op = Op.getOperand(0);
14932 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14933 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14934 VT.getVectorElementType().getSizeInBits() ==
14935 OpVT.getVectorElementType().getSizeInBits()) {
14936 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14941 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14942 TargetLowering::DAGCombinerInfo &DCI,
14943 const X86Subtarget *Subtarget) {
14944 if (!DCI.isBeforeLegalizeOps())
14947 if (!Subtarget->hasAVX())
14950 EVT VT = N->getValueType(0);
14951 SDValue Op = N->getOperand(0);
14952 EVT OpVT = Op.getValueType();
14953 DebugLoc dl = N->getDebugLoc();
14955 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14956 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14958 if (Subtarget->hasAVX2())
14959 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14961 // Optimize vectors in AVX mode
14962 // Sign extend v8i16 to v8i32 and
14965 // Divide input vector into two parts
14966 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14967 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14968 // concat the vectors to original VT
14970 unsigned NumElems = OpVT.getVectorNumElements();
14971 SmallVector<int,8> ShufMask1(NumElems, -1);
14972 for (unsigned i = 0; i != NumElems/2; ++i)
14975 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14978 SmallVector<int,8> ShufMask2(NumElems, -1);
14979 for (unsigned i = 0; i != NumElems/2; ++i)
14980 ShufMask2[i] = i + NumElems/2;
14982 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14985 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14986 VT.getVectorNumElements()/2);
14988 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14989 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14991 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14996 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14997 TargetLowering::DAGCombinerInfo &DCI,
14998 const X86Subtarget *Subtarget) {
14999 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
15000 // (and (i32 x86isd::setcc_carry), 1)
15001 // This eliminates the zext. This transformation is necessary because
15002 // ISD::SETCC is always legalized to i8.
15003 DebugLoc dl = N->getDebugLoc();
15004 SDValue N0 = N->getOperand(0);
15005 EVT VT = N->getValueType(0);
15006 EVT OpVT = N0.getValueType();
15008 if (N0.getOpcode() == ISD::AND &&
15010 N0.getOperand(0).hasOneUse()) {
15011 SDValue N00 = N0.getOperand(0);
15012 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15014 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15015 if (!C || C->getZExtValue() != 1)
15017 return DAG.getNode(ISD::AND, dl, VT,
15018 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15019 N00.getOperand(0), N00.getOperand(1)),
15020 DAG.getConstant(1, VT));
15023 // Optimize vectors in AVX mode:
15026 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15027 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15028 // Concat upper and lower parts.
15031 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15032 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15033 // Concat upper and lower parts.
15035 if (!DCI.isBeforeLegalizeOps())
15038 if (!Subtarget->hasAVX())
15041 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15042 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15044 if (Subtarget->hasAVX2())
15045 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15047 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15048 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15049 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15051 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15052 VT.getVectorNumElements()/2);
15054 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15055 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15057 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15063 // Optimize x == -y --> x+y == 0
15064 // x != -y --> x+y != 0
15065 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15066 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15067 SDValue LHS = N->getOperand(0);
15068 SDValue RHS = N->getOperand(1);
15070 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15071 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15072 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15073 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15074 LHS.getValueType(), RHS, LHS.getOperand(1));
15075 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15076 addV, DAG.getConstant(0, addV.getValueType()), CC);
15078 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15079 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15080 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15081 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15082 RHS.getValueType(), LHS, RHS.getOperand(1));
15083 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15084 addV, DAG.getConstant(0, addV.getValueType()), CC);
15089 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15090 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15091 unsigned X86CC = N->getConstantOperandVal(0);
15092 SDValue EFLAG = N->getOperand(1);
15093 DebugLoc DL = N->getDebugLoc();
15095 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15096 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15098 if (X86CC == X86::COND_B)
15099 return DAG.getNode(ISD::AND, DL, MVT::i8,
15100 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15101 DAG.getConstant(X86CC, MVT::i8), EFLAG),
15102 DAG.getConstant(1, MVT::i8));
15107 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15108 SDValue Op0 = N->getOperand(0);
15109 EVT InVT = Op0->getValueType(0);
15111 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15112 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15113 DebugLoc dl = N->getDebugLoc();
15114 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15115 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15116 // Notice that we use SINT_TO_FP because we know that the high bits
15117 // are zero and SINT_TO_FP is better supported by the hardware.
15118 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15124 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15125 const X86TargetLowering *XTLI) {
15126 SDValue Op0 = N->getOperand(0);
15127 EVT InVT = Op0->getValueType(0);
15129 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15130 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15131 DebugLoc dl = N->getDebugLoc();
15132 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15133 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15134 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15137 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15138 // a 32-bit target where SSE doesn't support i64->FP operations.
15139 if (Op0.getOpcode() == ISD::LOAD) {
15140 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15141 EVT VT = Ld->getValueType(0);
15142 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15143 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15144 !XTLI->getSubtarget()->is64Bit() &&
15145 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15146 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15147 Ld->getChain(), Op0, DAG);
15148 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15155 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15156 EVT VT = N->getValueType(0);
15158 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15159 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15160 DebugLoc dl = N->getDebugLoc();
15161 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15162 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15163 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15169 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15170 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15171 X86TargetLowering::DAGCombinerInfo &DCI) {
15172 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15173 // the result is either zero or one (depending on the input carry bit).
15174 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15175 if (X86::isZeroNode(N->getOperand(0)) &&
15176 X86::isZeroNode(N->getOperand(1)) &&
15177 // We don't have a good way to replace an EFLAGS use, so only do this when
15179 SDValue(N, 1).use_empty()) {
15180 DebugLoc DL = N->getDebugLoc();
15181 EVT VT = N->getValueType(0);
15182 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15183 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15184 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15185 DAG.getConstant(X86::COND_B,MVT::i8),
15187 DAG.getConstant(1, VT));
15188 return DCI.CombineTo(N, Res1, CarryOut);
15194 // fold (add Y, (sete X, 0)) -> adc 0, Y
15195 // (add Y, (setne X, 0)) -> sbb -1, Y
15196 // (sub (sete X, 0), Y) -> sbb 0, Y
15197 // (sub (setne X, 0), Y) -> adc -1, Y
15198 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15199 DebugLoc DL = N->getDebugLoc();
15201 // Look through ZExts.
15202 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15203 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15206 SDValue SetCC = Ext.getOperand(0);
15207 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15210 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15211 if (CC != X86::COND_E && CC != X86::COND_NE)
15214 SDValue Cmp = SetCC.getOperand(1);
15215 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15216 !X86::isZeroNode(Cmp.getOperand(1)) ||
15217 !Cmp.getOperand(0).getValueType().isInteger())
15220 SDValue CmpOp0 = Cmp.getOperand(0);
15221 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15222 DAG.getConstant(1, CmpOp0.getValueType()));
15224 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15225 if (CC == X86::COND_NE)
15226 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15227 DL, OtherVal.getValueType(), OtherVal,
15228 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15229 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15230 DL, OtherVal.getValueType(), OtherVal,
15231 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15234 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15235 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15236 const X86Subtarget *Subtarget) {
15237 EVT VT = N->getValueType(0);
15238 SDValue Op0 = N->getOperand(0);
15239 SDValue Op1 = N->getOperand(1);
15241 // Try to synthesize horizontal adds from adds of shuffles.
15242 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15243 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15244 isHorizontalBinOp(Op0, Op1, true))
15245 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15247 return OptimizeConditionalInDecrement(N, DAG);
15250 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15251 const X86Subtarget *Subtarget) {
15252 SDValue Op0 = N->getOperand(0);
15253 SDValue Op1 = N->getOperand(1);
15255 // X86 can't encode an immediate LHS of a sub. See if we can push the
15256 // negation into a preceding instruction.
15257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15258 // If the RHS of the sub is a XOR with one use and a constant, invert the
15259 // immediate. Then add one to the LHS of the sub so we can turn
15260 // X-Y -> X+~Y+1, saving one register.
15261 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15262 isa<ConstantSDNode>(Op1.getOperand(1))) {
15263 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15264 EVT VT = Op0.getValueType();
15265 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15267 DAG.getConstant(~XorC, VT));
15268 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15269 DAG.getConstant(C->getAPIntValue()+1, VT));
15273 // Try to synthesize horizontal adds from adds of shuffles.
15274 EVT VT = N->getValueType(0);
15275 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15276 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15277 isHorizontalBinOp(Op0, Op1, true))
15278 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15280 return OptimizeConditionalInDecrement(N, DAG);
15283 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15284 DAGCombinerInfo &DCI) const {
15285 SelectionDAG &DAG = DCI.DAG;
15286 switch (N->getOpcode()) {
15288 case ISD::EXTRACT_VECTOR_ELT:
15289 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15291 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15292 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15293 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15294 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15295 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15296 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15299 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15300 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15301 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15302 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15303 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15304 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15305 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15306 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15307 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15308 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15309 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15311 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15312 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15313 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15314 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15315 case ISD::ANY_EXTEND:
15316 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15317 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15318 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15319 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15320 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15321 case X86ISD::SHUFP: // Handle all target specific shuffles
15322 case X86ISD::PALIGN:
15323 case X86ISD::UNPCKH:
15324 case X86ISD::UNPCKL:
15325 case X86ISD::MOVHLPS:
15326 case X86ISD::MOVLHPS:
15327 case X86ISD::PSHUFD:
15328 case X86ISD::PSHUFHW:
15329 case X86ISD::PSHUFLW:
15330 case X86ISD::MOVSS:
15331 case X86ISD::MOVSD:
15332 case X86ISD::VPERMILP:
15333 case X86ISD::VPERM2X128:
15334 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15340 /// isTypeDesirableForOp - Return true if the target has native support for
15341 /// the specified value type and it is 'desirable' to use the type for the
15342 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15343 /// instruction encodings are longer and some i16 instructions are slow.
15344 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15345 if (!isTypeLegal(VT))
15347 if (VT != MVT::i16)
15354 case ISD::SIGN_EXTEND:
15355 case ISD::ZERO_EXTEND:
15356 case ISD::ANY_EXTEND:
15369 /// IsDesirableToPromoteOp - This method query the target whether it is
15370 /// beneficial for dag combiner to promote the specified node. If true, it
15371 /// should return the desired promotion type by reference.
15372 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15373 EVT VT = Op.getValueType();
15374 if (VT != MVT::i16)
15377 bool Promote = false;
15378 bool Commute = false;
15379 switch (Op.getOpcode()) {
15382 LoadSDNode *LD = cast<LoadSDNode>(Op);
15383 // If the non-extending load has a single use and it's not live out, then it
15384 // might be folded.
15385 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15386 Op.hasOneUse()*/) {
15387 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15388 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15389 // The only case where we'd want to promote LOAD (rather then it being
15390 // promoted as an operand is when it's only use is liveout.
15391 if (UI->getOpcode() != ISD::CopyToReg)
15398 case ISD::SIGN_EXTEND:
15399 case ISD::ZERO_EXTEND:
15400 case ISD::ANY_EXTEND:
15405 SDValue N0 = Op.getOperand(0);
15406 // Look out for (store (shl (load), x)).
15407 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15420 SDValue N0 = Op.getOperand(0);
15421 SDValue N1 = Op.getOperand(1);
15422 if (!Commute && MayFoldLoad(N1))
15424 // Avoid disabling potential load folding opportunities.
15425 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15427 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15437 //===----------------------------------------------------------------------===//
15438 // X86 Inline Assembly Support
15439 //===----------------------------------------------------------------------===//
15442 // Helper to match a string separated by whitespace.
15443 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15444 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15446 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15447 StringRef piece(*args[i]);
15448 if (!s.startswith(piece)) // Check if the piece matches.
15451 s = s.substr(piece.size());
15452 StringRef::size_type pos = s.find_first_not_of(" \t");
15453 if (pos == 0) // We matched a prefix.
15461 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15464 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15465 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15467 std::string AsmStr = IA->getAsmString();
15469 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15470 if (!Ty || Ty->getBitWidth() % 16 != 0)
15473 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15474 SmallVector<StringRef, 4> AsmPieces;
15475 SplitString(AsmStr, AsmPieces, ";\n");
15477 switch (AsmPieces.size()) {
15478 default: return false;
15480 // FIXME: this should verify that we are targeting a 486 or better. If not,
15481 // we will turn this bswap into something that will be lowered to logical
15482 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15483 // lower so don't worry about this.
15485 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15486 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15487 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15488 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15489 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15490 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15491 // No need to check constraints, nothing other than the equivalent of
15492 // "=r,0" would be valid here.
15493 return IntrinsicLowering::LowerToByteSwap(CI);
15496 // rorw $$8, ${0:w} --> llvm.bswap.i16
15497 if (CI->getType()->isIntegerTy(16) &&
15498 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15499 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15500 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15502 const std::string &ConstraintsStr = IA->getConstraintString();
15503 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15504 std::sort(AsmPieces.begin(), AsmPieces.end());
15505 if (AsmPieces.size() == 4 &&
15506 AsmPieces[0] == "~{cc}" &&
15507 AsmPieces[1] == "~{dirflag}" &&
15508 AsmPieces[2] == "~{flags}" &&
15509 AsmPieces[3] == "~{fpsr}")
15510 return IntrinsicLowering::LowerToByteSwap(CI);
15514 if (CI->getType()->isIntegerTy(32) &&
15515 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15516 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15517 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15518 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15520 const std::string &ConstraintsStr = IA->getConstraintString();
15521 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15522 std::sort(AsmPieces.begin(), AsmPieces.end());
15523 if (AsmPieces.size() == 4 &&
15524 AsmPieces[0] == "~{cc}" &&
15525 AsmPieces[1] == "~{dirflag}" &&
15526 AsmPieces[2] == "~{flags}" &&
15527 AsmPieces[3] == "~{fpsr}")
15528 return IntrinsicLowering::LowerToByteSwap(CI);
15531 if (CI->getType()->isIntegerTy(64)) {
15532 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15533 if (Constraints.size() >= 2 &&
15534 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15535 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15536 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15537 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15538 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15539 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15540 return IntrinsicLowering::LowerToByteSwap(CI);
15550 /// getConstraintType - Given a constraint letter, return the type of
15551 /// constraint it is for this target.
15552 X86TargetLowering::ConstraintType
15553 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15554 if (Constraint.size() == 1) {
15555 switch (Constraint[0]) {
15566 return C_RegisterClass;
15590 return TargetLowering::getConstraintType(Constraint);
15593 /// Examine constraint type and operand type and determine a weight value.
15594 /// This object must already have been set up with the operand type
15595 /// and the current alternative constraint selected.
15596 TargetLowering::ConstraintWeight
15597 X86TargetLowering::getSingleConstraintMatchWeight(
15598 AsmOperandInfo &info, const char *constraint) const {
15599 ConstraintWeight weight = CW_Invalid;
15600 Value *CallOperandVal = info.CallOperandVal;
15601 // If we don't have a value, we can't do a match,
15602 // but allow it at the lowest weight.
15603 if (CallOperandVal == NULL)
15605 Type *type = CallOperandVal->getType();
15606 // Look at the constraint type.
15607 switch (*constraint) {
15609 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15620 if (CallOperandVal->getType()->isIntegerTy())
15621 weight = CW_SpecificReg;
15626 if (type->isFloatingPointTy())
15627 weight = CW_SpecificReg;
15630 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15631 weight = CW_SpecificReg;
15635 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15636 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15637 weight = CW_Register;
15640 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15641 if (C->getZExtValue() <= 31)
15642 weight = CW_Constant;
15646 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15647 if (C->getZExtValue() <= 63)
15648 weight = CW_Constant;
15652 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15653 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15654 weight = CW_Constant;
15658 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15659 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15660 weight = CW_Constant;
15664 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15665 if (C->getZExtValue() <= 3)
15666 weight = CW_Constant;
15670 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15671 if (C->getZExtValue() <= 0xff)
15672 weight = CW_Constant;
15677 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15678 weight = CW_Constant;
15682 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15683 if ((C->getSExtValue() >= -0x80000000LL) &&
15684 (C->getSExtValue() <= 0x7fffffffLL))
15685 weight = CW_Constant;
15689 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15690 if (C->getZExtValue() <= 0xffffffff)
15691 weight = CW_Constant;
15698 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15699 /// with another that has more specific requirements based on the type of the
15700 /// corresponding operand.
15701 const char *X86TargetLowering::
15702 LowerXConstraint(EVT ConstraintVT) const {
15703 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15704 // 'f' like normal targets.
15705 if (ConstraintVT.isFloatingPoint()) {
15706 if (Subtarget->hasSSE2())
15708 if (Subtarget->hasSSE1())
15712 return TargetLowering::LowerXConstraint(ConstraintVT);
15715 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15716 /// vector. If it is invalid, don't add anything to Ops.
15717 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15718 std::string &Constraint,
15719 std::vector<SDValue>&Ops,
15720 SelectionDAG &DAG) const {
15721 SDValue Result(0, 0);
15723 // Only support length 1 constraints for now.
15724 if (Constraint.length() > 1) return;
15726 char ConstraintLetter = Constraint[0];
15727 switch (ConstraintLetter) {
15730 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15731 if (C->getZExtValue() <= 31) {
15732 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15738 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15739 if (C->getZExtValue() <= 63) {
15740 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15747 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15748 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15754 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15755 if (C->getZExtValue() <= 255) {
15756 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15762 // 32-bit signed value
15763 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15764 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15765 C->getSExtValue())) {
15766 // Widen to 64 bits here to get it sign extended.
15767 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15770 // FIXME gcc accepts some relocatable values here too, but only in certain
15771 // memory models; it's complicated.
15776 // 32-bit unsigned value
15777 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15778 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15779 C->getZExtValue())) {
15780 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15784 // FIXME gcc accepts some relocatable values here too, but only in certain
15785 // memory models; it's complicated.
15789 // Literal immediates are always ok.
15790 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15791 // Widen to 64 bits here to get it sign extended.
15792 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15796 // In any sort of PIC mode addresses need to be computed at runtime by
15797 // adding in a register or some sort of table lookup. These can't
15798 // be used as immediates.
15799 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15802 // If we are in non-pic codegen mode, we allow the address of a global (with
15803 // an optional displacement) to be used with 'i'.
15804 GlobalAddressSDNode *GA = 0;
15805 int64_t Offset = 0;
15807 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15809 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15810 Offset += GA->getOffset();
15812 } else if (Op.getOpcode() == ISD::ADD) {
15813 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15814 Offset += C->getZExtValue();
15815 Op = Op.getOperand(0);
15818 } else if (Op.getOpcode() == ISD::SUB) {
15819 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15820 Offset += -C->getZExtValue();
15821 Op = Op.getOperand(0);
15826 // Otherwise, this isn't something we can handle, reject it.
15830 const GlobalValue *GV = GA->getGlobal();
15831 // If we require an extra load to get this address, as in PIC mode, we
15832 // can't accept it.
15833 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15834 getTargetMachine())))
15837 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15838 GA->getValueType(0), Offset);
15843 if (Result.getNode()) {
15844 Ops.push_back(Result);
15847 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15850 std::pair<unsigned, const TargetRegisterClass*>
15851 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15853 // First, see if this is a constraint that directly corresponds to an LLVM
15855 if (Constraint.size() == 1) {
15856 // GCC Constraint Letters
15857 switch (Constraint[0]) {
15859 // TODO: Slight differences here in allocation order and leaving
15860 // RIP in the class. Do they matter any more here than they do
15861 // in the normal allocation?
15862 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15863 if (Subtarget->is64Bit()) {
15864 if (VT == MVT::i32 || VT == MVT::f32)
15865 return std::make_pair(0U, &X86::GR32RegClass);
15866 if (VT == MVT::i16)
15867 return std::make_pair(0U, &X86::GR16RegClass);
15868 if (VT == MVT::i8 || VT == MVT::i1)
15869 return std::make_pair(0U, &X86::GR8RegClass);
15870 if (VT == MVT::i64 || VT == MVT::f64)
15871 return std::make_pair(0U, &X86::GR64RegClass);
15874 // 32-bit fallthrough
15875 case 'Q': // Q_REGS
15876 if (VT == MVT::i32 || VT == MVT::f32)
15877 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15878 if (VT == MVT::i16)
15879 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15880 if (VT == MVT::i8 || VT == MVT::i1)
15881 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15882 if (VT == MVT::i64)
15883 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15885 case 'r': // GENERAL_REGS
15886 case 'l': // INDEX_REGS
15887 if (VT == MVT::i8 || VT == MVT::i1)
15888 return std::make_pair(0U, &X86::GR8RegClass);
15889 if (VT == MVT::i16)
15890 return std::make_pair(0U, &X86::GR16RegClass);
15891 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15892 return std::make_pair(0U, &X86::GR32RegClass);
15893 return std::make_pair(0U, &X86::GR64RegClass);
15894 case 'R': // LEGACY_REGS
15895 if (VT == MVT::i8 || VT == MVT::i1)
15896 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15897 if (VT == MVT::i16)
15898 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15899 if (VT == MVT::i32 || !Subtarget->is64Bit())
15900 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15901 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15902 case 'f': // FP Stack registers.
15903 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15904 // value to the correct fpstack register class.
15905 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15906 return std::make_pair(0U, &X86::RFP32RegClass);
15907 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15908 return std::make_pair(0U, &X86::RFP64RegClass);
15909 return std::make_pair(0U, &X86::RFP80RegClass);
15910 case 'y': // MMX_REGS if MMX allowed.
15911 if (!Subtarget->hasMMX()) break;
15912 return std::make_pair(0U, &X86::VR64RegClass);
15913 case 'Y': // SSE_REGS if SSE2 allowed
15914 if (!Subtarget->hasSSE2()) break;
15916 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15917 if (!Subtarget->hasSSE1()) break;
15919 switch (VT.getSimpleVT().SimpleTy) {
15921 // Scalar SSE types.
15924 return std::make_pair(0U, &X86::FR32RegClass);
15927 return std::make_pair(0U, &X86::FR64RegClass);
15935 return std::make_pair(0U, &X86::VR128RegClass);
15943 return std::make_pair(0U, &X86::VR256RegClass);
15949 // Use the default implementation in TargetLowering to convert the register
15950 // constraint into a member of a register class.
15951 std::pair<unsigned, const TargetRegisterClass*> Res;
15952 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15954 // Not found as a standard register?
15955 if (Res.second == 0) {
15956 // Map st(0) -> st(7) -> ST0
15957 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15958 tolower(Constraint[1]) == 's' &&
15959 tolower(Constraint[2]) == 't' &&
15960 Constraint[3] == '(' &&
15961 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15962 Constraint[5] == ')' &&
15963 Constraint[6] == '}') {
15965 Res.first = X86::ST0+Constraint[4]-'0';
15966 Res.second = &X86::RFP80RegClass;
15970 // GCC allows "st(0)" to be called just plain "st".
15971 if (StringRef("{st}").equals_lower(Constraint)) {
15972 Res.first = X86::ST0;
15973 Res.second = &X86::RFP80RegClass;
15978 if (StringRef("{flags}").equals_lower(Constraint)) {
15979 Res.first = X86::EFLAGS;
15980 Res.second = &X86::CCRRegClass;
15984 // 'A' means EAX + EDX.
15985 if (Constraint == "A") {
15986 Res.first = X86::EAX;
15987 Res.second = &X86::GR32_ADRegClass;
15993 // Otherwise, check to see if this is a register class of the wrong value
15994 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15995 // turn into {ax},{dx}.
15996 if (Res.second->hasType(VT))
15997 return Res; // Correct type already, nothing to do.
15999 // All of the single-register GCC register classes map their values onto
16000 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
16001 // really want an 8-bit or 32-bit register, map to the appropriate register
16002 // class and return the appropriate register.
16003 if (Res.second == &X86::GR16RegClass) {
16004 if (VT == MVT::i8) {
16005 unsigned DestReg = 0;
16006 switch (Res.first) {
16008 case X86::AX: DestReg = X86::AL; break;
16009 case X86::DX: DestReg = X86::DL; break;
16010 case X86::CX: DestReg = X86::CL; break;
16011 case X86::BX: DestReg = X86::BL; break;
16014 Res.first = DestReg;
16015 Res.second = &X86::GR8RegClass;
16017 } else if (VT == MVT::i32) {
16018 unsigned DestReg = 0;
16019 switch (Res.first) {
16021 case X86::AX: DestReg = X86::EAX; break;
16022 case X86::DX: DestReg = X86::EDX; break;
16023 case X86::CX: DestReg = X86::ECX; break;
16024 case X86::BX: DestReg = X86::EBX; break;
16025 case X86::SI: DestReg = X86::ESI; break;
16026 case X86::DI: DestReg = X86::EDI; break;
16027 case X86::BP: DestReg = X86::EBP; break;
16028 case X86::SP: DestReg = X86::ESP; break;
16031 Res.first = DestReg;
16032 Res.second = &X86::GR32RegClass;
16034 } else if (VT == MVT::i64) {
16035 unsigned DestReg = 0;
16036 switch (Res.first) {
16038 case X86::AX: DestReg = X86::RAX; break;
16039 case X86::DX: DestReg = X86::RDX; break;
16040 case X86::CX: DestReg = X86::RCX; break;
16041 case X86::BX: DestReg = X86::RBX; break;
16042 case X86::SI: DestReg = X86::RSI; break;
16043 case X86::DI: DestReg = X86::RDI; break;
16044 case X86::BP: DestReg = X86::RBP; break;
16045 case X86::SP: DestReg = X86::RSP; break;
16048 Res.first = DestReg;
16049 Res.second = &X86::GR64RegClass;
16052 } else if (Res.second == &X86::FR32RegClass ||
16053 Res.second == &X86::FR64RegClass ||
16054 Res.second == &X86::VR128RegClass) {
16055 // Handle references to XMM physical registers that got mapped into the
16056 // wrong class. This can happen with constraints like {xmm0} where the
16057 // target independent register mapper will just pick the first match it can
16058 // find, ignoring the required type.
16059 if (VT == MVT::f32)
16060 Res.second = &X86::FR32RegClass;
16061 else if (VT == MVT::f64)
16062 Res.second = &X86::FR64RegClass;
16063 else if (X86::VR128RegClass.hasType(VT))
16064 Res.second = &X86::VR128RegClass;