1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::PSHUFB:
3543 case X86ISD::PSHUFD:
3544 case X86ISD::PSHUFHW:
3545 case X86ISD::PSHUFLW:
3547 case X86ISD::PALIGNR:
3548 case X86ISD::MOVLHPS:
3549 case X86ISD::MOVLHPD:
3550 case X86ISD::MOVHLPS:
3551 case X86ISD::MOVLPS:
3552 case X86ISD::MOVLPD:
3553 case X86ISD::MOVSHDUP:
3554 case X86ISD::MOVSLDUP:
3555 case X86ISD::MOVDDUP:
3558 case X86ISD::UNPCKL:
3559 case X86ISD::UNPCKH:
3560 case X86ISD::VPERMILPI:
3561 case X86ISD::VPERM2X128:
3562 case X86ISD::VPERMI:
3567 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3568 SDValue V1, SelectionDAG &DAG) {
3570 default: llvm_unreachable("Unknown x86 shuffle node");
3571 case X86ISD::MOVSHDUP:
3572 case X86ISD::MOVSLDUP:
3573 case X86ISD::MOVDDUP:
3574 return DAG.getNode(Opc, dl, VT, V1);
3578 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3579 SDValue V1, unsigned TargetMask,
3580 SelectionDAG &DAG) {
3582 default: llvm_unreachable("Unknown x86 shuffle node");
3583 case X86ISD::PSHUFD:
3584 case X86ISD::PSHUFHW:
3585 case X86ISD::PSHUFLW:
3586 case X86ISD::VPERMILPI:
3587 case X86ISD::VPERMI:
3588 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3592 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3593 SDValue V1, SDValue V2, unsigned TargetMask,
3594 SelectionDAG &DAG) {
3596 default: llvm_unreachable("Unknown x86 shuffle node");
3597 case X86ISD::PALIGNR:
3598 case X86ISD::VALIGN:
3600 case X86ISD::VPERM2X128:
3601 return DAG.getNode(Opc, dl, VT, V1, V2,
3602 DAG.getConstant(TargetMask, MVT::i8));
3606 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3607 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3609 default: llvm_unreachable("Unknown x86 shuffle node");
3610 case X86ISD::MOVLHPS:
3611 case X86ISD::MOVLHPD:
3612 case X86ISD::MOVHLPS:
3613 case X86ISD::MOVLPS:
3614 case X86ISD::MOVLPD:
3617 case X86ISD::UNPCKL:
3618 case X86ISD::UNPCKH:
3619 return DAG.getNode(Opc, dl, VT, V1, V2);
3623 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3624 MachineFunction &MF = DAG.getMachineFunction();
3625 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3626 DAG.getSubtarget().getRegisterInfo());
3627 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3628 int ReturnAddrIndex = FuncInfo->getRAIndex();
3630 if (ReturnAddrIndex == 0) {
3631 // Set up a frame object for the return address.
3632 unsigned SlotSize = RegInfo->getSlotSize();
3633 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3636 FuncInfo->setRAIndex(ReturnAddrIndex);
3639 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3642 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3643 bool hasSymbolicDisplacement) {
3644 // Offset should fit into 32 bit immediate field.
3645 if (!isInt<32>(Offset))
3648 // If we don't have a symbolic displacement - we don't have any extra
3650 if (!hasSymbolicDisplacement)
3653 // FIXME: Some tweaks might be needed for medium code model.
3654 if (M != CodeModel::Small && M != CodeModel::Kernel)
3657 // For small code model we assume that latest object is 16MB before end of 31
3658 // bits boundary. We may also accept pretty large negative constants knowing
3659 // that all objects are in the positive half of address space.
3660 if (M == CodeModel::Small && Offset < 16*1024*1024)
3663 // For kernel code model we know that all object resist in the negative half
3664 // of 32bits address space. We may not accept negative offsets, since they may
3665 // be just off and we may accept pretty large positive ones.
3666 if (M == CodeModel::Kernel && Offset > 0)
3672 /// isCalleePop - Determines whether the callee is required to pop its
3673 /// own arguments. Callee pop is necessary to support tail calls.
3674 bool X86::isCalleePop(CallingConv::ID CallingConv,
3675 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3676 switch (CallingConv) {
3679 case CallingConv::X86_StdCall:
3680 case CallingConv::X86_FastCall:
3681 case CallingConv::X86_ThisCall:
3683 case CallingConv::Fast:
3684 case CallingConv::GHC:
3685 case CallingConv::HiPE:
3692 /// \brief Return true if the condition is an unsigned comparison operation.
3693 static bool isX86CCUnsigned(unsigned X86CC) {
3695 default: llvm_unreachable("Invalid integer condition!");
3696 case X86::COND_E: return true;
3697 case X86::COND_G: return false;
3698 case X86::COND_GE: return false;
3699 case X86::COND_L: return false;
3700 case X86::COND_LE: return false;
3701 case X86::COND_NE: return true;
3702 case X86::COND_B: return true;
3703 case X86::COND_A: return true;
3704 case X86::COND_BE: return true;
3705 case X86::COND_AE: return true;
3707 llvm_unreachable("covered switch fell through?!");
3710 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3711 /// specific condition code, returning the condition code and the LHS/RHS of the
3712 /// comparison to make.
3713 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3714 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3717 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3718 // X > -1 -> X == 0, jump !sign.
3719 RHS = DAG.getConstant(0, RHS.getValueType());
3720 return X86::COND_NS;
3722 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3723 // X < 0 -> X == 0, jump on sign.
3726 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3728 RHS = DAG.getConstant(0, RHS.getValueType());
3729 return X86::COND_LE;
3733 switch (SetCCOpcode) {
3734 default: llvm_unreachable("Invalid integer condition!");
3735 case ISD::SETEQ: return X86::COND_E;
3736 case ISD::SETGT: return X86::COND_G;
3737 case ISD::SETGE: return X86::COND_GE;
3738 case ISD::SETLT: return X86::COND_L;
3739 case ISD::SETLE: return X86::COND_LE;
3740 case ISD::SETNE: return X86::COND_NE;
3741 case ISD::SETULT: return X86::COND_B;
3742 case ISD::SETUGT: return X86::COND_A;
3743 case ISD::SETULE: return X86::COND_BE;
3744 case ISD::SETUGE: return X86::COND_AE;
3748 // First determine if it is required or is profitable to flip the operands.
3750 // If LHS is a foldable load, but RHS is not, flip the condition.
3751 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3752 !ISD::isNON_EXTLoad(RHS.getNode())) {
3753 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3754 std::swap(LHS, RHS);
3757 switch (SetCCOpcode) {
3763 std::swap(LHS, RHS);
3767 // On a floating point condition, the flags are set as follows:
3769 // 0 | 0 | 0 | X > Y
3770 // 0 | 0 | 1 | X < Y
3771 // 1 | 0 | 0 | X == Y
3772 // 1 | 1 | 1 | unordered
3773 switch (SetCCOpcode) {
3774 default: llvm_unreachable("Condcode should be pre-legalized away");
3776 case ISD::SETEQ: return X86::COND_E;
3777 case ISD::SETOLT: // flipped
3779 case ISD::SETGT: return X86::COND_A;
3780 case ISD::SETOLE: // flipped
3782 case ISD::SETGE: return X86::COND_AE;
3783 case ISD::SETUGT: // flipped
3785 case ISD::SETLT: return X86::COND_B;
3786 case ISD::SETUGE: // flipped
3788 case ISD::SETLE: return X86::COND_BE;
3790 case ISD::SETNE: return X86::COND_NE;
3791 case ISD::SETUO: return X86::COND_P;
3792 case ISD::SETO: return X86::COND_NP;
3794 case ISD::SETUNE: return X86::COND_INVALID;
3798 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3799 /// code. Current x86 isa includes the following FP cmov instructions:
3800 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3801 static bool hasFPCMov(unsigned X86CC) {
3817 /// isFPImmLegal - Returns true if the target can instruction select the
3818 /// specified FP immediate natively. If false, the legalizer will
3819 /// materialize the FP immediate as a load from a constant pool.
3820 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3821 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3822 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3828 /// \brief Returns true if it is beneficial to convert a load of a constant
3829 /// to just the constant itself.
3830 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3832 assert(Ty->isIntegerTy());
3834 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3835 if (BitSize == 0 || BitSize > 64)
3840 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3841 /// the specified range (L, H].
3842 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3843 return (Val < 0) || (Val >= Low && Val < Hi);
3846 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3847 /// specified value.
3848 static bool isUndefOrEqual(int Val, int CmpVal) {
3849 return (Val < 0 || Val == CmpVal);
3852 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3853 /// from position Pos and ending in Pos+Size, falls within the specified
3854 /// sequential range (L, L+Pos]. or is undef.
3855 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3856 unsigned Pos, unsigned Size, int Low) {
3857 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3858 if (!isUndefOrEqual(Mask[i], Low))
3863 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3864 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3865 /// the second operand.
3866 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3867 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3868 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3869 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3870 return (Mask[0] < 2 && Mask[1] < 2);
3874 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3875 /// is suitable for input to PSHUFHW.
3876 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3877 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3880 // Lower quadword copied in order or undef.
3881 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3884 // Upper quadword shuffled.
3885 for (unsigned i = 4; i != 8; ++i)
3886 if (!isUndefOrInRange(Mask[i], 4, 8))
3889 if (VT == MVT::v16i16) {
3890 // Lower quadword copied in order or undef.
3891 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3894 // Upper quadword shuffled.
3895 for (unsigned i = 12; i != 16; ++i)
3896 if (!isUndefOrInRange(Mask[i], 12, 16))
3903 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3904 /// is suitable for input to PSHUFLW.
3905 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3906 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3909 // Upper quadword copied in order.
3910 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3913 // Lower quadword shuffled.
3914 for (unsigned i = 0; i != 4; ++i)
3915 if (!isUndefOrInRange(Mask[i], 0, 4))
3918 if (VT == MVT::v16i16) {
3919 // Upper quadword copied in order.
3920 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3923 // Lower quadword shuffled.
3924 for (unsigned i = 8; i != 12; ++i)
3925 if (!isUndefOrInRange(Mask[i], 8, 12))
3932 /// \brief Return true if the mask specifies a shuffle of elements that is
3933 /// suitable for input to intralane (palignr) or interlane (valign) vector
3935 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3936 unsigned NumElts = VT.getVectorNumElements();
3937 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3938 unsigned NumLaneElts = NumElts/NumLanes;
3940 // Do not handle 64-bit element shuffles with palignr.
3941 if (NumLaneElts == 2)
3944 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3946 for (i = 0; i != NumLaneElts; ++i) {
3951 // Lane is all undef, go to next lane
3952 if (i == NumLaneElts)
3955 int Start = Mask[i+l];
3957 // Make sure its in this lane in one of the sources
3958 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3959 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3962 // If not lane 0, then we must match lane 0
3963 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3966 // Correct second source to be contiguous with first source
3967 if (Start >= (int)NumElts)
3968 Start -= NumElts - NumLaneElts;
3970 // Make sure we're shifting in the right direction.
3971 if (Start <= (int)(i+l))
3976 // Check the rest of the elements to see if they are consecutive.
3977 for (++i; i != NumLaneElts; ++i) {
3978 int Idx = Mask[i+l];
3980 // Make sure its in this lane
3981 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3982 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3985 // If not lane 0, then we must match lane 0
3986 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3989 if (Idx >= (int)NumElts)
3990 Idx -= NumElts - NumLaneElts;
3992 if (!isUndefOrEqual(Idx, Start+i))
4001 /// \brief Return true if the node specifies a shuffle of elements that is
4002 /// suitable for input to PALIGNR.
4003 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4004 const X86Subtarget *Subtarget) {
4005 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4006 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4007 VT.is512BitVector())
4008 // FIXME: Add AVX512BW.
4011 return isAlignrMask(Mask, VT, false);
4014 /// \brief Return true if the node specifies a shuffle of elements that is
4015 /// suitable for input to VALIGN.
4016 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4017 const X86Subtarget *Subtarget) {
4018 // FIXME: Add AVX512VL.
4019 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4021 return isAlignrMask(Mask, VT, true);
4024 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4025 /// the two vector operands have swapped position.
4026 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4027 unsigned NumElems) {
4028 for (unsigned i = 0; i != NumElems; ++i) {
4032 else if (idx < (int)NumElems)
4033 Mask[i] = idx + NumElems;
4035 Mask[i] = idx - NumElems;
4039 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4040 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4041 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4042 /// reverse of what x86 shuffles want.
4043 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4045 unsigned NumElems = VT.getVectorNumElements();
4046 unsigned NumLanes = VT.getSizeInBits()/128;
4047 unsigned NumLaneElems = NumElems/NumLanes;
4049 if (NumLaneElems != 2 && NumLaneElems != 4)
4052 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4053 bool symetricMaskRequired =
4054 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4056 // VSHUFPSY divides the resulting vector into 4 chunks.
4057 // The sources are also splitted into 4 chunks, and each destination
4058 // chunk must come from a different source chunk.
4060 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4061 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4063 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4064 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4066 // VSHUFPDY divides the resulting vector into 4 chunks.
4067 // The sources are also splitted into 4 chunks, and each destination
4068 // chunk must come from a different source chunk.
4070 // SRC1 => X3 X2 X1 X0
4071 // SRC2 => Y3 Y2 Y1 Y0
4073 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4075 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4076 unsigned HalfLaneElems = NumLaneElems/2;
4077 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4078 for (unsigned i = 0; i != NumLaneElems; ++i) {
4079 int Idx = Mask[i+l];
4080 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4081 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4083 // For VSHUFPSY, the mask of the second half must be the same as the
4084 // first but with the appropriate offsets. This works in the same way as
4085 // VPERMILPS works with masks.
4086 if (!symetricMaskRequired || Idx < 0)
4088 if (MaskVal[i] < 0) {
4089 MaskVal[i] = Idx - l;
4092 if ((signed)(Idx - l) != MaskVal[i])
4100 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4101 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4102 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4103 if (!VT.is128BitVector())
4106 unsigned NumElems = VT.getVectorNumElements();
4111 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4112 return isUndefOrEqual(Mask[0], 6) &&
4113 isUndefOrEqual(Mask[1], 7) &&
4114 isUndefOrEqual(Mask[2], 2) &&
4115 isUndefOrEqual(Mask[3], 3);
4118 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4119 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4121 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4122 if (!VT.is128BitVector())
4125 unsigned NumElems = VT.getVectorNumElements();
4130 return isUndefOrEqual(Mask[0], 2) &&
4131 isUndefOrEqual(Mask[1], 3) &&
4132 isUndefOrEqual(Mask[2], 2) &&
4133 isUndefOrEqual(Mask[3], 3);
4136 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4137 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4138 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4139 if (!VT.is128BitVector())
4142 unsigned NumElems = VT.getVectorNumElements();
4144 if (NumElems != 2 && NumElems != 4)
4147 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4148 if (!isUndefOrEqual(Mask[i], i + NumElems))
4151 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4152 if (!isUndefOrEqual(Mask[i], i))
4158 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4160 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4166 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i))
4173 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4180 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4181 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4182 /// i. e: If all but one element come from the same vector.
4183 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4184 // TODO: Deal with AVX's VINSERTPS
4185 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4188 unsigned CorrectPosV1 = 0;
4189 unsigned CorrectPosV2 = 0;
4190 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4191 if (Mask[i] == -1) {
4199 else if (Mask[i] == i + 4)
4203 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4204 // We have 3 elements (undefs count as elements from any vector) from one
4205 // vector, and one from another.
4212 // Some special combinations that can be optimized.
4215 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4216 SelectionDAG &DAG) {
4217 MVT VT = SVOp->getSimpleValueType(0);
4220 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4223 ArrayRef<int> Mask = SVOp->getMask();
4225 // These are the special masks that may be optimized.
4226 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4227 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4228 bool MatchEvenMask = true;
4229 bool MatchOddMask = true;
4230 for (int i=0; i<8; ++i) {
4231 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4232 MatchEvenMask = false;
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4234 MatchOddMask = false;
4237 if (!MatchEvenMask && !MatchOddMask)
4240 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4242 SDValue Op0 = SVOp->getOperand(0);
4243 SDValue Op1 = SVOp->getOperand(1);
4245 if (MatchEvenMask) {
4246 // Shift the second operand right to 32 bits.
4247 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4248 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4250 // Shift the first operand left to 32 bits.
4251 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4252 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4254 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4255 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4258 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4259 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4260 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4261 bool HasInt256, bool V2IsSplat = false) {
4263 assert(VT.getSizeInBits() >= 128 &&
4264 "Unsupported vector type for unpckl");
4266 unsigned NumElts = VT.getVectorNumElements();
4267 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4268 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4272 "Unsupported vector type for unpckh");
4274 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4275 unsigned NumLanes = VT.getSizeInBits()/128;
4276 unsigned NumLaneElts = NumElts/NumLanes;
4278 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4279 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4280 int BitI = Mask[l+i];
4281 int BitI1 = Mask[l+i+1];
4282 if (!isUndefOrEqual(BitI, j))
4285 if (!isUndefOrEqual(BitI1, NumElts))
4288 if (!isUndefOrEqual(BitI1, j + NumElts))
4297 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4298 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4299 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4300 bool HasInt256, bool V2IsSplat = false) {
4301 assert(VT.getSizeInBits() >= 128 &&
4302 "Unsupported vector type for unpckh");
4304 unsigned NumElts = VT.getVectorNumElements();
4305 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4306 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4309 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4310 "Unsupported vector type for unpckh");
4312 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4313 unsigned NumLanes = VT.getSizeInBits()/128;
4314 unsigned NumLaneElts = NumElts/NumLanes;
4316 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4317 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4318 int BitI = Mask[l+i];
4319 int BitI1 = Mask[l+i+1];
4320 if (!isUndefOrEqual(BitI, j))
4323 if (isUndefOrEqual(BitI1, NumElts))
4326 if (!isUndefOrEqual(BitI1, j+NumElts))
4334 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4335 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4337 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4338 unsigned NumElts = VT.getVectorNumElements();
4339 bool Is256BitVec = VT.is256BitVector();
4341 if (VT.is512BitVector())
4343 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4344 "Unsupported vector type for unpckh");
4346 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4347 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4350 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4351 // FIXME: Need a better way to get rid of this, there's no latency difference
4352 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4353 // the former later. We should also remove the "_undef" special mask.
4354 if (NumElts == 4 && Is256BitVec)
4357 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4358 // independently on 128-bit lanes.
4359 unsigned NumLanes = VT.getSizeInBits()/128;
4360 unsigned NumLaneElts = NumElts/NumLanes;
4362 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4363 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4364 int BitI = Mask[l+i];
4365 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4369 if (!isUndefOrEqual(BitI1, j))
4377 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4378 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4380 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4381 unsigned NumElts = VT.getVectorNumElements();
4383 if (VT.is512BitVector())
4386 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4387 "Unsupported vector type for unpckh");
4389 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4390 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4393 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4394 // independently on 128-bit lanes.
4395 unsigned NumLanes = VT.getSizeInBits()/128;
4396 unsigned NumLaneElts = NumElts/NumLanes;
4398 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4399 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4400 int BitI = Mask[l+i];
4401 int BitI1 = Mask[l+i+1];
4402 if (!isUndefOrEqual(BitI, j))
4404 if (!isUndefOrEqual(BitI1, j))
4411 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4412 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4413 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4414 if (!VT.is512BitVector())
4417 unsigned NumElts = VT.getVectorNumElements();
4418 unsigned HalfSize = NumElts/2;
4419 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4420 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4425 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4434 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4435 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4436 /// MOVSD, and MOVD, i.e. setting the lowest element.
4437 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4438 if (VT.getVectorElementType().getSizeInBits() < 32)
4440 if (!VT.is128BitVector())
4443 unsigned NumElts = VT.getVectorNumElements();
4445 if (!isUndefOrEqual(Mask[0], NumElts))
4448 for (unsigned i = 1; i != NumElts; ++i)
4449 if (!isUndefOrEqual(Mask[i], i))
4455 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4456 /// as permutations between 128-bit chunks or halves. As an example: this
4458 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4459 /// The first half comes from the second half of V1 and the second half from the
4460 /// the second half of V2.
4461 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4462 if (!HasFp256 || !VT.is256BitVector())
4465 // The shuffle result is divided into half A and half B. In total the two
4466 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4467 // B must come from C, D, E or F.
4468 unsigned HalfSize = VT.getVectorNumElements()/2;
4469 bool MatchA = false, MatchB = false;
4471 // Check if A comes from one of C, D, E, F.
4472 for (unsigned Half = 0; Half != 4; ++Half) {
4473 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4479 // Check if B comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4487 return MatchA && MatchB;
4490 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4491 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4492 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4493 MVT VT = SVOp->getSimpleValueType(0);
4495 unsigned HalfSize = VT.getVectorNumElements()/2;
4497 unsigned FstHalf = 0, SndHalf = 0;
4498 for (unsigned i = 0; i < HalfSize; ++i) {
4499 if (SVOp->getMaskElt(i) > 0) {
4500 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4504 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4505 if (SVOp->getMaskElt(i) > 0) {
4506 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4511 return (FstHalf | (SndHalf << 4));
4514 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4515 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4516 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4520 unsigned NumElts = VT.getVectorNumElements();
4522 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4523 for (unsigned i = 0; i != NumElts; ++i) {
4526 Imm8 |= Mask[i] << (i*2);
4531 unsigned LaneSize = 4;
4532 SmallVector<int, 4> MaskVal(LaneSize, -1);
4534 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4535 for (unsigned i = 0; i != LaneSize; ++i) {
4536 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4540 if (MaskVal[i] < 0) {
4541 MaskVal[i] = Mask[i+l] - l;
4542 Imm8 |= MaskVal[i] << (i*2);
4545 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4552 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4553 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4554 /// Note that VPERMIL mask matching is different depending whether theunderlying
4555 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4556 /// to the same elements of the low, but to the higher half of the source.
4557 /// In VPERMILPD the two lanes could be shuffled independently of each other
4558 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4559 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4560 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4561 if (VT.getSizeInBits() < 256 || EltSize < 32)
4563 bool symetricMaskRequired = (EltSize == 32);
4564 unsigned NumElts = VT.getVectorNumElements();
4566 unsigned NumLanes = VT.getSizeInBits()/128;
4567 unsigned LaneSize = NumElts/NumLanes;
4568 // 2 or 4 elements in one lane
4570 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4571 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4572 for (unsigned i = 0; i != LaneSize; ++i) {
4573 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4575 if (symetricMaskRequired) {
4576 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4577 ExpectedMaskVal[i] = Mask[i+l] - l;
4580 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4588 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4589 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4590 /// element of vector 2 and the other elements to come from vector 1 in order.
4591 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4592 bool V2IsSplat = false, bool V2IsUndef = false) {
4593 if (!VT.is128BitVector())
4596 unsigned NumOps = VT.getVectorNumElements();
4597 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4600 if (!isUndefOrEqual(Mask[0], 0))
4603 for (unsigned i = 1; i != NumOps; ++i)
4604 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4605 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4606 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4612 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4613 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4614 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4615 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4616 const X86Subtarget *Subtarget) {
4617 if (!Subtarget->hasSSE3())
4620 unsigned NumElems = VT.getVectorNumElements();
4622 if ((VT.is128BitVector() && NumElems != 4) ||
4623 (VT.is256BitVector() && NumElems != 8) ||
4624 (VT.is512BitVector() && NumElems != 16))
4627 // "i+1" is the value the indexed mask element must have
4628 for (unsigned i = 0; i != NumElems; i += 2)
4629 if (!isUndefOrEqual(Mask[i], i+1) ||
4630 !isUndefOrEqual(Mask[i+1], i+1))
4636 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4637 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4638 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4639 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4640 const X86Subtarget *Subtarget) {
4641 if (!Subtarget->hasSSE3())
4644 unsigned NumElems = VT.getVectorNumElements();
4646 if ((VT.is128BitVector() && NumElems != 4) ||
4647 (VT.is256BitVector() && NumElems != 8) ||
4648 (VT.is512BitVector() && NumElems != 16))
4651 // "i" is the value the indexed mask element must have
4652 for (unsigned i = 0; i != NumElems; i += 2)
4653 if (!isUndefOrEqual(Mask[i], i) ||
4654 !isUndefOrEqual(Mask[i+1], i))
4660 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4661 /// specifies a shuffle of elements that is suitable for input to 256-bit
4662 /// version of MOVDDUP.
4663 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4664 if (!HasFp256 || !VT.is256BitVector())
4667 unsigned NumElts = VT.getVectorNumElements();
4671 for (unsigned i = 0; i != NumElts/2; ++i)
4672 if (!isUndefOrEqual(Mask[i], 0))
4674 for (unsigned i = NumElts/2; i != NumElts; ++i)
4675 if (!isUndefOrEqual(Mask[i], NumElts/2))
4680 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4681 /// specifies a shuffle of elements that is suitable for input to 128-bit
4682 /// version of MOVDDUP.
4683 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4684 if (!VT.is128BitVector())
4687 unsigned e = VT.getVectorNumElements() / 2;
4688 for (unsigned i = 0; i != e; ++i)
4689 if (!isUndefOrEqual(Mask[i], i))
4691 for (unsigned i = 0; i != e; ++i)
4692 if (!isUndefOrEqual(Mask[e+i], i))
4697 /// isVEXTRACTIndex - Return true if the specified
4698 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4699 /// suitable for instruction that extract 128 or 256 bit vectors
4700 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4701 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4702 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4705 // The index should be aligned on a vecWidth-bit boundary.
4707 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4709 MVT VT = N->getSimpleValueType(0);
4710 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4711 bool Result = (Index * ElSize) % vecWidth == 0;
4716 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4717 /// operand specifies a subvector insert that is suitable for input to
4718 /// insertion of 128 or 256-bit subvectors
4719 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4720 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4721 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 // The index should be aligned on a vecWidth-bit boundary.
4725 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4727 MVT VT = N->getSimpleValueType(0);
4728 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4729 bool Result = (Index * ElSize) % vecWidth == 0;
4734 bool X86::isVINSERT128Index(SDNode *N) {
4735 return isVINSERTIndex(N, 128);
4738 bool X86::isVINSERT256Index(SDNode *N) {
4739 return isVINSERTIndex(N, 256);
4742 bool X86::isVEXTRACT128Index(SDNode *N) {
4743 return isVEXTRACTIndex(N, 128);
4746 bool X86::isVEXTRACT256Index(SDNode *N) {
4747 return isVEXTRACTIndex(N, 256);
4750 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4751 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4752 /// Handles 128-bit and 256-bit.
4753 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4754 MVT VT = N->getSimpleValueType(0);
4756 assert((VT.getSizeInBits() >= 128) &&
4757 "Unsupported vector type for PSHUF/SHUFP");
4759 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4760 // independently on 128-bit lanes.
4761 unsigned NumElts = VT.getVectorNumElements();
4762 unsigned NumLanes = VT.getSizeInBits()/128;
4763 unsigned NumLaneElts = NumElts/NumLanes;
4765 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4766 "Only supports 2, 4 or 8 elements per lane");
4768 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4770 for (unsigned i = 0; i != NumElts; ++i) {
4771 int Elt = N->getMaskElt(i);
4772 if (Elt < 0) continue;
4773 Elt &= NumLaneElts - 1;
4774 unsigned ShAmt = (i << Shift) % 8;
4775 Mask |= Elt << ShAmt;
4781 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4782 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4783 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4784 MVT VT = N->getSimpleValueType(0);
4786 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4787 "Unsupported vector type for PSHUFHW");
4789 unsigned NumElts = VT.getVectorNumElements();
4792 for (unsigned l = 0; l != NumElts; l += 8) {
4793 // 8 nodes per lane, but we only care about the last 4.
4794 for (unsigned i = 0; i < 4; ++i) {
4795 int Elt = N->getMaskElt(l+i+4);
4796 if (Elt < 0) continue;
4797 Elt &= 0x3; // only 2-bits.
4798 Mask |= Elt << (i * 2);
4805 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4806 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4807 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4808 MVT VT = N->getSimpleValueType(0);
4810 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4811 "Unsupported vector type for PSHUFHW");
4813 unsigned NumElts = VT.getVectorNumElements();
4816 for (unsigned l = 0; l != NumElts; l += 8) {
4817 // 8 nodes per lane, but we only care about the first 4.
4818 for (unsigned i = 0; i < 4; ++i) {
4819 int Elt = N->getMaskElt(l+i);
4820 if (Elt < 0) continue;
4821 Elt &= 0x3; // only 2-bits
4822 Mask |= Elt << (i * 2);
4829 /// \brief Return the appropriate immediate to shuffle the specified
4830 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4831 /// VALIGN (if Interlane is true) instructions.
4832 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4834 MVT VT = SVOp->getSimpleValueType(0);
4835 unsigned EltSize = InterLane ? 1 :
4836 VT.getVectorElementType().getSizeInBits() >> 3;
4838 unsigned NumElts = VT.getVectorNumElements();
4839 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4840 unsigned NumLaneElts = NumElts/NumLanes;
4844 for (i = 0; i != NumElts; ++i) {
4845 Val = SVOp->getMaskElt(i);
4849 if (Val >= (int)NumElts)
4850 Val -= NumElts - NumLaneElts;
4852 assert(Val - i > 0 && "PALIGNR imm should be positive");
4853 return (Val - i) * EltSize;
4856 /// \brief Return the appropriate immediate to shuffle the specified
4857 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4858 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4859 return getShuffleAlignrImmediate(SVOp, false);
4862 /// \brief Return the appropriate immediate to shuffle the specified
4863 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4864 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4865 return getShuffleAlignrImmediate(SVOp, true);
4869 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4870 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4871 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4872 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4875 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4877 MVT VecVT = N->getOperand(0).getSimpleValueType();
4878 MVT ElVT = VecVT.getVectorElementType();
4880 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4881 return Index / NumElemsPerChunk;
4884 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4887 llvm_unreachable("Illegal insert subvector for VINSERT");
4890 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4892 MVT VecVT = N->getSimpleValueType(0);
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4900 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4901 /// and VINSERTI128 instructions.
4902 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4903 return getExtractVEXTRACTImmediate(N, 128);
4906 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4908 /// and VINSERTI64x4 instructions.
4909 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 256);
4913 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4914 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4915 /// and VINSERTI128 instructions.
4916 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4917 return getInsertVINSERTImmediate(N, 128);
4920 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4922 /// and VINSERTI64x4 instructions.
4923 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 256);
4927 /// isZero - Returns true if Elt is a constant integer zero
4928 static bool isZero(SDValue V) {
4929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4930 return C && C->isNullValue();
4933 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4935 bool X86::isZeroNode(SDValue Elt) {
4938 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4939 return CFP->getValueAPF().isPosZero();
4943 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4944 /// match movhlps. The lower half elements should come from upper half of
4945 /// V1 (and in order), and the upper half elements should come from the upper
4946 /// half of V2 (and in order).
4947 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4948 if (!VT.is128BitVector())
4950 if (VT.getVectorNumElements() != 4)
4952 for (unsigned i = 0, e = 2; i != e; ++i)
4953 if (!isUndefOrEqual(Mask[i], i+2))
4955 for (unsigned i = 2; i != 4; ++i)
4956 if (!isUndefOrEqual(Mask[i], i+4))
4961 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4962 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4964 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4965 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4967 N = N->getOperand(0).getNode();
4968 if (!ISD::isNON_EXTLoad(N))
4971 *LD = cast<LoadSDNode>(N);
4975 // Test whether the given value is a vector value which will be legalized
4977 static bool WillBeConstantPoolLoad(SDNode *N) {
4978 if (N->getOpcode() != ISD::BUILD_VECTOR)
4981 // Check for any non-constant elements.
4982 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4983 switch (N->getOperand(i).getNode()->getOpcode()) {
4985 case ISD::ConstantFP:
4992 // Vectors of all-zeros and all-ones are materialized with special
4993 // instructions rather than being loaded.
4994 return !ISD::isBuildVectorAllZeros(N) &&
4995 !ISD::isBuildVectorAllOnes(N);
4998 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4999 /// match movlp{s|d}. The lower half elements should come from lower half of
5000 /// V1 (and in order), and the upper half elements should come from the upper
5001 /// half of V2 (and in order). And since V1 will become the source of the
5002 /// MOVLP, it must be either a vector load or a scalar load to vector.
5003 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5004 ArrayRef<int> Mask, MVT VT) {
5005 if (!VT.is128BitVector())
5008 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5010 // Is V2 is a vector load, don't do this transformation. We will try to use
5011 // load folding shufps op.
5012 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5015 unsigned NumElems = VT.getVectorNumElements();
5017 if (NumElems != 2 && NumElems != 4)
5019 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5020 if (!isUndefOrEqual(Mask[i], i))
5022 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5023 if (!isUndefOrEqual(Mask[i], i+NumElems))
5028 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5029 /// to an zero vector.
5030 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5031 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5032 SDValue V1 = N->getOperand(0);
5033 SDValue V2 = N->getOperand(1);
5034 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5035 for (unsigned i = 0; i != NumElems; ++i) {
5036 int Idx = N->getMaskElt(i);
5037 if (Idx >= (int)NumElems) {
5038 unsigned Opc = V2.getOpcode();
5039 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5041 if (Opc != ISD::BUILD_VECTOR ||
5042 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5044 } else if (Idx >= 0) {
5045 unsigned Opc = V1.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V1.getOperand(Idx)))
5056 /// getZeroVector - Returns a vector of specified type with all zero elements.
5058 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5059 SelectionDAG &DAG, SDLoc dl) {
5060 assert(VT.isVector() && "Expected a vector type");
5062 // Always build SSE zero vectors as <4 x i32> bitcasted
5063 // to their dest type. This ensures they get CSE'd.
5065 if (VT.is128BitVector()) { // SSE
5066 if (Subtarget->hasSSE2()) { // SSE2
5067 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5070 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5071 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5073 } else if (VT.is256BitVector()) { // AVX
5074 if (Subtarget->hasInt256()) { // AVX2
5075 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5076 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5077 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5079 // 256-bit logic and arithmetic instructions in AVX are all
5080 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5081 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5082 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5085 } else if (VT.is512BitVector()) { // AVX-512
5086 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5088 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5090 } else if (VT.getScalarType() == MVT::i1) {
5091 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5092 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5093 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5094 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5096 llvm_unreachable("Unexpected vector type");
5098 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5101 /// getOnesVector - Returns a vector of specified type with all bits set.
5102 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5103 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5104 /// Then bitcast to their original type, ensuring they get CSE'd.
5105 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5107 assert(VT.isVector() && "Expected a vector type");
5109 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5111 if (VT.is256BitVector()) {
5112 if (HasInt256) { // AVX2
5113 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5114 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5117 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5119 } else if (VT.is128BitVector()) {
5120 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 llvm_unreachable("Unexpected vector type");
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5127 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5128 /// that point to V2 points to its first element.
5129 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5130 for (unsigned i = 0; i != NumElems; ++i) {
5131 if (Mask[i] > (int)NumElems) {
5137 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5138 /// operation of specified width.
5139 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5141 unsigned NumElems = VT.getVectorNumElements();
5142 SmallVector<int, 8> Mask;
5143 Mask.push_back(NumElems);
5144 for (unsigned i = 1; i != NumElems; ++i)
5146 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5149 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5150 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5152 unsigned NumElems = VT.getVectorNumElements();
5153 SmallVector<int, 8> Mask;
5154 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5156 Mask.push_back(i + NumElems);
5158 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5162 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 unsigned NumElems = VT.getVectorNumElements();
5165 SmallVector<int, 8> Mask;
5166 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5167 Mask.push_back(i + Half);
5168 Mask.push_back(i + NumElems + Half);
5170 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5174 // a generic shuffle instruction because the target has no such instructions.
5175 // Generate shuffles which repeat i16 and i8 several times until they can be
5176 // represented by v4f32 and then be manipulated by target suported shuffles.
5177 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5178 MVT VT = V.getSimpleValueType();
5179 int NumElems = VT.getVectorNumElements();
5182 while (NumElems > 4) {
5183 if (EltNo < NumElems/2) {
5184 V = getUnpackl(DAG, dl, VT, V, V);
5186 V = getUnpackh(DAG, dl, VT, V, V);
5187 EltNo -= NumElems/2;
5194 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5195 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5196 MVT VT = V.getSimpleValueType();
5199 if (VT.is128BitVector()) {
5200 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5201 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5202 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5204 } else if (VT.is256BitVector()) {
5205 // To use VPERMILPS to splat scalars, the second half of indicies must
5206 // refer to the higher part, which is a duplication of the lower one,
5207 // because VPERMILPS can only handle in-lane permutations.
5208 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5209 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5211 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5212 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5215 llvm_unreachable("Vector size not supported");
5217 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5220 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5221 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5222 MVT SrcVT = SV->getSimpleValueType(0);
5223 SDValue V1 = SV->getOperand(0);
5226 int EltNo = SV->getSplatIndex();
5227 int NumElems = SrcVT.getVectorNumElements();
5228 bool Is256BitVec = SrcVT.is256BitVector();
5230 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5231 "Unknown how to promote splat for type");
5233 // Extract the 128-bit part containing the splat element and update
5234 // the splat element index when it refers to the higher register.
5236 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5237 if (EltNo >= NumElems/2)
5238 EltNo -= NumElems/2;
5241 // All i16 and i8 vector types can't be used directly by a generic shuffle
5242 // instruction because the target has no such instruction. Generate shuffles
5243 // which repeat i16 and i8 several times until they fit in i32, and then can
5244 // be manipulated by target suported shuffles.
5245 MVT EltVT = SrcVT.getVectorElementType();
5246 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5247 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5249 // Recreate the 256-bit vector and place the same 128-bit vector
5250 // into the low and high part. This is necessary because we want
5251 // to use VPERM* to shuffle the vectors
5253 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5256 return getLegalSplat(DAG, V1, EltNo);
5259 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5260 /// vector of zero or undef vector. This produces a shuffle where the low
5261 /// element of V2 is swizzled into the zero/undef vector, landing at element
5262 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5263 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5265 const X86Subtarget *Subtarget,
5266 SelectionDAG &DAG) {
5267 MVT VT = V2.getSimpleValueType();
5269 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5270 unsigned NumElems = VT.getVectorNumElements();
5271 SmallVector<int, 16> MaskVec;
5272 for (unsigned i = 0; i != NumElems; ++i)
5273 // If this is the insertion idx, put the low elt of V2 here.
5274 MaskVec.push_back(i == Idx ? NumElems : i);
5275 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5278 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5279 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5280 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5281 /// shuffles which use a single input multiple times, and in those cases it will
5282 /// adjust the mask to only have indices within that single input.
5283 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5284 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5285 unsigned NumElems = VT.getVectorNumElements();
5289 bool IsFakeUnary = false;
5290 switch(N->getOpcode()) {
5292 ImmN = N->getOperand(N->getNumOperands()-1);
5293 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5294 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5296 case X86ISD::UNPCKH:
5297 DecodeUNPCKHMask(VT, Mask);
5298 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5300 case X86ISD::UNPCKL:
5301 DecodeUNPCKLMask(VT, Mask);
5302 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 case X86ISD::MOVHLPS:
5305 DecodeMOVHLPSMask(NumElems, Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::MOVLHPS:
5309 DecodeMOVLHPSMask(NumElems, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::PALIGNR:
5313 ImmN = N->getOperand(N->getNumOperands()-1);
5314 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5316 case X86ISD::PSHUFD:
5317 case X86ISD::VPERMILPI:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFHW:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFLW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFB: {
5334 SDValue MaskNode = N->getOperand(1);
5335 while (MaskNode->getOpcode() == ISD::BITCAST)
5336 MaskNode = MaskNode->getOperand(0);
5338 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5339 // If we have a build-vector, then things are easy.
5340 EVT VT = MaskNode.getValueType();
5341 assert(VT.isVector() &&
5342 "Can't produce a non-vector with a build_vector!");
5343 if (!VT.isInteger())
5346 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5348 SmallVector<uint64_t, 32> RawMask;
5349 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5350 SDValue Op = MaskNode->getOperand(i);
5351 if (Op->getOpcode() == ISD::UNDEF) {
5352 RawMask.push_back((uint64_t)SM_SentinelUndef);
5355 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5358 APInt MaskElement = CN->getAPIntValue();
5360 // We now have to decode the element which could be any integer size and
5361 // extract each byte of it.
5362 for (int j = 0; j < NumBytesPerElement; ++j) {
5363 // Note that this is x86 and so always little endian: the low byte is
5364 // the first byte of the mask.
5365 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5366 MaskElement = MaskElement.lshr(8);
5369 DecodePSHUFBMask(RawMask, Mask);
5373 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5377 SDValue Ptr = MaskLoad->getBasePtr();
5378 if (Ptr->getOpcode() == X86ISD::Wrapper)
5379 Ptr = Ptr->getOperand(0);
5381 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5382 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5385 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5386 // FIXME: Support AVX-512 here.
5387 Type *Ty = C->getType();
5388 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5389 Ty->getVectorNumElements() != 32))
5392 DecodePSHUFBMask(C, Mask);
5398 case X86ISD::VPERMI:
5399 ImmN = N->getOperand(N->getNumOperands()-1);
5400 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5404 case X86ISD::MOVSD: {
5405 // The index 0 always comes from the first element of the second source,
5406 // this is why MOVSS and MOVSD are used in the first place. The other
5407 // elements come from the other positions of the first source vector
5408 Mask.push_back(NumElems);
5409 for (unsigned i = 1; i != NumElems; ++i) {
5414 case X86ISD::VPERM2X128:
5415 ImmN = N->getOperand(N->getNumOperands()-1);
5416 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5417 if (Mask.empty()) return false;
5419 case X86ISD::MOVSLDUP:
5420 DecodeMOVSLDUPMask(VT, Mask);
5422 case X86ISD::MOVSHDUP:
5423 DecodeMOVSHDUPMask(VT, Mask);
5425 case X86ISD::MOVDDUP:
5426 case X86ISD::MOVLHPD:
5427 case X86ISD::MOVLPD:
5428 case X86ISD::MOVLPS:
5429 // Not yet implemented
5431 default: llvm_unreachable("unknown target shuffle node");
5434 // If we have a fake unary shuffle, the shuffle mask is spread across two
5435 // inputs that are actually the same node. Re-map the mask to always point
5436 // into the first input.
5439 if (M >= (int)Mask.size())
5445 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5446 /// element of the result of the vector shuffle.
5447 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5450 return SDValue(); // Limit search depth.
5452 SDValue V = SDValue(N, 0);
5453 EVT VT = V.getValueType();
5454 unsigned Opcode = V.getOpcode();
5456 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5457 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5458 int Elt = SV->getMaskElt(Index);
5461 return DAG.getUNDEF(VT.getVectorElementType());
5463 unsigned NumElems = VT.getVectorNumElements();
5464 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5465 : SV->getOperand(1);
5466 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5469 // Recurse into target specific vector shuffles to find scalars.
5470 if (isTargetShuffle(Opcode)) {
5471 MVT ShufVT = V.getSimpleValueType();
5472 unsigned NumElems = ShufVT.getVectorNumElements();
5473 SmallVector<int, 16> ShuffleMask;
5476 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5479 int Elt = ShuffleMask[Index];
5481 return DAG.getUNDEF(ShufVT.getVectorElementType());
5483 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5485 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5489 // Actual nodes that may contain scalar elements
5490 if (Opcode == ISD::BITCAST) {
5491 V = V.getOperand(0);
5492 EVT SrcVT = V.getValueType();
5493 unsigned NumElems = VT.getVectorNumElements();
5495 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5499 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5500 return (Index == 0) ? V.getOperand(0)
5501 : DAG.getUNDEF(VT.getVectorElementType());
5503 if (V.getOpcode() == ISD::BUILD_VECTOR)
5504 return V.getOperand(Index);
5509 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5510 /// shuffle operation which come from a consecutively from a zero. The
5511 /// search can start in two different directions, from left or right.
5512 /// We count undefs as zeros until PreferredNum is reached.
5513 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5514 unsigned NumElems, bool ZerosFromLeft,
5516 unsigned PreferredNum = -1U) {
5517 unsigned NumZeros = 0;
5518 for (unsigned i = 0; i != NumElems; ++i) {
5519 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5520 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5524 if (X86::isZeroNode(Elt))
5526 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5527 NumZeros = std::min(NumZeros + 1, PreferredNum);
5535 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5536 /// correspond consecutively to elements from one of the vector operands,
5537 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5539 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5540 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5541 unsigned NumElems, unsigned &OpNum) {
5542 bool SeenV1 = false;
5543 bool SeenV2 = false;
5545 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5546 int Idx = SVOp->getMaskElt(i);
5547 // Ignore undef indicies
5551 if (Idx < (int)NumElems)
5556 // Only accept consecutive elements from the same vector
5557 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5561 OpNum = SeenV1 ? 0 : 1;
5565 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5566 /// logical left shift of a vector.
5567 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5568 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5570 SVOp->getSimpleValueType(0).getVectorNumElements();
5571 unsigned NumZeros = getNumOfConsecutiveZeros(
5572 SVOp, NumElems, false /* check zeros from right */, DAG,
5573 SVOp->getMaskElt(0));
5579 // Considering the elements in the mask that are not consecutive zeros,
5580 // check if they consecutively come from only one of the source vectors.
5582 // V1 = {X, A, B, C} 0
5584 // vector_shuffle V1, V2 <1, 2, 3, X>
5586 if (!isShuffleMaskConsecutive(SVOp,
5587 0, // Mask Start Index
5588 NumElems-NumZeros, // Mask End Index(exclusive)
5589 NumZeros, // Where to start looking in the src vector
5590 NumElems, // Number of elements in vector
5591 OpSrc)) // Which source operand ?
5596 ShVal = SVOp->getOperand(OpSrc);
5600 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5601 /// logical left shift of a vector.
5602 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5603 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5605 SVOp->getSimpleValueType(0).getVectorNumElements();
5606 unsigned NumZeros = getNumOfConsecutiveZeros(
5607 SVOp, NumElems, true /* check zeros from left */, DAG,
5608 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5614 // Considering the elements in the mask that are not consecutive zeros,
5615 // check if they consecutively come from only one of the source vectors.
5617 // 0 { A, B, X, X } = V2
5619 // vector_shuffle V1, V2 <X, X, 4, 5>
5621 if (!isShuffleMaskConsecutive(SVOp,
5622 NumZeros, // Mask Start Index
5623 NumElems, // Mask End Index(exclusive)
5624 0, // Where to start looking in the src vector
5625 NumElems, // Number of elements in vector
5626 OpSrc)) // Which source operand ?
5631 ShVal = SVOp->getOperand(OpSrc);
5635 /// isVectorShift - Returns true if the shuffle can be implemented as a
5636 /// logical left or right shift of a vector.
5637 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5638 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5639 // Although the logic below support any bitwidth size, there are no
5640 // shift instructions which handle more than 128-bit vectors.
5641 if (!SVOp->getSimpleValueType(0).is128BitVector())
5644 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5645 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5651 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5653 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5654 unsigned NumNonZero, unsigned NumZero,
5656 const X86Subtarget* Subtarget,
5657 const TargetLowering &TLI) {
5664 for (unsigned i = 0; i < 16; ++i) {
5665 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5666 if (ThisIsNonZero && First) {
5668 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5670 V = DAG.getUNDEF(MVT::v8i16);
5675 SDValue ThisElt, LastElt;
5676 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5677 if (LastIsNonZero) {
5678 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5679 MVT::i16, Op.getOperand(i-1));
5681 if (ThisIsNonZero) {
5682 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5683 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5684 ThisElt, DAG.getConstant(8, MVT::i8));
5686 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5690 if (ThisElt.getNode())
5691 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5692 DAG.getIntPtrConstant(i/2));
5696 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5699 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5701 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5702 unsigned NumNonZero, unsigned NumZero,
5704 const X86Subtarget* Subtarget,
5705 const TargetLowering &TLI) {
5712 for (unsigned i = 0; i < 8; ++i) {
5713 bool isNonZero = (NonZeros & (1 << i)) != 0;
5717 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5719 V = DAG.getUNDEF(MVT::v8i16);
5722 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5723 MVT::v8i16, V, Op.getOperand(i),
5724 DAG.getIntPtrConstant(i));
5731 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5732 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5733 unsigned NonZeros, unsigned NumNonZero,
5734 unsigned NumZero, SelectionDAG &DAG,
5735 const X86Subtarget *Subtarget,
5736 const TargetLowering &TLI) {
5737 // We know there's at least one non-zero element
5738 unsigned FirstNonZeroIdx = 0;
5739 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5740 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5741 X86::isZeroNode(FirstNonZero)) {
5743 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5747 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5750 SDValue V = FirstNonZero.getOperand(0);
5751 MVT VVT = V.getSimpleValueType();
5752 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5755 unsigned FirstNonZeroDst =
5756 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5757 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5758 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5759 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5761 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5762 SDValue Elem = Op.getOperand(Idx);
5763 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5766 // TODO: What else can be here? Deal with it.
5767 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5770 // TODO: Some optimizations are still possible here
5771 // ex: Getting one element from a vector, and the rest from another.
5772 if (Elem.getOperand(0) != V)
5775 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5778 else if (IncorrectIdx == -1U) {
5782 // There was already one element with an incorrect index.
5783 // We can't optimize this case to an insertps.
5787 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5789 EVT VT = Op.getSimpleValueType();
5790 unsigned ElementMoveMask = 0;
5791 if (IncorrectIdx == -1U)
5792 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5794 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5796 SDValue InsertpsMask =
5797 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5798 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5804 /// getVShift - Return a vector logical shift node.
5806 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5807 unsigned NumBits, SelectionDAG &DAG,
5808 const TargetLowering &TLI, SDLoc dl) {
5809 assert(VT.is128BitVector() && "Unknown type for VShift");
5810 EVT ShVT = MVT::v2i64;
5811 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5812 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5813 return DAG.getNode(ISD::BITCAST, dl, VT,
5814 DAG.getNode(Opc, dl, ShVT, SrcOp,
5815 DAG.getConstant(NumBits,
5816 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5820 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5822 // Check if the scalar load can be widened into a vector load. And if
5823 // the address is "base + cst" see if the cst can be "absorbed" into
5824 // the shuffle mask.
5825 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5826 SDValue Ptr = LD->getBasePtr();
5827 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5829 EVT PVT = LD->getValueType(0);
5830 if (PVT != MVT::i32 && PVT != MVT::f32)
5835 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5836 FI = FINode->getIndex();
5838 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5839 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5840 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5841 Offset = Ptr.getConstantOperandVal(1);
5842 Ptr = Ptr.getOperand(0);
5847 // FIXME: 256-bit vector instructions don't require a strict alignment,
5848 // improve this code to support it better.
5849 unsigned RequiredAlign = VT.getSizeInBits()/8;
5850 SDValue Chain = LD->getChain();
5851 // Make sure the stack object alignment is at least 16 or 32.
5852 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5853 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5854 if (MFI->isFixedObjectIndex(FI)) {
5855 // Can't change the alignment. FIXME: It's possible to compute
5856 // the exact stack offset and reference FI + adjust offset instead.
5857 // If someone *really* cares about this. That's the way to implement it.
5860 MFI->setObjectAlignment(FI, RequiredAlign);
5864 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5865 // Ptr + (Offset & ~15).
5868 if ((Offset % RequiredAlign) & 3)
5870 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5872 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5873 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5875 int EltNo = (Offset - StartOffset) >> 2;
5876 unsigned NumElems = VT.getVectorNumElements();
5878 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5879 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5880 LD->getPointerInfo().getWithOffset(StartOffset),
5881 false, false, false, 0);
5883 SmallVector<int, 8> Mask;
5884 for (unsigned i = 0; i != NumElems; ++i)
5885 Mask.push_back(EltNo);
5887 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5893 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5894 /// vector of type 'VT', see if the elements can be replaced by a single large
5895 /// load which has the same value as a build_vector whose operands are 'elts'.
5897 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5899 /// FIXME: we'd also like to handle the case where the last elements are zero
5900 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5901 /// There's even a handy isZeroNode for that purpose.
5902 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5903 SDLoc &DL, SelectionDAG &DAG,
5904 bool isAfterLegalize) {
5905 EVT EltVT = VT.getVectorElementType();
5906 unsigned NumElems = Elts.size();
5908 LoadSDNode *LDBase = nullptr;
5909 unsigned LastLoadedElt = -1U;
5911 // For each element in the initializer, see if we've found a load or an undef.
5912 // If we don't find an initial load element, or later load elements are
5913 // non-consecutive, bail out.
5914 for (unsigned i = 0; i < NumElems; ++i) {
5915 SDValue Elt = Elts[i];
5917 if (!Elt.getNode() ||
5918 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5921 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5923 LDBase = cast<LoadSDNode>(Elt.getNode());
5927 if (Elt.getOpcode() == ISD::UNDEF)
5930 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5931 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5936 // If we have found an entire vector of loads and undefs, then return a large
5937 // load of the entire vector width starting at the base pointer. If we found
5938 // consecutive loads for the low half, generate a vzext_load node.
5939 if (LastLoadedElt == NumElems - 1) {
5941 if (isAfterLegalize &&
5942 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5945 SDValue NewLd = SDValue();
5947 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5948 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5949 LDBase->getPointerInfo(),
5950 LDBase->isVolatile(), LDBase->isNonTemporal(),
5951 LDBase->isInvariant(), 0);
5952 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5953 LDBase->getPointerInfo(),
5954 LDBase->isVolatile(), LDBase->isNonTemporal(),
5955 LDBase->isInvariant(), LDBase->getAlignment());
5957 if (LDBase->hasAnyUseOfValue(1)) {
5958 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5960 SDValue(NewLd.getNode(), 1));
5961 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5962 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5963 SDValue(NewLd.getNode(), 1));
5968 if (NumElems == 4 && LastLoadedElt == 1 &&
5969 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5970 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5971 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5973 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5974 LDBase->getPointerInfo(),
5975 LDBase->getAlignment(),
5976 false/*isVolatile*/, true/*ReadMem*/,
5979 // Make sure the newly-created LOAD is in the same position as LDBase in
5980 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5981 // update uses of LDBase's output chain to use the TokenFactor.
5982 if (LDBase->hasAnyUseOfValue(1)) {
5983 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5984 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5985 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5986 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5987 SDValue(ResNode.getNode(), 1));
5990 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5995 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5996 /// to generate a splat value for the following cases:
5997 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5998 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5999 /// a scalar load, or a constant.
6000 /// The VBROADCAST node is returned when a pattern is found,
6001 /// or SDValue() otherwise.
6002 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6003 SelectionDAG &DAG) {
6004 // VBROADCAST requires AVX.
6005 // TODO: Splats could be generated for non-AVX CPUs using SSE
6006 // instructions, but there's less potential gain for only 128-bit vectors.
6007 if (!Subtarget->hasAVX())
6010 MVT VT = Op.getSimpleValueType();
6013 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6014 "Unsupported vector type for broadcast.");
6019 switch (Op.getOpcode()) {
6021 // Unknown pattern found.
6024 case ISD::BUILD_VECTOR: {
6025 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6026 BitVector UndefElements;
6027 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6029 // We need a splat of a single value to use broadcast, and it doesn't
6030 // make any sense if the value is only in one element of the vector.
6031 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6035 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6036 Ld.getOpcode() == ISD::ConstantFP);
6038 // Make sure that all of the users of a non-constant load are from the
6039 // BUILD_VECTOR node.
6040 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6045 case ISD::VECTOR_SHUFFLE: {
6046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6048 // Shuffles must have a splat mask where the first element is
6050 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6053 SDValue Sc = Op.getOperand(0);
6054 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6055 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6057 if (!Subtarget->hasInt256())
6060 // Use the register form of the broadcast instruction available on AVX2.
6061 if (VT.getSizeInBits() >= 256)
6062 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6063 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6066 Ld = Sc.getOperand(0);
6067 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6068 Ld.getOpcode() == ISD::ConstantFP);
6070 // The scalar_to_vector node and the suspected
6071 // load node must have exactly one user.
6072 // Constants may have multiple users.
6074 // AVX-512 has register version of the broadcast
6075 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6076 Ld.getValueType().getSizeInBits() >= 32;
6077 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6084 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6085 bool IsGE256 = (VT.getSizeInBits() >= 256);
6087 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6088 // instruction to save 8 or more bytes of constant pool data.
6089 // TODO: If multiple splats are generated to load the same constant,
6090 // it may be detrimental to overall size. There needs to be a way to detect
6091 // that condition to know if this is truly a size win.
6092 const Function *F = DAG.getMachineFunction().getFunction();
6093 bool OptForSize = F->getAttributes().
6094 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6096 // Handle broadcasting a single constant scalar from the constant pool
6098 // On Sandybridge (no AVX2), it is still better to load a constant vector
6099 // from the constant pool and not to broadcast it from a scalar.
6100 // But override that restriction when optimizing for size.
6101 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6102 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6103 EVT CVT = Ld.getValueType();
6104 assert(!CVT.isVector() && "Must not broadcast a vector type");
6106 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6107 // For size optimization, also splat v2f64 and v2i64, and for size opt
6108 // with AVX2, also splat i8 and i16.
6109 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6110 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6111 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6112 const Constant *C = nullptr;
6113 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6114 C = CI->getConstantIntValue();
6115 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6116 C = CF->getConstantFPValue();
6118 assert(C && "Invalid constant type");
6120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6121 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6122 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6123 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6124 MachinePointerInfo::getConstantPool(),
6125 false, false, false, Alignment);
6127 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6131 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6133 // Handle AVX2 in-register broadcasts.
6134 if (!IsLoad && Subtarget->hasInt256() &&
6135 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6136 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6138 // The scalar source must be a normal load.
6142 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6143 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6145 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6146 // double since there is no vbroadcastsd xmm
6147 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6148 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6152 // Unsupported broadcast.
6156 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6157 /// underlying vector and index.
6159 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6161 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6163 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6164 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6167 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6169 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6171 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6172 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6175 // In this case the vector is the extract_subvector expression and the index
6176 // is 2, as specified by the shuffle.
6177 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6178 SDValue ShuffleVec = SVOp->getOperand(0);
6179 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6180 assert(ShuffleVecVT.getVectorElementType() ==
6181 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6183 int ShuffleIdx = SVOp->getMaskElt(Idx);
6184 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6185 ExtractedFromVec = ShuffleVec;
6191 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6192 MVT VT = Op.getSimpleValueType();
6194 // Skip if insert_vec_elt is not supported.
6195 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6196 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6200 unsigned NumElems = Op.getNumOperands();
6204 SmallVector<unsigned, 4> InsertIndices;
6205 SmallVector<int, 8> Mask(NumElems, -1);
6207 for (unsigned i = 0; i != NumElems; ++i) {
6208 unsigned Opc = Op.getOperand(i).getOpcode();
6210 if (Opc == ISD::UNDEF)
6213 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6214 // Quit if more than 1 elements need inserting.
6215 if (InsertIndices.size() > 1)
6218 InsertIndices.push_back(i);
6222 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6223 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6224 // Quit if non-constant index.
6225 if (!isa<ConstantSDNode>(ExtIdx))
6227 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6229 // Quit if extracted from vector of different type.
6230 if (ExtractedFromVec.getValueType() != VT)
6233 if (!VecIn1.getNode())
6234 VecIn1 = ExtractedFromVec;
6235 else if (VecIn1 != ExtractedFromVec) {
6236 if (!VecIn2.getNode())
6237 VecIn2 = ExtractedFromVec;
6238 else if (VecIn2 != ExtractedFromVec)
6239 // Quit if more than 2 vectors to shuffle
6243 if (ExtractedFromVec == VecIn1)
6245 else if (ExtractedFromVec == VecIn2)
6246 Mask[i] = Idx + NumElems;
6249 if (!VecIn1.getNode())
6252 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6253 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6254 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6255 unsigned Idx = InsertIndices[i];
6256 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6257 DAG.getIntPtrConstant(Idx));
6263 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6265 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6267 MVT VT = Op.getSimpleValueType();
6268 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6269 "Unexpected type in LowerBUILD_VECTORvXi1!");
6272 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6273 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6274 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6275 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6278 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6279 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6280 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6281 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6284 bool AllContants = true;
6285 uint64_t Immediate = 0;
6286 int NonConstIdx = -1;
6287 bool IsSplat = true;
6288 unsigned NumNonConsts = 0;
6289 unsigned NumConsts = 0;
6290 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6291 SDValue In = Op.getOperand(idx);
6292 if (In.getOpcode() == ISD::UNDEF)
6294 if (!isa<ConstantSDNode>(In)) {
6295 AllContants = false;
6301 if (cast<ConstantSDNode>(In)->getZExtValue())
6302 Immediate |= (1ULL << idx);
6304 if (In != Op.getOperand(0))
6309 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6310 DAG.getConstant(Immediate, MVT::i16));
6311 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6312 DAG.getIntPtrConstant(0));
6315 if (NumNonConsts == 1 && NonConstIdx != 0) {
6318 SDValue VecAsImm = DAG.getConstant(Immediate,
6319 MVT::getIntegerVT(VT.getSizeInBits()));
6320 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6323 DstVec = DAG.getUNDEF(VT);
6324 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6325 Op.getOperand(NonConstIdx),
6326 DAG.getIntPtrConstant(NonConstIdx));
6328 if (!IsSplat && (NonConstIdx != 0))
6329 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6330 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6333 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6334 DAG.getConstant(-1, SelectVT),
6335 DAG.getConstant(0, SelectVT));
6337 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6338 DAG.getConstant((Immediate | 1), SelectVT),
6339 DAG.getConstant(Immediate, SelectVT));
6340 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6343 /// \brief Return true if \p N implements a horizontal binop and return the
6344 /// operands for the horizontal binop into V0 and V1.
6346 /// This is a helper function of PerformBUILD_VECTORCombine.
6347 /// This function checks that the build_vector \p N in input implements a
6348 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6349 /// operation to match.
6350 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6351 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6352 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6355 /// This function only analyzes elements of \p N whose indices are
6356 /// in range [BaseIdx, LastIdx).
6357 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6359 unsigned BaseIdx, unsigned LastIdx,
6360 SDValue &V0, SDValue &V1) {
6361 EVT VT = N->getValueType(0);
6363 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6364 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6365 "Invalid Vector in input!");
6367 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6368 bool CanFold = true;
6369 unsigned ExpectedVExtractIdx = BaseIdx;
6370 unsigned NumElts = LastIdx - BaseIdx;
6371 V0 = DAG.getUNDEF(VT);
6372 V1 = DAG.getUNDEF(VT);
6374 // Check if N implements a horizontal binop.
6375 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6376 SDValue Op = N->getOperand(i + BaseIdx);
6379 if (Op->getOpcode() == ISD::UNDEF) {
6380 // Update the expected vector extract index.
6381 if (i * 2 == NumElts)
6382 ExpectedVExtractIdx = BaseIdx;
6383 ExpectedVExtractIdx += 2;
6387 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6392 SDValue Op0 = Op.getOperand(0);
6393 SDValue Op1 = Op.getOperand(1);
6395 // Try to match the following pattern:
6396 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6397 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6398 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6399 Op0.getOperand(0) == Op1.getOperand(0) &&
6400 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6401 isa<ConstantSDNode>(Op1.getOperand(1)));
6405 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6406 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6408 if (i * 2 < NumElts) {
6409 if (V0.getOpcode() == ISD::UNDEF)
6410 V0 = Op0.getOperand(0);
6412 if (V1.getOpcode() == ISD::UNDEF)
6413 V1 = Op0.getOperand(0);
6414 if (i * 2 == NumElts)
6415 ExpectedVExtractIdx = BaseIdx;
6418 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6419 if (I0 == ExpectedVExtractIdx)
6420 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6421 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6422 // Try to match the following dag sequence:
6423 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6424 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6428 ExpectedVExtractIdx += 2;
6434 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6435 /// a concat_vector.
6437 /// This is a helper function of PerformBUILD_VECTORCombine.
6438 /// This function expects two 256-bit vectors called V0 and V1.
6439 /// At first, each vector is split into two separate 128-bit vectors.
6440 /// Then, the resulting 128-bit vectors are used to implement two
6441 /// horizontal binary operations.
6443 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6445 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6446 /// the two new horizontal binop.
6447 /// When Mode is set, the first horizontal binop dag node would take as input
6448 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6449 /// horizontal binop dag node would take as input the lower 128-bit of V1
6450 /// and the upper 128-bit of V1.
6452 /// HADD V0_LO, V0_HI
6453 /// HADD V1_LO, V1_HI
6455 /// Otherwise, the first horizontal binop dag node takes as input the lower
6456 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6457 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6459 /// HADD V0_LO, V1_LO
6460 /// HADD V0_HI, V1_HI
6462 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6463 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6464 /// the upper 128-bits of the result.
6465 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6466 SDLoc DL, SelectionDAG &DAG,
6467 unsigned X86Opcode, bool Mode,
6468 bool isUndefLO, bool isUndefHI) {
6469 EVT VT = V0.getValueType();
6470 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6471 "Invalid nodes in input!");
6473 unsigned NumElts = VT.getVectorNumElements();
6474 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6475 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6476 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6477 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6478 EVT NewVT = V0_LO.getValueType();
6480 SDValue LO = DAG.getUNDEF(NewVT);
6481 SDValue HI = DAG.getUNDEF(NewVT);
6484 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6485 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6486 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6487 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6488 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6490 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6491 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6492 V1_LO->getOpcode() != ISD::UNDEF))
6493 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6495 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6496 V1_HI->getOpcode() != ISD::UNDEF))
6497 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6500 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6503 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6504 /// sequence of 'vadd + vsub + blendi'.
6505 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6506 const X86Subtarget *Subtarget) {
6508 EVT VT = BV->getValueType(0);
6509 unsigned NumElts = VT.getVectorNumElements();
6510 SDValue InVec0 = DAG.getUNDEF(VT);
6511 SDValue InVec1 = DAG.getUNDEF(VT);
6513 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6514 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6516 // Odd-numbered elements in the input build vector are obtained from
6517 // adding two integer/float elements.
6518 // Even-numbered elements in the input build vector are obtained from
6519 // subtracting two integer/float elements.
6520 unsigned ExpectedOpcode = ISD::FSUB;
6521 unsigned NextExpectedOpcode = ISD::FADD;
6522 bool AddFound = false;
6523 bool SubFound = false;
6525 for (unsigned i = 0, e = NumElts; i != e; i++) {
6526 SDValue Op = BV->getOperand(i);
6528 // Skip 'undef' values.
6529 unsigned Opcode = Op.getOpcode();
6530 if (Opcode == ISD::UNDEF) {
6531 std::swap(ExpectedOpcode, NextExpectedOpcode);
6535 // Early exit if we found an unexpected opcode.
6536 if (Opcode != ExpectedOpcode)
6539 SDValue Op0 = Op.getOperand(0);
6540 SDValue Op1 = Op.getOperand(1);
6542 // Try to match the following pattern:
6543 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6544 // Early exit if we cannot match that sequence.
6545 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6546 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6547 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6548 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6549 Op0.getOperand(1) != Op1.getOperand(1))
6552 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6556 // We found a valid add/sub node. Update the information accordingly.
6562 // Update InVec0 and InVec1.
6563 if (InVec0.getOpcode() == ISD::UNDEF)
6564 InVec0 = Op0.getOperand(0);
6565 if (InVec1.getOpcode() == ISD::UNDEF)
6566 InVec1 = Op1.getOperand(0);
6568 // Make sure that operands in input to each add/sub node always
6569 // come from a same pair of vectors.
6570 if (InVec0 != Op0.getOperand(0)) {
6571 if (ExpectedOpcode == ISD::FSUB)
6574 // FADD is commutable. Try to commute the operands
6575 // and then test again.
6576 std::swap(Op0, Op1);
6577 if (InVec0 != Op0.getOperand(0))
6581 if (InVec1 != Op1.getOperand(0))
6584 // Update the pair of expected opcodes.
6585 std::swap(ExpectedOpcode, NextExpectedOpcode);
6588 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6589 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6590 InVec1.getOpcode() != ISD::UNDEF)
6591 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6596 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6597 const X86Subtarget *Subtarget) {
6599 EVT VT = N->getValueType(0);
6600 unsigned NumElts = VT.getVectorNumElements();
6601 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6602 SDValue InVec0, InVec1;
6604 // Try to match an ADDSUB.
6605 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6606 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6607 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6608 if (Value.getNode())
6612 // Try to match horizontal ADD/SUB.
6613 unsigned NumUndefsLO = 0;
6614 unsigned NumUndefsHI = 0;
6615 unsigned Half = NumElts/2;
6617 // Count the number of UNDEF operands in the build_vector in input.
6618 for (unsigned i = 0, e = Half; i != e; ++i)
6619 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6622 for (unsigned i = Half, e = NumElts; i != e; ++i)
6623 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6626 // Early exit if this is either a build_vector of all UNDEFs or all the
6627 // operands but one are UNDEF.
6628 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6631 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6632 // Try to match an SSE3 float HADD/HSUB.
6633 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6634 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6636 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6637 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6638 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6639 // Try to match an SSSE3 integer HADD/HSUB.
6640 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6641 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6643 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6644 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6647 if (!Subtarget->hasAVX())
6650 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6651 // Try to match an AVX horizontal add/sub of packed single/double
6652 // precision floating point values from 256-bit vectors.
6653 SDValue InVec2, InVec3;
6654 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6655 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6656 ((InVec0.getOpcode() == ISD::UNDEF ||
6657 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6658 ((InVec1.getOpcode() == ISD::UNDEF ||
6659 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6660 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6662 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6663 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6664 ((InVec0.getOpcode() == ISD::UNDEF ||
6665 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6666 ((InVec1.getOpcode() == ISD::UNDEF ||
6667 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6668 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6669 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6670 // Try to match an AVX2 horizontal add/sub of signed integers.
6671 SDValue InVec2, InVec3;
6673 bool CanFold = true;
6675 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6676 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6677 ((InVec0.getOpcode() == ISD::UNDEF ||
6678 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6679 ((InVec1.getOpcode() == ISD::UNDEF ||
6680 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6681 X86Opcode = X86ISD::HADD;
6682 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6683 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6684 ((InVec0.getOpcode() == ISD::UNDEF ||
6685 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6686 ((InVec1.getOpcode() == ISD::UNDEF ||
6687 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6688 X86Opcode = X86ISD::HSUB;
6693 // Fold this build_vector into a single horizontal add/sub.
6694 // Do this only if the target has AVX2.
6695 if (Subtarget->hasAVX2())
6696 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6698 // Do not try to expand this build_vector into a pair of horizontal
6699 // add/sub if we can emit a pair of scalar add/sub.
6700 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6703 // Convert this build_vector into a pair of horizontal binop followed by
6705 bool isUndefLO = NumUndefsLO == Half;
6706 bool isUndefHI = NumUndefsHI == Half;
6707 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6708 isUndefLO, isUndefHI);
6712 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6713 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6715 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6716 X86Opcode = X86ISD::HADD;
6717 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6718 X86Opcode = X86ISD::HSUB;
6719 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6720 X86Opcode = X86ISD::FHADD;
6721 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::FHSUB;
6726 // Don't try to expand this build_vector into a pair of horizontal add/sub
6727 // if we can simply emit a pair of scalar add/sub.
6728 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6731 // Convert this build_vector into two horizontal add/sub followed by
6733 bool isUndefLO = NumUndefsLO == Half;
6734 bool isUndefHI = NumUndefsHI == Half;
6735 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6736 isUndefLO, isUndefHI);
6743 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6746 MVT VT = Op.getSimpleValueType();
6747 MVT ExtVT = VT.getVectorElementType();
6748 unsigned NumElems = Op.getNumOperands();
6750 // Generate vectors for predicate vectors.
6751 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6752 return LowerBUILD_VECTORvXi1(Op, DAG);
6754 // Vectors containing all zeros can be matched by pxor and xorps later
6755 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6756 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6757 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6758 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6761 return getZeroVector(VT, Subtarget, DAG, dl);
6764 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6765 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6766 // vpcmpeqd on 256-bit vectors.
6767 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6768 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6771 if (!VT.is512BitVector())
6772 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6775 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6776 if (Broadcast.getNode())
6779 unsigned EVTBits = ExtVT.getSizeInBits();
6781 unsigned NumZero = 0;
6782 unsigned NumNonZero = 0;
6783 unsigned NonZeros = 0;
6784 bool IsAllConstants = true;
6785 SmallSet<SDValue, 8> Values;
6786 for (unsigned i = 0; i < NumElems; ++i) {
6787 SDValue Elt = Op.getOperand(i);
6788 if (Elt.getOpcode() == ISD::UNDEF)
6791 if (Elt.getOpcode() != ISD::Constant &&
6792 Elt.getOpcode() != ISD::ConstantFP)
6793 IsAllConstants = false;
6794 if (X86::isZeroNode(Elt))
6797 NonZeros |= (1 << i);
6802 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6803 if (NumNonZero == 0)
6804 return DAG.getUNDEF(VT);
6806 // Special case for single non-zero, non-undef, element.
6807 if (NumNonZero == 1) {
6808 unsigned Idx = countTrailingZeros(NonZeros);
6809 SDValue Item = Op.getOperand(Idx);
6811 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6812 // the value are obviously zero, truncate the value to i32 and do the
6813 // insertion that way. Only do this if the value is non-constant or if the
6814 // value is a constant being inserted into element 0. It is cheaper to do
6815 // a constant pool load than it is to do a movd + shuffle.
6816 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6817 (!IsAllConstants || Idx == 0)) {
6818 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6820 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6821 EVT VecVT = MVT::v4i32;
6822 unsigned VecElts = 4;
6824 // Truncate the value (which may itself be a constant) to i32, and
6825 // convert it to a vector with movd (S2V+shuffle to zero extend).
6826 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6827 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6829 // If using the new shuffle lowering, just directly insert this.
6830 if (ExperimentalVectorShuffleLowering)
6832 ISD::BITCAST, dl, VT,
6833 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6835 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6837 // Now we have our 32-bit value zero extended in the low element of
6838 // a vector. If Idx != 0, swizzle it into place.
6840 SmallVector<int, 4> Mask;
6841 Mask.push_back(Idx);
6842 for (unsigned i = 1; i != VecElts; ++i)
6844 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6847 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6851 // If we have a constant or non-constant insertion into the low element of
6852 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6853 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6854 // depending on what the source datatype is.
6857 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6859 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6860 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6861 if (VT.is256BitVector() || VT.is512BitVector()) {
6862 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6863 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6864 Item, DAG.getIntPtrConstant(0));
6866 assert(VT.is128BitVector() && "Expected an SSE value type!");
6867 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6868 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6869 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6872 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6873 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6874 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6875 if (VT.is256BitVector()) {
6876 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6877 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6879 assert(VT.is128BitVector() && "Expected an SSE value type!");
6880 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6882 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6886 // Is it a vector logical left shift?
6887 if (NumElems == 2 && Idx == 1 &&
6888 X86::isZeroNode(Op.getOperand(0)) &&
6889 !X86::isZeroNode(Op.getOperand(1))) {
6890 unsigned NumBits = VT.getSizeInBits();
6891 return getVShift(true, VT,
6892 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6893 VT, Op.getOperand(1)),
6894 NumBits/2, DAG, *this, dl);
6897 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6900 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6901 // is a non-constant being inserted into an element other than the low one,
6902 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6903 // movd/movss) to move this into the low element, then shuffle it into
6905 if (EVTBits == 32) {
6906 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6908 // If using the new shuffle lowering, just directly insert this.
6909 if (ExperimentalVectorShuffleLowering)
6910 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6912 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6913 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6914 SmallVector<int, 8> MaskVec;
6915 for (unsigned i = 0; i != NumElems; ++i)
6916 MaskVec.push_back(i == Idx ? 0 : 1);
6917 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6921 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6922 if (Values.size() == 1) {
6923 if (EVTBits == 32) {
6924 // Instead of a shuffle like this:
6925 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6926 // Check if it's possible to issue this instead.
6927 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6928 unsigned Idx = countTrailingZeros(NonZeros);
6929 SDValue Item = Op.getOperand(Idx);
6930 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6931 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6936 // A vector full of immediates; various special cases are already
6937 // handled, so this is best done with a single constant-pool load.
6941 // For AVX-length vectors, build the individual 128-bit pieces and use
6942 // shuffles to put them in place.
6943 if (VT.is256BitVector() || VT.is512BitVector()) {
6944 SmallVector<SDValue, 64> V;
6945 for (unsigned i = 0; i != NumElems; ++i)
6946 V.push_back(Op.getOperand(i));
6948 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6950 // Build both the lower and upper subvector.
6951 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6952 makeArrayRef(&V[0], NumElems/2));
6953 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6954 makeArrayRef(&V[NumElems / 2], NumElems/2));
6956 // Recreate the wider vector with the lower and upper part.
6957 if (VT.is256BitVector())
6958 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6959 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6962 // Let legalizer expand 2-wide build_vectors.
6963 if (EVTBits == 64) {
6964 if (NumNonZero == 1) {
6965 // One half is zero or undef.
6966 unsigned Idx = countTrailingZeros(NonZeros);
6967 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6968 Op.getOperand(Idx));
6969 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6974 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6975 if (EVTBits == 8 && NumElems == 16) {
6976 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6978 if (V.getNode()) return V;
6981 if (EVTBits == 16 && NumElems == 8) {
6982 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6984 if (V.getNode()) return V;
6987 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6988 if (EVTBits == 32 && NumElems == 4) {
6989 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6990 NumZero, DAG, Subtarget, *this);
6995 // If element VT is == 32 bits, turn it into a number of shuffles.
6996 SmallVector<SDValue, 8> V(NumElems);
6997 if (NumElems == 4 && NumZero > 0) {
6998 for (unsigned i = 0; i < 4; ++i) {
6999 bool isZero = !(NonZeros & (1 << i));
7001 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7003 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7006 for (unsigned i = 0; i < 2; ++i) {
7007 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7010 V[i] = V[i*2]; // Must be a zero vector.
7013 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7016 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7019 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 bool Reverse1 = (NonZeros & 0x3) == 2;
7025 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7029 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7030 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7032 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7035 if (Values.size() > 1 && VT.is128BitVector()) {
7036 // Check for a build vector of consecutive loads.
7037 for (unsigned i = 0; i < NumElems; ++i)
7038 V[i] = Op.getOperand(i);
7040 // Check for elements which are consecutive loads.
7041 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7045 // Check for a build vector from mostly shuffle plus few inserting.
7046 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7050 // For SSE 4.1, use insertps to put the high elements into the low element.
7051 if (getSubtarget()->hasSSE41()) {
7053 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7054 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7056 Result = DAG.getUNDEF(VT);
7058 for (unsigned i = 1; i < NumElems; ++i) {
7059 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7060 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7061 Op.getOperand(i), DAG.getIntPtrConstant(i));
7066 // Otherwise, expand into a number of unpckl*, start by extending each of
7067 // our (non-undef) elements to the full vector width with the element in the
7068 // bottom slot of the vector (which generates no code for SSE).
7069 for (unsigned i = 0; i < NumElems; ++i) {
7070 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7071 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7073 V[i] = DAG.getUNDEF(VT);
7076 // Next, we iteratively mix elements, e.g. for v4f32:
7077 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7078 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7079 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7080 unsigned EltStride = NumElems >> 1;
7081 while (EltStride != 0) {
7082 for (unsigned i = 0; i < EltStride; ++i) {
7083 // If V[i+EltStride] is undef and this is the first round of mixing,
7084 // then it is safe to just drop this shuffle: V[i] is already in the
7085 // right place, the one element (since it's the first round) being
7086 // inserted as undef can be dropped. This isn't safe for successive
7087 // rounds because they will permute elements within both vectors.
7088 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7089 EltStride == NumElems/2)
7092 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7101 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7102 // to create 256-bit vectors from two other 128-bit ones.
7103 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7105 MVT ResVT = Op.getSimpleValueType();
7107 assert((ResVT.is256BitVector() ||
7108 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7110 SDValue V1 = Op.getOperand(0);
7111 SDValue V2 = Op.getOperand(1);
7112 unsigned NumElems = ResVT.getVectorNumElements();
7113 if(ResVT.is256BitVector())
7114 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7116 if (Op.getNumOperands() == 4) {
7117 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7118 ResVT.getVectorNumElements()/2);
7119 SDValue V3 = Op.getOperand(2);
7120 SDValue V4 = Op.getOperand(3);
7121 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7122 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7124 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7127 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7128 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7129 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7130 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7131 Op.getNumOperands() == 4)));
7133 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7134 // from two other 128-bit ones.
7136 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7137 return LowerAVXCONCAT_VECTORS(Op, DAG);
7141 //===----------------------------------------------------------------------===//
7142 // Vector shuffle lowering
7144 // This is an experimental code path for lowering vector shuffles on x86. It is
7145 // designed to handle arbitrary vector shuffles and blends, gracefully
7146 // degrading performance as necessary. It works hard to recognize idiomatic
7147 // shuffles and lower them to optimal instruction patterns without leaving
7148 // a framework that allows reasonably efficient handling of all vector shuffle
7150 //===----------------------------------------------------------------------===//
7152 /// \brief Tiny helper function to identify a no-op mask.
7154 /// This is a somewhat boring predicate function. It checks whether the mask
7155 /// array input, which is assumed to be a single-input shuffle mask of the kind
7156 /// used by the X86 shuffle instructions (not a fully general
7157 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7158 /// in-place shuffle are 'no-op's.
7159 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7160 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7161 if (Mask[i] != -1 && Mask[i] != i)
7166 /// \brief Helper function to classify a mask as a single-input mask.
7168 /// This isn't a generic single-input test because in the vector shuffle
7169 /// lowering we canonicalize single inputs to be the first input operand. This
7170 /// means we can more quickly test for a single input by only checking whether
7171 /// an input from the second operand exists. We also assume that the size of
7172 /// mask corresponds to the size of the input vectors which isn't true in the
7173 /// fully general case.
7174 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7176 if (M >= (int)Mask.size())
7181 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7182 // 2013 will allow us to use it as a non-type template parameter.
7185 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7187 /// See its documentation for details.
7188 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7189 if (Mask.size() != Args.size())
7191 for (int i = 0, e = Mask.size(); i < e; ++i) {
7192 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7193 if (Mask[i] != -1 && Mask[i] != *Args[i])
7201 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7204 /// This is a fast way to test a shuffle mask against a fixed pattern:
7206 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7208 /// It returns true if the mask is exactly as wide as the argument list, and
7209 /// each element of the mask is either -1 (signifying undef) or the value given
7210 /// in the argument.
7211 static const VariadicFunction1<
7212 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7214 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7216 /// This helper function produces an 8-bit shuffle immediate corresponding to
7217 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7218 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7221 /// NB: We rely heavily on "undef" masks preserving the input lane.
7222 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7223 SelectionDAG &DAG) {
7224 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7225 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7226 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7227 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7228 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7231 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7232 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7233 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7234 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7235 return DAG.getConstant(Imm, MVT::i8);
7238 /// \brief Try to emit a blend instruction for a shuffle.
7240 /// This doesn't do any checks for the availability of instructions for blending
7241 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7242 /// be matched in the backend with the type given. What it does check for is
7243 /// that the shuffle mask is in fact a blend.
7244 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7245 SDValue V2, ArrayRef<int> Mask,
7246 const X86Subtarget *Subtarget,
7247 SelectionDAG &DAG) {
7249 unsigned BlendMask = 0;
7250 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7251 if (Mask[i] >= Size) {
7252 if (Mask[i] != i + Size)
7253 return SDValue(); // Shuffled V2 input!
7254 BlendMask |= 1u << i;
7257 if (Mask[i] >= 0 && Mask[i] != i)
7258 return SDValue(); // Shuffled V1 input!
7260 switch (VT.SimpleTy) {
7265 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7266 DAG.getConstant(BlendMask, MVT::i8));
7270 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7271 // that instruction.
7272 if (Subtarget->hasAVX2()) {
7273 int Scale = 8 / VT.getVectorNumElements();
7275 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7276 if (Mask[i] >= Size)
7277 for (int j = 0; j < Scale; ++j)
7278 BlendMask |= 1u << (i * Scale + j);
7280 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7281 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7282 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7283 return DAG.getNode(ISD::BITCAST, DL, VT,
7284 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7285 DAG.getConstant(BlendMask, MVT::i8)));
7289 // For integer shuffles we need to expand the mask and cast the inputs to
7290 // v8i16s prior to blending.
7291 int Scale = 8 / VT.getVectorNumElements();
7293 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7294 if (Mask[i] >= Size)
7295 for (int j = 0; j < Scale; ++j)
7296 BlendMask |= 1u << (i * Scale + j);
7298 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7299 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7300 return DAG.getNode(ISD::BITCAST, DL, VT,
7301 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7302 DAG.getConstant(BlendMask, MVT::i8)));
7306 llvm_unreachable("Not a supported integer vector type!");
7310 /// \brief Try to lower a vector shuffle as a byte rotation.
7312 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7313 /// byte-rotation of a the concatentation of two vectors. This routine will
7314 /// try to generically lower a vector shuffle through such an instruction. It
7315 /// does not check for the availability of PALIGNR-based lowerings, only the
7316 /// applicability of this strategy to the given mask. This matches shuffle
7317 /// vectors that look like:
7319 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7321 /// Essentially it concatenates V1 and V2, shifts right by some number of
7322 /// elements, and takes the low elements as the result. Note that while this is
7323 /// specified as a *right shift* because x86 is little-endian, it is a *left
7324 /// rotate* of the vector lanes.
7326 /// Note that this only handles 128-bit vector widths currently.
7327 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7330 SelectionDAG &DAG) {
7331 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7333 // We need to detect various ways of spelling a rotation:
7334 // [11, 12, 13, 14, 15, 0, 1, 2]
7335 // [-1, 12, 13, 14, -1, -1, 1, -1]
7336 // [-1, -1, -1, -1, -1, -1, 1, 2]
7337 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7338 // [-1, 4, 5, 6, -1, -1, 9, -1]
7339 // [-1, 4, 5, 6, -1, -1, -1, -1]
7342 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7345 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7347 // Based on the mod-Size value of this mask element determine where
7348 // a rotated vector would have started.
7349 int StartIdx = i - (Mask[i] % Size);
7351 // The identity rotation isn't interesting, stop.
7354 // If we found the tail of a vector the rotation must be the missing
7355 // front. If we found the head of a vector, it must be how much of the head.
7356 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7359 Rotation = CandidateRotation;
7360 else if (Rotation != CandidateRotation)
7361 // The rotations don't match, so we can't match this mask.
7364 // Compute which value this mask is pointing at.
7365 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7367 // Compute which of the two target values this index should be assigned to.
7368 // This reflects whether the high elements are remaining or the low elements
7370 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7372 // Either set up this value if we've not encountered it before, or check
7373 // that it remains consistent.
7376 else if (TargetV != MaskV)
7377 // This may be a rotation, but it pulls from the inputs in some
7378 // unsupported interleaving.
7382 // Check that we successfully analyzed the mask, and normalize the results.
7383 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7384 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7390 // Cast the inputs to v16i8 to match PALIGNR.
7391 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7392 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7394 assert(VT.getSizeInBits() == 128 &&
7395 "Rotate-based lowering only supports 128-bit lowering!");
7396 assert(Mask.size() <= 16 &&
7397 "Can shuffle at most 16 bytes in a 128-bit vector!");
7398 // The actual rotate instruction rotates bytes, so we need to scale the
7399 // rotation based on how many bytes are in the vector.
7400 int Scale = 16 / Mask.size();
7402 return DAG.getNode(ISD::BITCAST, DL, VT,
7403 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7404 DAG.getConstant(Rotation * Scale, MVT::i8)));
7407 /// \brief Compute whether each element of a shuffle is zeroable.
7409 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7410 /// Either it is an undef element in the shuffle mask, the element of the input
7411 /// referenced is undef, or the element of the input referenced is known to be
7412 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7413 /// as many lanes with this technique as possible to simplify the remaining
7415 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7416 SDValue V1, SDValue V2) {
7417 SmallBitVector Zeroable(Mask.size(), false);
7419 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7420 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7422 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7424 // Handle the easy cases.
7425 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7430 // If this is an index into a build_vector node, dig out the input value and
7432 SDValue V = M < Size ? V1 : V2;
7433 if (V.getOpcode() != ISD::BUILD_VECTOR)
7436 SDValue Input = V.getOperand(M % Size);
7437 // The UNDEF opcode check really should be dead code here, but not quite
7438 // worth asserting on (it isn't invalid, just unexpected).
7439 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7446 /// \brief Lower a vector shuffle as a zero or any extension.
7448 /// Given a specific number of elements, element bit width, and extension
7449 /// stride, produce either a zero or any extension based on the available
7450 /// features of the subtarget.
7451 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7452 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7453 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7454 assert(Scale > 1 && "Need a scale to extend.");
7455 int EltBits = VT.getSizeInBits() / NumElements;
7456 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7457 "Only 8, 16, and 32 bit elements can be extended.");
7458 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7460 // Found a valid zext mask! Try various lowering strategies based on the
7461 // input type and available ISA extensions.
7462 if (Subtarget->hasSSE41()) {
7463 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7464 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7465 NumElements / Scale);
7466 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7467 return DAG.getNode(ISD::BITCAST, DL, VT,
7468 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7471 // For any extends we can cheat for larger element sizes and use shuffle
7472 // instructions that can fold with a load and/or copy.
7473 if (AnyExt && EltBits == 32) {
7474 int PSHUFDMask[4] = {0, -1, 1, -1};
7476 ISD::BITCAST, DL, VT,
7477 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7478 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7479 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7481 if (AnyExt && EltBits == 16 && Scale > 2) {
7482 int PSHUFDMask[4] = {0, -1, 0, -1};
7483 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7484 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7485 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7486 int PSHUFHWMask[4] = {1, -1, -1, -1};
7488 ISD::BITCAST, DL, VT,
7489 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7490 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7491 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7494 // If this would require more than 2 unpack instructions to expand, use
7495 // pshufb when available. We can only use more than 2 unpack instructions
7496 // when zero extending i8 elements which also makes it easier to use pshufb.
7497 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7498 assert(NumElements == 16 && "Unexpected byte vector width!");
7499 SDValue PSHUFBMask[16];
7500 for (int i = 0; i < 16; ++i)
7502 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7503 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7504 return DAG.getNode(ISD::BITCAST, DL, VT,
7505 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7506 DAG.getNode(ISD::BUILD_VECTOR, DL,
7507 MVT::v16i8, PSHUFBMask)));
7510 // Otherwise emit a sequence of unpacks.
7512 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7513 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7514 : getZeroVector(InputVT, Subtarget, DAG, DL);
7515 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7516 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7520 } while (Scale > 1);
7521 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7524 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7526 /// This routine will try to do everything in its power to cleverly lower
7527 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7528 /// check for the profitability of this lowering, it tries to aggressively
7529 /// match this pattern. It will use all of the micro-architectural details it
7530 /// can to emit an efficient lowering. It handles both blends with all-zero
7531 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7532 /// masking out later).
7534 /// The reason we have dedicated lowering for zext-style shuffles is that they
7535 /// are both incredibly common and often quite performance sensitive.
7536 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7537 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7538 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7539 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7541 int Bits = VT.getSizeInBits();
7542 int NumElements = Mask.size();
7544 // Define a helper function to check a particular ext-scale and lower to it if
7546 auto Lower = [&](int Scale) -> SDValue {
7549 for (int i = 0; i < NumElements; ++i) {
7551 continue; // Valid anywhere but doesn't tell us anything.
7552 if (i % Scale != 0) {
7553 // Each of the extend elements needs to be zeroable.
7557 // We no lorger are in the anyext case.
7562 // Each of the base elements needs to be consecutive indices into the
7563 // same input vector.
7564 SDValue V = Mask[i] < NumElements ? V1 : V2;
7567 else if (InputV != V)
7568 return SDValue(); // Flip-flopping inputs.
7570 if (Mask[i] % NumElements != i / Scale)
7571 return SDValue(); // Non-consecutive strided elemenst.
7574 // If we fail to find an input, we have a zero-shuffle which should always
7575 // have already been handled.
7576 // FIXME: Maybe handle this here in case during blending we end up with one?
7580 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7581 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7584 // The widest scale possible for extending is to a 64-bit integer.
7585 assert(Bits % 64 == 0 &&
7586 "The number of bits in a vector must be divisible by 64 on x86!");
7587 int NumExtElements = Bits / 64;
7589 // Each iteration, try extending the elements half as much, but into twice as
7591 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7592 assert(NumElements % NumExtElements == 0 &&
7593 "The input vector size must be divisble by the extended size.");
7594 if (SDValue V = Lower(NumElements / NumExtElements))
7598 // No viable ext lowering found.
7602 /// \brief Try to lower insertion of a single element into a zero vector.
7604 /// This is a common pattern that we have especially efficient patterns to lower
7605 /// across all subtarget feature sets.
7606 static SDValue lowerVectorShuffleAsElementInsertion(
7607 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7608 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7609 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7611 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7612 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7614 if (Mask.size() == 2) {
7615 if (!Zeroable[V2Index ^ 1]) {
7616 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7617 // with 2 to flip from {2,3} to {0,1} and vice versa.
7618 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7619 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7620 if (Zeroable[V2Index])
7621 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7627 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7628 if (i != V2Index && !Zeroable[i])
7629 return SDValue(); // Not inserting into a zero vector.
7632 // Step over any bitcasts on either input so we can scan the actual
7633 // BUILD_VECTOR nodes.
7634 while (V1.getOpcode() == ISD::BITCAST)
7635 V1 = V1.getOperand(0);
7636 while (V2.getOpcode() == ISD::BITCAST)
7637 V2 = V2.getOperand(0);
7639 // Check for a single input from a SCALAR_TO_VECTOR node.
7640 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7641 // all the smarts here sunk into that routine. However, the current
7642 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7643 // vector shuffle lowering is dead.
7644 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7645 Mask[V2Index] == (int)Mask.size()) ||
7646 V2.getOpcode() == ISD::BUILD_VECTOR))
7649 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7651 // First, we need to zext the scalar if it is smaller than an i32.
7653 MVT EltVT = VT.getVectorElementType();
7654 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7655 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7656 // Zero-extend directly to i32.
7658 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7661 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7662 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7664 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7667 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7668 // the desired position. Otherwise it is more efficient to do a vector
7669 // shift left. We know that we can do a vector shift left because all
7670 // the inputs are zero.
7671 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7672 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7673 V2Shuffle[V2Index] = 0;
7674 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7676 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7678 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7680 V2Index * EltVT.getSizeInBits(),
7681 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7682 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7688 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7690 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7691 /// support for floating point shuffles but not integer shuffles. These
7692 /// instructions will incur a domain crossing penalty on some chips though so
7693 /// it is better to avoid lowering through this for integer vectors where
7695 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7696 const X86Subtarget *Subtarget,
7697 SelectionDAG &DAG) {
7699 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7700 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7701 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7702 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7703 ArrayRef<int> Mask = SVOp->getMask();
7704 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7706 if (isSingleInputShuffleMask(Mask)) {
7707 // Straight shuffle of a single input vector. Simulate this by using the
7708 // single input as both of the "inputs" to this instruction..
7709 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7711 if (Subtarget->hasAVX()) {
7712 // If we have AVX, we can use VPERMILPS which will allow folding a load
7713 // into the shuffle.
7714 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7715 DAG.getConstant(SHUFPDMask, MVT::i8));
7718 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7719 DAG.getConstant(SHUFPDMask, MVT::i8));
7721 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7722 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7724 // Use dedicated unpack instructions for masks that match their pattern.
7725 if (isShuffleEquivalent(Mask, 0, 2))
7726 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7727 if (isShuffleEquivalent(Mask, 1, 3))
7728 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7730 // If we have a single input, insert that into V1 if we can do so cheaply.
7731 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7732 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7733 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7736 if (Subtarget->hasSSE41())
7737 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7741 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7742 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7743 DAG.getConstant(SHUFPDMask, MVT::i8));
7746 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7748 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7749 /// the integer unit to minimize domain crossing penalties. However, for blends
7750 /// it falls back to the floating point shuffle operation with appropriate bit
7752 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7753 const X86Subtarget *Subtarget,
7754 SelectionDAG &DAG) {
7756 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7757 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7758 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7759 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7760 ArrayRef<int> Mask = SVOp->getMask();
7761 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7763 if (isSingleInputShuffleMask(Mask)) {
7764 // Straight shuffle of a single input vector. For everything from SSE2
7765 // onward this has a single fast instruction with no scary immediates.
7766 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7767 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7768 int WidenedMask[4] = {
7769 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7770 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7772 ISD::BITCAST, DL, MVT::v2i64,
7773 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7774 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7777 // Use dedicated unpack instructions for masks that match their pattern.
7778 if (isShuffleEquivalent(Mask, 0, 2))
7779 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7780 if (isShuffleEquivalent(Mask, 1, 3))
7781 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7783 // If we have a single input from V2 insert that into V1 if we can do so
7785 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7786 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7787 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7790 if (Subtarget->hasSSE41())
7791 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7795 // Try to use rotation instructions if available.
7796 if (Subtarget->hasSSSE3())
7797 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7798 DL, MVT::v2i64, V1, V2, Mask, DAG))
7801 // We implement this with SHUFPD which is pretty lame because it will likely
7802 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7803 // However, all the alternatives are still more cycles and newer chips don't
7804 // have this problem. It would be really nice if x86 had better shuffles here.
7805 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7806 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7807 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7808 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7811 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7813 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7814 /// It makes no assumptions about whether this is the *best* lowering, it simply
7816 static SDValue lowerVectorShuffleWithSHUPFS(SDLoc DL, MVT VT,
7817 ArrayRef<int> Mask, SDValue V1,
7818 SDValue V2, SelectionDAG &DAG) {
7819 SDValue LowV = V1, HighV = V2;
7820 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7823 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7825 if (NumV2Elements == 1) {
7827 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7830 // Compute the index adjacent to V2Index and in the same half by toggling
7832 int V2AdjIndex = V2Index ^ 1;
7834 if (Mask[V2AdjIndex] == -1) {
7835 // Handles all the cases where we have a single V2 element and an undef.
7836 // This will only ever happen in the high lanes because we commute the
7837 // vector otherwise.
7839 std::swap(LowV, HighV);
7840 NewMask[V2Index] -= 4;
7842 // Handle the case where the V2 element ends up adjacent to a V1 element.
7843 // To make this work, blend them together as the first step.
7844 int V1Index = V2AdjIndex;
7845 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7846 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7847 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7849 // Now proceed to reconstruct the final blend as we have the necessary
7850 // high or low half formed.
7857 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7858 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7860 } else if (NumV2Elements == 2) {
7861 if (Mask[0] < 4 && Mask[1] < 4) {
7862 // Handle the easy case where we have V1 in the low lanes and V2 in the
7863 // high lanes. We never see this reversed because we sort the shuffle.
7867 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7868 // trying to place elements directly, just blend them and set up the final
7869 // shuffle to place them.
7871 // The first two blend mask elements are for V1, the second two are for
7873 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7874 Mask[2] < 4 ? Mask[2] : Mask[3],
7875 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7876 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7877 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7878 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7880 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7883 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7884 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7885 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7886 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7889 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7890 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7893 /// \brief Lower 4-lane 32-bit floating point shuffles.
7895 /// Uses instructions exclusively from the floating point unit to minimize
7896 /// domain crossing penalties, as these are sufficient to implement all v4f32
7898 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7899 const X86Subtarget *Subtarget,
7900 SelectionDAG &DAG) {
7902 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7903 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7904 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7905 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7906 ArrayRef<int> Mask = SVOp->getMask();
7907 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7910 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7912 if (NumV2Elements == 0) {
7913 if (Subtarget->hasAVX()) {
7914 // If we have AVX, we can use VPERMILPS which will allow folding a load
7915 // into the shuffle.
7916 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7917 getV4X86ShuffleImm8ForMask(Mask, DAG));
7920 // Otherwise, use a straight shuffle of a single input vector. We pass the
7921 // input vector to both operands to simulate this with a SHUFPS.
7922 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7923 getV4X86ShuffleImm8ForMask(Mask, DAG));
7926 // Use dedicated unpack instructions for masks that match their pattern.
7927 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7928 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7929 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7930 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7932 // There are special ways we can lower some single-element blends. However, we
7933 // have custom ways we can lower more complex single-element blends below that
7934 // we defer to if both this and BLENDPS fail to match, so restrict this to
7935 // when the V2 input is targeting element 0 of the mask -- that is the fast
7937 if (NumV2Elements == 1 && Mask[0] >= 4)
7938 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
7939 Mask, Subtarget, DAG))
7942 if (Subtarget->hasSSE41())
7943 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7947 // Check for whether we can use INSERTPS to perform the blend. We only use
7948 // INSERTPS when the V1 elements are already in the correct locations
7949 // because otherwise we can just always use two SHUFPS instructions which
7950 // are much smaller to encode than a SHUFPS and an INSERTPS.
7951 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
7953 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7956 // When using INSERTPS we can zero any lane of the destination. Collect
7957 // the zero inputs into a mask and drop them from the lanes of V1 which
7958 // actually need to be present as inputs to the INSERTPS.
7959 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7961 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7962 bool InsertNeedsShuffle = false;
7964 for (int i = 0; i < 4; ++i)
7968 } else if (Mask[i] != i) {
7969 InsertNeedsShuffle = true;
7974 // We don't want to use INSERTPS or other insertion techniques if it will
7975 // require shuffling anyways.
7976 if (!InsertNeedsShuffle) {
7977 // If all of V1 is zeroable, replace it with undef.
7978 if ((ZMask | 1 << V2Index) == 0xF)
7979 V1 = DAG.getUNDEF(MVT::v4f32);
7981 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7982 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7984 // Insert the V2 element into the desired position.
7985 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7986 DAG.getConstant(InsertPSMask, MVT::i8));
7990 // Otherwise fall back to a SHUFPS lowering strategy.
7991 return lowerVectorShuffleWithSHUPFS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7994 /// \brief Lower 4-lane i32 vector shuffles.
7996 /// We try to handle these with integer-domain shuffles where we can, but for
7997 /// blends we use the floating point domain blend instructions.
7998 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7999 const X86Subtarget *Subtarget,
8000 SelectionDAG &DAG) {
8002 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8003 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8004 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8005 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8006 ArrayRef<int> Mask = SVOp->getMask();
8007 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8010 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8012 if (NumV2Elements == 0) {
8013 // Straight shuffle of a single input vector. For everything from SSE2
8014 // onward this has a single fast instruction with no scary immediates.
8015 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8016 // but we aren't actually going to use the UNPCK instruction because doing
8017 // so prevents folding a load into this instruction or making a copy.
8018 const int UnpackLoMask[] = {0, 0, 1, 1};
8019 const int UnpackHiMask[] = {2, 2, 3, 3};
8020 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8021 Mask = UnpackLoMask;
8022 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8023 Mask = UnpackHiMask;
8025 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8026 getV4X86ShuffleImm8ForMask(Mask, DAG));
8029 // Whenever we can lower this as a zext, that instruction is strictly faster
8030 // than any alternative.
8031 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8032 Mask, Subtarget, DAG))
8035 // Use dedicated unpack instructions for masks that match their pattern.
8036 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8037 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8038 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8039 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8041 // There are special ways we can lower some single-element blends.
8042 if (NumV2Elements == 1)
8043 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8044 Mask, Subtarget, DAG))
8047 if (Subtarget->hasSSE41())
8048 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8052 // Try to use rotation instructions if available.
8053 if (Subtarget->hasSSSE3())
8054 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8055 DL, MVT::v4i32, V1, V2, Mask, DAG))
8058 // We implement this with SHUFPS because it can blend from two vectors.
8059 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8060 // up the inputs, bypassing domain shift penalties that we would encur if we
8061 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8063 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8064 DAG.getVectorShuffle(
8066 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8067 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8070 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8071 /// shuffle lowering, and the most complex part.
8073 /// The lowering strategy is to try to form pairs of input lanes which are
8074 /// targeted at the same half of the final vector, and then use a dword shuffle
8075 /// to place them onto the right half, and finally unpack the paired lanes into
8076 /// their final position.
8078 /// The exact breakdown of how to form these dword pairs and align them on the
8079 /// correct sides is really tricky. See the comments within the function for
8080 /// more of the details.
8081 static SDValue lowerV8I16SingleInputVectorShuffle(
8082 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8083 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8084 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8085 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8086 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8088 SmallVector<int, 4> LoInputs;
8089 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8090 [](int M) { return M >= 0; });
8091 std::sort(LoInputs.begin(), LoInputs.end());
8092 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8093 SmallVector<int, 4> HiInputs;
8094 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8095 [](int M) { return M >= 0; });
8096 std::sort(HiInputs.begin(), HiInputs.end());
8097 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8099 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8100 int NumHToL = LoInputs.size() - NumLToL;
8102 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8103 int NumHToH = HiInputs.size() - NumLToH;
8104 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8105 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8106 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8107 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8109 // Use dedicated unpack instructions for masks that match their pattern.
8110 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8111 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8112 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8113 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8115 // Try to use rotation instructions if available.
8116 if (Subtarget->hasSSSE3())
8117 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8118 DL, MVT::v8i16, V, V, Mask, DAG))
8121 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8122 // such inputs we can swap two of the dwords across the half mark and end up
8123 // with <=2 inputs to each half in each half. Once there, we can fall through
8124 // to the generic code below. For example:
8126 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8127 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8129 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8130 // and an existing 2-into-2 on the other half. In this case we may have to
8131 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8132 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8133 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8134 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8135 // half than the one we target for fixing) will be fixed when we re-enter this
8136 // path. We will also combine away any sequence of PSHUFD instructions that
8137 // result into a single instruction. Here is an example of the tricky case:
8139 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8140 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8142 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8144 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8145 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8147 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8148 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8150 // The result is fine to be handled by the generic logic.
8151 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8152 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8153 int AOffset, int BOffset) {
8154 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8155 "Must call this with A having 3 or 1 inputs from the A half.");
8156 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8157 "Must call this with B having 1 or 3 inputs from the B half.");
8158 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8159 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8161 // Compute the index of dword with only one word among the three inputs in
8162 // a half by taking the sum of the half with three inputs and subtracting
8163 // the sum of the actual three inputs. The difference is the remaining
8166 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8167 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8168 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8169 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8170 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8171 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8172 int TripleNonInputIdx =
8173 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8174 TripleDWord = TripleNonInputIdx / 2;
8176 // We use xor with one to compute the adjacent DWord to whichever one the
8178 OneInputDWord = (OneInput / 2) ^ 1;
8180 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8181 // and BToA inputs. If there is also such a problem with the BToB and AToB
8182 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8183 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8184 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8185 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8186 // Compute how many inputs will be flipped by swapping these DWords. We
8188 // to balance this to ensure we don't form a 3-1 shuffle in the other
8190 int NumFlippedAToBInputs =
8191 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8192 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8193 int NumFlippedBToBInputs =
8194 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8195 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8196 if ((NumFlippedAToBInputs == 1 &&
8197 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8198 (NumFlippedBToBInputs == 1 &&
8199 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8200 // We choose whether to fix the A half or B half based on whether that
8201 // half has zero flipped inputs. At zero, we may not be able to fix it
8202 // with that half. We also bias towards fixing the B half because that
8203 // will more commonly be the high half, and we have to bias one way.
8204 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8205 ArrayRef<int> Inputs) {
8206 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8207 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8208 PinnedIdx ^ 1) != Inputs.end();
8209 // Determine whether the free index is in the flipped dword or the
8210 // unflipped dword based on where the pinned index is. We use this bit
8211 // in an xor to conditionally select the adjacent dword.
8212 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8213 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8214 FixFreeIdx) != Inputs.end();
8215 if (IsFixIdxInput == IsFixFreeIdxInput)
8217 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8218 FixFreeIdx) != Inputs.end();
8219 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8220 "We need to be changing the number of flipped inputs!");
8221 int PSHUFHalfMask[] = {0, 1, 2, 3};
8222 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8223 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8225 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8228 if (M != -1 && M == FixIdx)
8230 else if (M != -1 && M == FixFreeIdx)
8233 if (NumFlippedBToBInputs != 0) {
8235 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8236 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8238 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8240 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8241 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8246 int PSHUFDMask[] = {0, 1, 2, 3};
8247 PSHUFDMask[ADWord] = BDWord;
8248 PSHUFDMask[BDWord] = ADWord;
8249 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8250 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8251 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8252 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8254 // Adjust the mask to match the new locations of A and B.
8256 if (M != -1 && M/2 == ADWord)
8257 M = 2 * BDWord + M % 2;
8258 else if (M != -1 && M/2 == BDWord)
8259 M = 2 * ADWord + M % 2;
8261 // Recurse back into this routine to re-compute state now that this isn't
8262 // a 3 and 1 problem.
8263 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8266 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8267 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8268 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8269 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8271 // At this point there are at most two inputs to the low and high halves from
8272 // each half. That means the inputs can always be grouped into dwords and
8273 // those dwords can then be moved to the correct half with a dword shuffle.
8274 // We use at most one low and one high word shuffle to collect these paired
8275 // inputs into dwords, and finally a dword shuffle to place them.
8276 int PSHUFLMask[4] = {-1, -1, -1, -1};
8277 int PSHUFHMask[4] = {-1, -1, -1, -1};
8278 int PSHUFDMask[4] = {-1, -1, -1, -1};
8280 // First fix the masks for all the inputs that are staying in their
8281 // original halves. This will then dictate the targets of the cross-half
8283 auto fixInPlaceInputs =
8284 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8285 MutableArrayRef<int> SourceHalfMask,
8286 MutableArrayRef<int> HalfMask, int HalfOffset) {
8287 if (InPlaceInputs.empty())
8289 if (InPlaceInputs.size() == 1) {
8290 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8291 InPlaceInputs[0] - HalfOffset;
8292 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8295 if (IncomingInputs.empty()) {
8296 // Just fix all of the in place inputs.
8297 for (int Input : InPlaceInputs) {
8298 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8299 PSHUFDMask[Input / 2] = Input / 2;
8304 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8305 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8306 InPlaceInputs[0] - HalfOffset;
8307 // Put the second input next to the first so that they are packed into
8308 // a dword. We find the adjacent index by toggling the low bit.
8309 int AdjIndex = InPlaceInputs[0] ^ 1;
8310 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8311 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8312 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8314 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8315 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8317 // Now gather the cross-half inputs and place them into a free dword of
8318 // their target half.
8319 // FIXME: This operation could almost certainly be simplified dramatically to
8320 // look more like the 3-1 fixing operation.
8321 auto moveInputsToRightHalf = [&PSHUFDMask](
8322 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8323 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8324 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8326 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8327 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8329 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8331 int LowWord = Word & ~1;
8332 int HighWord = Word | 1;
8333 return isWordClobbered(SourceHalfMask, LowWord) ||
8334 isWordClobbered(SourceHalfMask, HighWord);
8337 if (IncomingInputs.empty())
8340 if (ExistingInputs.empty()) {
8341 // Map any dwords with inputs from them into the right half.
8342 for (int Input : IncomingInputs) {
8343 // If the source half mask maps over the inputs, turn those into
8344 // swaps and use the swapped lane.
8345 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8346 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8347 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8348 Input - SourceOffset;
8349 // We have to swap the uses in our half mask in one sweep.
8350 for (int &M : HalfMask)
8351 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8353 else if (M == Input)
8354 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8356 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8357 Input - SourceOffset &&
8358 "Previous placement doesn't match!");
8360 // Note that this correctly re-maps both when we do a swap and when
8361 // we observe the other side of the swap above. We rely on that to
8362 // avoid swapping the members of the input list directly.
8363 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8366 // Map the input's dword into the correct half.
8367 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8368 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8370 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8372 "Previous placement doesn't match!");
8375 // And just directly shift any other-half mask elements to be same-half
8376 // as we will have mirrored the dword containing the element into the
8377 // same position within that half.
8378 for (int &M : HalfMask)
8379 if (M >= SourceOffset && M < SourceOffset + 4) {
8380 M = M - SourceOffset + DestOffset;
8381 assert(M >= 0 && "This should never wrap below zero!");
8386 // Ensure we have the input in a viable dword of its current half. This
8387 // is particularly tricky because the original position may be clobbered
8388 // by inputs being moved and *staying* in that half.
8389 if (IncomingInputs.size() == 1) {
8390 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8391 int InputFixed = std::find(std::begin(SourceHalfMask),
8392 std::end(SourceHalfMask), -1) -
8393 std::begin(SourceHalfMask) + SourceOffset;
8394 SourceHalfMask[InputFixed - SourceOffset] =
8395 IncomingInputs[0] - SourceOffset;
8396 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8398 IncomingInputs[0] = InputFixed;
8400 } else if (IncomingInputs.size() == 2) {
8401 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8402 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8403 // We have two non-adjacent or clobbered inputs we need to extract from
8404 // the source half. To do this, we need to map them into some adjacent
8405 // dword slot in the source mask.
8406 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8407 IncomingInputs[1] - SourceOffset};
8409 // If there is a free slot in the source half mask adjacent to one of
8410 // the inputs, place the other input in it. We use (Index XOR 1) to
8411 // compute an adjacent index.
8412 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8413 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8414 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8415 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8416 InputsFixed[1] = InputsFixed[0] ^ 1;
8417 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8418 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8419 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8420 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8421 InputsFixed[0] = InputsFixed[1] ^ 1;
8422 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8423 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8424 // The two inputs are in the same DWord but it is clobbered and the
8425 // adjacent DWord isn't used at all. Move both inputs to the free
8427 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8428 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8429 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8430 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8432 // The only way we hit this point is if there is no clobbering
8433 // (because there are no off-half inputs to this half) and there is no
8434 // free slot adjacent to one of the inputs. In this case, we have to
8435 // swap an input with a non-input.
8436 for (int i = 0; i < 4; ++i)
8437 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8438 "We can't handle any clobbers here!");
8439 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8440 "Cannot have adjacent inputs here!");
8442 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8443 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8445 // We also have to update the final source mask in this case because
8446 // it may need to undo the above swap.
8447 for (int &M : FinalSourceHalfMask)
8448 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8449 M = InputsFixed[1] + SourceOffset;
8450 else if (M == InputsFixed[1] + SourceOffset)
8451 M = (InputsFixed[0] ^ 1) + SourceOffset;
8453 InputsFixed[1] = InputsFixed[0] ^ 1;
8456 // Point everything at the fixed inputs.
8457 for (int &M : HalfMask)
8458 if (M == IncomingInputs[0])
8459 M = InputsFixed[0] + SourceOffset;
8460 else if (M == IncomingInputs[1])
8461 M = InputsFixed[1] + SourceOffset;
8463 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8464 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8467 llvm_unreachable("Unhandled input size!");
8470 // Now hoist the DWord down to the right half.
8471 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8472 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8473 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8474 for (int &M : HalfMask)
8475 for (int Input : IncomingInputs)
8477 M = FreeDWord * 2 + Input % 2;
8479 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8480 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8481 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8482 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8484 // Now enact all the shuffles we've computed to move the inputs into their
8486 if (!isNoopShuffleMask(PSHUFLMask))
8487 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8488 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8489 if (!isNoopShuffleMask(PSHUFHMask))
8490 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8491 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8492 if (!isNoopShuffleMask(PSHUFDMask))
8493 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8494 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8495 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8496 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8498 // At this point, each half should contain all its inputs, and we can then
8499 // just shuffle them into their final position.
8500 assert(std::count_if(LoMask.begin(), LoMask.end(),
8501 [](int M) { return M >= 4; }) == 0 &&
8502 "Failed to lift all the high half inputs to the low mask!");
8503 assert(std::count_if(HiMask.begin(), HiMask.end(),
8504 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8505 "Failed to lift all the low half inputs to the high mask!");
8507 // Do a half shuffle for the low mask.
8508 if (!isNoopShuffleMask(LoMask))
8509 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8510 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8512 // Do a half shuffle with the high mask after shifting its values down.
8513 for (int &M : HiMask)
8516 if (!isNoopShuffleMask(HiMask))
8517 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8518 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8523 /// \brief Detect whether the mask pattern should be lowered through
8526 /// This essentially tests whether viewing the mask as an interleaving of two
8527 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8528 /// lowering it through interleaving is a significantly better strategy.
8529 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8530 int NumEvenInputs[2] = {0, 0};
8531 int NumOddInputs[2] = {0, 0};
8532 int NumLoInputs[2] = {0, 0};
8533 int NumHiInputs[2] = {0, 0};
8534 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8538 int InputIdx = Mask[i] >= Size;
8541 ++NumLoInputs[InputIdx];
8543 ++NumHiInputs[InputIdx];
8546 ++NumEvenInputs[InputIdx];
8548 ++NumOddInputs[InputIdx];
8551 // The minimum number of cross-input results for both the interleaved and
8552 // split cases. If interleaving results in fewer cross-input results, return
8554 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8555 NumEvenInputs[0] + NumOddInputs[1]);
8556 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8557 NumLoInputs[0] + NumHiInputs[1]);
8558 return InterleavedCrosses < SplitCrosses;
8561 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8563 /// This strategy only works when the inputs from each vector fit into a single
8564 /// half of that vector, and generally there are not so many inputs as to leave
8565 /// the in-place shuffles required highly constrained (and thus expensive). It
8566 /// shifts all the inputs into a single side of both input vectors and then
8567 /// uses an unpack to interleave these inputs in a single vector. At that
8568 /// point, we will fall back on the generic single input shuffle lowering.
8569 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8571 MutableArrayRef<int> Mask,
8572 const X86Subtarget *Subtarget,
8573 SelectionDAG &DAG) {
8574 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8575 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8576 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8577 for (int i = 0; i < 8; ++i)
8578 if (Mask[i] >= 0 && Mask[i] < 4)
8579 LoV1Inputs.push_back(i);
8580 else if (Mask[i] >= 4 && Mask[i] < 8)
8581 HiV1Inputs.push_back(i);
8582 else if (Mask[i] >= 8 && Mask[i] < 12)
8583 LoV2Inputs.push_back(i);
8584 else if (Mask[i] >= 12)
8585 HiV2Inputs.push_back(i);
8587 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8588 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8591 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8592 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8593 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8595 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8596 HiV1Inputs.size() + HiV2Inputs.size();
8598 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8599 ArrayRef<int> HiInputs, bool MoveToLo,
8601 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8602 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8603 if (BadInputs.empty())
8606 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8607 int MoveOffset = MoveToLo ? 0 : 4;
8609 if (GoodInputs.empty()) {
8610 for (int BadInput : BadInputs) {
8611 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8612 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8615 if (GoodInputs.size() == 2) {
8616 // If the low inputs are spread across two dwords, pack them into
8618 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8619 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8620 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8621 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8623 // Otherwise pin the good inputs.
8624 for (int GoodInput : GoodInputs)
8625 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8628 if (BadInputs.size() == 2) {
8629 // If we have two bad inputs then there may be either one or two good
8630 // inputs fixed in place. Find a fixed input, and then find the *other*
8631 // two adjacent indices by using modular arithmetic.
8633 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8634 [](int M) { return M >= 0; }) -
8635 std::begin(MoveMask);
8637 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8638 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8639 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8640 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8641 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8642 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8643 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8645 assert(BadInputs.size() == 1 && "All sizes handled");
8646 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8647 std::end(MoveMask), -1) -
8648 std::begin(MoveMask);
8649 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8650 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8654 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8657 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8659 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8662 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8663 // cross-half traffic in the final shuffle.
8665 // Munge the mask to be a single-input mask after the unpack merges the
8669 M = 2 * (M % 4) + (M / 8);
8671 return DAG.getVectorShuffle(
8672 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8673 DL, MVT::v8i16, V1, V2),
8674 DAG.getUNDEF(MVT::v8i16), Mask);
8677 /// \brief Generic lowering of 8-lane i16 shuffles.
8679 /// This handles both single-input shuffles and combined shuffle/blends with
8680 /// two inputs. The single input shuffles are immediately delegated to
8681 /// a dedicated lowering routine.
8683 /// The blends are lowered in one of three fundamental ways. If there are few
8684 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8685 /// of the input is significantly cheaper when lowered as an interleaving of
8686 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8687 /// halves of the inputs separately (making them have relatively few inputs)
8688 /// and then concatenate them.
8689 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8690 const X86Subtarget *Subtarget,
8691 SelectionDAG &DAG) {
8693 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8694 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8695 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8697 ArrayRef<int> OrigMask = SVOp->getMask();
8698 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8699 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8700 MutableArrayRef<int> Mask(MaskStorage);
8702 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8704 // Whenever we can lower this as a zext, that instruction is strictly faster
8705 // than any alternative.
8706 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8707 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8710 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8711 auto isV2 = [](int M) { return M >= 8; };
8713 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8714 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8716 if (NumV2Inputs == 0)
8717 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8719 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8720 "to be V1-input shuffles.");
8722 // There are special ways we can lower some single-element blends.
8723 if (NumV2Inputs == 1)
8724 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8725 Mask, Subtarget, DAG))
8728 if (Subtarget->hasSSE41())
8729 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8733 // Try to use rotation instructions if available.
8734 if (Subtarget->hasSSSE3())
8735 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8738 if (NumV1Inputs + NumV2Inputs <= 4)
8739 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8741 // Check whether an interleaving lowering is likely to be more efficient.
8742 // This isn't perfect but it is a strong heuristic that tends to work well on
8743 // the kinds of shuffles that show up in practice.
8745 // FIXME: Handle 1x, 2x, and 4x interleaving.
8746 if (shouldLowerAsInterleaving(Mask)) {
8747 // FIXME: Figure out whether we should pack these into the low or high
8750 int EMask[8], OMask[8];
8751 for (int i = 0; i < 4; ++i) {
8752 EMask[i] = Mask[2*i];
8753 OMask[i] = Mask[2*i + 1];
8758 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8759 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8761 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8764 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8765 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8767 for (int i = 0; i < 4; ++i) {
8768 LoBlendMask[i] = Mask[i];
8769 HiBlendMask[i] = Mask[i + 4];
8772 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8773 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8774 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8775 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8777 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8778 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8781 /// \brief Check whether a compaction lowering can be done by dropping even
8782 /// elements and compute how many times even elements must be dropped.
8784 /// This handles shuffles which take every Nth element where N is a power of
8785 /// two. Example shuffle masks:
8787 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8788 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8789 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8790 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8791 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8792 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8794 /// Any of these lanes can of course be undef.
8796 /// This routine only supports N <= 3.
8797 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8800 /// \returns N above, or the number of times even elements must be dropped if
8801 /// there is such a number. Otherwise returns zero.
8802 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8803 // Figure out whether we're looping over two inputs or just one.
8804 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8806 // The modulus for the shuffle vector entries is based on whether this is
8807 // a single input or not.
8808 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8809 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8810 "We should only be called with masks with a power-of-2 size!");
8812 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8814 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8815 // and 2^3 simultaneously. This is because we may have ambiguity with
8816 // partially undef inputs.
8817 bool ViableForN[3] = {true, true, true};
8819 for (int i = 0, e = Mask.size(); i < e; ++i) {
8820 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8825 bool IsAnyViable = false;
8826 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8827 if (ViableForN[j]) {
8830 // The shuffle mask must be equal to (i * 2^N) % M.
8831 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8834 ViableForN[j] = false;
8836 // Early exit if we exhaust the possible powers of two.
8841 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8845 // Return 0 as there is no viable power of two.
8849 /// \brief Generic lowering of v16i8 shuffles.
8851 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8852 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8853 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8854 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8856 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8857 const X86Subtarget *Subtarget,
8858 SelectionDAG &DAG) {
8860 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8861 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8862 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8863 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8864 ArrayRef<int> OrigMask = SVOp->getMask();
8865 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8867 // Try to use rotation instructions if available.
8868 if (Subtarget->hasSSSE3())
8869 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8873 // Try to use a zext lowering.
8874 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8875 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8878 int MaskStorage[16] = {
8879 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8880 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8881 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8882 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8883 MutableArrayRef<int> Mask(MaskStorage);
8884 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8885 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8888 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8890 // For single-input shuffles, there are some nicer lowering tricks we can use.
8891 if (NumV2Elements == 0) {
8892 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8893 // Notably, this handles splat and partial-splat shuffles more efficiently.
8894 // However, it only makes sense if the pre-duplication shuffle simplifies
8895 // things significantly. Currently, this means we need to be able to
8896 // express the pre-duplication shuffle as an i16 shuffle.
8898 // FIXME: We should check for other patterns which can be widened into an
8899 // i16 shuffle as well.
8900 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8901 for (int i = 0; i < 16; i += 2)
8902 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8907 auto tryToWidenViaDuplication = [&]() -> SDValue {
8908 if (!canWidenViaDuplication(Mask))
8910 SmallVector<int, 4> LoInputs;
8911 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8912 [](int M) { return M >= 0 && M < 8; });
8913 std::sort(LoInputs.begin(), LoInputs.end());
8914 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8916 SmallVector<int, 4> HiInputs;
8917 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8918 [](int M) { return M >= 8; });
8919 std::sort(HiInputs.begin(), HiInputs.end());
8920 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8923 bool TargetLo = LoInputs.size() >= HiInputs.size();
8924 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8925 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8927 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8928 SmallDenseMap<int, int, 8> LaneMap;
8929 for (int I : InPlaceInputs) {
8930 PreDupI16Shuffle[I/2] = I/2;
8933 int j = TargetLo ? 0 : 4, je = j + 4;
8934 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8935 // Check if j is already a shuffle of this input. This happens when
8936 // there are two adjacent bytes after we move the low one.
8937 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8938 // If we haven't yet mapped the input, search for a slot into which
8940 while (j < je && PreDupI16Shuffle[j] != -1)
8944 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8947 // Map this input with the i16 shuffle.
8948 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8951 // Update the lane map based on the mapping we ended up with.
8952 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8955 ISD::BITCAST, DL, MVT::v16i8,
8956 DAG.getVectorShuffle(MVT::v8i16, DL,
8957 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8958 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8960 // Unpack the bytes to form the i16s that will be shuffled into place.
8961 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8962 MVT::v16i8, V1, V1);
8964 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8965 for (int i = 0; i < 16; i += 2) {
8967 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8968 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8971 ISD::BITCAST, DL, MVT::v16i8,
8972 DAG.getVectorShuffle(MVT::v8i16, DL,
8973 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8974 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8976 if (SDValue V = tryToWidenViaDuplication())
8980 // Check whether an interleaving lowering is likely to be more efficient.
8981 // This isn't perfect but it is a strong heuristic that tends to work well on
8982 // the kinds of shuffles that show up in practice.
8984 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8985 if (shouldLowerAsInterleaving(Mask)) {
8986 // FIXME: Figure out whether we should pack these into the low or high
8989 int EMask[16], OMask[16];
8990 for (int i = 0; i < 8; ++i) {
8991 EMask[i] = Mask[2*i];
8992 OMask[i] = Mask[2*i + 1];
8997 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8998 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9000 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9003 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9004 // with PSHUFB. It is important to do this before we attempt to generate any
9005 // blends but after all of the single-input lowerings. If the single input
9006 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9007 // want to preserve that and we can DAG combine any longer sequences into
9008 // a PSHUFB in the end. But once we start blending from multiple inputs,
9009 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9010 // and there are *very* few patterns that would actually be faster than the
9011 // PSHUFB approach because of its ability to zero lanes.
9013 // FIXME: The only exceptions to the above are blends which are exact
9014 // interleavings with direct instructions supporting them. We currently don't
9015 // handle those well here.
9016 if (Subtarget->hasSSSE3()) {
9019 for (int i = 0; i < 16; ++i)
9020 if (Mask[i] == -1) {
9021 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9023 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9025 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9027 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9028 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9029 if (isSingleInputShuffleMask(Mask))
9030 return V1; // Single inputs are easy.
9032 // Otherwise, blend the two.
9033 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9034 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9035 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9038 // There are special ways we can lower some single-element blends.
9039 if (NumV2Elements == 1)
9040 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9041 Mask, Subtarget, DAG))
9044 // Check whether a compaction lowering can be done. This handles shuffles
9045 // which take every Nth element for some even N. See the helper function for
9048 // We special case these as they can be particularly efficiently handled with
9049 // the PACKUSB instruction on x86 and they show up in common patterns of
9050 // rearranging bytes to truncate wide elements.
9051 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9052 // NumEvenDrops is the power of two stride of the elements. Another way of
9053 // thinking about it is that we need to drop the even elements this many
9054 // times to get the original input.
9055 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9057 // First we need to zero all the dropped bytes.
9058 assert(NumEvenDrops <= 3 &&
9059 "No support for dropping even elements more than 3 times.");
9060 // We use the mask type to pick which bytes are preserved based on how many
9061 // elements are dropped.
9062 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9063 SDValue ByteClearMask =
9064 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9065 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9066 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9068 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9070 // Now pack things back together.
9071 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9072 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9073 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9074 for (int i = 1; i < NumEvenDrops; ++i) {
9075 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9076 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9082 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9083 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9084 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9085 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9087 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9088 MutableArrayRef<int> V1HalfBlendMask,
9089 MutableArrayRef<int> V2HalfBlendMask) {
9090 for (int i = 0; i < 8; ++i)
9091 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9092 V1HalfBlendMask[i] = HalfMask[i];
9094 } else if (HalfMask[i] >= 16) {
9095 V2HalfBlendMask[i] = HalfMask[i] - 16;
9096 HalfMask[i] = i + 8;
9099 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9100 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9102 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9104 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9105 MutableArrayRef<int> HiBlendMask) {
9107 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9108 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9110 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9111 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9112 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9113 [](int M) { return M >= 0 && M % 2 == 1; })) {
9114 // Use a mask to drop the high bytes.
9115 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9116 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9117 DAG.getConstant(0x00FF, MVT::v8i16));
9119 // This will be a single vector shuffle instead of a blend so nuke V2.
9120 V2 = DAG.getUNDEF(MVT::v8i16);
9122 // Squash the masks to point directly into V1.
9123 for (int &M : LoBlendMask)
9126 for (int &M : HiBlendMask)
9130 // Otherwise just unpack the low half of V into V1 and the high half into
9131 // V2 so that we can blend them as i16s.
9132 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9133 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9134 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9135 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9138 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9139 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9140 return std::make_pair(BlendedLo, BlendedHi);
9142 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9143 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9144 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9146 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9147 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9149 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9152 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9154 /// This routine breaks down the specific type of 128-bit shuffle and
9155 /// dispatches to the lowering routines accordingly.
9156 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9157 MVT VT, const X86Subtarget *Subtarget,
9158 SelectionDAG &DAG) {
9159 switch (VT.SimpleTy) {
9161 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9163 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9165 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9167 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9169 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9171 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9174 llvm_unreachable("Unimplemented!");
9178 /// \brief Test whether there are elements crossing 128-bit lanes in this
9181 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
9182 /// and we routinely test for these.
9183 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
9184 int LaneSize = 128 / VT.getScalarSizeInBits();
9185 int Size = Mask.size();
9186 for (int i = 0; i < Size; ++i)
9187 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9192 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
9194 /// This checks a shuffle mask to see if it is performing the same
9195 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
9196 /// that it is also not lane-crossing.
9197 static bool is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask) {
9198 int LaneSize = 128 / VT.getScalarSizeInBits();
9199 int Size = Mask.size();
9200 for (int i = LaneSize; i < Size; ++i)
9201 if (Mask[i] >= 0 && Mask[i] != (Mask[i % LaneSize] + (i / LaneSize) * LaneSize))
9206 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9209 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9210 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9211 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9212 /// we encode the logic here for specific shuffle lowering routines to bail to
9213 /// when they exhaust the features avaible to more directly handle the shuffle.
9214 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9216 const X86Subtarget *Subtarget,
9217 SelectionDAG &DAG) {
9219 MVT VT = Op.getSimpleValueType();
9220 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9221 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9222 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9223 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9224 ArrayRef<int> Mask = SVOp->getMask();
9226 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9227 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9229 int NumElements = VT.getVectorNumElements();
9230 int SplitNumElements = NumElements / 2;
9231 MVT ScalarVT = VT.getScalarType();
9232 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9234 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9235 DAG.getIntPtrConstant(0));
9236 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9237 DAG.getIntPtrConstant(SplitNumElements));
9238 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9239 DAG.getIntPtrConstant(0));
9240 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9241 DAG.getIntPtrConstant(SplitNumElements));
9243 // Now create two 4-way blends of these half-width vectors.
9244 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9245 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9246 for (int i = 0; i < SplitNumElements; ++i) {
9247 int M = HalfMask[i];
9248 if (M >= NumElements) {
9249 V2BlendMask.push_back(M - NumElements);
9250 V1BlendMask.push_back(-1);
9251 BlendMask.push_back(SplitNumElements + i);
9252 } else if (M >= 0) {
9253 V2BlendMask.push_back(-1);
9254 V1BlendMask.push_back(M);
9255 BlendMask.push_back(i);
9257 V2BlendMask.push_back(-1);
9258 V1BlendMask.push_back(-1);
9259 BlendMask.push_back(-1);
9262 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9263 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9264 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9266 SDValue Lo = HalfBlend(LoMask);
9267 SDValue Hi = HalfBlend(HiMask);
9268 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9271 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9273 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9274 /// isn't available.
9275 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9276 const X86Subtarget *Subtarget,
9277 SelectionDAG &DAG) {
9279 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9280 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9281 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9282 ArrayRef<int> Mask = SVOp->getMask();
9283 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9285 if (is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask))
9286 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9288 if (isSingleInputShuffleMask(Mask)) {
9289 // Non-half-crossing single input shuffles can be lowerid with an
9290 // interleaved permutation.
9291 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9292 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9293 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9294 DAG.getConstant(VPERMILPMask, MVT::i8));
9297 // X86 has dedicated unpack instructions that can handle specific blend
9298 // operations: UNPCKH and UNPCKL.
9299 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9300 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9301 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9302 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9304 // If we have a single input to the zero element, insert that into V1 if we
9305 // can do so cheaply.
9307 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9308 if (NumV2Elements == 1 && Mask[0] >= 4)
9309 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9310 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9313 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9317 // Check if the blend happens to exactly fit that of SHUFPD.
9318 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9319 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9320 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9321 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9322 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9323 DAG.getConstant(SHUFPDMask, MVT::i8));
9325 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9326 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9327 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9328 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9329 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9330 DAG.getConstant(SHUFPDMask, MVT::i8));
9333 // Shuffle the input elements into the desired positions in V1 and V2 and
9334 // blend them together.
9335 int V1Mask[] = {-1, -1, -1, -1};
9336 int V2Mask[] = {-1, -1, -1, -1};
9337 for (int i = 0; i < 4; ++i)
9338 if (Mask[i] >= 0 && Mask[i] < 4)
9339 V1Mask[i] = Mask[i];
9340 else if (Mask[i] >= 4)
9341 V2Mask[i] = Mask[i] - 4;
9343 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
9344 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
9346 unsigned BlendMask = 0;
9347 for (int i = 0; i < 4; ++i)
9349 BlendMask |= 1 << i;
9351 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
9352 DAG.getConstant(BlendMask, MVT::i8));
9355 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9357 /// This routine is only called when we have AVX2 and thus a reasonable
9358 /// instruction set for v4i64 shuffling..
9359 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9360 const X86Subtarget *Subtarget,
9361 SelectionDAG &DAG) {
9363 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9364 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9366 ArrayRef<int> Mask = SVOp->getMask();
9367 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9368 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9370 // FIXME: Actually implement this using AVX2!!!
9371 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
9372 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
9373 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
9374 DAG.getVectorShuffle(MVT::v4f64, DL, V1, V2, Mask));
9377 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9379 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9380 /// isn't available.
9381 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9382 const X86Subtarget *Subtarget,
9383 SelectionDAG &DAG) {
9385 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9386 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9387 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9388 ArrayRef<int> Mask = SVOp->getMask();
9389 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9391 if (is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9392 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9394 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9398 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9399 // options to efficiently lower the shuffle.
9400 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask)) {
9401 ArrayRef<int> LoMask = Mask.slice(0, 4);
9402 if (isSingleInputShuffleMask(Mask))
9403 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9404 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9406 // Use dedicated unpack instructions for masks that match their pattern.
9407 if (isShuffleEquivalent(LoMask, 0, 8, 1, 9))
9408 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9409 if (isShuffleEquivalent(LoMask, 2, 10, 3, 11))
9410 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9412 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9413 // have already handled any direct blends.
9414 int SHUFPSMask[] = {Mask[0], Mask[1], Mask[2], Mask[3]};
9415 for (int &M : SHUFPSMask)
9418 return lowerVectorShuffleWithSHUPFS(DL, MVT::v8f32, SHUFPSMask, V1, V2, DAG);
9421 // If we have a single input shuffle with different shuffle patterns in the
9422 // two 128-bit lanes use the variable mask to VPERMILPS.
9423 if (isSingleInputShuffleMask(Mask)) {
9424 SDValue VPermMask[8];
9425 for (int i = 0; i < 8; ++i)
9426 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9427 : DAG.getConstant(Mask[i], MVT::i32);
9429 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9430 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9433 // Shuffle the input elements into the desired positions in V1 and V2 and
9434 // blend them together.
9435 int V1Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9436 int V2Mask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9437 unsigned BlendMask = 0;
9438 for (int i = 0; i < 8; ++i)
9439 if (Mask[i] >= 0 && Mask[i] < 8) {
9440 V1Mask[i] = Mask[i];
9441 } else if (Mask[i] >= 8) {
9442 V2Mask[i] = Mask[i] - 8;
9443 BlendMask |= 1 << i;
9446 V1 = DAG.getVectorShuffle(MVT::v8f32, DL, V1, DAG.getUNDEF(MVT::v8f32), V1Mask);
9447 V2 = DAG.getVectorShuffle(MVT::v8f32, DL, V2, DAG.getUNDEF(MVT::v8f32), V2Mask);
9449 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v8f32, V1, V2,
9450 DAG.getConstant(BlendMask, MVT::i8));
9453 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9455 /// This routine is only called when we have AVX2 and thus a reasonable
9456 /// instruction set for v8i32 shuffling..
9457 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9458 const X86Subtarget *Subtarget,
9459 SelectionDAG &DAG) {
9461 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9462 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9463 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9464 ArrayRef<int> Mask = SVOp->getMask();
9465 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9466 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9468 // FIXME: Actually implement this using AVX2!!!
9469 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V1);
9470 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8f32, V2);
9471 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i32,
9472 DAG.getVectorShuffle(MVT::v8f32, DL, V1, V2, Mask));
9475 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9477 /// This routine is only called when we have AVX2 and thus a reasonable
9478 /// instruction set for v16i16 shuffling..
9479 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9480 const X86Subtarget *Subtarget,
9481 SelectionDAG &DAG) {
9483 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9484 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9485 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9486 ArrayRef<int> Mask = SVOp->getMask();
9487 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9488 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9490 // FIXME: Actually implement this using AVX2!!!
9492 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9495 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9497 /// This routine is only called when we have AVX2 and thus a reasonable
9498 /// instruction set for v32i8 shuffling..
9499 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9500 const X86Subtarget *Subtarget,
9501 SelectionDAG &DAG) {
9503 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9504 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9505 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9506 ArrayRef<int> Mask = SVOp->getMask();
9507 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9508 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9510 // FIXME: Actually implement this using AVX2!!!
9512 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9515 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9517 /// This routine either breaks down the specific type of a 256-bit x86 vector
9518 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9519 /// together based on the available instructions.
9520 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9521 MVT VT, const X86Subtarget *Subtarget,
9522 SelectionDAG &DAG) {
9524 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9525 ArrayRef<int> Mask = SVOp->getMask();
9527 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9528 // check for those subtargets here and avoid much of the subtarget querying in
9529 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9530 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9531 // floating point types there eventually, just immediately cast everything to
9532 // a float and operate entirely in that domain.
9533 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9534 int ElementBits = VT.getScalarSizeInBits();
9535 if (ElementBits < 32)
9536 // No floating point type available, decompose into 128-bit vectors.
9537 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9539 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9540 VT.getVectorNumElements());
9541 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9542 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9543 return DAG.getNode(ISD::BITCAST, DL, VT,
9544 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9547 switch (VT.SimpleTy) {
9549 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9551 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9553 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9555 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9557 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9559 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9562 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9566 /// \brief Tiny helper function to test whether a shuffle mask could be
9567 /// simplified by widening the elements being shuffled.
9568 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9569 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9570 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9571 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9572 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9578 /// \brief Top-level lowering for x86 vector shuffles.
9580 /// This handles decomposition, canonicalization, and lowering of all x86
9581 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9582 /// above in helper routines. The canonicalization attempts to widen shuffles
9583 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9584 /// s.t. only one of the two inputs needs to be tested, etc.
9585 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9586 SelectionDAG &DAG) {
9587 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9588 ArrayRef<int> Mask = SVOp->getMask();
9589 SDValue V1 = Op.getOperand(0);
9590 SDValue V2 = Op.getOperand(1);
9591 MVT VT = Op.getSimpleValueType();
9592 int NumElements = VT.getVectorNumElements();
9595 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9597 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9598 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9599 if (V1IsUndef && V2IsUndef)
9600 return DAG.getUNDEF(VT);
9602 // When we create a shuffle node we put the UNDEF node to second operand,
9603 // but in some cases the first operand may be transformed to UNDEF.
9604 // In this case we should just commute the node.
9606 return DAG.getCommutedVectorShuffle(*SVOp);
9608 // Check for non-undef masks pointing at an undef vector and make the masks
9609 // undef as well. This makes it easier to match the shuffle based solely on
9613 if (M >= NumElements) {
9614 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9615 for (int &M : NewMask)
9616 if (M >= NumElements)
9618 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9621 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9622 // lanes but wider integers. We cap this to not form integers larger than i64
9623 // but it might be interesting to form i128 integers to handle flipping the
9624 // low and high halves of AVX 256-bit vectors.
9625 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9626 canWidenShuffleElements(Mask)) {
9627 SmallVector<int, 8> NewMask;
9628 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9629 NewMask.push_back(Mask[i] != -1
9631 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9633 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9634 VT.getVectorNumElements() / 2);
9635 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9636 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9637 return DAG.getNode(ISD::BITCAST, dl, VT,
9638 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9641 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9642 for (int M : SVOp->getMask())
9645 else if (M < NumElements)
9650 // Commute the shuffle as needed such that more elements come from V1 than
9651 // V2. This allows us to match the shuffle pattern strictly on how many
9652 // elements come from V1 without handling the symmetric cases.
9653 if (NumV2Elements > NumV1Elements)
9654 return DAG.getCommutedVectorShuffle(*SVOp);
9656 // When the number of V1 and V2 elements are the same, try to minimize the
9657 // number of uses of V2 in the low half of the vector. When that is tied,
9658 // ensure that the sum of indices for V1 is equal to or lower than the sum
9660 if (NumV1Elements == NumV2Elements) {
9661 int LowV1Elements = 0, LowV2Elements = 0;
9662 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9663 if (M >= NumElements)
9667 if (LowV2Elements > LowV1Elements)
9668 return DAG.getCommutedVectorShuffle(*SVOp);
9670 int SumV1Indices = 0, SumV2Indices = 0;
9671 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
9672 if (SVOp->getMask()[i] >= NumElements)
9674 else if (SVOp->getMask()[i] >= 0)
9676 if (SumV2Indices < SumV1Indices)
9677 return DAG.getCommutedVectorShuffle(*SVOp);
9680 // For each vector width, delegate to a specialized lowering routine.
9681 if (VT.getSizeInBits() == 128)
9682 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9684 if (VT.getSizeInBits() == 256)
9685 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9687 llvm_unreachable("Unimplemented!");
9691 //===----------------------------------------------------------------------===//
9692 // Legacy vector shuffle lowering
9694 // This code is the legacy code handling vector shuffles until the above
9695 // replaces its functionality and performance.
9696 //===----------------------------------------------------------------------===//
9698 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9699 bool hasInt256, unsigned *MaskOut = nullptr) {
9700 MVT EltVT = VT.getVectorElementType();
9702 // There is no blend with immediate in AVX-512.
9703 if (VT.is512BitVector())
9706 if (!hasSSE41 || EltVT == MVT::i8)
9708 if (!hasInt256 && VT == MVT::v16i16)
9711 unsigned MaskValue = 0;
9712 unsigned NumElems = VT.getVectorNumElements();
9713 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9714 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9715 unsigned NumElemsInLane = NumElems / NumLanes;
9717 // Blend for v16i16 should be symetric for the both lanes.
9718 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9720 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9721 int EltIdx = MaskVals[i];
9723 if ((EltIdx < 0 || EltIdx == (int)i) &&
9724 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9727 if (((unsigned)EltIdx == (i + NumElems)) &&
9728 (SndLaneEltIdx < 0 ||
9729 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9730 MaskValue |= (1 << i);
9736 *MaskOut = MaskValue;
9740 // Try to lower a shuffle node into a simple blend instruction.
9741 // This function assumes isBlendMask returns true for this
9742 // SuffleVectorSDNode
9743 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9745 const X86Subtarget *Subtarget,
9746 SelectionDAG &DAG) {
9747 MVT VT = SVOp->getSimpleValueType(0);
9748 MVT EltVT = VT.getVectorElementType();
9749 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9750 Subtarget->hasInt256() && "Trying to lower a "
9751 "VECTOR_SHUFFLE to a Blend but "
9752 "with the wrong mask"));
9753 SDValue V1 = SVOp->getOperand(0);
9754 SDValue V2 = SVOp->getOperand(1);
9756 unsigned NumElems = VT.getVectorNumElements();
9758 // Convert i32 vectors to floating point if it is not AVX2.
9759 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9761 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9762 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9764 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9765 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9768 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9769 DAG.getConstant(MaskValue, MVT::i32));
9770 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9773 /// In vector type \p VT, return true if the element at index \p InputIdx
9774 /// falls on a different 128-bit lane than \p OutputIdx.
9775 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9776 unsigned OutputIdx) {
9777 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9778 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9781 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9782 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9783 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9784 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9786 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9787 SelectionDAG &DAG) {
9788 MVT VT = V1.getSimpleValueType();
9789 assert(VT.is128BitVector() || VT.is256BitVector());
9791 MVT EltVT = VT.getVectorElementType();
9792 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9793 unsigned NumElts = VT.getVectorNumElements();
9795 SmallVector<SDValue, 32> PshufbMask;
9796 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9797 int InputIdx = MaskVals[OutputIdx];
9798 unsigned InputByteIdx;
9800 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9801 InputByteIdx = 0x80;
9803 // Cross lane is not allowed.
9804 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9806 InputByteIdx = InputIdx * EltSizeInBytes;
9807 // Index is an byte offset within the 128-bit lane.
9808 InputByteIdx &= 0xf;
9811 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9812 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9813 if (InputByteIdx != 0x80)
9818 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9820 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9821 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9822 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9825 // v8i16 shuffles - Prefer shuffles in the following order:
9826 // 1. [all] pshuflw, pshufhw, optional move
9827 // 2. [ssse3] 1 x pshufb
9828 // 3. [ssse3] 2 x pshufb + 1 x por
9829 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9831 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9832 SelectionDAG &DAG) {
9833 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9834 SDValue V1 = SVOp->getOperand(0);
9835 SDValue V2 = SVOp->getOperand(1);
9837 SmallVector<int, 8> MaskVals;
9839 // Determine if more than 1 of the words in each of the low and high quadwords
9840 // of the result come from the same quadword of one of the two inputs. Undef
9841 // mask values count as coming from any quadword, for better codegen.
9843 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9844 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9845 unsigned LoQuad[] = { 0, 0, 0, 0 };
9846 unsigned HiQuad[] = { 0, 0, 0, 0 };
9847 // Indices of quads used.
9848 std::bitset<4> InputQuads;
9849 for (unsigned i = 0; i < 8; ++i) {
9850 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9851 int EltIdx = SVOp->getMaskElt(i);
9852 MaskVals.push_back(EltIdx);
9861 InputQuads.set(EltIdx / 4);
9864 int BestLoQuad = -1;
9865 unsigned MaxQuad = 1;
9866 for (unsigned i = 0; i < 4; ++i) {
9867 if (LoQuad[i] > MaxQuad) {
9869 MaxQuad = LoQuad[i];
9873 int BestHiQuad = -1;
9875 for (unsigned i = 0; i < 4; ++i) {
9876 if (HiQuad[i] > MaxQuad) {
9878 MaxQuad = HiQuad[i];
9882 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9883 // of the two input vectors, shuffle them into one input vector so only a
9884 // single pshufb instruction is necessary. If there are more than 2 input
9885 // quads, disable the next transformation since it does not help SSSE3.
9886 bool V1Used = InputQuads[0] || InputQuads[1];
9887 bool V2Used = InputQuads[2] || InputQuads[3];
9888 if (Subtarget->hasSSSE3()) {
9889 if (InputQuads.count() == 2 && V1Used && V2Used) {
9890 BestLoQuad = InputQuads[0] ? 0 : 1;
9891 BestHiQuad = InputQuads[2] ? 2 : 3;
9893 if (InputQuads.count() > 2) {
9899 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9900 // the shuffle mask. If a quad is scored as -1, that means that it contains
9901 // words from all 4 input quadwords.
9903 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9905 BestLoQuad < 0 ? 0 : BestLoQuad,
9906 BestHiQuad < 0 ? 1 : BestHiQuad
9908 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9909 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9910 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9911 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9913 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9914 // source words for the shuffle, to aid later transformations.
9915 bool AllWordsInNewV = true;
9916 bool InOrder[2] = { true, true };
9917 for (unsigned i = 0; i != 8; ++i) {
9918 int idx = MaskVals[i];
9920 InOrder[i/4] = false;
9921 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9923 AllWordsInNewV = false;
9927 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9928 if (AllWordsInNewV) {
9929 for (int i = 0; i != 8; ++i) {
9930 int idx = MaskVals[i];
9933 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9934 if ((idx != i) && idx < 4)
9936 if ((idx != i) && idx > 3)
9945 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9946 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9947 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9948 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9949 unsigned TargetMask = 0;
9950 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9951 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9952 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9953 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9954 getShufflePSHUFLWImmediate(SVOp);
9955 V1 = NewV.getOperand(0);
9956 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9960 // Promote splats to a larger type which usually leads to more efficient code.
9961 // FIXME: Is this true if pshufb is available?
9962 if (SVOp->isSplat())
9963 return PromoteSplat(SVOp, DAG);
9965 // If we have SSSE3, and all words of the result are from 1 input vector,
9966 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9967 // is present, fall back to case 4.
9968 if (Subtarget->hasSSSE3()) {
9969 SmallVector<SDValue,16> pshufbMask;
9971 // If we have elements from both input vectors, set the high bit of the
9972 // shuffle mask element to zero out elements that come from V2 in the V1
9973 // mask, and elements that come from V1 in the V2 mask, so that the two
9974 // results can be OR'd together.
9975 bool TwoInputs = V1Used && V2Used;
9976 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9978 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9980 // Calculate the shuffle mask for the second input, shuffle it, and
9981 // OR it with the first shuffled input.
9982 CommuteVectorShuffleMask(MaskVals, 8);
9983 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9984 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9985 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9988 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9989 // and update MaskVals with new element order.
9990 std::bitset<8> InOrder;
9991 if (BestLoQuad >= 0) {
9992 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9993 for (int i = 0; i != 4; ++i) {
9994 int idx = MaskVals[i];
9997 } else if ((idx / 4) == BestLoQuad) {
10002 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10005 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10006 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10007 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10008 NewV.getOperand(0),
10009 getShufflePSHUFLWImmediate(SVOp), DAG);
10013 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10014 // and update MaskVals with the new element order.
10015 if (BestHiQuad >= 0) {
10016 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10017 for (unsigned i = 4; i != 8; ++i) {
10018 int idx = MaskVals[i];
10021 } else if ((idx / 4) == BestHiQuad) {
10022 MaskV[i] = (idx & 3) + 4;
10026 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10029 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10030 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10031 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10032 NewV.getOperand(0),
10033 getShufflePSHUFHWImmediate(SVOp), DAG);
10037 // In case BestHi & BestLo were both -1, which means each quadword has a word
10038 // from each of the four input quadwords, calculate the InOrder bitvector now
10039 // before falling through to the insert/extract cleanup.
10040 if (BestLoQuad == -1 && BestHiQuad == -1) {
10042 for (int i = 0; i != 8; ++i)
10043 if (MaskVals[i] < 0 || MaskVals[i] == i)
10047 // The other elements are put in the right place using pextrw and pinsrw.
10048 for (unsigned i = 0; i != 8; ++i) {
10051 int EltIdx = MaskVals[i];
10054 SDValue ExtOp = (EltIdx < 8) ?
10055 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10056 DAG.getIntPtrConstant(EltIdx)) :
10057 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10058 DAG.getIntPtrConstant(EltIdx - 8));
10059 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10060 DAG.getIntPtrConstant(i));
10065 /// \brief v16i16 shuffles
10067 /// FIXME: We only support generation of a single pshufb currently. We can
10068 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10069 /// well (e.g 2 x pshufb + 1 x por).
10071 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10072 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10073 SDValue V1 = SVOp->getOperand(0);
10074 SDValue V2 = SVOp->getOperand(1);
10077 if (V2.getOpcode() != ISD::UNDEF)
10080 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10081 return getPSHUFB(MaskVals, V1, dl, DAG);
10084 // v16i8 shuffles - Prefer shuffles in the following order:
10085 // 1. [ssse3] 1 x pshufb
10086 // 2. [ssse3] 2 x pshufb + 1 x por
10087 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10088 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10089 const X86Subtarget* Subtarget,
10090 SelectionDAG &DAG) {
10091 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10092 SDValue V1 = SVOp->getOperand(0);
10093 SDValue V2 = SVOp->getOperand(1);
10095 ArrayRef<int> MaskVals = SVOp->getMask();
10097 // Promote splats to a larger type which usually leads to more efficient code.
10098 // FIXME: Is this true if pshufb is available?
10099 if (SVOp->isSplat())
10100 return PromoteSplat(SVOp, DAG);
10102 // If we have SSSE3, case 1 is generated when all result bytes come from
10103 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10104 // present, fall back to case 3.
10106 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10107 if (Subtarget->hasSSSE3()) {
10108 SmallVector<SDValue,16> pshufbMask;
10110 // If all result elements are from one input vector, then only translate
10111 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10113 // Otherwise, we have elements from both input vectors, and must zero out
10114 // elements that come from V2 in the first mask, and V1 in the second mask
10115 // so that we can OR them together.
10116 for (unsigned i = 0; i != 16; ++i) {
10117 int EltIdx = MaskVals[i];
10118 if (EltIdx < 0 || EltIdx >= 16)
10120 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10122 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10123 DAG.getNode(ISD::BUILD_VECTOR, dl,
10124 MVT::v16i8, pshufbMask));
10126 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10127 // the 2nd operand if it's undefined or zero.
10128 if (V2.getOpcode() == ISD::UNDEF ||
10129 ISD::isBuildVectorAllZeros(V2.getNode()))
10132 // Calculate the shuffle mask for the second input, shuffle it, and
10133 // OR it with the first shuffled input.
10134 pshufbMask.clear();
10135 for (unsigned i = 0; i != 16; ++i) {
10136 int EltIdx = MaskVals[i];
10137 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10138 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10140 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10141 DAG.getNode(ISD::BUILD_VECTOR, dl,
10142 MVT::v16i8, pshufbMask));
10143 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10146 // No SSSE3 - Calculate in place words and then fix all out of place words
10147 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10148 // the 16 different words that comprise the two doublequadword input vectors.
10149 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10150 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10152 for (int i = 0; i != 8; ++i) {
10153 int Elt0 = MaskVals[i*2];
10154 int Elt1 = MaskVals[i*2+1];
10156 // This word of the result is all undef, skip it.
10157 if (Elt0 < 0 && Elt1 < 0)
10160 // This word of the result is already in the correct place, skip it.
10161 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10164 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10165 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10168 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10169 // using a single extract together, load it and store it.
10170 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10171 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10172 DAG.getIntPtrConstant(Elt1 / 2));
10173 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10174 DAG.getIntPtrConstant(i));
10178 // If Elt1 is defined, extract it from the appropriate source. If the
10179 // source byte is not also odd, shift the extracted word left 8 bits
10180 // otherwise clear the bottom 8 bits if we need to do an or.
10182 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10183 DAG.getIntPtrConstant(Elt1 / 2));
10184 if ((Elt1 & 1) == 0)
10185 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10187 TLI.getShiftAmountTy(InsElt.getValueType())));
10188 else if (Elt0 >= 0)
10189 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10190 DAG.getConstant(0xFF00, MVT::i16));
10192 // If Elt0 is defined, extract it from the appropriate source. If the
10193 // source byte is not also even, shift the extracted word right 8 bits. If
10194 // Elt1 was also defined, OR the extracted values together before
10195 // inserting them in the result.
10197 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10198 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10199 if ((Elt0 & 1) != 0)
10200 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10202 TLI.getShiftAmountTy(InsElt0.getValueType())));
10203 else if (Elt1 >= 0)
10204 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10205 DAG.getConstant(0x00FF, MVT::i16));
10206 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10209 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10210 DAG.getIntPtrConstant(i));
10212 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10215 // v32i8 shuffles - Translate to VPSHUFB if possible.
10217 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10218 const X86Subtarget *Subtarget,
10219 SelectionDAG &DAG) {
10220 MVT VT = SVOp->getSimpleValueType(0);
10221 SDValue V1 = SVOp->getOperand(0);
10222 SDValue V2 = SVOp->getOperand(1);
10224 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10226 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10227 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10228 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10230 // VPSHUFB may be generated if
10231 // (1) one of input vector is undefined or zeroinitializer.
10232 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10233 // And (2) the mask indexes don't cross the 128-bit lane.
10234 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10235 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10238 if (V1IsAllZero && !V2IsAllZero) {
10239 CommuteVectorShuffleMask(MaskVals, 32);
10242 return getPSHUFB(MaskVals, V1, dl, DAG);
10245 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10246 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10247 /// done when every pair / quad of shuffle mask elements point to elements in
10248 /// the right sequence. e.g.
10249 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10251 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10252 SelectionDAG &DAG) {
10253 MVT VT = SVOp->getSimpleValueType(0);
10255 unsigned NumElems = VT.getVectorNumElements();
10258 switch (VT.SimpleTy) {
10259 default: llvm_unreachable("Unexpected!");
10262 return SDValue(SVOp, 0);
10263 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10264 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10265 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10266 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10267 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10268 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10271 SmallVector<int, 8> MaskVec;
10272 for (unsigned i = 0; i != NumElems; i += Scale) {
10274 for (unsigned j = 0; j != Scale; ++j) {
10275 int EltIdx = SVOp->getMaskElt(i+j);
10279 StartIdx = (EltIdx / Scale);
10280 if (EltIdx != (int)(StartIdx*Scale + j))
10283 MaskVec.push_back(StartIdx);
10286 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10287 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10288 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10291 /// getVZextMovL - Return a zero-extending vector move low node.
10293 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10294 SDValue SrcOp, SelectionDAG &DAG,
10295 const X86Subtarget *Subtarget, SDLoc dl) {
10296 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10297 LoadSDNode *LD = nullptr;
10298 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10299 LD = dyn_cast<LoadSDNode>(SrcOp);
10301 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10303 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10304 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10305 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10306 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10307 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10309 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10310 return DAG.getNode(ISD::BITCAST, dl, VT,
10311 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10312 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10314 SrcOp.getOperand(0)
10320 return DAG.getNode(ISD::BITCAST, dl, VT,
10321 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10322 DAG.getNode(ISD::BITCAST, dl,
10326 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10327 /// which could not be matched by any known target speficic shuffle
10329 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10331 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10332 if (NewOp.getNode())
10335 MVT VT = SVOp->getSimpleValueType(0);
10337 unsigned NumElems = VT.getVectorNumElements();
10338 unsigned NumLaneElems = NumElems / 2;
10341 MVT EltVT = VT.getVectorElementType();
10342 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10345 SmallVector<int, 16> Mask;
10346 for (unsigned l = 0; l < 2; ++l) {
10347 // Build a shuffle mask for the output, discovering on the fly which
10348 // input vectors to use as shuffle operands (recorded in InputUsed).
10349 // If building a suitable shuffle vector proves too hard, then bail
10350 // out with UseBuildVector set.
10351 bool UseBuildVector = false;
10352 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10353 unsigned LaneStart = l * NumLaneElems;
10354 for (unsigned i = 0; i != NumLaneElems; ++i) {
10355 // The mask element. This indexes into the input.
10356 int Idx = SVOp->getMaskElt(i+LaneStart);
10358 // the mask element does not index into any input vector.
10359 Mask.push_back(-1);
10363 // The input vector this mask element indexes into.
10364 int Input = Idx / NumLaneElems;
10366 // Turn the index into an offset from the start of the input vector.
10367 Idx -= Input * NumLaneElems;
10369 // Find or create a shuffle vector operand to hold this input.
10371 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10372 if (InputUsed[OpNo] == Input)
10373 // This input vector is already an operand.
10375 if (InputUsed[OpNo] < 0) {
10376 // Create a new operand for this input vector.
10377 InputUsed[OpNo] = Input;
10382 if (OpNo >= array_lengthof(InputUsed)) {
10383 // More than two input vectors used! Give up on trying to create a
10384 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10385 UseBuildVector = true;
10389 // Add the mask index for the new shuffle vector.
10390 Mask.push_back(Idx + OpNo * NumLaneElems);
10393 if (UseBuildVector) {
10394 SmallVector<SDValue, 16> SVOps;
10395 for (unsigned i = 0; i != NumLaneElems; ++i) {
10396 // The mask element. This indexes into the input.
10397 int Idx = SVOp->getMaskElt(i+LaneStart);
10399 SVOps.push_back(DAG.getUNDEF(EltVT));
10403 // The input vector this mask element indexes into.
10404 int Input = Idx / NumElems;
10406 // Turn the index into an offset from the start of the input vector.
10407 Idx -= Input * NumElems;
10409 // Extract the vector element by hand.
10410 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10411 SVOp->getOperand(Input),
10412 DAG.getIntPtrConstant(Idx)));
10415 // Construct the output using a BUILD_VECTOR.
10416 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10417 } else if (InputUsed[0] < 0) {
10418 // No input vectors were used! The result is undefined.
10419 Output[l] = DAG.getUNDEF(NVT);
10421 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10422 (InputUsed[0] % 2) * NumLaneElems,
10424 // If only one input was used, use an undefined vector for the other.
10425 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10426 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10427 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10428 // At least one input vector was used. Create a new shuffle vector.
10429 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10435 // Concatenate the result back
10436 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10439 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10440 /// 4 elements, and match them with several different shuffle types.
10442 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10443 SDValue V1 = SVOp->getOperand(0);
10444 SDValue V2 = SVOp->getOperand(1);
10446 MVT VT = SVOp->getSimpleValueType(0);
10448 assert(VT.is128BitVector() && "Unsupported vector size");
10450 std::pair<int, int> Locs[4];
10451 int Mask1[] = { -1, -1, -1, -1 };
10452 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10454 unsigned NumHi = 0;
10455 unsigned NumLo = 0;
10456 for (unsigned i = 0; i != 4; ++i) {
10457 int Idx = PermMask[i];
10459 Locs[i] = std::make_pair(-1, -1);
10461 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10463 Locs[i] = std::make_pair(0, NumLo);
10464 Mask1[NumLo] = Idx;
10467 Locs[i] = std::make_pair(1, NumHi);
10469 Mask1[2+NumHi] = Idx;
10475 if (NumLo <= 2 && NumHi <= 2) {
10476 // If no more than two elements come from either vector. This can be
10477 // implemented with two shuffles. First shuffle gather the elements.
10478 // The second shuffle, which takes the first shuffle as both of its
10479 // vector operands, put the elements into the right order.
10480 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10482 int Mask2[] = { -1, -1, -1, -1 };
10484 for (unsigned i = 0; i != 4; ++i)
10485 if (Locs[i].first != -1) {
10486 unsigned Idx = (i < 2) ? 0 : 4;
10487 Idx += Locs[i].first * 2 + Locs[i].second;
10491 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10494 if (NumLo == 3 || NumHi == 3) {
10495 // Otherwise, we must have three elements from one vector, call it X, and
10496 // one element from the other, call it Y. First, use a shufps to build an
10497 // intermediate vector with the one element from Y and the element from X
10498 // that will be in the same half in the final destination (the indexes don't
10499 // matter). Then, use a shufps to build the final vector, taking the half
10500 // containing the element from Y from the intermediate, and the other half
10503 // Normalize it so the 3 elements come from V1.
10504 CommuteVectorShuffleMask(PermMask, 4);
10508 // Find the element from V2.
10510 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10511 int Val = PermMask[HiIndex];
10518 Mask1[0] = PermMask[HiIndex];
10520 Mask1[2] = PermMask[HiIndex^1];
10522 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10524 if (HiIndex >= 2) {
10525 Mask1[0] = PermMask[0];
10526 Mask1[1] = PermMask[1];
10527 Mask1[2] = HiIndex & 1 ? 6 : 4;
10528 Mask1[3] = HiIndex & 1 ? 4 : 6;
10529 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10532 Mask1[0] = HiIndex & 1 ? 2 : 0;
10533 Mask1[1] = HiIndex & 1 ? 0 : 2;
10534 Mask1[2] = PermMask[2];
10535 Mask1[3] = PermMask[3];
10540 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10543 // Break it into (shuffle shuffle_hi, shuffle_lo).
10544 int LoMask[] = { -1, -1, -1, -1 };
10545 int HiMask[] = { -1, -1, -1, -1 };
10547 int *MaskPtr = LoMask;
10548 unsigned MaskIdx = 0;
10549 unsigned LoIdx = 0;
10550 unsigned HiIdx = 2;
10551 for (unsigned i = 0; i != 4; ++i) {
10558 int Idx = PermMask[i];
10560 Locs[i] = std::make_pair(-1, -1);
10561 } else if (Idx < 4) {
10562 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10563 MaskPtr[LoIdx] = Idx;
10566 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10567 MaskPtr[HiIdx] = Idx;
10572 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10573 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10574 int MaskOps[] = { -1, -1, -1, -1 };
10575 for (unsigned i = 0; i != 4; ++i)
10576 if (Locs[i].first != -1)
10577 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10578 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10581 static bool MayFoldVectorLoad(SDValue V) {
10582 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10583 V = V.getOperand(0);
10585 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10586 V = V.getOperand(0);
10587 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10588 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10589 // BUILD_VECTOR (load), undef
10590 V = V.getOperand(0);
10592 return MayFoldLoad(V);
10596 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10597 MVT VT = Op.getSimpleValueType();
10599 // Canonizalize to v2f64.
10600 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10601 return DAG.getNode(ISD::BITCAST, dl, VT,
10602 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10607 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10609 SDValue V1 = Op.getOperand(0);
10610 SDValue V2 = Op.getOperand(1);
10611 MVT VT = Op.getSimpleValueType();
10613 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10615 if (HasSSE2 && VT == MVT::v2f64)
10616 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10618 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10619 return DAG.getNode(ISD::BITCAST, dl, VT,
10620 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10621 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10622 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10626 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10627 SDValue V1 = Op.getOperand(0);
10628 SDValue V2 = Op.getOperand(1);
10629 MVT VT = Op.getSimpleValueType();
10631 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10632 "unsupported shuffle type");
10634 if (V2.getOpcode() == ISD::UNDEF)
10638 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10642 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10643 SDValue V1 = Op.getOperand(0);
10644 SDValue V2 = Op.getOperand(1);
10645 MVT VT = Op.getSimpleValueType();
10646 unsigned NumElems = VT.getVectorNumElements();
10648 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10649 // operand of these instructions is only memory, so check if there's a
10650 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10652 bool CanFoldLoad = false;
10654 // Trivial case, when V2 comes from a load.
10655 if (MayFoldVectorLoad(V2))
10656 CanFoldLoad = true;
10658 // When V1 is a load, it can be folded later into a store in isel, example:
10659 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10661 // (MOVLPSmr addr:$src1, VR128:$src2)
10662 // So, recognize this potential and also use MOVLPS or MOVLPD
10663 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10664 CanFoldLoad = true;
10666 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10668 if (HasSSE2 && NumElems == 2)
10669 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10672 // If we don't care about the second element, proceed to use movss.
10673 if (SVOp->getMaskElt(1) != -1)
10674 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10677 // movl and movlp will both match v2i64, but v2i64 is never matched by
10678 // movl earlier because we make it strict to avoid messing with the movlp load
10679 // folding logic (see the code above getMOVLP call). Match it here then,
10680 // this is horrible, but will stay like this until we move all shuffle
10681 // matching to x86 specific nodes. Note that for the 1st condition all
10682 // types are matched with movsd.
10684 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10685 // as to remove this logic from here, as much as possible
10686 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10687 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10688 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10691 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10693 // Invert the operand order and use SHUFPS to match it.
10694 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10695 getShuffleSHUFImmediate(SVOp), DAG);
10698 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10699 SelectionDAG &DAG) {
10701 MVT VT = Load->getSimpleValueType(0);
10702 MVT EVT = VT.getVectorElementType();
10703 SDValue Addr = Load->getOperand(1);
10704 SDValue NewAddr = DAG.getNode(
10705 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10706 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10709 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10710 DAG.getMachineFunction().getMachineMemOperand(
10711 Load->getMemOperand(), 0, EVT.getStoreSize()));
10715 // It is only safe to call this function if isINSERTPSMask is true for
10716 // this shufflevector mask.
10717 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10718 SelectionDAG &DAG) {
10719 // Generate an insertps instruction when inserting an f32 from memory onto a
10720 // v4f32 or when copying a member from one v4f32 to another.
10721 // We also use it for transferring i32 from one register to another,
10722 // since it simply copies the same bits.
10723 // If we're transferring an i32 from memory to a specific element in a
10724 // register, we output a generic DAG that will match the PINSRD
10726 MVT VT = SVOp->getSimpleValueType(0);
10727 MVT EVT = VT.getVectorElementType();
10728 SDValue V1 = SVOp->getOperand(0);
10729 SDValue V2 = SVOp->getOperand(1);
10730 auto Mask = SVOp->getMask();
10731 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10732 "unsupported vector type for insertps/pinsrd");
10734 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10735 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10736 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10740 unsigned DestIndex;
10744 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10747 // If we have 1 element from each vector, we have to check if we're
10748 // changing V1's element's place. If so, we're done. Otherwise, we
10749 // should assume we're changing V2's element's place and behave
10751 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10752 assert(DestIndex <= INT32_MAX && "truncated destination index");
10753 if (FromV1 == FromV2 &&
10754 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10758 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10761 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10762 "More than one element from V1 and from V2, or no elements from one "
10763 "of the vectors. This case should not have returned true from "
10768 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10771 // Get an index into the source vector in the range [0,4) (the mask is
10772 // in the range [0,8) because it can address V1 and V2)
10773 unsigned SrcIndex = Mask[DestIndex] % 4;
10774 if (MayFoldLoad(From)) {
10775 // Trivial case, when From comes from a load and is only used by the
10776 // shuffle. Make it use insertps from the vector that we need from that
10779 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10780 if (!NewLoad.getNode())
10783 if (EVT == MVT::f32) {
10784 // Create this as a scalar to vector to match the instruction pattern.
10785 SDValue LoadScalarToVector =
10786 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10787 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10788 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10790 } else { // EVT == MVT::i32
10791 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10792 // instruction, to match the PINSRD instruction, which loads an i32 to a
10793 // certain vector element.
10794 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10795 DAG.getConstant(DestIndex, MVT::i32));
10799 // Vector-element-to-vector
10800 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10801 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10804 // Reduce a vector shuffle to zext.
10805 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10806 SelectionDAG &DAG) {
10807 // PMOVZX is only available from SSE41.
10808 if (!Subtarget->hasSSE41())
10811 MVT VT = Op.getSimpleValueType();
10813 // Only AVX2 support 256-bit vector integer extending.
10814 if (!Subtarget->hasInt256() && VT.is256BitVector())
10817 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10819 SDValue V1 = Op.getOperand(0);
10820 SDValue V2 = Op.getOperand(1);
10821 unsigned NumElems = VT.getVectorNumElements();
10823 // Extending is an unary operation and the element type of the source vector
10824 // won't be equal to or larger than i64.
10825 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10826 VT.getVectorElementType() == MVT::i64)
10829 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10830 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10831 while ((1U << Shift) < NumElems) {
10832 if (SVOp->getMaskElt(1U << Shift) == 1)
10835 // The maximal ratio is 8, i.e. from i8 to i64.
10840 // Check the shuffle mask.
10841 unsigned Mask = (1U << Shift) - 1;
10842 for (unsigned i = 0; i != NumElems; ++i) {
10843 int EltIdx = SVOp->getMaskElt(i);
10844 if ((i & Mask) != 0 && EltIdx != -1)
10846 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10850 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10851 MVT NeVT = MVT::getIntegerVT(NBits);
10852 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10854 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10857 // Simplify the operand as it's prepared to be fed into shuffle.
10858 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10859 if (V1.getOpcode() == ISD::BITCAST &&
10860 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10861 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10862 V1.getOperand(0).getOperand(0)
10863 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10864 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10865 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10866 ConstantSDNode *CIdx =
10867 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10868 // If it's foldable, i.e. normal load with single use, we will let code
10869 // selection to fold it. Otherwise, we will short the conversion sequence.
10870 if (CIdx && CIdx->getZExtValue() == 0 &&
10871 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10872 MVT FullVT = V.getSimpleValueType();
10873 MVT V1VT = V1.getSimpleValueType();
10874 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10875 // The "ext_vec_elt" node is wider than the result node.
10876 // In this case we should extract subvector from V.
10877 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10878 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10879 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10880 FullVT.getVectorNumElements()/Ratio);
10881 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10882 DAG.getIntPtrConstant(0));
10884 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10888 return DAG.getNode(ISD::BITCAST, DL, VT,
10889 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10892 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10893 SelectionDAG &DAG) {
10894 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10895 MVT VT = Op.getSimpleValueType();
10897 SDValue V1 = Op.getOperand(0);
10898 SDValue V2 = Op.getOperand(1);
10900 if (isZeroShuffle(SVOp))
10901 return getZeroVector(VT, Subtarget, DAG, dl);
10903 // Handle splat operations
10904 if (SVOp->isSplat()) {
10905 // Use vbroadcast whenever the splat comes from a foldable load
10906 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10907 if (Broadcast.getNode())
10911 // Check integer expanding shuffles.
10912 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10913 if (NewOp.getNode())
10916 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10918 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10919 VT == MVT::v32i8) {
10920 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10921 if (NewOp.getNode())
10922 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10923 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10924 // FIXME: Figure out a cleaner way to do this.
10925 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10926 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10927 if (NewOp.getNode()) {
10928 MVT NewVT = NewOp.getSimpleValueType();
10929 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10930 NewVT, true, false))
10931 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10934 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10935 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10936 if (NewOp.getNode()) {
10937 MVT NewVT = NewOp.getSimpleValueType();
10938 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10939 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10948 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10949 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10950 SDValue V1 = Op.getOperand(0);
10951 SDValue V2 = Op.getOperand(1);
10952 MVT VT = Op.getSimpleValueType();
10954 unsigned NumElems = VT.getVectorNumElements();
10955 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10956 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10957 bool V1IsSplat = false;
10958 bool V2IsSplat = false;
10959 bool HasSSE2 = Subtarget->hasSSE2();
10960 bool HasFp256 = Subtarget->hasFp256();
10961 bool HasInt256 = Subtarget->hasInt256();
10962 MachineFunction &MF = DAG.getMachineFunction();
10963 bool OptForSize = MF.getFunction()->getAttributes().
10964 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10966 // Check if we should use the experimental vector shuffle lowering. If so,
10967 // delegate completely to that code path.
10968 if (ExperimentalVectorShuffleLowering)
10969 return lowerVectorShuffle(Op, Subtarget, DAG);
10971 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10973 if (V1IsUndef && V2IsUndef)
10974 return DAG.getUNDEF(VT);
10976 // When we create a shuffle node we put the UNDEF node to second operand,
10977 // but in some cases the first operand may be transformed to UNDEF.
10978 // In this case we should just commute the node.
10980 return DAG.getCommutedVectorShuffle(*SVOp);
10982 // Vector shuffle lowering takes 3 steps:
10984 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10985 // narrowing and commutation of operands should be handled.
10986 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10988 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10989 // so the shuffle can be broken into other shuffles and the legalizer can
10990 // try the lowering again.
10992 // The general idea is that no vector_shuffle operation should be left to
10993 // be matched during isel, all of them must be converted to a target specific
10996 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10997 // narrowing and commutation of operands should be handled. The actual code
10998 // doesn't include all of those, work in progress...
10999 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11000 if (NewOp.getNode())
11003 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11005 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11006 // unpckh_undef). Only use pshufd if speed is more important than size.
11007 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11008 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11009 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11010 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11012 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11013 V2IsUndef && MayFoldVectorLoad(V1))
11014 return getMOVDDup(Op, dl, V1, DAG);
11016 if (isMOVHLPS_v_undef_Mask(M, VT))
11017 return getMOVHighToLow(Op, dl, DAG);
11019 // Use to match splats
11020 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11021 (VT == MVT::v2f64 || VT == MVT::v2i64))
11022 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11024 if (isPSHUFDMask(M, VT)) {
11025 // The actual implementation will match the mask in the if above and then
11026 // during isel it can match several different instructions, not only pshufd
11027 // as its name says, sad but true, emulate the behavior for now...
11028 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11029 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11031 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11033 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11034 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11036 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11037 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11040 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11044 if (isPALIGNRMask(M, VT, Subtarget))
11045 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11046 getShufflePALIGNRImmediate(SVOp),
11049 if (isVALIGNMask(M, VT, Subtarget))
11050 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11051 getShuffleVALIGNImmediate(SVOp),
11054 // Check if this can be converted into a logical shift.
11055 bool isLeft = false;
11056 unsigned ShAmt = 0;
11058 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11059 if (isShift && ShVal.hasOneUse()) {
11060 // If the shifted value has multiple uses, it may be cheaper to use
11061 // v_set0 + movlhps or movhlps, etc.
11062 MVT EltVT = VT.getVectorElementType();
11063 ShAmt *= EltVT.getSizeInBits();
11064 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11067 if (isMOVLMask(M, VT)) {
11068 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11069 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11070 if (!isMOVLPMask(M, VT)) {
11071 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11072 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11074 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11075 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11079 // FIXME: fold these into legal mask.
11080 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11081 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11083 if (isMOVHLPSMask(M, VT))
11084 return getMOVHighToLow(Op, dl, DAG);
11086 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11087 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11089 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11090 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11092 if (isMOVLPMask(M, VT))
11093 return getMOVLP(Op, dl, DAG, HasSSE2);
11095 if (ShouldXformToMOVHLPS(M, VT) ||
11096 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11097 return DAG.getCommutedVectorShuffle(*SVOp);
11100 // No better options. Use a vshldq / vsrldq.
11101 MVT EltVT = VT.getVectorElementType();
11102 ShAmt *= EltVT.getSizeInBits();
11103 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11106 bool Commuted = false;
11107 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11108 // 1,1,1,1 -> v8i16 though.
11109 BitVector UndefElements;
11110 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11111 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11113 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11114 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11117 // Canonicalize the splat or undef, if present, to be on the RHS.
11118 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11119 CommuteVectorShuffleMask(M, NumElems);
11121 std::swap(V1IsSplat, V2IsSplat);
11125 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11126 // Shuffling low element of v1 into undef, just return v1.
11129 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11130 // the instruction selector will not match, so get a canonical MOVL with
11131 // swapped operands to undo the commute.
11132 return getMOVL(DAG, dl, VT, V2, V1);
11135 if (isUNPCKLMask(M, VT, HasInt256))
11136 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11138 if (isUNPCKHMask(M, VT, HasInt256))
11139 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11142 // Normalize mask so all entries that point to V2 points to its first
11143 // element then try to match unpck{h|l} again. If match, return a
11144 // new vector_shuffle with the corrected mask.p
11145 SmallVector<int, 8> NewMask(M.begin(), M.end());
11146 NormalizeMask(NewMask, NumElems);
11147 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11148 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11149 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11150 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11154 // Commute is back and try unpck* again.
11155 // FIXME: this seems wrong.
11156 CommuteVectorShuffleMask(M, NumElems);
11158 std::swap(V1IsSplat, V2IsSplat);
11160 if (isUNPCKLMask(M, VT, HasInt256))
11161 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11163 if (isUNPCKHMask(M, VT, HasInt256))
11164 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11167 // Normalize the node to match x86 shuffle ops if needed
11168 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11169 return DAG.getCommutedVectorShuffle(*SVOp);
11171 // The checks below are all present in isShuffleMaskLegal, but they are
11172 // inlined here right now to enable us to directly emit target specific
11173 // nodes, and remove one by one until they don't return Op anymore.
11175 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11176 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11177 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11178 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11181 if (isPSHUFHWMask(M, VT, HasInt256))
11182 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11183 getShufflePSHUFHWImmediate(SVOp),
11186 if (isPSHUFLWMask(M, VT, HasInt256))
11187 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11188 getShufflePSHUFLWImmediate(SVOp),
11191 unsigned MaskValue;
11192 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11194 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11196 if (isSHUFPMask(M, VT))
11197 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11198 getShuffleSHUFImmediate(SVOp), DAG);
11200 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11201 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11202 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11203 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11205 //===--------------------------------------------------------------------===//
11206 // Generate target specific nodes for 128 or 256-bit shuffles only
11207 // supported in the AVX instruction set.
11210 // Handle VMOVDDUPY permutations
11211 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11212 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11214 // Handle VPERMILPS/D* permutations
11215 if (isVPERMILPMask(M, VT)) {
11216 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11217 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11218 getShuffleSHUFImmediate(SVOp), DAG);
11219 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11220 getShuffleSHUFImmediate(SVOp), DAG);
11224 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11225 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11226 Idx*(NumElems/2), DAG, dl);
11228 // Handle VPERM2F128/VPERM2I128 permutations
11229 if (isVPERM2X128Mask(M, VT, HasFp256))
11230 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11231 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11233 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11234 return getINSERTPS(SVOp, dl, DAG);
11237 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11238 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11240 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11241 VT.is512BitVector()) {
11242 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11243 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11244 SmallVector<SDValue, 16> permclMask;
11245 for (unsigned i = 0; i != NumElems; ++i) {
11246 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11249 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11251 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11252 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11253 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11254 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11255 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11258 //===--------------------------------------------------------------------===//
11259 // Since no target specific shuffle was selected for this generic one,
11260 // lower it into other known shuffles. FIXME: this isn't true yet, but
11261 // this is the plan.
11264 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11265 if (VT == MVT::v8i16) {
11266 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11267 if (NewOp.getNode())
11271 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11272 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11273 if (NewOp.getNode())
11277 if (VT == MVT::v16i8) {
11278 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11279 if (NewOp.getNode())
11283 if (VT == MVT::v32i8) {
11284 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11285 if (NewOp.getNode())
11289 // Handle all 128-bit wide vectors with 4 elements, and match them with
11290 // several different shuffle types.
11291 if (NumElems == 4 && VT.is128BitVector())
11292 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11294 // Handle general 256-bit shuffles
11295 if (VT.is256BitVector())
11296 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11301 // This function assumes its argument is a BUILD_VECTOR of constants or
11302 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11304 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11305 unsigned &MaskValue) {
11307 unsigned NumElems = BuildVector->getNumOperands();
11308 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11309 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11310 unsigned NumElemsInLane = NumElems / NumLanes;
11312 // Blend for v16i16 should be symetric for the both lanes.
11313 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11314 SDValue EltCond = BuildVector->getOperand(i);
11315 SDValue SndLaneEltCond =
11316 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11318 int Lane1Cond = -1, Lane2Cond = -1;
11319 if (isa<ConstantSDNode>(EltCond))
11320 Lane1Cond = !isZero(EltCond);
11321 if (isa<ConstantSDNode>(SndLaneEltCond))
11322 Lane2Cond = !isZero(SndLaneEltCond);
11324 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11325 // Lane1Cond != 0, means we want the first argument.
11326 // Lane1Cond == 0, means we want the second argument.
11327 // The encoding of this argument is 0 for the first argument, 1
11328 // for the second. Therefore, invert the condition.
11329 MaskValue |= !Lane1Cond << i;
11330 else if (Lane1Cond < 0)
11331 MaskValue |= !Lane2Cond << i;
11338 // Try to lower a vselect node into a simple blend instruction.
11339 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11340 SelectionDAG &DAG) {
11341 SDValue Cond = Op.getOperand(0);
11342 SDValue LHS = Op.getOperand(1);
11343 SDValue RHS = Op.getOperand(2);
11345 MVT VT = Op.getSimpleValueType();
11346 MVT EltVT = VT.getVectorElementType();
11347 unsigned NumElems = VT.getVectorNumElements();
11349 // There is no blend with immediate in AVX-512.
11350 if (VT.is512BitVector())
11353 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11355 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11358 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11361 // Check the mask for BLEND and build the value.
11362 unsigned MaskValue = 0;
11363 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11366 // Convert i32 vectors to floating point if it is not AVX2.
11367 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11369 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11370 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11372 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11373 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11376 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11377 DAG.getConstant(MaskValue, MVT::i32));
11378 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11381 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11382 // A vselect where all conditions and data are constants can be optimized into
11383 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11384 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11385 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11386 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11389 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11390 if (BlendOp.getNode())
11393 // Some types for vselect were previously set to Expand, not Legal or
11394 // Custom. Return an empty SDValue so we fall-through to Expand, after
11395 // the Custom lowering phase.
11396 MVT VT = Op.getSimpleValueType();
11397 switch (VT.SimpleTy) {
11402 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11407 // We couldn't create a "Blend with immediate" node.
11408 // This node should still be legal, but we'll have to emit a blendv*
11413 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11414 MVT VT = Op.getSimpleValueType();
11417 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11420 if (VT.getSizeInBits() == 8) {
11421 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11422 Op.getOperand(0), Op.getOperand(1));
11423 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11424 DAG.getValueType(VT));
11425 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11428 if (VT.getSizeInBits() == 16) {
11429 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11430 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11432 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11433 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11434 DAG.getNode(ISD::BITCAST, dl,
11437 Op.getOperand(1)));
11438 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11439 Op.getOperand(0), Op.getOperand(1));
11440 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11441 DAG.getValueType(VT));
11442 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11445 if (VT == MVT::f32) {
11446 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11447 // the result back to FR32 register. It's only worth matching if the
11448 // result has a single use which is a store or a bitcast to i32. And in
11449 // the case of a store, it's not worth it if the index is a constant 0,
11450 // because a MOVSSmr can be used instead, which is smaller and faster.
11451 if (!Op.hasOneUse())
11453 SDNode *User = *Op.getNode()->use_begin();
11454 if ((User->getOpcode() != ISD::STORE ||
11455 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11456 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11457 (User->getOpcode() != ISD::BITCAST ||
11458 User->getValueType(0) != MVT::i32))
11460 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11461 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11464 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11467 if (VT == MVT::i32 || VT == MVT::i64) {
11468 // ExtractPS/pextrq works with constant index.
11469 if (isa<ConstantSDNode>(Op.getOperand(1)))
11475 /// Extract one bit from mask vector, like v16i1 or v8i1.
11476 /// AVX-512 feature.
11478 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11479 SDValue Vec = Op.getOperand(0);
11481 MVT VecVT = Vec.getSimpleValueType();
11482 SDValue Idx = Op.getOperand(1);
11483 MVT EltVT = Op.getSimpleValueType();
11485 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11487 // variable index can't be handled in mask registers,
11488 // extend vector to VR512
11489 if (!isa<ConstantSDNode>(Idx)) {
11490 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11491 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11492 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11493 ExtVT.getVectorElementType(), Ext, Idx);
11494 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11497 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11498 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11499 unsigned MaxSift = rc->getSize()*8 - 1;
11500 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11501 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11502 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11503 DAG.getConstant(MaxSift, MVT::i8));
11504 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11505 DAG.getIntPtrConstant(0));
11509 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11510 SelectionDAG &DAG) const {
11512 SDValue Vec = Op.getOperand(0);
11513 MVT VecVT = Vec.getSimpleValueType();
11514 SDValue Idx = Op.getOperand(1);
11516 if (Op.getSimpleValueType() == MVT::i1)
11517 return ExtractBitFromMaskVector(Op, DAG);
11519 if (!isa<ConstantSDNode>(Idx)) {
11520 if (VecVT.is512BitVector() ||
11521 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11522 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11525 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11526 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11527 MaskEltVT.getSizeInBits());
11529 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11530 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11531 getZeroVector(MaskVT, Subtarget, DAG, dl),
11532 Idx, DAG.getConstant(0, getPointerTy()));
11533 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11534 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11535 Perm, DAG.getConstant(0, getPointerTy()));
11540 // If this is a 256-bit vector result, first extract the 128-bit vector and
11541 // then extract the element from the 128-bit vector.
11542 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11544 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11545 // Get the 128-bit vector.
11546 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11547 MVT EltVT = VecVT.getVectorElementType();
11549 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11551 //if (IdxVal >= NumElems/2)
11552 // IdxVal -= NumElems/2;
11553 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11554 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11555 DAG.getConstant(IdxVal, MVT::i32));
11558 assert(VecVT.is128BitVector() && "Unexpected vector length");
11560 if (Subtarget->hasSSE41()) {
11561 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11566 MVT VT = Op.getSimpleValueType();
11567 // TODO: handle v16i8.
11568 if (VT.getSizeInBits() == 16) {
11569 SDValue Vec = Op.getOperand(0);
11570 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11572 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11574 DAG.getNode(ISD::BITCAST, dl,
11576 Op.getOperand(1)));
11577 // Transform it so it match pextrw which produces a 32-bit result.
11578 MVT EltVT = MVT::i32;
11579 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11580 Op.getOperand(0), Op.getOperand(1));
11581 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11582 DAG.getValueType(VT));
11583 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11586 if (VT.getSizeInBits() == 32) {
11587 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11591 // SHUFPS the element to the lowest double word, then movss.
11592 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11593 MVT VVT = Op.getOperand(0).getSimpleValueType();
11594 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11595 DAG.getUNDEF(VVT), Mask);
11596 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11597 DAG.getIntPtrConstant(0));
11600 if (VT.getSizeInBits() == 64) {
11601 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11602 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11603 // to match extract_elt for f64.
11604 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11608 // UNPCKHPD the element to the lowest double word, then movsd.
11609 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11610 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11611 int Mask[2] = { 1, -1 };
11612 MVT VVT = Op.getOperand(0).getSimpleValueType();
11613 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11614 DAG.getUNDEF(VVT), Mask);
11615 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11616 DAG.getIntPtrConstant(0));
11622 /// Insert one bit to mask vector, like v16i1 or v8i1.
11623 /// AVX-512 feature.
11625 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11627 SDValue Vec = Op.getOperand(0);
11628 SDValue Elt = Op.getOperand(1);
11629 SDValue Idx = Op.getOperand(2);
11630 MVT VecVT = Vec.getSimpleValueType();
11632 if (!isa<ConstantSDNode>(Idx)) {
11633 // Non constant index. Extend source and destination,
11634 // insert element and then truncate the result.
11635 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11636 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11637 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11638 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11639 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11640 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11643 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11644 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11645 if (Vec.getOpcode() == ISD::UNDEF)
11646 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11647 DAG.getConstant(IdxVal, MVT::i8));
11648 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11649 unsigned MaxSift = rc->getSize()*8 - 1;
11650 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11651 DAG.getConstant(MaxSift, MVT::i8));
11652 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11653 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11654 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11657 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11658 SelectionDAG &DAG) const {
11659 MVT VT = Op.getSimpleValueType();
11660 MVT EltVT = VT.getVectorElementType();
11662 if (EltVT == MVT::i1)
11663 return InsertBitToMaskVector(Op, DAG);
11666 SDValue N0 = Op.getOperand(0);
11667 SDValue N1 = Op.getOperand(1);
11668 SDValue N2 = Op.getOperand(2);
11669 if (!isa<ConstantSDNode>(N2))
11671 auto *N2C = cast<ConstantSDNode>(N2);
11672 unsigned IdxVal = N2C->getZExtValue();
11674 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11675 // into that, and then insert the subvector back into the result.
11676 if (VT.is256BitVector() || VT.is512BitVector()) {
11677 // Get the desired 128-bit vector half.
11678 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11680 // Insert the element into the desired half.
11681 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11682 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11684 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11685 DAG.getConstant(IdxIn128, MVT::i32));
11687 // Insert the changed part back to the 256-bit vector
11688 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11690 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11692 if (Subtarget->hasSSE41()) {
11693 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11695 if (VT == MVT::v8i16) {
11696 Opc = X86ISD::PINSRW;
11698 assert(VT == MVT::v16i8);
11699 Opc = X86ISD::PINSRB;
11702 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11704 if (N1.getValueType() != MVT::i32)
11705 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11706 if (N2.getValueType() != MVT::i32)
11707 N2 = DAG.getIntPtrConstant(IdxVal);
11708 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11711 if (EltVT == MVT::f32) {
11712 // Bits [7:6] of the constant are the source select. This will always be
11713 // zero here. The DAG Combiner may combine an extract_elt index into
11715 // bits. For example (insert (extract, 3), 2) could be matched by
11717 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11718 // Bits [5:4] of the constant are the destination select. This is the
11719 // value of the incoming immediate.
11720 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11721 // combine either bitwise AND or insert of float 0.0 to set these bits.
11722 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11723 // Create this as a scalar to vector..
11724 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11725 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11728 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11729 // PINSR* works with constant index.
11734 if (EltVT == MVT::i8)
11737 if (EltVT.getSizeInBits() == 16) {
11738 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11739 // as its second argument.
11740 if (N1.getValueType() != MVT::i32)
11741 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11742 if (N2.getValueType() != MVT::i32)
11743 N2 = DAG.getIntPtrConstant(IdxVal);
11744 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11749 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11751 MVT OpVT = Op.getSimpleValueType();
11753 // If this is a 256-bit vector result, first insert into a 128-bit
11754 // vector and then insert into the 256-bit vector.
11755 if (!OpVT.is128BitVector()) {
11756 // Insert into a 128-bit vector.
11757 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11758 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11759 OpVT.getVectorNumElements() / SizeFactor);
11761 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11763 // Insert the 128-bit vector.
11764 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11767 if (OpVT == MVT::v1i64 &&
11768 Op.getOperand(0).getValueType() == MVT::i64)
11769 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11771 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11772 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11773 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11774 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11777 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11778 // a simple subregister reference or explicit instructions to grab
11779 // upper bits of a vector.
11780 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11781 SelectionDAG &DAG) {
11783 SDValue In = Op.getOperand(0);
11784 SDValue Idx = Op.getOperand(1);
11785 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11786 MVT ResVT = Op.getSimpleValueType();
11787 MVT InVT = In.getSimpleValueType();
11789 if (Subtarget->hasFp256()) {
11790 if (ResVT.is128BitVector() &&
11791 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11792 isa<ConstantSDNode>(Idx)) {
11793 return Extract128BitVector(In, IdxVal, DAG, dl);
11795 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11796 isa<ConstantSDNode>(Idx)) {
11797 return Extract256BitVector(In, IdxVal, DAG, dl);
11803 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11804 // simple superregister reference or explicit instructions to insert
11805 // the upper bits of a vector.
11806 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11807 SelectionDAG &DAG) {
11808 if (Subtarget->hasFp256()) {
11809 SDLoc dl(Op.getNode());
11810 SDValue Vec = Op.getNode()->getOperand(0);
11811 SDValue SubVec = Op.getNode()->getOperand(1);
11812 SDValue Idx = Op.getNode()->getOperand(2);
11814 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11815 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11816 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11817 isa<ConstantSDNode>(Idx)) {
11818 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11819 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11822 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11823 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11824 isa<ConstantSDNode>(Idx)) {
11825 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11826 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11832 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11833 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11834 // one of the above mentioned nodes. It has to be wrapped because otherwise
11835 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11836 // be used to form addressing mode. These wrapped nodes will be selected
11839 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11840 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11842 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11843 // global base reg.
11844 unsigned char OpFlag = 0;
11845 unsigned WrapperKind = X86ISD::Wrapper;
11846 CodeModel::Model M = DAG.getTarget().getCodeModel();
11848 if (Subtarget->isPICStyleRIPRel() &&
11849 (M == CodeModel::Small || M == CodeModel::Kernel))
11850 WrapperKind = X86ISD::WrapperRIP;
11851 else if (Subtarget->isPICStyleGOT())
11852 OpFlag = X86II::MO_GOTOFF;
11853 else if (Subtarget->isPICStyleStubPIC())
11854 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11856 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11857 CP->getAlignment(),
11858 CP->getOffset(), OpFlag);
11860 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11861 // With PIC, the address is actually $g + Offset.
11863 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11864 DAG.getNode(X86ISD::GlobalBaseReg,
11865 SDLoc(), getPointerTy()),
11872 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11873 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11875 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11876 // global base reg.
11877 unsigned char OpFlag = 0;
11878 unsigned WrapperKind = X86ISD::Wrapper;
11879 CodeModel::Model M = DAG.getTarget().getCodeModel();
11881 if (Subtarget->isPICStyleRIPRel() &&
11882 (M == CodeModel::Small || M == CodeModel::Kernel))
11883 WrapperKind = X86ISD::WrapperRIP;
11884 else if (Subtarget->isPICStyleGOT())
11885 OpFlag = X86II::MO_GOTOFF;
11886 else if (Subtarget->isPICStyleStubPIC())
11887 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11889 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11892 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11894 // With PIC, the address is actually $g + Offset.
11896 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11897 DAG.getNode(X86ISD::GlobalBaseReg,
11898 SDLoc(), getPointerTy()),
11905 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11906 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11908 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11909 // global base reg.
11910 unsigned char OpFlag = 0;
11911 unsigned WrapperKind = X86ISD::Wrapper;
11912 CodeModel::Model M = DAG.getTarget().getCodeModel();
11914 if (Subtarget->isPICStyleRIPRel() &&
11915 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11916 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11917 OpFlag = X86II::MO_GOTPCREL;
11918 WrapperKind = X86ISD::WrapperRIP;
11919 } else if (Subtarget->isPICStyleGOT()) {
11920 OpFlag = X86II::MO_GOT;
11921 } else if (Subtarget->isPICStyleStubPIC()) {
11922 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11923 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11924 OpFlag = X86II::MO_DARWIN_NONLAZY;
11927 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11930 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11932 // With PIC, the address is actually $g + Offset.
11933 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11934 !Subtarget->is64Bit()) {
11935 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11936 DAG.getNode(X86ISD::GlobalBaseReg,
11937 SDLoc(), getPointerTy()),
11941 // For symbols that require a load from a stub to get the address, emit the
11943 if (isGlobalStubReference(OpFlag))
11944 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11945 MachinePointerInfo::getGOT(), false, false, false, 0);
11951 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11952 // Create the TargetBlockAddressAddress node.
11953 unsigned char OpFlags =
11954 Subtarget->ClassifyBlockAddressReference();
11955 CodeModel::Model M = DAG.getTarget().getCodeModel();
11956 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11957 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11959 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11962 if (Subtarget->isPICStyleRIPRel() &&
11963 (M == CodeModel::Small || M == CodeModel::Kernel))
11964 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11966 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11968 // With PIC, the address is actually $g + Offset.
11969 if (isGlobalRelativeToPICBase(OpFlags)) {
11970 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11971 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11979 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11980 int64_t Offset, SelectionDAG &DAG) const {
11981 // Create the TargetGlobalAddress node, folding in the constant
11982 // offset if it is legal.
11983 unsigned char OpFlags =
11984 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11985 CodeModel::Model M = DAG.getTarget().getCodeModel();
11987 if (OpFlags == X86II::MO_NO_FLAG &&
11988 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11989 // A direct static reference to a global.
11990 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11993 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11996 if (Subtarget->isPICStyleRIPRel() &&
11997 (M == CodeModel::Small || M == CodeModel::Kernel))
11998 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12000 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12002 // With PIC, the address is actually $g + Offset.
12003 if (isGlobalRelativeToPICBase(OpFlags)) {
12004 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12005 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12009 // For globals that require a load from a stub to get the address, emit the
12011 if (isGlobalStubReference(OpFlags))
12012 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12013 MachinePointerInfo::getGOT(), false, false, false, 0);
12015 // If there was a non-zero offset that we didn't fold, create an explicit
12016 // addition for it.
12018 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12019 DAG.getConstant(Offset, getPointerTy()));
12025 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12026 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12027 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12028 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12032 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12033 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12034 unsigned char OperandFlags, bool LocalDynamic = false) {
12035 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12036 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12038 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12039 GA->getValueType(0),
12043 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12047 SDValue Ops[] = { Chain, TGA, *InFlag };
12048 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12050 SDValue Ops[] = { Chain, TGA };
12051 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12054 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12055 MFI->setAdjustsStack(true);
12057 SDValue Flag = Chain.getValue(1);
12058 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12061 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12063 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12066 SDLoc dl(GA); // ? function entry point might be better
12067 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12068 DAG.getNode(X86ISD::GlobalBaseReg,
12069 SDLoc(), PtrVT), InFlag);
12070 InFlag = Chain.getValue(1);
12072 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12075 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12077 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12079 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12080 X86::RAX, X86II::MO_TLSGD);
12083 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12089 // Get the start address of the TLS block for this module.
12090 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12091 .getInfo<X86MachineFunctionInfo>();
12092 MFI->incNumLocalDynamicTLSAccesses();
12096 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12097 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12100 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12101 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12102 InFlag = Chain.getValue(1);
12103 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12104 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12107 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12111 unsigned char OperandFlags = X86II::MO_DTPOFF;
12112 unsigned WrapperKind = X86ISD::Wrapper;
12113 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12114 GA->getValueType(0),
12115 GA->getOffset(), OperandFlags);
12116 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12118 // Add x@dtpoff with the base.
12119 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12122 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12123 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12124 const EVT PtrVT, TLSModel::Model model,
12125 bool is64Bit, bool isPIC) {
12128 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12129 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12130 is64Bit ? 257 : 256));
12132 SDValue ThreadPointer =
12133 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12134 MachinePointerInfo(Ptr), false, false, false, 0);
12136 unsigned char OperandFlags = 0;
12137 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12139 unsigned WrapperKind = X86ISD::Wrapper;
12140 if (model == TLSModel::LocalExec) {
12141 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12142 } else if (model == TLSModel::InitialExec) {
12144 OperandFlags = X86II::MO_GOTTPOFF;
12145 WrapperKind = X86ISD::WrapperRIP;
12147 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12150 llvm_unreachable("Unexpected model");
12153 // emit "addl x@ntpoff,%eax" (local exec)
12154 // or "addl x@indntpoff,%eax" (initial exec)
12155 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12157 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12158 GA->getOffset(), OperandFlags);
12159 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12161 if (model == TLSModel::InitialExec) {
12162 if (isPIC && !is64Bit) {
12163 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12164 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12168 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12169 MachinePointerInfo::getGOT(), false, false, false, 0);
12172 // The address of the thread local variable is the add of the thread
12173 // pointer with the offset of the variable.
12174 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12178 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12180 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12181 const GlobalValue *GV = GA->getGlobal();
12183 if (Subtarget->isTargetELF()) {
12184 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12187 case TLSModel::GeneralDynamic:
12188 if (Subtarget->is64Bit())
12189 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12190 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12191 case TLSModel::LocalDynamic:
12192 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12193 Subtarget->is64Bit());
12194 case TLSModel::InitialExec:
12195 case TLSModel::LocalExec:
12196 return LowerToTLSExecModel(
12197 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12198 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12200 llvm_unreachable("Unknown TLS model.");
12203 if (Subtarget->isTargetDarwin()) {
12204 // Darwin only has one model of TLS. Lower to that.
12205 unsigned char OpFlag = 0;
12206 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12207 X86ISD::WrapperRIP : X86ISD::Wrapper;
12209 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12210 // global base reg.
12211 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12212 !Subtarget->is64Bit();
12214 OpFlag = X86II::MO_TLVP_PIC_BASE;
12216 OpFlag = X86II::MO_TLVP;
12218 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12219 GA->getValueType(0),
12220 GA->getOffset(), OpFlag);
12221 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12223 // With PIC32, the address is actually $g + Offset.
12225 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12226 DAG.getNode(X86ISD::GlobalBaseReg,
12227 SDLoc(), getPointerTy()),
12230 // Lowering the machine isd will make sure everything is in the right
12232 SDValue Chain = DAG.getEntryNode();
12233 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12234 SDValue Args[] = { Chain, Offset };
12235 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12237 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12238 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12239 MFI->setAdjustsStack(true);
12241 // And our return value (tls address) is in the standard call return value
12243 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12244 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12245 Chain.getValue(1));
12248 if (Subtarget->isTargetKnownWindowsMSVC() ||
12249 Subtarget->isTargetWindowsGNU()) {
12250 // Just use the implicit TLS architecture
12251 // Need to generate someting similar to:
12252 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12254 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12255 // mov rcx, qword [rdx+rcx*8]
12256 // mov eax, .tls$:tlsvar
12257 // [rax+rcx] contains the address
12258 // Windows 64bit: gs:0x58
12259 // Windows 32bit: fs:__tls_array
12262 SDValue Chain = DAG.getEntryNode();
12264 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12265 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12266 // use its literal value of 0x2C.
12267 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12268 ? Type::getInt8PtrTy(*DAG.getContext(),
12270 : Type::getInt32PtrTy(*DAG.getContext(),
12274 Subtarget->is64Bit()
12275 ? DAG.getIntPtrConstant(0x58)
12276 : (Subtarget->isTargetWindowsGNU()
12277 ? DAG.getIntPtrConstant(0x2C)
12278 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12280 SDValue ThreadPointer =
12281 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12282 MachinePointerInfo(Ptr), false, false, false, 0);
12284 // Load the _tls_index variable
12285 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12286 if (Subtarget->is64Bit())
12287 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12288 IDX, MachinePointerInfo(), MVT::i32,
12289 false, false, false, 0);
12291 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12292 false, false, false, 0);
12294 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12296 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12298 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12299 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12300 false, false, false, 0);
12302 // Get the offset of start of .tls section
12303 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12304 GA->getValueType(0),
12305 GA->getOffset(), X86II::MO_SECREL);
12306 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12308 // The address of the thread local variable is the add of the thread
12309 // pointer with the offset of the variable.
12310 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12313 llvm_unreachable("TLS not implemented for this target.");
12316 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12317 /// and take a 2 x i32 value to shift plus a shift amount.
12318 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12319 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12320 MVT VT = Op.getSimpleValueType();
12321 unsigned VTBits = VT.getSizeInBits();
12323 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12324 SDValue ShOpLo = Op.getOperand(0);
12325 SDValue ShOpHi = Op.getOperand(1);
12326 SDValue ShAmt = Op.getOperand(2);
12327 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12328 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12330 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12331 DAG.getConstant(VTBits - 1, MVT::i8));
12332 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12333 DAG.getConstant(VTBits - 1, MVT::i8))
12334 : DAG.getConstant(0, VT);
12336 SDValue Tmp2, Tmp3;
12337 if (Op.getOpcode() == ISD::SHL_PARTS) {
12338 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12339 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12341 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12342 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12345 // If the shift amount is larger or equal than the width of a part we can't
12346 // rely on the results of shld/shrd. Insert a test and select the appropriate
12347 // values for large shift amounts.
12348 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12349 DAG.getConstant(VTBits, MVT::i8));
12350 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12351 AndNode, DAG.getConstant(0, MVT::i8));
12354 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12355 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12356 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12358 if (Op.getOpcode() == ISD::SHL_PARTS) {
12359 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12360 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12362 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12363 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12366 SDValue Ops[2] = { Lo, Hi };
12367 return DAG.getMergeValues(Ops, dl);
12370 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12371 SelectionDAG &DAG) const {
12372 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12374 if (SrcVT.isVector())
12377 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12378 "Unknown SINT_TO_FP to lower!");
12380 // These are really Legal; return the operand so the caller accepts it as
12382 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12384 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12385 Subtarget->is64Bit()) {
12390 unsigned Size = SrcVT.getSizeInBits()/8;
12391 MachineFunction &MF = DAG.getMachineFunction();
12392 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12393 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12394 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12396 MachinePointerInfo::getFixedStack(SSFI),
12398 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12401 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12403 SelectionDAG &DAG) const {
12407 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12409 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12411 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12413 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12415 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12416 MachineMemOperand *MMO;
12418 int SSFI = FI->getIndex();
12420 DAG.getMachineFunction()
12421 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12422 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12424 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12425 StackSlot = StackSlot.getOperand(1);
12427 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12428 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12430 Tys, Ops, SrcVT, MMO);
12433 Chain = Result.getValue(1);
12434 SDValue InFlag = Result.getValue(2);
12436 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12437 // shouldn't be necessary except that RFP cannot be live across
12438 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12439 MachineFunction &MF = DAG.getMachineFunction();
12440 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12441 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12442 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12443 Tys = DAG.getVTList(MVT::Other);
12445 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12447 MachineMemOperand *MMO =
12448 DAG.getMachineFunction()
12449 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12450 MachineMemOperand::MOStore, SSFISize, SSFISize);
12452 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12453 Ops, Op.getValueType(), MMO);
12454 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12455 MachinePointerInfo::getFixedStack(SSFI),
12456 false, false, false, 0);
12462 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12463 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12464 SelectionDAG &DAG) const {
12465 // This algorithm is not obvious. Here it is what we're trying to output:
12468 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12469 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12471 haddpd %xmm0, %xmm0
12473 pshufd $0x4e, %xmm0, %xmm1
12479 LLVMContext *Context = DAG.getContext();
12481 // Build some magic constants.
12482 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12483 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12484 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12486 SmallVector<Constant*,2> CV1;
12488 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12489 APInt(64, 0x4330000000000000ULL))));
12491 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12492 APInt(64, 0x4530000000000000ULL))));
12493 Constant *C1 = ConstantVector::get(CV1);
12494 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12496 // Load the 64-bit value into an XMM register.
12497 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12499 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12500 MachinePointerInfo::getConstantPool(),
12501 false, false, false, 16);
12502 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12503 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12506 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12507 MachinePointerInfo::getConstantPool(),
12508 false, false, false, 16);
12509 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12510 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12513 if (Subtarget->hasSSE3()) {
12514 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12515 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12517 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12518 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12520 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12521 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12525 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12526 DAG.getIntPtrConstant(0));
12529 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12530 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12531 SelectionDAG &DAG) const {
12533 // FP constant to bias correct the final result.
12534 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12537 // Load the 32-bit value into an XMM register.
12538 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12541 // Zero out the upper parts of the register.
12542 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12544 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12545 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12546 DAG.getIntPtrConstant(0));
12548 // Or the load with the bias.
12549 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12550 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12551 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12552 MVT::v2f64, Load)),
12553 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12554 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12555 MVT::v2f64, Bias)));
12556 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12557 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12558 DAG.getIntPtrConstant(0));
12560 // Subtract the bias.
12561 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12563 // Handle final rounding.
12564 EVT DestVT = Op.getValueType();
12566 if (DestVT.bitsLT(MVT::f64))
12567 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12568 DAG.getIntPtrConstant(0));
12569 if (DestVT.bitsGT(MVT::f64))
12570 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12572 // Handle final rounding.
12576 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12577 SelectionDAG &DAG) const {
12578 SDValue N0 = Op.getOperand(0);
12579 MVT SVT = N0.getSimpleValueType();
12582 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12583 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12584 "Custom UINT_TO_FP is not supported!");
12586 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12587 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12588 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12591 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12592 SelectionDAG &DAG) const {
12593 SDValue N0 = Op.getOperand(0);
12596 if (Op.getValueType().isVector())
12597 return lowerUINT_TO_FP_vec(Op, DAG);
12599 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12600 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12601 // the optimization here.
12602 if (DAG.SignBitIsZero(N0))
12603 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12605 MVT SrcVT = N0.getSimpleValueType();
12606 MVT DstVT = Op.getSimpleValueType();
12607 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12608 return LowerUINT_TO_FP_i64(Op, DAG);
12609 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12610 return LowerUINT_TO_FP_i32(Op, DAG);
12611 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12614 // Make a 64-bit buffer, and use it to build an FILD.
12615 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12616 if (SrcVT == MVT::i32) {
12617 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12618 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12619 getPointerTy(), StackSlot, WordOff);
12620 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12621 StackSlot, MachinePointerInfo(),
12623 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12624 OffsetSlot, MachinePointerInfo(),
12626 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12630 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12631 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12632 StackSlot, MachinePointerInfo(),
12634 // For i64 source, we need to add the appropriate power of 2 if the input
12635 // was negative. This is the same as the optimization in
12636 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12637 // we must be careful to do the computation in x87 extended precision, not
12638 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12639 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12640 MachineMemOperand *MMO =
12641 DAG.getMachineFunction()
12642 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12643 MachineMemOperand::MOLoad, 8, 8);
12645 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12646 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12647 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12650 APInt FF(32, 0x5F800000ULL);
12652 // Check whether the sign bit is set.
12653 SDValue SignSet = DAG.getSetCC(dl,
12654 getSetCCResultType(*DAG.getContext(), MVT::i64),
12655 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12658 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12659 SDValue FudgePtr = DAG.getConstantPool(
12660 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12663 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12664 SDValue Zero = DAG.getIntPtrConstant(0);
12665 SDValue Four = DAG.getIntPtrConstant(4);
12666 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12668 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12670 // Load the value out, extending it from f32 to f80.
12671 // FIXME: Avoid the extend by constructing the right constant pool?
12672 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12673 FudgePtr, MachinePointerInfo::getConstantPool(),
12674 MVT::f32, false, false, false, 4);
12675 // Extend everything to 80 bits to force it to be done on x87.
12676 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12677 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12680 std::pair<SDValue,SDValue>
12681 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12682 bool IsSigned, bool IsReplace) const {
12685 EVT DstTy = Op.getValueType();
12687 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12688 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12692 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12693 DstTy.getSimpleVT() >= MVT::i16 &&
12694 "Unknown FP_TO_INT to lower!");
12696 // These are really Legal.
12697 if (DstTy == MVT::i32 &&
12698 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12699 return std::make_pair(SDValue(), SDValue());
12700 if (Subtarget->is64Bit() &&
12701 DstTy == MVT::i64 &&
12702 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12703 return std::make_pair(SDValue(), SDValue());
12705 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12706 // stack slot, or into the FTOL runtime function.
12707 MachineFunction &MF = DAG.getMachineFunction();
12708 unsigned MemSize = DstTy.getSizeInBits()/8;
12709 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12710 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12713 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12714 Opc = X86ISD::WIN_FTOL;
12716 switch (DstTy.getSimpleVT().SimpleTy) {
12717 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12718 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12719 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12720 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12723 SDValue Chain = DAG.getEntryNode();
12724 SDValue Value = Op.getOperand(0);
12725 EVT TheVT = Op.getOperand(0).getValueType();
12726 // FIXME This causes a redundant load/store if the SSE-class value is already
12727 // in memory, such as if it is on the callstack.
12728 if (isScalarFPTypeInSSEReg(TheVT)) {
12729 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12730 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12731 MachinePointerInfo::getFixedStack(SSFI),
12733 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12735 Chain, StackSlot, DAG.getValueType(TheVT)
12738 MachineMemOperand *MMO =
12739 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12740 MachineMemOperand::MOLoad, MemSize, MemSize);
12741 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12742 Chain = Value.getValue(1);
12743 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12744 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12747 MachineMemOperand *MMO =
12748 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12749 MachineMemOperand::MOStore, MemSize, MemSize);
12751 if (Opc != X86ISD::WIN_FTOL) {
12752 // Build the FP_TO_INT*_IN_MEM
12753 SDValue Ops[] = { Chain, Value, StackSlot };
12754 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12756 return std::make_pair(FIST, StackSlot);
12758 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12759 DAG.getVTList(MVT::Other, MVT::Glue),
12761 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12762 MVT::i32, ftol.getValue(1));
12763 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12764 MVT::i32, eax.getValue(2));
12765 SDValue Ops[] = { eax, edx };
12766 SDValue pair = IsReplace
12767 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12768 : DAG.getMergeValues(Ops, DL);
12769 return std::make_pair(pair, SDValue());
12773 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12774 const X86Subtarget *Subtarget) {
12775 MVT VT = Op->getSimpleValueType(0);
12776 SDValue In = Op->getOperand(0);
12777 MVT InVT = In.getSimpleValueType();
12780 // Optimize vectors in AVX mode:
12783 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12784 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12785 // Concat upper and lower parts.
12788 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12789 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12790 // Concat upper and lower parts.
12793 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12794 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12795 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12798 if (Subtarget->hasInt256())
12799 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12801 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12802 SDValue Undef = DAG.getUNDEF(InVT);
12803 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12804 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12805 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12807 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12808 VT.getVectorNumElements()/2);
12810 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12811 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12813 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12816 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12817 SelectionDAG &DAG) {
12818 MVT VT = Op->getSimpleValueType(0);
12819 SDValue In = Op->getOperand(0);
12820 MVT InVT = In.getSimpleValueType();
12822 unsigned int NumElts = VT.getVectorNumElements();
12823 if (NumElts != 8 && NumElts != 16)
12826 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12827 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12829 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12831 // Now we have only mask extension
12832 assert(InVT.getVectorElementType() == MVT::i1);
12833 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12834 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12835 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12836 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12837 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12838 MachinePointerInfo::getConstantPool(),
12839 false, false, false, Alignment);
12841 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12842 if (VT.is512BitVector())
12844 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12847 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12848 SelectionDAG &DAG) {
12849 if (Subtarget->hasFp256()) {
12850 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12858 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12859 SelectionDAG &DAG) {
12861 MVT VT = Op.getSimpleValueType();
12862 SDValue In = Op.getOperand(0);
12863 MVT SVT = In.getSimpleValueType();
12865 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12866 return LowerZERO_EXTEND_AVX512(Op, DAG);
12868 if (Subtarget->hasFp256()) {
12869 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12874 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12875 VT.getVectorNumElements() != SVT.getVectorNumElements());
12879 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12881 MVT VT = Op.getSimpleValueType();
12882 SDValue In = Op.getOperand(0);
12883 MVT InVT = In.getSimpleValueType();
12885 if (VT == MVT::i1) {
12886 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12887 "Invalid scalar TRUNCATE operation");
12888 if (InVT.getSizeInBits() >= 32)
12890 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12891 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12893 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12894 "Invalid TRUNCATE operation");
12896 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12897 if (VT.getVectorElementType().getSizeInBits() >=8)
12898 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12900 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12901 unsigned NumElts = InVT.getVectorNumElements();
12902 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12903 if (InVT.getSizeInBits() < 512) {
12904 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12905 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12909 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12910 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12911 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12912 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12913 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12914 MachinePointerInfo::getConstantPool(),
12915 false, false, false, Alignment);
12916 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12917 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12918 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12921 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12922 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12923 if (Subtarget->hasInt256()) {
12924 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12925 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12926 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12928 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12929 DAG.getIntPtrConstant(0));
12932 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12933 DAG.getIntPtrConstant(0));
12934 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12935 DAG.getIntPtrConstant(2));
12936 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12937 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12938 static const int ShufMask[] = {0, 2, 4, 6};
12939 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12942 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12943 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12944 if (Subtarget->hasInt256()) {
12945 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12947 SmallVector<SDValue,32> pshufbMask;
12948 for (unsigned i = 0; i < 2; ++i) {
12949 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12950 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12951 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12952 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12953 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12954 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12955 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12956 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12957 for (unsigned j = 0; j < 8; ++j)
12958 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12960 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12961 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12962 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12964 static const int ShufMask[] = {0, 2, -1, -1};
12965 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12967 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12968 DAG.getIntPtrConstant(0));
12969 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12972 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12973 DAG.getIntPtrConstant(0));
12975 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12976 DAG.getIntPtrConstant(4));
12978 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12979 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12981 // The PSHUFB mask:
12982 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12983 -1, -1, -1, -1, -1, -1, -1, -1};
12985 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12986 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12987 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12989 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12990 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12992 // The MOVLHPS Mask:
12993 static const int ShufMask2[] = {0, 1, 4, 5};
12994 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12995 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12998 // Handle truncation of V256 to V128 using shuffles.
12999 if (!VT.is128BitVector() || !InVT.is256BitVector())
13002 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13004 unsigned NumElems = VT.getVectorNumElements();
13005 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13007 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13008 // Prepare truncation shuffle mask
13009 for (unsigned i = 0; i != NumElems; ++i)
13010 MaskVec[i] = i * 2;
13011 SDValue V = DAG.getVectorShuffle(NVT, DL,
13012 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13013 DAG.getUNDEF(NVT), &MaskVec[0]);
13014 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13015 DAG.getIntPtrConstant(0));
13018 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13019 SelectionDAG &DAG) const {
13020 assert(!Op.getSimpleValueType().isVector());
13022 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13023 /*IsSigned=*/ true, /*IsReplace=*/ false);
13024 SDValue FIST = Vals.first, StackSlot = Vals.second;
13025 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13026 if (!FIST.getNode()) return Op;
13028 if (StackSlot.getNode())
13029 // Load the result.
13030 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13031 FIST, StackSlot, MachinePointerInfo(),
13032 false, false, false, 0);
13034 // The node is the result.
13038 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13039 SelectionDAG &DAG) const {
13040 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13041 /*IsSigned=*/ false, /*IsReplace=*/ false);
13042 SDValue FIST = Vals.first, StackSlot = Vals.second;
13043 assert(FIST.getNode() && "Unexpected failure");
13045 if (StackSlot.getNode())
13046 // Load the result.
13047 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13048 FIST, StackSlot, MachinePointerInfo(),
13049 false, false, false, 0);
13051 // The node is the result.
13055 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13057 MVT VT = Op.getSimpleValueType();
13058 SDValue In = Op.getOperand(0);
13059 MVT SVT = In.getSimpleValueType();
13061 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13063 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13064 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13065 In, DAG.getUNDEF(SVT)));
13068 // The only differences between FABS and FNEG are the mask and the logic op.
13069 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13070 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13071 "Wrong opcode for lowering FABS or FNEG.");
13073 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13075 MVT VT = Op.getSimpleValueType();
13076 // Assume scalar op for initialization; update for vector if needed.
13077 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13078 // generate a 16-byte vector constant and logic op even for the scalar case.
13079 // Using a 16-byte mask allows folding the load of the mask with
13080 // the logic op, so it can save (~4 bytes) on code size.
13082 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13083 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13084 // decide if we should generate a 16-byte constant mask when we only need 4 or
13085 // 8 bytes for the scalar case.
13086 if (VT.isVector()) {
13087 EltVT = VT.getVectorElementType();
13088 NumElts = VT.getVectorNumElements();
13091 unsigned EltBits = EltVT.getSizeInBits();
13092 LLVMContext *Context = DAG.getContext();
13093 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13095 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13096 Constant *C = ConstantInt::get(*Context, MaskElt);
13097 C = ConstantVector::getSplat(NumElts, C);
13098 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13099 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13100 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13101 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13102 MachinePointerInfo::getConstantPool(),
13103 false, false, false, Alignment);
13105 if (VT.isVector()) {
13106 // For a vector, cast operands to a vector type, perform the logic op,
13107 // and cast the result back to the original value type.
13108 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13109 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13110 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13111 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13112 return DAG.getNode(ISD::BITCAST, dl, VT,
13113 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13115 // If not vector, then scalar.
13116 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13117 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13120 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13122 LLVMContext *Context = DAG.getContext();
13123 SDValue Op0 = Op.getOperand(0);
13124 SDValue Op1 = Op.getOperand(1);
13126 MVT VT = Op.getSimpleValueType();
13127 MVT SrcVT = Op1.getSimpleValueType();
13129 // If second operand is smaller, extend it first.
13130 if (SrcVT.bitsLT(VT)) {
13131 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13134 // And if it is bigger, shrink it first.
13135 if (SrcVT.bitsGT(VT)) {
13136 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13140 // At this point the operands and the result should have the same
13141 // type, and that won't be f80 since that is not custom lowered.
13143 // First get the sign bit of second operand.
13144 SmallVector<Constant*,4> CV;
13145 if (SrcVT == MVT::f64) {
13146 const fltSemantics &Sem = APFloat::IEEEdouble;
13147 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13148 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13150 const fltSemantics &Sem = APFloat::IEEEsingle;
13151 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13152 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13153 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13154 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13156 Constant *C = ConstantVector::get(CV);
13157 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13158 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13159 MachinePointerInfo::getConstantPool(),
13160 false, false, false, 16);
13161 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13163 // Shift sign bit right or left if the two operands have different types.
13164 if (SrcVT.bitsGT(VT)) {
13165 // Op0 is MVT::f32, Op1 is MVT::f64.
13166 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13167 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13168 DAG.getConstant(32, MVT::i32));
13169 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13170 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13171 DAG.getIntPtrConstant(0));
13174 // Clear first operand sign bit.
13176 if (VT == MVT::f64) {
13177 const fltSemantics &Sem = APFloat::IEEEdouble;
13178 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13179 APInt(64, ~(1ULL << 63)))));
13180 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13182 const fltSemantics &Sem = APFloat::IEEEsingle;
13183 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13184 APInt(32, ~(1U << 31)))));
13185 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13186 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13187 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13189 C = ConstantVector::get(CV);
13190 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13191 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13192 MachinePointerInfo::getConstantPool(),
13193 false, false, false, 16);
13194 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13196 // Or the value with the sign bit.
13197 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13200 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13201 SDValue N0 = Op.getOperand(0);
13203 MVT VT = Op.getSimpleValueType();
13205 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13206 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13207 DAG.getConstant(1, VT));
13208 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13211 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13213 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13214 SelectionDAG &DAG) {
13215 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13217 if (!Subtarget->hasSSE41())
13220 if (!Op->hasOneUse())
13223 SDNode *N = Op.getNode();
13226 SmallVector<SDValue, 8> Opnds;
13227 DenseMap<SDValue, unsigned> VecInMap;
13228 SmallVector<SDValue, 8> VecIns;
13229 EVT VT = MVT::Other;
13231 // Recognize a special case where a vector is casted into wide integer to
13233 Opnds.push_back(N->getOperand(0));
13234 Opnds.push_back(N->getOperand(1));
13236 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13237 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13238 // BFS traverse all OR'd operands.
13239 if (I->getOpcode() == ISD::OR) {
13240 Opnds.push_back(I->getOperand(0));
13241 Opnds.push_back(I->getOperand(1));
13242 // Re-evaluate the number of nodes to be traversed.
13243 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13247 // Quit if a non-EXTRACT_VECTOR_ELT
13248 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13251 // Quit if without a constant index.
13252 SDValue Idx = I->getOperand(1);
13253 if (!isa<ConstantSDNode>(Idx))
13256 SDValue ExtractedFromVec = I->getOperand(0);
13257 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13258 if (M == VecInMap.end()) {
13259 VT = ExtractedFromVec.getValueType();
13260 // Quit if not 128/256-bit vector.
13261 if (!VT.is128BitVector() && !VT.is256BitVector())
13263 // Quit if not the same type.
13264 if (VecInMap.begin() != VecInMap.end() &&
13265 VT != VecInMap.begin()->first.getValueType())
13267 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13268 VecIns.push_back(ExtractedFromVec);
13270 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13273 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13274 "Not extracted from 128-/256-bit vector.");
13276 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13278 for (DenseMap<SDValue, unsigned>::const_iterator
13279 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13280 // Quit if not all elements are used.
13281 if (I->second != FullMask)
13285 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13287 // Cast all vectors into TestVT for PTEST.
13288 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13289 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13291 // If more than one full vectors are evaluated, OR them first before PTEST.
13292 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13293 // Each iteration will OR 2 nodes and append the result until there is only
13294 // 1 node left, i.e. the final OR'd value of all vectors.
13295 SDValue LHS = VecIns[Slot];
13296 SDValue RHS = VecIns[Slot + 1];
13297 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13300 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13301 VecIns.back(), VecIns.back());
13304 /// \brief return true if \c Op has a use that doesn't just read flags.
13305 static bool hasNonFlagsUse(SDValue Op) {
13306 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13308 SDNode *User = *UI;
13309 unsigned UOpNo = UI.getOperandNo();
13310 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13311 // Look pass truncate.
13312 UOpNo = User->use_begin().getOperandNo();
13313 User = *User->use_begin();
13316 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13317 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13323 /// Emit nodes that will be selected as "test Op0,Op0", or something
13325 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13326 SelectionDAG &DAG) const {
13327 if (Op.getValueType() == MVT::i1)
13328 // KORTEST instruction should be selected
13329 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13330 DAG.getConstant(0, Op.getValueType()));
13332 // CF and OF aren't always set the way we want. Determine which
13333 // of these we need.
13334 bool NeedCF = false;
13335 bool NeedOF = false;
13338 case X86::COND_A: case X86::COND_AE:
13339 case X86::COND_B: case X86::COND_BE:
13342 case X86::COND_G: case X86::COND_GE:
13343 case X86::COND_L: case X86::COND_LE:
13344 case X86::COND_O: case X86::COND_NO: {
13345 // Check if we really need to set the
13346 // Overflow flag. If NoSignedWrap is present
13347 // that is not actually needed.
13348 switch (Op->getOpcode()) {
13353 const BinaryWithFlagsSDNode *BinNode =
13354 cast<BinaryWithFlagsSDNode>(Op.getNode());
13355 if (BinNode->hasNoSignedWrap())
13365 // See if we can use the EFLAGS value from the operand instead of
13366 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13367 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13368 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13369 // Emit a CMP with 0, which is the TEST pattern.
13370 //if (Op.getValueType() == MVT::i1)
13371 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13372 // DAG.getConstant(0, MVT::i1));
13373 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13374 DAG.getConstant(0, Op.getValueType()));
13376 unsigned Opcode = 0;
13377 unsigned NumOperands = 0;
13379 // Truncate operations may prevent the merge of the SETCC instruction
13380 // and the arithmetic instruction before it. Attempt to truncate the operands
13381 // of the arithmetic instruction and use a reduced bit-width instruction.
13382 bool NeedTruncation = false;
13383 SDValue ArithOp = Op;
13384 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13385 SDValue Arith = Op->getOperand(0);
13386 // Both the trunc and the arithmetic op need to have one user each.
13387 if (Arith->hasOneUse())
13388 switch (Arith.getOpcode()) {
13395 NeedTruncation = true;
13401 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13402 // which may be the result of a CAST. We use the variable 'Op', which is the
13403 // non-casted variable when we check for possible users.
13404 switch (ArithOp.getOpcode()) {
13406 // Due to an isel shortcoming, be conservative if this add is likely to be
13407 // selected as part of a load-modify-store instruction. When the root node
13408 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13409 // uses of other nodes in the match, such as the ADD in this case. This
13410 // leads to the ADD being left around and reselected, with the result being
13411 // two adds in the output. Alas, even if none our users are stores, that
13412 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13413 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13414 // climbing the DAG back to the root, and it doesn't seem to be worth the
13416 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13417 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13418 if (UI->getOpcode() != ISD::CopyToReg &&
13419 UI->getOpcode() != ISD::SETCC &&
13420 UI->getOpcode() != ISD::STORE)
13423 if (ConstantSDNode *C =
13424 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13425 // An add of one will be selected as an INC.
13426 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13427 Opcode = X86ISD::INC;
13432 // An add of negative one (subtract of one) will be selected as a DEC.
13433 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13434 Opcode = X86ISD::DEC;
13440 // Otherwise use a regular EFLAGS-setting add.
13441 Opcode = X86ISD::ADD;
13446 // If we have a constant logical shift that's only used in a comparison
13447 // against zero turn it into an equivalent AND. This allows turning it into
13448 // a TEST instruction later.
13449 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13450 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13451 EVT VT = Op.getValueType();
13452 unsigned BitWidth = VT.getSizeInBits();
13453 unsigned ShAmt = Op->getConstantOperandVal(1);
13454 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13456 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13457 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13458 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13459 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13461 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13462 DAG.getConstant(Mask, VT));
13463 DAG.ReplaceAllUsesWith(Op, New);
13469 // If the primary and result isn't used, don't bother using X86ISD::AND,
13470 // because a TEST instruction will be better.
13471 if (!hasNonFlagsUse(Op))
13477 // Due to the ISEL shortcoming noted above, be conservative if this op is
13478 // likely to be selected as part of a load-modify-store instruction.
13479 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13480 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13481 if (UI->getOpcode() == ISD::STORE)
13484 // Otherwise use a regular EFLAGS-setting instruction.
13485 switch (ArithOp.getOpcode()) {
13486 default: llvm_unreachable("unexpected operator!");
13487 case ISD::SUB: Opcode = X86ISD::SUB; break;
13488 case ISD::XOR: Opcode = X86ISD::XOR; break;
13489 case ISD::AND: Opcode = X86ISD::AND; break;
13491 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13492 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13493 if (EFLAGS.getNode())
13496 Opcode = X86ISD::OR;
13510 return SDValue(Op.getNode(), 1);
13516 // If we found that truncation is beneficial, perform the truncation and
13518 if (NeedTruncation) {
13519 EVT VT = Op.getValueType();
13520 SDValue WideVal = Op->getOperand(0);
13521 EVT WideVT = WideVal.getValueType();
13522 unsigned ConvertedOp = 0;
13523 // Use a target machine opcode to prevent further DAGCombine
13524 // optimizations that may separate the arithmetic operations
13525 // from the setcc node.
13526 switch (WideVal.getOpcode()) {
13528 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13529 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13530 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13531 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13532 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13537 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13538 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13539 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13540 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13546 // Emit a CMP with 0, which is the TEST pattern.
13547 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13548 DAG.getConstant(0, Op.getValueType()));
13550 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13551 SmallVector<SDValue, 4> Ops;
13552 for (unsigned i = 0; i != NumOperands; ++i)
13553 Ops.push_back(Op.getOperand(i));
13555 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13556 DAG.ReplaceAllUsesWith(Op, New);
13557 return SDValue(New.getNode(), 1);
13560 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13562 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13563 SDLoc dl, SelectionDAG &DAG) const {
13564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13565 if (C->getAPIntValue() == 0)
13566 return EmitTest(Op0, X86CC, dl, DAG);
13568 if (Op0.getValueType() == MVT::i1)
13569 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13572 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13573 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13574 // Do the comparison at i32 if it's smaller, besides the Atom case.
13575 // This avoids subregister aliasing issues. Keep the smaller reference
13576 // if we're optimizing for size, however, as that'll allow better folding
13577 // of memory operations.
13578 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13579 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13580 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13581 !Subtarget->isAtom()) {
13582 unsigned ExtendOp =
13583 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13584 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13585 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13587 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13588 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13589 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13591 return SDValue(Sub.getNode(), 1);
13593 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13596 /// Convert a comparison if required by the subtarget.
13597 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13598 SelectionDAG &DAG) const {
13599 // If the subtarget does not support the FUCOMI instruction, floating-point
13600 // comparisons have to be converted.
13601 if (Subtarget->hasCMov() ||
13602 Cmp.getOpcode() != X86ISD::CMP ||
13603 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13604 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13607 // The instruction selector will select an FUCOM instruction instead of
13608 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13609 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13610 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13612 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13613 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13614 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13615 DAG.getConstant(8, MVT::i8));
13616 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13617 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13620 static bool isAllOnes(SDValue V) {
13621 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13622 return C && C->isAllOnesValue();
13625 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13626 /// if it's possible.
13627 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13628 SDLoc dl, SelectionDAG &DAG) const {
13629 SDValue Op0 = And.getOperand(0);
13630 SDValue Op1 = And.getOperand(1);
13631 if (Op0.getOpcode() == ISD::TRUNCATE)
13632 Op0 = Op0.getOperand(0);
13633 if (Op1.getOpcode() == ISD::TRUNCATE)
13634 Op1 = Op1.getOperand(0);
13637 if (Op1.getOpcode() == ISD::SHL)
13638 std::swap(Op0, Op1);
13639 if (Op0.getOpcode() == ISD::SHL) {
13640 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13641 if (And00C->getZExtValue() == 1) {
13642 // If we looked past a truncate, check that it's only truncating away
13644 unsigned BitWidth = Op0.getValueSizeInBits();
13645 unsigned AndBitWidth = And.getValueSizeInBits();
13646 if (BitWidth > AndBitWidth) {
13648 DAG.computeKnownBits(Op0, Zeros, Ones);
13649 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13653 RHS = Op0.getOperand(1);
13655 } else if (Op1.getOpcode() == ISD::Constant) {
13656 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13657 uint64_t AndRHSVal = AndRHS->getZExtValue();
13658 SDValue AndLHS = Op0;
13660 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13661 LHS = AndLHS.getOperand(0);
13662 RHS = AndLHS.getOperand(1);
13665 // Use BT if the immediate can't be encoded in a TEST instruction.
13666 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13668 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13672 if (LHS.getNode()) {
13673 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13674 // instruction. Since the shift amount is in-range-or-undefined, we know
13675 // that doing a bittest on the i32 value is ok. We extend to i32 because
13676 // the encoding for the i16 version is larger than the i32 version.
13677 // Also promote i16 to i32 for performance / code size reason.
13678 if (LHS.getValueType() == MVT::i8 ||
13679 LHS.getValueType() == MVT::i16)
13680 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13682 // If the operand types disagree, extend the shift amount to match. Since
13683 // BT ignores high bits (like shifts) we can use anyextend.
13684 if (LHS.getValueType() != RHS.getValueType())
13685 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13687 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13688 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13689 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13690 DAG.getConstant(Cond, MVT::i8), BT);
13696 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13698 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13703 // SSE Condition code mapping:
13712 switch (SetCCOpcode) {
13713 default: llvm_unreachable("Unexpected SETCC condition");
13715 case ISD::SETEQ: SSECC = 0; break;
13717 case ISD::SETGT: Swap = true; // Fallthrough
13719 case ISD::SETOLT: SSECC = 1; break;
13721 case ISD::SETGE: Swap = true; // Fallthrough
13723 case ISD::SETOLE: SSECC = 2; break;
13724 case ISD::SETUO: SSECC = 3; break;
13726 case ISD::SETNE: SSECC = 4; break;
13727 case ISD::SETULE: Swap = true; // Fallthrough
13728 case ISD::SETUGE: SSECC = 5; break;
13729 case ISD::SETULT: Swap = true; // Fallthrough
13730 case ISD::SETUGT: SSECC = 6; break;
13731 case ISD::SETO: SSECC = 7; break;
13733 case ISD::SETONE: SSECC = 8; break;
13736 std::swap(Op0, Op1);
13741 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13742 // ones, and then concatenate the result back.
13743 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13744 MVT VT = Op.getSimpleValueType();
13746 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13747 "Unsupported value type for operation");
13749 unsigned NumElems = VT.getVectorNumElements();
13751 SDValue CC = Op.getOperand(2);
13753 // Extract the LHS vectors
13754 SDValue LHS = Op.getOperand(0);
13755 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13756 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13758 // Extract the RHS vectors
13759 SDValue RHS = Op.getOperand(1);
13760 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13761 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13763 // Issue the operation on the smaller types and concatenate the result back
13764 MVT EltVT = VT.getVectorElementType();
13765 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13766 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13767 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13768 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13771 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13772 const X86Subtarget *Subtarget) {
13773 SDValue Op0 = Op.getOperand(0);
13774 SDValue Op1 = Op.getOperand(1);
13775 SDValue CC = Op.getOperand(2);
13776 MVT VT = Op.getSimpleValueType();
13779 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13780 Op.getValueType().getScalarType() == MVT::i1 &&
13781 "Cannot set masked compare for this operation");
13783 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13785 bool Unsigned = false;
13788 switch (SetCCOpcode) {
13789 default: llvm_unreachable("Unexpected SETCC condition");
13790 case ISD::SETNE: SSECC = 4; break;
13791 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13792 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13793 case ISD::SETLT: Swap = true; //fall-through
13794 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13795 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13796 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13797 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13798 case ISD::SETULE: Unsigned = true; //fall-through
13799 case ISD::SETLE: SSECC = 2; break;
13803 std::swap(Op0, Op1);
13805 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13806 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13807 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13808 DAG.getConstant(SSECC, MVT::i8));
13811 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13812 /// operand \p Op1. If non-trivial (for example because it's not constant)
13813 /// return an empty value.
13814 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13816 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13820 MVT VT = Op1.getSimpleValueType();
13821 MVT EVT = VT.getVectorElementType();
13822 unsigned n = VT.getVectorNumElements();
13823 SmallVector<SDValue, 8> ULTOp1;
13825 for (unsigned i = 0; i < n; ++i) {
13826 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13827 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13830 // Avoid underflow.
13831 APInt Val = Elt->getAPIntValue();
13835 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13838 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13841 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13842 SelectionDAG &DAG) {
13843 SDValue Op0 = Op.getOperand(0);
13844 SDValue Op1 = Op.getOperand(1);
13845 SDValue CC = Op.getOperand(2);
13846 MVT VT = Op.getSimpleValueType();
13847 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13848 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13853 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13854 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13857 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13858 unsigned Opc = X86ISD::CMPP;
13859 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13860 assert(VT.getVectorNumElements() <= 16);
13861 Opc = X86ISD::CMPM;
13863 // In the two special cases we can't handle, emit two comparisons.
13866 unsigned CombineOpc;
13867 if (SetCCOpcode == ISD::SETUEQ) {
13868 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13870 assert(SetCCOpcode == ISD::SETONE);
13871 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13874 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13875 DAG.getConstant(CC0, MVT::i8));
13876 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13877 DAG.getConstant(CC1, MVT::i8));
13878 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13880 // Handle all other FP comparisons here.
13881 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13882 DAG.getConstant(SSECC, MVT::i8));
13885 // Break 256-bit integer vector compare into smaller ones.
13886 if (VT.is256BitVector() && !Subtarget->hasInt256())
13887 return Lower256IntVSETCC(Op, DAG);
13889 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13890 EVT OpVT = Op1.getValueType();
13891 if (Subtarget->hasAVX512()) {
13892 if (Op1.getValueType().is512BitVector() ||
13893 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13894 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13895 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13897 // In AVX-512 architecture setcc returns mask with i1 elements,
13898 // But there is no compare instruction for i8 and i16 elements in KNL.
13899 // We are not talking about 512-bit operands in this case, these
13900 // types are illegal.
13902 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13903 OpVT.getVectorElementType().getSizeInBits() >= 8))
13904 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13905 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13908 // We are handling one of the integer comparisons here. Since SSE only has
13909 // GT and EQ comparisons for integer, swapping operands and multiple
13910 // operations may be required for some comparisons.
13912 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13913 bool Subus = false;
13915 switch (SetCCOpcode) {
13916 default: llvm_unreachable("Unexpected SETCC condition");
13917 case ISD::SETNE: Invert = true;
13918 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13919 case ISD::SETLT: Swap = true;
13920 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13921 case ISD::SETGE: Swap = true;
13922 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13923 Invert = true; break;
13924 case ISD::SETULT: Swap = true;
13925 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13926 FlipSigns = true; break;
13927 case ISD::SETUGE: Swap = true;
13928 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13929 FlipSigns = true; Invert = true; break;
13932 // Special case: Use min/max operations for SETULE/SETUGE
13933 MVT VET = VT.getVectorElementType();
13935 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13936 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13939 switch (SetCCOpcode) {
13941 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13942 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13945 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13948 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13949 if (!MinMax && hasSubus) {
13950 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13952 // t = psubus Op0, Op1
13953 // pcmpeq t, <0..0>
13954 switch (SetCCOpcode) {
13956 case ISD::SETULT: {
13957 // If the comparison is against a constant we can turn this into a
13958 // setule. With psubus, setule does not require a swap. This is
13959 // beneficial because the constant in the register is no longer
13960 // destructed as the destination so it can be hoisted out of a loop.
13961 // Only do this pre-AVX since vpcmp* is no longer destructive.
13962 if (Subtarget->hasAVX())
13964 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13965 if (ULEOp1.getNode()) {
13967 Subus = true; Invert = false; Swap = false;
13971 // Psubus is better than flip-sign because it requires no inversion.
13972 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13973 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13977 Opc = X86ISD::SUBUS;
13983 std::swap(Op0, Op1);
13985 // Check that the operation in question is available (most are plain SSE2,
13986 // but PCMPGTQ and PCMPEQQ have different requirements).
13987 if (VT == MVT::v2i64) {
13988 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13989 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13991 // First cast everything to the right type.
13992 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13993 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13995 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13996 // bits of the inputs before performing those operations. The lower
13997 // compare is always unsigned.
14000 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14002 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14003 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14004 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14005 Sign, Zero, Sign, Zero);
14007 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14008 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14010 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14011 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14012 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14014 // Create masks for only the low parts/high parts of the 64 bit integers.
14015 static const int MaskHi[] = { 1, 1, 3, 3 };
14016 static const int MaskLo[] = { 0, 0, 2, 2 };
14017 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14018 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14019 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14021 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14022 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14025 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14027 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14030 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14031 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14032 // pcmpeqd + pshufd + pand.
14033 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14035 // First cast everything to the right type.
14036 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14037 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14040 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14042 // Make sure the lower and upper halves are both all-ones.
14043 static const int Mask[] = { 1, 0, 3, 2 };
14044 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14045 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14048 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14050 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14054 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14055 // bits of the inputs before performing those operations.
14057 EVT EltVT = VT.getVectorElementType();
14058 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14059 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14060 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14063 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14065 // If the logical-not of the result is required, perform that now.
14067 Result = DAG.getNOT(dl, Result, VT);
14070 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14073 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14074 getZeroVector(VT, Subtarget, DAG, dl));
14079 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14081 MVT VT = Op.getSimpleValueType();
14083 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14085 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14086 && "SetCC type must be 8-bit or 1-bit integer");
14087 SDValue Op0 = Op.getOperand(0);
14088 SDValue Op1 = Op.getOperand(1);
14090 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14092 // Optimize to BT if possible.
14093 // Lower (X & (1 << N)) == 0 to BT(X, N).
14094 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14095 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14096 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14097 Op1.getOpcode() == ISD::Constant &&
14098 cast<ConstantSDNode>(Op1)->isNullValue() &&
14099 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14100 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14101 if (NewSetCC.getNode())
14105 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14107 if (Op1.getOpcode() == ISD::Constant &&
14108 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14109 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14110 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14112 // If the input is a setcc, then reuse the input setcc or use a new one with
14113 // the inverted condition.
14114 if (Op0.getOpcode() == X86ISD::SETCC) {
14115 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14116 bool Invert = (CC == ISD::SETNE) ^
14117 cast<ConstantSDNode>(Op1)->isNullValue();
14121 CCode = X86::GetOppositeBranchCondition(CCode);
14122 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14123 DAG.getConstant(CCode, MVT::i8),
14124 Op0.getOperand(1));
14126 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14130 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14131 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14132 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14134 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14135 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14138 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14139 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14140 if (X86CC == X86::COND_INVALID)
14143 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14144 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14145 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14146 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14148 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14152 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14153 static bool isX86LogicalCmp(SDValue Op) {
14154 unsigned Opc = Op.getNode()->getOpcode();
14155 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14156 Opc == X86ISD::SAHF)
14158 if (Op.getResNo() == 1 &&
14159 (Opc == X86ISD::ADD ||
14160 Opc == X86ISD::SUB ||
14161 Opc == X86ISD::ADC ||
14162 Opc == X86ISD::SBB ||
14163 Opc == X86ISD::SMUL ||
14164 Opc == X86ISD::UMUL ||
14165 Opc == X86ISD::INC ||
14166 Opc == X86ISD::DEC ||
14167 Opc == X86ISD::OR ||
14168 Opc == X86ISD::XOR ||
14169 Opc == X86ISD::AND))
14172 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14178 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14179 if (V.getOpcode() != ISD::TRUNCATE)
14182 SDValue VOp0 = V.getOperand(0);
14183 unsigned InBits = VOp0.getValueSizeInBits();
14184 unsigned Bits = V.getValueSizeInBits();
14185 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14188 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14189 bool addTest = true;
14190 SDValue Cond = Op.getOperand(0);
14191 SDValue Op1 = Op.getOperand(1);
14192 SDValue Op2 = Op.getOperand(2);
14194 EVT VT = Op1.getValueType();
14197 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14198 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14199 // sequence later on.
14200 if (Cond.getOpcode() == ISD::SETCC &&
14201 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14202 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14203 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14204 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14205 int SSECC = translateX86FSETCC(
14206 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14209 if (Subtarget->hasAVX512()) {
14210 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14211 DAG.getConstant(SSECC, MVT::i8));
14212 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14214 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14215 DAG.getConstant(SSECC, MVT::i8));
14216 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14217 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14218 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14222 if (Cond.getOpcode() == ISD::SETCC) {
14223 SDValue NewCond = LowerSETCC(Cond, DAG);
14224 if (NewCond.getNode())
14228 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14229 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14230 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14231 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14232 if (Cond.getOpcode() == X86ISD::SETCC &&
14233 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14234 isZero(Cond.getOperand(1).getOperand(1))) {
14235 SDValue Cmp = Cond.getOperand(1);
14237 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14239 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14240 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14241 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14243 SDValue CmpOp0 = Cmp.getOperand(0);
14244 // Apply further optimizations for special cases
14245 // (select (x != 0), -1, 0) -> neg & sbb
14246 // (select (x == 0), 0, -1) -> neg & sbb
14247 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14248 if (YC->isNullValue() &&
14249 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14250 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14251 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14252 DAG.getConstant(0, CmpOp0.getValueType()),
14254 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14255 DAG.getConstant(X86::COND_B, MVT::i8),
14256 SDValue(Neg.getNode(), 1));
14260 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14261 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14262 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14264 SDValue Res = // Res = 0 or -1.
14265 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14266 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14268 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14269 Res = DAG.getNOT(DL, Res, Res.getValueType());
14271 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14272 if (!N2C || !N2C->isNullValue())
14273 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14278 // Look past (and (setcc_carry (cmp ...)), 1).
14279 if (Cond.getOpcode() == ISD::AND &&
14280 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14281 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14282 if (C && C->getAPIntValue() == 1)
14283 Cond = Cond.getOperand(0);
14286 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14287 // setting operand in place of the X86ISD::SETCC.
14288 unsigned CondOpcode = Cond.getOpcode();
14289 if (CondOpcode == X86ISD::SETCC ||
14290 CondOpcode == X86ISD::SETCC_CARRY) {
14291 CC = Cond.getOperand(0);
14293 SDValue Cmp = Cond.getOperand(1);
14294 unsigned Opc = Cmp.getOpcode();
14295 MVT VT = Op.getSimpleValueType();
14297 bool IllegalFPCMov = false;
14298 if (VT.isFloatingPoint() && !VT.isVector() &&
14299 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14300 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14302 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14303 Opc == X86ISD::BT) { // FIXME
14307 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14308 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14309 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14310 Cond.getOperand(0).getValueType() != MVT::i8)) {
14311 SDValue LHS = Cond.getOperand(0);
14312 SDValue RHS = Cond.getOperand(1);
14313 unsigned X86Opcode;
14316 switch (CondOpcode) {
14317 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14318 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14319 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14320 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14321 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14322 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14323 default: llvm_unreachable("unexpected overflowing operator");
14325 if (CondOpcode == ISD::UMULO)
14326 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14329 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14331 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14333 if (CondOpcode == ISD::UMULO)
14334 Cond = X86Op.getValue(2);
14336 Cond = X86Op.getValue(1);
14338 CC = DAG.getConstant(X86Cond, MVT::i8);
14343 // Look pass the truncate if the high bits are known zero.
14344 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14345 Cond = Cond.getOperand(0);
14347 // We know the result of AND is compared against zero. Try to match
14349 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14350 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14351 if (NewSetCC.getNode()) {
14352 CC = NewSetCC.getOperand(0);
14353 Cond = NewSetCC.getOperand(1);
14360 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14361 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14364 // a < b ? -1 : 0 -> RES = ~setcc_carry
14365 // a < b ? 0 : -1 -> RES = setcc_carry
14366 // a >= b ? -1 : 0 -> RES = setcc_carry
14367 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14368 if (Cond.getOpcode() == X86ISD::SUB) {
14369 Cond = ConvertCmpIfNecessary(Cond, DAG);
14370 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14372 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14373 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14374 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14375 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14376 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14377 return DAG.getNOT(DL, Res, Res.getValueType());
14382 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14383 // widen the cmov and push the truncate through. This avoids introducing a new
14384 // branch during isel and doesn't add any extensions.
14385 if (Op.getValueType() == MVT::i8 &&
14386 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14387 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14388 if (T1.getValueType() == T2.getValueType() &&
14389 // Blacklist CopyFromReg to avoid partial register stalls.
14390 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14391 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14392 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14393 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14397 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14398 // condition is true.
14399 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14400 SDValue Ops[] = { Op2, Op1, CC, Cond };
14401 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14404 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14405 MVT VT = Op->getSimpleValueType(0);
14406 SDValue In = Op->getOperand(0);
14407 MVT InVT = In.getSimpleValueType();
14410 unsigned int NumElts = VT.getVectorNumElements();
14411 if (NumElts != 8 && NumElts != 16)
14414 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14415 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14417 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14418 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14420 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14421 Constant *C = ConstantInt::get(*DAG.getContext(),
14422 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14424 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14425 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14426 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14427 MachinePointerInfo::getConstantPool(),
14428 false, false, false, Alignment);
14429 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14430 if (VT.is512BitVector())
14432 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14435 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14436 SelectionDAG &DAG) {
14437 MVT VT = Op->getSimpleValueType(0);
14438 SDValue In = Op->getOperand(0);
14439 MVT InVT = In.getSimpleValueType();
14442 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14443 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14445 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14446 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14447 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14450 if (Subtarget->hasInt256())
14451 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14453 // Optimize vectors in AVX mode
14454 // Sign extend v8i16 to v8i32 and
14457 // Divide input vector into two parts
14458 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14459 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14460 // concat the vectors to original VT
14462 unsigned NumElems = InVT.getVectorNumElements();
14463 SDValue Undef = DAG.getUNDEF(InVT);
14465 SmallVector<int,8> ShufMask1(NumElems, -1);
14466 for (unsigned i = 0; i != NumElems/2; ++i)
14469 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14471 SmallVector<int,8> ShufMask2(NumElems, -1);
14472 for (unsigned i = 0; i != NumElems/2; ++i)
14473 ShufMask2[i] = i + NumElems/2;
14475 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14477 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14478 VT.getVectorNumElements()/2);
14480 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14481 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14483 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14486 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14487 // may emit an illegal shuffle but the expansion is still better than scalar
14488 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14489 // we'll emit a shuffle and a arithmetic shift.
14490 // TODO: It is possible to support ZExt by zeroing the undef values during
14491 // the shuffle phase or after the shuffle.
14492 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14493 SelectionDAG &DAG) {
14494 MVT RegVT = Op.getSimpleValueType();
14495 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14496 assert(RegVT.isInteger() &&
14497 "We only custom lower integer vector sext loads.");
14499 // Nothing useful we can do without SSE2 shuffles.
14500 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14502 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14504 EVT MemVT = Ld->getMemoryVT();
14505 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14506 unsigned RegSz = RegVT.getSizeInBits();
14508 ISD::LoadExtType Ext = Ld->getExtensionType();
14510 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14511 && "Only anyext and sext are currently implemented.");
14512 assert(MemVT != RegVT && "Cannot extend to the same type");
14513 assert(MemVT.isVector() && "Must load a vector from memory");
14515 unsigned NumElems = RegVT.getVectorNumElements();
14516 unsigned MemSz = MemVT.getSizeInBits();
14517 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14519 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14520 // The only way in which we have a legal 256-bit vector result but not the
14521 // integer 256-bit operations needed to directly lower a sextload is if we
14522 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14523 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14524 // correctly legalized. We do this late to allow the canonical form of
14525 // sextload to persist throughout the rest of the DAG combiner -- it wants
14526 // to fold together any extensions it can, and so will fuse a sign_extend
14527 // of an sextload into a sextload targeting a wider value.
14529 if (MemSz == 128) {
14530 // Just switch this to a normal load.
14531 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14532 "it must be a legal 128-bit vector "
14534 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14535 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14536 Ld->isInvariant(), Ld->getAlignment());
14538 assert(MemSz < 128 &&
14539 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14540 // Do an sext load to a 128-bit vector type. We want to use the same
14541 // number of elements, but elements half as wide. This will end up being
14542 // recursively lowered by this routine, but will succeed as we definitely
14543 // have all the necessary features if we're using AVX1.
14545 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14546 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14548 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14549 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14550 Ld->isNonTemporal(), Ld->isInvariant(),
14551 Ld->getAlignment());
14554 // Replace chain users with the new chain.
14555 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14556 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14558 // Finally, do a normal sign-extend to the desired register.
14559 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14562 // All sizes must be a power of two.
14563 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14564 "Non-power-of-two elements are not custom lowered!");
14566 // Attempt to load the original value using scalar loads.
14567 // Find the largest scalar type that divides the total loaded size.
14568 MVT SclrLoadTy = MVT::i8;
14569 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14570 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14571 MVT Tp = (MVT::SimpleValueType)tp;
14572 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14577 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14578 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14580 SclrLoadTy = MVT::f64;
14582 // Calculate the number of scalar loads that we need to perform
14583 // in order to load our vector from memory.
14584 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14586 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14587 "Can only lower sext loads with a single scalar load!");
14589 unsigned loadRegZize = RegSz;
14590 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14593 // Represent our vector as a sequence of elements which are the
14594 // largest scalar that we can load.
14595 EVT LoadUnitVecVT = EVT::getVectorVT(
14596 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14598 // Represent the data using the same element type that is stored in
14599 // memory. In practice, we ''widen'' MemVT.
14601 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14602 loadRegZize / MemVT.getScalarType().getSizeInBits());
14604 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14605 "Invalid vector type");
14607 // We can't shuffle using an illegal type.
14608 assert(TLI.isTypeLegal(WideVecVT) &&
14609 "We only lower types that form legal widened vector types");
14611 SmallVector<SDValue, 8> Chains;
14612 SDValue Ptr = Ld->getBasePtr();
14613 SDValue Increment =
14614 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14615 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14617 for (unsigned i = 0; i < NumLoads; ++i) {
14618 // Perform a single load.
14619 SDValue ScalarLoad =
14620 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14621 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14622 Ld->getAlignment());
14623 Chains.push_back(ScalarLoad.getValue(1));
14624 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14625 // another round of DAGCombining.
14627 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14629 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14630 ScalarLoad, DAG.getIntPtrConstant(i));
14632 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14635 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14637 // Bitcast the loaded value to a vector of the original element type, in
14638 // the size of the target vector type.
14639 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14640 unsigned SizeRatio = RegSz / MemSz;
14642 if (Ext == ISD::SEXTLOAD) {
14643 // If we have SSE4.1, we can directly emit a VSEXT node.
14644 if (Subtarget->hasSSE41()) {
14645 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14646 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14650 // Otherwise we'll shuffle the small elements in the high bits of the
14651 // larger type and perform an arithmetic shift. If the shift is not legal
14652 // it's better to scalarize.
14653 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14654 "We can't implement a sext load without an arithmetic right shift!");
14656 // Redistribute the loaded elements into the different locations.
14657 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14658 for (unsigned i = 0; i != NumElems; ++i)
14659 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14661 SDValue Shuff = DAG.getVectorShuffle(
14662 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14664 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14666 // Build the arithmetic shift.
14667 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14668 MemVT.getVectorElementType().getSizeInBits();
14670 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14672 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14676 // Redistribute the loaded elements into the different locations.
14677 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14678 for (unsigned i = 0; i != NumElems; ++i)
14679 ShuffleVec[i * SizeRatio] = i;
14681 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14682 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14684 // Bitcast to the requested type.
14685 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14686 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14690 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14691 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14692 // from the AND / OR.
14693 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14694 Opc = Op.getOpcode();
14695 if (Opc != ISD::OR && Opc != ISD::AND)
14697 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14698 Op.getOperand(0).hasOneUse() &&
14699 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14700 Op.getOperand(1).hasOneUse());
14703 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14704 // 1 and that the SETCC node has a single use.
14705 static bool isXor1OfSetCC(SDValue Op) {
14706 if (Op.getOpcode() != ISD::XOR)
14708 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14709 if (N1C && N1C->getAPIntValue() == 1) {
14710 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14711 Op.getOperand(0).hasOneUse();
14716 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14717 bool addTest = true;
14718 SDValue Chain = Op.getOperand(0);
14719 SDValue Cond = Op.getOperand(1);
14720 SDValue Dest = Op.getOperand(2);
14723 bool Inverted = false;
14725 if (Cond.getOpcode() == ISD::SETCC) {
14726 // Check for setcc([su]{add,sub,mul}o == 0).
14727 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14728 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14729 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14730 Cond.getOperand(0).getResNo() == 1 &&
14731 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14732 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14733 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14734 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14735 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14736 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14738 Cond = Cond.getOperand(0);
14740 SDValue NewCond = LowerSETCC(Cond, DAG);
14741 if (NewCond.getNode())
14746 // FIXME: LowerXALUO doesn't handle these!!
14747 else if (Cond.getOpcode() == X86ISD::ADD ||
14748 Cond.getOpcode() == X86ISD::SUB ||
14749 Cond.getOpcode() == X86ISD::SMUL ||
14750 Cond.getOpcode() == X86ISD::UMUL)
14751 Cond = LowerXALUO(Cond, DAG);
14754 // Look pass (and (setcc_carry (cmp ...)), 1).
14755 if (Cond.getOpcode() == ISD::AND &&
14756 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14757 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14758 if (C && C->getAPIntValue() == 1)
14759 Cond = Cond.getOperand(0);
14762 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14763 // setting operand in place of the X86ISD::SETCC.
14764 unsigned CondOpcode = Cond.getOpcode();
14765 if (CondOpcode == X86ISD::SETCC ||
14766 CondOpcode == X86ISD::SETCC_CARRY) {
14767 CC = Cond.getOperand(0);
14769 SDValue Cmp = Cond.getOperand(1);
14770 unsigned Opc = Cmp.getOpcode();
14771 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14772 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14776 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14780 // These can only come from an arithmetic instruction with overflow,
14781 // e.g. SADDO, UADDO.
14782 Cond = Cond.getNode()->getOperand(1);
14788 CondOpcode = Cond.getOpcode();
14789 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14790 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14791 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14792 Cond.getOperand(0).getValueType() != MVT::i8)) {
14793 SDValue LHS = Cond.getOperand(0);
14794 SDValue RHS = Cond.getOperand(1);
14795 unsigned X86Opcode;
14798 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14799 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14801 switch (CondOpcode) {
14802 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14804 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14806 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14809 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14810 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14812 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14814 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14817 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14818 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14819 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14820 default: llvm_unreachable("unexpected overflowing operator");
14823 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14824 if (CondOpcode == ISD::UMULO)
14825 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14828 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14830 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14832 if (CondOpcode == ISD::UMULO)
14833 Cond = X86Op.getValue(2);
14835 Cond = X86Op.getValue(1);
14837 CC = DAG.getConstant(X86Cond, MVT::i8);
14841 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14842 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14843 if (CondOpc == ISD::OR) {
14844 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14845 // two branches instead of an explicit OR instruction with a
14847 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14848 isX86LogicalCmp(Cmp)) {
14849 CC = Cond.getOperand(0).getOperand(0);
14850 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14851 Chain, Dest, CC, Cmp);
14852 CC = Cond.getOperand(1).getOperand(0);
14856 } else { // ISD::AND
14857 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14858 // two branches instead of an explicit AND instruction with a
14859 // separate test. However, we only do this if this block doesn't
14860 // have a fall-through edge, because this requires an explicit
14861 // jmp when the condition is false.
14862 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14863 isX86LogicalCmp(Cmp) &&
14864 Op.getNode()->hasOneUse()) {
14865 X86::CondCode CCode =
14866 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14867 CCode = X86::GetOppositeBranchCondition(CCode);
14868 CC = DAG.getConstant(CCode, MVT::i8);
14869 SDNode *User = *Op.getNode()->use_begin();
14870 // Look for an unconditional branch following this conditional branch.
14871 // We need this because we need to reverse the successors in order
14872 // to implement FCMP_OEQ.
14873 if (User->getOpcode() == ISD::BR) {
14874 SDValue FalseBB = User->getOperand(1);
14876 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14877 assert(NewBR == User);
14881 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14882 Chain, Dest, CC, Cmp);
14883 X86::CondCode CCode =
14884 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14885 CCode = X86::GetOppositeBranchCondition(CCode);
14886 CC = DAG.getConstant(CCode, MVT::i8);
14892 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14893 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14894 // It should be transformed during dag combiner except when the condition
14895 // is set by a arithmetics with overflow node.
14896 X86::CondCode CCode =
14897 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14898 CCode = X86::GetOppositeBranchCondition(CCode);
14899 CC = DAG.getConstant(CCode, MVT::i8);
14900 Cond = Cond.getOperand(0).getOperand(1);
14902 } else if (Cond.getOpcode() == ISD::SETCC &&
14903 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14904 // For FCMP_OEQ, we can emit
14905 // two branches instead of an explicit AND instruction with a
14906 // separate test. However, we only do this if this block doesn't
14907 // have a fall-through edge, because this requires an explicit
14908 // jmp when the condition is false.
14909 if (Op.getNode()->hasOneUse()) {
14910 SDNode *User = *Op.getNode()->use_begin();
14911 // Look for an unconditional branch following this conditional branch.
14912 // We need this because we need to reverse the successors in order
14913 // to implement FCMP_OEQ.
14914 if (User->getOpcode() == ISD::BR) {
14915 SDValue FalseBB = User->getOperand(1);
14917 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14918 assert(NewBR == User);
14922 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14923 Cond.getOperand(0), Cond.getOperand(1));
14924 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14925 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14926 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14927 Chain, Dest, CC, Cmp);
14928 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14933 } else if (Cond.getOpcode() == ISD::SETCC &&
14934 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14935 // For FCMP_UNE, we can emit
14936 // two branches instead of an explicit AND instruction with a
14937 // separate test. However, we only do this if this block doesn't
14938 // have a fall-through edge, because this requires an explicit
14939 // jmp when the condition is false.
14940 if (Op.getNode()->hasOneUse()) {
14941 SDNode *User = *Op.getNode()->use_begin();
14942 // Look for an unconditional branch following this conditional branch.
14943 // We need this because we need to reverse the successors in order
14944 // to implement FCMP_UNE.
14945 if (User->getOpcode() == ISD::BR) {
14946 SDValue FalseBB = User->getOperand(1);
14948 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14949 assert(NewBR == User);
14952 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14953 Cond.getOperand(0), Cond.getOperand(1));
14954 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14955 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14956 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14957 Chain, Dest, CC, Cmp);
14958 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14968 // Look pass the truncate if the high bits are known zero.
14969 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14970 Cond = Cond.getOperand(0);
14972 // We know the result of AND is compared against zero. Try to match
14974 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14975 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14976 if (NewSetCC.getNode()) {
14977 CC = NewSetCC.getOperand(0);
14978 Cond = NewSetCC.getOperand(1);
14985 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14986 CC = DAG.getConstant(X86Cond, MVT::i8);
14987 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14989 Cond = ConvertCmpIfNecessary(Cond, DAG);
14990 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14991 Chain, Dest, CC, Cond);
14994 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14995 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14996 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14997 // that the guard pages used by the OS virtual memory manager are allocated in
14998 // correct sequence.
15000 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15001 SelectionDAG &DAG) const {
15002 MachineFunction &MF = DAG.getMachineFunction();
15003 bool SplitStack = MF.shouldSplitStack();
15004 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15009 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15010 SDNode* Node = Op.getNode();
15012 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15013 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15014 " not tell us which reg is the stack pointer!");
15015 EVT VT = Node->getValueType(0);
15016 SDValue Tmp1 = SDValue(Node, 0);
15017 SDValue Tmp2 = SDValue(Node, 1);
15018 SDValue Tmp3 = Node->getOperand(2);
15019 SDValue Chain = Tmp1.getOperand(0);
15021 // Chain the dynamic stack allocation so that it doesn't modify the stack
15022 // pointer when other instructions are using the stack.
15023 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15026 SDValue Size = Tmp2.getOperand(1);
15027 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15028 Chain = SP.getValue(1);
15029 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15030 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15031 unsigned StackAlign = TFI.getStackAlignment();
15032 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15033 if (Align > StackAlign)
15034 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15035 DAG.getConstant(-(uint64_t)Align, VT));
15036 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15038 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15039 DAG.getIntPtrConstant(0, true), SDValue(),
15042 SDValue Ops[2] = { Tmp1, Tmp2 };
15043 return DAG.getMergeValues(Ops, dl);
15047 SDValue Chain = Op.getOperand(0);
15048 SDValue Size = Op.getOperand(1);
15049 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15050 EVT VT = Op.getNode()->getValueType(0);
15052 bool Is64Bit = Subtarget->is64Bit();
15053 EVT SPTy = getPointerTy();
15056 MachineRegisterInfo &MRI = MF.getRegInfo();
15059 // The 64 bit implementation of segmented stacks needs to clobber both r10
15060 // r11. This makes it impossible to use it along with nested parameters.
15061 const Function *F = MF.getFunction();
15063 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15065 if (I->hasNestAttr())
15066 report_fatal_error("Cannot use segmented stacks with functions that "
15067 "have nested arguments.");
15070 const TargetRegisterClass *AddrRegClass =
15071 getRegClassFor(getPointerTy());
15072 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15073 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15074 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15075 DAG.getRegister(Vreg, SPTy));
15076 SDValue Ops1[2] = { Value, Chain };
15077 return DAG.getMergeValues(Ops1, dl);
15080 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15082 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15083 Flag = Chain.getValue(1);
15084 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15086 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15088 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15089 DAG.getSubtarget().getRegisterInfo());
15090 unsigned SPReg = RegInfo->getStackRegister();
15091 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15092 Chain = SP.getValue(1);
15095 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15096 DAG.getConstant(-(uint64_t)Align, VT));
15097 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15100 SDValue Ops1[2] = { SP, Chain };
15101 return DAG.getMergeValues(Ops1, dl);
15105 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15106 MachineFunction &MF = DAG.getMachineFunction();
15107 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15109 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15112 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15113 // vastart just stores the address of the VarArgsFrameIndex slot into the
15114 // memory location argument.
15115 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15117 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15118 MachinePointerInfo(SV), false, false, 0);
15122 // gp_offset (0 - 6 * 8)
15123 // fp_offset (48 - 48 + 8 * 16)
15124 // overflow_arg_area (point to parameters coming in memory).
15126 SmallVector<SDValue, 8> MemOps;
15127 SDValue FIN = Op.getOperand(1);
15129 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15130 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15132 FIN, MachinePointerInfo(SV), false, false, 0);
15133 MemOps.push_back(Store);
15136 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15137 FIN, DAG.getIntPtrConstant(4));
15138 Store = DAG.getStore(Op.getOperand(0), DL,
15139 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15141 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15142 MemOps.push_back(Store);
15144 // Store ptr to overflow_arg_area
15145 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15146 FIN, DAG.getIntPtrConstant(4));
15147 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15149 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15150 MachinePointerInfo(SV, 8),
15152 MemOps.push_back(Store);
15154 // Store ptr to reg_save_area.
15155 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15156 FIN, DAG.getIntPtrConstant(8));
15157 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15159 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15160 MachinePointerInfo(SV, 16), false, false, 0);
15161 MemOps.push_back(Store);
15162 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15165 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15166 assert(Subtarget->is64Bit() &&
15167 "LowerVAARG only handles 64-bit va_arg!");
15168 assert((Subtarget->isTargetLinux() ||
15169 Subtarget->isTargetDarwin()) &&
15170 "Unhandled target in LowerVAARG");
15171 assert(Op.getNode()->getNumOperands() == 4);
15172 SDValue Chain = Op.getOperand(0);
15173 SDValue SrcPtr = Op.getOperand(1);
15174 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15175 unsigned Align = Op.getConstantOperandVal(3);
15178 EVT ArgVT = Op.getNode()->getValueType(0);
15179 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15180 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15183 // Decide which area this value should be read from.
15184 // TODO: Implement the AMD64 ABI in its entirety. This simple
15185 // selection mechanism works only for the basic types.
15186 if (ArgVT == MVT::f80) {
15187 llvm_unreachable("va_arg for f80 not yet implemented");
15188 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15189 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15190 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15191 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15193 llvm_unreachable("Unhandled argument type in LowerVAARG");
15196 if (ArgMode == 2) {
15197 // Sanity Check: Make sure using fp_offset makes sense.
15198 assert(!DAG.getTarget().Options.UseSoftFloat &&
15199 !(DAG.getMachineFunction()
15200 .getFunction()->getAttributes()
15201 .hasAttribute(AttributeSet::FunctionIndex,
15202 Attribute::NoImplicitFloat)) &&
15203 Subtarget->hasSSE1());
15206 // Insert VAARG_64 node into the DAG
15207 // VAARG_64 returns two values: Variable Argument Address, Chain
15208 SmallVector<SDValue, 11> InstOps;
15209 InstOps.push_back(Chain);
15210 InstOps.push_back(SrcPtr);
15211 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15212 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15213 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15214 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15215 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15216 VTs, InstOps, MVT::i64,
15217 MachinePointerInfo(SV),
15219 /*Volatile=*/false,
15221 /*WriteMem=*/true);
15222 Chain = VAARG.getValue(1);
15224 // Load the next argument and return it
15225 return DAG.getLoad(ArgVT, dl,
15228 MachinePointerInfo(),
15229 false, false, false, 0);
15232 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15233 SelectionDAG &DAG) {
15234 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15235 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15236 SDValue Chain = Op.getOperand(0);
15237 SDValue DstPtr = Op.getOperand(1);
15238 SDValue SrcPtr = Op.getOperand(2);
15239 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15240 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15243 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15244 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15246 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15249 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15250 // amount is a constant. Takes immediate version of shift as input.
15251 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15252 SDValue SrcOp, uint64_t ShiftAmt,
15253 SelectionDAG &DAG) {
15254 MVT ElementType = VT.getVectorElementType();
15256 // Fold this packed shift into its first operand if ShiftAmt is 0.
15260 // Check for ShiftAmt >= element width
15261 if (ShiftAmt >= ElementType.getSizeInBits()) {
15262 if (Opc == X86ISD::VSRAI)
15263 ShiftAmt = ElementType.getSizeInBits() - 1;
15265 return DAG.getConstant(0, VT);
15268 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15269 && "Unknown target vector shift-by-constant node");
15271 // Fold this packed vector shift into a build vector if SrcOp is a
15272 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15273 if (VT == SrcOp.getSimpleValueType() &&
15274 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15275 SmallVector<SDValue, 8> Elts;
15276 unsigned NumElts = SrcOp->getNumOperands();
15277 ConstantSDNode *ND;
15280 default: llvm_unreachable(nullptr);
15281 case X86ISD::VSHLI:
15282 for (unsigned i=0; i!=NumElts; ++i) {
15283 SDValue CurrentOp = SrcOp->getOperand(i);
15284 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15285 Elts.push_back(CurrentOp);
15288 ND = cast<ConstantSDNode>(CurrentOp);
15289 const APInt &C = ND->getAPIntValue();
15290 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15293 case X86ISD::VSRLI:
15294 for (unsigned i=0; i!=NumElts; ++i) {
15295 SDValue CurrentOp = SrcOp->getOperand(i);
15296 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15297 Elts.push_back(CurrentOp);
15300 ND = cast<ConstantSDNode>(CurrentOp);
15301 const APInt &C = ND->getAPIntValue();
15302 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15305 case X86ISD::VSRAI:
15306 for (unsigned i=0; i!=NumElts; ++i) {
15307 SDValue CurrentOp = SrcOp->getOperand(i);
15308 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15309 Elts.push_back(CurrentOp);
15312 ND = cast<ConstantSDNode>(CurrentOp);
15313 const APInt &C = ND->getAPIntValue();
15314 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15319 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15322 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15325 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15326 // may or may not be a constant. Takes immediate version of shift as input.
15327 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15328 SDValue SrcOp, SDValue ShAmt,
15329 SelectionDAG &DAG) {
15330 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15332 // Catch shift-by-constant.
15333 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15334 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15335 CShAmt->getZExtValue(), DAG);
15337 // Change opcode to non-immediate version
15339 default: llvm_unreachable("Unknown target vector shift node");
15340 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15341 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15342 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15345 // Need to build a vector containing shift amount
15346 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15349 ShOps[1] = DAG.getConstant(0, MVT::i32);
15350 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15351 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15353 // The return type has to be a 128-bit type with the same element
15354 // type as the input type.
15355 MVT EltVT = VT.getVectorElementType();
15356 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15358 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15359 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15362 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15363 /// necessary casting for \p Mask when lowering masking intrinsics.
15364 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15365 SDValue PreservedSrc, SelectionDAG &DAG) {
15366 EVT VT = Op.getValueType();
15367 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15368 MVT::i1, VT.getVectorNumElements());
15371 assert(MaskVT.isSimple() && "invalid mask type");
15372 return DAG.getNode(ISD::VSELECT, dl, VT,
15373 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15377 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15379 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15380 case Intrinsic::x86_fma_vfmadd_ps:
15381 case Intrinsic::x86_fma_vfmadd_pd:
15382 case Intrinsic::x86_fma_vfmadd_ps_256:
15383 case Intrinsic::x86_fma_vfmadd_pd_256:
15384 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15385 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15386 return X86ISD::FMADD;
15387 case Intrinsic::x86_fma_vfmsub_ps:
15388 case Intrinsic::x86_fma_vfmsub_pd:
15389 case Intrinsic::x86_fma_vfmsub_ps_256:
15390 case Intrinsic::x86_fma_vfmsub_pd_256:
15391 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15392 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15393 return X86ISD::FMSUB;
15394 case Intrinsic::x86_fma_vfnmadd_ps:
15395 case Intrinsic::x86_fma_vfnmadd_pd:
15396 case Intrinsic::x86_fma_vfnmadd_ps_256:
15397 case Intrinsic::x86_fma_vfnmadd_pd_256:
15398 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15399 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15400 return X86ISD::FNMADD;
15401 case Intrinsic::x86_fma_vfnmsub_ps:
15402 case Intrinsic::x86_fma_vfnmsub_pd:
15403 case Intrinsic::x86_fma_vfnmsub_ps_256:
15404 case Intrinsic::x86_fma_vfnmsub_pd_256:
15405 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15406 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15407 return X86ISD::FNMSUB;
15408 case Intrinsic::x86_fma_vfmaddsub_ps:
15409 case Intrinsic::x86_fma_vfmaddsub_pd:
15410 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15411 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15412 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15413 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15414 return X86ISD::FMADDSUB;
15415 case Intrinsic::x86_fma_vfmsubadd_ps:
15416 case Intrinsic::x86_fma_vfmsubadd_pd:
15417 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15418 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15419 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15420 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15421 return X86ISD::FMSUBADD;
15425 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15427 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15429 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15431 switch(IntrData->Type) {
15432 case INTR_TYPE_1OP:
15433 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15434 case INTR_TYPE_2OP:
15435 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15437 case INTR_TYPE_3OP:
15438 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15439 Op.getOperand(2), Op.getOperand(3));
15440 case COMI: { // Comparison intrinsics
15441 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15442 SDValue LHS = Op.getOperand(1);
15443 SDValue RHS = Op.getOperand(2);
15444 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15445 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15446 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15447 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15448 DAG.getConstant(X86CC, MVT::i8), Cond);
15449 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15452 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15453 Op.getOperand(1), Op.getOperand(2), DAG);
15460 default: return SDValue(); // Don't custom lower most intrinsics.
15462 // Arithmetic intrinsics.
15463 case Intrinsic::x86_sse2_pmulu_dq:
15464 case Intrinsic::x86_avx2_pmulu_dq:
15465 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15466 Op.getOperand(1), Op.getOperand(2));
15468 case Intrinsic::x86_sse41_pmuldq:
15469 case Intrinsic::x86_avx2_pmul_dq:
15470 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15471 Op.getOperand(1), Op.getOperand(2));
15473 case Intrinsic::x86_sse2_pmulhu_w:
15474 case Intrinsic::x86_avx2_pmulhu_w:
15475 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15476 Op.getOperand(1), Op.getOperand(2));
15478 case Intrinsic::x86_sse2_pmulh_w:
15479 case Intrinsic::x86_avx2_pmulh_w:
15480 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15481 Op.getOperand(1), Op.getOperand(2));
15483 // SSE/SSE2/AVX floating point max/min intrinsics.
15484 case Intrinsic::x86_sse_max_ps:
15485 case Intrinsic::x86_sse2_max_pd:
15486 case Intrinsic::x86_avx_max_ps_256:
15487 case Intrinsic::x86_avx_max_pd_256:
15488 case Intrinsic::x86_sse_min_ps:
15489 case Intrinsic::x86_sse2_min_pd:
15490 case Intrinsic::x86_avx_min_ps_256:
15491 case Intrinsic::x86_avx_min_pd_256: {
15494 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15495 case Intrinsic::x86_sse_max_ps:
15496 case Intrinsic::x86_sse2_max_pd:
15497 case Intrinsic::x86_avx_max_ps_256:
15498 case Intrinsic::x86_avx_max_pd_256:
15499 Opcode = X86ISD::FMAX;
15501 case Intrinsic::x86_sse_min_ps:
15502 case Intrinsic::x86_sse2_min_pd:
15503 case Intrinsic::x86_avx_min_ps_256:
15504 case Intrinsic::x86_avx_min_pd_256:
15505 Opcode = X86ISD::FMIN;
15508 return DAG.getNode(Opcode, dl, Op.getValueType(),
15509 Op.getOperand(1), Op.getOperand(2));
15512 // AVX2 variable shift intrinsics
15513 case Intrinsic::x86_avx2_psllv_d:
15514 case Intrinsic::x86_avx2_psllv_q:
15515 case Intrinsic::x86_avx2_psllv_d_256:
15516 case Intrinsic::x86_avx2_psllv_q_256:
15517 case Intrinsic::x86_avx2_psrlv_d:
15518 case Intrinsic::x86_avx2_psrlv_q:
15519 case Intrinsic::x86_avx2_psrlv_d_256:
15520 case Intrinsic::x86_avx2_psrlv_q_256:
15521 case Intrinsic::x86_avx2_psrav_d:
15522 case Intrinsic::x86_avx2_psrav_d_256: {
15525 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15526 case Intrinsic::x86_avx2_psllv_d:
15527 case Intrinsic::x86_avx2_psllv_q:
15528 case Intrinsic::x86_avx2_psllv_d_256:
15529 case Intrinsic::x86_avx2_psllv_q_256:
15532 case Intrinsic::x86_avx2_psrlv_d:
15533 case Intrinsic::x86_avx2_psrlv_q:
15534 case Intrinsic::x86_avx2_psrlv_d_256:
15535 case Intrinsic::x86_avx2_psrlv_q_256:
15538 case Intrinsic::x86_avx2_psrav_d:
15539 case Intrinsic::x86_avx2_psrav_d_256:
15543 return DAG.getNode(Opcode, dl, Op.getValueType(),
15544 Op.getOperand(1), Op.getOperand(2));
15547 case Intrinsic::x86_sse2_packssdw_128:
15548 case Intrinsic::x86_sse2_packsswb_128:
15549 case Intrinsic::x86_avx2_packssdw:
15550 case Intrinsic::x86_avx2_packsswb:
15551 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15552 Op.getOperand(1), Op.getOperand(2));
15554 case Intrinsic::x86_sse2_packuswb_128:
15555 case Intrinsic::x86_sse41_packusdw:
15556 case Intrinsic::x86_avx2_packuswb:
15557 case Intrinsic::x86_avx2_packusdw:
15558 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15559 Op.getOperand(1), Op.getOperand(2));
15561 case Intrinsic::x86_ssse3_pshuf_b_128:
15562 case Intrinsic::x86_avx2_pshuf_b:
15563 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15564 Op.getOperand(1), Op.getOperand(2));
15566 case Intrinsic::x86_sse2_pshuf_d:
15567 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15568 Op.getOperand(1), Op.getOperand(2));
15570 case Intrinsic::x86_sse2_pshufl_w:
15571 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15572 Op.getOperand(1), Op.getOperand(2));
15574 case Intrinsic::x86_sse2_pshufh_w:
15575 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15576 Op.getOperand(1), Op.getOperand(2));
15578 case Intrinsic::x86_ssse3_psign_b_128:
15579 case Intrinsic::x86_ssse3_psign_w_128:
15580 case Intrinsic::x86_ssse3_psign_d_128:
15581 case Intrinsic::x86_avx2_psign_b:
15582 case Intrinsic::x86_avx2_psign_w:
15583 case Intrinsic::x86_avx2_psign_d:
15584 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15585 Op.getOperand(1), Op.getOperand(2));
15587 case Intrinsic::x86_avx2_permd:
15588 case Intrinsic::x86_avx2_permps:
15589 // Operands intentionally swapped. Mask is last operand to intrinsic,
15590 // but second operand for node/instruction.
15591 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15592 Op.getOperand(2), Op.getOperand(1));
15594 case Intrinsic::x86_avx512_mask_valign_q_512:
15595 case Intrinsic::x86_avx512_mask_valign_d_512:
15596 // Vector source operands are swapped.
15597 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15598 Op.getValueType(), Op.getOperand(2),
15601 Op.getOperand(5), Op.getOperand(4), DAG);
15603 // ptest and testp intrinsics. The intrinsic these come from are designed to
15604 // return an integer value, not just an instruction so lower it to the ptest
15605 // or testp pattern and a setcc for the result.
15606 case Intrinsic::x86_sse41_ptestz:
15607 case Intrinsic::x86_sse41_ptestc:
15608 case Intrinsic::x86_sse41_ptestnzc:
15609 case Intrinsic::x86_avx_ptestz_256:
15610 case Intrinsic::x86_avx_ptestc_256:
15611 case Intrinsic::x86_avx_ptestnzc_256:
15612 case Intrinsic::x86_avx_vtestz_ps:
15613 case Intrinsic::x86_avx_vtestc_ps:
15614 case Intrinsic::x86_avx_vtestnzc_ps:
15615 case Intrinsic::x86_avx_vtestz_pd:
15616 case Intrinsic::x86_avx_vtestc_pd:
15617 case Intrinsic::x86_avx_vtestnzc_pd:
15618 case Intrinsic::x86_avx_vtestz_ps_256:
15619 case Intrinsic::x86_avx_vtestc_ps_256:
15620 case Intrinsic::x86_avx_vtestnzc_ps_256:
15621 case Intrinsic::x86_avx_vtestz_pd_256:
15622 case Intrinsic::x86_avx_vtestc_pd_256:
15623 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15624 bool IsTestPacked = false;
15627 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15628 case Intrinsic::x86_avx_vtestz_ps:
15629 case Intrinsic::x86_avx_vtestz_pd:
15630 case Intrinsic::x86_avx_vtestz_ps_256:
15631 case Intrinsic::x86_avx_vtestz_pd_256:
15632 IsTestPacked = true; // Fallthrough
15633 case Intrinsic::x86_sse41_ptestz:
15634 case Intrinsic::x86_avx_ptestz_256:
15636 X86CC = X86::COND_E;
15638 case Intrinsic::x86_avx_vtestc_ps:
15639 case Intrinsic::x86_avx_vtestc_pd:
15640 case Intrinsic::x86_avx_vtestc_ps_256:
15641 case Intrinsic::x86_avx_vtestc_pd_256:
15642 IsTestPacked = true; // Fallthrough
15643 case Intrinsic::x86_sse41_ptestc:
15644 case Intrinsic::x86_avx_ptestc_256:
15646 X86CC = X86::COND_B;
15648 case Intrinsic::x86_avx_vtestnzc_ps:
15649 case Intrinsic::x86_avx_vtestnzc_pd:
15650 case Intrinsic::x86_avx_vtestnzc_ps_256:
15651 case Intrinsic::x86_avx_vtestnzc_pd_256:
15652 IsTestPacked = true; // Fallthrough
15653 case Intrinsic::x86_sse41_ptestnzc:
15654 case Intrinsic::x86_avx_ptestnzc_256:
15656 X86CC = X86::COND_A;
15660 SDValue LHS = Op.getOperand(1);
15661 SDValue RHS = Op.getOperand(2);
15662 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15663 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15664 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15665 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15666 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15668 case Intrinsic::x86_avx512_kortestz_w:
15669 case Intrinsic::x86_avx512_kortestc_w: {
15670 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15671 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15672 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15673 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15674 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15675 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15676 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15679 case Intrinsic::x86_sse42_pcmpistria128:
15680 case Intrinsic::x86_sse42_pcmpestria128:
15681 case Intrinsic::x86_sse42_pcmpistric128:
15682 case Intrinsic::x86_sse42_pcmpestric128:
15683 case Intrinsic::x86_sse42_pcmpistrio128:
15684 case Intrinsic::x86_sse42_pcmpestrio128:
15685 case Intrinsic::x86_sse42_pcmpistris128:
15686 case Intrinsic::x86_sse42_pcmpestris128:
15687 case Intrinsic::x86_sse42_pcmpistriz128:
15688 case Intrinsic::x86_sse42_pcmpestriz128: {
15692 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15693 case Intrinsic::x86_sse42_pcmpistria128:
15694 Opcode = X86ISD::PCMPISTRI;
15695 X86CC = X86::COND_A;
15697 case Intrinsic::x86_sse42_pcmpestria128:
15698 Opcode = X86ISD::PCMPESTRI;
15699 X86CC = X86::COND_A;
15701 case Intrinsic::x86_sse42_pcmpistric128:
15702 Opcode = X86ISD::PCMPISTRI;
15703 X86CC = X86::COND_B;
15705 case Intrinsic::x86_sse42_pcmpestric128:
15706 Opcode = X86ISD::PCMPESTRI;
15707 X86CC = X86::COND_B;
15709 case Intrinsic::x86_sse42_pcmpistrio128:
15710 Opcode = X86ISD::PCMPISTRI;
15711 X86CC = X86::COND_O;
15713 case Intrinsic::x86_sse42_pcmpestrio128:
15714 Opcode = X86ISD::PCMPESTRI;
15715 X86CC = X86::COND_O;
15717 case Intrinsic::x86_sse42_pcmpistris128:
15718 Opcode = X86ISD::PCMPISTRI;
15719 X86CC = X86::COND_S;
15721 case Intrinsic::x86_sse42_pcmpestris128:
15722 Opcode = X86ISD::PCMPESTRI;
15723 X86CC = X86::COND_S;
15725 case Intrinsic::x86_sse42_pcmpistriz128:
15726 Opcode = X86ISD::PCMPISTRI;
15727 X86CC = X86::COND_E;
15729 case Intrinsic::x86_sse42_pcmpestriz128:
15730 Opcode = X86ISD::PCMPESTRI;
15731 X86CC = X86::COND_E;
15734 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15735 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15736 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15737 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15738 DAG.getConstant(X86CC, MVT::i8),
15739 SDValue(PCMP.getNode(), 1));
15740 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15743 case Intrinsic::x86_sse42_pcmpistri128:
15744 case Intrinsic::x86_sse42_pcmpestri128: {
15746 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15747 Opcode = X86ISD::PCMPISTRI;
15749 Opcode = X86ISD::PCMPESTRI;
15751 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15752 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15753 return DAG.getNode(Opcode, dl, VTs, NewOps);
15756 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15757 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15758 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15759 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15760 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15761 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15762 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15763 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15764 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15765 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15766 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15767 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15768 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15769 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15770 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15771 dl, Op.getValueType(),
15775 Op.getOperand(4), Op.getOperand(1), DAG);
15780 case Intrinsic::x86_fma_vfmadd_ps:
15781 case Intrinsic::x86_fma_vfmadd_pd:
15782 case Intrinsic::x86_fma_vfmsub_ps:
15783 case Intrinsic::x86_fma_vfmsub_pd:
15784 case Intrinsic::x86_fma_vfnmadd_ps:
15785 case Intrinsic::x86_fma_vfnmadd_pd:
15786 case Intrinsic::x86_fma_vfnmsub_ps:
15787 case Intrinsic::x86_fma_vfnmsub_pd:
15788 case Intrinsic::x86_fma_vfmaddsub_ps:
15789 case Intrinsic::x86_fma_vfmaddsub_pd:
15790 case Intrinsic::x86_fma_vfmsubadd_ps:
15791 case Intrinsic::x86_fma_vfmsubadd_pd:
15792 case Intrinsic::x86_fma_vfmadd_ps_256:
15793 case Intrinsic::x86_fma_vfmadd_pd_256:
15794 case Intrinsic::x86_fma_vfmsub_ps_256:
15795 case Intrinsic::x86_fma_vfmsub_pd_256:
15796 case Intrinsic::x86_fma_vfnmadd_ps_256:
15797 case Intrinsic::x86_fma_vfnmadd_pd_256:
15798 case Intrinsic::x86_fma_vfnmsub_ps_256:
15799 case Intrinsic::x86_fma_vfnmsub_pd_256:
15800 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15801 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15802 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15803 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15804 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15805 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15809 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15810 SDValue Src, SDValue Mask, SDValue Base,
15811 SDValue Index, SDValue ScaleOp, SDValue Chain,
15812 const X86Subtarget * Subtarget) {
15814 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15815 assert(C && "Invalid scale type");
15816 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15817 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15818 Index.getSimpleValueType().getVectorNumElements());
15820 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15822 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15824 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15825 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15826 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15827 SDValue Segment = DAG.getRegister(0, MVT::i32);
15828 if (Src.getOpcode() == ISD::UNDEF)
15829 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15830 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15831 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15832 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15833 return DAG.getMergeValues(RetOps, dl);
15836 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15837 SDValue Src, SDValue Mask, SDValue Base,
15838 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15840 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15841 assert(C && "Invalid scale type");
15842 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15843 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15844 SDValue Segment = DAG.getRegister(0, MVT::i32);
15845 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15846 Index.getSimpleValueType().getVectorNumElements());
15848 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15850 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15852 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15853 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15854 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15855 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15856 return SDValue(Res, 1);
15859 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15860 SDValue Mask, SDValue Base, SDValue Index,
15861 SDValue ScaleOp, SDValue Chain) {
15863 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15864 assert(C && "Invalid scale type");
15865 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15866 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15867 SDValue Segment = DAG.getRegister(0, MVT::i32);
15869 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15871 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15873 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15875 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15876 //SDVTList VTs = DAG.getVTList(MVT::Other);
15877 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15878 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15879 return SDValue(Res, 0);
15882 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15883 // read performance monitor counters (x86_rdpmc).
15884 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15885 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15886 SmallVectorImpl<SDValue> &Results) {
15887 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15888 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15891 // The ECX register is used to select the index of the performance counter
15893 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15895 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15897 // Reads the content of a 64-bit performance counter and returns it in the
15898 // registers EDX:EAX.
15899 if (Subtarget->is64Bit()) {
15900 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15901 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15904 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15905 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15908 Chain = HI.getValue(1);
15910 if (Subtarget->is64Bit()) {
15911 // The EAX register is loaded with the low-order 32 bits. The EDX register
15912 // is loaded with the supported high-order bits of the counter.
15913 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15914 DAG.getConstant(32, MVT::i8));
15915 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15916 Results.push_back(Chain);
15920 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15921 SDValue Ops[] = { LO, HI };
15922 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15923 Results.push_back(Pair);
15924 Results.push_back(Chain);
15927 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15928 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15929 // also used to custom lower READCYCLECOUNTER nodes.
15930 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15931 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15932 SmallVectorImpl<SDValue> &Results) {
15933 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15934 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15937 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15938 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15939 // and the EAX register is loaded with the low-order 32 bits.
15940 if (Subtarget->is64Bit()) {
15941 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15942 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15945 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15946 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15949 SDValue Chain = HI.getValue(1);
15951 if (Opcode == X86ISD::RDTSCP_DAG) {
15952 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15954 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15955 // the ECX register. Add 'ecx' explicitly to the chain.
15956 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15958 // Explicitly store the content of ECX at the location passed in input
15959 // to the 'rdtscp' intrinsic.
15960 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15961 MachinePointerInfo(), false, false, 0);
15964 if (Subtarget->is64Bit()) {
15965 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15966 // the EAX register is loaded with the low-order 32 bits.
15967 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15968 DAG.getConstant(32, MVT::i8));
15969 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15970 Results.push_back(Chain);
15974 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15975 SDValue Ops[] = { LO, HI };
15976 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15977 Results.push_back(Pair);
15978 Results.push_back(Chain);
15981 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15982 SelectionDAG &DAG) {
15983 SmallVector<SDValue, 2> Results;
15985 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15987 return DAG.getMergeValues(Results, DL);
15991 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15992 SelectionDAG &DAG) {
15993 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15995 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16000 switch(IntrData->Type) {
16002 llvm_unreachable("Unknown Intrinsic Type");
16006 // Emit the node with the right value type.
16007 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16008 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16010 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16011 // Otherwise return the value from Rand, which is always 0, casted to i32.
16012 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16013 DAG.getConstant(1, Op->getValueType(1)),
16014 DAG.getConstant(X86::COND_B, MVT::i32),
16015 SDValue(Result.getNode(), 1) };
16016 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16017 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16020 // Return { result, isValid, chain }.
16021 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16022 SDValue(Result.getNode(), 2));
16025 //gather(v1, mask, index, base, scale);
16026 SDValue Chain = Op.getOperand(0);
16027 SDValue Src = Op.getOperand(2);
16028 SDValue Base = Op.getOperand(3);
16029 SDValue Index = Op.getOperand(4);
16030 SDValue Mask = Op.getOperand(5);
16031 SDValue Scale = Op.getOperand(6);
16032 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16036 //scatter(base, mask, index, v1, scale);
16037 SDValue Chain = Op.getOperand(0);
16038 SDValue Base = Op.getOperand(2);
16039 SDValue Mask = Op.getOperand(3);
16040 SDValue Index = Op.getOperand(4);
16041 SDValue Src = Op.getOperand(5);
16042 SDValue Scale = Op.getOperand(6);
16043 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16046 SDValue Hint = Op.getOperand(6);
16048 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16049 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16050 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16051 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16052 SDValue Chain = Op.getOperand(0);
16053 SDValue Mask = Op.getOperand(2);
16054 SDValue Index = Op.getOperand(3);
16055 SDValue Base = Op.getOperand(4);
16056 SDValue Scale = Op.getOperand(5);
16057 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16059 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16061 SmallVector<SDValue, 2> Results;
16062 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16063 return DAG.getMergeValues(Results, dl);
16065 // Read Performance Monitoring Counters.
16067 SmallVector<SDValue, 2> Results;
16068 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16069 return DAG.getMergeValues(Results, dl);
16071 // XTEST intrinsics.
16073 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16074 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16075 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16076 DAG.getConstant(X86::COND_NE, MVT::i8),
16078 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16079 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16080 Ret, SDValue(InTrans.getNode(), 1));
16084 SmallVector<SDValue, 2> Results;
16085 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16086 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16087 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16088 DAG.getConstant(-1, MVT::i8));
16089 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16090 Op.getOperand(4), GenCF.getValue(1));
16091 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16092 Op.getOperand(5), MachinePointerInfo(),
16094 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16095 DAG.getConstant(X86::COND_B, MVT::i8),
16097 Results.push_back(SetCC);
16098 Results.push_back(Store);
16099 return DAG.getMergeValues(Results, dl);
16104 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16105 SelectionDAG &DAG) const {
16106 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16107 MFI->setReturnAddressIsTaken(true);
16109 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16112 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16114 EVT PtrVT = getPointerTy();
16117 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16118 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16119 DAG.getSubtarget().getRegisterInfo());
16120 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16121 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16122 DAG.getNode(ISD::ADD, dl, PtrVT,
16123 FrameAddr, Offset),
16124 MachinePointerInfo(), false, false, false, 0);
16127 // Just load the return address.
16128 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16129 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16130 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16133 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16134 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16135 MFI->setFrameAddressIsTaken(true);
16137 EVT VT = Op.getValueType();
16138 SDLoc dl(Op); // FIXME probably not meaningful
16139 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16140 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16141 DAG.getSubtarget().getRegisterInfo());
16142 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16143 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16144 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16145 "Invalid Frame Register!");
16146 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16148 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16149 MachinePointerInfo(),
16150 false, false, false, 0);
16154 // FIXME? Maybe this could be a TableGen attribute on some registers and
16155 // this table could be generated automatically from RegInfo.
16156 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16158 unsigned Reg = StringSwitch<unsigned>(RegName)
16159 .Case("esp", X86::ESP)
16160 .Case("rsp", X86::RSP)
16164 report_fatal_error("Invalid register name global variable");
16167 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16168 SelectionDAG &DAG) const {
16169 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16170 DAG.getSubtarget().getRegisterInfo());
16171 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16174 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16175 SDValue Chain = Op.getOperand(0);
16176 SDValue Offset = Op.getOperand(1);
16177 SDValue Handler = Op.getOperand(2);
16180 EVT PtrVT = getPointerTy();
16181 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16182 DAG.getSubtarget().getRegisterInfo());
16183 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16184 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16185 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16186 "Invalid Frame Register!");
16187 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16188 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16190 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16191 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16192 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16193 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16195 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16197 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16198 DAG.getRegister(StoreAddrReg, PtrVT));
16201 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16202 SelectionDAG &DAG) const {
16204 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16205 DAG.getVTList(MVT::i32, MVT::Other),
16206 Op.getOperand(0), Op.getOperand(1));
16209 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16210 SelectionDAG &DAG) const {
16212 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16213 Op.getOperand(0), Op.getOperand(1));
16216 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16217 return Op.getOperand(0);
16220 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16221 SelectionDAG &DAG) const {
16222 SDValue Root = Op.getOperand(0);
16223 SDValue Trmp = Op.getOperand(1); // trampoline
16224 SDValue FPtr = Op.getOperand(2); // nested function
16225 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16228 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16229 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16231 if (Subtarget->is64Bit()) {
16232 SDValue OutChains[6];
16234 // Large code-model.
16235 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16236 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16238 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16239 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16241 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16243 // Load the pointer to the nested function into R11.
16244 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16245 SDValue Addr = Trmp;
16246 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16247 Addr, MachinePointerInfo(TrmpAddr),
16250 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16251 DAG.getConstant(2, MVT::i64));
16252 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16253 MachinePointerInfo(TrmpAddr, 2),
16256 // Load the 'nest' parameter value into R10.
16257 // R10 is specified in X86CallingConv.td
16258 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16259 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16260 DAG.getConstant(10, MVT::i64));
16261 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16262 Addr, MachinePointerInfo(TrmpAddr, 10),
16265 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16266 DAG.getConstant(12, MVT::i64));
16267 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16268 MachinePointerInfo(TrmpAddr, 12),
16271 // Jump to the nested function.
16272 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16273 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16274 DAG.getConstant(20, MVT::i64));
16275 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16276 Addr, MachinePointerInfo(TrmpAddr, 20),
16279 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16280 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16281 DAG.getConstant(22, MVT::i64));
16282 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16283 MachinePointerInfo(TrmpAddr, 22),
16286 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16288 const Function *Func =
16289 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16290 CallingConv::ID CC = Func->getCallingConv();
16295 llvm_unreachable("Unsupported calling convention");
16296 case CallingConv::C:
16297 case CallingConv::X86_StdCall: {
16298 // Pass 'nest' parameter in ECX.
16299 // Must be kept in sync with X86CallingConv.td
16300 NestReg = X86::ECX;
16302 // Check that ECX wasn't needed by an 'inreg' parameter.
16303 FunctionType *FTy = Func->getFunctionType();
16304 const AttributeSet &Attrs = Func->getAttributes();
16306 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16307 unsigned InRegCount = 0;
16310 for (FunctionType::param_iterator I = FTy->param_begin(),
16311 E = FTy->param_end(); I != E; ++I, ++Idx)
16312 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16313 // FIXME: should only count parameters that are lowered to integers.
16314 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16316 if (InRegCount > 2) {
16317 report_fatal_error("Nest register in use - reduce number of inreg"
16323 case CallingConv::X86_FastCall:
16324 case CallingConv::X86_ThisCall:
16325 case CallingConv::Fast:
16326 // Pass 'nest' parameter in EAX.
16327 // Must be kept in sync with X86CallingConv.td
16328 NestReg = X86::EAX;
16332 SDValue OutChains[4];
16333 SDValue Addr, Disp;
16335 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16336 DAG.getConstant(10, MVT::i32));
16337 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16339 // This is storing the opcode for MOV32ri.
16340 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16341 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16342 OutChains[0] = DAG.getStore(Root, dl,
16343 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16344 Trmp, MachinePointerInfo(TrmpAddr),
16347 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16348 DAG.getConstant(1, MVT::i32));
16349 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16350 MachinePointerInfo(TrmpAddr, 1),
16353 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16354 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16355 DAG.getConstant(5, MVT::i32));
16356 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16357 MachinePointerInfo(TrmpAddr, 5),
16360 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16361 DAG.getConstant(6, MVT::i32));
16362 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16363 MachinePointerInfo(TrmpAddr, 6),
16366 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16370 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16371 SelectionDAG &DAG) const {
16373 The rounding mode is in bits 11:10 of FPSR, and has the following
16375 00 Round to nearest
16380 FLT_ROUNDS, on the other hand, expects the following:
16387 To perform the conversion, we do:
16388 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16391 MachineFunction &MF = DAG.getMachineFunction();
16392 const TargetMachine &TM = MF.getTarget();
16393 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16394 unsigned StackAlignment = TFI.getStackAlignment();
16395 MVT VT = Op.getSimpleValueType();
16398 // Save FP Control Word to stack slot
16399 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16400 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16402 MachineMemOperand *MMO =
16403 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16404 MachineMemOperand::MOStore, 2, 2);
16406 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16407 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16408 DAG.getVTList(MVT::Other),
16409 Ops, MVT::i16, MMO);
16411 // Load FP Control Word from stack slot
16412 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16413 MachinePointerInfo(), false, false, false, 0);
16415 // Transform as necessary
16417 DAG.getNode(ISD::SRL, DL, MVT::i16,
16418 DAG.getNode(ISD::AND, DL, MVT::i16,
16419 CWD, DAG.getConstant(0x800, MVT::i16)),
16420 DAG.getConstant(11, MVT::i8));
16422 DAG.getNode(ISD::SRL, DL, MVT::i16,
16423 DAG.getNode(ISD::AND, DL, MVT::i16,
16424 CWD, DAG.getConstant(0x400, MVT::i16)),
16425 DAG.getConstant(9, MVT::i8));
16428 DAG.getNode(ISD::AND, DL, MVT::i16,
16429 DAG.getNode(ISD::ADD, DL, MVT::i16,
16430 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16431 DAG.getConstant(1, MVT::i16)),
16432 DAG.getConstant(3, MVT::i16));
16434 return DAG.getNode((VT.getSizeInBits() < 16 ?
16435 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16438 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16439 MVT VT = Op.getSimpleValueType();
16441 unsigned NumBits = VT.getSizeInBits();
16444 Op = Op.getOperand(0);
16445 if (VT == MVT::i8) {
16446 // Zero extend to i32 since there is not an i8 bsr.
16448 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16451 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16452 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16453 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16455 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16458 DAG.getConstant(NumBits+NumBits-1, OpVT),
16459 DAG.getConstant(X86::COND_E, MVT::i8),
16462 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16464 // Finally xor with NumBits-1.
16465 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16468 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16472 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16473 MVT VT = Op.getSimpleValueType();
16475 unsigned NumBits = VT.getSizeInBits();
16478 Op = Op.getOperand(0);
16479 if (VT == MVT::i8) {
16480 // Zero extend to i32 since there is not an i8 bsr.
16482 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16485 // Issue a bsr (scan bits in reverse).
16486 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16487 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16489 // And xor with NumBits-1.
16490 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16493 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16497 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16498 MVT VT = Op.getSimpleValueType();
16499 unsigned NumBits = VT.getSizeInBits();
16501 Op = Op.getOperand(0);
16503 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16504 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16505 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16507 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16510 DAG.getConstant(NumBits, VT),
16511 DAG.getConstant(X86::COND_E, MVT::i8),
16514 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16517 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16518 // ones, and then concatenate the result back.
16519 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16520 MVT VT = Op.getSimpleValueType();
16522 assert(VT.is256BitVector() && VT.isInteger() &&
16523 "Unsupported value type for operation");
16525 unsigned NumElems = VT.getVectorNumElements();
16528 // Extract the LHS vectors
16529 SDValue LHS = Op.getOperand(0);
16530 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16531 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16533 // Extract the RHS vectors
16534 SDValue RHS = Op.getOperand(1);
16535 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16536 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16538 MVT EltVT = VT.getVectorElementType();
16539 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16541 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16542 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16543 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16546 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16547 assert(Op.getSimpleValueType().is256BitVector() &&
16548 Op.getSimpleValueType().isInteger() &&
16549 "Only handle AVX 256-bit vector integer operation");
16550 return Lower256IntArith(Op, DAG);
16553 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16554 assert(Op.getSimpleValueType().is256BitVector() &&
16555 Op.getSimpleValueType().isInteger() &&
16556 "Only handle AVX 256-bit vector integer operation");
16557 return Lower256IntArith(Op, DAG);
16560 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16561 SelectionDAG &DAG) {
16563 MVT VT = Op.getSimpleValueType();
16565 // Decompose 256-bit ops into smaller 128-bit ops.
16566 if (VT.is256BitVector() && !Subtarget->hasInt256())
16567 return Lower256IntArith(Op, DAG);
16569 SDValue A = Op.getOperand(0);
16570 SDValue B = Op.getOperand(1);
16572 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16573 if (VT == MVT::v4i32) {
16574 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16575 "Should not custom lower when pmuldq is available!");
16577 // Extract the odd parts.
16578 static const int UnpackMask[] = { 1, -1, 3, -1 };
16579 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16580 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16582 // Multiply the even parts.
16583 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16584 // Now multiply odd parts.
16585 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16587 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16588 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16590 // Merge the two vectors back together with a shuffle. This expands into 2
16592 static const int ShufMask[] = { 0, 4, 2, 6 };
16593 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16596 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16597 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16599 // Ahi = psrlqi(a, 32);
16600 // Bhi = psrlqi(b, 32);
16602 // AloBlo = pmuludq(a, b);
16603 // AloBhi = pmuludq(a, Bhi);
16604 // AhiBlo = pmuludq(Ahi, b);
16606 // AloBhi = psllqi(AloBhi, 32);
16607 // AhiBlo = psllqi(AhiBlo, 32);
16608 // return AloBlo + AloBhi + AhiBlo;
16610 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16611 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16613 // Bit cast to 32-bit vectors for MULUDQ
16614 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16615 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16616 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16617 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16618 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16619 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16621 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16622 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16623 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16625 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16626 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16628 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16629 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16632 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16633 assert(Subtarget->isTargetWin64() && "Unexpected target");
16634 EVT VT = Op.getValueType();
16635 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16636 "Unexpected return type for lowering");
16640 switch (Op->getOpcode()) {
16641 default: llvm_unreachable("Unexpected request for libcall!");
16642 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16643 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16644 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16645 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16646 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16647 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16651 SDValue InChain = DAG.getEntryNode();
16653 TargetLowering::ArgListTy Args;
16654 TargetLowering::ArgListEntry Entry;
16655 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16656 EVT ArgVT = Op->getOperand(i).getValueType();
16657 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16658 "Unexpected argument type for lowering");
16659 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16660 Entry.Node = StackPtr;
16661 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16663 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16664 Entry.Ty = PointerType::get(ArgTy,0);
16665 Entry.isSExt = false;
16666 Entry.isZExt = false;
16667 Args.push_back(Entry);
16670 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16673 TargetLowering::CallLoweringInfo CLI(DAG);
16674 CLI.setDebugLoc(dl).setChain(InChain)
16675 .setCallee(getLibcallCallingConv(LC),
16676 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16677 Callee, std::move(Args), 0)
16678 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16680 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16681 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16684 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16685 SelectionDAG &DAG) {
16686 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16687 EVT VT = Op0.getValueType();
16690 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16691 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16693 // PMULxD operations multiply each even value (starting at 0) of LHS with
16694 // the related value of RHS and produce a widen result.
16695 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16696 // => <2 x i64> <ae|cg>
16698 // In other word, to have all the results, we need to perform two PMULxD:
16699 // 1. one with the even values.
16700 // 2. one with the odd values.
16701 // To achieve #2, with need to place the odd values at an even position.
16703 // Place the odd value at an even position (basically, shift all values 1
16704 // step to the left):
16705 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16706 // <a|b|c|d> => <b|undef|d|undef>
16707 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16708 // <e|f|g|h> => <f|undef|h|undef>
16709 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16711 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16713 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16714 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16716 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16717 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16718 // => <2 x i64> <ae|cg>
16719 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16720 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16721 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16722 // => <2 x i64> <bf|dh>
16723 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16724 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16726 // Shuffle it back into the right order.
16727 SDValue Highs, Lows;
16728 if (VT == MVT::v8i32) {
16729 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16730 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16731 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16732 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16734 const int HighMask[] = {1, 5, 3, 7};
16735 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16736 const int LowMask[] = {0, 4, 2, 6};
16737 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16740 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16741 // unsigned multiply.
16742 if (IsSigned && !Subtarget->hasSSE41()) {
16744 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16745 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16746 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16747 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16748 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16750 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16751 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16754 // The first result of MUL_LOHI is actually the low value, followed by the
16756 SDValue Ops[] = {Lows, Highs};
16757 return DAG.getMergeValues(Ops, dl);
16760 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16761 const X86Subtarget *Subtarget) {
16762 MVT VT = Op.getSimpleValueType();
16764 SDValue R = Op.getOperand(0);
16765 SDValue Amt = Op.getOperand(1);
16767 // Optimize shl/srl/sra with constant shift amount.
16768 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16769 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16770 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16772 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16773 (Subtarget->hasInt256() &&
16774 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16775 (Subtarget->hasAVX512() &&
16776 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16777 if (Op.getOpcode() == ISD::SHL)
16778 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16780 if (Op.getOpcode() == ISD::SRL)
16781 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16783 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16784 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16788 if (VT == MVT::v16i8) {
16789 if (Op.getOpcode() == ISD::SHL) {
16790 // Make a large shift.
16791 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16792 MVT::v8i16, R, ShiftAmt,
16794 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16795 // Zero out the rightmost bits.
16796 SmallVector<SDValue, 16> V(16,
16797 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16799 return DAG.getNode(ISD::AND, dl, VT, SHL,
16800 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16802 if (Op.getOpcode() == ISD::SRL) {
16803 // Make a large shift.
16804 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16805 MVT::v8i16, R, ShiftAmt,
16807 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16808 // Zero out the leftmost bits.
16809 SmallVector<SDValue, 16> V(16,
16810 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16812 return DAG.getNode(ISD::AND, dl, VT, SRL,
16813 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16815 if (Op.getOpcode() == ISD::SRA) {
16816 if (ShiftAmt == 7) {
16817 // R s>> 7 === R s< 0
16818 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16819 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16822 // R s>> a === ((R u>> a) ^ m) - m
16823 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16824 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16826 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16827 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16828 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16831 llvm_unreachable("Unknown shift opcode.");
16834 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16835 if (Op.getOpcode() == ISD::SHL) {
16836 // Make a large shift.
16837 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16838 MVT::v16i16, R, ShiftAmt,
16840 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16841 // Zero out the rightmost bits.
16842 SmallVector<SDValue, 32> V(32,
16843 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16845 return DAG.getNode(ISD::AND, dl, VT, SHL,
16846 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16848 if (Op.getOpcode() == ISD::SRL) {
16849 // Make a large shift.
16850 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16851 MVT::v16i16, R, ShiftAmt,
16853 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16854 // Zero out the leftmost bits.
16855 SmallVector<SDValue, 32> V(32,
16856 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16858 return DAG.getNode(ISD::AND, dl, VT, SRL,
16859 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16861 if (Op.getOpcode() == ISD::SRA) {
16862 if (ShiftAmt == 7) {
16863 // R s>> 7 === R s< 0
16864 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16865 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16868 // R s>> a === ((R u>> a) ^ m) - m
16869 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16870 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16872 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16873 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16874 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16877 llvm_unreachable("Unknown shift opcode.");
16882 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16883 if (!Subtarget->is64Bit() &&
16884 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16885 Amt.getOpcode() == ISD::BITCAST &&
16886 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16887 Amt = Amt.getOperand(0);
16888 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16889 VT.getVectorNumElements();
16890 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16891 uint64_t ShiftAmt = 0;
16892 for (unsigned i = 0; i != Ratio; ++i) {
16893 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16897 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16899 // Check remaining shift amounts.
16900 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16901 uint64_t ShAmt = 0;
16902 for (unsigned j = 0; j != Ratio; ++j) {
16903 ConstantSDNode *C =
16904 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16908 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16910 if (ShAmt != ShiftAmt)
16913 switch (Op.getOpcode()) {
16915 llvm_unreachable("Unknown shift opcode!");
16917 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16920 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16923 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16931 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16932 const X86Subtarget* Subtarget) {
16933 MVT VT = Op.getSimpleValueType();
16935 SDValue R = Op.getOperand(0);
16936 SDValue Amt = Op.getOperand(1);
16938 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16939 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16940 (Subtarget->hasInt256() &&
16941 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16942 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16943 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16945 EVT EltVT = VT.getVectorElementType();
16947 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16948 unsigned NumElts = VT.getVectorNumElements();
16950 for (i = 0; i != NumElts; ++i) {
16951 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16955 for (j = i; j != NumElts; ++j) {
16956 SDValue Arg = Amt.getOperand(j);
16957 if (Arg.getOpcode() == ISD::UNDEF) continue;
16958 if (Arg != Amt.getOperand(i))
16961 if (i != NumElts && j == NumElts)
16962 BaseShAmt = Amt.getOperand(i);
16964 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16965 Amt = Amt.getOperand(0);
16966 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16967 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16968 SDValue InVec = Amt.getOperand(0);
16969 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16970 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16972 for (; i != NumElts; ++i) {
16973 SDValue Arg = InVec.getOperand(i);
16974 if (Arg.getOpcode() == ISD::UNDEF) continue;
16978 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16979 if (ConstantSDNode *C =
16980 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16981 unsigned SplatIdx =
16982 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16983 if (C->getZExtValue() == SplatIdx)
16984 BaseShAmt = InVec.getOperand(1);
16987 if (!BaseShAmt.getNode())
16988 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16989 DAG.getIntPtrConstant(0));
16993 if (BaseShAmt.getNode()) {
16994 if (EltVT.bitsGT(MVT::i32))
16995 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16996 else if (EltVT.bitsLT(MVT::i32))
16997 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16999 switch (Op.getOpcode()) {
17001 llvm_unreachable("Unknown shift opcode!");
17003 switch (VT.SimpleTy) {
17004 default: return SDValue();
17013 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17016 switch (VT.SimpleTy) {
17017 default: return SDValue();
17024 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17027 switch (VT.SimpleTy) {
17028 default: return SDValue();
17037 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17043 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17044 if (!Subtarget->is64Bit() &&
17045 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17046 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17047 Amt.getOpcode() == ISD::BITCAST &&
17048 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17049 Amt = Amt.getOperand(0);
17050 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17051 VT.getVectorNumElements();
17052 std::vector<SDValue> Vals(Ratio);
17053 for (unsigned i = 0; i != Ratio; ++i)
17054 Vals[i] = Amt.getOperand(i);
17055 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17056 for (unsigned j = 0; j != Ratio; ++j)
17057 if (Vals[j] != Amt.getOperand(i + j))
17060 switch (Op.getOpcode()) {
17062 llvm_unreachable("Unknown shift opcode!");
17064 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17066 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17068 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17075 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17076 SelectionDAG &DAG) {
17077 MVT VT = Op.getSimpleValueType();
17079 SDValue R = Op.getOperand(0);
17080 SDValue Amt = Op.getOperand(1);
17083 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17084 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17086 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17090 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17094 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17096 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17097 if (Subtarget->hasInt256()) {
17098 if (Op.getOpcode() == ISD::SRL &&
17099 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17100 VT == MVT::v4i64 || VT == MVT::v8i32))
17102 if (Op.getOpcode() == ISD::SHL &&
17103 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17104 VT == MVT::v4i64 || VT == MVT::v8i32))
17106 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17110 // If possible, lower this packed shift into a vector multiply instead of
17111 // expanding it into a sequence of scalar shifts.
17112 // Do this only if the vector shift count is a constant build_vector.
17113 if (Op.getOpcode() == ISD::SHL &&
17114 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17115 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17116 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17117 SmallVector<SDValue, 8> Elts;
17118 EVT SVT = VT.getScalarType();
17119 unsigned SVTBits = SVT.getSizeInBits();
17120 const APInt &One = APInt(SVTBits, 1);
17121 unsigned NumElems = VT.getVectorNumElements();
17123 for (unsigned i=0; i !=NumElems; ++i) {
17124 SDValue Op = Amt->getOperand(i);
17125 if (Op->getOpcode() == ISD::UNDEF) {
17126 Elts.push_back(Op);
17130 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17131 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17132 uint64_t ShAmt = C.getZExtValue();
17133 if (ShAmt >= SVTBits) {
17134 Elts.push_back(DAG.getUNDEF(SVT));
17137 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17139 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17140 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17143 // Lower SHL with variable shift amount.
17144 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17145 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17147 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17148 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17149 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17150 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17153 // If possible, lower this shift as a sequence of two shifts by
17154 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17156 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17158 // Could be rewritten as:
17159 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17161 // The advantage is that the two shifts from the example would be
17162 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17163 // the vector shift into four scalar shifts plus four pairs of vector
17165 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17166 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17167 unsigned TargetOpcode = X86ISD::MOVSS;
17168 bool CanBeSimplified;
17169 // The splat value for the first packed shift (the 'X' from the example).
17170 SDValue Amt1 = Amt->getOperand(0);
17171 // The splat value for the second packed shift (the 'Y' from the example).
17172 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17173 Amt->getOperand(2);
17175 // See if it is possible to replace this node with a sequence of
17176 // two shifts followed by a MOVSS/MOVSD
17177 if (VT == MVT::v4i32) {
17178 // Check if it is legal to use a MOVSS.
17179 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17180 Amt2 == Amt->getOperand(3);
17181 if (!CanBeSimplified) {
17182 // Otherwise, check if we can still simplify this node using a MOVSD.
17183 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17184 Amt->getOperand(2) == Amt->getOperand(3);
17185 TargetOpcode = X86ISD::MOVSD;
17186 Amt2 = Amt->getOperand(2);
17189 // Do similar checks for the case where the machine value type
17191 CanBeSimplified = Amt1 == Amt->getOperand(1);
17192 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17193 CanBeSimplified = Amt2 == Amt->getOperand(i);
17195 if (!CanBeSimplified) {
17196 TargetOpcode = X86ISD::MOVSD;
17197 CanBeSimplified = true;
17198 Amt2 = Amt->getOperand(4);
17199 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17200 CanBeSimplified = Amt1 == Amt->getOperand(i);
17201 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17202 CanBeSimplified = Amt2 == Amt->getOperand(j);
17206 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17207 isa<ConstantSDNode>(Amt2)) {
17208 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17209 EVT CastVT = MVT::v4i32;
17211 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17212 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17214 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17215 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17216 if (TargetOpcode == X86ISD::MOVSD)
17217 CastVT = MVT::v2i64;
17218 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17219 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17220 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17222 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17226 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17227 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17230 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17231 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17233 // Turn 'a' into a mask suitable for VSELECT
17234 SDValue VSelM = DAG.getConstant(0x80, VT);
17235 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17236 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17238 SDValue CM1 = DAG.getConstant(0x0f, VT);
17239 SDValue CM2 = DAG.getConstant(0x3f, VT);
17241 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17242 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17243 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17244 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17245 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17248 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17249 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17250 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17252 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17253 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17254 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17255 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17256 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17259 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17260 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17261 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17263 // return VSELECT(r, r+r, a);
17264 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17265 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17269 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17270 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17271 // solution better.
17272 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17273 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17275 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17276 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17277 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17278 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17279 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17282 // Decompose 256-bit shifts into smaller 128-bit shifts.
17283 if (VT.is256BitVector()) {
17284 unsigned NumElems = VT.getVectorNumElements();
17285 MVT EltVT = VT.getVectorElementType();
17286 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17288 // Extract the two vectors
17289 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17290 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17292 // Recreate the shift amount vectors
17293 SDValue Amt1, Amt2;
17294 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17295 // Constant shift amount
17296 SmallVector<SDValue, 4> Amt1Csts;
17297 SmallVector<SDValue, 4> Amt2Csts;
17298 for (unsigned i = 0; i != NumElems/2; ++i)
17299 Amt1Csts.push_back(Amt->getOperand(i));
17300 for (unsigned i = NumElems/2; i != NumElems; ++i)
17301 Amt2Csts.push_back(Amt->getOperand(i));
17303 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17304 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17306 // Variable shift amount
17307 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17308 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17311 // Issue new vector shifts for the smaller types
17312 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17313 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17315 // Concatenate the result back
17316 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17322 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17323 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17324 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17325 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17326 // has only one use.
17327 SDNode *N = Op.getNode();
17328 SDValue LHS = N->getOperand(0);
17329 SDValue RHS = N->getOperand(1);
17330 unsigned BaseOp = 0;
17333 switch (Op.getOpcode()) {
17334 default: llvm_unreachable("Unknown ovf instruction!");
17336 // A subtract of one will be selected as a INC. Note that INC doesn't
17337 // set CF, so we can't do this for UADDO.
17338 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17340 BaseOp = X86ISD::INC;
17341 Cond = X86::COND_O;
17344 BaseOp = X86ISD::ADD;
17345 Cond = X86::COND_O;
17348 BaseOp = X86ISD::ADD;
17349 Cond = X86::COND_B;
17352 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17353 // set CF, so we can't do this for USUBO.
17354 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17356 BaseOp = X86ISD::DEC;
17357 Cond = X86::COND_O;
17360 BaseOp = X86ISD::SUB;
17361 Cond = X86::COND_O;
17364 BaseOp = X86ISD::SUB;
17365 Cond = X86::COND_B;
17368 BaseOp = X86ISD::SMUL;
17369 Cond = X86::COND_O;
17371 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17372 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17374 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17377 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17378 DAG.getConstant(X86::COND_O, MVT::i32),
17379 SDValue(Sum.getNode(), 2));
17381 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17385 // Also sets EFLAGS.
17386 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17387 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17390 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17391 DAG.getConstant(Cond, MVT::i32),
17392 SDValue(Sum.getNode(), 1));
17394 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17397 // Sign extension of the low part of vector elements. This may be used either
17398 // when sign extend instructions are not available or if the vector element
17399 // sizes already match the sign-extended size. If the vector elements are in
17400 // their pre-extended size and sign extend instructions are available, that will
17401 // be handled by LowerSIGN_EXTEND.
17402 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17403 SelectionDAG &DAG) const {
17405 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17406 MVT VT = Op.getSimpleValueType();
17408 if (!Subtarget->hasSSE2() || !VT.isVector())
17411 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17412 ExtraVT.getScalarType().getSizeInBits();
17414 switch (VT.SimpleTy) {
17415 default: return SDValue();
17418 if (!Subtarget->hasFp256())
17420 if (!Subtarget->hasInt256()) {
17421 // needs to be split
17422 unsigned NumElems = VT.getVectorNumElements();
17424 // Extract the LHS vectors
17425 SDValue LHS = Op.getOperand(0);
17426 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17427 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17429 MVT EltVT = VT.getVectorElementType();
17430 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17432 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17433 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17434 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17436 SDValue Extra = DAG.getValueType(ExtraVT);
17438 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17439 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17441 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17446 SDValue Op0 = Op.getOperand(0);
17448 // This is a sign extension of some low part of vector elements without
17449 // changing the size of the vector elements themselves:
17450 // Shift-Left + Shift-Right-Algebraic.
17451 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17453 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17459 /// Returns true if the operand type is exactly twice the native width, and
17460 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17461 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17462 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17463 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17464 const X86Subtarget &Subtarget =
17465 getTargetMachine().getSubtarget<X86Subtarget>();
17466 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17469 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17470 else if (OpWidth == 128)
17471 return Subtarget.hasCmpxchg16b();
17476 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17477 return needsCmpXchgNb(SI->getValueOperand()->getType());
17480 // Note: this turns large loads into lock cmpxchg8b/16b.
17481 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17482 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17483 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17484 return needsCmpXchgNb(PTy->getElementType());
17487 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17488 const X86Subtarget &Subtarget =
17489 getTargetMachine().getSubtarget<X86Subtarget>();
17490 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17491 const Type *MemType = AI->getType();
17493 // If the operand is too big, we must see if cmpxchg8/16b is available
17494 // and default to library calls otherwise.
17495 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17496 return needsCmpXchgNb(MemType);
17498 AtomicRMWInst::BinOp Op = AI->getOperation();
17501 llvm_unreachable("Unknown atomic operation");
17502 case AtomicRMWInst::Xchg:
17503 case AtomicRMWInst::Add:
17504 case AtomicRMWInst::Sub:
17505 // It's better to use xadd, xsub or xchg for these in all cases.
17507 case AtomicRMWInst::Or:
17508 case AtomicRMWInst::And:
17509 case AtomicRMWInst::Xor:
17510 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17511 // prefix to a normal instruction for these operations.
17512 return !AI->use_empty();
17513 case AtomicRMWInst::Nand:
17514 case AtomicRMWInst::Max:
17515 case AtomicRMWInst::Min:
17516 case AtomicRMWInst::UMax:
17517 case AtomicRMWInst::UMin:
17518 // These always require a non-trivial set of data operations on x86. We must
17519 // use a cmpxchg loop.
17524 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17525 SelectionDAG &DAG) {
17527 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17528 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17529 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17530 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17532 // The only fence that needs an instruction is a sequentially-consistent
17533 // cross-thread fence.
17534 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17535 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17536 // no-sse2). There isn't any reason to disable it if the target processor
17538 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17539 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17541 SDValue Chain = Op.getOperand(0);
17542 SDValue Zero = DAG.getConstant(0, MVT::i32);
17544 DAG.getRegister(X86::ESP, MVT::i32), // Base
17545 DAG.getTargetConstant(1, MVT::i8), // Scale
17546 DAG.getRegister(0, MVT::i32), // Index
17547 DAG.getTargetConstant(0, MVT::i32), // Disp
17548 DAG.getRegister(0, MVT::i32), // Segment.
17552 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17553 return SDValue(Res, 0);
17556 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17557 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17560 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17561 SelectionDAG &DAG) {
17562 MVT T = Op.getSimpleValueType();
17566 switch(T.SimpleTy) {
17567 default: llvm_unreachable("Invalid value type!");
17568 case MVT::i8: Reg = X86::AL; size = 1; break;
17569 case MVT::i16: Reg = X86::AX; size = 2; break;
17570 case MVT::i32: Reg = X86::EAX; size = 4; break;
17572 assert(Subtarget->is64Bit() && "Node not type legal!");
17573 Reg = X86::RAX; size = 8;
17576 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17577 Op.getOperand(2), SDValue());
17578 SDValue Ops[] = { cpIn.getValue(0),
17581 DAG.getTargetConstant(size, MVT::i8),
17582 cpIn.getValue(1) };
17583 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17584 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17585 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17589 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17590 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17591 MVT::i32, cpOut.getValue(2));
17592 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17593 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17595 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17596 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17597 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17601 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17602 SelectionDAG &DAG) {
17603 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17604 MVT DstVT = Op.getSimpleValueType();
17606 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17607 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17608 if (DstVT != MVT::f64)
17609 // This conversion needs to be expanded.
17612 SDValue InVec = Op->getOperand(0);
17614 unsigned NumElts = SrcVT.getVectorNumElements();
17615 EVT SVT = SrcVT.getVectorElementType();
17617 // Widen the vector in input in the case of MVT::v2i32.
17618 // Example: from MVT::v2i32 to MVT::v4i32.
17619 SmallVector<SDValue, 16> Elts;
17620 for (unsigned i = 0, e = NumElts; i != e; ++i)
17621 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17622 DAG.getIntPtrConstant(i)));
17624 // Explicitly mark the extra elements as Undef.
17625 SDValue Undef = DAG.getUNDEF(SVT);
17626 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17627 Elts.push_back(Undef);
17629 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17630 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17631 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17632 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17633 DAG.getIntPtrConstant(0));
17636 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17637 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17638 assert((DstVT == MVT::i64 ||
17639 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17640 "Unexpected custom BITCAST");
17641 // i64 <=> MMX conversions are Legal.
17642 if (SrcVT==MVT::i64 && DstVT.isVector())
17644 if (DstVT==MVT::i64 && SrcVT.isVector())
17646 // MMX <=> MMX conversions are Legal.
17647 if (SrcVT.isVector() && DstVT.isVector())
17649 // All other conversions need to be expanded.
17653 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17654 SDNode *Node = Op.getNode();
17656 EVT T = Node->getValueType(0);
17657 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17658 DAG.getConstant(0, T), Node->getOperand(2));
17659 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17660 cast<AtomicSDNode>(Node)->getMemoryVT(),
17661 Node->getOperand(0),
17662 Node->getOperand(1), negOp,
17663 cast<AtomicSDNode>(Node)->getMemOperand(),
17664 cast<AtomicSDNode>(Node)->getOrdering(),
17665 cast<AtomicSDNode>(Node)->getSynchScope());
17668 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17669 SDNode *Node = Op.getNode();
17671 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17673 // Convert seq_cst store -> xchg
17674 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17675 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17676 // (The only way to get a 16-byte store is cmpxchg16b)
17677 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17678 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17679 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17680 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17681 cast<AtomicSDNode>(Node)->getMemoryVT(),
17682 Node->getOperand(0),
17683 Node->getOperand(1), Node->getOperand(2),
17684 cast<AtomicSDNode>(Node)->getMemOperand(),
17685 cast<AtomicSDNode>(Node)->getOrdering(),
17686 cast<AtomicSDNode>(Node)->getSynchScope());
17687 return Swap.getValue(1);
17689 // Other atomic stores have a simple pattern.
17693 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17694 EVT VT = Op.getNode()->getSimpleValueType(0);
17696 // Let legalize expand this if it isn't a legal type yet.
17697 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17700 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17703 bool ExtraOp = false;
17704 switch (Op.getOpcode()) {
17705 default: llvm_unreachable("Invalid code");
17706 case ISD::ADDC: Opc = X86ISD::ADD; break;
17707 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17708 case ISD::SUBC: Opc = X86ISD::SUB; break;
17709 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17713 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17715 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17716 Op.getOperand(1), Op.getOperand(2));
17719 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17720 SelectionDAG &DAG) {
17721 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17723 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17724 // which returns the values as { float, float } (in XMM0) or
17725 // { double, double } (which is returned in XMM0, XMM1).
17727 SDValue Arg = Op.getOperand(0);
17728 EVT ArgVT = Arg.getValueType();
17729 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17731 TargetLowering::ArgListTy Args;
17732 TargetLowering::ArgListEntry Entry;
17736 Entry.isSExt = false;
17737 Entry.isZExt = false;
17738 Args.push_back(Entry);
17740 bool isF64 = ArgVT == MVT::f64;
17741 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17742 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17743 // the results are returned via SRet in memory.
17744 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17745 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17746 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17748 Type *RetTy = isF64
17749 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17750 : (Type*)VectorType::get(ArgTy, 4);
17752 TargetLowering::CallLoweringInfo CLI(DAG);
17753 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17754 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17756 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17759 // Returned in xmm0 and xmm1.
17760 return CallResult.first;
17762 // Returned in bits 0:31 and 32:64 xmm0.
17763 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17764 CallResult.first, DAG.getIntPtrConstant(0));
17765 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17766 CallResult.first, DAG.getIntPtrConstant(1));
17767 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17768 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17771 /// LowerOperation - Provide custom lowering hooks for some operations.
17773 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17774 switch (Op.getOpcode()) {
17775 default: llvm_unreachable("Should not custom lower this!");
17776 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17777 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17778 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17779 return LowerCMP_SWAP(Op, Subtarget, DAG);
17780 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17781 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17782 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17783 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17784 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17785 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17786 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17787 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17788 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17789 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17790 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17791 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17792 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17793 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17794 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17795 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17796 case ISD::SHL_PARTS:
17797 case ISD::SRA_PARTS:
17798 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17799 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17800 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17801 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17802 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17803 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17804 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17805 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17806 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17807 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17808 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17810 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17811 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17812 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17813 case ISD::SETCC: return LowerSETCC(Op, DAG);
17814 case ISD::SELECT: return LowerSELECT(Op, DAG);
17815 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17816 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17817 case ISD::VASTART: return LowerVASTART(Op, DAG);
17818 case ISD::VAARG: return LowerVAARG(Op, DAG);
17819 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17820 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17821 case ISD::INTRINSIC_VOID:
17822 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17823 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17824 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17825 case ISD::FRAME_TO_ARGS_OFFSET:
17826 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17827 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17828 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17829 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17830 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17831 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17832 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17833 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17834 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17835 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17836 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17837 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17838 case ISD::UMUL_LOHI:
17839 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17842 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17848 case ISD::UMULO: return LowerXALUO(Op, DAG);
17849 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17850 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17854 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17855 case ISD::ADD: return LowerADD(Op, DAG);
17856 case ISD::SUB: return LowerSUB(Op, DAG);
17857 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17861 /// ReplaceNodeResults - Replace a node with an illegal result type
17862 /// with a new node built out of custom code.
17863 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17864 SmallVectorImpl<SDValue>&Results,
17865 SelectionDAG &DAG) const {
17867 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17868 switch (N->getOpcode()) {
17870 llvm_unreachable("Do not know how to custom type legalize this operation!");
17871 case ISD::SIGN_EXTEND_INREG:
17876 // We don't want to expand or promote these.
17883 case ISD::UDIVREM: {
17884 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17885 Results.push_back(V);
17888 case ISD::FP_TO_SINT:
17889 case ISD::FP_TO_UINT: {
17890 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17892 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17895 std::pair<SDValue,SDValue> Vals =
17896 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17897 SDValue FIST = Vals.first, StackSlot = Vals.second;
17898 if (FIST.getNode()) {
17899 EVT VT = N->getValueType(0);
17900 // Return a load from the stack slot.
17901 if (StackSlot.getNode())
17902 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17903 MachinePointerInfo(),
17904 false, false, false, 0));
17906 Results.push_back(FIST);
17910 case ISD::UINT_TO_FP: {
17911 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17912 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17913 N->getValueType(0) != MVT::v2f32)
17915 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17917 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17919 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17920 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17921 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17922 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17923 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17924 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17927 case ISD::FP_ROUND: {
17928 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17930 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17931 Results.push_back(V);
17934 case ISD::INTRINSIC_W_CHAIN: {
17935 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17937 default : llvm_unreachable("Do not know how to custom type "
17938 "legalize this intrinsic operation!");
17939 case Intrinsic::x86_rdtsc:
17940 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17942 case Intrinsic::x86_rdtscp:
17943 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17945 case Intrinsic::x86_rdpmc:
17946 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17949 case ISD::READCYCLECOUNTER: {
17950 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17953 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17954 EVT T = N->getValueType(0);
17955 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17956 bool Regs64bit = T == MVT::i128;
17957 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17958 SDValue cpInL, cpInH;
17959 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17960 DAG.getConstant(0, HalfT));
17961 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17962 DAG.getConstant(1, HalfT));
17963 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17964 Regs64bit ? X86::RAX : X86::EAX,
17966 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17967 Regs64bit ? X86::RDX : X86::EDX,
17968 cpInH, cpInL.getValue(1));
17969 SDValue swapInL, swapInH;
17970 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17971 DAG.getConstant(0, HalfT));
17972 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17973 DAG.getConstant(1, HalfT));
17974 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17975 Regs64bit ? X86::RBX : X86::EBX,
17976 swapInL, cpInH.getValue(1));
17977 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17978 Regs64bit ? X86::RCX : X86::ECX,
17979 swapInH, swapInL.getValue(1));
17980 SDValue Ops[] = { swapInH.getValue(0),
17982 swapInH.getValue(1) };
17983 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17984 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17985 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17986 X86ISD::LCMPXCHG8_DAG;
17987 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17988 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17989 Regs64bit ? X86::RAX : X86::EAX,
17990 HalfT, Result.getValue(1));
17991 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17992 Regs64bit ? X86::RDX : X86::EDX,
17993 HalfT, cpOutL.getValue(2));
17994 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17996 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17997 MVT::i32, cpOutH.getValue(2));
17999 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18000 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18001 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18003 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18004 Results.push_back(Success);
18005 Results.push_back(EFLAGS.getValue(1));
18008 case ISD::ATOMIC_SWAP:
18009 case ISD::ATOMIC_LOAD_ADD:
18010 case ISD::ATOMIC_LOAD_SUB:
18011 case ISD::ATOMIC_LOAD_AND:
18012 case ISD::ATOMIC_LOAD_OR:
18013 case ISD::ATOMIC_LOAD_XOR:
18014 case ISD::ATOMIC_LOAD_NAND:
18015 case ISD::ATOMIC_LOAD_MIN:
18016 case ISD::ATOMIC_LOAD_MAX:
18017 case ISD::ATOMIC_LOAD_UMIN:
18018 case ISD::ATOMIC_LOAD_UMAX:
18019 case ISD::ATOMIC_LOAD: {
18020 // Delegate to generic TypeLegalization. Situations we can really handle
18021 // should have already been dealt with by AtomicExpandPass.cpp.
18024 case ISD::BITCAST: {
18025 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18026 EVT DstVT = N->getValueType(0);
18027 EVT SrcVT = N->getOperand(0)->getValueType(0);
18029 if (SrcVT != MVT::f64 ||
18030 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18033 unsigned NumElts = DstVT.getVectorNumElements();
18034 EVT SVT = DstVT.getVectorElementType();
18035 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18036 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18037 MVT::v2f64, N->getOperand(0));
18038 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18040 if (ExperimentalVectorWideningLegalization) {
18041 // If we are legalizing vectors by widening, we already have the desired
18042 // legal vector type, just return it.
18043 Results.push_back(ToVecInt);
18047 SmallVector<SDValue, 8> Elts;
18048 for (unsigned i = 0, e = NumElts; i != e; ++i)
18049 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18050 ToVecInt, DAG.getIntPtrConstant(i)));
18052 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18057 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18059 default: return nullptr;
18060 case X86ISD::BSF: return "X86ISD::BSF";
18061 case X86ISD::BSR: return "X86ISD::BSR";
18062 case X86ISD::SHLD: return "X86ISD::SHLD";
18063 case X86ISD::SHRD: return "X86ISD::SHRD";
18064 case X86ISD::FAND: return "X86ISD::FAND";
18065 case X86ISD::FANDN: return "X86ISD::FANDN";
18066 case X86ISD::FOR: return "X86ISD::FOR";
18067 case X86ISD::FXOR: return "X86ISD::FXOR";
18068 case X86ISD::FSRL: return "X86ISD::FSRL";
18069 case X86ISD::FILD: return "X86ISD::FILD";
18070 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18071 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18072 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18073 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18074 case X86ISD::FLD: return "X86ISD::FLD";
18075 case X86ISD::FST: return "X86ISD::FST";
18076 case X86ISD::CALL: return "X86ISD::CALL";
18077 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18078 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18079 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18080 case X86ISD::BT: return "X86ISD::BT";
18081 case X86ISD::CMP: return "X86ISD::CMP";
18082 case X86ISD::COMI: return "X86ISD::COMI";
18083 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18084 case X86ISD::CMPM: return "X86ISD::CMPM";
18085 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18086 case X86ISD::SETCC: return "X86ISD::SETCC";
18087 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18088 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18089 case X86ISD::CMOV: return "X86ISD::CMOV";
18090 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18091 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18092 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18093 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18094 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18095 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18096 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18097 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18098 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18099 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18100 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18101 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18102 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18103 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18104 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18105 case X86ISD::BLENDV: return "X86ISD::BLENDV";
18106 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18107 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18108 case X86ISD::HADD: return "X86ISD::HADD";
18109 case X86ISD::HSUB: return "X86ISD::HSUB";
18110 case X86ISD::FHADD: return "X86ISD::FHADD";
18111 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18112 case X86ISD::UMAX: return "X86ISD::UMAX";
18113 case X86ISD::UMIN: return "X86ISD::UMIN";
18114 case X86ISD::SMAX: return "X86ISD::SMAX";
18115 case X86ISD::SMIN: return "X86ISD::SMIN";
18116 case X86ISD::FMAX: return "X86ISD::FMAX";
18117 case X86ISD::FMIN: return "X86ISD::FMIN";
18118 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18119 case X86ISD::FMINC: return "X86ISD::FMINC";
18120 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18121 case X86ISD::FRCP: return "X86ISD::FRCP";
18122 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18123 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18124 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18125 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18126 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18127 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18128 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18129 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18130 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18131 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18132 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18133 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18134 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18135 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18136 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18137 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18138 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18139 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18140 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18141 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18142 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18143 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18144 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18145 case X86ISD::VSHL: return "X86ISD::VSHL";
18146 case X86ISD::VSRL: return "X86ISD::VSRL";
18147 case X86ISD::VSRA: return "X86ISD::VSRA";
18148 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18149 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18150 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18151 case X86ISD::CMPP: return "X86ISD::CMPP";
18152 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18153 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18154 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18155 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18156 case X86ISD::ADD: return "X86ISD::ADD";
18157 case X86ISD::SUB: return "X86ISD::SUB";
18158 case X86ISD::ADC: return "X86ISD::ADC";
18159 case X86ISD::SBB: return "X86ISD::SBB";
18160 case X86ISD::SMUL: return "X86ISD::SMUL";
18161 case X86ISD::UMUL: return "X86ISD::UMUL";
18162 case X86ISD::INC: return "X86ISD::INC";
18163 case X86ISD::DEC: return "X86ISD::DEC";
18164 case X86ISD::OR: return "X86ISD::OR";
18165 case X86ISD::XOR: return "X86ISD::XOR";
18166 case X86ISD::AND: return "X86ISD::AND";
18167 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18168 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18169 case X86ISD::PTEST: return "X86ISD::PTEST";
18170 case X86ISD::TESTP: return "X86ISD::TESTP";
18171 case X86ISD::TESTM: return "X86ISD::TESTM";
18172 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18173 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18174 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18175 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18176 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18177 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18178 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18179 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18180 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18181 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18182 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18183 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18184 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18185 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18186 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18187 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18188 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18189 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18190 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18191 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18192 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18193 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18194 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18195 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18196 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18197 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18198 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18199 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18200 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18201 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18202 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18203 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18204 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18205 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18206 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18207 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18208 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18209 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18210 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18211 case X86ISD::SAHF: return "X86ISD::SAHF";
18212 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18213 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18214 case X86ISD::FMADD: return "X86ISD::FMADD";
18215 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18216 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18217 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18218 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18219 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18220 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18221 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18222 case X86ISD::XTEST: return "X86ISD::XTEST";
18226 // isLegalAddressingMode - Return true if the addressing mode represented
18227 // by AM is legal for this target, for a load/store of the specified type.
18228 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18230 // X86 supports extremely general addressing modes.
18231 CodeModel::Model M = getTargetMachine().getCodeModel();
18232 Reloc::Model R = getTargetMachine().getRelocationModel();
18234 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18235 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18240 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18242 // If a reference to this global requires an extra load, we can't fold it.
18243 if (isGlobalStubReference(GVFlags))
18246 // If BaseGV requires a register for the PIC base, we cannot also have a
18247 // BaseReg specified.
18248 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18251 // If lower 4G is not available, then we must use rip-relative addressing.
18252 if ((M != CodeModel::Small || R != Reloc::Static) &&
18253 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18257 switch (AM.Scale) {
18263 // These scales always work.
18268 // These scales are formed with basereg+scalereg. Only accept if there is
18273 default: // Other stuff never works.
18280 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18281 unsigned Bits = Ty->getScalarSizeInBits();
18283 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18284 // particularly cheaper than those without.
18288 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18289 // variable shifts just as cheap as scalar ones.
18290 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18293 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18294 // fully general vector.
18298 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18299 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18301 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18302 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18303 return NumBits1 > NumBits2;
18306 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18307 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18310 if (!isTypeLegal(EVT::getEVT(Ty1)))
18313 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18315 // Assuming the caller doesn't have a zeroext or signext return parameter,
18316 // truncation all the way down to i1 is valid.
18320 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18321 return isInt<32>(Imm);
18324 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18325 // Can also use sub to handle negated immediates.
18326 return isInt<32>(Imm);
18329 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18330 if (!VT1.isInteger() || !VT2.isInteger())
18332 unsigned NumBits1 = VT1.getSizeInBits();
18333 unsigned NumBits2 = VT2.getSizeInBits();
18334 return NumBits1 > NumBits2;
18337 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18338 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18339 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18342 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18343 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18344 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18347 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18348 EVT VT1 = Val.getValueType();
18349 if (isZExtFree(VT1, VT2))
18352 if (Val.getOpcode() != ISD::LOAD)
18355 if (!VT1.isSimple() || !VT1.isInteger() ||
18356 !VT2.isSimple() || !VT2.isInteger())
18359 switch (VT1.getSimpleVT().SimpleTy) {
18364 // X86 has 8, 16, and 32-bit zero-extending loads.
18372 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18373 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18376 VT = VT.getScalarType();
18378 if (!VT.isSimple())
18381 switch (VT.getSimpleVT().SimpleTy) {
18392 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18393 // i16 instructions are longer (0x66 prefix) and potentially slower.
18394 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18397 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18398 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18399 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18400 /// are assumed to be legal.
18402 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18404 if (!VT.isSimple())
18407 MVT SVT = VT.getSimpleVT();
18409 // Very little shuffling can be done for 64-bit vectors right now.
18410 if (VT.getSizeInBits() == 64)
18413 // If this is a single-input shuffle with no 128 bit lane crossings we can
18414 // lower it into pshufb.
18415 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18416 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18417 bool isLegal = true;
18418 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18419 if (M[I] >= (int)SVT.getVectorNumElements() ||
18420 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18429 // FIXME: blends, shifts.
18430 return (SVT.getVectorNumElements() == 2 ||
18431 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18432 isMOVLMask(M, SVT) ||
18433 isMOVHLPSMask(M, SVT) ||
18434 isSHUFPMask(M, SVT) ||
18435 isPSHUFDMask(M, SVT) ||
18436 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18437 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18438 isPALIGNRMask(M, SVT, Subtarget) ||
18439 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18440 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18441 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18442 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18443 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18447 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18449 if (!VT.isSimple())
18452 MVT SVT = VT.getSimpleVT();
18453 unsigned NumElts = SVT.getVectorNumElements();
18454 // FIXME: This collection of masks seems suspect.
18457 if (NumElts == 4 && SVT.is128BitVector()) {
18458 return (isMOVLMask(Mask, SVT) ||
18459 isCommutedMOVLMask(Mask, SVT, true) ||
18460 isSHUFPMask(Mask, SVT) ||
18461 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18466 //===----------------------------------------------------------------------===//
18467 // X86 Scheduler Hooks
18468 //===----------------------------------------------------------------------===//
18470 /// Utility function to emit xbegin specifying the start of an RTM region.
18471 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18472 const TargetInstrInfo *TII) {
18473 DebugLoc DL = MI->getDebugLoc();
18475 const BasicBlock *BB = MBB->getBasicBlock();
18476 MachineFunction::iterator I = MBB;
18479 // For the v = xbegin(), we generate
18490 MachineBasicBlock *thisMBB = MBB;
18491 MachineFunction *MF = MBB->getParent();
18492 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18493 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18494 MF->insert(I, mainMBB);
18495 MF->insert(I, sinkMBB);
18497 // Transfer the remainder of BB and its successor edges to sinkMBB.
18498 sinkMBB->splice(sinkMBB->begin(), MBB,
18499 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18500 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18504 // # fallthrough to mainMBB
18505 // # abortion to sinkMBB
18506 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18507 thisMBB->addSuccessor(mainMBB);
18508 thisMBB->addSuccessor(sinkMBB);
18512 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18513 mainMBB->addSuccessor(sinkMBB);
18516 // EAX is live into the sinkMBB
18517 sinkMBB->addLiveIn(X86::EAX);
18518 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18519 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18522 MI->eraseFromParent();
18526 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18527 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18528 // in the .td file.
18529 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18530 const TargetInstrInfo *TII) {
18532 switch (MI->getOpcode()) {
18533 default: llvm_unreachable("illegal opcode!");
18534 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18535 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18536 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18537 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18538 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18539 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18540 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18541 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18544 DebugLoc dl = MI->getDebugLoc();
18545 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18547 unsigned NumArgs = MI->getNumOperands();
18548 for (unsigned i = 1; i < NumArgs; ++i) {
18549 MachineOperand &Op = MI->getOperand(i);
18550 if (!(Op.isReg() && Op.isImplicit()))
18551 MIB.addOperand(Op);
18553 if (MI->hasOneMemOperand())
18554 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18556 BuildMI(*BB, MI, dl,
18557 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18558 .addReg(X86::XMM0);
18560 MI->eraseFromParent();
18564 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18565 // defs in an instruction pattern
18566 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18567 const TargetInstrInfo *TII) {
18569 switch (MI->getOpcode()) {
18570 default: llvm_unreachable("illegal opcode!");
18571 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18572 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18573 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18574 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18575 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18576 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18577 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18578 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18581 DebugLoc dl = MI->getDebugLoc();
18582 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18584 unsigned NumArgs = MI->getNumOperands(); // remove the results
18585 for (unsigned i = 1; i < NumArgs; ++i) {
18586 MachineOperand &Op = MI->getOperand(i);
18587 if (!(Op.isReg() && Op.isImplicit()))
18588 MIB.addOperand(Op);
18590 if (MI->hasOneMemOperand())
18591 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18593 BuildMI(*BB, MI, dl,
18594 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18597 MI->eraseFromParent();
18601 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18602 const TargetInstrInfo *TII,
18603 const X86Subtarget* Subtarget) {
18604 DebugLoc dl = MI->getDebugLoc();
18606 // Address into RAX/EAX, other two args into ECX, EDX.
18607 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18608 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18609 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18610 for (int i = 0; i < X86::AddrNumOperands; ++i)
18611 MIB.addOperand(MI->getOperand(i));
18613 unsigned ValOps = X86::AddrNumOperands;
18614 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18615 .addReg(MI->getOperand(ValOps).getReg());
18616 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18617 .addReg(MI->getOperand(ValOps+1).getReg());
18619 // The instruction doesn't actually take any operands though.
18620 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18622 MI->eraseFromParent(); // The pseudo is gone now.
18626 MachineBasicBlock *
18627 X86TargetLowering::EmitVAARG64WithCustomInserter(
18629 MachineBasicBlock *MBB) const {
18630 // Emit va_arg instruction on X86-64.
18632 // Operands to this pseudo-instruction:
18633 // 0 ) Output : destination address (reg)
18634 // 1-5) Input : va_list address (addr, i64mem)
18635 // 6 ) ArgSize : Size (in bytes) of vararg type
18636 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18637 // 8 ) Align : Alignment of type
18638 // 9 ) EFLAGS (implicit-def)
18640 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18641 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18643 unsigned DestReg = MI->getOperand(0).getReg();
18644 MachineOperand &Base = MI->getOperand(1);
18645 MachineOperand &Scale = MI->getOperand(2);
18646 MachineOperand &Index = MI->getOperand(3);
18647 MachineOperand &Disp = MI->getOperand(4);
18648 MachineOperand &Segment = MI->getOperand(5);
18649 unsigned ArgSize = MI->getOperand(6).getImm();
18650 unsigned ArgMode = MI->getOperand(7).getImm();
18651 unsigned Align = MI->getOperand(8).getImm();
18653 // Memory Reference
18654 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18655 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18656 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18658 // Machine Information
18659 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18660 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18661 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18662 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18663 DebugLoc DL = MI->getDebugLoc();
18665 // struct va_list {
18668 // i64 overflow_area (address)
18669 // i64 reg_save_area (address)
18671 // sizeof(va_list) = 24
18672 // alignment(va_list) = 8
18674 unsigned TotalNumIntRegs = 6;
18675 unsigned TotalNumXMMRegs = 8;
18676 bool UseGPOffset = (ArgMode == 1);
18677 bool UseFPOffset = (ArgMode == 2);
18678 unsigned MaxOffset = TotalNumIntRegs * 8 +
18679 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18681 /* Align ArgSize to a multiple of 8 */
18682 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18683 bool NeedsAlign = (Align > 8);
18685 MachineBasicBlock *thisMBB = MBB;
18686 MachineBasicBlock *overflowMBB;
18687 MachineBasicBlock *offsetMBB;
18688 MachineBasicBlock *endMBB;
18690 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18691 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18692 unsigned OffsetReg = 0;
18694 if (!UseGPOffset && !UseFPOffset) {
18695 // If we only pull from the overflow region, we don't create a branch.
18696 // We don't need to alter control flow.
18697 OffsetDestReg = 0; // unused
18698 OverflowDestReg = DestReg;
18700 offsetMBB = nullptr;
18701 overflowMBB = thisMBB;
18704 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18705 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18706 // If not, pull from overflow_area. (branch to overflowMBB)
18711 // offsetMBB overflowMBB
18716 // Registers for the PHI in endMBB
18717 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18718 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18720 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18721 MachineFunction *MF = MBB->getParent();
18722 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18723 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18724 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18726 MachineFunction::iterator MBBIter = MBB;
18729 // Insert the new basic blocks
18730 MF->insert(MBBIter, offsetMBB);
18731 MF->insert(MBBIter, overflowMBB);
18732 MF->insert(MBBIter, endMBB);
18734 // Transfer the remainder of MBB and its successor edges to endMBB.
18735 endMBB->splice(endMBB->begin(), thisMBB,
18736 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18737 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18739 // Make offsetMBB and overflowMBB successors of thisMBB
18740 thisMBB->addSuccessor(offsetMBB);
18741 thisMBB->addSuccessor(overflowMBB);
18743 // endMBB is a successor of both offsetMBB and overflowMBB
18744 offsetMBB->addSuccessor(endMBB);
18745 overflowMBB->addSuccessor(endMBB);
18747 // Load the offset value into a register
18748 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18749 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18753 .addDisp(Disp, UseFPOffset ? 4 : 0)
18754 .addOperand(Segment)
18755 .setMemRefs(MMOBegin, MMOEnd);
18757 // Check if there is enough room left to pull this argument.
18758 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18760 .addImm(MaxOffset + 8 - ArgSizeA8);
18762 // Branch to "overflowMBB" if offset >= max
18763 // Fall through to "offsetMBB" otherwise
18764 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18765 .addMBB(overflowMBB);
18768 // In offsetMBB, emit code to use the reg_save_area.
18770 assert(OffsetReg != 0);
18772 // Read the reg_save_area address.
18773 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18774 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18779 .addOperand(Segment)
18780 .setMemRefs(MMOBegin, MMOEnd);
18782 // Zero-extend the offset
18783 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18784 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18787 .addImm(X86::sub_32bit);
18789 // Add the offset to the reg_save_area to get the final address.
18790 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18791 .addReg(OffsetReg64)
18792 .addReg(RegSaveReg);
18794 // Compute the offset for the next argument
18795 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18796 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18798 .addImm(UseFPOffset ? 16 : 8);
18800 // Store it back into the va_list.
18801 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18805 .addDisp(Disp, UseFPOffset ? 4 : 0)
18806 .addOperand(Segment)
18807 .addReg(NextOffsetReg)
18808 .setMemRefs(MMOBegin, MMOEnd);
18811 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18816 // Emit code to use overflow area
18819 // Load the overflow_area address into a register.
18820 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18821 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18826 .addOperand(Segment)
18827 .setMemRefs(MMOBegin, MMOEnd);
18829 // If we need to align it, do so. Otherwise, just copy the address
18830 // to OverflowDestReg.
18832 // Align the overflow address
18833 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18834 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18836 // aligned_addr = (addr + (align-1)) & ~(align-1)
18837 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18838 .addReg(OverflowAddrReg)
18841 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18843 .addImm(~(uint64_t)(Align-1));
18845 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18846 .addReg(OverflowAddrReg);
18849 // Compute the next overflow address after this argument.
18850 // (the overflow address should be kept 8-byte aligned)
18851 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18852 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18853 .addReg(OverflowDestReg)
18854 .addImm(ArgSizeA8);
18856 // Store the new overflow address.
18857 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18862 .addOperand(Segment)
18863 .addReg(NextAddrReg)
18864 .setMemRefs(MMOBegin, MMOEnd);
18866 // If we branched, emit the PHI to the front of endMBB.
18868 BuildMI(*endMBB, endMBB->begin(), DL,
18869 TII->get(X86::PHI), DestReg)
18870 .addReg(OffsetDestReg).addMBB(offsetMBB)
18871 .addReg(OverflowDestReg).addMBB(overflowMBB);
18874 // Erase the pseudo instruction
18875 MI->eraseFromParent();
18880 MachineBasicBlock *
18881 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18883 MachineBasicBlock *MBB) const {
18884 // Emit code to save XMM registers to the stack. The ABI says that the
18885 // number of registers to save is given in %al, so it's theoretically
18886 // possible to do an indirect jump trick to avoid saving all of them,
18887 // however this code takes a simpler approach and just executes all
18888 // of the stores if %al is non-zero. It's less code, and it's probably
18889 // easier on the hardware branch predictor, and stores aren't all that
18890 // expensive anyway.
18892 // Create the new basic blocks. One block contains all the XMM stores,
18893 // and one block is the final destination regardless of whether any
18894 // stores were performed.
18895 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18896 MachineFunction *F = MBB->getParent();
18897 MachineFunction::iterator MBBIter = MBB;
18899 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18900 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18901 F->insert(MBBIter, XMMSaveMBB);
18902 F->insert(MBBIter, EndMBB);
18904 // Transfer the remainder of MBB and its successor edges to EndMBB.
18905 EndMBB->splice(EndMBB->begin(), MBB,
18906 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18907 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18909 // The original block will now fall through to the XMM save block.
18910 MBB->addSuccessor(XMMSaveMBB);
18911 // The XMMSaveMBB will fall through to the end block.
18912 XMMSaveMBB->addSuccessor(EndMBB);
18914 // Now add the instructions.
18915 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18916 DebugLoc DL = MI->getDebugLoc();
18918 unsigned CountReg = MI->getOperand(0).getReg();
18919 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18920 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18922 if (!Subtarget->isTargetWin64()) {
18923 // If %al is 0, branch around the XMM save block.
18924 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18925 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18926 MBB->addSuccessor(EndMBB);
18929 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18930 // that was just emitted, but clearly shouldn't be "saved".
18931 assert((MI->getNumOperands() <= 3 ||
18932 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18933 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18934 && "Expected last argument to be EFLAGS");
18935 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18936 // In the XMM save block, save all the XMM argument registers.
18937 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18938 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18939 MachineMemOperand *MMO =
18940 F->getMachineMemOperand(
18941 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18942 MachineMemOperand::MOStore,
18943 /*Size=*/16, /*Align=*/16);
18944 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18945 .addFrameIndex(RegSaveFrameIndex)
18946 .addImm(/*Scale=*/1)
18947 .addReg(/*IndexReg=*/0)
18948 .addImm(/*Disp=*/Offset)
18949 .addReg(/*Segment=*/0)
18950 .addReg(MI->getOperand(i).getReg())
18951 .addMemOperand(MMO);
18954 MI->eraseFromParent(); // The pseudo instruction is gone now.
18959 // The EFLAGS operand of SelectItr might be missing a kill marker
18960 // because there were multiple uses of EFLAGS, and ISel didn't know
18961 // which to mark. Figure out whether SelectItr should have had a
18962 // kill marker, and set it if it should. Returns the correct kill
18964 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18965 MachineBasicBlock* BB,
18966 const TargetRegisterInfo* TRI) {
18967 // Scan forward through BB for a use/def of EFLAGS.
18968 MachineBasicBlock::iterator miI(std::next(SelectItr));
18969 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18970 const MachineInstr& mi = *miI;
18971 if (mi.readsRegister(X86::EFLAGS))
18973 if (mi.definesRegister(X86::EFLAGS))
18974 break; // Should have kill-flag - update below.
18977 // If we hit the end of the block, check whether EFLAGS is live into a
18979 if (miI == BB->end()) {
18980 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18981 sEnd = BB->succ_end();
18982 sItr != sEnd; ++sItr) {
18983 MachineBasicBlock* succ = *sItr;
18984 if (succ->isLiveIn(X86::EFLAGS))
18989 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18990 // out. SelectMI should have a kill flag on EFLAGS.
18991 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18995 MachineBasicBlock *
18996 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18997 MachineBasicBlock *BB) const {
18998 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18999 DebugLoc DL = MI->getDebugLoc();
19001 // To "insert" a SELECT_CC instruction, we actually have to insert the
19002 // diamond control-flow pattern. The incoming instruction knows the
19003 // destination vreg to set, the condition code register to branch on, the
19004 // true/false values to select between, and a branch opcode to use.
19005 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19006 MachineFunction::iterator It = BB;
19012 // cmpTY ccX, r1, r2
19014 // fallthrough --> copy0MBB
19015 MachineBasicBlock *thisMBB = BB;
19016 MachineFunction *F = BB->getParent();
19017 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19018 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19019 F->insert(It, copy0MBB);
19020 F->insert(It, sinkMBB);
19022 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19023 // live into the sink and copy blocks.
19024 const TargetRegisterInfo *TRI =
19025 BB->getParent()->getSubtarget().getRegisterInfo();
19026 if (!MI->killsRegister(X86::EFLAGS) &&
19027 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19028 copy0MBB->addLiveIn(X86::EFLAGS);
19029 sinkMBB->addLiveIn(X86::EFLAGS);
19032 // Transfer the remainder of BB and its successor edges to sinkMBB.
19033 sinkMBB->splice(sinkMBB->begin(), BB,
19034 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19035 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19037 // Add the true and fallthrough blocks as its successors.
19038 BB->addSuccessor(copy0MBB);
19039 BB->addSuccessor(sinkMBB);
19041 // Create the conditional branch instruction.
19043 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19044 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19047 // %FalseValue = ...
19048 // # fallthrough to sinkMBB
19049 copy0MBB->addSuccessor(sinkMBB);
19052 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19054 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19055 TII->get(X86::PHI), MI->getOperand(0).getReg())
19056 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19057 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19059 MI->eraseFromParent(); // The pseudo instruction is gone now.
19063 MachineBasicBlock *
19064 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19065 MachineBasicBlock *BB) const {
19066 MachineFunction *MF = BB->getParent();
19067 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19068 DebugLoc DL = MI->getDebugLoc();
19069 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19071 assert(MF->shouldSplitStack());
19073 const bool Is64Bit = Subtarget->is64Bit();
19074 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19076 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19077 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19080 // ... [Till the alloca]
19081 // If stacklet is not large enough, jump to mallocMBB
19084 // Allocate by subtracting from RSP
19085 // Jump to continueMBB
19088 // Allocate by call to runtime
19092 // [rest of original BB]
19095 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19096 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19097 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19099 MachineRegisterInfo &MRI = MF->getRegInfo();
19100 const TargetRegisterClass *AddrRegClass =
19101 getRegClassFor(getPointerTy());
19103 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19104 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19105 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19106 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19107 sizeVReg = MI->getOperand(1).getReg(),
19108 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19110 MachineFunction::iterator MBBIter = BB;
19113 MF->insert(MBBIter, bumpMBB);
19114 MF->insert(MBBIter, mallocMBB);
19115 MF->insert(MBBIter, continueMBB);
19117 continueMBB->splice(continueMBB->begin(), BB,
19118 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19119 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19121 // Add code to the main basic block to check if the stack limit has been hit,
19122 // and if so, jump to mallocMBB otherwise to bumpMBB.
19123 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19124 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19125 .addReg(tmpSPVReg).addReg(sizeVReg);
19126 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19127 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19128 .addReg(SPLimitVReg);
19129 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19131 // bumpMBB simply decreases the stack pointer, since we know the current
19132 // stacklet has enough space.
19133 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19134 .addReg(SPLimitVReg);
19135 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19136 .addReg(SPLimitVReg);
19137 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19139 // Calls into a routine in libgcc to allocate more space from the heap.
19140 const uint32_t *RegMask = MF->getTarget()
19141 .getSubtargetImpl()
19142 ->getRegisterInfo()
19143 ->getCallPreservedMask(CallingConv::C);
19145 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19147 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19148 .addExternalSymbol("__morestack_allocate_stack_space")
19149 .addRegMask(RegMask)
19150 .addReg(X86::RDI, RegState::Implicit)
19151 .addReg(X86::RAX, RegState::ImplicitDefine);
19152 } else if (Is64Bit) {
19153 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19155 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19156 .addExternalSymbol("__morestack_allocate_stack_space")
19157 .addRegMask(RegMask)
19158 .addReg(X86::EDI, RegState::Implicit)
19159 .addReg(X86::EAX, RegState::ImplicitDefine);
19161 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19163 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19164 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19165 .addExternalSymbol("__morestack_allocate_stack_space")
19166 .addRegMask(RegMask)
19167 .addReg(X86::EAX, RegState::ImplicitDefine);
19171 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19174 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19175 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19176 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19178 // Set up the CFG correctly.
19179 BB->addSuccessor(bumpMBB);
19180 BB->addSuccessor(mallocMBB);
19181 mallocMBB->addSuccessor(continueMBB);
19182 bumpMBB->addSuccessor(continueMBB);
19184 // Take care of the PHI nodes.
19185 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19186 MI->getOperand(0).getReg())
19187 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19188 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19190 // Delete the original pseudo instruction.
19191 MI->eraseFromParent();
19194 return continueMBB;
19197 MachineBasicBlock *
19198 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19199 MachineBasicBlock *BB) const {
19200 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19201 DebugLoc DL = MI->getDebugLoc();
19203 assert(!Subtarget->isTargetMacho());
19205 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19206 // non-trivial part is impdef of ESP.
19208 if (Subtarget->isTargetWin64()) {
19209 if (Subtarget->isTargetCygMing()) {
19210 // ___chkstk(Mingw64):
19211 // Clobbers R10, R11, RAX and EFLAGS.
19213 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19214 .addExternalSymbol("___chkstk")
19215 .addReg(X86::RAX, RegState::Implicit)
19216 .addReg(X86::RSP, RegState::Implicit)
19217 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19218 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19219 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19221 // __chkstk(MSVCRT): does not update stack pointer.
19222 // Clobbers R10, R11 and EFLAGS.
19223 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19224 .addExternalSymbol("__chkstk")
19225 .addReg(X86::RAX, RegState::Implicit)
19226 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19227 // RAX has the offset to be subtracted from RSP.
19228 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19233 const char *StackProbeSymbol =
19234 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19236 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19237 .addExternalSymbol(StackProbeSymbol)
19238 .addReg(X86::EAX, RegState::Implicit)
19239 .addReg(X86::ESP, RegState::Implicit)
19240 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19241 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19242 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19245 MI->eraseFromParent(); // The pseudo instruction is gone now.
19249 MachineBasicBlock *
19250 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19251 MachineBasicBlock *BB) const {
19252 // This is pretty easy. We're taking the value that we received from
19253 // our load from the relocation, sticking it in either RDI (x86-64)
19254 // or EAX and doing an indirect call. The return value will then
19255 // be in the normal return register.
19256 MachineFunction *F = BB->getParent();
19257 const X86InstrInfo *TII =
19258 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19259 DebugLoc DL = MI->getDebugLoc();
19261 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19262 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19264 // Get a register mask for the lowered call.
19265 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19266 // proper register mask.
19267 const uint32_t *RegMask = F->getTarget()
19268 .getSubtargetImpl()
19269 ->getRegisterInfo()
19270 ->getCallPreservedMask(CallingConv::C);
19271 if (Subtarget->is64Bit()) {
19272 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19273 TII->get(X86::MOV64rm), X86::RDI)
19275 .addImm(0).addReg(0)
19276 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19277 MI->getOperand(3).getTargetFlags())
19279 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19280 addDirectMem(MIB, X86::RDI);
19281 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19282 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19283 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19284 TII->get(X86::MOV32rm), X86::EAX)
19286 .addImm(0).addReg(0)
19287 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19288 MI->getOperand(3).getTargetFlags())
19290 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19291 addDirectMem(MIB, X86::EAX);
19292 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19294 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19295 TII->get(X86::MOV32rm), X86::EAX)
19296 .addReg(TII->getGlobalBaseReg(F))
19297 .addImm(0).addReg(0)
19298 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19299 MI->getOperand(3).getTargetFlags())
19301 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19302 addDirectMem(MIB, X86::EAX);
19303 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19306 MI->eraseFromParent(); // The pseudo instruction is gone now.
19310 MachineBasicBlock *
19311 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19312 MachineBasicBlock *MBB) const {
19313 DebugLoc DL = MI->getDebugLoc();
19314 MachineFunction *MF = MBB->getParent();
19315 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19316 MachineRegisterInfo &MRI = MF->getRegInfo();
19318 const BasicBlock *BB = MBB->getBasicBlock();
19319 MachineFunction::iterator I = MBB;
19322 // Memory Reference
19323 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19324 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19327 unsigned MemOpndSlot = 0;
19329 unsigned CurOp = 0;
19331 DstReg = MI->getOperand(CurOp++).getReg();
19332 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19333 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19334 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19335 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19337 MemOpndSlot = CurOp;
19339 MVT PVT = getPointerTy();
19340 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19341 "Invalid Pointer Size!");
19343 // For v = setjmp(buf), we generate
19346 // buf[LabelOffset] = restoreMBB
19347 // SjLjSetup restoreMBB
19353 // v = phi(main, restore)
19358 MachineBasicBlock *thisMBB = MBB;
19359 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19360 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19361 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19362 MF->insert(I, mainMBB);
19363 MF->insert(I, sinkMBB);
19364 MF->push_back(restoreMBB);
19366 MachineInstrBuilder MIB;
19368 // Transfer the remainder of BB and its successor edges to sinkMBB.
19369 sinkMBB->splice(sinkMBB->begin(), MBB,
19370 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19371 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19374 unsigned PtrStoreOpc = 0;
19375 unsigned LabelReg = 0;
19376 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19377 Reloc::Model RM = MF->getTarget().getRelocationModel();
19378 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19379 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19381 // Prepare IP either in reg or imm.
19382 if (!UseImmLabel) {
19383 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19384 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19385 LabelReg = MRI.createVirtualRegister(PtrRC);
19386 if (Subtarget->is64Bit()) {
19387 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19391 .addMBB(restoreMBB)
19394 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19395 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19396 .addReg(XII->getGlobalBaseReg(MF))
19399 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19403 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19405 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19406 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19407 if (i == X86::AddrDisp)
19408 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19410 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19413 MIB.addReg(LabelReg);
19415 MIB.addMBB(restoreMBB);
19416 MIB.setMemRefs(MMOBegin, MMOEnd);
19418 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19419 .addMBB(restoreMBB);
19421 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19422 MF->getSubtarget().getRegisterInfo());
19423 MIB.addRegMask(RegInfo->getNoPreservedMask());
19424 thisMBB->addSuccessor(mainMBB);
19425 thisMBB->addSuccessor(restoreMBB);
19429 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19430 mainMBB->addSuccessor(sinkMBB);
19433 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19434 TII->get(X86::PHI), DstReg)
19435 .addReg(mainDstReg).addMBB(mainMBB)
19436 .addReg(restoreDstReg).addMBB(restoreMBB);
19439 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19440 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19441 restoreMBB->addSuccessor(sinkMBB);
19443 MI->eraseFromParent();
19447 MachineBasicBlock *
19448 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19449 MachineBasicBlock *MBB) const {
19450 DebugLoc DL = MI->getDebugLoc();
19451 MachineFunction *MF = MBB->getParent();
19452 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19453 MachineRegisterInfo &MRI = MF->getRegInfo();
19455 // Memory Reference
19456 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19457 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19459 MVT PVT = getPointerTy();
19460 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19461 "Invalid Pointer Size!");
19463 const TargetRegisterClass *RC =
19464 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19465 unsigned Tmp = MRI.createVirtualRegister(RC);
19466 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19467 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19468 MF->getSubtarget().getRegisterInfo());
19469 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19470 unsigned SP = RegInfo->getStackRegister();
19472 MachineInstrBuilder MIB;
19474 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19475 const int64_t SPOffset = 2 * PVT.getStoreSize();
19477 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19478 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19481 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19482 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19483 MIB.addOperand(MI->getOperand(i));
19484 MIB.setMemRefs(MMOBegin, MMOEnd);
19486 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19487 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19488 if (i == X86::AddrDisp)
19489 MIB.addDisp(MI->getOperand(i), LabelOffset);
19491 MIB.addOperand(MI->getOperand(i));
19493 MIB.setMemRefs(MMOBegin, MMOEnd);
19495 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19496 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19497 if (i == X86::AddrDisp)
19498 MIB.addDisp(MI->getOperand(i), SPOffset);
19500 MIB.addOperand(MI->getOperand(i));
19502 MIB.setMemRefs(MMOBegin, MMOEnd);
19504 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19506 MI->eraseFromParent();
19510 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19511 // accumulator loops. Writing back to the accumulator allows the coalescer
19512 // to remove extra copies in the loop.
19513 MachineBasicBlock *
19514 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19515 MachineBasicBlock *MBB) const {
19516 MachineOperand &AddendOp = MI->getOperand(3);
19518 // Bail out early if the addend isn't a register - we can't switch these.
19519 if (!AddendOp.isReg())
19522 MachineFunction &MF = *MBB->getParent();
19523 MachineRegisterInfo &MRI = MF.getRegInfo();
19525 // Check whether the addend is defined by a PHI:
19526 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19527 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19528 if (!AddendDef.isPHI())
19531 // Look for the following pattern:
19533 // %addend = phi [%entry, 0], [%loop, %result]
19535 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19539 // %addend = phi [%entry, 0], [%loop, %result]
19541 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19543 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19544 assert(AddendDef.getOperand(i).isReg());
19545 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19546 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19547 if (&PHISrcInst == MI) {
19548 // Found a matching instruction.
19549 unsigned NewFMAOpc = 0;
19550 switch (MI->getOpcode()) {
19551 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19552 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19553 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19554 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19555 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19556 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19557 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19558 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19559 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19560 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19561 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19562 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19563 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19564 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19565 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19566 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19567 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19568 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19569 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19570 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19571 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19572 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19573 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19574 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19575 default: llvm_unreachable("Unrecognized FMA variant.");
19578 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19579 MachineInstrBuilder MIB =
19580 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19581 .addOperand(MI->getOperand(0))
19582 .addOperand(MI->getOperand(3))
19583 .addOperand(MI->getOperand(2))
19584 .addOperand(MI->getOperand(1));
19585 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19586 MI->eraseFromParent();
19593 MachineBasicBlock *
19594 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19595 MachineBasicBlock *BB) const {
19596 switch (MI->getOpcode()) {
19597 default: llvm_unreachable("Unexpected instr type to insert");
19598 case X86::TAILJMPd64:
19599 case X86::TAILJMPr64:
19600 case X86::TAILJMPm64:
19601 llvm_unreachable("TAILJMP64 would not be touched here.");
19602 case X86::TCRETURNdi64:
19603 case X86::TCRETURNri64:
19604 case X86::TCRETURNmi64:
19606 case X86::WIN_ALLOCA:
19607 return EmitLoweredWinAlloca(MI, BB);
19608 case X86::SEG_ALLOCA_32:
19609 case X86::SEG_ALLOCA_64:
19610 return EmitLoweredSegAlloca(MI, BB);
19611 case X86::TLSCall_32:
19612 case X86::TLSCall_64:
19613 return EmitLoweredTLSCall(MI, BB);
19614 case X86::CMOV_GR8:
19615 case X86::CMOV_FR32:
19616 case X86::CMOV_FR64:
19617 case X86::CMOV_V4F32:
19618 case X86::CMOV_V2F64:
19619 case X86::CMOV_V2I64:
19620 case X86::CMOV_V8F32:
19621 case X86::CMOV_V4F64:
19622 case X86::CMOV_V4I64:
19623 case X86::CMOV_V16F32:
19624 case X86::CMOV_V8F64:
19625 case X86::CMOV_V8I64:
19626 case X86::CMOV_GR16:
19627 case X86::CMOV_GR32:
19628 case X86::CMOV_RFP32:
19629 case X86::CMOV_RFP64:
19630 case X86::CMOV_RFP80:
19631 return EmitLoweredSelect(MI, BB);
19633 case X86::FP32_TO_INT16_IN_MEM:
19634 case X86::FP32_TO_INT32_IN_MEM:
19635 case X86::FP32_TO_INT64_IN_MEM:
19636 case X86::FP64_TO_INT16_IN_MEM:
19637 case X86::FP64_TO_INT32_IN_MEM:
19638 case X86::FP64_TO_INT64_IN_MEM:
19639 case X86::FP80_TO_INT16_IN_MEM:
19640 case X86::FP80_TO_INT32_IN_MEM:
19641 case X86::FP80_TO_INT64_IN_MEM: {
19642 MachineFunction *F = BB->getParent();
19643 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19644 DebugLoc DL = MI->getDebugLoc();
19646 // Change the floating point control register to use "round towards zero"
19647 // mode when truncating to an integer value.
19648 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19649 addFrameReference(BuildMI(*BB, MI, DL,
19650 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19652 // Load the old value of the high byte of the control word...
19654 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19655 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19658 // Set the high part to be round to zero...
19659 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19662 // Reload the modified control word now...
19663 addFrameReference(BuildMI(*BB, MI, DL,
19664 TII->get(X86::FLDCW16m)), CWFrameIdx);
19666 // Restore the memory image of control word to original value
19667 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19670 // Get the X86 opcode to use.
19672 switch (MI->getOpcode()) {
19673 default: llvm_unreachable("illegal opcode!");
19674 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19675 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19676 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19677 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19678 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19679 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19680 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19681 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19682 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19686 MachineOperand &Op = MI->getOperand(0);
19688 AM.BaseType = X86AddressMode::RegBase;
19689 AM.Base.Reg = Op.getReg();
19691 AM.BaseType = X86AddressMode::FrameIndexBase;
19692 AM.Base.FrameIndex = Op.getIndex();
19694 Op = MI->getOperand(1);
19696 AM.Scale = Op.getImm();
19697 Op = MI->getOperand(2);
19699 AM.IndexReg = Op.getImm();
19700 Op = MI->getOperand(3);
19701 if (Op.isGlobal()) {
19702 AM.GV = Op.getGlobal();
19704 AM.Disp = Op.getImm();
19706 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19707 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19709 // Reload the original control word now.
19710 addFrameReference(BuildMI(*BB, MI, DL,
19711 TII->get(X86::FLDCW16m)), CWFrameIdx);
19713 MI->eraseFromParent(); // The pseudo instruction is gone now.
19716 // String/text processing lowering.
19717 case X86::PCMPISTRM128REG:
19718 case X86::VPCMPISTRM128REG:
19719 case X86::PCMPISTRM128MEM:
19720 case X86::VPCMPISTRM128MEM:
19721 case X86::PCMPESTRM128REG:
19722 case X86::VPCMPESTRM128REG:
19723 case X86::PCMPESTRM128MEM:
19724 case X86::VPCMPESTRM128MEM:
19725 assert(Subtarget->hasSSE42() &&
19726 "Target must have SSE4.2 or AVX features enabled");
19727 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19729 // String/text processing lowering.
19730 case X86::PCMPISTRIREG:
19731 case X86::VPCMPISTRIREG:
19732 case X86::PCMPISTRIMEM:
19733 case X86::VPCMPISTRIMEM:
19734 case X86::PCMPESTRIREG:
19735 case X86::VPCMPESTRIREG:
19736 case X86::PCMPESTRIMEM:
19737 case X86::VPCMPESTRIMEM:
19738 assert(Subtarget->hasSSE42() &&
19739 "Target must have SSE4.2 or AVX features enabled");
19740 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19742 // Thread synchronization.
19744 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19749 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19751 case X86::VASTART_SAVE_XMM_REGS:
19752 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19754 case X86::VAARG_64:
19755 return EmitVAARG64WithCustomInserter(MI, BB);
19757 case X86::EH_SjLj_SetJmp32:
19758 case X86::EH_SjLj_SetJmp64:
19759 return emitEHSjLjSetJmp(MI, BB);
19761 case X86::EH_SjLj_LongJmp32:
19762 case X86::EH_SjLj_LongJmp64:
19763 return emitEHSjLjLongJmp(MI, BB);
19765 case TargetOpcode::STACKMAP:
19766 case TargetOpcode::PATCHPOINT:
19767 return emitPatchPoint(MI, BB);
19769 case X86::VFMADDPDr213r:
19770 case X86::VFMADDPSr213r:
19771 case X86::VFMADDSDr213r:
19772 case X86::VFMADDSSr213r:
19773 case X86::VFMSUBPDr213r:
19774 case X86::VFMSUBPSr213r:
19775 case X86::VFMSUBSDr213r:
19776 case X86::VFMSUBSSr213r:
19777 case X86::VFNMADDPDr213r:
19778 case X86::VFNMADDPSr213r:
19779 case X86::VFNMADDSDr213r:
19780 case X86::VFNMADDSSr213r:
19781 case X86::VFNMSUBPDr213r:
19782 case X86::VFNMSUBPSr213r:
19783 case X86::VFNMSUBSDr213r:
19784 case X86::VFNMSUBSSr213r:
19785 case X86::VFMADDPDr213rY:
19786 case X86::VFMADDPSr213rY:
19787 case X86::VFMSUBPDr213rY:
19788 case X86::VFMSUBPSr213rY:
19789 case X86::VFNMADDPDr213rY:
19790 case X86::VFNMADDPSr213rY:
19791 case X86::VFNMSUBPDr213rY:
19792 case X86::VFNMSUBPSr213rY:
19793 return emitFMA3Instr(MI, BB);
19797 //===----------------------------------------------------------------------===//
19798 // X86 Optimization Hooks
19799 //===----------------------------------------------------------------------===//
19801 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19804 const SelectionDAG &DAG,
19805 unsigned Depth) const {
19806 unsigned BitWidth = KnownZero.getBitWidth();
19807 unsigned Opc = Op.getOpcode();
19808 assert((Opc >= ISD::BUILTIN_OP_END ||
19809 Opc == ISD::INTRINSIC_WO_CHAIN ||
19810 Opc == ISD::INTRINSIC_W_CHAIN ||
19811 Opc == ISD::INTRINSIC_VOID) &&
19812 "Should use MaskedValueIsZero if you don't know whether Op"
19813 " is a target node!");
19815 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19829 // These nodes' second result is a boolean.
19830 if (Op.getResNo() == 0)
19833 case X86ISD::SETCC:
19834 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19836 case ISD::INTRINSIC_WO_CHAIN: {
19837 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19838 unsigned NumLoBits = 0;
19841 case Intrinsic::x86_sse_movmsk_ps:
19842 case Intrinsic::x86_avx_movmsk_ps_256:
19843 case Intrinsic::x86_sse2_movmsk_pd:
19844 case Intrinsic::x86_avx_movmsk_pd_256:
19845 case Intrinsic::x86_mmx_pmovmskb:
19846 case Intrinsic::x86_sse2_pmovmskb_128:
19847 case Intrinsic::x86_avx2_pmovmskb: {
19848 // High bits of movmskp{s|d}, pmovmskb are known zero.
19850 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19851 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19852 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19853 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19854 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19855 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19856 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19857 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19859 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19868 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19870 const SelectionDAG &,
19871 unsigned Depth) const {
19872 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19873 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19874 return Op.getValueType().getScalarType().getSizeInBits();
19880 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19881 /// node is a GlobalAddress + offset.
19882 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19883 const GlobalValue* &GA,
19884 int64_t &Offset) const {
19885 if (N->getOpcode() == X86ISD::Wrapper) {
19886 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19887 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19888 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19892 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19895 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19896 /// same as extracting the high 128-bit part of 256-bit vector and then
19897 /// inserting the result into the low part of a new 256-bit vector
19898 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19899 EVT VT = SVOp->getValueType(0);
19900 unsigned NumElems = VT.getVectorNumElements();
19902 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19903 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19904 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19905 SVOp->getMaskElt(j) >= 0)
19911 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19912 /// same as extracting the low 128-bit part of 256-bit vector and then
19913 /// inserting the result into the high part of a new 256-bit vector
19914 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19915 EVT VT = SVOp->getValueType(0);
19916 unsigned NumElems = VT.getVectorNumElements();
19918 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19919 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19920 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19921 SVOp->getMaskElt(j) >= 0)
19927 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19928 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19929 TargetLowering::DAGCombinerInfo &DCI,
19930 const X86Subtarget* Subtarget) {
19932 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19933 SDValue V1 = SVOp->getOperand(0);
19934 SDValue V2 = SVOp->getOperand(1);
19935 EVT VT = SVOp->getValueType(0);
19936 unsigned NumElems = VT.getVectorNumElements();
19938 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19939 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19943 // V UNDEF BUILD_VECTOR UNDEF
19945 // CONCAT_VECTOR CONCAT_VECTOR
19948 // RESULT: V + zero extended
19950 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19951 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19952 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19955 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19958 // To match the shuffle mask, the first half of the mask should
19959 // be exactly the first vector, and all the rest a splat with the
19960 // first element of the second one.
19961 for (unsigned i = 0; i != NumElems/2; ++i)
19962 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19963 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19966 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19967 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19968 if (Ld->hasNUsesOfValue(1, 0)) {
19969 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19970 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19972 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19974 Ld->getPointerInfo(),
19975 Ld->getAlignment(),
19976 false/*isVolatile*/, true/*ReadMem*/,
19977 false/*WriteMem*/);
19979 // Make sure the newly-created LOAD is in the same position as Ld in
19980 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19981 // and update uses of Ld's output chain to use the TokenFactor.
19982 if (Ld->hasAnyUseOfValue(1)) {
19983 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19984 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19985 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19986 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19987 SDValue(ResNode.getNode(), 1));
19990 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19994 // Emit a zeroed vector and insert the desired subvector on its
19996 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19997 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19998 return DCI.CombineTo(N, InsV);
20001 //===--------------------------------------------------------------------===//
20002 // Combine some shuffles into subvector extracts and inserts:
20005 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20006 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20007 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20008 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20009 return DCI.CombineTo(N, InsV);
20012 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20013 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20014 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20015 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20016 return DCI.CombineTo(N, InsV);
20022 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20025 /// This is the leaf of the recursive combinine below. When we have found some
20026 /// chain of single-use x86 shuffle instructions and accumulated the combined
20027 /// shuffle mask represented by them, this will try to pattern match that mask
20028 /// into either a single instruction if there is a special purpose instruction
20029 /// for this operation, or into a PSHUFB instruction which is a fully general
20030 /// instruction but should only be used to replace chains over a certain depth.
20031 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20032 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20033 TargetLowering::DAGCombinerInfo &DCI,
20034 const X86Subtarget *Subtarget) {
20035 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20037 // Find the operand that enters the chain. Note that multiple uses are OK
20038 // here, we're not going to remove the operand we find.
20039 SDValue Input = Op.getOperand(0);
20040 while (Input.getOpcode() == ISD::BITCAST)
20041 Input = Input.getOperand(0);
20043 MVT VT = Input.getSimpleValueType();
20044 MVT RootVT = Root.getSimpleValueType();
20047 // Just remove no-op shuffle masks.
20048 if (Mask.size() == 1) {
20049 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20054 // Use the float domain if the operand type is a floating point type.
20055 bool FloatDomain = VT.isFloatingPoint();
20057 // For floating point shuffles, we don't have free copies in the shuffle
20058 // instructions or the ability to load as part of the instruction, so
20059 // canonicalize their shuffles to UNPCK or MOV variants.
20061 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20062 // vectors because it can have a load folded into it that UNPCK cannot. This
20063 // doesn't preclude something switching to the shorter encoding post-RA.
20065 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20066 bool Lo = Mask.equals(0, 0);
20069 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20070 // is no slower than UNPCKLPD but has the option to fold the input operand
20071 // into even an unaligned memory load.
20072 if (Lo && Subtarget->hasSSE3()) {
20073 Shuffle = X86ISD::MOVDDUP;
20074 ShuffleVT = MVT::v2f64;
20076 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20077 // than the UNPCK variants.
20078 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20079 ShuffleVT = MVT::v4f32;
20081 if (Depth == 1 && Root->getOpcode() == Shuffle)
20082 return false; // Nothing to do!
20083 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20084 DCI.AddToWorklist(Op.getNode());
20085 if (Shuffle == X86ISD::MOVDDUP)
20086 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20088 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20089 DCI.AddToWorklist(Op.getNode());
20090 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20094 if (Subtarget->hasSSE3() &&
20095 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20096 bool Lo = Mask.equals(0, 0, 2, 2);
20097 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20098 MVT ShuffleVT = MVT::v4f32;
20099 if (Depth == 1 && Root->getOpcode() == Shuffle)
20100 return false; // Nothing to do!
20101 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20102 DCI.AddToWorklist(Op.getNode());
20103 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20104 DCI.AddToWorklist(Op.getNode());
20105 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20109 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20110 bool Lo = Mask.equals(0, 0, 1, 1);
20111 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20112 MVT ShuffleVT = MVT::v4f32;
20113 if (Depth == 1 && Root->getOpcode() == Shuffle)
20114 return false; // Nothing to do!
20115 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20116 DCI.AddToWorklist(Op.getNode());
20117 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20118 DCI.AddToWorklist(Op.getNode());
20119 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20125 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20126 // variants as none of these have single-instruction variants that are
20127 // superior to the UNPCK formulation.
20128 if (!FloatDomain &&
20129 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20130 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20131 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20132 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20134 bool Lo = Mask[0] == 0;
20135 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20136 if (Depth == 1 && Root->getOpcode() == Shuffle)
20137 return false; // Nothing to do!
20139 switch (Mask.size()) {
20141 ShuffleVT = MVT::v8i16;
20144 ShuffleVT = MVT::v16i8;
20147 llvm_unreachable("Impossible mask size!");
20149 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20150 DCI.AddToWorklist(Op.getNode());
20151 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20152 DCI.AddToWorklist(Op.getNode());
20153 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20158 // Don't try to re-form single instruction chains under any circumstances now
20159 // that we've done encoding canonicalization for them.
20163 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20164 // can replace them with a single PSHUFB instruction profitably. Intel's
20165 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20166 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20167 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20168 SmallVector<SDValue, 16> PSHUFBMask;
20169 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20170 int Ratio = 16 / Mask.size();
20171 for (unsigned i = 0; i < 16; ++i) {
20172 if (Mask[i / Ratio] == SM_SentinelUndef) {
20173 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20176 int M = Mask[i / Ratio] != SM_SentinelZero
20177 ? Ratio * Mask[i / Ratio] + i % Ratio
20179 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20181 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20182 DCI.AddToWorklist(Op.getNode());
20183 SDValue PSHUFBMaskOp =
20184 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20185 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20186 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20187 DCI.AddToWorklist(Op.getNode());
20188 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20193 // Failed to find any combines.
20197 /// \brief Fully generic combining of x86 shuffle instructions.
20199 /// This should be the last combine run over the x86 shuffle instructions. Once
20200 /// they have been fully optimized, this will recursively consider all chains
20201 /// of single-use shuffle instructions, build a generic model of the cumulative
20202 /// shuffle operation, and check for simpler instructions which implement this
20203 /// operation. We use this primarily for two purposes:
20205 /// 1) Collapse generic shuffles to specialized single instructions when
20206 /// equivalent. In most cases, this is just an encoding size win, but
20207 /// sometimes we will collapse multiple generic shuffles into a single
20208 /// special-purpose shuffle.
20209 /// 2) Look for sequences of shuffle instructions with 3 or more total
20210 /// instructions, and replace them with the slightly more expensive SSSE3
20211 /// PSHUFB instruction if available. We do this as the last combining step
20212 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20213 /// a suitable short sequence of other instructions. The PHUFB will either
20214 /// use a register or have to read from memory and so is slightly (but only
20215 /// slightly) more expensive than the other shuffle instructions.
20217 /// Because this is inherently a quadratic operation (for each shuffle in
20218 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20219 /// This should never be an issue in practice as the shuffle lowering doesn't
20220 /// produce sequences of more than 8 instructions.
20222 /// FIXME: We will currently miss some cases where the redundant shuffling
20223 /// would simplify under the threshold for PSHUFB formation because of
20224 /// combine-ordering. To fix this, we should do the redundant instruction
20225 /// combining in this recursive walk.
20226 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20227 ArrayRef<int> RootMask,
20228 int Depth, bool HasPSHUFB,
20230 TargetLowering::DAGCombinerInfo &DCI,
20231 const X86Subtarget *Subtarget) {
20232 // Bound the depth of our recursive combine because this is ultimately
20233 // quadratic in nature.
20237 // Directly rip through bitcasts to find the underlying operand.
20238 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20239 Op = Op.getOperand(0);
20241 MVT VT = Op.getSimpleValueType();
20242 if (!VT.isVector())
20243 return false; // Bail if we hit a non-vector.
20244 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20245 // version should be added.
20246 if (VT.getSizeInBits() != 128)
20249 assert(Root.getSimpleValueType().isVector() &&
20250 "Shuffles operate on vector types!");
20251 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20252 "Can only combine shuffles of the same vector register size.");
20254 if (!isTargetShuffle(Op.getOpcode()))
20256 SmallVector<int, 16> OpMask;
20258 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20259 // We only can combine unary shuffles which we can decode the mask for.
20260 if (!HaveMask || !IsUnary)
20263 assert(VT.getVectorNumElements() == OpMask.size() &&
20264 "Different mask size from vector size!");
20265 assert(((RootMask.size() > OpMask.size() &&
20266 RootMask.size() % OpMask.size() == 0) ||
20267 (OpMask.size() > RootMask.size() &&
20268 OpMask.size() % RootMask.size() == 0) ||
20269 OpMask.size() == RootMask.size()) &&
20270 "The smaller number of elements must divide the larger.");
20271 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20272 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20273 assert(((RootRatio == 1 && OpRatio == 1) ||
20274 (RootRatio == 1) != (OpRatio == 1)) &&
20275 "Must not have a ratio for both incoming and op masks!");
20277 SmallVector<int, 16> Mask;
20278 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20280 // Merge this shuffle operation's mask into our accumulated mask. Note that
20281 // this shuffle's mask will be the first applied to the input, followed by the
20282 // root mask to get us all the way to the root value arrangement. The reason
20283 // for this order is that we are recursing up the operation chain.
20284 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20285 int RootIdx = i / RootRatio;
20286 if (RootMask[RootIdx] < 0) {
20287 // This is a zero or undef lane, we're done.
20288 Mask.push_back(RootMask[RootIdx]);
20292 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20293 int OpIdx = RootMaskedIdx / OpRatio;
20294 if (OpMask[OpIdx] < 0) {
20295 // The incoming lanes are zero or undef, it doesn't matter which ones we
20297 Mask.push_back(OpMask[OpIdx]);
20301 // Ok, we have non-zero lanes, map them through.
20302 Mask.push_back(OpMask[OpIdx] * OpRatio +
20303 RootMaskedIdx % OpRatio);
20306 // See if we can recurse into the operand to combine more things.
20307 switch (Op.getOpcode()) {
20308 case X86ISD::PSHUFB:
20310 case X86ISD::PSHUFD:
20311 case X86ISD::PSHUFHW:
20312 case X86ISD::PSHUFLW:
20313 if (Op.getOperand(0).hasOneUse() &&
20314 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20315 HasPSHUFB, DAG, DCI, Subtarget))
20319 case X86ISD::UNPCKL:
20320 case X86ISD::UNPCKH:
20321 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20322 // We can't check for single use, we have to check that this shuffle is the only user.
20323 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20324 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20325 HasPSHUFB, DAG, DCI, Subtarget))
20330 // Minor canonicalization of the accumulated shuffle mask to make it easier
20331 // to match below. All this does is detect masks with squential pairs of
20332 // elements, and shrink them to the half-width mask. It does this in a loop
20333 // so it will reduce the size of the mask to the minimal width mask which
20334 // performs an equivalent shuffle.
20335 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20336 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20337 Mask[i] = Mask[2 * i] / 2;
20338 Mask.resize(Mask.size() / 2);
20341 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20345 /// \brief Get the PSHUF-style mask from PSHUF node.
20347 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20348 /// PSHUF-style masks that can be reused with such instructions.
20349 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20350 SmallVector<int, 4> Mask;
20352 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20356 switch (N.getOpcode()) {
20357 case X86ISD::PSHUFD:
20359 case X86ISD::PSHUFLW:
20362 case X86ISD::PSHUFHW:
20363 Mask.erase(Mask.begin(), Mask.begin() + 4);
20364 for (int &M : Mask)
20368 llvm_unreachable("No valid shuffle instruction found!");
20372 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20374 /// We walk up the chain and look for a combinable shuffle, skipping over
20375 /// shuffles that we could hoist this shuffle's transformation past without
20376 /// altering anything.
20378 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20380 TargetLowering::DAGCombinerInfo &DCI) {
20381 assert(N.getOpcode() == X86ISD::PSHUFD &&
20382 "Called with something other than an x86 128-bit half shuffle!");
20385 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20386 // of the shuffles in the chain so that we can form a fresh chain to replace
20388 SmallVector<SDValue, 8> Chain;
20389 SDValue V = N.getOperand(0);
20390 for (; V.hasOneUse(); V = V.getOperand(0)) {
20391 switch (V.getOpcode()) {
20393 return SDValue(); // Nothing combined!
20396 // Skip bitcasts as we always know the type for the target specific
20400 case X86ISD::PSHUFD:
20401 // Found another dword shuffle.
20404 case X86ISD::PSHUFLW:
20405 // Check that the low words (being shuffled) are the identity in the
20406 // dword shuffle, and the high words are self-contained.
20407 if (Mask[0] != 0 || Mask[1] != 1 ||
20408 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20411 Chain.push_back(V);
20414 case X86ISD::PSHUFHW:
20415 // Check that the high words (being shuffled) are the identity in the
20416 // dword shuffle, and the low words are self-contained.
20417 if (Mask[2] != 2 || Mask[3] != 3 ||
20418 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20421 Chain.push_back(V);
20424 case X86ISD::UNPCKL:
20425 case X86ISD::UNPCKH:
20426 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20427 // shuffle into a preceding word shuffle.
20428 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20431 // Search for a half-shuffle which we can combine with.
20432 unsigned CombineOp =
20433 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20434 if (V.getOperand(0) != V.getOperand(1) ||
20435 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20437 Chain.push_back(V);
20438 V = V.getOperand(0);
20440 switch (V.getOpcode()) {
20442 return SDValue(); // Nothing to combine.
20444 case X86ISD::PSHUFLW:
20445 case X86ISD::PSHUFHW:
20446 if (V.getOpcode() == CombineOp)
20449 Chain.push_back(V);
20453 V = V.getOperand(0);
20457 } while (V.hasOneUse());
20460 // Break out of the loop if we break out of the switch.
20464 if (!V.hasOneUse())
20465 // We fell out of the loop without finding a viable combining instruction.
20468 // Merge this node's mask and our incoming mask.
20469 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20470 for (int &M : Mask)
20472 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20473 getV4X86ShuffleImm8ForMask(Mask, DAG));
20475 // Rebuild the chain around this new shuffle.
20476 while (!Chain.empty()) {
20477 SDValue W = Chain.pop_back_val();
20479 if (V.getValueType() != W.getOperand(0).getValueType())
20480 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20482 switch (W.getOpcode()) {
20484 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20486 case X86ISD::UNPCKL:
20487 case X86ISD::UNPCKH:
20488 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20491 case X86ISD::PSHUFD:
20492 case X86ISD::PSHUFLW:
20493 case X86ISD::PSHUFHW:
20494 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20498 if (V.getValueType() != N.getValueType())
20499 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20501 // Return the new chain to replace N.
20505 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20507 /// We walk up the chain, skipping shuffles of the other half and looking
20508 /// through shuffles which switch halves trying to find a shuffle of the same
20509 /// pair of dwords.
20510 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20512 TargetLowering::DAGCombinerInfo &DCI) {
20514 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20515 "Called with something other than an x86 128-bit half shuffle!");
20517 unsigned CombineOpcode = N.getOpcode();
20519 // Walk up a single-use chain looking for a combinable shuffle.
20520 SDValue V = N.getOperand(0);
20521 for (; V.hasOneUse(); V = V.getOperand(0)) {
20522 switch (V.getOpcode()) {
20524 return false; // Nothing combined!
20527 // Skip bitcasts as we always know the type for the target specific
20531 case X86ISD::PSHUFLW:
20532 case X86ISD::PSHUFHW:
20533 if (V.getOpcode() == CombineOpcode)
20536 // Other-half shuffles are no-ops.
20539 // Break out of the loop if we break out of the switch.
20543 if (!V.hasOneUse())
20544 // We fell out of the loop without finding a viable combining instruction.
20547 // Combine away the bottom node as its shuffle will be accumulated into
20548 // a preceding shuffle.
20549 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20551 // Record the old value.
20554 // Merge this node's mask and our incoming mask (adjusted to account for all
20555 // the pshufd instructions encountered).
20556 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20557 for (int &M : Mask)
20559 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20560 getV4X86ShuffleImm8ForMask(Mask, DAG));
20562 // Check that the shuffles didn't cancel each other out. If not, we need to
20563 // combine to the new one.
20565 // Replace the combinable shuffle with the combined one, updating all users
20566 // so that we re-evaluate the chain here.
20567 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20572 /// \brief Try to combine x86 target specific shuffles.
20573 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20574 TargetLowering::DAGCombinerInfo &DCI,
20575 const X86Subtarget *Subtarget) {
20577 MVT VT = N.getSimpleValueType();
20578 SmallVector<int, 4> Mask;
20580 switch (N.getOpcode()) {
20581 case X86ISD::PSHUFD:
20582 case X86ISD::PSHUFLW:
20583 case X86ISD::PSHUFHW:
20584 Mask = getPSHUFShuffleMask(N);
20585 assert(Mask.size() == 4);
20591 // Nuke no-op shuffles that show up after combining.
20592 if (isNoopShuffleMask(Mask))
20593 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20595 // Look for simplifications involving one or two shuffle instructions.
20596 SDValue V = N.getOperand(0);
20597 switch (N.getOpcode()) {
20600 case X86ISD::PSHUFLW:
20601 case X86ISD::PSHUFHW:
20602 assert(VT == MVT::v8i16);
20605 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20606 return SDValue(); // We combined away this shuffle, so we're done.
20608 // See if this reduces to a PSHUFD which is no more expensive and can
20609 // combine with more operations.
20610 if (canWidenShuffleElements(Mask)) {
20611 int DMask[] = {-1, -1, -1, -1};
20612 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20613 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20614 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20615 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20616 DCI.AddToWorklist(V.getNode());
20617 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20618 getV4X86ShuffleImm8ForMask(DMask, DAG));
20619 DCI.AddToWorklist(V.getNode());
20620 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20623 // Look for shuffle patterns which can be implemented as a single unpack.
20624 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20625 // only works when we have a PSHUFD followed by two half-shuffles.
20626 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20627 (V.getOpcode() == X86ISD::PSHUFLW ||
20628 V.getOpcode() == X86ISD::PSHUFHW) &&
20629 V.getOpcode() != N.getOpcode() &&
20631 SDValue D = V.getOperand(0);
20632 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20633 D = D.getOperand(0);
20634 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20635 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20636 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20637 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20638 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20640 for (int i = 0; i < 4; ++i) {
20641 WordMask[i + NOffset] = Mask[i] + NOffset;
20642 WordMask[i + VOffset] = VMask[i] + VOffset;
20644 // Map the word mask through the DWord mask.
20646 for (int i = 0; i < 8; ++i)
20647 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20648 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20649 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20650 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20651 std::begin(UnpackLoMask)) ||
20652 std::equal(std::begin(MappedMask), std::end(MappedMask),
20653 std::begin(UnpackHiMask))) {
20654 // We can replace all three shuffles with an unpack.
20655 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20656 DCI.AddToWorklist(V.getNode());
20657 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20659 DL, MVT::v8i16, V, V);
20666 case X86ISD::PSHUFD:
20667 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20676 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20678 /// We combine this directly on the abstract vector shuffle nodes so it is
20679 /// easier to generically match. We also insert dummy vector shuffle nodes for
20680 /// the operands which explicitly discard the lanes which are unused by this
20681 /// operation to try to flow through the rest of the combiner the fact that
20682 /// they're unused.
20683 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20685 EVT VT = N->getValueType(0);
20687 // We only handle target-independent shuffles.
20688 // FIXME: It would be easy and harmless to use the target shuffle mask
20689 // extraction tool to support more.
20690 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20693 auto *SVN = cast<ShuffleVectorSDNode>(N);
20694 ArrayRef<int> Mask = SVN->getMask();
20695 SDValue V1 = N->getOperand(0);
20696 SDValue V2 = N->getOperand(1);
20698 // We require the first shuffle operand to be the SUB node, and the second to
20699 // be the ADD node.
20700 // FIXME: We should support the commuted patterns.
20701 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20704 // If there are other uses of these operations we can't fold them.
20705 if (!V1->hasOneUse() || !V2->hasOneUse())
20708 // Ensure that both operations have the same operands. Note that we can
20709 // commute the FADD operands.
20710 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20711 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20712 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20715 // We're looking for blends between FADD and FSUB nodes. We insist on these
20716 // nodes being lined up in a specific expected pattern.
20717 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20718 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20719 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20722 // Only specific types are legal at this point, assert so we notice if and
20723 // when these change.
20724 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20725 VT == MVT::v4f64) &&
20726 "Unknown vector type encountered!");
20728 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20731 /// PerformShuffleCombine - Performs several different shuffle combines.
20732 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20733 TargetLowering::DAGCombinerInfo &DCI,
20734 const X86Subtarget *Subtarget) {
20736 SDValue N0 = N->getOperand(0);
20737 SDValue N1 = N->getOperand(1);
20738 EVT VT = N->getValueType(0);
20740 // Don't create instructions with illegal types after legalize types has run.
20741 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20742 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20745 // If we have legalized the vector types, look for blends of FADD and FSUB
20746 // nodes that we can fuse into an ADDSUB node.
20747 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20748 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20751 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20752 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20753 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20754 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20756 // During Type Legalization, when promoting illegal vector types,
20757 // the backend might introduce new shuffle dag nodes and bitcasts.
20759 // This code performs the following transformation:
20760 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20761 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20763 // We do this only if both the bitcast and the BINOP dag nodes have
20764 // one use. Also, perform this transformation only if the new binary
20765 // operation is legal. This is to avoid introducing dag nodes that
20766 // potentially need to be further expanded (or custom lowered) into a
20767 // less optimal sequence of dag nodes.
20768 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20769 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20770 N0.getOpcode() == ISD::BITCAST) {
20771 SDValue BC0 = N0.getOperand(0);
20772 EVT SVT = BC0.getValueType();
20773 unsigned Opcode = BC0.getOpcode();
20774 unsigned NumElts = VT.getVectorNumElements();
20776 if (BC0.hasOneUse() && SVT.isVector() &&
20777 SVT.getVectorNumElements() * 2 == NumElts &&
20778 TLI.isOperationLegal(Opcode, VT)) {
20779 bool CanFold = false;
20791 unsigned SVTNumElts = SVT.getVectorNumElements();
20792 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20793 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20794 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20795 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20796 CanFold = SVOp->getMaskElt(i) < 0;
20799 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20800 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20801 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20802 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20807 // Only handle 128 wide vector from here on.
20808 if (!VT.is128BitVector())
20811 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20812 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20813 // consecutive, non-overlapping, and in the right order.
20814 SmallVector<SDValue, 16> Elts;
20815 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20816 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20818 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20822 if (isTargetShuffle(N->getOpcode())) {
20824 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20825 if (Shuffle.getNode())
20828 // Try recursively combining arbitrary sequences of x86 shuffle
20829 // instructions into higher-order shuffles. We do this after combining
20830 // specific PSHUF instruction sequences into their minimal form so that we
20831 // can evaluate how many specialized shuffle instructions are involved in
20832 // a particular chain.
20833 SmallVector<int, 1> NonceMask; // Just a placeholder.
20834 NonceMask.push_back(0);
20835 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20836 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20838 return SDValue(); // This routine will use CombineTo to replace N.
20844 /// PerformTruncateCombine - Converts truncate operation to
20845 /// a sequence of vector shuffle operations.
20846 /// It is possible when we truncate 256-bit vector to 128-bit vector
20847 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20848 TargetLowering::DAGCombinerInfo &DCI,
20849 const X86Subtarget *Subtarget) {
20853 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20854 /// specific shuffle of a load can be folded into a single element load.
20855 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20856 /// shuffles have been customed lowered so we need to handle those here.
20857 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20858 TargetLowering::DAGCombinerInfo &DCI) {
20859 if (DCI.isBeforeLegalizeOps())
20862 SDValue InVec = N->getOperand(0);
20863 SDValue EltNo = N->getOperand(1);
20865 if (!isa<ConstantSDNode>(EltNo))
20868 EVT VT = InVec.getValueType();
20870 if (InVec.getOpcode() == ISD::BITCAST) {
20871 // Don't duplicate a load with other uses.
20872 if (!InVec.hasOneUse())
20874 EVT BCVT = InVec.getOperand(0).getValueType();
20875 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20877 InVec = InVec.getOperand(0);
20880 if (!isTargetShuffle(InVec.getOpcode()))
20883 // Don't duplicate a load with other uses.
20884 if (!InVec.hasOneUse())
20887 SmallVector<int, 16> ShuffleMask;
20889 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20893 // Select the input vector, guarding against out of range extract vector.
20894 unsigned NumElems = VT.getVectorNumElements();
20895 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20896 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20897 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20898 : InVec.getOperand(1);
20900 // If inputs to shuffle are the same for both ops, then allow 2 uses
20901 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20903 if (LdNode.getOpcode() == ISD::BITCAST) {
20904 // Don't duplicate a load with other uses.
20905 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20908 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20909 LdNode = LdNode.getOperand(0);
20912 if (!ISD::isNormalLoad(LdNode.getNode()))
20915 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20917 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20920 EVT EltVT = N->getValueType(0);
20921 // If there's a bitcast before the shuffle, check if the load type and
20922 // alignment is valid.
20923 unsigned Align = LN0->getAlignment();
20924 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20925 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20926 EltVT.getTypeForEVT(*DAG.getContext()));
20928 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20931 // All checks match so transform back to vector_shuffle so that DAG combiner
20932 // can finish the job
20935 // Create shuffle node taking into account the case that its a unary shuffle
20936 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20937 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20938 InVec.getOperand(0), Shuffle,
20940 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20941 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20945 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20946 /// generation and convert it from being a bunch of shuffles and extracts
20947 /// to a simple store and scalar loads to extract the elements.
20948 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20949 TargetLowering::DAGCombinerInfo &DCI) {
20950 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20951 if (NewOp.getNode())
20954 SDValue InputVector = N->getOperand(0);
20956 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20957 // from mmx to v2i32 has a single usage.
20958 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20959 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20960 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20961 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20962 N->getValueType(0),
20963 InputVector.getNode()->getOperand(0));
20965 // Only operate on vectors of 4 elements, where the alternative shuffling
20966 // gets to be more expensive.
20967 if (InputVector.getValueType() != MVT::v4i32)
20970 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20971 // single use which is a sign-extend or zero-extend, and all elements are
20973 SmallVector<SDNode *, 4> Uses;
20974 unsigned ExtractedElements = 0;
20975 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20976 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20977 if (UI.getUse().getResNo() != InputVector.getResNo())
20980 SDNode *Extract = *UI;
20981 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20984 if (Extract->getValueType(0) != MVT::i32)
20986 if (!Extract->hasOneUse())
20988 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20989 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20991 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20994 // Record which element was extracted.
20995 ExtractedElements |=
20996 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20998 Uses.push_back(Extract);
21001 // If not all the elements were used, this may not be worthwhile.
21002 if (ExtractedElements != 15)
21005 // Ok, we've now decided to do the transformation.
21006 SDLoc dl(InputVector);
21008 // Store the value to a temporary stack slot.
21009 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21010 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21011 MachinePointerInfo(), false, false, 0);
21013 // Replace each use (extract) with a load of the appropriate element.
21014 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21015 UE = Uses.end(); UI != UE; ++UI) {
21016 SDNode *Extract = *UI;
21018 // cOMpute the element's address.
21019 SDValue Idx = Extract->getOperand(1);
21021 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21022 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21023 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21024 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21026 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21027 StackPtr, OffsetVal);
21029 // Load the scalar.
21030 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21031 ScalarAddr, MachinePointerInfo(),
21032 false, false, false, 0);
21034 // Replace the exact with the load.
21035 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21038 // The replacement was made in place; don't return anything.
21042 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21043 static std::pair<unsigned, bool>
21044 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21045 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21046 if (!VT.isVector())
21047 return std::make_pair(0, false);
21049 bool NeedSplit = false;
21050 switch (VT.getSimpleVT().SimpleTy) {
21051 default: return std::make_pair(0, false);
21055 if (!Subtarget->hasAVX2())
21057 if (!Subtarget->hasAVX())
21058 return std::make_pair(0, false);
21063 if (!Subtarget->hasSSE2())
21064 return std::make_pair(0, false);
21067 // SSE2 has only a small subset of the operations.
21068 bool hasUnsigned = Subtarget->hasSSE41() ||
21069 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21070 bool hasSigned = Subtarget->hasSSE41() ||
21071 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21073 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21076 // Check for x CC y ? x : y.
21077 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21078 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21083 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21086 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21089 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21092 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21094 // Check for x CC y ? y : x -- a min/max with reversed arms.
21095 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21096 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21101 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21104 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21107 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21110 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21114 return std::make_pair(Opc, NeedSplit);
21118 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21119 const X86Subtarget *Subtarget) {
21121 SDValue Cond = N->getOperand(0);
21122 SDValue LHS = N->getOperand(1);
21123 SDValue RHS = N->getOperand(2);
21125 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21126 SDValue CondSrc = Cond->getOperand(0);
21127 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21128 Cond = CondSrc->getOperand(0);
21131 MVT VT = N->getSimpleValueType(0);
21132 MVT EltVT = VT.getVectorElementType();
21133 unsigned NumElems = VT.getVectorNumElements();
21134 // There is no blend with immediate in AVX-512.
21135 if (VT.is512BitVector())
21138 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21140 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21143 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21146 // A vselect where all conditions and data are constants can be optimized into
21147 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21148 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21149 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21152 unsigned MaskValue = 0;
21153 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21156 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21157 for (unsigned i = 0; i < NumElems; ++i) {
21158 // Be sure we emit undef where we can.
21159 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21160 ShuffleMask[i] = -1;
21162 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21165 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21168 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21170 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21171 TargetLowering::DAGCombinerInfo &DCI,
21172 const X86Subtarget *Subtarget) {
21174 SDValue Cond = N->getOperand(0);
21175 // Get the LHS/RHS of the select.
21176 SDValue LHS = N->getOperand(1);
21177 SDValue RHS = N->getOperand(2);
21178 EVT VT = LHS.getValueType();
21179 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21181 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21182 // instructions match the semantics of the common C idiom x<y?x:y but not
21183 // x<=y?x:y, because of how they handle negative zero (which can be
21184 // ignored in unsafe-math mode).
21185 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21186 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21187 (Subtarget->hasSSE2() ||
21188 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21189 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21191 unsigned Opcode = 0;
21192 // Check for x CC y ? x : y.
21193 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21194 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21198 // Converting this to a min would handle NaNs incorrectly, and swapping
21199 // the operands would cause it to handle comparisons between positive
21200 // and negative zero incorrectly.
21201 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21202 if (!DAG.getTarget().Options.UnsafeFPMath &&
21203 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21205 std::swap(LHS, RHS);
21207 Opcode = X86ISD::FMIN;
21210 // Converting this to a min would handle comparisons between positive
21211 // and negative zero incorrectly.
21212 if (!DAG.getTarget().Options.UnsafeFPMath &&
21213 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21215 Opcode = X86ISD::FMIN;
21218 // Converting this to a min would handle both negative zeros and NaNs
21219 // incorrectly, but we can swap the operands to fix both.
21220 std::swap(LHS, RHS);
21224 Opcode = X86ISD::FMIN;
21228 // Converting this to a max would handle comparisons between positive
21229 // and negative zero incorrectly.
21230 if (!DAG.getTarget().Options.UnsafeFPMath &&
21231 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21233 Opcode = X86ISD::FMAX;
21236 // Converting this to a max would handle NaNs incorrectly, and swapping
21237 // the operands would cause it to handle comparisons between positive
21238 // and negative zero incorrectly.
21239 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21240 if (!DAG.getTarget().Options.UnsafeFPMath &&
21241 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21243 std::swap(LHS, RHS);
21245 Opcode = X86ISD::FMAX;
21248 // Converting this to a max would handle both negative zeros and NaNs
21249 // incorrectly, but we can swap the operands to fix both.
21250 std::swap(LHS, RHS);
21254 Opcode = X86ISD::FMAX;
21257 // Check for x CC y ? y : x -- a min/max with reversed arms.
21258 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21259 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21263 // Converting this to a min would handle comparisons between positive
21264 // and negative zero incorrectly, and swapping the operands would
21265 // cause it to handle NaNs incorrectly.
21266 if (!DAG.getTarget().Options.UnsafeFPMath &&
21267 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21268 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21270 std::swap(LHS, RHS);
21272 Opcode = X86ISD::FMIN;
21275 // Converting this to a min would handle NaNs incorrectly.
21276 if (!DAG.getTarget().Options.UnsafeFPMath &&
21277 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21279 Opcode = X86ISD::FMIN;
21282 // Converting this to a min would handle both negative zeros and NaNs
21283 // incorrectly, but we can swap the operands to fix both.
21284 std::swap(LHS, RHS);
21288 Opcode = X86ISD::FMIN;
21292 // Converting this to a max would handle NaNs incorrectly.
21293 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21295 Opcode = X86ISD::FMAX;
21298 // Converting this to a max would handle comparisons between positive
21299 // and negative zero incorrectly, and swapping the operands would
21300 // cause it to handle NaNs incorrectly.
21301 if (!DAG.getTarget().Options.UnsafeFPMath &&
21302 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21303 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21305 std::swap(LHS, RHS);
21307 Opcode = X86ISD::FMAX;
21310 // Converting this to a max would handle both negative zeros and NaNs
21311 // incorrectly, but we can swap the operands to fix both.
21312 std::swap(LHS, RHS);
21316 Opcode = X86ISD::FMAX;
21322 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21325 EVT CondVT = Cond.getValueType();
21326 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21327 CondVT.getVectorElementType() == MVT::i1) {
21328 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21329 // lowering on KNL. In this case we convert it to
21330 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21331 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21332 // Since SKX these selects have a proper lowering.
21333 EVT OpVT = LHS.getValueType();
21334 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21335 (OpVT.getVectorElementType() == MVT::i8 ||
21336 OpVT.getVectorElementType() == MVT::i16) &&
21337 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21338 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21339 DCI.AddToWorklist(Cond.getNode());
21340 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21343 // If this is a select between two integer constants, try to do some
21345 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21346 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21347 // Don't do this for crazy integer types.
21348 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21349 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21350 // so that TrueC (the true value) is larger than FalseC.
21351 bool NeedsCondInvert = false;
21353 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21354 // Efficiently invertible.
21355 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21356 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21357 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21358 NeedsCondInvert = true;
21359 std::swap(TrueC, FalseC);
21362 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21363 if (FalseC->getAPIntValue() == 0 &&
21364 TrueC->getAPIntValue().isPowerOf2()) {
21365 if (NeedsCondInvert) // Invert the condition if needed.
21366 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21367 DAG.getConstant(1, Cond.getValueType()));
21369 // Zero extend the condition if needed.
21370 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21372 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21373 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21374 DAG.getConstant(ShAmt, MVT::i8));
21377 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21378 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21379 if (NeedsCondInvert) // Invert the condition if needed.
21380 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21381 DAG.getConstant(1, Cond.getValueType()));
21383 // Zero extend the condition if needed.
21384 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21385 FalseC->getValueType(0), Cond);
21386 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21387 SDValue(FalseC, 0));
21390 // Optimize cases that will turn into an LEA instruction. This requires
21391 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21392 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21393 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21394 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21396 bool isFastMultiplier = false;
21398 switch ((unsigned char)Diff) {
21400 case 1: // result = add base, cond
21401 case 2: // result = lea base( , cond*2)
21402 case 3: // result = lea base(cond, cond*2)
21403 case 4: // result = lea base( , cond*4)
21404 case 5: // result = lea base(cond, cond*4)
21405 case 8: // result = lea base( , cond*8)
21406 case 9: // result = lea base(cond, cond*8)
21407 isFastMultiplier = true;
21412 if (isFastMultiplier) {
21413 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21414 if (NeedsCondInvert) // Invert the condition if needed.
21415 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21416 DAG.getConstant(1, Cond.getValueType()));
21418 // Zero extend the condition if needed.
21419 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21421 // Scale the condition by the difference.
21423 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21424 DAG.getConstant(Diff, Cond.getValueType()));
21426 // Add the base if non-zero.
21427 if (FalseC->getAPIntValue() != 0)
21428 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21429 SDValue(FalseC, 0));
21436 // Canonicalize max and min:
21437 // (x > y) ? x : y -> (x >= y) ? x : y
21438 // (x < y) ? x : y -> (x <= y) ? x : y
21439 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21440 // the need for an extra compare
21441 // against zero. e.g.
21442 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21444 // testl %edi, %edi
21446 // cmovgl %edi, %eax
21450 // cmovsl %eax, %edi
21451 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21452 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21453 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21454 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21459 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21460 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21461 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21462 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21467 // Early exit check
21468 if (!TLI.isTypeLegal(VT))
21471 // Match VSELECTs into subs with unsigned saturation.
21472 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21473 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21474 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21475 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21476 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21478 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21479 // left side invert the predicate to simplify logic below.
21481 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21483 CC = ISD::getSetCCInverse(CC, true);
21484 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21488 if (Other.getNode() && Other->getNumOperands() == 2 &&
21489 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21490 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21491 SDValue CondRHS = Cond->getOperand(1);
21493 // Look for a general sub with unsigned saturation first.
21494 // x >= y ? x-y : 0 --> subus x, y
21495 // x > y ? x-y : 0 --> subus x, y
21496 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21497 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21498 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21500 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21501 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21502 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21503 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21504 // If the RHS is a constant we have to reverse the const
21505 // canonicalization.
21506 // x > C-1 ? x+-C : 0 --> subus x, C
21507 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21508 CondRHSConst->getAPIntValue() ==
21509 (-OpRHSConst->getAPIntValue() - 1))
21510 return DAG.getNode(
21511 X86ISD::SUBUS, DL, VT, OpLHS,
21512 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21514 // Another special case: If C was a sign bit, the sub has been
21515 // canonicalized into a xor.
21516 // FIXME: Would it be better to use computeKnownBits to determine
21517 // whether it's safe to decanonicalize the xor?
21518 // x s< 0 ? x^C : 0 --> subus x, C
21519 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21520 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21521 OpRHSConst->getAPIntValue().isSignBit())
21522 // Note that we have to rebuild the RHS constant here to ensure we
21523 // don't rely on particular values of undef lanes.
21524 return DAG.getNode(
21525 X86ISD::SUBUS, DL, VT, OpLHS,
21526 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21531 // Try to match a min/max vector operation.
21532 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21533 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21534 unsigned Opc = ret.first;
21535 bool NeedSplit = ret.second;
21537 if (Opc && NeedSplit) {
21538 unsigned NumElems = VT.getVectorNumElements();
21539 // Extract the LHS vectors
21540 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21541 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21543 // Extract the RHS vectors
21544 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21545 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21547 // Create min/max for each subvector
21548 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21549 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21551 // Merge the result
21552 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21554 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21557 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21558 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21559 // Check if SETCC has already been promoted
21560 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21561 // Check that condition value type matches vselect operand type
21564 assert(Cond.getValueType().isVector() &&
21565 "vector select expects a vector selector!");
21567 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21568 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21570 if (!TValIsAllOnes && !FValIsAllZeros) {
21571 // Try invert the condition if true value is not all 1s and false value
21573 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21574 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21576 if (TValIsAllZeros || FValIsAllOnes) {
21577 SDValue CC = Cond.getOperand(2);
21578 ISD::CondCode NewCC =
21579 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21580 Cond.getOperand(0).getValueType().isInteger());
21581 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21582 std::swap(LHS, RHS);
21583 TValIsAllOnes = FValIsAllOnes;
21584 FValIsAllZeros = TValIsAllZeros;
21588 if (TValIsAllOnes || FValIsAllZeros) {
21591 if (TValIsAllOnes && FValIsAllZeros)
21593 else if (TValIsAllOnes)
21594 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21595 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21596 else if (FValIsAllZeros)
21597 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21598 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21600 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21604 // Try to fold this VSELECT into a MOVSS/MOVSD
21605 if (N->getOpcode() == ISD::VSELECT &&
21606 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21607 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21608 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21609 bool CanFold = false;
21610 unsigned NumElems = Cond.getNumOperands();
21614 if (isZero(Cond.getOperand(0))) {
21617 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21618 // fold (vselect <0,-1> -> (movsd A, B)
21619 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21620 CanFold = isAllOnes(Cond.getOperand(i));
21621 } else if (isAllOnes(Cond.getOperand(0))) {
21625 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21626 // fold (vselect <-1,0> -> (movsd B, A)
21627 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21628 CanFold = isZero(Cond.getOperand(i));
21632 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21633 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21634 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21637 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21638 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21639 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21640 // (v2i64 (bitcast B)))))
21642 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21643 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21644 // (v2f64 (bitcast B)))))
21646 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21647 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21648 // (v2i64 (bitcast A)))))
21650 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21651 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21652 // (v2f64 (bitcast A)))))
21654 CanFold = (isZero(Cond.getOperand(0)) &&
21655 isZero(Cond.getOperand(1)) &&
21656 isAllOnes(Cond.getOperand(2)) &&
21657 isAllOnes(Cond.getOperand(3)));
21659 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21660 isAllOnes(Cond.getOperand(1)) &&
21661 isZero(Cond.getOperand(2)) &&
21662 isZero(Cond.getOperand(3))) {
21664 std::swap(LHS, RHS);
21668 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21669 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21670 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21671 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21673 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21679 // If we know that this node is legal then we know that it is going to be
21680 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21681 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21682 // to simplify previous instructions.
21683 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21684 !DCI.isBeforeLegalize() &&
21685 // We explicitly check against v8i16 and v16i16 because, although
21686 // they're marked as Custom, they might only be legal when Cond is a
21687 // build_vector of constants. This will be taken care in a later
21689 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21690 VT != MVT::v8i16)) {
21691 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21693 // Don't optimize vector selects that map to mask-registers.
21697 // Check all uses of that condition operand to check whether it will be
21698 // consumed by non-BLEND instructions, which may depend on all bits are set
21700 for (SDNode::use_iterator I = Cond->use_begin(),
21701 E = Cond->use_end(); I != E; ++I)
21702 if (I->getOpcode() != ISD::VSELECT)
21703 // TODO: Add other opcodes eventually lowered into BLEND.
21706 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21707 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21709 APInt KnownZero, KnownOne;
21710 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21711 DCI.isBeforeLegalizeOps());
21712 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21713 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21714 DCI.CommitTargetLoweringOpt(TLO);
21717 // We should generate an X86ISD::BLENDI from a vselect if its argument
21718 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21719 // constants. This specific pattern gets generated when we split a
21720 // selector for a 512 bit vector in a machine without AVX512 (but with
21721 // 256-bit vectors), during legalization:
21723 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21725 // Iff we find this pattern and the build_vectors are built from
21726 // constants, we translate the vselect into a shuffle_vector that we
21727 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21728 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21729 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21730 if (Shuffle.getNode())
21737 // Check whether a boolean test is testing a boolean value generated by
21738 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21741 // Simplify the following patterns:
21742 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21743 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21744 // to (Op EFLAGS Cond)
21746 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21747 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21748 // to (Op EFLAGS !Cond)
21750 // where Op could be BRCOND or CMOV.
21752 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21753 // Quit if not CMP and SUB with its value result used.
21754 if (Cmp.getOpcode() != X86ISD::CMP &&
21755 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21758 // Quit if not used as a boolean value.
21759 if (CC != X86::COND_E && CC != X86::COND_NE)
21762 // Check CMP operands. One of them should be 0 or 1 and the other should be
21763 // an SetCC or extended from it.
21764 SDValue Op1 = Cmp.getOperand(0);
21765 SDValue Op2 = Cmp.getOperand(1);
21768 const ConstantSDNode* C = nullptr;
21769 bool needOppositeCond = (CC == X86::COND_E);
21770 bool checkAgainstTrue = false; // Is it a comparison against 1?
21772 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21774 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21776 else // Quit if all operands are not constants.
21779 if (C->getZExtValue() == 1) {
21780 needOppositeCond = !needOppositeCond;
21781 checkAgainstTrue = true;
21782 } else if (C->getZExtValue() != 0)
21783 // Quit if the constant is neither 0 or 1.
21786 bool truncatedToBoolWithAnd = false;
21787 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21788 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21789 SetCC.getOpcode() == ISD::TRUNCATE ||
21790 SetCC.getOpcode() == ISD::AND) {
21791 if (SetCC.getOpcode() == ISD::AND) {
21793 ConstantSDNode *CS;
21794 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21795 CS->getZExtValue() == 1)
21797 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21798 CS->getZExtValue() == 1)
21802 SetCC = SetCC.getOperand(OpIdx);
21803 truncatedToBoolWithAnd = true;
21805 SetCC = SetCC.getOperand(0);
21808 switch (SetCC.getOpcode()) {
21809 case X86ISD::SETCC_CARRY:
21810 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21811 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21812 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21813 // truncated to i1 using 'and'.
21814 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21816 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21817 "Invalid use of SETCC_CARRY!");
21819 case X86ISD::SETCC:
21820 // Set the condition code or opposite one if necessary.
21821 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21822 if (needOppositeCond)
21823 CC = X86::GetOppositeBranchCondition(CC);
21824 return SetCC.getOperand(1);
21825 case X86ISD::CMOV: {
21826 // Check whether false/true value has canonical one, i.e. 0 or 1.
21827 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21828 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21829 // Quit if true value is not a constant.
21832 // Quit if false value is not a constant.
21834 SDValue Op = SetCC.getOperand(0);
21835 // Skip 'zext' or 'trunc' node.
21836 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21837 Op.getOpcode() == ISD::TRUNCATE)
21838 Op = Op.getOperand(0);
21839 // A special case for rdrand/rdseed, where 0 is set if false cond is
21841 if ((Op.getOpcode() != X86ISD::RDRAND &&
21842 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21845 // Quit if false value is not the constant 0 or 1.
21846 bool FValIsFalse = true;
21847 if (FVal && FVal->getZExtValue() != 0) {
21848 if (FVal->getZExtValue() != 1)
21850 // If FVal is 1, opposite cond is needed.
21851 needOppositeCond = !needOppositeCond;
21852 FValIsFalse = false;
21854 // Quit if TVal is not the constant opposite of FVal.
21855 if (FValIsFalse && TVal->getZExtValue() != 1)
21857 if (!FValIsFalse && TVal->getZExtValue() != 0)
21859 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21860 if (needOppositeCond)
21861 CC = X86::GetOppositeBranchCondition(CC);
21862 return SetCC.getOperand(3);
21869 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21870 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21871 TargetLowering::DAGCombinerInfo &DCI,
21872 const X86Subtarget *Subtarget) {
21875 // If the flag operand isn't dead, don't touch this CMOV.
21876 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21879 SDValue FalseOp = N->getOperand(0);
21880 SDValue TrueOp = N->getOperand(1);
21881 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21882 SDValue Cond = N->getOperand(3);
21884 if (CC == X86::COND_E || CC == X86::COND_NE) {
21885 switch (Cond.getOpcode()) {
21889 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21890 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21891 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21897 Flags = checkBoolTestSetCCCombine(Cond, CC);
21898 if (Flags.getNode() &&
21899 // Extra check as FCMOV only supports a subset of X86 cond.
21900 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21901 SDValue Ops[] = { FalseOp, TrueOp,
21902 DAG.getConstant(CC, MVT::i8), Flags };
21903 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21906 // If this is a select between two integer constants, try to do some
21907 // optimizations. Note that the operands are ordered the opposite of SELECT
21909 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21910 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21911 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21912 // larger than FalseC (the false value).
21913 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21914 CC = X86::GetOppositeBranchCondition(CC);
21915 std::swap(TrueC, FalseC);
21916 std::swap(TrueOp, FalseOp);
21919 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21920 // This is efficient for any integer data type (including i8/i16) and
21922 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21923 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21924 DAG.getConstant(CC, MVT::i8), Cond);
21926 // Zero extend the condition if needed.
21927 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21929 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21930 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21931 DAG.getConstant(ShAmt, MVT::i8));
21932 if (N->getNumValues() == 2) // Dead flag value?
21933 return DCI.CombineTo(N, Cond, SDValue());
21937 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21938 // for any integer data type, including i8/i16.
21939 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21940 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21941 DAG.getConstant(CC, MVT::i8), Cond);
21943 // Zero extend the condition if needed.
21944 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21945 FalseC->getValueType(0), Cond);
21946 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21947 SDValue(FalseC, 0));
21949 if (N->getNumValues() == 2) // Dead flag value?
21950 return DCI.CombineTo(N, Cond, SDValue());
21954 // Optimize cases that will turn into an LEA instruction. This requires
21955 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21956 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21957 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21958 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21960 bool isFastMultiplier = false;
21962 switch ((unsigned char)Diff) {
21964 case 1: // result = add base, cond
21965 case 2: // result = lea base( , cond*2)
21966 case 3: // result = lea base(cond, cond*2)
21967 case 4: // result = lea base( , cond*4)
21968 case 5: // result = lea base(cond, cond*4)
21969 case 8: // result = lea base( , cond*8)
21970 case 9: // result = lea base(cond, cond*8)
21971 isFastMultiplier = true;
21976 if (isFastMultiplier) {
21977 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21978 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21979 DAG.getConstant(CC, MVT::i8), Cond);
21980 // Zero extend the condition if needed.
21981 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21983 // Scale the condition by the difference.
21985 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21986 DAG.getConstant(Diff, Cond.getValueType()));
21988 // Add the base if non-zero.
21989 if (FalseC->getAPIntValue() != 0)
21990 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21991 SDValue(FalseC, 0));
21992 if (N->getNumValues() == 2) // Dead flag value?
21993 return DCI.CombineTo(N, Cond, SDValue());
22000 // Handle these cases:
22001 // (select (x != c), e, c) -> select (x != c), e, x),
22002 // (select (x == c), c, e) -> select (x == c), x, e)
22003 // where the c is an integer constant, and the "select" is the combination
22004 // of CMOV and CMP.
22006 // The rationale for this change is that the conditional-move from a constant
22007 // needs two instructions, however, conditional-move from a register needs
22008 // only one instruction.
22010 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22011 // some instruction-combining opportunities. This opt needs to be
22012 // postponed as late as possible.
22014 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22015 // the DCI.xxxx conditions are provided to postpone the optimization as
22016 // late as possible.
22018 ConstantSDNode *CmpAgainst = nullptr;
22019 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22020 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22021 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22023 if (CC == X86::COND_NE &&
22024 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22025 CC = X86::GetOppositeBranchCondition(CC);
22026 std::swap(TrueOp, FalseOp);
22029 if (CC == X86::COND_E &&
22030 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22031 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22032 DAG.getConstant(CC, MVT::i8), Cond };
22033 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22041 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22042 const X86Subtarget *Subtarget) {
22043 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22045 default: return SDValue();
22046 // SSE/AVX/AVX2 blend intrinsics.
22047 case Intrinsic::x86_avx2_pblendvb:
22048 case Intrinsic::x86_avx2_pblendw:
22049 case Intrinsic::x86_avx2_pblendd_128:
22050 case Intrinsic::x86_avx2_pblendd_256:
22051 // Don't try to simplify this intrinsic if we don't have AVX2.
22052 if (!Subtarget->hasAVX2())
22055 case Intrinsic::x86_avx_blend_pd_256:
22056 case Intrinsic::x86_avx_blend_ps_256:
22057 case Intrinsic::x86_avx_blendv_pd_256:
22058 case Intrinsic::x86_avx_blendv_ps_256:
22059 // Don't try to simplify this intrinsic if we don't have AVX.
22060 if (!Subtarget->hasAVX())
22063 case Intrinsic::x86_sse41_pblendw:
22064 case Intrinsic::x86_sse41_blendpd:
22065 case Intrinsic::x86_sse41_blendps:
22066 case Intrinsic::x86_sse41_blendvps:
22067 case Intrinsic::x86_sse41_blendvpd:
22068 case Intrinsic::x86_sse41_pblendvb: {
22069 SDValue Op0 = N->getOperand(1);
22070 SDValue Op1 = N->getOperand(2);
22071 SDValue Mask = N->getOperand(3);
22073 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22074 if (!Subtarget->hasSSE41())
22077 // fold (blend A, A, Mask) -> A
22080 // fold (blend A, B, allZeros) -> A
22081 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22083 // fold (blend A, B, allOnes) -> B
22084 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22087 // Simplify the case where the mask is a constant i32 value.
22088 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22089 if (C->isNullValue())
22091 if (C->isAllOnesValue())
22098 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22099 case Intrinsic::x86_sse2_psrai_w:
22100 case Intrinsic::x86_sse2_psrai_d:
22101 case Intrinsic::x86_avx2_psrai_w:
22102 case Intrinsic::x86_avx2_psrai_d:
22103 case Intrinsic::x86_sse2_psra_w:
22104 case Intrinsic::x86_sse2_psra_d:
22105 case Intrinsic::x86_avx2_psra_w:
22106 case Intrinsic::x86_avx2_psra_d: {
22107 SDValue Op0 = N->getOperand(1);
22108 SDValue Op1 = N->getOperand(2);
22109 EVT VT = Op0.getValueType();
22110 assert(VT.isVector() && "Expected a vector type!");
22112 if (isa<BuildVectorSDNode>(Op1))
22113 Op1 = Op1.getOperand(0);
22115 if (!isa<ConstantSDNode>(Op1))
22118 EVT SVT = VT.getVectorElementType();
22119 unsigned SVTBits = SVT.getSizeInBits();
22121 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22122 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22123 uint64_t ShAmt = C.getZExtValue();
22125 // Don't try to convert this shift into a ISD::SRA if the shift
22126 // count is bigger than or equal to the element size.
22127 if (ShAmt >= SVTBits)
22130 // Trivial case: if the shift count is zero, then fold this
22131 // into the first operand.
22135 // Replace this packed shift intrinsic with a target independent
22137 SDValue Splat = DAG.getConstant(C, VT);
22138 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22143 /// PerformMulCombine - Optimize a single multiply with constant into two
22144 /// in order to implement it with two cheaper instructions, e.g.
22145 /// LEA + SHL, LEA + LEA.
22146 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22147 TargetLowering::DAGCombinerInfo &DCI) {
22148 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22151 EVT VT = N->getValueType(0);
22152 if (VT != MVT::i64)
22155 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22158 uint64_t MulAmt = C->getZExtValue();
22159 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22162 uint64_t MulAmt1 = 0;
22163 uint64_t MulAmt2 = 0;
22164 if ((MulAmt % 9) == 0) {
22166 MulAmt2 = MulAmt / 9;
22167 } else if ((MulAmt % 5) == 0) {
22169 MulAmt2 = MulAmt / 5;
22170 } else if ((MulAmt % 3) == 0) {
22172 MulAmt2 = MulAmt / 3;
22175 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22178 if (isPowerOf2_64(MulAmt2) &&
22179 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22180 // If second multiplifer is pow2, issue it first. We want the multiply by
22181 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22183 std::swap(MulAmt1, MulAmt2);
22186 if (isPowerOf2_64(MulAmt1))
22187 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22188 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22190 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22191 DAG.getConstant(MulAmt1, VT));
22193 if (isPowerOf2_64(MulAmt2))
22194 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22195 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22197 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22198 DAG.getConstant(MulAmt2, VT));
22200 // Do not add new nodes to DAG combiner worklist.
22201 DCI.CombineTo(N, NewMul, false);
22206 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22207 SDValue N0 = N->getOperand(0);
22208 SDValue N1 = N->getOperand(1);
22209 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22210 EVT VT = N0.getValueType();
22212 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22213 // since the result of setcc_c is all zero's or all ones.
22214 if (VT.isInteger() && !VT.isVector() &&
22215 N1C && N0.getOpcode() == ISD::AND &&
22216 N0.getOperand(1).getOpcode() == ISD::Constant) {
22217 SDValue N00 = N0.getOperand(0);
22218 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22219 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22220 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22221 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22222 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22223 APInt ShAmt = N1C->getAPIntValue();
22224 Mask = Mask.shl(ShAmt);
22226 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22227 N00, DAG.getConstant(Mask, VT));
22231 // Hardware support for vector shifts is sparse which makes us scalarize the
22232 // vector operations in many cases. Also, on sandybridge ADD is faster than
22234 // (shl V, 1) -> add V,V
22235 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22236 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22237 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22238 // We shift all of the values by one. In many cases we do not have
22239 // hardware support for this operation. This is better expressed as an ADD
22241 if (N1SplatC->getZExtValue() == 1)
22242 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22248 /// \brief Returns a vector of 0s if the node in input is a vector logical
22249 /// shift by a constant amount which is known to be bigger than or equal
22250 /// to the vector element size in bits.
22251 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22252 const X86Subtarget *Subtarget) {
22253 EVT VT = N->getValueType(0);
22255 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22256 (!Subtarget->hasInt256() ||
22257 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22260 SDValue Amt = N->getOperand(1);
22262 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22263 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22264 APInt ShiftAmt = AmtSplat->getAPIntValue();
22265 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22267 // SSE2/AVX2 logical shifts always return a vector of 0s
22268 // if the shift amount is bigger than or equal to
22269 // the element size. The constant shift amount will be
22270 // encoded as a 8-bit immediate.
22271 if (ShiftAmt.trunc(8).uge(MaxAmount))
22272 return getZeroVector(VT, Subtarget, DAG, DL);
22278 /// PerformShiftCombine - Combine shifts.
22279 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22280 TargetLowering::DAGCombinerInfo &DCI,
22281 const X86Subtarget *Subtarget) {
22282 if (N->getOpcode() == ISD::SHL) {
22283 SDValue V = PerformSHLCombine(N, DAG);
22284 if (V.getNode()) return V;
22287 if (N->getOpcode() != ISD::SRA) {
22288 // Try to fold this logical shift into a zero vector.
22289 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22290 if (V.getNode()) return V;
22296 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22297 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22298 // and friends. Likewise for OR -> CMPNEQSS.
22299 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22300 TargetLowering::DAGCombinerInfo &DCI,
22301 const X86Subtarget *Subtarget) {
22304 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22305 // we're requiring SSE2 for both.
22306 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22307 SDValue N0 = N->getOperand(0);
22308 SDValue N1 = N->getOperand(1);
22309 SDValue CMP0 = N0->getOperand(1);
22310 SDValue CMP1 = N1->getOperand(1);
22313 // The SETCCs should both refer to the same CMP.
22314 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22317 SDValue CMP00 = CMP0->getOperand(0);
22318 SDValue CMP01 = CMP0->getOperand(1);
22319 EVT VT = CMP00.getValueType();
22321 if (VT == MVT::f32 || VT == MVT::f64) {
22322 bool ExpectingFlags = false;
22323 // Check for any users that want flags:
22324 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22325 !ExpectingFlags && UI != UE; ++UI)
22326 switch (UI->getOpcode()) {
22331 ExpectingFlags = true;
22333 case ISD::CopyToReg:
22334 case ISD::SIGN_EXTEND:
22335 case ISD::ZERO_EXTEND:
22336 case ISD::ANY_EXTEND:
22340 if (!ExpectingFlags) {
22341 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22342 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22344 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22345 X86::CondCode tmp = cc0;
22350 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22351 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22352 // FIXME: need symbolic constants for these magic numbers.
22353 // See X86ATTInstPrinter.cpp:printSSECC().
22354 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22355 if (Subtarget->hasAVX512()) {
22356 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22357 CMP01, DAG.getConstant(x86cc, MVT::i8));
22358 if (N->getValueType(0) != MVT::i1)
22359 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22363 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22364 CMP00.getValueType(), CMP00, CMP01,
22365 DAG.getConstant(x86cc, MVT::i8));
22367 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22368 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22370 if (is64BitFP && !Subtarget->is64Bit()) {
22371 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22372 // 64-bit integer, since that's not a legal type. Since
22373 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22374 // bits, but can do this little dance to extract the lowest 32 bits
22375 // and work with those going forward.
22376 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22378 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22380 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22381 Vector32, DAG.getIntPtrConstant(0));
22385 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22386 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22387 DAG.getConstant(1, IntVT));
22388 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22389 return OneBitOfTruth;
22397 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22398 /// so it can be folded inside ANDNP.
22399 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22400 EVT VT = N->getValueType(0);
22402 // Match direct AllOnes for 128 and 256-bit vectors
22403 if (ISD::isBuildVectorAllOnes(N))
22406 // Look through a bit convert.
22407 if (N->getOpcode() == ISD::BITCAST)
22408 N = N->getOperand(0).getNode();
22410 // Sometimes the operand may come from a insert_subvector building a 256-bit
22412 if (VT.is256BitVector() &&
22413 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22414 SDValue V1 = N->getOperand(0);
22415 SDValue V2 = N->getOperand(1);
22417 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22418 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22419 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22420 ISD::isBuildVectorAllOnes(V2.getNode()))
22427 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22428 // register. In most cases we actually compare or select YMM-sized registers
22429 // and mixing the two types creates horrible code. This method optimizes
22430 // some of the transition sequences.
22431 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22432 TargetLowering::DAGCombinerInfo &DCI,
22433 const X86Subtarget *Subtarget) {
22434 EVT VT = N->getValueType(0);
22435 if (!VT.is256BitVector())
22438 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22439 N->getOpcode() == ISD::ZERO_EXTEND ||
22440 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22442 SDValue Narrow = N->getOperand(0);
22443 EVT NarrowVT = Narrow->getValueType(0);
22444 if (!NarrowVT.is128BitVector())
22447 if (Narrow->getOpcode() != ISD::XOR &&
22448 Narrow->getOpcode() != ISD::AND &&
22449 Narrow->getOpcode() != ISD::OR)
22452 SDValue N0 = Narrow->getOperand(0);
22453 SDValue N1 = Narrow->getOperand(1);
22456 // The Left side has to be a trunc.
22457 if (N0.getOpcode() != ISD::TRUNCATE)
22460 // The type of the truncated inputs.
22461 EVT WideVT = N0->getOperand(0)->getValueType(0);
22465 // The right side has to be a 'trunc' or a constant vector.
22466 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22467 ConstantSDNode *RHSConstSplat = nullptr;
22468 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22469 RHSConstSplat = RHSBV->getConstantSplatNode();
22470 if (!RHSTrunc && !RHSConstSplat)
22473 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22475 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22478 // Set N0 and N1 to hold the inputs to the new wide operation.
22479 N0 = N0->getOperand(0);
22480 if (RHSConstSplat) {
22481 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22482 SDValue(RHSConstSplat, 0));
22483 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22484 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22485 } else if (RHSTrunc) {
22486 N1 = N1->getOperand(0);
22489 // Generate the wide operation.
22490 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22491 unsigned Opcode = N->getOpcode();
22493 case ISD::ANY_EXTEND:
22495 case ISD::ZERO_EXTEND: {
22496 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22497 APInt Mask = APInt::getAllOnesValue(InBits);
22498 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22499 return DAG.getNode(ISD::AND, DL, VT,
22500 Op, DAG.getConstant(Mask, VT));
22502 case ISD::SIGN_EXTEND:
22503 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22504 Op, DAG.getValueType(NarrowVT));
22506 llvm_unreachable("Unexpected opcode");
22510 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22511 TargetLowering::DAGCombinerInfo &DCI,
22512 const X86Subtarget *Subtarget) {
22513 EVT VT = N->getValueType(0);
22514 if (DCI.isBeforeLegalizeOps())
22517 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22521 // Create BEXTR instructions
22522 // BEXTR is ((X >> imm) & (2**size-1))
22523 if (VT == MVT::i32 || VT == MVT::i64) {
22524 SDValue N0 = N->getOperand(0);
22525 SDValue N1 = N->getOperand(1);
22528 // Check for BEXTR.
22529 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22530 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22531 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22532 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22533 if (MaskNode && ShiftNode) {
22534 uint64_t Mask = MaskNode->getZExtValue();
22535 uint64_t Shift = ShiftNode->getZExtValue();
22536 if (isMask_64(Mask)) {
22537 uint64_t MaskSize = CountPopulation_64(Mask);
22538 if (Shift + MaskSize <= VT.getSizeInBits())
22539 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22540 DAG.getConstant(Shift | (MaskSize << 8), VT));
22548 // Want to form ANDNP nodes:
22549 // 1) In the hopes of then easily combining them with OR and AND nodes
22550 // to form PBLEND/PSIGN.
22551 // 2) To match ANDN packed intrinsics
22552 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22555 SDValue N0 = N->getOperand(0);
22556 SDValue N1 = N->getOperand(1);
22559 // Check LHS for vnot
22560 if (N0.getOpcode() == ISD::XOR &&
22561 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22562 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22563 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22565 // Check RHS for vnot
22566 if (N1.getOpcode() == ISD::XOR &&
22567 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22568 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22569 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22574 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22575 TargetLowering::DAGCombinerInfo &DCI,
22576 const X86Subtarget *Subtarget) {
22577 if (DCI.isBeforeLegalizeOps())
22580 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22584 SDValue N0 = N->getOperand(0);
22585 SDValue N1 = N->getOperand(1);
22586 EVT VT = N->getValueType(0);
22588 // look for psign/blend
22589 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22590 if (!Subtarget->hasSSSE3() ||
22591 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22594 // Canonicalize pandn to RHS
22595 if (N0.getOpcode() == X86ISD::ANDNP)
22597 // or (and (m, y), (pandn m, x))
22598 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22599 SDValue Mask = N1.getOperand(0);
22600 SDValue X = N1.getOperand(1);
22602 if (N0.getOperand(0) == Mask)
22603 Y = N0.getOperand(1);
22604 if (N0.getOperand(1) == Mask)
22605 Y = N0.getOperand(0);
22607 // Check to see if the mask appeared in both the AND and ANDNP and
22611 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22612 // Look through mask bitcast.
22613 if (Mask.getOpcode() == ISD::BITCAST)
22614 Mask = Mask.getOperand(0);
22615 if (X.getOpcode() == ISD::BITCAST)
22616 X = X.getOperand(0);
22617 if (Y.getOpcode() == ISD::BITCAST)
22618 Y = Y.getOperand(0);
22620 EVT MaskVT = Mask.getValueType();
22622 // Validate that the Mask operand is a vector sra node.
22623 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22624 // there is no psrai.b
22625 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22626 unsigned SraAmt = ~0;
22627 if (Mask.getOpcode() == ISD::SRA) {
22628 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22629 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22630 SraAmt = AmtConst->getZExtValue();
22631 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22632 SDValue SraC = Mask.getOperand(1);
22633 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22635 if ((SraAmt + 1) != EltBits)
22640 // Now we know we at least have a plendvb with the mask val. See if
22641 // we can form a psignb/w/d.
22642 // psign = x.type == y.type == mask.type && y = sub(0, x);
22643 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22644 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22645 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22646 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22647 "Unsupported VT for PSIGN");
22648 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22649 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22651 // PBLENDVB only available on SSE 4.1
22652 if (!Subtarget->hasSSE41())
22655 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22657 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22658 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22659 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22660 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22661 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22665 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22668 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22669 MachineFunction &MF = DAG.getMachineFunction();
22670 bool OptForSize = MF.getFunction()->getAttributes().
22671 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22673 // SHLD/SHRD instructions have lower register pressure, but on some
22674 // platforms they have higher latency than the equivalent
22675 // series of shifts/or that would otherwise be generated.
22676 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22677 // have higher latencies and we are not optimizing for size.
22678 if (!OptForSize && Subtarget->isSHLDSlow())
22681 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22683 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22685 if (!N0.hasOneUse() || !N1.hasOneUse())
22688 SDValue ShAmt0 = N0.getOperand(1);
22689 if (ShAmt0.getValueType() != MVT::i8)
22691 SDValue ShAmt1 = N1.getOperand(1);
22692 if (ShAmt1.getValueType() != MVT::i8)
22694 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22695 ShAmt0 = ShAmt0.getOperand(0);
22696 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22697 ShAmt1 = ShAmt1.getOperand(0);
22700 unsigned Opc = X86ISD::SHLD;
22701 SDValue Op0 = N0.getOperand(0);
22702 SDValue Op1 = N1.getOperand(0);
22703 if (ShAmt0.getOpcode() == ISD::SUB) {
22704 Opc = X86ISD::SHRD;
22705 std::swap(Op0, Op1);
22706 std::swap(ShAmt0, ShAmt1);
22709 unsigned Bits = VT.getSizeInBits();
22710 if (ShAmt1.getOpcode() == ISD::SUB) {
22711 SDValue Sum = ShAmt1.getOperand(0);
22712 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22713 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22714 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22715 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22716 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22717 return DAG.getNode(Opc, DL, VT,
22719 DAG.getNode(ISD::TRUNCATE, DL,
22722 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22723 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22725 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22726 return DAG.getNode(Opc, DL, VT,
22727 N0.getOperand(0), N1.getOperand(0),
22728 DAG.getNode(ISD::TRUNCATE, DL,
22735 // Generate NEG and CMOV for integer abs.
22736 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22737 EVT VT = N->getValueType(0);
22739 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22740 // 8-bit integer abs to NEG and CMOV.
22741 if (VT.isInteger() && VT.getSizeInBits() == 8)
22744 SDValue N0 = N->getOperand(0);
22745 SDValue N1 = N->getOperand(1);
22748 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22749 // and change it to SUB and CMOV.
22750 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22751 N0.getOpcode() == ISD::ADD &&
22752 N0.getOperand(1) == N1 &&
22753 N1.getOpcode() == ISD::SRA &&
22754 N1.getOperand(0) == N0.getOperand(0))
22755 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22756 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22757 // Generate SUB & CMOV.
22758 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22759 DAG.getConstant(0, VT), N0.getOperand(0));
22761 SDValue Ops[] = { N0.getOperand(0), Neg,
22762 DAG.getConstant(X86::COND_GE, MVT::i8),
22763 SDValue(Neg.getNode(), 1) };
22764 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22769 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22770 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22771 TargetLowering::DAGCombinerInfo &DCI,
22772 const X86Subtarget *Subtarget) {
22773 if (DCI.isBeforeLegalizeOps())
22776 if (Subtarget->hasCMov()) {
22777 SDValue RV = performIntegerAbsCombine(N, DAG);
22785 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22786 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22787 TargetLowering::DAGCombinerInfo &DCI,
22788 const X86Subtarget *Subtarget) {
22789 LoadSDNode *Ld = cast<LoadSDNode>(N);
22790 EVT RegVT = Ld->getValueType(0);
22791 EVT MemVT = Ld->getMemoryVT();
22793 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22795 // On Sandybridge unaligned 256bit loads are inefficient.
22796 ISD::LoadExtType Ext = Ld->getExtensionType();
22797 unsigned Alignment = Ld->getAlignment();
22798 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22799 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22800 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22801 unsigned NumElems = RegVT.getVectorNumElements();
22805 SDValue Ptr = Ld->getBasePtr();
22806 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22808 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22810 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22811 Ld->getPointerInfo(), Ld->isVolatile(),
22812 Ld->isNonTemporal(), Ld->isInvariant(),
22814 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22815 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22816 Ld->getPointerInfo(), Ld->isVolatile(),
22817 Ld->isNonTemporal(), Ld->isInvariant(),
22818 std::min(16U, Alignment));
22819 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22821 Load2.getValue(1));
22823 SDValue NewVec = DAG.getUNDEF(RegVT);
22824 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22825 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22826 return DCI.CombineTo(N, NewVec, TF, true);
22832 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22833 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22834 const X86Subtarget *Subtarget) {
22835 StoreSDNode *St = cast<StoreSDNode>(N);
22836 EVT VT = St->getValue().getValueType();
22837 EVT StVT = St->getMemoryVT();
22839 SDValue StoredVal = St->getOperand(1);
22840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22842 // If we are saving a concatenation of two XMM registers, perform two stores.
22843 // On Sandy Bridge, 256-bit memory operations are executed by two
22844 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22845 // memory operation.
22846 unsigned Alignment = St->getAlignment();
22847 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22848 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22849 StVT == VT && !IsAligned) {
22850 unsigned NumElems = VT.getVectorNumElements();
22854 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22855 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22857 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22858 SDValue Ptr0 = St->getBasePtr();
22859 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22861 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22862 St->getPointerInfo(), St->isVolatile(),
22863 St->isNonTemporal(), Alignment);
22864 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22865 St->getPointerInfo(), St->isVolatile(),
22866 St->isNonTemporal(),
22867 std::min(16U, Alignment));
22868 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22871 // Optimize trunc store (of multiple scalars) to shuffle and store.
22872 // First, pack all of the elements in one place. Next, store to memory
22873 // in fewer chunks.
22874 if (St->isTruncatingStore() && VT.isVector()) {
22875 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22876 unsigned NumElems = VT.getVectorNumElements();
22877 assert(StVT != VT && "Cannot truncate to the same type");
22878 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22879 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22881 // From, To sizes and ElemCount must be pow of two
22882 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22883 // We are going to use the original vector elt for storing.
22884 // Accumulated smaller vector elements must be a multiple of the store size.
22885 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22887 unsigned SizeRatio = FromSz / ToSz;
22889 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22891 // Create a type on which we perform the shuffle
22892 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22893 StVT.getScalarType(), NumElems*SizeRatio);
22895 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22897 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22898 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22899 for (unsigned i = 0; i != NumElems; ++i)
22900 ShuffleVec[i] = i * SizeRatio;
22902 // Can't shuffle using an illegal type.
22903 if (!TLI.isTypeLegal(WideVecVT))
22906 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22907 DAG.getUNDEF(WideVecVT),
22909 // At this point all of the data is stored at the bottom of the
22910 // register. We now need to save it to mem.
22912 // Find the largest store unit
22913 MVT StoreType = MVT::i8;
22914 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22915 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22916 MVT Tp = (MVT::SimpleValueType)tp;
22917 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22921 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22922 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22923 (64 <= NumElems * ToSz))
22924 StoreType = MVT::f64;
22926 // Bitcast the original vector into a vector of store-size units
22927 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22928 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22929 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22930 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22931 SmallVector<SDValue, 8> Chains;
22932 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22933 TLI.getPointerTy());
22934 SDValue Ptr = St->getBasePtr();
22936 // Perform one or more big stores into memory.
22937 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22938 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22939 StoreType, ShuffWide,
22940 DAG.getIntPtrConstant(i));
22941 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22942 St->getPointerInfo(), St->isVolatile(),
22943 St->isNonTemporal(), St->getAlignment());
22944 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22945 Chains.push_back(Ch);
22948 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22951 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22952 // the FP state in cases where an emms may be missing.
22953 // A preferable solution to the general problem is to figure out the right
22954 // places to insert EMMS. This qualifies as a quick hack.
22956 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22957 if (VT.getSizeInBits() != 64)
22960 const Function *F = DAG.getMachineFunction().getFunction();
22961 bool NoImplicitFloatOps = F->getAttributes().
22962 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22963 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22964 && Subtarget->hasSSE2();
22965 if ((VT.isVector() ||
22966 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22967 isa<LoadSDNode>(St->getValue()) &&
22968 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22969 St->getChain().hasOneUse() && !St->isVolatile()) {
22970 SDNode* LdVal = St->getValue().getNode();
22971 LoadSDNode *Ld = nullptr;
22972 int TokenFactorIndex = -1;
22973 SmallVector<SDValue, 8> Ops;
22974 SDNode* ChainVal = St->getChain().getNode();
22975 // Must be a store of a load. We currently handle two cases: the load
22976 // is a direct child, and it's under an intervening TokenFactor. It is
22977 // possible to dig deeper under nested TokenFactors.
22978 if (ChainVal == LdVal)
22979 Ld = cast<LoadSDNode>(St->getChain());
22980 else if (St->getValue().hasOneUse() &&
22981 ChainVal->getOpcode() == ISD::TokenFactor) {
22982 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22983 if (ChainVal->getOperand(i).getNode() == LdVal) {
22984 TokenFactorIndex = i;
22985 Ld = cast<LoadSDNode>(St->getValue());
22987 Ops.push_back(ChainVal->getOperand(i));
22991 if (!Ld || !ISD::isNormalLoad(Ld))
22994 // If this is not the MMX case, i.e. we are just turning i64 load/store
22995 // into f64 load/store, avoid the transformation if there are multiple
22996 // uses of the loaded value.
22997 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23002 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23003 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23005 if (Subtarget->is64Bit() || F64IsLegal) {
23006 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23007 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23008 Ld->getPointerInfo(), Ld->isVolatile(),
23009 Ld->isNonTemporal(), Ld->isInvariant(),
23010 Ld->getAlignment());
23011 SDValue NewChain = NewLd.getValue(1);
23012 if (TokenFactorIndex != -1) {
23013 Ops.push_back(NewChain);
23014 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23016 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23017 St->getPointerInfo(),
23018 St->isVolatile(), St->isNonTemporal(),
23019 St->getAlignment());
23022 // Otherwise, lower to two pairs of 32-bit loads / stores.
23023 SDValue LoAddr = Ld->getBasePtr();
23024 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23025 DAG.getConstant(4, MVT::i32));
23027 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23028 Ld->getPointerInfo(),
23029 Ld->isVolatile(), Ld->isNonTemporal(),
23030 Ld->isInvariant(), Ld->getAlignment());
23031 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23032 Ld->getPointerInfo().getWithOffset(4),
23033 Ld->isVolatile(), Ld->isNonTemporal(),
23035 MinAlign(Ld->getAlignment(), 4));
23037 SDValue NewChain = LoLd.getValue(1);
23038 if (TokenFactorIndex != -1) {
23039 Ops.push_back(LoLd);
23040 Ops.push_back(HiLd);
23041 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23044 LoAddr = St->getBasePtr();
23045 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23046 DAG.getConstant(4, MVT::i32));
23048 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23049 St->getPointerInfo(),
23050 St->isVolatile(), St->isNonTemporal(),
23051 St->getAlignment());
23052 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23053 St->getPointerInfo().getWithOffset(4),
23055 St->isNonTemporal(),
23056 MinAlign(St->getAlignment(), 4));
23057 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23062 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23063 /// and return the operands for the horizontal operation in LHS and RHS. A
23064 /// horizontal operation performs the binary operation on successive elements
23065 /// of its first operand, then on successive elements of its second operand,
23066 /// returning the resulting values in a vector. For example, if
23067 /// A = < float a0, float a1, float a2, float a3 >
23069 /// B = < float b0, float b1, float b2, float b3 >
23070 /// then the result of doing a horizontal operation on A and B is
23071 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23072 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23073 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23074 /// set to A, RHS to B, and the routine returns 'true'.
23075 /// Note that the binary operation should have the property that if one of the
23076 /// operands is UNDEF then the result is UNDEF.
23077 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23078 // Look for the following pattern: if
23079 // A = < float a0, float a1, float a2, float a3 >
23080 // B = < float b0, float b1, float b2, float b3 >
23082 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23083 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23084 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23085 // which is A horizontal-op B.
23087 // At least one of the operands should be a vector shuffle.
23088 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23089 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23092 MVT VT = LHS.getSimpleValueType();
23094 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23095 "Unsupported vector type for horizontal add/sub");
23097 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23098 // operate independently on 128-bit lanes.
23099 unsigned NumElts = VT.getVectorNumElements();
23100 unsigned NumLanes = VT.getSizeInBits()/128;
23101 unsigned NumLaneElts = NumElts / NumLanes;
23102 assert((NumLaneElts % 2 == 0) &&
23103 "Vector type should have an even number of elements in each lane");
23104 unsigned HalfLaneElts = NumLaneElts/2;
23106 // View LHS in the form
23107 // LHS = VECTOR_SHUFFLE A, B, LMask
23108 // If LHS is not a shuffle then pretend it is the shuffle
23109 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23110 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23113 SmallVector<int, 16> LMask(NumElts);
23114 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23115 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23116 A = LHS.getOperand(0);
23117 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23118 B = LHS.getOperand(1);
23119 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23120 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23122 if (LHS.getOpcode() != ISD::UNDEF)
23124 for (unsigned i = 0; i != NumElts; ++i)
23128 // Likewise, view RHS in the form
23129 // RHS = VECTOR_SHUFFLE C, D, RMask
23131 SmallVector<int, 16> RMask(NumElts);
23132 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23133 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23134 C = RHS.getOperand(0);
23135 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23136 D = RHS.getOperand(1);
23137 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23138 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23140 if (RHS.getOpcode() != ISD::UNDEF)
23142 for (unsigned i = 0; i != NumElts; ++i)
23146 // Check that the shuffles are both shuffling the same vectors.
23147 if (!(A == C && B == D) && !(A == D && B == C))
23150 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23151 if (!A.getNode() && !B.getNode())
23154 // If A and B occur in reverse order in RHS, then "swap" them (which means
23155 // rewriting the mask).
23157 CommuteVectorShuffleMask(RMask, NumElts);
23159 // At this point LHS and RHS are equivalent to
23160 // LHS = VECTOR_SHUFFLE A, B, LMask
23161 // RHS = VECTOR_SHUFFLE A, B, RMask
23162 // Check that the masks correspond to performing a horizontal operation.
23163 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23164 for (unsigned i = 0; i != NumLaneElts; ++i) {
23165 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23167 // Ignore any UNDEF components.
23168 if (LIdx < 0 || RIdx < 0 ||
23169 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23170 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23173 // Check that successive elements are being operated on. If not, this is
23174 // not a horizontal operation.
23175 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23176 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23177 if (!(LIdx == Index && RIdx == Index + 1) &&
23178 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23183 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23184 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23188 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23189 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23190 const X86Subtarget *Subtarget) {
23191 EVT VT = N->getValueType(0);
23192 SDValue LHS = N->getOperand(0);
23193 SDValue RHS = N->getOperand(1);
23195 // Try to synthesize horizontal adds from adds of shuffles.
23196 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23197 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23198 isHorizontalBinOp(LHS, RHS, true))
23199 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23203 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23204 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23205 const X86Subtarget *Subtarget) {
23206 EVT VT = N->getValueType(0);
23207 SDValue LHS = N->getOperand(0);
23208 SDValue RHS = N->getOperand(1);
23210 // Try to synthesize horizontal subs from subs of shuffles.
23211 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23212 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23213 isHorizontalBinOp(LHS, RHS, false))
23214 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23218 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23219 /// X86ISD::FXOR nodes.
23220 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23221 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23222 // F[X]OR(0.0, x) -> x
23223 // F[X]OR(x, 0.0) -> x
23224 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23225 if (C->getValueAPF().isPosZero())
23226 return N->getOperand(1);
23227 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23228 if (C->getValueAPF().isPosZero())
23229 return N->getOperand(0);
23233 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23234 /// X86ISD::FMAX nodes.
23235 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23236 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23238 // Only perform optimizations if UnsafeMath is used.
23239 if (!DAG.getTarget().Options.UnsafeFPMath)
23242 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23243 // into FMINC and FMAXC, which are Commutative operations.
23244 unsigned NewOp = 0;
23245 switch (N->getOpcode()) {
23246 default: llvm_unreachable("unknown opcode");
23247 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23248 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23251 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23252 N->getOperand(0), N->getOperand(1));
23255 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23256 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23257 // FAND(0.0, x) -> 0.0
23258 // FAND(x, 0.0) -> 0.0
23259 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23260 if (C->getValueAPF().isPosZero())
23261 return N->getOperand(0);
23262 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23263 if (C->getValueAPF().isPosZero())
23264 return N->getOperand(1);
23268 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23269 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23270 // FANDN(x, 0.0) -> 0.0
23271 // FANDN(0.0, x) -> x
23272 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23273 if (C->getValueAPF().isPosZero())
23274 return N->getOperand(1);
23275 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23276 if (C->getValueAPF().isPosZero())
23277 return N->getOperand(1);
23281 static SDValue PerformBTCombine(SDNode *N,
23283 TargetLowering::DAGCombinerInfo &DCI) {
23284 // BT ignores high bits in the bit index operand.
23285 SDValue Op1 = N->getOperand(1);
23286 if (Op1.hasOneUse()) {
23287 unsigned BitWidth = Op1.getValueSizeInBits();
23288 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23289 APInt KnownZero, KnownOne;
23290 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23291 !DCI.isBeforeLegalizeOps());
23292 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23293 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23294 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23295 DCI.CommitTargetLoweringOpt(TLO);
23300 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23301 SDValue Op = N->getOperand(0);
23302 if (Op.getOpcode() == ISD::BITCAST)
23303 Op = Op.getOperand(0);
23304 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23305 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23306 VT.getVectorElementType().getSizeInBits() ==
23307 OpVT.getVectorElementType().getSizeInBits()) {
23308 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23313 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23314 const X86Subtarget *Subtarget) {
23315 EVT VT = N->getValueType(0);
23316 if (!VT.isVector())
23319 SDValue N0 = N->getOperand(0);
23320 SDValue N1 = N->getOperand(1);
23321 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23324 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23325 // both SSE and AVX2 since there is no sign-extended shift right
23326 // operation on a vector with 64-bit elements.
23327 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23328 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23329 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23330 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23331 SDValue N00 = N0.getOperand(0);
23333 // EXTLOAD has a better solution on AVX2,
23334 // it may be replaced with X86ISD::VSEXT node.
23335 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23336 if (!ISD::isNormalLoad(N00.getNode()))
23339 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23340 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23342 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23348 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23349 TargetLowering::DAGCombinerInfo &DCI,
23350 const X86Subtarget *Subtarget) {
23351 if (!DCI.isBeforeLegalizeOps())
23354 if (!Subtarget->hasFp256())
23357 EVT VT = N->getValueType(0);
23358 if (VT.isVector() && VT.getSizeInBits() == 256) {
23359 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23367 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23368 const X86Subtarget* Subtarget) {
23370 EVT VT = N->getValueType(0);
23372 // Let legalize expand this if it isn't a legal type yet.
23373 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23376 EVT ScalarVT = VT.getScalarType();
23377 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23378 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23381 SDValue A = N->getOperand(0);
23382 SDValue B = N->getOperand(1);
23383 SDValue C = N->getOperand(2);
23385 bool NegA = (A.getOpcode() == ISD::FNEG);
23386 bool NegB = (B.getOpcode() == ISD::FNEG);
23387 bool NegC = (C.getOpcode() == ISD::FNEG);
23389 // Negative multiplication when NegA xor NegB
23390 bool NegMul = (NegA != NegB);
23392 A = A.getOperand(0);
23394 B = B.getOperand(0);
23396 C = C.getOperand(0);
23400 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23402 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23404 return DAG.getNode(Opcode, dl, VT, A, B, C);
23407 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23408 TargetLowering::DAGCombinerInfo &DCI,
23409 const X86Subtarget *Subtarget) {
23410 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23411 // (and (i32 x86isd::setcc_carry), 1)
23412 // This eliminates the zext. This transformation is necessary because
23413 // ISD::SETCC is always legalized to i8.
23415 SDValue N0 = N->getOperand(0);
23416 EVT VT = N->getValueType(0);
23418 if (N0.getOpcode() == ISD::AND &&
23420 N0.getOperand(0).hasOneUse()) {
23421 SDValue N00 = N0.getOperand(0);
23422 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23423 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23424 if (!C || C->getZExtValue() != 1)
23426 return DAG.getNode(ISD::AND, dl, VT,
23427 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23428 N00.getOperand(0), N00.getOperand(1)),
23429 DAG.getConstant(1, VT));
23433 if (N0.getOpcode() == ISD::TRUNCATE &&
23435 N0.getOperand(0).hasOneUse()) {
23436 SDValue N00 = N0.getOperand(0);
23437 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23438 return DAG.getNode(ISD::AND, dl, VT,
23439 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23440 N00.getOperand(0), N00.getOperand(1)),
23441 DAG.getConstant(1, VT));
23444 if (VT.is256BitVector()) {
23445 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23453 // Optimize x == -y --> x+y == 0
23454 // x != -y --> x+y != 0
23455 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23456 const X86Subtarget* Subtarget) {
23457 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23458 SDValue LHS = N->getOperand(0);
23459 SDValue RHS = N->getOperand(1);
23460 EVT VT = N->getValueType(0);
23463 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23464 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23465 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23466 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23467 LHS.getValueType(), RHS, LHS.getOperand(1));
23468 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23469 addV, DAG.getConstant(0, addV.getValueType()), CC);
23471 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23472 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23473 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23474 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23475 RHS.getValueType(), LHS, RHS.getOperand(1));
23476 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23477 addV, DAG.getConstant(0, addV.getValueType()), CC);
23480 if (VT.getScalarType() == MVT::i1) {
23481 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23482 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23483 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23484 if (!IsSEXT0 && !IsVZero0)
23486 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23487 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23488 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23490 if (!IsSEXT1 && !IsVZero1)
23493 if (IsSEXT0 && IsVZero1) {
23494 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23495 if (CC == ISD::SETEQ)
23496 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23497 return LHS.getOperand(0);
23499 if (IsSEXT1 && IsVZero0) {
23500 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23501 if (CC == ISD::SETEQ)
23502 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23503 return RHS.getOperand(0);
23510 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23511 const X86Subtarget *Subtarget) {
23513 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23514 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23515 "X86insertps is only defined for v4x32");
23517 SDValue Ld = N->getOperand(1);
23518 if (MayFoldLoad(Ld)) {
23519 // Extract the countS bits from the immediate so we can get the proper
23520 // address when narrowing the vector load to a specific element.
23521 // When the second source op is a memory address, interps doesn't use
23522 // countS and just gets an f32 from that address.
23523 unsigned DestIndex =
23524 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23525 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23529 // Create this as a scalar to vector to match the instruction pattern.
23530 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23531 // countS bits are ignored when loading from memory on insertps, which
23532 // means we don't need to explicitly set them to 0.
23533 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23534 LoadScalarToVector, N->getOperand(2));
23537 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23538 // as "sbb reg,reg", since it can be extended without zext and produces
23539 // an all-ones bit which is more useful than 0/1 in some cases.
23540 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23543 return DAG.getNode(ISD::AND, DL, VT,
23544 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23545 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23546 DAG.getConstant(1, VT));
23547 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23548 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23549 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23550 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23553 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23554 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23555 TargetLowering::DAGCombinerInfo &DCI,
23556 const X86Subtarget *Subtarget) {
23558 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23559 SDValue EFLAGS = N->getOperand(1);
23561 if (CC == X86::COND_A) {
23562 // Try to convert COND_A into COND_B in an attempt to facilitate
23563 // materializing "setb reg".
23565 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23566 // cannot take an immediate as its first operand.
23568 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23569 EFLAGS.getValueType().isInteger() &&
23570 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23571 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23572 EFLAGS.getNode()->getVTList(),
23573 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23574 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23575 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23579 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23580 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23582 if (CC == X86::COND_B)
23583 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23587 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23588 if (Flags.getNode()) {
23589 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23590 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23596 // Optimize branch condition evaluation.
23598 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23599 TargetLowering::DAGCombinerInfo &DCI,
23600 const X86Subtarget *Subtarget) {
23602 SDValue Chain = N->getOperand(0);
23603 SDValue Dest = N->getOperand(1);
23604 SDValue EFLAGS = N->getOperand(3);
23605 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23609 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23610 if (Flags.getNode()) {
23611 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23612 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23619 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23620 SelectionDAG &DAG) {
23621 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23622 // optimize away operation when it's from a constant.
23624 // The general transformation is:
23625 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23626 // AND(VECTOR_CMP(x,y), constant2)
23627 // constant2 = UNARYOP(constant)
23629 // Early exit if this isn't a vector operation, the operand of the
23630 // unary operation isn't a bitwise AND, or if the sizes of the operations
23631 // aren't the same.
23632 EVT VT = N->getValueType(0);
23633 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23634 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23635 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23638 // Now check that the other operand of the AND is a constant. We could
23639 // make the transformation for non-constant splats as well, but it's unclear
23640 // that would be a benefit as it would not eliminate any operations, just
23641 // perform one more step in scalar code before moving to the vector unit.
23642 if (BuildVectorSDNode *BV =
23643 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23644 // Bail out if the vector isn't a constant.
23645 if (!BV->isConstant())
23648 // Everything checks out. Build up the new and improved node.
23650 EVT IntVT = BV->getValueType(0);
23651 // Create a new constant of the appropriate type for the transformed
23653 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23654 // The AND node needs bitcasts to/from an integer vector type around it.
23655 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23656 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23657 N->getOperand(0)->getOperand(0), MaskConst);
23658 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23665 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23666 const X86TargetLowering *XTLI) {
23667 // First try to optimize away the conversion entirely when it's
23668 // conditionally from a constant. Vectors only.
23669 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23670 if (Res != SDValue())
23673 // Now move on to more general possibilities.
23674 SDValue Op0 = N->getOperand(0);
23675 EVT InVT = Op0->getValueType(0);
23677 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23678 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23680 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23681 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23682 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23685 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23686 // a 32-bit target where SSE doesn't support i64->FP operations.
23687 if (Op0.getOpcode() == ISD::LOAD) {
23688 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23689 EVT VT = Ld->getValueType(0);
23690 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23691 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23692 !XTLI->getSubtarget()->is64Bit() &&
23694 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23695 Ld->getChain(), Op0, DAG);
23696 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23703 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23704 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23705 X86TargetLowering::DAGCombinerInfo &DCI) {
23706 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23707 // the result is either zero or one (depending on the input carry bit).
23708 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23709 if (X86::isZeroNode(N->getOperand(0)) &&
23710 X86::isZeroNode(N->getOperand(1)) &&
23711 // We don't have a good way to replace an EFLAGS use, so only do this when
23713 SDValue(N, 1).use_empty()) {
23715 EVT VT = N->getValueType(0);
23716 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23717 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23718 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23719 DAG.getConstant(X86::COND_B,MVT::i8),
23721 DAG.getConstant(1, VT));
23722 return DCI.CombineTo(N, Res1, CarryOut);
23728 // fold (add Y, (sete X, 0)) -> adc 0, Y
23729 // (add Y, (setne X, 0)) -> sbb -1, Y
23730 // (sub (sete X, 0), Y) -> sbb 0, Y
23731 // (sub (setne X, 0), Y) -> adc -1, Y
23732 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23735 // Look through ZExts.
23736 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23737 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23740 SDValue SetCC = Ext.getOperand(0);
23741 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23744 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23745 if (CC != X86::COND_E && CC != X86::COND_NE)
23748 SDValue Cmp = SetCC.getOperand(1);
23749 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23750 !X86::isZeroNode(Cmp.getOperand(1)) ||
23751 !Cmp.getOperand(0).getValueType().isInteger())
23754 SDValue CmpOp0 = Cmp.getOperand(0);
23755 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23756 DAG.getConstant(1, CmpOp0.getValueType()));
23758 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23759 if (CC == X86::COND_NE)
23760 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23761 DL, OtherVal.getValueType(), OtherVal,
23762 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23763 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23764 DL, OtherVal.getValueType(), OtherVal,
23765 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23768 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23769 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23770 const X86Subtarget *Subtarget) {
23771 EVT VT = N->getValueType(0);
23772 SDValue Op0 = N->getOperand(0);
23773 SDValue Op1 = N->getOperand(1);
23775 // Try to synthesize horizontal adds from adds of shuffles.
23776 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23777 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23778 isHorizontalBinOp(Op0, Op1, true))
23779 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23781 return OptimizeConditionalInDecrement(N, DAG);
23784 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23785 const X86Subtarget *Subtarget) {
23786 SDValue Op0 = N->getOperand(0);
23787 SDValue Op1 = N->getOperand(1);
23789 // X86 can't encode an immediate LHS of a sub. See if we can push the
23790 // negation into a preceding instruction.
23791 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23792 // If the RHS of the sub is a XOR with one use and a constant, invert the
23793 // immediate. Then add one to the LHS of the sub so we can turn
23794 // X-Y -> X+~Y+1, saving one register.
23795 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23796 isa<ConstantSDNode>(Op1.getOperand(1))) {
23797 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23798 EVT VT = Op0.getValueType();
23799 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23801 DAG.getConstant(~XorC, VT));
23802 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23803 DAG.getConstant(C->getAPIntValue()+1, VT));
23807 // Try to synthesize horizontal adds from adds of shuffles.
23808 EVT VT = N->getValueType(0);
23809 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23810 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23811 isHorizontalBinOp(Op0, Op1, true))
23812 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23814 return OptimizeConditionalInDecrement(N, DAG);
23817 /// performVZEXTCombine - Performs build vector combines
23818 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23819 TargetLowering::DAGCombinerInfo &DCI,
23820 const X86Subtarget *Subtarget) {
23821 // (vzext (bitcast (vzext (x)) -> (vzext x)
23822 SDValue In = N->getOperand(0);
23823 while (In.getOpcode() == ISD::BITCAST)
23824 In = In.getOperand(0);
23826 if (In.getOpcode() != X86ISD::VZEXT)
23829 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23833 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23834 DAGCombinerInfo &DCI) const {
23835 SelectionDAG &DAG = DCI.DAG;
23836 switch (N->getOpcode()) {
23838 case ISD::EXTRACT_VECTOR_ELT:
23839 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23841 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23842 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23843 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23844 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23845 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23846 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23849 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23850 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23851 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23852 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23853 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23854 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23855 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23856 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23857 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23859 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23861 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23862 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23863 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23864 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23865 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23866 case ISD::ANY_EXTEND:
23867 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23868 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23869 case ISD::SIGN_EXTEND_INREG:
23870 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23871 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23872 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23873 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23874 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23875 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23876 case X86ISD::SHUFP: // Handle all target specific shuffles
23877 case X86ISD::PALIGNR:
23878 case X86ISD::UNPCKH:
23879 case X86ISD::UNPCKL:
23880 case X86ISD::MOVHLPS:
23881 case X86ISD::MOVLHPS:
23882 case X86ISD::PSHUFB:
23883 case X86ISD::PSHUFD:
23884 case X86ISD::PSHUFHW:
23885 case X86ISD::PSHUFLW:
23886 case X86ISD::MOVSS:
23887 case X86ISD::MOVSD:
23888 case X86ISD::VPERMILPI:
23889 case X86ISD::VPERM2X128:
23890 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23891 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23892 case ISD::INTRINSIC_WO_CHAIN:
23893 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23894 case X86ISD::INSERTPS:
23895 return PerformINSERTPSCombine(N, DAG, Subtarget);
23896 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23902 /// isTypeDesirableForOp - Return true if the target has native support for
23903 /// the specified value type and it is 'desirable' to use the type for the
23904 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23905 /// instruction encodings are longer and some i16 instructions are slow.
23906 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23907 if (!isTypeLegal(VT))
23909 if (VT != MVT::i16)
23916 case ISD::SIGN_EXTEND:
23917 case ISD::ZERO_EXTEND:
23918 case ISD::ANY_EXTEND:
23931 /// IsDesirableToPromoteOp - This method query the target whether it is
23932 /// beneficial for dag combiner to promote the specified node. If true, it
23933 /// should return the desired promotion type by reference.
23934 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23935 EVT VT = Op.getValueType();
23936 if (VT != MVT::i16)
23939 bool Promote = false;
23940 bool Commute = false;
23941 switch (Op.getOpcode()) {
23944 LoadSDNode *LD = cast<LoadSDNode>(Op);
23945 // If the non-extending load has a single use and it's not live out, then it
23946 // might be folded.
23947 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23948 Op.hasOneUse()*/) {
23949 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23950 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23951 // The only case where we'd want to promote LOAD (rather then it being
23952 // promoted as an operand is when it's only use is liveout.
23953 if (UI->getOpcode() != ISD::CopyToReg)
23960 case ISD::SIGN_EXTEND:
23961 case ISD::ZERO_EXTEND:
23962 case ISD::ANY_EXTEND:
23967 SDValue N0 = Op.getOperand(0);
23968 // Look out for (store (shl (load), x)).
23969 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23982 SDValue N0 = Op.getOperand(0);
23983 SDValue N1 = Op.getOperand(1);
23984 if (!Commute && MayFoldLoad(N1))
23986 // Avoid disabling potential load folding opportunities.
23987 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23989 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23999 //===----------------------------------------------------------------------===//
24000 // X86 Inline Assembly Support
24001 //===----------------------------------------------------------------------===//
24004 // Helper to match a string separated by whitespace.
24005 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24006 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24008 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24009 StringRef piece(*args[i]);
24010 if (!s.startswith(piece)) // Check if the piece matches.
24013 s = s.substr(piece.size());
24014 StringRef::size_type pos = s.find_first_not_of(" \t");
24015 if (pos == 0) // We matched a prefix.
24023 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24026 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24028 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24029 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24030 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24031 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24033 if (AsmPieces.size() == 3)
24035 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24042 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24043 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24045 std::string AsmStr = IA->getAsmString();
24047 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24048 if (!Ty || Ty->getBitWidth() % 16 != 0)
24051 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24052 SmallVector<StringRef, 4> AsmPieces;
24053 SplitString(AsmStr, AsmPieces, ";\n");
24055 switch (AsmPieces.size()) {
24056 default: return false;
24058 // FIXME: this should verify that we are targeting a 486 or better. If not,
24059 // we will turn this bswap into something that will be lowered to logical
24060 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24061 // lower so don't worry about this.
24063 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24064 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24065 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24066 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24067 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24068 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24069 // No need to check constraints, nothing other than the equivalent of
24070 // "=r,0" would be valid here.
24071 return IntrinsicLowering::LowerToByteSwap(CI);
24074 // rorw $$8, ${0:w} --> llvm.bswap.i16
24075 if (CI->getType()->isIntegerTy(16) &&
24076 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24077 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24078 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24080 const std::string &ConstraintsStr = IA->getConstraintString();
24081 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24082 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24083 if (clobbersFlagRegisters(AsmPieces))
24084 return IntrinsicLowering::LowerToByteSwap(CI);
24088 if (CI->getType()->isIntegerTy(32) &&
24089 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24090 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24091 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24092 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24094 const std::string &ConstraintsStr = IA->getConstraintString();
24095 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24096 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24097 if (clobbersFlagRegisters(AsmPieces))
24098 return IntrinsicLowering::LowerToByteSwap(CI);
24101 if (CI->getType()->isIntegerTy(64)) {
24102 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24103 if (Constraints.size() >= 2 &&
24104 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24105 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24106 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24107 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24108 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24109 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24110 return IntrinsicLowering::LowerToByteSwap(CI);
24118 /// getConstraintType - Given a constraint letter, return the type of
24119 /// constraint it is for this target.
24120 X86TargetLowering::ConstraintType
24121 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24122 if (Constraint.size() == 1) {
24123 switch (Constraint[0]) {
24134 return C_RegisterClass;
24158 return TargetLowering::getConstraintType(Constraint);
24161 /// Examine constraint type and operand type and determine a weight value.
24162 /// This object must already have been set up with the operand type
24163 /// and the current alternative constraint selected.
24164 TargetLowering::ConstraintWeight
24165 X86TargetLowering::getSingleConstraintMatchWeight(
24166 AsmOperandInfo &info, const char *constraint) const {
24167 ConstraintWeight weight = CW_Invalid;
24168 Value *CallOperandVal = info.CallOperandVal;
24169 // If we don't have a value, we can't do a match,
24170 // but allow it at the lowest weight.
24171 if (!CallOperandVal)
24173 Type *type = CallOperandVal->getType();
24174 // Look at the constraint type.
24175 switch (*constraint) {
24177 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24188 if (CallOperandVal->getType()->isIntegerTy())
24189 weight = CW_SpecificReg;
24194 if (type->isFloatingPointTy())
24195 weight = CW_SpecificReg;
24198 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24199 weight = CW_SpecificReg;
24203 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24204 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24205 weight = CW_Register;
24208 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24209 if (C->getZExtValue() <= 31)
24210 weight = CW_Constant;
24214 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24215 if (C->getZExtValue() <= 63)
24216 weight = CW_Constant;
24220 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24221 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24222 weight = CW_Constant;
24226 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24227 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24228 weight = CW_Constant;
24232 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24233 if (C->getZExtValue() <= 3)
24234 weight = CW_Constant;
24238 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24239 if (C->getZExtValue() <= 0xff)
24240 weight = CW_Constant;
24245 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24246 weight = CW_Constant;
24250 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24251 if ((C->getSExtValue() >= -0x80000000LL) &&
24252 (C->getSExtValue() <= 0x7fffffffLL))
24253 weight = CW_Constant;
24257 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24258 if (C->getZExtValue() <= 0xffffffff)
24259 weight = CW_Constant;
24266 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24267 /// with another that has more specific requirements based on the type of the
24268 /// corresponding operand.
24269 const char *X86TargetLowering::
24270 LowerXConstraint(EVT ConstraintVT) const {
24271 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24272 // 'f' like normal targets.
24273 if (ConstraintVT.isFloatingPoint()) {
24274 if (Subtarget->hasSSE2())
24276 if (Subtarget->hasSSE1())
24280 return TargetLowering::LowerXConstraint(ConstraintVT);
24283 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24284 /// vector. If it is invalid, don't add anything to Ops.
24285 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24286 std::string &Constraint,
24287 std::vector<SDValue>&Ops,
24288 SelectionDAG &DAG) const {
24291 // Only support length 1 constraints for now.
24292 if (Constraint.length() > 1) return;
24294 char ConstraintLetter = Constraint[0];
24295 switch (ConstraintLetter) {
24298 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24299 if (C->getZExtValue() <= 31) {
24300 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24306 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24307 if (C->getZExtValue() <= 63) {
24308 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24314 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24315 if (isInt<8>(C->getSExtValue())) {
24316 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24323 if (C->getZExtValue() <= 255) {
24324 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24330 // 32-bit signed value
24331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24332 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24333 C->getSExtValue())) {
24334 // Widen to 64 bits here to get it sign extended.
24335 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24338 // FIXME gcc accepts some relocatable values here too, but only in certain
24339 // memory models; it's complicated.
24344 // 32-bit unsigned value
24345 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24346 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24347 C->getZExtValue())) {
24348 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24352 // FIXME gcc accepts some relocatable values here too, but only in certain
24353 // memory models; it's complicated.
24357 // Literal immediates are always ok.
24358 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24359 // Widen to 64 bits here to get it sign extended.
24360 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24364 // In any sort of PIC mode addresses need to be computed at runtime by
24365 // adding in a register or some sort of table lookup. These can't
24366 // be used as immediates.
24367 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24370 // If we are in non-pic codegen mode, we allow the address of a global (with
24371 // an optional displacement) to be used with 'i'.
24372 GlobalAddressSDNode *GA = nullptr;
24373 int64_t Offset = 0;
24375 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24377 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24378 Offset += GA->getOffset();
24380 } else if (Op.getOpcode() == ISD::ADD) {
24381 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24382 Offset += C->getZExtValue();
24383 Op = Op.getOperand(0);
24386 } else if (Op.getOpcode() == ISD::SUB) {
24387 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24388 Offset += -C->getZExtValue();
24389 Op = Op.getOperand(0);
24394 // Otherwise, this isn't something we can handle, reject it.
24398 const GlobalValue *GV = GA->getGlobal();
24399 // If we require an extra load to get this address, as in PIC mode, we
24400 // can't accept it.
24401 if (isGlobalStubReference(
24402 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24405 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24406 GA->getValueType(0), Offset);
24411 if (Result.getNode()) {
24412 Ops.push_back(Result);
24415 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24418 std::pair<unsigned, const TargetRegisterClass*>
24419 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24421 // First, see if this is a constraint that directly corresponds to an LLVM
24423 if (Constraint.size() == 1) {
24424 // GCC Constraint Letters
24425 switch (Constraint[0]) {
24427 // TODO: Slight differences here in allocation order and leaving
24428 // RIP in the class. Do they matter any more here than they do
24429 // in the normal allocation?
24430 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24431 if (Subtarget->is64Bit()) {
24432 if (VT == MVT::i32 || VT == MVT::f32)
24433 return std::make_pair(0U, &X86::GR32RegClass);
24434 if (VT == MVT::i16)
24435 return std::make_pair(0U, &X86::GR16RegClass);
24436 if (VT == MVT::i8 || VT == MVT::i1)
24437 return std::make_pair(0U, &X86::GR8RegClass);
24438 if (VT == MVT::i64 || VT == MVT::f64)
24439 return std::make_pair(0U, &X86::GR64RegClass);
24442 // 32-bit fallthrough
24443 case 'Q': // Q_REGS
24444 if (VT == MVT::i32 || VT == MVT::f32)
24445 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24446 if (VT == MVT::i16)
24447 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24448 if (VT == MVT::i8 || VT == MVT::i1)
24449 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24450 if (VT == MVT::i64)
24451 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24453 case 'r': // GENERAL_REGS
24454 case 'l': // INDEX_REGS
24455 if (VT == MVT::i8 || VT == MVT::i1)
24456 return std::make_pair(0U, &X86::GR8RegClass);
24457 if (VT == MVT::i16)
24458 return std::make_pair(0U, &X86::GR16RegClass);
24459 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24460 return std::make_pair(0U, &X86::GR32RegClass);
24461 return std::make_pair(0U, &X86::GR64RegClass);
24462 case 'R': // LEGACY_REGS
24463 if (VT == MVT::i8 || VT == MVT::i1)
24464 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24465 if (VT == MVT::i16)
24466 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24467 if (VT == MVT::i32 || !Subtarget->is64Bit())
24468 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24469 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24470 case 'f': // FP Stack registers.
24471 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24472 // value to the correct fpstack register class.
24473 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24474 return std::make_pair(0U, &X86::RFP32RegClass);
24475 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24476 return std::make_pair(0U, &X86::RFP64RegClass);
24477 return std::make_pair(0U, &X86::RFP80RegClass);
24478 case 'y': // MMX_REGS if MMX allowed.
24479 if (!Subtarget->hasMMX()) break;
24480 return std::make_pair(0U, &X86::VR64RegClass);
24481 case 'Y': // SSE_REGS if SSE2 allowed
24482 if (!Subtarget->hasSSE2()) break;
24484 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24485 if (!Subtarget->hasSSE1()) break;
24487 switch (VT.SimpleTy) {
24489 // Scalar SSE types.
24492 return std::make_pair(0U, &X86::FR32RegClass);
24495 return std::make_pair(0U, &X86::FR64RegClass);
24503 return std::make_pair(0U, &X86::VR128RegClass);
24511 return std::make_pair(0U, &X86::VR256RegClass);
24516 return std::make_pair(0U, &X86::VR512RegClass);
24522 // Use the default implementation in TargetLowering to convert the register
24523 // constraint into a member of a register class.
24524 std::pair<unsigned, const TargetRegisterClass*> Res;
24525 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24527 // Not found as a standard register?
24529 // Map st(0) -> st(7) -> ST0
24530 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24531 tolower(Constraint[1]) == 's' &&
24532 tolower(Constraint[2]) == 't' &&
24533 Constraint[3] == '(' &&
24534 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24535 Constraint[5] == ')' &&
24536 Constraint[6] == '}') {
24538 Res.first = X86::FP0+Constraint[4]-'0';
24539 Res.second = &X86::RFP80RegClass;
24543 // GCC allows "st(0)" to be called just plain "st".
24544 if (StringRef("{st}").equals_lower(Constraint)) {
24545 Res.first = X86::FP0;
24546 Res.second = &X86::RFP80RegClass;
24551 if (StringRef("{flags}").equals_lower(Constraint)) {
24552 Res.first = X86::EFLAGS;
24553 Res.second = &X86::CCRRegClass;
24557 // 'A' means EAX + EDX.
24558 if (Constraint == "A") {
24559 Res.first = X86::EAX;
24560 Res.second = &X86::GR32_ADRegClass;
24566 // Otherwise, check to see if this is a register class of the wrong value
24567 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24568 // turn into {ax},{dx}.
24569 if (Res.second->hasType(VT))
24570 return Res; // Correct type already, nothing to do.
24572 // All of the single-register GCC register classes map their values onto
24573 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24574 // really want an 8-bit or 32-bit register, map to the appropriate register
24575 // class and return the appropriate register.
24576 if (Res.second == &X86::GR16RegClass) {
24577 if (VT == MVT::i8 || VT == MVT::i1) {
24578 unsigned DestReg = 0;
24579 switch (Res.first) {
24581 case X86::AX: DestReg = X86::AL; break;
24582 case X86::DX: DestReg = X86::DL; break;
24583 case X86::CX: DestReg = X86::CL; break;
24584 case X86::BX: DestReg = X86::BL; break;
24587 Res.first = DestReg;
24588 Res.second = &X86::GR8RegClass;
24590 } else if (VT == MVT::i32 || VT == MVT::f32) {
24591 unsigned DestReg = 0;
24592 switch (Res.first) {
24594 case X86::AX: DestReg = X86::EAX; break;
24595 case X86::DX: DestReg = X86::EDX; break;
24596 case X86::CX: DestReg = X86::ECX; break;
24597 case X86::BX: DestReg = X86::EBX; break;
24598 case X86::SI: DestReg = X86::ESI; break;
24599 case X86::DI: DestReg = X86::EDI; break;
24600 case X86::BP: DestReg = X86::EBP; break;
24601 case X86::SP: DestReg = X86::ESP; break;
24604 Res.first = DestReg;
24605 Res.second = &X86::GR32RegClass;
24607 } else if (VT == MVT::i64 || VT == MVT::f64) {
24608 unsigned DestReg = 0;
24609 switch (Res.first) {
24611 case X86::AX: DestReg = X86::RAX; break;
24612 case X86::DX: DestReg = X86::RDX; break;
24613 case X86::CX: DestReg = X86::RCX; break;
24614 case X86::BX: DestReg = X86::RBX; break;
24615 case X86::SI: DestReg = X86::RSI; break;
24616 case X86::DI: DestReg = X86::RDI; break;
24617 case X86::BP: DestReg = X86::RBP; break;
24618 case X86::SP: DestReg = X86::RSP; break;
24621 Res.first = DestReg;
24622 Res.second = &X86::GR64RegClass;
24625 } else if (Res.second == &X86::FR32RegClass ||
24626 Res.second == &X86::FR64RegClass ||
24627 Res.second == &X86::VR128RegClass ||
24628 Res.second == &X86::VR256RegClass ||
24629 Res.second == &X86::FR32XRegClass ||
24630 Res.second == &X86::FR64XRegClass ||
24631 Res.second == &X86::VR128XRegClass ||
24632 Res.second == &X86::VR256XRegClass ||
24633 Res.second == &X86::VR512RegClass) {
24634 // Handle references to XMM physical registers that got mapped into the
24635 // wrong class. This can happen with constraints like {xmm0} where the
24636 // target independent register mapper will just pick the first match it can
24637 // find, ignoring the required type.
24639 if (VT == MVT::f32 || VT == MVT::i32)
24640 Res.second = &X86::FR32RegClass;
24641 else if (VT == MVT::f64 || VT == MVT::i64)
24642 Res.second = &X86::FR64RegClass;
24643 else if (X86::VR128RegClass.hasType(VT))
24644 Res.second = &X86::VR128RegClass;
24645 else if (X86::VR256RegClass.hasType(VT))
24646 Res.second = &X86::VR256RegClass;
24647 else if (X86::VR512RegClass.hasType(VT))
24648 Res.second = &X86::VR512RegClass;
24654 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24656 // Scaling factors are not free at all.
24657 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24658 // will take 2 allocations in the out of order engine instead of 1
24659 // for plain addressing mode, i.e. inst (reg1).
24661 // vaddps (%rsi,%drx), %ymm0, %ymm1
24662 // Requires two allocations (one for the load, one for the computation)
24664 // vaddps (%rsi), %ymm0, %ymm1
24665 // Requires just 1 allocation, i.e., freeing allocations for other operations
24666 // and having less micro operations to execute.
24668 // For some X86 architectures, this is even worse because for instance for
24669 // stores, the complex addressing mode forces the instruction to use the
24670 // "load" ports instead of the dedicated "store" port.
24671 // E.g., on Haswell:
24672 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24673 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24674 if (isLegalAddressingMode(AM, Ty))
24675 // Scale represents reg2 * scale, thus account for 1
24676 // as soon as we use a second register.
24677 return AM.Scale != 0;
24681 bool X86TargetLowering::isTargetFTOL() const {
24682 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();