1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!TM.Options.UseSoftFloat) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!TM.Options.UseSoftFloat) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!TM.Options.UseSoftFloat) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, &X86::FR32RegClass);
520 addRegisterClass(MVT::f64, &X86::FR64RegClass);
522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS , MVT::f64, Custom);
524 setOperationAction(ISD::FABS , MVT::f32, Custom);
526 // Use XORP to simulate FNEG.
527 setOperationAction(ISD::FNEG , MVT::f64, Custom);
528 setOperationAction(ISD::FNEG , MVT::f32, Custom);
530 // Use ANDPD and ORPD to simulate FCOPYSIGN.
531 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
532 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
534 // Lower this to FGETSIGNx86 plus an AND.
535 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
536 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
538 // We don't support sin/cos/fmod
539 setOperationAction(ISD::FSIN , MVT::f64, Expand);
540 setOperationAction(ISD::FCOS , MVT::f64, Expand);
541 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
542 setOperationAction(ISD::FSIN , MVT::f32, Expand);
543 setOperationAction(ISD::FCOS , MVT::f32, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
546 // Expand FP immediates into loads from the stack, except for the special
548 addLegalFPImmediate(APFloat(+0.0)); // xorpd
549 addLegalFPImmediate(APFloat(+0.0f)); // xorps
550 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
551 // Use SSE for f32, x87 for f64.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, &X86::FR32RegClass);
554 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
556 // Use ANDPS to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f32, Custom);
559 // Use XORP to simulate FNEG.
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
564 // Use ANDPS and ORPS to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // We don't support sin/cos/fmod
569 setOperationAction(ISD::FSIN , MVT::f32, Expand);
570 setOperationAction(ISD::FCOS , MVT::f32, Expand);
571 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
573 // Special cases we handle for FP constants.
574 addLegalFPImmediate(APFloat(+0.0f)); // xorps
575 addLegalFPImmediate(APFloat(+0.0)); // FLD0
576 addLegalFPImmediate(APFloat(+1.0)); // FLD1
577 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
578 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
580 if (!TM.Options.UnsafeFPMath) {
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
585 } else if (!TM.Options.UseSoftFloat) {
586 // f32 and f64 in x87.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
596 if (!TM.Options.UnsafeFPMath) {
597 setOperationAction(ISD::FSIN , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f64, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
608 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 // Long double always uses X87.
619 if (!TM.Options.UseSoftFloat) {
620 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
621 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
625 addLegalFPImmediate(TmpFlt); // FLD0
627 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630 APFloat TmpFlt2(+1.0);
631 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
633 addLegalFPImmediate(TmpFlt2); // FLD1
634 TmpFlt2.changeSign();
635 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f80, Expand);
640 setOperationAction(ISD::FCOS , MVT::f80, Expand);
641 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665 // First set operation action for all vector types to either promote
666 // (for widening) or expand (for scalarization). Then we will selectively
667 // turn on ones that can be effectively codegen'd.
668 for (MVT VT : MVT::vector_valuetypes()) {
669 setOperationAction(ISD::ADD , VT, Expand);
670 setOperationAction(ISD::SUB , VT, Expand);
671 setOperationAction(ISD::FADD, VT, Expand);
672 setOperationAction(ISD::FNEG, VT, Expand);
673 setOperationAction(ISD::FSUB, VT, Expand);
674 setOperationAction(ISD::MUL , VT, Expand);
675 setOperationAction(ISD::FMUL, VT, Expand);
676 setOperationAction(ISD::SDIV, VT, Expand);
677 setOperationAction(ISD::UDIV, VT, Expand);
678 setOperationAction(ISD::FDIV, VT, Expand);
679 setOperationAction(ISD::SREM, VT, Expand);
680 setOperationAction(ISD::UREM, VT, Expand);
681 setOperationAction(ISD::LOAD, VT, Expand);
682 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::FABS, VT, Expand);
688 setOperationAction(ISD::FSIN, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FCOS, VT, Expand);
691 setOperationAction(ISD::FSINCOS, VT, Expand);
692 setOperationAction(ISD::FREM, VT, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FPOWI, VT, Expand);
695 setOperationAction(ISD::FSQRT, VT, Expand);
696 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
697 setOperationAction(ISD::FFLOOR, VT, Expand);
698 setOperationAction(ISD::FCEIL, VT, Expand);
699 setOperationAction(ISD::FTRUNC, VT, Expand);
700 setOperationAction(ISD::FRINT, VT, Expand);
701 setOperationAction(ISD::FNEARBYINT, VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHS, VT, Expand);
704 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
705 setOperationAction(ISD::MULHU, VT, Expand);
706 setOperationAction(ISD::SDIVREM, VT, Expand);
707 setOperationAction(ISD::UDIVREM, VT, Expand);
708 setOperationAction(ISD::FPOW, VT, Expand);
709 setOperationAction(ISD::CTPOP, VT, Expand);
710 setOperationAction(ISD::CTTZ, VT, Expand);
711 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::CTLZ, VT, Expand);
713 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
714 setOperationAction(ISD::SHL, VT, Expand);
715 setOperationAction(ISD::SRA, VT, Expand);
716 setOperationAction(ISD::SRL, VT, Expand);
717 setOperationAction(ISD::ROTL, VT, Expand);
718 setOperationAction(ISD::ROTR, VT, Expand);
719 setOperationAction(ISD::BSWAP, VT, Expand);
720 setOperationAction(ISD::SETCC, VT, Expand);
721 setOperationAction(ISD::FLOG, VT, Expand);
722 setOperationAction(ISD::FLOG2, VT, Expand);
723 setOperationAction(ISD::FLOG10, VT, Expand);
724 setOperationAction(ISD::FEXP, VT, Expand);
725 setOperationAction(ISD::FEXP2, VT, Expand);
726 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
728 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
731 setOperationAction(ISD::TRUNCATE, VT, Expand);
732 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
733 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
734 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
735 setOperationAction(ISD::VSELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 for (MVT InnerVT : MVT::vector_valuetypes()) {
738 setTruncStoreAction(InnerVT, VT, Expand);
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
741 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
743 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
744 // types, we have to deal with them whether we ask for Expansion or not.
745 // Setting Expand causes its own optimisation problems though, so leave
747 if (VT.getVectorElementType() == MVT::i1)
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
752 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
753 // with -msoft-float, disable use of MMX as well.
754 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
755 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
756 // No operations on x86mmx supported, everything uses intrinsics.
759 // MMX-sized vectors (other than x86mmx) are expected to be expanded
760 // into smaller operations.
761 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
762 setOperationAction(ISD::MULHS, MMXTy, Expand);
763 setOperationAction(ISD::AND, MMXTy, Expand);
764 setOperationAction(ISD::OR, MMXTy, Expand);
765 setOperationAction(ISD::XOR, MMXTy, Expand);
766 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
767 setOperationAction(ISD::SELECT, MMXTy, Expand);
768 setOperationAction(ISD::BITCAST, MMXTy, Expand);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
772 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
773 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
775 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
776 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
777 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
778 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
780 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
781 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
782 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
783 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
785 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
787 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
788 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
791 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
792 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
794 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
795 // registers cannot be used even for integer operations.
796 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
797 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
798 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
799 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
801 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
802 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
803 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
804 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
805 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
806 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
807 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
808 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
809 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
810 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
811 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
812 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
813 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
814 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
815 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
816 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
817 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
818 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
819 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
820 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
821 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
822 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
824 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
825 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
826 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
827 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
831 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
835 // Only provide customized ctpop vector bit twiddling for vector types we
836 // know to perform better than using the popcnt instructions on each vector
837 // element. If popcnt isn't supported, always provide the custom version.
838 if (!Subtarget->hasPOPCNT()) {
839 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
840 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
843 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
844 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
845 MVT VT = (MVT::SimpleValueType)i;
846 // Do not attempt to custom lower non-power-of-2 vectors
847 if (!isPowerOf2_32(VT.getVectorNumElements()))
849 // Do not attempt to custom lower non-128-bit vectors
850 if (!VT.is128BitVector())
852 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
853 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
854 setOperationAction(ISD::VSELECT, VT, Custom);
855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
858 // We support custom legalizing of sext and anyext loads for specific
859 // memory vector types which we can load as a scalar (or sequence of
860 // scalars) and extend in-register to a legal 128-bit vector type. For sext
861 // loads these must work with a single scalar load.
862 for (MVT VT : MVT::integer_vector_valuetypes()) {
863 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
864 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
866 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
867 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
874 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
875 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
876 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
878 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
879 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
880 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
881 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
883 if (Subtarget->is64Bit()) {
884 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
888 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
889 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
890 MVT VT = (MVT::SimpleValueType)i;
892 // Do not attempt to promote non-128-bit vectors
893 if (!VT.is128BitVector())
896 setOperationAction(ISD::AND, VT, Promote);
897 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
898 setOperationAction(ISD::OR, VT, Promote);
899 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
900 setOperationAction(ISD::XOR, VT, Promote);
901 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
902 setOperationAction(ISD::LOAD, VT, Promote);
903 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
904 setOperationAction(ISD::SELECT, VT, Promote);
905 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
908 // Custom lower v2i64 and v2f64 selects.
909 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
910 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
911 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
912 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
914 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
915 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
917 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
918 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
919 // As there is no 64-bit GPR available, we need build a special custom
920 // sequence to convert from v2i32 to v2f32.
921 if (!Subtarget->is64Bit())
922 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
924 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
925 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
927 for (MVT VT : MVT::fp_vector_valuetypes())
928 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
930 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
931 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
932 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
935 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
936 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
937 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
938 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
939 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
940 setOperationAction(ISD::FRINT, RoundedTy, Legal);
941 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
944 // FIXME: Do we need to handle scalar-to-vector here?
945 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
947 // We directly match byte blends in the backend as they match the VSELECT
949 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
951 // SSE41 brings specific instructions for doing vector sign extend even in
952 // cases where we don't have SRA.
953 for (MVT VT : MVT::integer_vector_valuetypes()) {
954 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
955 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
956 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
959 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
960 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
961 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
962 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
963 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
964 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
967 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
968 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
969 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
970 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
971 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
972 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
974 // i8 and i16 vectors are custom because the source register and source
975 // source memory operand types are not the same width. f32 vectors are
976 // custom since the immediate controlling the insert encodes additional
978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
983 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
984 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
985 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
988 // FIXME: these should be Legal, but that's only for the case where
989 // the index is constant. For now custom expand to deal with that.
990 if (Subtarget->is64Bit()) {
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
996 if (Subtarget->hasSSE2()) {
997 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
998 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1000 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1001 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1003 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1004 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1006 // In the customized shift lowering, the legal cases in AVX2 will be
1008 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1009 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1011 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1012 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1014 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1017 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1018 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1019 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1020 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1021 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1022 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1023 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1025 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1026 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1027 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1029 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1032 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1033 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1034 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1035 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1036 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1037 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1040 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1043 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1044 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1045 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1046 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1047 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1048 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1049 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1051 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1052 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1053 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1055 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1056 // even though v8i16 is a legal type.
1057 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1058 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1061 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1062 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1063 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1065 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1066 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1068 for (MVT VT : MVT::fp_vector_valuetypes())
1069 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1071 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1072 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1074 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1075 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1077 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1078 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1080 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1081 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1082 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1083 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1085 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1086 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1087 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1089 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1090 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1091 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1092 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1093 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1094 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1095 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1098 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1099 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1100 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1102 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1103 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1104 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1105 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FMA, MVT::f32, Legal);
1108 setOperationAction(ISD::FMA, MVT::f64, Legal);
1111 if (Subtarget->hasInt256()) {
1112 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1113 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1114 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1115 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1117 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1118 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1119 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1120 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1122 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1123 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1124 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1125 // Don't lower v32i8 because there is no 128-bit byte mul
1127 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1128 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1129 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1130 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1132 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1133 // when we have a 256bit-wide blend with immediate.
1134 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1136 // Only provide customized ctpop vector bit twiddling for vector types we
1137 // know to perform better than using the popcnt instructions on each
1138 // vector element. If popcnt isn't supported, always provide the custom
1140 if (!Subtarget->hasPOPCNT())
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 // Custom CTPOP always performs better on natively supported v8i32
1144 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1146 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1147 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1148 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1149 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1150 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1151 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1152 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1154 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1155 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1156 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1157 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1158 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1159 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1161 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1174 // Don't lower v32i8 because there is no 128-bit byte mul
1177 // In the customized shift lowering, the legal cases in AVX2 will be
1179 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1180 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1182 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1185 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1187 // Custom lower several nodes for 256-bit types.
1188 for (MVT VT : MVT::vector_valuetypes()) {
1189 if (VT.getScalarSizeInBits() >= 32) {
1190 setOperationAction(ISD::MLOAD, VT, Legal);
1191 setOperationAction(ISD::MSTORE, VT, Legal);
1193 // Extract subvector is special because the value type
1194 // (result) is 128-bit but the source is 256-bit wide.
1195 if (VT.is128BitVector()) {
1196 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1198 // Do not attempt to custom lower other non-256-bit vectors
1199 if (!VT.is256BitVector())
1202 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1203 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1204 setOperationAction(ISD::VSELECT, VT, Custom);
1205 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1206 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1207 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1208 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1209 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1212 if (Subtarget->hasInt256())
1213 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1216 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1217 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1218 MVT VT = (MVT::SimpleValueType)i;
1220 // Do not attempt to promote non-256-bit vectors
1221 if (!VT.is256BitVector())
1224 setOperationAction(ISD::AND, VT, Promote);
1225 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1226 setOperationAction(ISD::OR, VT, Promote);
1227 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1228 setOperationAction(ISD::XOR, VT, Promote);
1229 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1230 setOperationAction(ISD::LOAD, VT, Promote);
1231 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1232 setOperationAction(ISD::SELECT, VT, Promote);
1233 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1237 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1238 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1239 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1240 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1241 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1243 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1244 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1245 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1247 for (MVT VT : MVT::fp_vector_valuetypes())
1248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1250 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1251 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1252 setOperationAction(ISD::XOR, MVT::i1, Legal);
1253 setOperationAction(ISD::OR, MVT::i1, Legal);
1254 setOperationAction(ISD::AND, MVT::i1, Legal);
1255 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1256 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1257 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1258 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1259 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1261 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1262 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1263 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1264 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1265 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1266 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1268 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1269 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1270 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1271 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1272 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1273 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1274 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1275 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1277 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1278 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1279 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1280 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1281 if (Subtarget->is64Bit()) {
1282 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1283 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1284 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1285 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1287 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1288 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1289 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1290 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1291 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1292 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1293 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1294 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1295 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1296 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1297 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1298 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1299 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1300 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1302 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1303 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1304 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1305 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1306 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1307 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1308 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1309 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1310 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1311 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1312 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1313 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1314 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1316 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1318 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1320 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1322 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1323 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1327 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1328 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1329 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1330 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1331 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1333 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1334 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1339 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1340 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1341 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1342 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1343 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1344 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1345 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1346 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1348 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1349 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1351 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1352 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1354 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1356 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1357 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1359 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1360 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1362 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1363 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1365 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1366 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1367 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1368 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1369 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1370 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1372 if (Subtarget->hasCDI()) {
1373 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1374 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1376 if (Subtarget->hasDQI()) {
1377 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1378 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1379 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1381 // Custom lower several nodes.
1382 for (MVT VT : MVT::vector_valuetypes()) {
1383 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1384 // Extract subvector is special because the value type
1385 // (result) is 256/128-bit but the source is 512-bit wide.
1386 if (VT.is128BitVector() || VT.is256BitVector()) {
1387 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1389 if (VT.getVectorElementType() == MVT::i1)
1390 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1392 // Do not attempt to custom lower other non-512-bit vectors
1393 if (!VT.is512BitVector())
1396 if ( EltSize >= 32) {
1397 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1398 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1399 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1400 setOperationAction(ISD::VSELECT, VT, Legal);
1401 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1402 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1403 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1404 setOperationAction(ISD::MLOAD, VT, Legal);
1405 setOperationAction(ISD::MSTORE, VT, Legal);
1408 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1409 MVT VT = (MVT::SimpleValueType)i;
1411 // Do not attempt to promote non-512-bit vectors.
1412 if (!VT.is512BitVector())
1415 setOperationAction(ISD::SELECT, VT, Promote);
1416 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1420 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1421 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1422 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1424 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1425 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1427 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1428 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1429 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1430 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1431 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1432 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1433 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1434 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1435 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1436 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1438 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1439 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1441 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1442 const MVT VT = (MVT::SimpleValueType)i;
1444 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1446 // Do not attempt to promote non-512-bit vectors.
1447 if (!VT.is512BitVector())
1451 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1452 setOperationAction(ISD::VSELECT, VT, Legal);
1457 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1458 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1459 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1461 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1463 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1464 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1465 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1466 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1468 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1469 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1470 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1471 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1472 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1473 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1476 // We want to custom lower some of our intrinsics.
1477 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1478 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1479 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1480 if (!Subtarget->is64Bit())
1481 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1483 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1484 // handle type legalization for these operations here.
1486 // FIXME: We really should do custom legalization for addition and
1487 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1488 // than generic legalization for 64-bit multiplication-with-overflow, though.
1489 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1490 // Add/Sub/Mul with overflow operations are custom lowered.
1492 setOperationAction(ISD::SADDO, VT, Custom);
1493 setOperationAction(ISD::UADDO, VT, Custom);
1494 setOperationAction(ISD::SSUBO, VT, Custom);
1495 setOperationAction(ISD::USUBO, VT, Custom);
1496 setOperationAction(ISD::SMULO, VT, Custom);
1497 setOperationAction(ISD::UMULO, VT, Custom);
1501 if (!Subtarget->is64Bit()) {
1502 // These libcalls are not available in 32-bit.
1503 setLibcallName(RTLIB::SHL_I128, nullptr);
1504 setLibcallName(RTLIB::SRL_I128, nullptr);
1505 setLibcallName(RTLIB::SRA_I128, nullptr);
1508 // Combine sin / cos into one node or libcall if possible.
1509 if (Subtarget->hasSinCos()) {
1510 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1511 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1512 if (Subtarget->isTargetDarwin()) {
1513 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1514 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1515 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1516 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1520 if (Subtarget->isTargetWin64()) {
1521 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1522 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1523 setOperationAction(ISD::SREM, MVT::i128, Custom);
1524 setOperationAction(ISD::UREM, MVT::i128, Custom);
1525 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1526 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1529 // We have target-specific dag combine patterns for the following nodes:
1530 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1531 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1532 setTargetDAGCombine(ISD::BITCAST);
1533 setTargetDAGCombine(ISD::VSELECT);
1534 setTargetDAGCombine(ISD::SELECT);
1535 setTargetDAGCombine(ISD::SHL);
1536 setTargetDAGCombine(ISD::SRA);
1537 setTargetDAGCombine(ISD::SRL);
1538 setTargetDAGCombine(ISD::OR);
1539 setTargetDAGCombine(ISD::AND);
1540 setTargetDAGCombine(ISD::ADD);
1541 setTargetDAGCombine(ISD::FADD);
1542 setTargetDAGCombine(ISD::FSUB);
1543 setTargetDAGCombine(ISD::FMA);
1544 setTargetDAGCombine(ISD::SUB);
1545 setTargetDAGCombine(ISD::LOAD);
1546 setTargetDAGCombine(ISD::MLOAD);
1547 setTargetDAGCombine(ISD::STORE);
1548 setTargetDAGCombine(ISD::MSTORE);
1549 setTargetDAGCombine(ISD::ZERO_EXTEND);
1550 setTargetDAGCombine(ISD::ANY_EXTEND);
1551 setTargetDAGCombine(ISD::SIGN_EXTEND);
1552 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1553 setTargetDAGCombine(ISD::TRUNCATE);
1554 setTargetDAGCombine(ISD::SINT_TO_FP);
1555 setTargetDAGCombine(ISD::SETCC);
1556 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1557 setTargetDAGCombine(ISD::BUILD_VECTOR);
1558 setTargetDAGCombine(ISD::MUL);
1559 setTargetDAGCombine(ISD::XOR);
1561 computeRegisterProperties(Subtarget->getRegisterInfo());
1563 // On Darwin, -Os means optimize for size without hurting performance,
1564 // do not reduce the limit.
1565 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1566 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1567 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1568 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1569 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1570 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1571 setPrefLoopAlignment(4); // 2^4 bytes.
1573 // Predictable cmov don't hurt on atom because it's in-order.
1574 PredictableSelectIsExpensive = !Subtarget->isAtom();
1575 EnableExtLdPromotion = true;
1576 setPrefFunctionAlignment(4); // 2^4 bytes.
1578 verifyIntrinsicTables();
1581 // This has so far only been implemented for 64-bit MachO.
1582 bool X86TargetLowering::useLoadStackGuardNode() const {
1583 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1586 TargetLoweringBase::LegalizeTypeAction
1587 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1588 if (ExperimentalVectorWideningLegalization &&
1589 VT.getVectorNumElements() != 1 &&
1590 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1591 return TypeWidenVector;
1593 return TargetLoweringBase::getPreferredVectorAction(VT);
1596 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1598 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1600 const unsigned NumElts = VT.getVectorNumElements();
1601 const EVT EltVT = VT.getVectorElementType();
1602 if (VT.is512BitVector()) {
1603 if (Subtarget->hasAVX512())
1604 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1605 EltVT == MVT::f32 || EltVT == MVT::f64)
1607 case 8: return MVT::v8i1;
1608 case 16: return MVT::v16i1;
1610 if (Subtarget->hasBWI())
1611 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1613 case 32: return MVT::v32i1;
1614 case 64: return MVT::v64i1;
1618 if (VT.is256BitVector() || VT.is128BitVector()) {
1619 if (Subtarget->hasVLX())
1620 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1621 EltVT == MVT::f32 || EltVT == MVT::f64)
1623 case 2: return MVT::v2i1;
1624 case 4: return MVT::v4i1;
1625 case 8: return MVT::v8i1;
1627 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1628 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1630 case 8: return MVT::v8i1;
1631 case 16: return MVT::v16i1;
1632 case 32: return MVT::v32i1;
1636 return VT.changeVectorElementTypeToInteger();
1639 /// Helper for getByValTypeAlignment to determine
1640 /// the desired ByVal argument alignment.
1641 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1644 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1645 if (VTy->getBitWidth() == 128)
1647 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1648 unsigned EltAlign = 0;
1649 getMaxByValAlign(ATy->getElementType(), EltAlign);
1650 if (EltAlign > MaxAlign)
1651 MaxAlign = EltAlign;
1652 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1653 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1654 unsigned EltAlign = 0;
1655 getMaxByValAlign(STy->getElementType(i), EltAlign);
1656 if (EltAlign > MaxAlign)
1657 MaxAlign = EltAlign;
1664 /// Return the desired alignment for ByVal aggregate
1665 /// function arguments in the caller parameter area. For X86, aggregates
1666 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1667 /// are at 4-byte boundaries.
1668 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1669 if (Subtarget->is64Bit()) {
1670 // Max of 8 and alignment of type.
1671 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1678 if (Subtarget->hasSSE1())
1679 getMaxByValAlign(Ty, Align);
1683 /// Returns the target specific optimal type for load
1684 /// and store operations as a result of memset, memcpy, and memmove
1685 /// lowering. If DstAlign is zero that means it's safe to destination
1686 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1687 /// means there isn't a need to check it against alignment requirement,
1688 /// probably because the source does not need to be loaded. If 'IsMemset' is
1689 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1690 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1691 /// source is constant so it does not need to be loaded.
1692 /// It returns EVT::Other if the type should be determined using generic
1693 /// target-independent logic.
1695 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1696 unsigned DstAlign, unsigned SrcAlign,
1697 bool IsMemset, bool ZeroMemset,
1699 MachineFunction &MF) const {
1700 const Function *F = MF.getFunction();
1701 if ((!IsMemset || ZeroMemset) &&
1702 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1704 (Subtarget->isUnalignedMemAccessFast() ||
1705 ((DstAlign == 0 || DstAlign >= 16) &&
1706 (SrcAlign == 0 || SrcAlign >= 16)))) {
1708 if (Subtarget->hasInt256())
1710 if (Subtarget->hasFp256())
1713 if (Subtarget->hasSSE2())
1715 if (Subtarget->hasSSE1())
1717 } else if (!MemcpyStrSrc && Size >= 8 &&
1718 !Subtarget->is64Bit() &&
1719 Subtarget->hasSSE2()) {
1720 // Do not use f64 to lower memcpy if source is string constant. It's
1721 // better to use i32 to avoid the loads.
1725 if (Subtarget->is64Bit() && Size >= 8)
1730 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1732 return X86ScalarSSEf32;
1733 else if (VT == MVT::f64)
1734 return X86ScalarSSEf64;
1739 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1744 *Fast = Subtarget->isUnalignedMemAccessFast();
1748 /// Return the entry encoding for a jump table in the
1749 /// current function. The returned value is a member of the
1750 /// MachineJumpTableInfo::JTEntryKind enum.
1751 unsigned X86TargetLowering::getJumpTableEncoding() const {
1752 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1754 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1755 Subtarget->isPICStyleGOT())
1756 return MachineJumpTableInfo::EK_Custom32;
1758 // Otherwise, use the normal jump table encoding heuristics.
1759 return TargetLowering::getJumpTableEncoding();
1763 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1764 const MachineBasicBlock *MBB,
1765 unsigned uid,MCContext &Ctx) const{
1766 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1767 Subtarget->isPICStyleGOT());
1768 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1770 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1771 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1774 /// Returns relocation base for the given PIC jumptable.
1775 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1776 SelectionDAG &DAG) const {
1777 if (!Subtarget->is64Bit())
1778 // This doesn't have SDLoc associated with it, but is not really the
1779 // same as a Register.
1780 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1784 /// This returns the relocation base for the given PIC jumptable,
1785 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1786 const MCExpr *X86TargetLowering::
1787 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1788 MCContext &Ctx) const {
1789 // X86-64 uses RIP relative addressing based on the jump table label.
1790 if (Subtarget->isPICStyleRIPRel())
1791 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1793 // Otherwise, the reference is relative to the PIC base.
1794 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1797 std::pair<const TargetRegisterClass *, uint8_t>
1798 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1800 const TargetRegisterClass *RRC = nullptr;
1802 switch (VT.SimpleTy) {
1804 return TargetLowering::findRepresentativeClass(TRI, VT);
1805 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1806 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1809 RRC = &X86::VR64RegClass;
1811 case MVT::f32: case MVT::f64:
1812 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1813 case MVT::v4f32: case MVT::v2f64:
1814 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1816 RRC = &X86::VR128RegClass;
1819 return std::make_pair(RRC, Cost);
1822 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1823 unsigned &Offset) const {
1824 if (!Subtarget->isTargetLinux())
1827 if (Subtarget->is64Bit()) {
1828 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1830 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1842 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1843 unsigned DestAS) const {
1844 assert(SrcAS != DestAS && "Expected different address spaces!");
1846 return SrcAS < 256 && DestAS < 256;
1849 //===----------------------------------------------------------------------===//
1850 // Return Value Calling Convention Implementation
1851 //===----------------------------------------------------------------------===//
1853 #include "X86GenCallingConv.inc"
1856 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1857 MachineFunction &MF, bool isVarArg,
1858 const SmallVectorImpl<ISD::OutputArg> &Outs,
1859 LLVMContext &Context) const {
1860 SmallVector<CCValAssign, 16> RVLocs;
1861 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1862 return CCInfo.CheckReturn(Outs, RetCC_X86);
1865 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1866 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1871 X86TargetLowering::LowerReturn(SDValue Chain,
1872 CallingConv::ID CallConv, bool isVarArg,
1873 const SmallVectorImpl<ISD::OutputArg> &Outs,
1874 const SmallVectorImpl<SDValue> &OutVals,
1875 SDLoc dl, SelectionDAG &DAG) const {
1876 MachineFunction &MF = DAG.getMachineFunction();
1877 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1879 SmallVector<CCValAssign, 16> RVLocs;
1880 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1881 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1884 SmallVector<SDValue, 6> RetOps;
1885 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1886 // Operand #1 = Bytes To Pop
1887 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1890 // Copy the result values into the output registers.
1891 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1892 CCValAssign &VA = RVLocs[i];
1893 assert(VA.isRegLoc() && "Can only return in registers!");
1894 SDValue ValToCopy = OutVals[i];
1895 EVT ValVT = ValToCopy.getValueType();
1897 // Promote values to the appropriate types.
1898 if (VA.getLocInfo() == CCValAssign::SExt)
1899 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1900 else if (VA.getLocInfo() == CCValAssign::ZExt)
1901 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1902 else if (VA.getLocInfo() == CCValAssign::AExt)
1903 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1904 else if (VA.getLocInfo() == CCValAssign::BCvt)
1905 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1907 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1908 "Unexpected FP-extend for return value.");
1910 // If this is x86-64, and we disabled SSE, we can't return FP values,
1911 // or SSE or MMX vectors.
1912 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1913 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1914 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1915 report_fatal_error("SSE register return with SSE disabled");
1917 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1918 // llvm-gcc has never done it right and no one has noticed, so this
1919 // should be OK for now.
1920 if (ValVT == MVT::f64 &&
1921 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1922 report_fatal_error("SSE2 register return with SSE2 disabled");
1924 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1925 // the RET instruction and handled by the FP Stackifier.
1926 if (VA.getLocReg() == X86::FP0 ||
1927 VA.getLocReg() == X86::FP1) {
1928 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1929 // change the value to the FP stack register class.
1930 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1931 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1932 RetOps.push_back(ValToCopy);
1933 // Don't emit a copytoreg.
1937 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1938 // which is returned in RAX / RDX.
1939 if (Subtarget->is64Bit()) {
1940 if (ValVT == MVT::x86mmx) {
1941 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1942 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1943 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1945 // If we don't have SSE2 available, convert to v4f32 so the generated
1946 // register is legal.
1947 if (!Subtarget->hasSSE2())
1948 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1953 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1954 Flag = Chain.getValue(1);
1955 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1958 // The x86-64 ABIs require that for returning structs by value we copy
1959 // the sret argument into %rax/%eax (depending on ABI) for the return.
1960 // Win32 requires us to put the sret argument to %eax as well.
1961 // We saved the argument into a virtual register in the entry block,
1962 // so now we copy the value out and into %rax/%eax.
1964 // Checking Function.hasStructRetAttr() here is insufficient because the IR
1965 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
1966 // false, then an sret argument may be implicitly inserted in the SelDAG. In
1967 // either case FuncInfo->setSRetReturnReg() will have been called.
1968 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
1969 assert((Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) &&
1970 "No need for an sret register");
1971 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
1974 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1975 X86::RAX : X86::EAX;
1976 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1977 Flag = Chain.getValue(1);
1979 // RAX/EAX now acts like a return value.
1980 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1983 RetOps[0] = Chain; // Update chain.
1985 // Add the flag if we have it.
1987 RetOps.push_back(Flag);
1989 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
1992 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1993 if (N->getNumValues() != 1)
1995 if (!N->hasNUsesOfValue(1, 0))
1998 SDValue TCChain = Chain;
1999 SDNode *Copy = *N->use_begin();
2000 if (Copy->getOpcode() == ISD::CopyToReg) {
2001 // If the copy has a glue operand, we conservatively assume it isn't safe to
2002 // perform a tail call.
2003 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2005 TCChain = Copy->getOperand(0);
2006 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2009 bool HasRet = false;
2010 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2012 if (UI->getOpcode() != X86ISD::RET_FLAG)
2014 // If we are returning more than one value, we can definitely
2015 // not make a tail call see PR19530
2016 if (UI->getNumOperands() > 4)
2018 if (UI->getNumOperands() == 4 &&
2019 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2032 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2033 ISD::NodeType ExtendKind) const {
2035 // TODO: Is this also valid on 32-bit?
2036 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2037 ReturnMVT = MVT::i8;
2039 ReturnMVT = MVT::i32;
2041 EVT MinVT = getRegisterType(Context, ReturnMVT);
2042 return VT.bitsLT(MinVT) ? MinVT : VT;
2045 /// Lower the result values of a call into the
2046 /// appropriate copies out of appropriate physical registers.
2049 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2050 CallingConv::ID CallConv, bool isVarArg,
2051 const SmallVectorImpl<ISD::InputArg> &Ins,
2052 SDLoc dl, SelectionDAG &DAG,
2053 SmallVectorImpl<SDValue> &InVals) const {
2055 // Assign locations to each value returned by this call.
2056 SmallVector<CCValAssign, 16> RVLocs;
2057 bool Is64Bit = Subtarget->is64Bit();
2058 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2060 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2062 // Copy all of the result registers out of their specified physreg.
2063 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2064 CCValAssign &VA = RVLocs[i];
2065 EVT CopyVT = VA.getValVT();
2067 // If this is x86-64, and we disabled SSE, we can't return FP values
2068 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2069 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2070 report_fatal_error("SSE register return with SSE disabled");
2073 // If we prefer to use the value in xmm registers, copy it out as f80 and
2074 // use a truncate to move it from fp stack reg to xmm reg.
2075 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2076 isScalarFPTypeInSSEReg(VA.getValVT()))
2079 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2080 CopyVT, InFlag).getValue(1);
2081 SDValue Val = Chain.getValue(0);
2083 if (CopyVT != VA.getValVT())
2084 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2085 // This truncation won't change the value.
2086 DAG.getIntPtrConstant(1));
2088 InFlag = Chain.getValue(2);
2089 InVals.push_back(Val);
2095 //===----------------------------------------------------------------------===//
2096 // C & StdCall & Fast Calling Convention implementation
2097 //===----------------------------------------------------------------------===//
2098 // StdCall calling convention seems to be standard for many Windows' API
2099 // routines and around. It differs from C calling convention just a little:
2100 // callee should clean up the stack, not caller. Symbols should be also
2101 // decorated in some fancy way :) It doesn't support any vector arguments.
2102 // For info on fast calling convention see Fast Calling Convention (tail call)
2103 // implementation LowerX86_32FastCCCallTo.
2105 /// CallIsStructReturn - Determines whether a call uses struct return
2107 enum StructReturnType {
2112 static StructReturnType
2113 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2115 return NotStructReturn;
2117 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2118 if (!Flags.isSRet())
2119 return NotStructReturn;
2120 if (Flags.isInReg())
2121 return RegStructReturn;
2122 return StackStructReturn;
2125 /// Determines whether a function uses struct return semantics.
2126 static StructReturnType
2127 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2129 return NotStructReturn;
2131 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2132 if (!Flags.isSRet())
2133 return NotStructReturn;
2134 if (Flags.isInReg())
2135 return RegStructReturn;
2136 return StackStructReturn;
2139 /// Make a copy of an aggregate at address specified by "Src" to address
2140 /// "Dst" with size and alignment information specified by the specific
2141 /// parameter attribute. The copy will be passed as a byval function parameter.
2143 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2144 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2146 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2148 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2149 /*isVolatile*/false, /*AlwaysInline=*/true,
2150 /*isTailCall*/false,
2151 MachinePointerInfo(), MachinePointerInfo());
2154 /// Return true if the calling convention is one that
2155 /// supports tail call optimization.
2156 static bool IsTailCallConvention(CallingConv::ID CC) {
2157 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2158 CC == CallingConv::HiPE);
2161 /// \brief Return true if the calling convention is a C calling convention.
2162 static bool IsCCallConvention(CallingConv::ID CC) {
2163 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2164 CC == CallingConv::X86_64_SysV);
2167 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2168 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2172 CallingConv::ID CalleeCC = CS.getCallingConv();
2173 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2179 /// Return true if the function is being made into
2180 /// a tailcall target by changing its ABI.
2181 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2182 bool GuaranteedTailCallOpt) {
2183 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2187 X86TargetLowering::LowerMemArgument(SDValue Chain,
2188 CallingConv::ID CallConv,
2189 const SmallVectorImpl<ISD::InputArg> &Ins,
2190 SDLoc dl, SelectionDAG &DAG,
2191 const CCValAssign &VA,
2192 MachineFrameInfo *MFI,
2194 // Create the nodes corresponding to a load from this parameter slot.
2195 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2196 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2197 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2198 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2201 // If value is passed by pointer we have address passed instead of the value
2203 if (VA.getLocInfo() == CCValAssign::Indirect)
2204 ValVT = VA.getLocVT();
2206 ValVT = VA.getValVT();
2208 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2209 // changed with more analysis.
2210 // In case of tail call optimization mark all arguments mutable. Since they
2211 // could be overwritten by lowering of arguments in case of a tail call.
2212 if (Flags.isByVal()) {
2213 unsigned Bytes = Flags.getByValSize();
2214 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2215 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2216 return DAG.getFrameIndex(FI, getPointerTy());
2218 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2219 VA.getLocMemOffset(), isImmutable);
2220 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2221 return DAG.getLoad(ValVT, dl, Chain, FIN,
2222 MachinePointerInfo::getFixedStack(FI),
2223 false, false, false, 0);
2227 // FIXME: Get this from tablegen.
2228 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2229 const X86Subtarget *Subtarget) {
2230 assert(Subtarget->is64Bit());
2232 if (Subtarget->isCallingConvWin64(CallConv)) {
2233 static const MCPhysReg GPR64ArgRegsWin64[] = {
2234 X86::RCX, X86::RDX, X86::R8, X86::R9
2236 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2239 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2240 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2242 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2245 // FIXME: Get this from tablegen.
2246 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2247 CallingConv::ID CallConv,
2248 const X86Subtarget *Subtarget) {
2249 assert(Subtarget->is64Bit());
2250 if (Subtarget->isCallingConvWin64(CallConv)) {
2251 // The XMM registers which might contain var arg parameters are shadowed
2252 // in their paired GPR. So we only need to save the GPR to their home
2254 // TODO: __vectorcall will change this.
2258 const Function *Fn = MF.getFunction();
2259 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2260 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2261 "SSE register cannot be used when SSE is disabled!");
2262 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2263 !Subtarget->hasSSE1())
2264 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2268 static const MCPhysReg XMMArgRegs64Bit[] = {
2269 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2270 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2272 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2276 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2277 CallingConv::ID CallConv,
2279 const SmallVectorImpl<ISD::InputArg> &Ins,
2282 SmallVectorImpl<SDValue> &InVals)
2284 MachineFunction &MF = DAG.getMachineFunction();
2285 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2286 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2288 const Function* Fn = MF.getFunction();
2289 if (Fn->hasExternalLinkage() &&
2290 Subtarget->isTargetCygMing() &&
2291 Fn->getName() == "main")
2292 FuncInfo->setForceFramePointer(true);
2294 MachineFrameInfo *MFI = MF.getFrameInfo();
2295 bool Is64Bit = Subtarget->is64Bit();
2296 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2298 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2299 "Var args not supported with calling convention fastcc, ghc or hipe");
2301 // Assign locations to all of the incoming arguments.
2302 SmallVector<CCValAssign, 16> ArgLocs;
2303 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2305 // Allocate shadow area for Win64
2307 CCInfo.AllocateStack(32, 8);
2309 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2311 unsigned LastVal = ~0U;
2313 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2314 CCValAssign &VA = ArgLocs[i];
2315 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2317 assert(VA.getValNo() != LastVal &&
2318 "Don't support value assigned to multiple locs yet");
2320 LastVal = VA.getValNo();
2322 if (VA.isRegLoc()) {
2323 EVT RegVT = VA.getLocVT();
2324 const TargetRegisterClass *RC;
2325 if (RegVT == MVT::i32)
2326 RC = &X86::GR32RegClass;
2327 else if (Is64Bit && RegVT == MVT::i64)
2328 RC = &X86::GR64RegClass;
2329 else if (RegVT == MVT::f32)
2330 RC = &X86::FR32RegClass;
2331 else if (RegVT == MVT::f64)
2332 RC = &X86::FR64RegClass;
2333 else if (RegVT.is512BitVector())
2334 RC = &X86::VR512RegClass;
2335 else if (RegVT.is256BitVector())
2336 RC = &X86::VR256RegClass;
2337 else if (RegVT.is128BitVector())
2338 RC = &X86::VR128RegClass;
2339 else if (RegVT == MVT::x86mmx)
2340 RC = &X86::VR64RegClass;
2341 else if (RegVT == MVT::i1)
2342 RC = &X86::VK1RegClass;
2343 else if (RegVT == MVT::v8i1)
2344 RC = &X86::VK8RegClass;
2345 else if (RegVT == MVT::v16i1)
2346 RC = &X86::VK16RegClass;
2347 else if (RegVT == MVT::v32i1)
2348 RC = &X86::VK32RegClass;
2349 else if (RegVT == MVT::v64i1)
2350 RC = &X86::VK64RegClass;
2352 llvm_unreachable("Unknown argument type!");
2354 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2355 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2357 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2358 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2360 if (VA.getLocInfo() == CCValAssign::SExt)
2361 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2362 DAG.getValueType(VA.getValVT()));
2363 else if (VA.getLocInfo() == CCValAssign::ZExt)
2364 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2365 DAG.getValueType(VA.getValVT()));
2366 else if (VA.getLocInfo() == CCValAssign::BCvt)
2367 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2369 if (VA.isExtInLoc()) {
2370 // Handle MMX values passed in XMM regs.
2371 if (RegVT.isVector())
2372 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2374 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2377 assert(VA.isMemLoc());
2378 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2381 // If value is passed via pointer - do a load.
2382 if (VA.getLocInfo() == CCValAssign::Indirect)
2383 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2384 MachinePointerInfo(), false, false, false, 0);
2386 InVals.push_back(ArgValue);
2389 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2390 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2391 // The x86-64 ABIs require that for returning structs by value we copy
2392 // the sret argument into %rax/%eax (depending on ABI) for the return.
2393 // Win32 requires us to put the sret argument to %eax as well.
2394 // Save the argument into a virtual register so that we can access it
2395 // from the return points.
2396 if (Ins[i].Flags.isSRet()) {
2397 unsigned Reg = FuncInfo->getSRetReturnReg();
2399 MVT PtrTy = getPointerTy();
2400 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2401 FuncInfo->setSRetReturnReg(Reg);
2403 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2404 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2410 unsigned StackSize = CCInfo.getNextStackOffset();
2411 // Align stack specially for tail calls.
2412 if (FuncIsMadeTailCallSafe(CallConv,
2413 MF.getTarget().Options.GuaranteedTailCallOpt))
2414 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2416 // If the function takes variable number of arguments, make a frame index for
2417 // the start of the first vararg value... for expansion of llvm.va_start. We
2418 // can skip this if there are no va_start calls.
2419 if (MFI->hasVAStart() &&
2420 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2421 CallConv != CallingConv::X86_ThisCall))) {
2422 FuncInfo->setVarArgsFrameIndex(
2423 MFI->CreateFixedObject(1, StackSize, true));
2426 MachineModuleInfo &MMI = MF.getMMI();
2427 const Function *WinEHParent = nullptr;
2428 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2429 WinEHParent = MMI.getWinEHParent(Fn);
2430 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2431 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2433 // Figure out if XMM registers are in use.
2434 assert(!(MF.getTarget().Options.UseSoftFloat &&
2435 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2436 "SSE register cannot be used when SSE is disabled!");
2438 // 64-bit calling conventions support varargs and register parameters, so we
2439 // have to do extra work to spill them in the prologue.
2440 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2441 // Find the first unallocated argument registers.
2442 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2443 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2444 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2445 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2446 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2447 "SSE register cannot be used when SSE is disabled!");
2449 // Gather all the live in physical registers.
2450 SmallVector<SDValue, 6> LiveGPRs;
2451 SmallVector<SDValue, 8> LiveXMMRegs;
2453 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2454 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2456 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2458 if (!ArgXMMs.empty()) {
2459 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2460 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2461 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2462 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2463 LiveXMMRegs.push_back(
2464 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2469 // Get to the caller-allocated home save location. Add 8 to account
2470 // for the return address.
2471 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2472 FuncInfo->setRegSaveFrameIndex(
2473 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2474 // Fixup to set vararg frame on shadow area (4 x i64).
2476 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2478 // For X86-64, if there are vararg parameters that are passed via
2479 // registers, then we must store them to their spots on the stack so
2480 // they may be loaded by deferencing the result of va_next.
2481 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2482 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2483 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2484 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2487 // Store the integer parameter registers.
2488 SmallVector<SDValue, 8> MemOps;
2489 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2491 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2492 for (SDValue Val : LiveGPRs) {
2493 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2494 DAG.getIntPtrConstant(Offset));
2496 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2497 MachinePointerInfo::getFixedStack(
2498 FuncInfo->getRegSaveFrameIndex(), Offset),
2500 MemOps.push_back(Store);
2504 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2505 // Now store the XMM (fp + vector) parameter registers.
2506 SmallVector<SDValue, 12> SaveXMMOps;
2507 SaveXMMOps.push_back(Chain);
2508 SaveXMMOps.push_back(ALVal);
2509 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2510 FuncInfo->getRegSaveFrameIndex()));
2511 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2512 FuncInfo->getVarArgsFPOffset()));
2513 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2515 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2516 MVT::Other, SaveXMMOps));
2519 if (!MemOps.empty())
2520 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2521 } else if (IsWinEHOutlined) {
2522 // Get to the caller-allocated home save location. Add 8 to account
2523 // for the return address.
2524 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2525 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2526 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2528 MMI.getWinEHFuncInfo(Fn)
2529 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2530 FuncInfo->getRegSaveFrameIndex();
2532 // Store the second integer parameter (rdx) into rsp+16 relative to the
2533 // stack pointer at the entry of the function.
2535 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2536 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2537 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2538 Chain = DAG.getStore(
2539 Val.getValue(1), dl, Val, RSFIN,
2540 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2541 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2544 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2545 // Find the largest legal vector type.
2546 MVT VecVT = MVT::Other;
2547 // FIXME: Only some x86_32 calling conventions support AVX512.
2548 if (Subtarget->hasAVX512() &&
2549 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2550 CallConv == CallingConv::Intel_OCL_BI)))
2551 VecVT = MVT::v16f32;
2552 else if (Subtarget->hasAVX())
2554 else if (Subtarget->hasSSE2())
2557 // We forward some GPRs and some vector types.
2558 SmallVector<MVT, 2> RegParmTypes;
2559 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2560 RegParmTypes.push_back(IntVT);
2561 if (VecVT != MVT::Other)
2562 RegParmTypes.push_back(VecVT);
2564 // Compute the set of forwarded registers. The rest are scratch.
2565 SmallVectorImpl<ForwardedRegister> &Forwards =
2566 FuncInfo->getForwardedMustTailRegParms();
2567 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2569 // Conservatively forward AL on x86_64, since it might be used for varargs.
2570 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2571 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2572 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2575 // Copy all forwards from physical to virtual registers.
2576 for (ForwardedRegister &F : Forwards) {
2577 // FIXME: Can we use a less constrained schedule?
2578 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2579 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2580 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2584 // Some CCs need callee pop.
2585 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2586 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2587 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2589 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2590 // If this is an sret function, the return should pop the hidden pointer.
2591 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2592 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2593 argsAreStructReturn(Ins) == StackStructReturn)
2594 FuncInfo->setBytesToPopOnReturn(4);
2598 // RegSaveFrameIndex is X86-64 only.
2599 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2600 if (CallConv == CallingConv::X86_FastCall ||
2601 CallConv == CallingConv::X86_ThisCall)
2602 // fastcc functions can't have varargs.
2603 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2606 FuncInfo->setArgumentStackSize(StackSize);
2608 if (IsWinEHParent) {
2609 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2610 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2611 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2612 SDValue Neg2 = DAG.getConstant(-2, MVT::i64);
2613 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2614 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2615 /*isVolatile=*/true,
2616 /*isNonTemporal=*/false, /*Alignment=*/0);
2623 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2624 SDValue StackPtr, SDValue Arg,
2625 SDLoc dl, SelectionDAG &DAG,
2626 const CCValAssign &VA,
2627 ISD::ArgFlagsTy Flags) const {
2628 unsigned LocMemOffset = VA.getLocMemOffset();
2629 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2630 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2631 if (Flags.isByVal())
2632 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2634 return DAG.getStore(Chain, dl, Arg, PtrOff,
2635 MachinePointerInfo::getStack(LocMemOffset),
2639 /// Emit a load of return address if tail call
2640 /// optimization is performed and it is required.
2642 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2643 SDValue &OutRetAddr, SDValue Chain,
2644 bool IsTailCall, bool Is64Bit,
2645 int FPDiff, SDLoc dl) const {
2646 // Adjust the Return address stack slot.
2647 EVT VT = getPointerTy();
2648 OutRetAddr = getReturnAddressFrameIndex(DAG);
2650 // Load the "old" Return address.
2651 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2652 false, false, false, 0);
2653 return SDValue(OutRetAddr.getNode(), 1);
2656 /// Emit a store of the return address if tail call
2657 /// optimization is performed and it is required (FPDiff!=0).
2658 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2659 SDValue Chain, SDValue RetAddrFrIdx,
2660 EVT PtrVT, unsigned SlotSize,
2661 int FPDiff, SDLoc dl) {
2662 // Store the return address to the appropriate stack slot.
2663 if (!FPDiff) return Chain;
2664 // Calculate the new stack slot for the return address.
2665 int NewReturnAddrFI =
2666 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2668 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2669 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2670 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2676 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2677 SmallVectorImpl<SDValue> &InVals) const {
2678 SelectionDAG &DAG = CLI.DAG;
2680 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2681 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2682 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2683 SDValue Chain = CLI.Chain;
2684 SDValue Callee = CLI.Callee;
2685 CallingConv::ID CallConv = CLI.CallConv;
2686 bool &isTailCall = CLI.IsTailCall;
2687 bool isVarArg = CLI.IsVarArg;
2689 MachineFunction &MF = DAG.getMachineFunction();
2690 bool Is64Bit = Subtarget->is64Bit();
2691 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2692 StructReturnType SR = callIsStructReturn(Outs);
2693 bool IsSibcall = false;
2694 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2696 if (MF.getTarget().Options.DisableTailCalls)
2699 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2701 // Force this to be a tail call. The verifier rules are enough to ensure
2702 // that we can lower this successfully without moving the return address
2705 } else if (isTailCall) {
2706 // Check if it's really possible to do a tail call.
2707 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2708 isVarArg, SR != NotStructReturn,
2709 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2710 Outs, OutVals, Ins, DAG);
2712 // Sibcalls are automatically detected tailcalls which do not require
2714 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2721 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2722 "Var args not supported with calling convention fastcc, ghc or hipe");
2724 // Analyze operands of the call, assigning locations to each operand.
2725 SmallVector<CCValAssign, 16> ArgLocs;
2726 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2728 // Allocate shadow area for Win64
2730 CCInfo.AllocateStack(32, 8);
2732 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2734 // Get a count of how many bytes are to be pushed on the stack.
2735 unsigned NumBytes = CCInfo.getNextStackOffset();
2737 // This is a sibcall. The memory operands are available in caller's
2738 // own caller's stack.
2740 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2741 IsTailCallConvention(CallConv))
2742 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2745 if (isTailCall && !IsSibcall && !IsMustTail) {
2746 // Lower arguments at fp - stackoffset + fpdiff.
2747 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2749 FPDiff = NumBytesCallerPushed - NumBytes;
2751 // Set the delta of movement of the returnaddr stackslot.
2752 // But only set if delta is greater than previous delta.
2753 if (FPDiff < X86Info->getTCReturnAddrDelta())
2754 X86Info->setTCReturnAddrDelta(FPDiff);
2757 unsigned NumBytesToPush = NumBytes;
2758 unsigned NumBytesToPop = NumBytes;
2760 // If we have an inalloca argument, all stack space has already been allocated
2761 // for us and be right at the top of the stack. We don't support multiple
2762 // arguments passed in memory when using inalloca.
2763 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2765 if (!ArgLocs.back().isMemLoc())
2766 report_fatal_error("cannot use inalloca attribute on a register "
2768 if (ArgLocs.back().getLocMemOffset() != 0)
2769 report_fatal_error("any parameter with the inalloca attribute must be "
2770 "the only memory argument");
2774 Chain = DAG.getCALLSEQ_START(
2775 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2777 SDValue RetAddrFrIdx;
2778 // Load return address for tail calls.
2779 if (isTailCall && FPDiff)
2780 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2781 Is64Bit, FPDiff, dl);
2783 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2784 SmallVector<SDValue, 8> MemOpChains;
2787 // Walk the register/memloc assignments, inserting copies/loads. In the case
2788 // of tail call optimization arguments are handle later.
2789 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2790 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2791 // Skip inalloca arguments, they have already been written.
2792 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2793 if (Flags.isInAlloca())
2796 CCValAssign &VA = ArgLocs[i];
2797 EVT RegVT = VA.getLocVT();
2798 SDValue Arg = OutVals[i];
2799 bool isByVal = Flags.isByVal();
2801 // Promote the value if needed.
2802 switch (VA.getLocInfo()) {
2803 default: llvm_unreachable("Unknown loc info!");
2804 case CCValAssign::Full: break;
2805 case CCValAssign::SExt:
2806 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2808 case CCValAssign::ZExt:
2809 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2811 case CCValAssign::AExt:
2812 if (RegVT.is128BitVector()) {
2813 // Special case: passing MMX values in XMM registers.
2814 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2815 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2816 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2818 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2820 case CCValAssign::BCvt:
2821 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2823 case CCValAssign::Indirect: {
2824 // Store the argument.
2825 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2826 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2827 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2828 MachinePointerInfo::getFixedStack(FI),
2835 if (VA.isRegLoc()) {
2836 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2837 if (isVarArg && IsWin64) {
2838 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2839 // shadow reg if callee is a varargs function.
2840 unsigned ShadowReg = 0;
2841 switch (VA.getLocReg()) {
2842 case X86::XMM0: ShadowReg = X86::RCX; break;
2843 case X86::XMM1: ShadowReg = X86::RDX; break;
2844 case X86::XMM2: ShadowReg = X86::R8; break;
2845 case X86::XMM3: ShadowReg = X86::R9; break;
2848 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2850 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2851 assert(VA.isMemLoc());
2852 if (!StackPtr.getNode())
2853 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2855 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2856 dl, DAG, VA, Flags));
2860 if (!MemOpChains.empty())
2861 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2863 if (Subtarget->isPICStyleGOT()) {
2864 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2867 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2868 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2870 // If we are tail calling and generating PIC/GOT style code load the
2871 // address of the callee into ECX. The value in ecx is used as target of
2872 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2873 // for tail calls on PIC/GOT architectures. Normally we would just put the
2874 // address of GOT into ebx and then call target@PLT. But for tail calls
2875 // ebx would be restored (since ebx is callee saved) before jumping to the
2878 // Note: The actual moving to ECX is done further down.
2879 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2880 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2881 !G->getGlobal()->hasProtectedVisibility())
2882 Callee = LowerGlobalAddress(Callee, DAG);
2883 else if (isa<ExternalSymbolSDNode>(Callee))
2884 Callee = LowerExternalSymbol(Callee, DAG);
2888 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2889 // From AMD64 ABI document:
2890 // For calls that may call functions that use varargs or stdargs
2891 // (prototype-less calls or calls to functions containing ellipsis (...) in
2892 // the declaration) %al is used as hidden argument to specify the number
2893 // of SSE registers used. The contents of %al do not need to match exactly
2894 // the number of registers, but must be an ubound on the number of SSE
2895 // registers used and is in the range 0 - 8 inclusive.
2897 // Count the number of XMM registers allocated.
2898 static const MCPhysReg XMMArgRegs[] = {
2899 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2900 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2902 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2903 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2904 && "SSE registers cannot be used when SSE is disabled");
2906 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2907 DAG.getConstant(NumXMMRegs, MVT::i8)));
2910 if (isVarArg && IsMustTail) {
2911 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2912 for (const auto &F : Forwards) {
2913 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2914 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2918 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2919 // don't need this because the eligibility check rejects calls that require
2920 // shuffling arguments passed in memory.
2921 if (!IsSibcall && isTailCall) {
2922 // Force all the incoming stack arguments to be loaded from the stack
2923 // before any new outgoing arguments are stored to the stack, because the
2924 // outgoing stack slots may alias the incoming argument stack slots, and
2925 // the alias isn't otherwise explicit. This is slightly more conservative
2926 // than necessary, because it means that each store effectively depends
2927 // on every argument instead of just those arguments it would clobber.
2928 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2930 SmallVector<SDValue, 8> MemOpChains2;
2933 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2934 CCValAssign &VA = ArgLocs[i];
2937 assert(VA.isMemLoc());
2938 SDValue Arg = OutVals[i];
2939 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2940 // Skip inalloca arguments. They don't require any work.
2941 if (Flags.isInAlloca())
2943 // Create frame index.
2944 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2945 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2946 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2947 FIN = DAG.getFrameIndex(FI, getPointerTy());
2949 if (Flags.isByVal()) {
2950 // Copy relative to framepointer.
2951 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2952 if (!StackPtr.getNode())
2953 StackPtr = DAG.getCopyFromReg(Chain, dl,
2954 RegInfo->getStackRegister(),
2956 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2958 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2962 // Store relative to framepointer.
2963 MemOpChains2.push_back(
2964 DAG.getStore(ArgChain, dl, Arg, FIN,
2965 MachinePointerInfo::getFixedStack(FI),
2970 if (!MemOpChains2.empty())
2971 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2973 // Store the return address to the appropriate stack slot.
2974 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2975 getPointerTy(), RegInfo->getSlotSize(),
2979 // Build a sequence of copy-to-reg nodes chained together with token chain
2980 // and flag operands which copy the outgoing args into registers.
2982 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2983 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2984 RegsToPass[i].second, InFlag);
2985 InFlag = Chain.getValue(1);
2988 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2989 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2990 // In the 64-bit large code model, we have to make all calls
2991 // through a register, since the call instruction's 32-bit
2992 // pc-relative offset may not be large enough to hold the whole
2994 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
2995 // If the callee is a GlobalAddress node (quite common, every direct call
2996 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2998 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3000 // We should use extra load for direct calls to dllimported functions in
3002 const GlobalValue *GV = G->getGlobal();
3003 if (!GV->hasDLLImportStorageClass()) {
3004 unsigned char OpFlags = 0;
3005 bool ExtraLoad = false;
3006 unsigned WrapperKind = ISD::DELETED_NODE;
3008 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3009 // external symbols most go through the PLT in PIC mode. If the symbol
3010 // has hidden or protected visibility, or if it is static or local, then
3011 // we don't need to use the PLT - we can directly call it.
3012 if (Subtarget->isTargetELF() &&
3013 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3014 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3015 OpFlags = X86II::MO_PLT;
3016 } else if (Subtarget->isPICStyleStubAny() &&
3017 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3018 (!Subtarget->getTargetTriple().isMacOSX() ||
3019 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3020 // PC-relative references to external symbols should go through $stub,
3021 // unless we're building with the leopard linker or later, which
3022 // automatically synthesizes these stubs.
3023 OpFlags = X86II::MO_DARWIN_STUB;
3024 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3025 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3026 // If the function is marked as non-lazy, generate an indirect call
3027 // which loads from the GOT directly. This avoids runtime overhead
3028 // at the cost of eager binding (and one extra byte of encoding).
3029 OpFlags = X86II::MO_GOTPCREL;
3030 WrapperKind = X86ISD::WrapperRIP;
3034 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3035 G->getOffset(), OpFlags);
3037 // Add a wrapper if needed.
3038 if (WrapperKind != ISD::DELETED_NODE)
3039 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3040 // Add extra indirection if needed.
3042 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3043 MachinePointerInfo::getGOT(),
3044 false, false, false, 0);
3046 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3047 unsigned char OpFlags = 0;
3049 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3050 // external symbols should go through the PLT.
3051 if (Subtarget->isTargetELF() &&
3052 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3053 OpFlags = X86II::MO_PLT;
3054 } else if (Subtarget->isPICStyleStubAny() &&
3055 (!Subtarget->getTargetTriple().isMacOSX() ||
3056 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3057 // PC-relative references to external symbols should go through $stub,
3058 // unless we're building with the leopard linker or later, which
3059 // automatically synthesizes these stubs.
3060 OpFlags = X86II::MO_DARWIN_STUB;
3063 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3065 } else if (Subtarget->isTarget64BitILP32() &&
3066 Callee->getValueType(0) == MVT::i32) {
3067 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3068 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3071 // Returns a chain & a flag for retval copy to use.
3072 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3073 SmallVector<SDValue, 8> Ops;
3075 if (!IsSibcall && isTailCall) {
3076 Chain = DAG.getCALLSEQ_END(Chain,
3077 DAG.getIntPtrConstant(NumBytesToPop, true),
3078 DAG.getIntPtrConstant(0, true), InFlag, dl);
3079 InFlag = Chain.getValue(1);
3082 Ops.push_back(Chain);
3083 Ops.push_back(Callee);
3086 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3088 // Add argument registers to the end of the list so that they are known live
3090 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3091 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3092 RegsToPass[i].second.getValueType()));
3094 // Add a register mask operand representing the call-preserved registers.
3095 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3096 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3097 assert(Mask && "Missing call preserved mask for calling convention");
3098 Ops.push_back(DAG.getRegisterMask(Mask));
3100 if (InFlag.getNode())
3101 Ops.push_back(InFlag);
3105 //// If this is the first return lowered for this function, add the regs
3106 //// to the liveout set for the function.
3107 // This isn't right, although it's probably harmless on x86; liveouts
3108 // should be computed from returns not tail calls. Consider a void
3109 // function making a tail call to a function returning int.
3110 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3113 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3114 InFlag = Chain.getValue(1);
3116 // Create the CALLSEQ_END node.
3117 unsigned NumBytesForCalleeToPop;
3118 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3119 DAG.getTarget().Options.GuaranteedTailCallOpt))
3120 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3121 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3122 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3123 SR == StackStructReturn)
3124 // If this is a call to a struct-return function, the callee
3125 // pops the hidden struct pointer, so we have to push it back.
3126 // This is common for Darwin/X86, Linux & Mingw32 targets.
3127 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3128 NumBytesForCalleeToPop = 4;
3130 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3132 // Returns a flag for retval copy to use.
3134 Chain = DAG.getCALLSEQ_END(Chain,
3135 DAG.getIntPtrConstant(NumBytesToPop, true),
3136 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3139 InFlag = Chain.getValue(1);
3142 // Handle result values, copying them out of physregs into vregs that we
3144 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3145 Ins, dl, DAG, InVals);
3148 //===----------------------------------------------------------------------===//
3149 // Fast Calling Convention (tail call) implementation
3150 //===----------------------------------------------------------------------===//
3152 // Like std call, callee cleans arguments, convention except that ECX is
3153 // reserved for storing the tail called function address. Only 2 registers are
3154 // free for argument passing (inreg). Tail call optimization is performed
3156 // * tailcallopt is enabled
3157 // * caller/callee are fastcc
3158 // On X86_64 architecture with GOT-style position independent code only local
3159 // (within module) calls are supported at the moment.
3160 // To keep the stack aligned according to platform abi the function
3161 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3162 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3163 // If a tail called function callee has more arguments than the caller the
3164 // caller needs to make sure that there is room to move the RETADDR to. This is
3165 // achieved by reserving an area the size of the argument delta right after the
3166 // original RETADDR, but before the saved framepointer or the spilled registers
3167 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3179 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3180 /// for a 16 byte align requirement.
3182 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3183 SelectionDAG& DAG) const {
3184 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3185 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3186 unsigned StackAlignment = TFI.getStackAlignment();
3187 uint64_t AlignMask = StackAlignment - 1;
3188 int64_t Offset = StackSize;
3189 unsigned SlotSize = RegInfo->getSlotSize();
3190 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3191 // Number smaller than 12 so just add the difference.
3192 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3194 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3195 Offset = ((~AlignMask) & Offset) + StackAlignment +
3196 (StackAlignment-SlotSize);
3201 /// MatchingStackOffset - Return true if the given stack call argument is
3202 /// already available in the same position (relatively) of the caller's
3203 /// incoming argument stack.
3205 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3206 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3207 const X86InstrInfo *TII) {
3208 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3210 if (Arg.getOpcode() == ISD::CopyFromReg) {
3211 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3212 if (!TargetRegisterInfo::isVirtualRegister(VR))
3214 MachineInstr *Def = MRI->getVRegDef(VR);
3217 if (!Flags.isByVal()) {
3218 if (!TII->isLoadFromStackSlot(Def, FI))
3221 unsigned Opcode = Def->getOpcode();
3222 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3223 Opcode == X86::LEA64_32r) &&
3224 Def->getOperand(1).isFI()) {
3225 FI = Def->getOperand(1).getIndex();
3226 Bytes = Flags.getByValSize();
3230 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3231 if (Flags.isByVal())
3232 // ByVal argument is passed in as a pointer but it's now being
3233 // dereferenced. e.g.
3234 // define @foo(%struct.X* %A) {
3235 // tail call @bar(%struct.X* byval %A)
3238 SDValue Ptr = Ld->getBasePtr();
3239 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3242 FI = FINode->getIndex();
3243 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3244 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3245 FI = FINode->getIndex();
3246 Bytes = Flags.getByValSize();
3250 assert(FI != INT_MAX);
3251 if (!MFI->isFixedObjectIndex(FI))
3253 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3256 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3257 /// for tail call optimization. Targets which want to do tail call
3258 /// optimization should implement this function.
3260 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3261 CallingConv::ID CalleeCC,
3263 bool isCalleeStructRet,
3264 bool isCallerStructRet,
3266 const SmallVectorImpl<ISD::OutputArg> &Outs,
3267 const SmallVectorImpl<SDValue> &OutVals,
3268 const SmallVectorImpl<ISD::InputArg> &Ins,
3269 SelectionDAG &DAG) const {
3270 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3273 // If -tailcallopt is specified, make fastcc functions tail-callable.
3274 const MachineFunction &MF = DAG.getMachineFunction();
3275 const Function *CallerF = MF.getFunction();
3277 // If the function return type is x86_fp80 and the callee return type is not,
3278 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3279 // perform a tailcall optimization here.
3280 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3283 CallingConv::ID CallerCC = CallerF->getCallingConv();
3284 bool CCMatch = CallerCC == CalleeCC;
3285 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3286 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3288 // Win64 functions have extra shadow space for argument homing. Don't do the
3289 // sibcall if the caller and callee have mismatched expectations for this
3291 if (IsCalleeWin64 != IsCallerWin64)
3294 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3295 if (IsTailCallConvention(CalleeCC) && CCMatch)
3300 // Look for obvious safe cases to perform tail call optimization that do not
3301 // require ABI changes. This is what gcc calls sibcall.
3303 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3304 // emit a special epilogue.
3305 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3306 if (RegInfo->needsStackRealignment(MF))
3309 // Also avoid sibcall optimization if either caller or callee uses struct
3310 // return semantics.
3311 if (isCalleeStructRet || isCallerStructRet)
3314 // An stdcall/thiscall caller is expected to clean up its arguments; the
3315 // callee isn't going to do that.
3316 // FIXME: this is more restrictive than needed. We could produce a tailcall
3317 // when the stack adjustment matches. For example, with a thiscall that takes
3318 // only one argument.
3319 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3320 CallerCC == CallingConv::X86_ThisCall))
3323 // Do not sibcall optimize vararg calls unless all arguments are passed via
3325 if (isVarArg && !Outs.empty()) {
3327 // Optimizing for varargs on Win64 is unlikely to be safe without
3328 // additional testing.
3329 if (IsCalleeWin64 || IsCallerWin64)
3332 SmallVector<CCValAssign, 16> ArgLocs;
3333 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3336 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3337 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3338 if (!ArgLocs[i].isRegLoc())
3342 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3343 // stack. Therefore, if it's not used by the call it is not safe to optimize
3344 // this into a sibcall.
3345 bool Unused = false;
3346 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3353 SmallVector<CCValAssign, 16> RVLocs;
3354 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3356 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3357 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3358 CCValAssign &VA = RVLocs[i];
3359 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3364 // If the calling conventions do not match, then we'd better make sure the
3365 // results are returned in the same way as what the caller expects.
3367 SmallVector<CCValAssign, 16> RVLocs1;
3368 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3370 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3372 SmallVector<CCValAssign, 16> RVLocs2;
3373 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3375 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3377 if (RVLocs1.size() != RVLocs2.size())
3379 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3380 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3382 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3384 if (RVLocs1[i].isRegLoc()) {
3385 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3388 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3394 // If the callee takes no arguments then go on to check the results of the
3396 if (!Outs.empty()) {
3397 // Check if stack adjustment is needed. For now, do not do this if any
3398 // argument is passed on the stack.
3399 SmallVector<CCValAssign, 16> ArgLocs;
3400 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3403 // Allocate shadow area for Win64
3405 CCInfo.AllocateStack(32, 8);
3407 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3408 if (CCInfo.getNextStackOffset()) {
3409 MachineFunction &MF = DAG.getMachineFunction();
3410 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3413 // Check if the arguments are already laid out in the right way as
3414 // the caller's fixed stack objects.
3415 MachineFrameInfo *MFI = MF.getFrameInfo();
3416 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3417 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3418 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3419 CCValAssign &VA = ArgLocs[i];
3420 SDValue Arg = OutVals[i];
3421 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3422 if (VA.getLocInfo() == CCValAssign::Indirect)
3424 if (!VA.isRegLoc()) {
3425 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3432 // If the tailcall address may be in a register, then make sure it's
3433 // possible to register allocate for it. In 32-bit, the call address can
3434 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3435 // callee-saved registers are restored. These happen to be the same
3436 // registers used to pass 'inreg' arguments so watch out for those.
3437 if (!Subtarget->is64Bit() &&
3438 ((!isa<GlobalAddressSDNode>(Callee) &&
3439 !isa<ExternalSymbolSDNode>(Callee)) ||
3440 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3441 unsigned NumInRegs = 0;
3442 // In PIC we need an extra register to formulate the address computation
3444 unsigned MaxInRegs =
3445 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3448 CCValAssign &VA = ArgLocs[i];
3451 unsigned Reg = VA.getLocReg();
3454 case X86::EAX: case X86::EDX: case X86::ECX:
3455 if (++NumInRegs == MaxInRegs)
3467 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3468 const TargetLibraryInfo *libInfo) const {
3469 return X86::createFastISel(funcInfo, libInfo);
3472 //===----------------------------------------------------------------------===//
3473 // Other Lowering Hooks
3474 //===----------------------------------------------------------------------===//
3476 static bool MayFoldLoad(SDValue Op) {
3477 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3480 static bool MayFoldIntoStore(SDValue Op) {
3481 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3484 static bool isTargetShuffle(unsigned Opcode) {
3486 default: return false;
3487 case X86ISD::BLENDI:
3488 case X86ISD::PSHUFB:
3489 case X86ISD::PSHUFD:
3490 case X86ISD::PSHUFHW:
3491 case X86ISD::PSHUFLW:
3493 case X86ISD::PALIGNR:
3494 case X86ISD::MOVLHPS:
3495 case X86ISD::MOVLHPD:
3496 case X86ISD::MOVHLPS:
3497 case X86ISD::MOVLPS:
3498 case X86ISD::MOVLPD:
3499 case X86ISD::MOVSHDUP:
3500 case X86ISD::MOVSLDUP:
3501 case X86ISD::MOVDDUP:
3504 case X86ISD::UNPCKL:
3505 case X86ISD::UNPCKH:
3506 case X86ISD::VPERMILPI:
3507 case X86ISD::VPERM2X128:
3508 case X86ISD::VPERMI:
3513 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3514 SDValue V1, unsigned TargetMask,
3515 SelectionDAG &DAG) {
3517 default: llvm_unreachable("Unknown x86 shuffle node");
3518 case X86ISD::PSHUFD:
3519 case X86ISD::PSHUFHW:
3520 case X86ISD::PSHUFLW:
3521 case X86ISD::VPERMILPI:
3522 case X86ISD::VPERMI:
3523 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3527 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3528 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3530 default: llvm_unreachable("Unknown x86 shuffle node");
3531 case X86ISD::MOVLHPS:
3532 case X86ISD::MOVLHPD:
3533 case X86ISD::MOVHLPS:
3534 case X86ISD::MOVLPS:
3535 case X86ISD::MOVLPD:
3538 case X86ISD::UNPCKL:
3539 case X86ISD::UNPCKH:
3540 return DAG.getNode(Opc, dl, VT, V1, V2);
3544 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3545 MachineFunction &MF = DAG.getMachineFunction();
3546 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3547 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3548 int ReturnAddrIndex = FuncInfo->getRAIndex();
3550 if (ReturnAddrIndex == 0) {
3551 // Set up a frame object for the return address.
3552 unsigned SlotSize = RegInfo->getSlotSize();
3553 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3556 FuncInfo->setRAIndex(ReturnAddrIndex);
3559 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3562 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3563 bool hasSymbolicDisplacement) {
3564 // Offset should fit into 32 bit immediate field.
3565 if (!isInt<32>(Offset))
3568 // If we don't have a symbolic displacement - we don't have any extra
3570 if (!hasSymbolicDisplacement)
3573 // FIXME: Some tweaks might be needed for medium code model.
3574 if (M != CodeModel::Small && M != CodeModel::Kernel)
3577 // For small code model we assume that latest object is 16MB before end of 31
3578 // bits boundary. We may also accept pretty large negative constants knowing
3579 // that all objects are in the positive half of address space.
3580 if (M == CodeModel::Small && Offset < 16*1024*1024)
3583 // For kernel code model we know that all object resist in the negative half
3584 // of 32bits address space. We may not accept negative offsets, since they may
3585 // be just off and we may accept pretty large positive ones.
3586 if (M == CodeModel::Kernel && Offset >= 0)
3592 /// isCalleePop - Determines whether the callee is required to pop its
3593 /// own arguments. Callee pop is necessary to support tail calls.
3594 bool X86::isCalleePop(CallingConv::ID CallingConv,
3595 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3596 switch (CallingConv) {
3599 case CallingConv::X86_StdCall:
3600 case CallingConv::X86_FastCall:
3601 case CallingConv::X86_ThisCall:
3603 case CallingConv::Fast:
3604 case CallingConv::GHC:
3605 case CallingConv::HiPE:
3612 /// \brief Return true if the condition is an unsigned comparison operation.
3613 static bool isX86CCUnsigned(unsigned X86CC) {
3615 default: llvm_unreachable("Invalid integer condition!");
3616 case X86::COND_E: return true;
3617 case X86::COND_G: return false;
3618 case X86::COND_GE: return false;
3619 case X86::COND_L: return false;
3620 case X86::COND_LE: return false;
3621 case X86::COND_NE: return true;
3622 case X86::COND_B: return true;
3623 case X86::COND_A: return true;
3624 case X86::COND_BE: return true;
3625 case X86::COND_AE: return true;
3627 llvm_unreachable("covered switch fell through?!");
3630 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3631 /// specific condition code, returning the condition code and the LHS/RHS of the
3632 /// comparison to make.
3633 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3634 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3636 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3637 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3638 // X > -1 -> X == 0, jump !sign.
3639 RHS = DAG.getConstant(0, RHS.getValueType());
3640 return X86::COND_NS;
3642 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3643 // X < 0 -> X == 0, jump on sign.
3646 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3648 RHS = DAG.getConstant(0, RHS.getValueType());
3649 return X86::COND_LE;
3653 switch (SetCCOpcode) {
3654 default: llvm_unreachable("Invalid integer condition!");
3655 case ISD::SETEQ: return X86::COND_E;
3656 case ISD::SETGT: return X86::COND_G;
3657 case ISD::SETGE: return X86::COND_GE;
3658 case ISD::SETLT: return X86::COND_L;
3659 case ISD::SETLE: return X86::COND_LE;
3660 case ISD::SETNE: return X86::COND_NE;
3661 case ISD::SETULT: return X86::COND_B;
3662 case ISD::SETUGT: return X86::COND_A;
3663 case ISD::SETULE: return X86::COND_BE;
3664 case ISD::SETUGE: return X86::COND_AE;
3668 // First determine if it is required or is profitable to flip the operands.
3670 // If LHS is a foldable load, but RHS is not, flip the condition.
3671 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3672 !ISD::isNON_EXTLoad(RHS.getNode())) {
3673 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3674 std::swap(LHS, RHS);
3677 switch (SetCCOpcode) {
3683 std::swap(LHS, RHS);
3687 // On a floating point condition, the flags are set as follows:
3689 // 0 | 0 | 0 | X > Y
3690 // 0 | 0 | 1 | X < Y
3691 // 1 | 0 | 0 | X == Y
3692 // 1 | 1 | 1 | unordered
3693 switch (SetCCOpcode) {
3694 default: llvm_unreachable("Condcode should be pre-legalized away");
3696 case ISD::SETEQ: return X86::COND_E;
3697 case ISD::SETOLT: // flipped
3699 case ISD::SETGT: return X86::COND_A;
3700 case ISD::SETOLE: // flipped
3702 case ISD::SETGE: return X86::COND_AE;
3703 case ISD::SETUGT: // flipped
3705 case ISD::SETLT: return X86::COND_B;
3706 case ISD::SETUGE: // flipped
3708 case ISD::SETLE: return X86::COND_BE;
3710 case ISD::SETNE: return X86::COND_NE;
3711 case ISD::SETUO: return X86::COND_P;
3712 case ISD::SETO: return X86::COND_NP;
3714 case ISD::SETUNE: return X86::COND_INVALID;
3718 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3719 /// code. Current x86 isa includes the following FP cmov instructions:
3720 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3721 static bool hasFPCMov(unsigned X86CC) {
3737 /// isFPImmLegal - Returns true if the target can instruction select the
3738 /// specified FP immediate natively. If false, the legalizer will
3739 /// materialize the FP immediate as a load from a constant pool.
3740 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3741 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3742 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3748 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3749 ISD::LoadExtType ExtTy,
3751 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3752 // relocation target a movq or addq instruction: don't let the load shrink.
3753 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3754 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3755 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3756 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3760 /// \brief Returns true if it is beneficial to convert a load of a constant
3761 /// to just the constant itself.
3762 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3764 assert(Ty->isIntegerTy());
3766 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3767 if (BitSize == 0 || BitSize > 64)
3772 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3773 unsigned Index) const {
3774 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3777 return (Index == 0 || Index == ResVT.getVectorNumElements());
3780 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3781 // Speculate cttz only if we can directly use TZCNT.
3782 return Subtarget->hasBMI();
3785 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3786 // Speculate ctlz only if we can directly use LZCNT.
3787 return Subtarget->hasLZCNT();
3790 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3791 /// the specified range (L, H].
3792 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3793 return (Val < 0) || (Val >= Low && Val < Hi);
3796 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3797 /// specified value.
3798 static bool isUndefOrEqual(int Val, int CmpVal) {
3799 return (Val < 0 || Val == CmpVal);
3802 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3803 /// from position Pos and ending in Pos+Size, falls within the specified
3804 /// sequential range (Low, Low+Size]. or is undef.
3805 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3806 unsigned Pos, unsigned Size, int Low) {
3807 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3808 if (!isUndefOrEqual(Mask[i], Low))
3813 /// isVEXTRACTIndex - Return true if the specified
3814 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3815 /// suitable for instruction that extract 128 or 256 bit vectors
3816 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3817 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3818 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3821 // The index should be aligned on a vecWidth-bit boundary.
3823 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3825 MVT VT = N->getSimpleValueType(0);
3826 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3827 bool Result = (Index * ElSize) % vecWidth == 0;
3832 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3833 /// operand specifies a subvector insert that is suitable for input to
3834 /// insertion of 128 or 256-bit subvectors
3835 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3836 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3837 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3839 // The index should be aligned on a vecWidth-bit boundary.
3841 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3843 MVT VT = N->getSimpleValueType(0);
3844 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3845 bool Result = (Index * ElSize) % vecWidth == 0;
3850 bool X86::isVINSERT128Index(SDNode *N) {
3851 return isVINSERTIndex(N, 128);
3854 bool X86::isVINSERT256Index(SDNode *N) {
3855 return isVINSERTIndex(N, 256);
3858 bool X86::isVEXTRACT128Index(SDNode *N) {
3859 return isVEXTRACTIndex(N, 128);
3862 bool X86::isVEXTRACT256Index(SDNode *N) {
3863 return isVEXTRACTIndex(N, 256);
3866 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3867 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3868 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3869 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3872 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3874 MVT VecVT = N->getOperand(0).getSimpleValueType();
3875 MVT ElVT = VecVT.getVectorElementType();
3877 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3878 return Index / NumElemsPerChunk;
3881 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3882 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3883 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3884 llvm_unreachable("Illegal insert subvector for VINSERT");
3887 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3889 MVT VecVT = N->getSimpleValueType(0);
3890 MVT ElVT = VecVT.getVectorElementType();
3892 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3893 return Index / NumElemsPerChunk;
3896 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3897 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3898 /// and VINSERTI128 instructions.
3899 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3900 return getExtractVEXTRACTImmediate(N, 128);
3903 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3904 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3905 /// and VINSERTI64x4 instructions.
3906 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
3907 return getExtractVEXTRACTImmediate(N, 256);
3910 /// getInsertVINSERT128Immediate - Return the appropriate immediate
3911 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3912 /// and VINSERTI128 instructions.
3913 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
3914 return getInsertVINSERTImmediate(N, 128);
3917 /// getInsertVINSERT256Immediate - Return the appropriate immediate
3918 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
3919 /// and VINSERTI64x4 instructions.
3920 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
3921 return getInsertVINSERTImmediate(N, 256);
3924 /// isZero - Returns true if Elt is a constant integer zero
3925 static bool isZero(SDValue V) {
3926 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
3927 return C && C->isNullValue();
3930 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3932 bool X86::isZeroNode(SDValue Elt) {
3935 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
3936 return CFP->getValueAPF().isPosZero();
3940 /// getZeroVector - Returns a vector of specified type with all zero elements.
3942 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
3943 SelectionDAG &DAG, SDLoc dl) {
3944 assert(VT.isVector() && "Expected a vector type");
3946 // Always build SSE zero vectors as <4 x i32> bitcasted
3947 // to their dest type. This ensures they get CSE'd.
3949 if (VT.is128BitVector()) { // SSE
3950 if (Subtarget->hasSSE2()) { // SSE2
3951 SDValue Cst = DAG.getConstant(0, MVT::i32);
3952 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3954 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
3955 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3957 } else if (VT.is256BitVector()) { // AVX
3958 if (Subtarget->hasInt256()) { // AVX2
3959 SDValue Cst = DAG.getConstant(0, MVT::i32);
3960 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3961 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
3963 // 256-bit logic and arithmetic instructions in AVX are all
3964 // floating-point, no support for integer ops. Emit fp zeroed vectors.
3965 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
3966 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3967 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
3969 } else if (VT.is512BitVector()) { // AVX-512
3970 SDValue Cst = DAG.getConstant(0, MVT::i32);
3971 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
3972 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3973 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
3974 } else if (VT.getScalarType() == MVT::i1) {
3976 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
3977 && "Unexpected vector type");
3978 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
3979 && "Unexpected vector type");
3980 SDValue Cst = DAG.getConstant(0, MVT::i1);
3981 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
3982 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3984 llvm_unreachable("Unexpected vector type");
3986 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3989 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
3990 SelectionDAG &DAG, SDLoc dl,
3991 unsigned vectorWidth) {
3992 assert((vectorWidth == 128 || vectorWidth == 256) &&
3993 "Unsupported vector width");
3994 EVT VT = Vec.getValueType();
3995 EVT ElVT = VT.getVectorElementType();
3996 unsigned Factor = VT.getSizeInBits()/vectorWidth;
3997 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
3998 VT.getVectorNumElements()/Factor);
4000 // Extract from UNDEF is UNDEF.
4001 if (Vec.getOpcode() == ISD::UNDEF)
4002 return DAG.getUNDEF(ResultVT);
4004 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4005 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4007 // This is the index of the first element of the vectorWidth-bit chunk
4009 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4012 // If the input is a buildvector just emit a smaller one.
4013 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4014 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4015 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4018 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
4019 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4022 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4023 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4024 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4025 /// instructions or a simple subregister reference. Idx is an index in the
4026 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4027 /// lowering EXTRACT_VECTOR_ELT operations easier.
4028 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4029 SelectionDAG &DAG, SDLoc dl) {
4030 assert((Vec.getValueType().is256BitVector() ||
4031 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4032 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4035 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4036 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4037 SelectionDAG &DAG, SDLoc dl) {
4038 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4039 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4042 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4043 unsigned IdxVal, SelectionDAG &DAG,
4044 SDLoc dl, unsigned vectorWidth) {
4045 assert((vectorWidth == 128 || vectorWidth == 256) &&
4046 "Unsupported vector width");
4047 // Inserting UNDEF is Result
4048 if (Vec.getOpcode() == ISD::UNDEF)
4050 EVT VT = Vec.getValueType();
4051 EVT ElVT = VT.getVectorElementType();
4052 EVT ResultVT = Result.getValueType();
4054 // Insert the relevant vectorWidth bits.
4055 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4057 // This is the index of the first element of the vectorWidth-bit chunk
4059 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4062 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
4063 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4066 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4067 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4068 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4069 /// simple superregister reference. Idx is an index in the 128 bits
4070 /// we want. It need not be aligned to a 128-bit boundary. That makes
4071 /// lowering INSERT_VECTOR_ELT operations easier.
4072 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4073 SelectionDAG &DAG, SDLoc dl) {
4074 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4076 // For insertion into the zero index (low half) of a 256-bit vector, it is
4077 // more efficient to generate a blend with immediate instead of an insert*128.
4078 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4079 // extend the subvector to the size of the result vector. Make sure that
4080 // we are not recursing on that node by checking for undef here.
4081 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4082 Result.getOpcode() != ISD::UNDEF) {
4083 EVT ResultVT = Result.getValueType();
4084 SDValue ZeroIndex = DAG.getIntPtrConstant(0);
4085 SDValue Undef = DAG.getUNDEF(ResultVT);
4086 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4089 // The blend instruction, and therefore its mask, depend on the data type.
4090 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4091 if (ScalarType.isFloatingPoint()) {
4092 // Choose either vblendps (float) or vblendpd (double).
4093 unsigned ScalarSize = ScalarType.getSizeInBits();
4094 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4095 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4096 SDValue Mask = DAG.getConstant(MaskVal, MVT::i8);
4097 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4100 const X86Subtarget &Subtarget =
4101 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4103 // AVX2 is needed for 256-bit integer blend support.
4104 // Integers must be cast to 32-bit because there is only vpblendd;
4105 // vpblendw can't be used for this because it has a handicapped mask.
4107 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4108 // is still more efficient than using the wrong domain vinsertf128 that
4109 // will be created by InsertSubVector().
4110 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4112 SDValue Mask = DAG.getConstant(0x0f, MVT::i8);
4113 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4114 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4115 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4118 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4121 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4122 SelectionDAG &DAG, SDLoc dl) {
4123 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4124 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4127 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4128 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4129 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4130 /// large BUILD_VECTORS.
4131 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4132 unsigned NumElems, SelectionDAG &DAG,
4134 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4135 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4138 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4139 unsigned NumElems, SelectionDAG &DAG,
4141 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4142 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4145 /// getOnesVector - Returns a vector of specified type with all bits set.
4146 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4147 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4148 /// Then bitcast to their original type, ensuring they get CSE'd.
4149 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4151 assert(VT.isVector() && "Expected a vector type");
4153 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
4155 if (VT.is256BitVector()) {
4156 if (HasInt256) { // AVX2
4157 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4158 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4160 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4161 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4163 } else if (VT.is128BitVector()) {
4164 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4166 llvm_unreachable("Unexpected vector type");
4168 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4171 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4172 /// operation of specified width.
4173 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4175 unsigned NumElems = VT.getVectorNumElements();
4176 SmallVector<int, 8> Mask;
4177 Mask.push_back(NumElems);
4178 for (unsigned i = 1; i != NumElems; ++i)
4180 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4183 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4184 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4186 unsigned NumElems = VT.getVectorNumElements();
4187 SmallVector<int, 8> Mask;
4188 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4190 Mask.push_back(i + NumElems);
4192 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4195 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4196 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4198 unsigned NumElems = VT.getVectorNumElements();
4199 SmallVector<int, 8> Mask;
4200 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4201 Mask.push_back(i + Half);
4202 Mask.push_back(i + NumElems + Half);
4204 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4207 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4208 /// vector of zero or undef vector. This produces a shuffle where the low
4209 /// element of V2 is swizzled into the zero/undef vector, landing at element
4210 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4211 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4213 const X86Subtarget *Subtarget,
4214 SelectionDAG &DAG) {
4215 MVT VT = V2.getSimpleValueType();
4217 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4218 unsigned NumElems = VT.getVectorNumElements();
4219 SmallVector<int, 16> MaskVec;
4220 for (unsigned i = 0; i != NumElems; ++i)
4221 // If this is the insertion idx, put the low elt of V2 here.
4222 MaskVec.push_back(i == Idx ? NumElems : i);
4223 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4226 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4227 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4228 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4229 /// shuffles which use a single input multiple times, and in those cases it will
4230 /// adjust the mask to only have indices within that single input.
4231 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4232 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4233 unsigned NumElems = VT.getVectorNumElements();
4237 bool IsFakeUnary = false;
4238 switch(N->getOpcode()) {
4239 case X86ISD::BLENDI:
4240 ImmN = N->getOperand(N->getNumOperands()-1);
4241 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4244 ImmN = N->getOperand(N->getNumOperands()-1);
4245 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4246 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4248 case X86ISD::UNPCKH:
4249 DecodeUNPCKHMask(VT, Mask);
4250 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4252 case X86ISD::UNPCKL:
4253 DecodeUNPCKLMask(VT, Mask);
4254 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4256 case X86ISD::MOVHLPS:
4257 DecodeMOVHLPSMask(NumElems, Mask);
4258 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4260 case X86ISD::MOVLHPS:
4261 DecodeMOVLHPSMask(NumElems, Mask);
4262 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4264 case X86ISD::PALIGNR:
4265 ImmN = N->getOperand(N->getNumOperands()-1);
4266 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4268 case X86ISD::PSHUFD:
4269 case X86ISD::VPERMILPI:
4270 ImmN = N->getOperand(N->getNumOperands()-1);
4271 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4274 case X86ISD::PSHUFHW:
4275 ImmN = N->getOperand(N->getNumOperands()-1);
4276 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4279 case X86ISD::PSHUFLW:
4280 ImmN = N->getOperand(N->getNumOperands()-1);
4281 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4284 case X86ISD::PSHUFB: {
4286 SDValue MaskNode = N->getOperand(1);
4287 while (MaskNode->getOpcode() == ISD::BITCAST)
4288 MaskNode = MaskNode->getOperand(0);
4290 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4291 // If we have a build-vector, then things are easy.
4292 EVT VT = MaskNode.getValueType();
4293 assert(VT.isVector() &&
4294 "Can't produce a non-vector with a build_vector!");
4295 if (!VT.isInteger())
4298 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4300 SmallVector<uint64_t, 32> RawMask;
4301 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4302 SDValue Op = MaskNode->getOperand(i);
4303 if (Op->getOpcode() == ISD::UNDEF) {
4304 RawMask.push_back((uint64_t)SM_SentinelUndef);
4307 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4310 APInt MaskElement = CN->getAPIntValue();
4312 // We now have to decode the element which could be any integer size and
4313 // extract each byte of it.
4314 for (int j = 0; j < NumBytesPerElement; ++j) {
4315 // Note that this is x86 and so always little endian: the low byte is
4316 // the first byte of the mask.
4317 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4318 MaskElement = MaskElement.lshr(8);
4321 DecodePSHUFBMask(RawMask, Mask);
4325 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4329 SDValue Ptr = MaskLoad->getBasePtr();
4330 if (Ptr->getOpcode() == X86ISD::Wrapper)
4331 Ptr = Ptr->getOperand(0);
4333 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4334 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4337 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4338 DecodePSHUFBMask(C, Mask);
4346 case X86ISD::VPERMI:
4347 ImmN = N->getOperand(N->getNumOperands()-1);
4348 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4353 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4355 case X86ISD::VPERM2X128:
4356 ImmN = N->getOperand(N->getNumOperands()-1);
4357 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4358 if (Mask.empty()) return false;
4360 case X86ISD::MOVSLDUP:
4361 DecodeMOVSLDUPMask(VT, Mask);
4364 case X86ISD::MOVSHDUP:
4365 DecodeMOVSHDUPMask(VT, Mask);
4368 case X86ISD::MOVDDUP:
4369 DecodeMOVDDUPMask(VT, Mask);
4372 case X86ISD::MOVLHPD:
4373 case X86ISD::MOVLPD:
4374 case X86ISD::MOVLPS:
4375 // Not yet implemented
4377 default: llvm_unreachable("unknown target shuffle node");
4380 // If we have a fake unary shuffle, the shuffle mask is spread across two
4381 // inputs that are actually the same node. Re-map the mask to always point
4382 // into the first input.
4385 if (M >= (int)Mask.size())
4391 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4392 /// element of the result of the vector shuffle.
4393 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4396 return SDValue(); // Limit search depth.
4398 SDValue V = SDValue(N, 0);
4399 EVT VT = V.getValueType();
4400 unsigned Opcode = V.getOpcode();
4402 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4403 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4404 int Elt = SV->getMaskElt(Index);
4407 return DAG.getUNDEF(VT.getVectorElementType());
4409 unsigned NumElems = VT.getVectorNumElements();
4410 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4411 : SV->getOperand(1);
4412 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4415 // Recurse into target specific vector shuffles to find scalars.
4416 if (isTargetShuffle(Opcode)) {
4417 MVT ShufVT = V.getSimpleValueType();
4418 unsigned NumElems = ShufVT.getVectorNumElements();
4419 SmallVector<int, 16> ShuffleMask;
4422 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4425 int Elt = ShuffleMask[Index];
4427 return DAG.getUNDEF(ShufVT.getVectorElementType());
4429 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4431 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4435 // Actual nodes that may contain scalar elements
4436 if (Opcode == ISD::BITCAST) {
4437 V = V.getOperand(0);
4438 EVT SrcVT = V.getValueType();
4439 unsigned NumElems = VT.getVectorNumElements();
4441 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4445 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4446 return (Index == 0) ? V.getOperand(0)
4447 : DAG.getUNDEF(VT.getVectorElementType());
4449 if (V.getOpcode() == ISD::BUILD_VECTOR)
4450 return V.getOperand(Index);
4455 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4457 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4458 unsigned NumNonZero, unsigned NumZero,
4460 const X86Subtarget* Subtarget,
4461 const TargetLowering &TLI) {
4469 // SSE4.1 - use PINSRB to insert each byte directly.
4470 if (Subtarget->hasSSE41()) {
4471 for (unsigned i = 0; i < 16; ++i) {
4472 bool isNonZero = (NonZeros & (1 << i)) != 0;
4476 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4478 V = DAG.getUNDEF(MVT::v16i8);
4481 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4482 MVT::v16i8, V, Op.getOperand(i),
4483 DAG.getIntPtrConstant(i));
4490 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4491 for (unsigned i = 0; i < 16; ++i) {
4492 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4493 if (ThisIsNonZero && First) {
4495 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4497 V = DAG.getUNDEF(MVT::v8i16);
4502 SDValue ThisElt, LastElt;
4503 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4504 if (LastIsNonZero) {
4505 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4506 MVT::i16, Op.getOperand(i-1));
4508 if (ThisIsNonZero) {
4509 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4510 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4511 ThisElt, DAG.getConstant(8, MVT::i8));
4513 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4517 if (ThisElt.getNode())
4518 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4519 DAG.getIntPtrConstant(i/2));
4523 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4526 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4528 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4529 unsigned NumNonZero, unsigned NumZero,
4531 const X86Subtarget* Subtarget,
4532 const TargetLowering &TLI) {
4539 for (unsigned i = 0; i < 8; ++i) {
4540 bool isNonZero = (NonZeros & (1 << i)) != 0;
4544 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4546 V = DAG.getUNDEF(MVT::v8i16);
4549 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4550 MVT::v8i16, V, Op.getOperand(i),
4551 DAG.getIntPtrConstant(i));
4558 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4559 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4560 const X86Subtarget *Subtarget,
4561 const TargetLowering &TLI) {
4562 // Find all zeroable elements.
4563 std::bitset<4> Zeroable;
4564 for (int i=0; i < 4; ++i) {
4565 SDValue Elt = Op->getOperand(i);
4566 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4568 assert(Zeroable.size() - Zeroable.count() > 1 &&
4569 "We expect at least two non-zero elements!");
4571 // We only know how to deal with build_vector nodes where elements are either
4572 // zeroable or extract_vector_elt with constant index.
4573 SDValue FirstNonZero;
4574 unsigned FirstNonZeroIdx;
4575 for (unsigned i=0; i < 4; ++i) {
4578 SDValue Elt = Op->getOperand(i);
4579 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4580 !isa<ConstantSDNode>(Elt.getOperand(1)))
4582 // Make sure that this node is extracting from a 128-bit vector.
4583 MVT VT = Elt.getOperand(0).getSimpleValueType();
4584 if (!VT.is128BitVector())
4586 if (!FirstNonZero.getNode()) {
4588 FirstNonZeroIdx = i;
4592 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4593 SDValue V1 = FirstNonZero.getOperand(0);
4594 MVT VT = V1.getSimpleValueType();
4596 // See if this build_vector can be lowered as a blend with zero.
4598 unsigned EltMaskIdx, EltIdx;
4600 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4601 if (Zeroable[EltIdx]) {
4602 // The zero vector will be on the right hand side.
4603 Mask[EltIdx] = EltIdx+4;
4607 Elt = Op->getOperand(EltIdx);
4608 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4609 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4610 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4612 Mask[EltIdx] = EltIdx;
4616 // Let the shuffle legalizer deal with blend operations.
4617 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4618 if (V1.getSimpleValueType() != VT)
4619 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4620 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4623 // See if we can lower this build_vector to a INSERTPS.
4624 if (!Subtarget->hasSSE41())
4627 SDValue V2 = Elt.getOperand(0);
4628 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4631 bool CanFold = true;
4632 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4636 SDValue Current = Op->getOperand(i);
4637 SDValue SrcVector = Current->getOperand(0);
4640 CanFold = SrcVector == V1 &&
4641 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4647 assert(V1.getNode() && "Expected at least two non-zero elements!");
4648 if (V1.getSimpleValueType() != MVT::v4f32)
4649 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4650 if (V2.getSimpleValueType() != MVT::v4f32)
4651 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4653 // Ok, we can emit an INSERTPS instruction.
4654 unsigned ZMask = Zeroable.to_ulong();
4656 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4657 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4658 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
4659 DAG.getIntPtrConstant(InsertPSMask));
4660 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
4663 /// Return a vector logical shift node.
4664 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4665 unsigned NumBits, SelectionDAG &DAG,
4666 const TargetLowering &TLI, SDLoc dl) {
4667 assert(VT.is128BitVector() && "Unknown type for VShift");
4668 MVT ShVT = MVT::v2i64;
4669 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4670 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4671 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4672 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4673 SDValue ShiftVal = DAG.getConstant(NumBits/8, ScalarShiftTy);
4674 return DAG.getNode(ISD::BITCAST, dl, VT,
4675 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4679 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4681 // Check if the scalar load can be widened into a vector load. And if
4682 // the address is "base + cst" see if the cst can be "absorbed" into
4683 // the shuffle mask.
4684 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4685 SDValue Ptr = LD->getBasePtr();
4686 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4688 EVT PVT = LD->getValueType(0);
4689 if (PVT != MVT::i32 && PVT != MVT::f32)
4694 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4695 FI = FINode->getIndex();
4697 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4698 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4699 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4700 Offset = Ptr.getConstantOperandVal(1);
4701 Ptr = Ptr.getOperand(0);
4706 // FIXME: 256-bit vector instructions don't require a strict alignment,
4707 // improve this code to support it better.
4708 unsigned RequiredAlign = VT.getSizeInBits()/8;
4709 SDValue Chain = LD->getChain();
4710 // Make sure the stack object alignment is at least 16 or 32.
4711 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4712 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4713 if (MFI->isFixedObjectIndex(FI)) {
4714 // Can't change the alignment. FIXME: It's possible to compute
4715 // the exact stack offset and reference FI + adjust offset instead.
4716 // If someone *really* cares about this. That's the way to implement it.
4719 MFI->setObjectAlignment(FI, RequiredAlign);
4723 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4724 // Ptr + (Offset & ~15).
4727 if ((Offset % RequiredAlign) & 3)
4729 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4731 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
4732 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4734 int EltNo = (Offset - StartOffset) >> 2;
4735 unsigned NumElems = VT.getVectorNumElements();
4737 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4738 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4739 LD->getPointerInfo().getWithOffset(StartOffset),
4740 false, false, false, 0);
4742 SmallVector<int, 8> Mask(NumElems, EltNo);
4744 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4750 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4751 /// elements can be replaced by a single large load which has the same value as
4752 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4754 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4756 /// FIXME: we'd also like to handle the case where the last elements are zero
4757 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4758 /// There's even a handy isZeroNode for that purpose.
4759 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4760 SDLoc &DL, SelectionDAG &DAG,
4761 bool isAfterLegalize) {
4762 unsigned NumElems = Elts.size();
4764 LoadSDNode *LDBase = nullptr;
4765 unsigned LastLoadedElt = -1U;
4767 // For each element in the initializer, see if we've found a load or an undef.
4768 // If we don't find an initial load element, or later load elements are
4769 // non-consecutive, bail out.
4770 for (unsigned i = 0; i < NumElems; ++i) {
4771 SDValue Elt = Elts[i];
4772 // Look through a bitcast.
4773 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4774 Elt = Elt.getOperand(0);
4775 if (!Elt.getNode() ||
4776 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4779 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4781 LDBase = cast<LoadSDNode>(Elt.getNode());
4785 if (Elt.getOpcode() == ISD::UNDEF)
4788 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4789 EVT LdVT = Elt.getValueType();
4790 // Each loaded element must be the correct fractional portion of the
4791 // requested vector load.
4792 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4794 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4799 // If we have found an entire vector of loads and undefs, then return a large
4800 // load of the entire vector width starting at the base pointer. If we found
4801 // consecutive loads for the low half, generate a vzext_load node.
4802 if (LastLoadedElt == NumElems - 1) {
4803 assert(LDBase && "Did not find base load for merging consecutive loads");
4804 EVT EltVT = LDBase->getValueType(0);
4805 // Ensure that the input vector size for the merged loads matches the
4806 // cumulative size of the input elements.
4807 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4810 if (isAfterLegalize &&
4811 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4814 SDValue NewLd = SDValue();
4816 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4817 LDBase->getPointerInfo(), LDBase->isVolatile(),
4818 LDBase->isNonTemporal(), LDBase->isInvariant(),
4819 LDBase->getAlignment());
4821 if (LDBase->hasAnyUseOfValue(1)) {
4822 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4824 SDValue(NewLd.getNode(), 1));
4825 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4826 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4827 SDValue(NewLd.getNode(), 1));
4833 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4834 //of a v4i32 / v4f32. It's probably worth generalizing.
4835 EVT EltVT = VT.getVectorElementType();
4836 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4837 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4838 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4839 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4841 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4842 LDBase->getPointerInfo(),
4843 LDBase->getAlignment(),
4844 false/*isVolatile*/, true/*ReadMem*/,
4847 // Make sure the newly-created LOAD is in the same position as LDBase in
4848 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4849 // update uses of LDBase's output chain to use the TokenFactor.
4850 if (LDBase->hasAnyUseOfValue(1)) {
4851 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4852 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4853 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4854 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4855 SDValue(ResNode.getNode(), 1));
4858 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4863 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4864 /// to generate a splat value for the following cases:
4865 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4866 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4867 /// a scalar load, or a constant.
4868 /// The VBROADCAST node is returned when a pattern is found,
4869 /// or SDValue() otherwise.
4870 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4871 SelectionDAG &DAG) {
4872 // VBROADCAST requires AVX.
4873 // TODO: Splats could be generated for non-AVX CPUs using SSE
4874 // instructions, but there's less potential gain for only 128-bit vectors.
4875 if (!Subtarget->hasAVX())
4878 MVT VT = Op.getSimpleValueType();
4881 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4882 "Unsupported vector type for broadcast.");
4887 switch (Op.getOpcode()) {
4889 // Unknown pattern found.
4892 case ISD::BUILD_VECTOR: {
4893 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4894 BitVector UndefElements;
4895 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4897 // We need a splat of a single value to use broadcast, and it doesn't
4898 // make any sense if the value is only in one element of the vector.
4899 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4903 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4904 Ld.getOpcode() == ISD::ConstantFP);
4906 // Make sure that all of the users of a non-constant load are from the
4907 // BUILD_VECTOR node.
4908 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
4913 case ISD::VECTOR_SHUFFLE: {
4914 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4916 // Shuffles must have a splat mask where the first element is
4918 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4921 SDValue Sc = Op.getOperand(0);
4922 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4923 Sc.getOpcode() != ISD::BUILD_VECTOR) {
4925 if (!Subtarget->hasInt256())
4928 // Use the register form of the broadcast instruction available on AVX2.
4929 if (VT.getSizeInBits() >= 256)
4930 Sc = Extract128BitVector(Sc, 0, DAG, dl);
4931 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
4934 Ld = Sc.getOperand(0);
4935 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4936 Ld.getOpcode() == ISD::ConstantFP);
4938 // The scalar_to_vector node and the suspected
4939 // load node must have exactly one user.
4940 // Constants may have multiple users.
4942 // AVX-512 has register version of the broadcast
4943 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
4944 Ld.getValueType().getSizeInBits() >= 32;
4945 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
4952 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4953 bool IsGE256 = (VT.getSizeInBits() >= 256);
4955 // When optimizing for size, generate up to 5 extra bytes for a broadcast
4956 // instruction to save 8 or more bytes of constant pool data.
4957 // TODO: If multiple splats are generated to load the same constant,
4958 // it may be detrimental to overall size. There needs to be a way to detect
4959 // that condition to know if this is truly a size win.
4960 const Function *F = DAG.getMachineFunction().getFunction();
4961 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
4963 // Handle broadcasting a single constant scalar from the constant pool
4965 // On Sandybridge (no AVX2), it is still better to load a constant vector
4966 // from the constant pool and not to broadcast it from a scalar.
4967 // But override that restriction when optimizing for size.
4968 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
4969 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
4970 EVT CVT = Ld.getValueType();
4971 assert(!CVT.isVector() && "Must not broadcast a vector type");
4973 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
4974 // For size optimization, also splat v2f64 and v2i64, and for size opt
4975 // with AVX2, also splat i8 and i16.
4976 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
4977 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
4978 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
4979 const Constant *C = nullptr;
4980 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4981 C = CI->getConstantIntValue();
4982 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4983 C = CF->getConstantFPValue();
4985 assert(C && "Invalid constant type");
4987 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4988 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
4989 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4990 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4991 MachinePointerInfo::getConstantPool(),
4992 false, false, false, Alignment);
4994 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4998 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5000 // Handle AVX2 in-register broadcasts.
5001 if (!IsLoad && Subtarget->hasInt256() &&
5002 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5003 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5005 // The scalar source must be a normal load.
5009 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5010 (Subtarget->hasVLX() && ScalarSize == 64))
5011 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5013 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5014 // double since there is no vbroadcastsd xmm
5015 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5016 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5017 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5020 // Unsupported broadcast.
5024 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5025 /// underlying vector and index.
5027 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5029 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5031 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5032 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5035 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5037 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5039 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5040 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5043 // In this case the vector is the extract_subvector expression and the index
5044 // is 2, as specified by the shuffle.
5045 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5046 SDValue ShuffleVec = SVOp->getOperand(0);
5047 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5048 assert(ShuffleVecVT.getVectorElementType() ==
5049 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5051 int ShuffleIdx = SVOp->getMaskElt(Idx);
5052 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5053 ExtractedFromVec = ShuffleVec;
5059 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5060 MVT VT = Op.getSimpleValueType();
5062 // Skip if insert_vec_elt is not supported.
5063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5064 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5068 unsigned NumElems = Op.getNumOperands();
5072 SmallVector<unsigned, 4> InsertIndices;
5073 SmallVector<int, 8> Mask(NumElems, -1);
5075 for (unsigned i = 0; i != NumElems; ++i) {
5076 unsigned Opc = Op.getOperand(i).getOpcode();
5078 if (Opc == ISD::UNDEF)
5081 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5082 // Quit if more than 1 elements need inserting.
5083 if (InsertIndices.size() > 1)
5086 InsertIndices.push_back(i);
5090 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5091 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5092 // Quit if non-constant index.
5093 if (!isa<ConstantSDNode>(ExtIdx))
5095 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5097 // Quit if extracted from vector of different type.
5098 if (ExtractedFromVec.getValueType() != VT)
5101 if (!VecIn1.getNode())
5102 VecIn1 = ExtractedFromVec;
5103 else if (VecIn1 != ExtractedFromVec) {
5104 if (!VecIn2.getNode())
5105 VecIn2 = ExtractedFromVec;
5106 else if (VecIn2 != ExtractedFromVec)
5107 // Quit if more than 2 vectors to shuffle
5111 if (ExtractedFromVec == VecIn1)
5113 else if (ExtractedFromVec == VecIn2)
5114 Mask[i] = Idx + NumElems;
5117 if (!VecIn1.getNode())
5120 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5121 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5122 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5123 unsigned Idx = InsertIndices[i];
5124 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5125 DAG.getIntPtrConstant(Idx));
5131 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5133 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5135 MVT VT = Op.getSimpleValueType();
5136 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5137 "Unexpected type in LowerBUILD_VECTORvXi1!");
5140 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5141 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5142 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5143 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5146 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5147 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5148 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5149 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5152 bool AllContants = true;
5153 uint64_t Immediate = 0;
5154 int NonConstIdx = -1;
5155 bool IsSplat = true;
5156 unsigned NumNonConsts = 0;
5157 unsigned NumConsts = 0;
5158 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5159 SDValue In = Op.getOperand(idx);
5160 if (In.getOpcode() == ISD::UNDEF)
5162 if (!isa<ConstantSDNode>(In)) {
5163 AllContants = false;
5168 if (cast<ConstantSDNode>(In)->getZExtValue())
5169 Immediate |= (1ULL << idx);
5171 if (In != Op.getOperand(0))
5176 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5177 DAG.getConstant(Immediate, MVT::i16));
5178 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5179 DAG.getIntPtrConstant(0));
5182 if (NumNonConsts == 1 && NonConstIdx != 0) {
5185 SDValue VecAsImm = DAG.getConstant(Immediate,
5186 MVT::getIntegerVT(VT.getSizeInBits()));
5187 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5190 DstVec = DAG.getUNDEF(VT);
5191 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5192 Op.getOperand(NonConstIdx),
5193 DAG.getIntPtrConstant(NonConstIdx));
5195 if (!IsSplat && (NonConstIdx != 0))
5196 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5197 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5200 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5201 DAG.getConstant(-1, SelectVT),
5202 DAG.getConstant(0, SelectVT));
5204 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5205 DAG.getConstant((Immediate | 1), SelectVT),
5206 DAG.getConstant(Immediate, SelectVT));
5207 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5210 /// \brief Return true if \p N implements a horizontal binop and return the
5211 /// operands for the horizontal binop into V0 and V1.
5213 /// This is a helper function of LowerToHorizontalOp().
5214 /// This function checks that the build_vector \p N in input implements a
5215 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5216 /// operation to match.
5217 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5218 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5219 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5222 /// This function only analyzes elements of \p N whose indices are
5223 /// in range [BaseIdx, LastIdx).
5224 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5226 unsigned BaseIdx, unsigned LastIdx,
5227 SDValue &V0, SDValue &V1) {
5228 EVT VT = N->getValueType(0);
5230 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5231 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5232 "Invalid Vector in input!");
5234 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5235 bool CanFold = true;
5236 unsigned ExpectedVExtractIdx = BaseIdx;
5237 unsigned NumElts = LastIdx - BaseIdx;
5238 V0 = DAG.getUNDEF(VT);
5239 V1 = DAG.getUNDEF(VT);
5241 // Check if N implements a horizontal binop.
5242 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5243 SDValue Op = N->getOperand(i + BaseIdx);
5246 if (Op->getOpcode() == ISD::UNDEF) {
5247 // Update the expected vector extract index.
5248 if (i * 2 == NumElts)
5249 ExpectedVExtractIdx = BaseIdx;
5250 ExpectedVExtractIdx += 2;
5254 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5259 SDValue Op0 = Op.getOperand(0);
5260 SDValue Op1 = Op.getOperand(1);
5262 // Try to match the following pattern:
5263 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5264 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5265 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5266 Op0.getOperand(0) == Op1.getOperand(0) &&
5267 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5268 isa<ConstantSDNode>(Op1.getOperand(1)));
5272 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5273 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5275 if (i * 2 < NumElts) {
5276 if (V0.getOpcode() == ISD::UNDEF) {
5277 V0 = Op0.getOperand(0);
5278 if (V0.getValueType() != VT)
5282 if (V1.getOpcode() == ISD::UNDEF) {
5283 V1 = Op0.getOperand(0);
5284 if (V1.getValueType() != VT)
5287 if (i * 2 == NumElts)
5288 ExpectedVExtractIdx = BaseIdx;
5291 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5292 if (I0 == ExpectedVExtractIdx)
5293 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5294 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5295 // Try to match the following dag sequence:
5296 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5297 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5301 ExpectedVExtractIdx += 2;
5307 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5308 /// a concat_vector.
5310 /// This is a helper function of LowerToHorizontalOp().
5311 /// This function expects two 256-bit vectors called V0 and V1.
5312 /// At first, each vector is split into two separate 128-bit vectors.
5313 /// Then, the resulting 128-bit vectors are used to implement two
5314 /// horizontal binary operations.
5316 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5318 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5319 /// the two new horizontal binop.
5320 /// When Mode is set, the first horizontal binop dag node would take as input
5321 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5322 /// horizontal binop dag node would take as input the lower 128-bit of V1
5323 /// and the upper 128-bit of V1.
5325 /// HADD V0_LO, V0_HI
5326 /// HADD V1_LO, V1_HI
5328 /// Otherwise, the first horizontal binop dag node takes as input the lower
5329 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5330 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5332 /// HADD V0_LO, V1_LO
5333 /// HADD V0_HI, V1_HI
5335 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5336 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5337 /// the upper 128-bits of the result.
5338 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5339 SDLoc DL, SelectionDAG &DAG,
5340 unsigned X86Opcode, bool Mode,
5341 bool isUndefLO, bool isUndefHI) {
5342 EVT VT = V0.getValueType();
5343 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5344 "Invalid nodes in input!");
5346 unsigned NumElts = VT.getVectorNumElements();
5347 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5348 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5349 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5350 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5351 EVT NewVT = V0_LO.getValueType();
5353 SDValue LO = DAG.getUNDEF(NewVT);
5354 SDValue HI = DAG.getUNDEF(NewVT);
5357 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5358 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5359 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5360 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5361 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5363 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5364 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5365 V1_LO->getOpcode() != ISD::UNDEF))
5366 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5368 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5369 V1_HI->getOpcode() != ISD::UNDEF))
5370 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5373 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5376 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5378 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5379 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5380 EVT VT = BV->getValueType(0);
5381 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5382 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5386 unsigned NumElts = VT.getVectorNumElements();
5387 SDValue InVec0 = DAG.getUNDEF(VT);
5388 SDValue InVec1 = DAG.getUNDEF(VT);
5390 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5391 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5393 // Odd-numbered elements in the input build vector are obtained from
5394 // adding two integer/float elements.
5395 // Even-numbered elements in the input build vector are obtained from
5396 // subtracting two integer/float elements.
5397 unsigned ExpectedOpcode = ISD::FSUB;
5398 unsigned NextExpectedOpcode = ISD::FADD;
5399 bool AddFound = false;
5400 bool SubFound = false;
5402 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5403 SDValue Op = BV->getOperand(i);
5405 // Skip 'undef' values.
5406 unsigned Opcode = Op.getOpcode();
5407 if (Opcode == ISD::UNDEF) {
5408 std::swap(ExpectedOpcode, NextExpectedOpcode);
5412 // Early exit if we found an unexpected opcode.
5413 if (Opcode != ExpectedOpcode)
5416 SDValue Op0 = Op.getOperand(0);
5417 SDValue Op1 = Op.getOperand(1);
5419 // Try to match the following pattern:
5420 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5421 // Early exit if we cannot match that sequence.
5422 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5423 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5424 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5425 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5426 Op0.getOperand(1) != Op1.getOperand(1))
5429 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5433 // We found a valid add/sub node. Update the information accordingly.
5439 // Update InVec0 and InVec1.
5440 if (InVec0.getOpcode() == ISD::UNDEF) {
5441 InVec0 = Op0.getOperand(0);
5442 if (InVec0.getValueType() != VT)
5445 if (InVec1.getOpcode() == ISD::UNDEF) {
5446 InVec1 = Op1.getOperand(0);
5447 if (InVec1.getValueType() != VT)
5451 // Make sure that operands in input to each add/sub node always
5452 // come from a same pair of vectors.
5453 if (InVec0 != Op0.getOperand(0)) {
5454 if (ExpectedOpcode == ISD::FSUB)
5457 // FADD is commutable. Try to commute the operands
5458 // and then test again.
5459 std::swap(Op0, Op1);
5460 if (InVec0 != Op0.getOperand(0))
5464 if (InVec1 != Op1.getOperand(0))
5467 // Update the pair of expected opcodes.
5468 std::swap(ExpectedOpcode, NextExpectedOpcode);
5471 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5472 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5473 InVec1.getOpcode() != ISD::UNDEF)
5474 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5479 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5480 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5481 const X86Subtarget *Subtarget,
5482 SelectionDAG &DAG) {
5483 EVT VT = BV->getValueType(0);
5484 unsigned NumElts = VT.getVectorNumElements();
5485 unsigned NumUndefsLO = 0;
5486 unsigned NumUndefsHI = 0;
5487 unsigned Half = NumElts/2;
5489 // Count the number of UNDEF operands in the build_vector in input.
5490 for (unsigned i = 0, e = Half; i != e; ++i)
5491 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5494 for (unsigned i = Half, e = NumElts; i != e; ++i)
5495 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5498 // Early exit if this is either a build_vector of all UNDEFs or all the
5499 // operands but one are UNDEF.
5500 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5504 SDValue InVec0, InVec1;
5505 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5506 // Try to match an SSE3 float HADD/HSUB.
5507 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5508 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5510 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5511 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5512 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5513 // Try to match an SSSE3 integer HADD/HSUB.
5514 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5515 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5517 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5518 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5521 if (!Subtarget->hasAVX())
5524 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5525 // Try to match an AVX horizontal add/sub of packed single/double
5526 // precision floating point values from 256-bit vectors.
5527 SDValue InVec2, InVec3;
5528 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5529 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5530 ((InVec0.getOpcode() == ISD::UNDEF ||
5531 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5532 ((InVec1.getOpcode() == ISD::UNDEF ||
5533 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5534 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5536 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5537 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5538 ((InVec0.getOpcode() == ISD::UNDEF ||
5539 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5540 ((InVec1.getOpcode() == ISD::UNDEF ||
5541 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5542 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5543 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5544 // Try to match an AVX2 horizontal add/sub of signed integers.
5545 SDValue InVec2, InVec3;
5547 bool CanFold = true;
5549 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5550 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5551 ((InVec0.getOpcode() == ISD::UNDEF ||
5552 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5553 ((InVec1.getOpcode() == ISD::UNDEF ||
5554 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5555 X86Opcode = X86ISD::HADD;
5556 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5557 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5558 ((InVec0.getOpcode() == ISD::UNDEF ||
5559 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5560 ((InVec1.getOpcode() == ISD::UNDEF ||
5561 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5562 X86Opcode = X86ISD::HSUB;
5567 // Fold this build_vector into a single horizontal add/sub.
5568 // Do this only if the target has AVX2.
5569 if (Subtarget->hasAVX2())
5570 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5572 // Do not try to expand this build_vector into a pair of horizontal
5573 // add/sub if we can emit a pair of scalar add/sub.
5574 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5577 // Convert this build_vector into a pair of horizontal binop followed by
5579 bool isUndefLO = NumUndefsLO == Half;
5580 bool isUndefHI = NumUndefsHI == Half;
5581 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5582 isUndefLO, isUndefHI);
5586 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5587 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5589 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5590 X86Opcode = X86ISD::HADD;
5591 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5592 X86Opcode = X86ISD::HSUB;
5593 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5594 X86Opcode = X86ISD::FHADD;
5595 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5596 X86Opcode = X86ISD::FHSUB;
5600 // Don't try to expand this build_vector into a pair of horizontal add/sub
5601 // if we can simply emit a pair of scalar add/sub.
5602 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5605 // Convert this build_vector into two horizontal add/sub followed by
5607 bool isUndefLO = NumUndefsLO == Half;
5608 bool isUndefHI = NumUndefsHI == Half;
5609 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5610 isUndefLO, isUndefHI);
5617 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5620 MVT VT = Op.getSimpleValueType();
5621 MVT ExtVT = VT.getVectorElementType();
5622 unsigned NumElems = Op.getNumOperands();
5624 // Generate vectors for predicate vectors.
5625 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5626 return LowerBUILD_VECTORvXi1(Op, DAG);
5628 // Vectors containing all zeros can be matched by pxor and xorps later
5629 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5630 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5631 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5632 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5635 return getZeroVector(VT, Subtarget, DAG, dl);
5638 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5639 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5640 // vpcmpeqd on 256-bit vectors.
5641 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5642 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5645 if (!VT.is512BitVector())
5646 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5649 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5650 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5652 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5653 return HorizontalOp;
5654 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5657 unsigned EVTBits = ExtVT.getSizeInBits();
5659 unsigned NumZero = 0;
5660 unsigned NumNonZero = 0;
5661 unsigned NonZeros = 0;
5662 bool IsAllConstants = true;
5663 SmallSet<SDValue, 8> Values;
5664 for (unsigned i = 0; i < NumElems; ++i) {
5665 SDValue Elt = Op.getOperand(i);
5666 if (Elt.getOpcode() == ISD::UNDEF)
5669 if (Elt.getOpcode() != ISD::Constant &&
5670 Elt.getOpcode() != ISD::ConstantFP)
5671 IsAllConstants = false;
5672 if (X86::isZeroNode(Elt))
5675 NonZeros |= (1 << i);
5680 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5681 if (NumNonZero == 0)
5682 return DAG.getUNDEF(VT);
5684 // Special case for single non-zero, non-undef, element.
5685 if (NumNonZero == 1) {
5686 unsigned Idx = countTrailingZeros(NonZeros);
5687 SDValue Item = Op.getOperand(Idx);
5689 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5690 // the value are obviously zero, truncate the value to i32 and do the
5691 // insertion that way. Only do this if the value is non-constant or if the
5692 // value is a constant being inserted into element 0. It is cheaper to do
5693 // a constant pool load than it is to do a movd + shuffle.
5694 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5695 (!IsAllConstants || Idx == 0)) {
5696 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5698 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5699 EVT VecVT = MVT::v4i32;
5701 // Truncate the value (which may itself be a constant) to i32, and
5702 // convert it to a vector with movd (S2V+shuffle to zero extend).
5703 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5704 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5706 ISD::BITCAST, dl, VT,
5707 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5711 // If we have a constant or non-constant insertion into the low element of
5712 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5713 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5714 // depending on what the source datatype is.
5717 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5719 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5720 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5721 if (VT.is512BitVector()) {
5722 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5723 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5724 Item, DAG.getIntPtrConstant(0));
5726 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5727 "Expected an SSE value type!");
5728 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5729 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5730 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5733 // We can't directly insert an i8 or i16 into a vector, so zero extend
5735 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5736 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5737 if (VT.is256BitVector()) {
5738 if (Subtarget->hasAVX()) {
5739 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5740 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5742 // Without AVX, we need to extend to a 128-bit vector and then
5743 // insert into the 256-bit vector.
5744 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5745 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5746 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5749 assert(VT.is128BitVector() && "Expected an SSE value type!");
5750 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5751 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5753 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5757 // Is it a vector logical left shift?
5758 if (NumElems == 2 && Idx == 1 &&
5759 X86::isZeroNode(Op.getOperand(0)) &&
5760 !X86::isZeroNode(Op.getOperand(1))) {
5761 unsigned NumBits = VT.getSizeInBits();
5762 return getVShift(true, VT,
5763 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5764 VT, Op.getOperand(1)),
5765 NumBits/2, DAG, *this, dl);
5768 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5771 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5772 // is a non-constant being inserted into an element other than the low one,
5773 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5774 // movd/movss) to move this into the low element, then shuffle it into
5776 if (EVTBits == 32) {
5777 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5778 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5782 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5783 if (Values.size() == 1) {
5784 if (EVTBits == 32) {
5785 // Instead of a shuffle like this:
5786 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5787 // Check if it's possible to issue this instead.
5788 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5789 unsigned Idx = countTrailingZeros(NonZeros);
5790 SDValue Item = Op.getOperand(Idx);
5791 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5792 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5797 // A vector full of immediates; various special cases are already
5798 // handled, so this is best done with a single constant-pool load.
5802 // For AVX-length vectors, see if we can use a vector load to get all of the
5803 // elements, otherwise build the individual 128-bit pieces and use
5804 // shuffles to put them in place.
5805 if (VT.is256BitVector() || VT.is512BitVector()) {
5806 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5808 // Check for a build vector of consecutive loads.
5809 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5812 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5814 // Build both the lower and upper subvector.
5815 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5816 makeArrayRef(&V[0], NumElems/2));
5817 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5818 makeArrayRef(&V[NumElems / 2], NumElems/2));
5820 // Recreate the wider vector with the lower and upper part.
5821 if (VT.is256BitVector())
5822 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5823 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5826 // Let legalizer expand 2-wide build_vectors.
5827 if (EVTBits == 64) {
5828 if (NumNonZero == 1) {
5829 // One half is zero or undef.
5830 unsigned Idx = countTrailingZeros(NonZeros);
5831 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5832 Op.getOperand(Idx));
5833 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5838 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5839 if (EVTBits == 8 && NumElems == 16)
5840 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5844 if (EVTBits == 16 && NumElems == 8)
5845 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5849 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5850 if (EVTBits == 32 && NumElems == 4)
5851 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5854 // If element VT is == 32 bits, turn it into a number of shuffles.
5855 SmallVector<SDValue, 8> V(NumElems);
5856 if (NumElems == 4 && NumZero > 0) {
5857 for (unsigned i = 0; i < 4; ++i) {
5858 bool isZero = !(NonZeros & (1 << i));
5860 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5862 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5865 for (unsigned i = 0; i < 2; ++i) {
5866 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5869 V[i] = V[i*2]; // Must be a zero vector.
5872 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5875 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5878 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5883 bool Reverse1 = (NonZeros & 0x3) == 2;
5884 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5888 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5889 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5891 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5894 if (Values.size() > 1 && VT.is128BitVector()) {
5895 // Check for a build vector of consecutive loads.
5896 for (unsigned i = 0; i < NumElems; ++i)
5897 V[i] = Op.getOperand(i);
5899 // Check for elements which are consecutive loads.
5900 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5903 // Check for a build vector from mostly shuffle plus few inserting.
5904 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
5907 // For SSE 4.1, use insertps to put the high elements into the low element.
5908 if (Subtarget->hasSSE41()) {
5910 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5911 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5913 Result = DAG.getUNDEF(VT);
5915 for (unsigned i = 1; i < NumElems; ++i) {
5916 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5917 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5918 Op.getOperand(i), DAG.getIntPtrConstant(i));
5923 // Otherwise, expand into a number of unpckl*, start by extending each of
5924 // our (non-undef) elements to the full vector width with the element in the
5925 // bottom slot of the vector (which generates no code for SSE).
5926 for (unsigned i = 0; i < NumElems; ++i) {
5927 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5928 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5930 V[i] = DAG.getUNDEF(VT);
5933 // Next, we iteratively mix elements, e.g. for v4f32:
5934 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5935 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5936 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5937 unsigned EltStride = NumElems >> 1;
5938 while (EltStride != 0) {
5939 for (unsigned i = 0; i < EltStride; ++i) {
5940 // If V[i+EltStride] is undef and this is the first round of mixing,
5941 // then it is safe to just drop this shuffle: V[i] is already in the
5942 // right place, the one element (since it's the first round) being
5943 // inserted as undef can be dropped. This isn't safe for successive
5944 // rounds because they will permute elements within both vectors.
5945 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5946 EltStride == NumElems/2)
5949 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5958 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5959 // to create 256-bit vectors from two other 128-bit ones.
5960 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5962 MVT ResVT = Op.getSimpleValueType();
5964 assert((ResVT.is256BitVector() ||
5965 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
5967 SDValue V1 = Op.getOperand(0);
5968 SDValue V2 = Op.getOperand(1);
5969 unsigned NumElems = ResVT.getVectorNumElements();
5970 if (ResVT.is256BitVector())
5971 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5973 if (Op.getNumOperands() == 4) {
5974 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
5975 ResVT.getVectorNumElements()/2);
5976 SDValue V3 = Op.getOperand(2);
5977 SDValue V4 = Op.getOperand(3);
5978 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
5979 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
5981 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5984 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
5985 const X86Subtarget *Subtarget,
5986 SelectionDAG & DAG) {
5988 MVT ResVT = Op.getSimpleValueType();
5989 unsigned NumOfOperands = Op.getNumOperands();
5991 assert(isPowerOf2_32(NumOfOperands) &&
5992 "Unexpected number of operands in CONCAT_VECTORS");
5994 if (NumOfOperands > 2) {
5995 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
5996 ResVT.getVectorNumElements()/2);
5997 SmallVector<SDValue, 2> Ops;
5998 for (unsigned i = 0; i < NumOfOperands/2; i++)
5999 Ops.push_back(Op.getOperand(i));
6000 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6002 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6003 Ops.push_back(Op.getOperand(i));
6004 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6005 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6008 SDValue V1 = Op.getOperand(0);
6009 SDValue V2 = Op.getOperand(1);
6010 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6011 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6013 if (IsZeroV1 && IsZeroV2)
6014 return getZeroVector(ResVT, Subtarget, DAG, dl);
6016 SDValue ZeroIdx = DAG.getIntPtrConstant(0);
6017 SDValue Undef = DAG.getUNDEF(ResVT);
6018 unsigned NumElems = ResVT.getVectorNumElements();
6019 SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);
6021 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6022 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6026 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6027 // Zero the upper bits of V1
6028 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6029 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6032 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6035 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6036 const X86Subtarget *Subtarget,
6037 SelectionDAG &DAG) {
6038 MVT VT = Op.getSimpleValueType();
6039 if (VT.getVectorElementType() == MVT::i1)
6040 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6042 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6043 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6044 Op.getNumOperands() == 4)));
6046 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6047 // from two other 128-bit ones.
6049 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6050 return LowerAVXCONCAT_VECTORS(Op, DAG);
6054 //===----------------------------------------------------------------------===//
6055 // Vector shuffle lowering
6057 // This is an experimental code path for lowering vector shuffles on x86. It is
6058 // designed to handle arbitrary vector shuffles and blends, gracefully
6059 // degrading performance as necessary. It works hard to recognize idiomatic
6060 // shuffles and lower them to optimal instruction patterns without leaving
6061 // a framework that allows reasonably efficient handling of all vector shuffle
6063 //===----------------------------------------------------------------------===//
6065 /// \brief Tiny helper function to identify a no-op mask.
6067 /// This is a somewhat boring predicate function. It checks whether the mask
6068 /// array input, which is assumed to be a single-input shuffle mask of the kind
6069 /// used by the X86 shuffle instructions (not a fully general
6070 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6071 /// in-place shuffle are 'no-op's.
6072 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6073 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6074 if (Mask[i] != -1 && Mask[i] != i)
6079 /// \brief Helper function to classify a mask as a single-input mask.
6081 /// This isn't a generic single-input test because in the vector shuffle
6082 /// lowering we canonicalize single inputs to be the first input operand. This
6083 /// means we can more quickly test for a single input by only checking whether
6084 /// an input from the second operand exists. We also assume that the size of
6085 /// mask corresponds to the size of the input vectors which isn't true in the
6086 /// fully general case.
6087 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6089 if (M >= (int)Mask.size())
6094 /// \brief Test whether there are elements crossing 128-bit lanes in this
6097 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6098 /// and we routinely test for these.
6099 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6100 int LaneSize = 128 / VT.getScalarSizeInBits();
6101 int Size = Mask.size();
6102 for (int i = 0; i < Size; ++i)
6103 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6108 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6110 /// This checks a shuffle mask to see if it is performing the same
6111 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6112 /// that it is also not lane-crossing. It may however involve a blend from the
6113 /// same lane of a second vector.
6115 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6116 /// non-trivial to compute in the face of undef lanes. The representation is
6117 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6118 /// entries from both V1 and V2 inputs to the wider mask.
6120 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6121 SmallVectorImpl<int> &RepeatedMask) {
6122 int LaneSize = 128 / VT.getScalarSizeInBits();
6123 RepeatedMask.resize(LaneSize, -1);
6124 int Size = Mask.size();
6125 for (int i = 0; i < Size; ++i) {
6128 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6129 // This entry crosses lanes, so there is no way to model this shuffle.
6132 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6133 if (RepeatedMask[i % LaneSize] == -1)
6134 // This is the first non-undef entry in this slot of a 128-bit lane.
6135 RepeatedMask[i % LaneSize] =
6136 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6137 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6138 // Found a mismatch with the repeated mask.
6144 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6147 /// This is a fast way to test a shuffle mask against a fixed pattern:
6149 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6151 /// It returns true if the mask is exactly as wide as the argument list, and
6152 /// each element of the mask is either -1 (signifying undef) or the value given
6153 /// in the argument.
6154 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6155 ArrayRef<int> ExpectedMask) {
6156 if (Mask.size() != ExpectedMask.size())
6159 int Size = Mask.size();
6161 // If the values are build vectors, we can look through them to find
6162 // equivalent inputs that make the shuffles equivalent.
6163 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6164 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6166 for (int i = 0; i < Size; ++i)
6167 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6168 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6169 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6170 if (!MaskBV || !ExpectedBV ||
6171 MaskBV->getOperand(Mask[i] % Size) !=
6172 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6179 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6181 /// This helper function produces an 8-bit shuffle immediate corresponding to
6182 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6183 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6186 /// NB: We rely heavily on "undef" masks preserving the input lane.
6187 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6188 SelectionDAG &DAG) {
6189 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6190 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6191 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6192 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6193 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6196 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6197 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6198 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6199 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6200 return DAG.getConstant(Imm, MVT::i8);
6203 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6205 /// This is used as a fallback approach when first class blend instructions are
6206 /// unavailable. Currently it is only suitable for integer vectors, but could
6207 /// be generalized for floating point vectors if desirable.
6208 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6209 SDValue V2, ArrayRef<int> Mask,
6210 SelectionDAG &DAG) {
6211 assert(VT.isInteger() && "Only supports integer vector types!");
6212 MVT EltVT = VT.getScalarType();
6213 int NumEltBits = EltVT.getSizeInBits();
6214 SDValue Zero = DAG.getConstant(0, EltVT);
6215 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), EltVT);
6216 SmallVector<SDValue, 16> MaskOps;
6217 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6218 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6219 return SDValue(); // Shuffled input!
6220 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6223 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6224 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6225 // We have to cast V2 around.
6226 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6227 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6228 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6229 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6230 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6231 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6234 /// \brief Try to emit a blend instruction for a shuffle.
6236 /// This doesn't do any checks for the availability of instructions for blending
6237 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6238 /// be matched in the backend with the type given. What it does check for is
6239 /// that the shuffle mask is in fact a blend.
6240 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6241 SDValue V2, ArrayRef<int> Mask,
6242 const X86Subtarget *Subtarget,
6243 SelectionDAG &DAG) {
6244 unsigned BlendMask = 0;
6245 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6246 if (Mask[i] >= Size) {
6247 if (Mask[i] != i + Size)
6248 return SDValue(); // Shuffled V2 input!
6249 BlendMask |= 1u << i;
6252 if (Mask[i] >= 0 && Mask[i] != i)
6253 return SDValue(); // Shuffled V1 input!
6255 switch (VT.SimpleTy) {
6260 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6261 DAG.getConstant(BlendMask, MVT::i8));
6265 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6269 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6270 // that instruction.
6271 if (Subtarget->hasAVX2()) {
6272 // Scale the blend by the number of 32-bit dwords per element.
6273 int Scale = VT.getScalarSizeInBits() / 32;
6275 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6276 if (Mask[i] >= Size)
6277 for (int j = 0; j < Scale; ++j)
6278 BlendMask |= 1u << (i * Scale + j);
6280 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6281 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6282 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6283 return DAG.getNode(ISD::BITCAST, DL, VT,
6284 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6285 DAG.getConstant(BlendMask, MVT::i8)));
6289 // For integer shuffles we need to expand the mask and cast the inputs to
6290 // v8i16s prior to blending.
6291 int Scale = 8 / VT.getVectorNumElements();
6293 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6294 if (Mask[i] >= Size)
6295 for (int j = 0; j < Scale; ++j)
6296 BlendMask |= 1u << (i * Scale + j);
6298 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6299 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6300 return DAG.getNode(ISD::BITCAST, DL, VT,
6301 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6302 DAG.getConstant(BlendMask, MVT::i8)));
6306 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6307 SmallVector<int, 8> RepeatedMask;
6308 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6309 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6310 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6312 for (int i = 0; i < 8; ++i)
6313 if (RepeatedMask[i] >= 16)
6314 BlendMask |= 1u << i;
6315 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6316 DAG.getConstant(BlendMask, MVT::i8));
6322 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6323 "256-bit byte-blends require AVX2 support!");
6325 // Scale the blend by the number of bytes per element.
6326 int Scale = VT.getScalarSizeInBits() / 8;
6328 // This form of blend is always done on bytes. Compute the byte vector
6330 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6332 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6333 // mix of LLVM's code generator and the x86 backend. We tell the code
6334 // generator that boolean values in the elements of an x86 vector register
6335 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6336 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6337 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6338 // of the element (the remaining are ignored) and 0 in that high bit would
6339 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6340 // the LLVM model for boolean values in vector elements gets the relevant
6341 // bit set, it is set backwards and over constrained relative to x86's
6343 SmallVector<SDValue, 32> VSELECTMask;
6344 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6345 for (int j = 0; j < Scale; ++j)
6346 VSELECTMask.push_back(
6347 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6348 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8));
6350 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6351 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6353 ISD::BITCAST, DL, VT,
6354 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6355 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6360 llvm_unreachable("Not a supported integer vector type!");
6364 /// \brief Try to lower as a blend of elements from two inputs followed by
6365 /// a single-input permutation.
6367 /// This matches the pattern where we can blend elements from two inputs and
6368 /// then reduce the shuffle to a single-input permutation.
6369 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6372 SelectionDAG &DAG) {
6373 // We build up the blend mask while checking whether a blend is a viable way
6374 // to reduce the shuffle.
6375 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6376 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6378 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6382 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6384 if (BlendMask[Mask[i] % Size] == -1)
6385 BlendMask[Mask[i] % Size] = Mask[i];
6386 else if (BlendMask[Mask[i] % Size] != Mask[i])
6387 return SDValue(); // Can't blend in the needed input!
6389 PermuteMask[i] = Mask[i] % Size;
6392 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6393 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6396 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6397 /// blends and permutes.
6399 /// This matches the extremely common pattern for handling combined
6400 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6401 /// operations. It will try to pick the best arrangement of shuffles and
6403 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6407 SelectionDAG &DAG) {
6408 // Shuffle the input elements into the desired positions in V1 and V2 and
6409 // blend them together.
6410 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6411 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6412 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6413 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6414 if (Mask[i] >= 0 && Mask[i] < Size) {
6415 V1Mask[i] = Mask[i];
6417 } else if (Mask[i] >= Size) {
6418 V2Mask[i] = Mask[i] - Size;
6419 BlendMask[i] = i + Size;
6422 // Try to lower with the simpler initial blend strategy unless one of the
6423 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6424 // shuffle may be able to fold with a load or other benefit. However, when
6425 // we'll have to do 2x as many shuffles in order to achieve this, blending
6426 // first is a better strategy.
6427 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6428 if (SDValue BlendPerm =
6429 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6432 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6433 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6434 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6437 /// \brief Try to lower a vector shuffle as a byte rotation.
6439 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6440 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6441 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6442 /// try to generically lower a vector shuffle through such an pattern. It
6443 /// does not check for the profitability of lowering either as PALIGNR or
6444 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6445 /// This matches shuffle vectors that look like:
6447 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6449 /// Essentially it concatenates V1 and V2, shifts right by some number of
6450 /// elements, and takes the low elements as the result. Note that while this is
6451 /// specified as a *right shift* because x86 is little-endian, it is a *left
6452 /// rotate* of the vector lanes.
6453 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6456 const X86Subtarget *Subtarget,
6457 SelectionDAG &DAG) {
6458 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6460 int NumElts = Mask.size();
6461 int NumLanes = VT.getSizeInBits() / 128;
6462 int NumLaneElts = NumElts / NumLanes;
6464 // We need to detect various ways of spelling a rotation:
6465 // [11, 12, 13, 14, 15, 0, 1, 2]
6466 // [-1, 12, 13, 14, -1, -1, 1, -1]
6467 // [-1, -1, -1, -1, -1, -1, 1, 2]
6468 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6469 // [-1, 4, 5, 6, -1, -1, 9, -1]
6470 // [-1, 4, 5, 6, -1, -1, -1, -1]
6473 for (int l = 0; l < NumElts; l += NumLaneElts) {
6474 for (int i = 0; i < NumLaneElts; ++i) {
6475 if (Mask[l + i] == -1)
6477 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6479 // Get the mod-Size index and lane correct it.
6480 int LaneIdx = (Mask[l + i] % NumElts) - l;
6481 // Make sure it was in this lane.
6482 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6485 // Determine where a rotated vector would have started.
6486 int StartIdx = i - LaneIdx;
6488 // The identity rotation isn't interesting, stop.
6491 // If we found the tail of a vector the rotation must be the missing
6492 // front. If we found the head of a vector, it must be how much of the
6494 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6497 Rotation = CandidateRotation;
6498 else if (Rotation != CandidateRotation)
6499 // The rotations don't match, so we can't match this mask.
6502 // Compute which value this mask is pointing at.
6503 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6505 // Compute which of the two target values this index should be assigned
6506 // to. This reflects whether the high elements are remaining or the low
6507 // elements are remaining.
6508 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6510 // Either set up this value if we've not encountered it before, or check
6511 // that it remains consistent.
6514 else if (TargetV != MaskV)
6515 // This may be a rotation, but it pulls from the inputs in some
6516 // unsupported interleaving.
6521 // Check that we successfully analyzed the mask, and normalize the results.
6522 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6523 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6529 // The actual rotate instruction rotates bytes, so we need to scale the
6530 // rotation based on how many bytes are in the vector lane.
6531 int Scale = 16 / NumLaneElts;
6533 // SSSE3 targets can use the palignr instruction.
6534 if (Subtarget->hasSSSE3()) {
6535 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6536 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6537 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6538 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6540 return DAG.getNode(ISD::BITCAST, DL, VT,
6541 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6542 DAG.getConstant(Rotation * Scale, MVT::i8)));
6545 assert(VT.getSizeInBits() == 128 &&
6546 "Rotate-based lowering only supports 128-bit lowering!");
6547 assert(Mask.size() <= 16 &&
6548 "Can shuffle at most 16 bytes in a 128-bit vector!");
6550 // Default SSE2 implementation
6551 int LoByteShift = 16 - Rotation * Scale;
6552 int HiByteShift = Rotation * Scale;
6554 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6555 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6556 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6558 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6559 DAG.getConstant(LoByteShift, MVT::i8));
6560 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6561 DAG.getConstant(HiByteShift, MVT::i8));
6562 return DAG.getNode(ISD::BITCAST, DL, VT,
6563 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6566 /// \brief Compute whether each element of a shuffle is zeroable.
6568 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6569 /// Either it is an undef element in the shuffle mask, the element of the input
6570 /// referenced is undef, or the element of the input referenced is known to be
6571 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6572 /// as many lanes with this technique as possible to simplify the remaining
6574 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6575 SDValue V1, SDValue V2) {
6576 SmallBitVector Zeroable(Mask.size(), false);
6578 while (V1.getOpcode() == ISD::BITCAST)
6579 V1 = V1->getOperand(0);
6580 while (V2.getOpcode() == ISD::BITCAST)
6581 V2 = V2->getOperand(0);
6583 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6584 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6586 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6588 // Handle the easy cases.
6589 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6594 // If this is an index into a build_vector node (which has the same number
6595 // of elements), dig out the input value and use it.
6596 SDValue V = M < Size ? V1 : V2;
6597 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6600 SDValue Input = V.getOperand(M % Size);
6601 // The UNDEF opcode check really should be dead code here, but not quite
6602 // worth asserting on (it isn't invalid, just unexpected).
6603 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6610 /// \brief Try to emit a bitmask instruction for a shuffle.
6612 /// This handles cases where we can model a blend exactly as a bitmask due to
6613 /// one of the inputs being zeroable.
6614 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6615 SDValue V2, ArrayRef<int> Mask,
6616 SelectionDAG &DAG) {
6617 MVT EltVT = VT.getScalarType();
6618 int NumEltBits = EltVT.getSizeInBits();
6619 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6620 SDValue Zero = DAG.getConstant(0, IntEltVT);
6621 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), IntEltVT);
6622 if (EltVT.isFloatingPoint()) {
6623 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6624 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6626 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6627 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6629 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6632 if (Mask[i] % Size != i)
6633 return SDValue(); // Not a blend.
6635 V = Mask[i] < Size ? V1 : V2;
6636 else if (V != (Mask[i] < Size ? V1 : V2))
6637 return SDValue(); // Can only let one input through the mask.
6639 VMaskOps[i] = AllOnes;
6642 return SDValue(); // No non-zeroable elements!
6644 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6645 V = DAG.getNode(VT.isFloatingPoint()
6646 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6651 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6653 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6654 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6655 /// matches elements from one of the input vectors shuffled to the left or
6656 /// right with zeroable elements 'shifted in'. It handles both the strictly
6657 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6660 /// PSHL : (little-endian) left bit shift.
6661 /// [ zz, 0, zz, 2 ]
6662 /// [ -1, 4, zz, -1 ]
6663 /// PSRL : (little-endian) right bit shift.
6665 /// [ -1, -1, 7, zz]
6666 /// PSLLDQ : (little-endian) left byte shift
6667 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6668 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6669 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6670 /// PSRLDQ : (little-endian) right byte shift
6671 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6672 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6673 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6674 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6675 SDValue V2, ArrayRef<int> Mask,
6676 SelectionDAG &DAG) {
6677 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6679 int Size = Mask.size();
6680 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6682 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6683 for (int i = 0; i < Size; i += Scale)
6684 for (int j = 0; j < Shift; ++j)
6685 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6691 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6692 for (int i = 0; i != Size; i += Scale) {
6693 unsigned Pos = Left ? i + Shift : i;
6694 unsigned Low = Left ? i : i + Shift;
6695 unsigned Len = Scale - Shift;
6696 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6697 Low + (V == V1 ? 0 : Size)))
6701 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6702 bool ByteShift = ShiftEltBits > 64;
6703 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6704 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6705 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6707 // Normalize the scale for byte shifts to still produce an i64 element
6709 Scale = ByteShift ? Scale / 2 : Scale;
6711 // We need to round trip through the appropriate type for the shift.
6712 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6713 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6714 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6715 "Illegal integer vector type");
6716 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6718 V = DAG.getNode(OpCode, DL, ShiftVT, V, DAG.getConstant(ShiftAmt, MVT::i8));
6719 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6722 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6723 // keep doubling the size of the integer elements up to that. We can
6724 // then shift the elements of the integer vector by whole multiples of
6725 // their width within the elements of the larger integer vector. Test each
6726 // multiple to see if we can find a match with the moved element indices
6727 // and that the shifted in elements are all zeroable.
6728 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6729 for (int Shift = 1; Shift != Scale; ++Shift)
6730 for (bool Left : {true, false})
6731 if (CheckZeros(Shift, Scale, Left))
6732 for (SDValue V : {V1, V2})
6733 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6740 /// \brief Lower a vector shuffle as a zero or any extension.
6742 /// Given a specific number of elements, element bit width, and extension
6743 /// stride, produce either a zero or any extension based on the available
6744 /// features of the subtarget.
6745 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6746 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6747 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6748 assert(Scale > 1 && "Need a scale to extend.");
6749 int NumElements = VT.getVectorNumElements();
6750 int EltBits = VT.getScalarSizeInBits();
6751 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6752 "Only 8, 16, and 32 bit elements can be extended.");
6753 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6755 // Found a valid zext mask! Try various lowering strategies based on the
6756 // input type and available ISA extensions.
6757 if (Subtarget->hasSSE41()) {
6758 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6759 NumElements / Scale);
6760 return DAG.getNode(ISD::BITCAST, DL, VT,
6761 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6764 // For any extends we can cheat for larger element sizes and use shuffle
6765 // instructions that can fold with a load and/or copy.
6766 if (AnyExt && EltBits == 32) {
6767 int PSHUFDMask[4] = {0, -1, 1, -1};
6769 ISD::BITCAST, DL, VT,
6770 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6771 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6772 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
6774 if (AnyExt && EltBits == 16 && Scale > 2) {
6775 int PSHUFDMask[4] = {0, -1, 0, -1};
6776 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6777 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6778 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
6779 int PSHUFHWMask[4] = {1, -1, -1, -1};
6781 ISD::BITCAST, DL, VT,
6782 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6783 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6784 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
6787 // If this would require more than 2 unpack instructions to expand, use
6788 // pshufb when available. We can only use more than 2 unpack instructions
6789 // when zero extending i8 elements which also makes it easier to use pshufb.
6790 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6791 assert(NumElements == 16 && "Unexpected byte vector width!");
6792 SDValue PSHUFBMask[16];
6793 for (int i = 0; i < 16; ++i)
6795 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
6796 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6797 return DAG.getNode(ISD::BITCAST, DL, VT,
6798 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6799 DAG.getNode(ISD::BUILD_VECTOR, DL,
6800 MVT::v16i8, PSHUFBMask)));
6803 // Otherwise emit a sequence of unpacks.
6805 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6806 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6807 : getZeroVector(InputVT, Subtarget, DAG, DL);
6808 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6809 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6813 } while (Scale > 1);
6814 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6817 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6819 /// This routine will try to do everything in its power to cleverly lower
6820 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6821 /// check for the profitability of this lowering, it tries to aggressively
6822 /// match this pattern. It will use all of the micro-architectural details it
6823 /// can to emit an efficient lowering. It handles both blends with all-zero
6824 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6825 /// masking out later).
6827 /// The reason we have dedicated lowering for zext-style shuffles is that they
6828 /// are both incredibly common and often quite performance sensitive.
6829 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6830 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6831 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6832 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6834 int Bits = VT.getSizeInBits();
6835 int NumElements = VT.getVectorNumElements();
6836 assert(VT.getScalarSizeInBits() <= 32 &&
6837 "Exceeds 32-bit integer zero extension limit");
6838 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6840 // Define a helper function to check a particular ext-scale and lower to it if
6842 auto Lower = [&](int Scale) -> SDValue {
6845 for (int i = 0; i < NumElements; ++i) {
6847 continue; // Valid anywhere but doesn't tell us anything.
6848 if (i % Scale != 0) {
6849 // Each of the extended elements need to be zeroable.
6853 // We no longer are in the anyext case.
6858 // Each of the base elements needs to be consecutive indices into the
6859 // same input vector.
6860 SDValue V = Mask[i] < NumElements ? V1 : V2;
6863 else if (InputV != V)
6864 return SDValue(); // Flip-flopping inputs.
6866 if (Mask[i] % NumElements != i / Scale)
6867 return SDValue(); // Non-consecutive strided elements.
6870 // If we fail to find an input, we have a zero-shuffle which should always
6871 // have already been handled.
6872 // FIXME: Maybe handle this here in case during blending we end up with one?
6876 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6877 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6880 // The widest scale possible for extending is to a 64-bit integer.
6881 assert(Bits % 64 == 0 &&
6882 "The number of bits in a vector must be divisible by 64 on x86!");
6883 int NumExtElements = Bits / 64;
6885 // Each iteration, try extending the elements half as much, but into twice as
6887 for (; NumExtElements < NumElements; NumExtElements *= 2) {
6888 assert(NumElements % NumExtElements == 0 &&
6889 "The input vector size must be divisible by the extended size.");
6890 if (SDValue V = Lower(NumElements / NumExtElements))
6894 // General extends failed, but 128-bit vectors may be able to use MOVQ.
6898 // Returns one of the source operands if the shuffle can be reduced to a
6899 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
6900 auto CanZExtLowHalf = [&]() {
6901 for (int i = NumElements / 2; i != NumElements; ++i)
6904 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
6906 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
6911 if (SDValue V = CanZExtLowHalf()) {
6912 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
6913 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
6914 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6917 // No viable ext lowering found.
6921 /// \brief Try to get a scalar value for a specific element of a vector.
6923 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
6924 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
6925 SelectionDAG &DAG) {
6926 MVT VT = V.getSimpleValueType();
6927 MVT EltVT = VT.getVectorElementType();
6928 while (V.getOpcode() == ISD::BITCAST)
6929 V = V.getOperand(0);
6930 // If the bitcasts shift the element size, we can't extract an equivalent
6932 MVT NewVT = V.getSimpleValueType();
6933 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
6936 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6937 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
6938 // Ensure the scalar operand is the same size as the destination.
6939 // FIXME: Add support for scalar truncation where possible.
6940 SDValue S = V.getOperand(Idx);
6941 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
6942 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
6948 /// \brief Helper to test for a load that can be folded with x86 shuffles.
6950 /// This is particularly important because the set of instructions varies
6951 /// significantly based on whether the operand is a load or not.
6952 static bool isShuffleFoldableLoad(SDValue V) {
6953 while (V.getOpcode() == ISD::BITCAST)
6954 V = V.getOperand(0);
6956 return ISD::isNON_EXTLoad(V.getNode());
6959 /// \brief Try to lower insertion of a single element into a zero vector.
6961 /// This is a common pattern that we have especially efficient patterns to lower
6962 /// across all subtarget feature sets.
6963 static SDValue lowerVectorShuffleAsElementInsertion(
6964 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6965 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6966 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6968 MVT EltVT = VT.getVectorElementType();
6970 int V2Index = std::find_if(Mask.begin(), Mask.end(),
6971 [&Mask](int M) { return M >= (int)Mask.size(); }) -
6973 bool IsV1Zeroable = true;
6974 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6975 if (i != V2Index && !Zeroable[i]) {
6976 IsV1Zeroable = false;
6980 // Check for a single input from a SCALAR_TO_VECTOR node.
6981 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
6982 // all the smarts here sunk into that routine. However, the current
6983 // lowering of BUILD_VECTOR makes that nearly impossible until the old
6984 // vector shuffle lowering is dead.
6985 if (SDValue V2S = getScalarValueForVectorElement(
6986 V2, Mask[V2Index] - Mask.size(), DAG)) {
6987 // We need to zext the scalar if it is smaller than an i32.
6988 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
6989 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
6990 // Using zext to expand a narrow element won't work for non-zero
6995 // Zero-extend directly to i32.
6997 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
6999 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7000 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7001 EltVT == MVT::i16) {
7002 // Either not inserting from the low element of the input or the input
7003 // element size is too small to use VZEXT_MOVL to clear the high bits.
7007 if (!IsV1Zeroable) {
7008 // If V1 can't be treated as a zero vector we have fewer options to lower
7009 // this. We can't support integer vectors or non-zero targets cheaply, and
7010 // the V1 elements can't be permuted in any way.
7011 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7012 if (!VT.isFloatingPoint() || V2Index != 0)
7014 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7015 V1Mask[V2Index] = -1;
7016 if (!isNoopShuffleMask(V1Mask))
7018 // This is essentially a special case blend operation, but if we have
7019 // general purpose blend operations, they are always faster. Bail and let
7020 // the rest of the lowering handle these as blends.
7021 if (Subtarget->hasSSE41())
7024 // Otherwise, use MOVSD or MOVSS.
7025 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7026 "Only two types of floating point element types to handle!");
7027 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7031 // This lowering only works for the low element with floating point vectors.
7032 if (VT.isFloatingPoint() && V2Index != 0)
7035 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7037 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7040 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7041 // the desired position. Otherwise it is more efficient to do a vector
7042 // shift left. We know that we can do a vector shift left because all
7043 // the inputs are zero.
7044 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7045 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7046 V2Shuffle[V2Index] = 0;
7047 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7049 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7051 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7053 V2Index * EltVT.getSizeInBits()/8,
7054 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7055 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7061 /// \brief Try to lower broadcast of a single element.
7063 /// For convenience, this code also bundles all of the subtarget feature set
7064 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7065 /// a convenient way to factor it out.
7066 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7068 const X86Subtarget *Subtarget,
7069 SelectionDAG &DAG) {
7070 if (!Subtarget->hasAVX())
7072 if (VT.isInteger() && !Subtarget->hasAVX2())
7075 // Check that the mask is a broadcast.
7076 int BroadcastIdx = -1;
7078 if (M >= 0 && BroadcastIdx == -1)
7080 else if (M >= 0 && M != BroadcastIdx)
7083 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7084 "a sorted mask where the broadcast "
7087 // Go up the chain of (vector) values to find a scalar load that we can
7088 // combine with the broadcast.
7090 switch (V.getOpcode()) {
7091 case ISD::CONCAT_VECTORS: {
7092 int OperandSize = Mask.size() / V.getNumOperands();
7093 V = V.getOperand(BroadcastIdx / OperandSize);
7094 BroadcastIdx %= OperandSize;
7098 case ISD::INSERT_SUBVECTOR: {
7099 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7100 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7104 int BeginIdx = (int)ConstantIdx->getZExtValue();
7106 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7107 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7108 BroadcastIdx -= BeginIdx;
7119 // Check if this is a broadcast of a scalar. We special case lowering
7120 // for scalars so that we can more effectively fold with loads.
7121 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7122 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7123 V = V.getOperand(BroadcastIdx);
7125 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7126 // Only AVX2 has register broadcasts.
7127 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7129 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7130 // We can't broadcast from a vector register without AVX2, and we can only
7131 // broadcast from the zero-element of a vector register.
7135 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7138 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7139 // INSERTPS when the V1 elements are already in the correct locations
7140 // because otherwise we can just always use two SHUFPS instructions which
7141 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7142 // perform INSERTPS if a single V1 element is out of place and all V2
7143 // elements are zeroable.
7144 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7146 SelectionDAG &DAG) {
7147 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7148 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7149 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7150 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7152 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7155 int V1DstIndex = -1;
7156 int V2DstIndex = -1;
7157 bool V1UsedInPlace = false;
7159 for (int i = 0; i < 4; ++i) {
7160 // Synthesize a zero mask from the zeroable elements (includes undefs).
7166 // Flag if we use any V1 inputs in place.
7168 V1UsedInPlace = true;
7172 // We can only insert a single non-zeroable element.
7173 if (V1DstIndex != -1 || V2DstIndex != -1)
7177 // V1 input out of place for insertion.
7180 // V2 input for insertion.
7185 // Don't bother if we have no (non-zeroable) element for insertion.
7186 if (V1DstIndex == -1 && V2DstIndex == -1)
7189 // Determine element insertion src/dst indices. The src index is from the
7190 // start of the inserted vector, not the start of the concatenated vector.
7191 unsigned V2SrcIndex = 0;
7192 if (V1DstIndex != -1) {
7193 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7194 // and don't use the original V2 at all.
7195 V2SrcIndex = Mask[V1DstIndex];
7196 V2DstIndex = V1DstIndex;
7199 V2SrcIndex = Mask[V2DstIndex] - 4;
7202 // If no V1 inputs are used in place, then the result is created only from
7203 // the zero mask and the V2 insertion - so remove V1 dependency.
7205 V1 = DAG.getUNDEF(MVT::v4f32);
7207 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7208 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7210 // Insert the V2 element into the desired position.
7212 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7213 DAG.getConstant(InsertPSMask, MVT::i8));
7216 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7217 /// UNPCK instruction.
7219 /// This specifically targets cases where we end up with alternating between
7220 /// the two inputs, and so can permute them into something that feeds a single
7221 /// UNPCK instruction. Note that this routine only targets integer vectors
7222 /// because for floating point vectors we have a generalized SHUFPS lowering
7223 /// strategy that handles everything that doesn't *exactly* match an unpack,
7224 /// making this clever lowering unnecessary.
7225 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7226 SDValue V2, ArrayRef<int> Mask,
7227 SelectionDAG &DAG) {
7228 assert(!VT.isFloatingPoint() &&
7229 "This routine only supports integer vectors.");
7230 assert(!isSingleInputShuffleMask(Mask) &&
7231 "This routine should only be used when blending two inputs.");
7232 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7234 int Size = Mask.size();
7236 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7237 return M >= 0 && M % Size < Size / 2;
7239 int NumHiInputs = std::count_if(
7240 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7242 bool UnpackLo = NumLoInputs >= NumHiInputs;
7244 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7245 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7246 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7248 for (int i = 0; i < Size; ++i) {
7252 // Each element of the unpack contains Scale elements from this mask.
7253 int UnpackIdx = i / Scale;
7255 // We only handle the case where V1 feeds the first slots of the unpack.
7256 // We rely on canonicalization to ensure this is the case.
7257 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7260 // Setup the mask for this input. The indexing is tricky as we have to
7261 // handle the unpack stride.
7262 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7263 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7267 // If we will have to shuffle both inputs to use the unpack, check whether
7268 // we can just unpack first and shuffle the result. If so, skip this unpack.
7269 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7270 !isNoopShuffleMask(V2Mask))
7273 // Shuffle the inputs into place.
7274 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7275 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7277 // Cast the inputs to the type we will use to unpack them.
7278 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7279 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7281 // Unpack the inputs and cast the result back to the desired type.
7282 return DAG.getNode(ISD::BITCAST, DL, VT,
7283 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7284 DL, UnpackVT, V1, V2));
7287 // We try each unpack from the largest to the smallest to try and find one
7288 // that fits this mask.
7289 int OrigNumElements = VT.getVectorNumElements();
7290 int OrigScalarSize = VT.getScalarSizeInBits();
7291 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7292 int Scale = ScalarSize / OrigScalarSize;
7293 int NumElements = OrigNumElements / Scale;
7294 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7295 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7299 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7301 if (NumLoInputs == 0 || NumHiInputs == 0) {
7302 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7303 "We have to have *some* inputs!");
7304 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7306 // FIXME: We could consider the total complexity of the permute of each
7307 // possible unpacking. Or at the least we should consider how many
7308 // half-crossings are created.
7309 // FIXME: We could consider commuting the unpacks.
7311 SmallVector<int, 32> PermMask;
7312 PermMask.assign(Size, -1);
7313 for (int i = 0; i < Size; ++i) {
7317 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7320 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7322 return DAG.getVectorShuffle(
7323 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7325 DAG.getUNDEF(VT), PermMask);
7331 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7333 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7334 /// support for floating point shuffles but not integer shuffles. These
7335 /// instructions will incur a domain crossing penalty on some chips though so
7336 /// it is better to avoid lowering through this for integer vectors where
7338 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7339 const X86Subtarget *Subtarget,
7340 SelectionDAG &DAG) {
7342 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7343 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7344 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7345 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7346 ArrayRef<int> Mask = SVOp->getMask();
7347 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7349 if (isSingleInputShuffleMask(Mask)) {
7350 // Use low duplicate instructions for masks that match their pattern.
7351 if (Subtarget->hasSSE3())
7352 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7353 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7355 // Straight shuffle of a single input vector. Simulate this by using the
7356 // single input as both of the "inputs" to this instruction..
7357 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7359 if (Subtarget->hasAVX()) {
7360 // If we have AVX, we can use VPERMILPS which will allow folding a load
7361 // into the shuffle.
7362 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7363 DAG.getConstant(SHUFPDMask, MVT::i8));
7366 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7367 DAG.getConstant(SHUFPDMask, MVT::i8));
7369 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7370 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7372 // If we have a single input, insert that into V1 if we can do so cheaply.
7373 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7374 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7375 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7377 // Try inverting the insertion since for v2 masks it is easy to do and we
7378 // can't reliably sort the mask one way or the other.
7379 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7380 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7381 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7382 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7386 // Try to use one of the special instruction patterns to handle two common
7387 // blend patterns if a zero-blend above didn't work.
7388 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7389 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7390 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7391 // We can either use a special instruction to load over the low double or
7392 // to move just the low double.
7394 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7396 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7398 if (Subtarget->hasSSE41())
7399 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7403 // Use dedicated unpack instructions for masks that match their pattern.
7404 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7405 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7406 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7407 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7409 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7410 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7411 DAG.getConstant(SHUFPDMask, MVT::i8));
7414 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7416 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7417 /// the integer unit to minimize domain crossing penalties. However, for blends
7418 /// it falls back to the floating point shuffle operation with appropriate bit
7420 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7421 const X86Subtarget *Subtarget,
7422 SelectionDAG &DAG) {
7424 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7425 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7426 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7427 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7428 ArrayRef<int> Mask = SVOp->getMask();
7429 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7431 if (isSingleInputShuffleMask(Mask)) {
7432 // Check for being able to broadcast a single element.
7433 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7434 Mask, Subtarget, DAG))
7437 // Straight shuffle of a single input vector. For everything from SSE2
7438 // onward this has a single fast instruction with no scary immediates.
7439 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7440 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7441 int WidenedMask[4] = {
7442 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7443 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7445 ISD::BITCAST, DL, MVT::v2i64,
7446 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7447 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7449 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7450 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7451 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7452 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7454 // If we have a blend of two PACKUS operations an the blend aligns with the
7455 // low and half halves, we can just merge the PACKUS operations. This is
7456 // particularly important as it lets us merge shuffles that this routine itself
7458 auto GetPackNode = [](SDValue V) {
7459 while (V.getOpcode() == ISD::BITCAST)
7460 V = V.getOperand(0);
7462 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7464 if (SDValue V1Pack = GetPackNode(V1))
7465 if (SDValue V2Pack = GetPackNode(V2))
7466 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7467 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7468 Mask[0] == 0 ? V1Pack.getOperand(0)
7469 : V1Pack.getOperand(1),
7470 Mask[1] == 2 ? V2Pack.getOperand(0)
7471 : V2Pack.getOperand(1)));
7473 // Try to use shift instructions.
7475 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7478 // When loading a scalar and then shuffling it into a vector we can often do
7479 // the insertion cheaply.
7480 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7481 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7483 // Try inverting the insertion since for v2 masks it is easy to do and we
7484 // can't reliably sort the mask one way or the other.
7485 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7486 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7487 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7490 // We have different paths for blend lowering, but they all must use the
7491 // *exact* same predicate.
7492 bool IsBlendSupported = Subtarget->hasSSE41();
7493 if (IsBlendSupported)
7494 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7498 // Use dedicated unpack instructions for masks that match their pattern.
7499 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7500 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7501 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7502 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7504 // Try to use byte rotation instructions.
7505 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7506 if (Subtarget->hasSSSE3())
7507 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7508 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7511 // If we have direct support for blends, we should lower by decomposing into
7512 // a permute. That will be faster than the domain cross.
7513 if (IsBlendSupported)
7514 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7517 // We implement this with SHUFPD which is pretty lame because it will likely
7518 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7519 // However, all the alternatives are still more cycles and newer chips don't
7520 // have this problem. It would be really nice if x86 had better shuffles here.
7521 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7522 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7523 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7524 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7527 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7529 /// This is used to disable more specialized lowerings when the shufps lowering
7530 /// will happen to be efficient.
7531 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7532 // This routine only handles 128-bit shufps.
7533 assert(Mask.size() == 4 && "Unsupported mask size!");
7535 // To lower with a single SHUFPS we need to have the low half and high half
7536 // each requiring a single input.
7537 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7539 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7545 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7547 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7548 /// It makes no assumptions about whether this is the *best* lowering, it simply
7550 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7551 ArrayRef<int> Mask, SDValue V1,
7552 SDValue V2, SelectionDAG &DAG) {
7553 SDValue LowV = V1, HighV = V2;
7554 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7557 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7559 if (NumV2Elements == 1) {
7561 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7564 // Compute the index adjacent to V2Index and in the same half by toggling
7566 int V2AdjIndex = V2Index ^ 1;
7568 if (Mask[V2AdjIndex] == -1) {
7569 // Handles all the cases where we have a single V2 element and an undef.
7570 // This will only ever happen in the high lanes because we commute the
7571 // vector otherwise.
7573 std::swap(LowV, HighV);
7574 NewMask[V2Index] -= 4;
7576 // Handle the case where the V2 element ends up adjacent to a V1 element.
7577 // To make this work, blend them together as the first step.
7578 int V1Index = V2AdjIndex;
7579 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7580 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7581 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7583 // Now proceed to reconstruct the final blend as we have the necessary
7584 // high or low half formed.
7591 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7592 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7594 } else if (NumV2Elements == 2) {
7595 if (Mask[0] < 4 && Mask[1] < 4) {
7596 // Handle the easy case where we have V1 in the low lanes and V2 in the
7600 } else if (Mask[2] < 4 && Mask[3] < 4) {
7601 // We also handle the reversed case because this utility may get called
7602 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7603 // arrange things in the right direction.
7609 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7610 // trying to place elements directly, just blend them and set up the final
7611 // shuffle to place them.
7613 // The first two blend mask elements are for V1, the second two are for
7615 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7616 Mask[2] < 4 ? Mask[2] : Mask[3],
7617 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7618 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7619 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7620 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7622 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7625 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7626 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7627 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7628 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7631 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7632 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7635 /// \brief Lower 4-lane 32-bit floating point shuffles.
7637 /// Uses instructions exclusively from the floating point unit to minimize
7638 /// domain crossing penalties, as these are sufficient to implement all v4f32
7640 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7641 const X86Subtarget *Subtarget,
7642 SelectionDAG &DAG) {
7644 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7645 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7646 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7647 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7648 ArrayRef<int> Mask = SVOp->getMask();
7649 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7652 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7654 if (NumV2Elements == 0) {
7655 // Check for being able to broadcast a single element.
7656 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7657 Mask, Subtarget, DAG))
7660 // Use even/odd duplicate instructions for masks that match their pattern.
7661 if (Subtarget->hasSSE3()) {
7662 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7663 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7664 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7665 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7668 if (Subtarget->hasAVX()) {
7669 // If we have AVX, we can use VPERMILPS which will allow folding a load
7670 // into the shuffle.
7671 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7672 getV4X86ShuffleImm8ForMask(Mask, DAG));
7675 // Otherwise, use a straight shuffle of a single input vector. We pass the
7676 // input vector to both operands to simulate this with a SHUFPS.
7677 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7678 getV4X86ShuffleImm8ForMask(Mask, DAG));
7681 // There are special ways we can lower some single-element blends. However, we
7682 // have custom ways we can lower more complex single-element blends below that
7683 // we defer to if both this and BLENDPS fail to match, so restrict this to
7684 // when the V2 input is targeting element 0 of the mask -- that is the fast
7686 if (NumV2Elements == 1 && Mask[0] >= 4)
7687 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7688 Mask, Subtarget, DAG))
7691 if (Subtarget->hasSSE41()) {
7692 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7696 // Use INSERTPS if we can complete the shuffle efficiently.
7697 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7700 if (!isSingleSHUFPSMask(Mask))
7701 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7702 DL, MVT::v4f32, V1, V2, Mask, DAG))
7706 // Use dedicated unpack instructions for masks that match their pattern.
7707 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7708 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7709 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7710 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7711 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7712 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7713 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7714 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7716 // Otherwise fall back to a SHUFPS lowering strategy.
7717 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7720 /// \brief Lower 4-lane i32 vector shuffles.
7722 /// We try to handle these with integer-domain shuffles where we can, but for
7723 /// blends we use the floating point domain blend instructions.
7724 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7725 const X86Subtarget *Subtarget,
7726 SelectionDAG &DAG) {
7728 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7729 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7730 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7731 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7732 ArrayRef<int> Mask = SVOp->getMask();
7733 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7735 // Whenever we can lower this as a zext, that instruction is strictly faster
7736 // than any alternative. It also allows us to fold memory operands into the
7737 // shuffle in many cases.
7738 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7739 Mask, Subtarget, DAG))
7743 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7745 if (NumV2Elements == 0) {
7746 // Check for being able to broadcast a single element.
7747 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7748 Mask, Subtarget, DAG))
7751 // Straight shuffle of a single input vector. For everything from SSE2
7752 // onward this has a single fast instruction with no scary immediates.
7753 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7754 // but we aren't actually going to use the UNPCK instruction because doing
7755 // so prevents folding a load into this instruction or making a copy.
7756 const int UnpackLoMask[] = {0, 0, 1, 1};
7757 const int UnpackHiMask[] = {2, 2, 3, 3};
7758 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7759 Mask = UnpackLoMask;
7760 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7761 Mask = UnpackHiMask;
7763 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7764 getV4X86ShuffleImm8ForMask(Mask, DAG));
7767 // Try to use shift instructions.
7769 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7772 // There are special ways we can lower some single-element blends.
7773 if (NumV2Elements == 1)
7774 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7775 Mask, Subtarget, DAG))
7778 // We have different paths for blend lowering, but they all must use the
7779 // *exact* same predicate.
7780 bool IsBlendSupported = Subtarget->hasSSE41();
7781 if (IsBlendSupported)
7782 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7786 if (SDValue Masked =
7787 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7790 // Use dedicated unpack instructions for masks that match their pattern.
7791 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7792 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7793 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7794 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7795 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7796 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7797 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7798 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7800 // Try to use byte rotation instructions.
7801 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7802 if (Subtarget->hasSSSE3())
7803 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7804 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7807 // If we have direct support for blends, we should lower by decomposing into
7808 // a permute. That will be faster than the domain cross.
7809 if (IsBlendSupported)
7810 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7813 // Try to lower by permuting the inputs into an unpack instruction.
7814 if (SDValue Unpack =
7815 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7818 // We implement this with SHUFPS because it can blend from two vectors.
7819 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7820 // up the inputs, bypassing domain shift penalties that we would encur if we
7821 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7823 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7824 DAG.getVectorShuffle(
7826 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7827 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7830 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7831 /// shuffle lowering, and the most complex part.
7833 /// The lowering strategy is to try to form pairs of input lanes which are
7834 /// targeted at the same half of the final vector, and then use a dword shuffle
7835 /// to place them onto the right half, and finally unpack the paired lanes into
7836 /// their final position.
7838 /// The exact breakdown of how to form these dword pairs and align them on the
7839 /// correct sides is really tricky. See the comments within the function for
7840 /// more of the details.
7842 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7843 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7844 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7845 /// vector, form the analogous 128-bit 8-element Mask.
7846 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7847 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7848 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7849 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7850 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7852 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7853 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7854 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7856 SmallVector<int, 4> LoInputs;
7857 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7858 [](int M) { return M >= 0; });
7859 std::sort(LoInputs.begin(), LoInputs.end());
7860 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7861 SmallVector<int, 4> HiInputs;
7862 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7863 [](int M) { return M >= 0; });
7864 std::sort(HiInputs.begin(), HiInputs.end());
7865 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7867 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7868 int NumHToL = LoInputs.size() - NumLToL;
7870 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7871 int NumHToH = HiInputs.size() - NumLToH;
7872 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7873 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7874 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7875 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7877 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7878 // such inputs we can swap two of the dwords across the half mark and end up
7879 // with <=2 inputs to each half in each half. Once there, we can fall through
7880 // to the generic code below. For example:
7882 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7883 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7885 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7886 // and an existing 2-into-2 on the other half. In this case we may have to
7887 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7888 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7889 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7890 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7891 // half than the one we target for fixing) will be fixed when we re-enter this
7892 // path. We will also combine away any sequence of PSHUFD instructions that
7893 // result into a single instruction. Here is an example of the tricky case:
7895 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7896 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7898 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7900 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7901 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7903 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7904 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7906 // The result is fine to be handled by the generic logic.
7907 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7908 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7909 int AOffset, int BOffset) {
7910 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7911 "Must call this with A having 3 or 1 inputs from the A half.");
7912 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7913 "Must call this with B having 1 or 3 inputs from the B half.");
7914 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7915 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7917 // Compute the index of dword with only one word among the three inputs in
7918 // a half by taking the sum of the half with three inputs and subtracting
7919 // the sum of the actual three inputs. The difference is the remaining
7922 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7923 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7924 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7925 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7926 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7927 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7928 int TripleNonInputIdx =
7929 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7930 TripleDWord = TripleNonInputIdx / 2;
7932 // We use xor with one to compute the adjacent DWord to whichever one the
7934 OneInputDWord = (OneInput / 2) ^ 1;
7936 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7937 // and BToA inputs. If there is also such a problem with the BToB and AToB
7938 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7939 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7940 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7941 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7942 // Compute how many inputs will be flipped by swapping these DWords. We
7944 // to balance this to ensure we don't form a 3-1 shuffle in the other
7946 int NumFlippedAToBInputs =
7947 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7948 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7949 int NumFlippedBToBInputs =
7950 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7951 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7952 if ((NumFlippedAToBInputs == 1 &&
7953 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7954 (NumFlippedBToBInputs == 1 &&
7955 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7956 // We choose whether to fix the A half or B half based on whether that
7957 // half has zero flipped inputs. At zero, we may not be able to fix it
7958 // with that half. We also bias towards fixing the B half because that
7959 // will more commonly be the high half, and we have to bias one way.
7960 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7961 ArrayRef<int> Inputs) {
7962 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7963 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7964 PinnedIdx ^ 1) != Inputs.end();
7965 // Determine whether the free index is in the flipped dword or the
7966 // unflipped dword based on where the pinned index is. We use this bit
7967 // in an xor to conditionally select the adjacent dword.
7968 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7969 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7970 FixFreeIdx) != Inputs.end();
7971 if (IsFixIdxInput == IsFixFreeIdxInput)
7973 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7974 FixFreeIdx) != Inputs.end();
7975 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7976 "We need to be changing the number of flipped inputs!");
7977 int PSHUFHalfMask[] = {0, 1, 2, 3};
7978 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7979 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7981 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7984 if (M != -1 && M == FixIdx)
7986 else if (M != -1 && M == FixFreeIdx)
7989 if (NumFlippedBToBInputs != 0) {
7991 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7992 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7994 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7996 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7997 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8002 int PSHUFDMask[] = {0, 1, 2, 3};
8003 PSHUFDMask[ADWord] = BDWord;
8004 PSHUFDMask[BDWord] = ADWord;
8005 V = DAG.getNode(ISD::BITCAST, DL, VT,
8006 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8007 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8008 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8010 // Adjust the mask to match the new locations of A and B.
8012 if (M != -1 && M/2 == ADWord)
8013 M = 2 * BDWord + M % 2;
8014 else if (M != -1 && M/2 == BDWord)
8015 M = 2 * ADWord + M % 2;
8017 // Recurse back into this routine to re-compute state now that this isn't
8018 // a 3 and 1 problem.
8019 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8022 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8023 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8024 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8025 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8027 // At this point there are at most two inputs to the low and high halves from
8028 // each half. That means the inputs can always be grouped into dwords and
8029 // those dwords can then be moved to the correct half with a dword shuffle.
8030 // We use at most one low and one high word shuffle to collect these paired
8031 // inputs into dwords, and finally a dword shuffle to place them.
8032 int PSHUFLMask[4] = {-1, -1, -1, -1};
8033 int PSHUFHMask[4] = {-1, -1, -1, -1};
8034 int PSHUFDMask[4] = {-1, -1, -1, -1};
8036 // First fix the masks for all the inputs that are staying in their
8037 // original halves. This will then dictate the targets of the cross-half
8039 auto fixInPlaceInputs =
8040 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8041 MutableArrayRef<int> SourceHalfMask,
8042 MutableArrayRef<int> HalfMask, int HalfOffset) {
8043 if (InPlaceInputs.empty())
8045 if (InPlaceInputs.size() == 1) {
8046 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8047 InPlaceInputs[0] - HalfOffset;
8048 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8051 if (IncomingInputs.empty()) {
8052 // Just fix all of the in place inputs.
8053 for (int Input : InPlaceInputs) {
8054 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8055 PSHUFDMask[Input / 2] = Input / 2;
8060 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8061 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8062 InPlaceInputs[0] - HalfOffset;
8063 // Put the second input next to the first so that they are packed into
8064 // a dword. We find the adjacent index by toggling the low bit.
8065 int AdjIndex = InPlaceInputs[0] ^ 1;
8066 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8067 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8068 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8070 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8071 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8073 // Now gather the cross-half inputs and place them into a free dword of
8074 // their target half.
8075 // FIXME: This operation could almost certainly be simplified dramatically to
8076 // look more like the 3-1 fixing operation.
8077 auto moveInputsToRightHalf = [&PSHUFDMask](
8078 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8079 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8080 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8082 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8083 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8085 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8087 int LowWord = Word & ~1;
8088 int HighWord = Word | 1;
8089 return isWordClobbered(SourceHalfMask, LowWord) ||
8090 isWordClobbered(SourceHalfMask, HighWord);
8093 if (IncomingInputs.empty())
8096 if (ExistingInputs.empty()) {
8097 // Map any dwords with inputs from them into the right half.
8098 for (int Input : IncomingInputs) {
8099 // If the source half mask maps over the inputs, turn those into
8100 // swaps and use the swapped lane.
8101 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8102 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8103 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8104 Input - SourceOffset;
8105 // We have to swap the uses in our half mask in one sweep.
8106 for (int &M : HalfMask)
8107 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8109 else if (M == Input)
8110 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8112 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8113 Input - SourceOffset &&
8114 "Previous placement doesn't match!");
8116 // Note that this correctly re-maps both when we do a swap and when
8117 // we observe the other side of the swap above. We rely on that to
8118 // avoid swapping the members of the input list directly.
8119 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8122 // Map the input's dword into the correct half.
8123 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8124 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8126 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8128 "Previous placement doesn't match!");
8131 // And just directly shift any other-half mask elements to be same-half
8132 // as we will have mirrored the dword containing the element into the
8133 // same position within that half.
8134 for (int &M : HalfMask)
8135 if (M >= SourceOffset && M < SourceOffset + 4) {
8136 M = M - SourceOffset + DestOffset;
8137 assert(M >= 0 && "This should never wrap below zero!");
8142 // Ensure we have the input in a viable dword of its current half. This
8143 // is particularly tricky because the original position may be clobbered
8144 // by inputs being moved and *staying* in that half.
8145 if (IncomingInputs.size() == 1) {
8146 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8147 int InputFixed = std::find(std::begin(SourceHalfMask),
8148 std::end(SourceHalfMask), -1) -
8149 std::begin(SourceHalfMask) + SourceOffset;
8150 SourceHalfMask[InputFixed - SourceOffset] =
8151 IncomingInputs[0] - SourceOffset;
8152 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8154 IncomingInputs[0] = InputFixed;
8156 } else if (IncomingInputs.size() == 2) {
8157 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8158 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8159 // We have two non-adjacent or clobbered inputs we need to extract from
8160 // the source half. To do this, we need to map them into some adjacent
8161 // dword slot in the source mask.
8162 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8163 IncomingInputs[1] - SourceOffset};
8165 // If there is a free slot in the source half mask adjacent to one of
8166 // the inputs, place the other input in it. We use (Index XOR 1) to
8167 // compute an adjacent index.
8168 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8169 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8170 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8171 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8172 InputsFixed[1] = InputsFixed[0] ^ 1;
8173 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8174 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8175 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8176 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8177 InputsFixed[0] = InputsFixed[1] ^ 1;
8178 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8179 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8180 // The two inputs are in the same DWord but it is clobbered and the
8181 // adjacent DWord isn't used at all. Move both inputs to the free
8183 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8184 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8185 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8186 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8188 // The only way we hit this point is if there is no clobbering
8189 // (because there are no off-half inputs to this half) and there is no
8190 // free slot adjacent to one of the inputs. In this case, we have to
8191 // swap an input with a non-input.
8192 for (int i = 0; i < 4; ++i)
8193 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8194 "We can't handle any clobbers here!");
8195 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8196 "Cannot have adjacent inputs here!");
8198 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8199 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8201 // We also have to update the final source mask in this case because
8202 // it may need to undo the above swap.
8203 for (int &M : FinalSourceHalfMask)
8204 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8205 M = InputsFixed[1] + SourceOffset;
8206 else if (M == InputsFixed[1] + SourceOffset)
8207 M = (InputsFixed[0] ^ 1) + SourceOffset;
8209 InputsFixed[1] = InputsFixed[0] ^ 1;
8212 // Point everything at the fixed inputs.
8213 for (int &M : HalfMask)
8214 if (M == IncomingInputs[0])
8215 M = InputsFixed[0] + SourceOffset;
8216 else if (M == IncomingInputs[1])
8217 M = InputsFixed[1] + SourceOffset;
8219 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8220 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8223 llvm_unreachable("Unhandled input size!");
8226 // Now hoist the DWord down to the right half.
8227 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8228 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8229 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8230 for (int &M : HalfMask)
8231 for (int Input : IncomingInputs)
8233 M = FreeDWord * 2 + Input % 2;
8235 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8236 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8237 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8238 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8240 // Now enact all the shuffles we've computed to move the inputs into their
8242 if (!isNoopShuffleMask(PSHUFLMask))
8243 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8244 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8245 if (!isNoopShuffleMask(PSHUFHMask))
8246 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8247 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8248 if (!isNoopShuffleMask(PSHUFDMask))
8249 V = DAG.getNode(ISD::BITCAST, DL, VT,
8250 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8251 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8252 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8254 // At this point, each half should contain all its inputs, and we can then
8255 // just shuffle them into their final position.
8256 assert(std::count_if(LoMask.begin(), LoMask.end(),
8257 [](int M) { return M >= 4; }) == 0 &&
8258 "Failed to lift all the high half inputs to the low mask!");
8259 assert(std::count_if(HiMask.begin(), HiMask.end(),
8260 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8261 "Failed to lift all the low half inputs to the high mask!");
8263 // Do a half shuffle for the low mask.
8264 if (!isNoopShuffleMask(LoMask))
8265 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8266 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8268 // Do a half shuffle with the high mask after shifting its values down.
8269 for (int &M : HiMask)
8272 if (!isNoopShuffleMask(HiMask))
8273 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8274 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8279 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8280 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8281 SDValue V2, ArrayRef<int> Mask,
8282 SelectionDAG &DAG, bool &V1InUse,
8284 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8290 int Size = Mask.size();
8291 int Scale = 16 / Size;
8292 for (int i = 0; i < 16; ++i) {
8293 if (Mask[i / Scale] == -1) {
8294 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8296 const int ZeroMask = 0x80;
8297 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8299 int V2Idx = Mask[i / Scale] < Size
8301 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8302 if (Zeroable[i / Scale])
8303 V1Idx = V2Idx = ZeroMask;
8304 V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
8305 V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
8306 V1InUse |= (ZeroMask != V1Idx);
8307 V2InUse |= (ZeroMask != V2Idx);
8312 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8313 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8314 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8316 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8317 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8318 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8320 // If we need shuffled inputs from both, blend the two.
8322 if (V1InUse && V2InUse)
8323 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8325 V = V1InUse ? V1 : V2;
8327 // Cast the result back to the correct type.
8328 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8331 /// \brief Generic lowering of 8-lane i16 shuffles.
8333 /// This handles both single-input shuffles and combined shuffle/blends with
8334 /// two inputs. The single input shuffles are immediately delegated to
8335 /// a dedicated lowering routine.
8337 /// The blends are lowered in one of three fundamental ways. If there are few
8338 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8339 /// of the input is significantly cheaper when lowered as an interleaving of
8340 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8341 /// halves of the inputs separately (making them have relatively few inputs)
8342 /// and then concatenate them.
8343 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8344 const X86Subtarget *Subtarget,
8345 SelectionDAG &DAG) {
8347 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8348 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8349 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8350 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8351 ArrayRef<int> OrigMask = SVOp->getMask();
8352 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8353 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8354 MutableArrayRef<int> Mask(MaskStorage);
8356 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8358 // Whenever we can lower this as a zext, that instruction is strictly faster
8359 // than any alternative.
8360 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8361 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8364 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8366 auto isV2 = [](int M) { return M >= 8; };
8368 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8370 if (NumV2Inputs == 0) {
8371 // Check for being able to broadcast a single element.
8372 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8373 Mask, Subtarget, DAG))
8376 // Try to use shift instructions.
8378 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8381 // Use dedicated unpack instructions for masks that match their pattern.
8382 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8383 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8384 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8385 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8387 // Try to use byte rotation instructions.
8388 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8389 Mask, Subtarget, DAG))
8392 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8396 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8397 "All single-input shuffles should be canonicalized to be V1-input "
8400 // Try to use shift instructions.
8402 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8405 // There are special ways we can lower some single-element blends.
8406 if (NumV2Inputs == 1)
8407 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8408 Mask, Subtarget, DAG))
8411 // We have different paths for blend lowering, but they all must use the
8412 // *exact* same predicate.
8413 bool IsBlendSupported = Subtarget->hasSSE41();
8414 if (IsBlendSupported)
8415 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8419 if (SDValue Masked =
8420 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8423 // Use dedicated unpack instructions for masks that match their pattern.
8424 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8425 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8426 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8427 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8429 // Try to use byte rotation instructions.
8430 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8431 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8434 if (SDValue BitBlend =
8435 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8438 if (SDValue Unpack =
8439 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8442 // If we can't directly blend but can use PSHUFB, that will be better as it
8443 // can both shuffle and set up the inefficient blend.
8444 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8445 bool V1InUse, V2InUse;
8446 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8450 // We can always bit-blend if we have to so the fallback strategy is to
8451 // decompose into single-input permutes and blends.
8452 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8456 /// \brief Check whether a compaction lowering can be done by dropping even
8457 /// elements and compute how many times even elements must be dropped.
8459 /// This handles shuffles which take every Nth element where N is a power of
8460 /// two. Example shuffle masks:
8462 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8463 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8464 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8465 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8466 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8467 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8469 /// Any of these lanes can of course be undef.
8471 /// This routine only supports N <= 3.
8472 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8475 /// \returns N above, or the number of times even elements must be dropped if
8476 /// there is such a number. Otherwise returns zero.
8477 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8478 // Figure out whether we're looping over two inputs or just one.
8479 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8481 // The modulus for the shuffle vector entries is based on whether this is
8482 // a single input or not.
8483 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8484 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8485 "We should only be called with masks with a power-of-2 size!");
8487 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8489 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8490 // and 2^3 simultaneously. This is because we may have ambiguity with
8491 // partially undef inputs.
8492 bool ViableForN[3] = {true, true, true};
8494 for (int i = 0, e = Mask.size(); i < e; ++i) {
8495 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8500 bool IsAnyViable = false;
8501 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8502 if (ViableForN[j]) {
8505 // The shuffle mask must be equal to (i * 2^N) % M.
8506 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8509 ViableForN[j] = false;
8511 // Early exit if we exhaust the possible powers of two.
8516 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8520 // Return 0 as there is no viable power of two.
8524 /// \brief Generic lowering of v16i8 shuffles.
8526 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8527 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8528 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8529 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8531 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8532 const X86Subtarget *Subtarget,
8533 SelectionDAG &DAG) {
8535 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8536 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8537 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8538 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8539 ArrayRef<int> Mask = SVOp->getMask();
8540 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8542 // Try to use shift instructions.
8544 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8547 // Try to use byte rotation instructions.
8548 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8549 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8552 // Try to use a zext lowering.
8553 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8554 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8558 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8560 // For single-input shuffles, there are some nicer lowering tricks we can use.
8561 if (NumV2Elements == 0) {
8562 // Check for being able to broadcast a single element.
8563 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8564 Mask, Subtarget, DAG))
8567 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8568 // Notably, this handles splat and partial-splat shuffles more efficiently.
8569 // However, it only makes sense if the pre-duplication shuffle simplifies
8570 // things significantly. Currently, this means we need to be able to
8571 // express the pre-duplication shuffle as an i16 shuffle.
8573 // FIXME: We should check for other patterns which can be widened into an
8574 // i16 shuffle as well.
8575 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8576 for (int i = 0; i < 16; i += 2)
8577 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8582 auto tryToWidenViaDuplication = [&]() -> SDValue {
8583 if (!canWidenViaDuplication(Mask))
8585 SmallVector<int, 4> LoInputs;
8586 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8587 [](int M) { return M >= 0 && M < 8; });
8588 std::sort(LoInputs.begin(), LoInputs.end());
8589 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8591 SmallVector<int, 4> HiInputs;
8592 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8593 [](int M) { return M >= 8; });
8594 std::sort(HiInputs.begin(), HiInputs.end());
8595 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8598 bool TargetLo = LoInputs.size() >= HiInputs.size();
8599 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8600 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8602 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8603 SmallDenseMap<int, int, 8> LaneMap;
8604 for (int I : InPlaceInputs) {
8605 PreDupI16Shuffle[I/2] = I/2;
8608 int j = TargetLo ? 0 : 4, je = j + 4;
8609 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8610 // Check if j is already a shuffle of this input. This happens when
8611 // there are two adjacent bytes after we move the low one.
8612 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8613 // If we haven't yet mapped the input, search for a slot into which
8615 while (j < je && PreDupI16Shuffle[j] != -1)
8619 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8622 // Map this input with the i16 shuffle.
8623 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8626 // Update the lane map based on the mapping we ended up with.
8627 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8630 ISD::BITCAST, DL, MVT::v16i8,
8631 DAG.getVectorShuffle(MVT::v8i16, DL,
8632 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8633 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8635 // Unpack the bytes to form the i16s that will be shuffled into place.
8636 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8637 MVT::v16i8, V1, V1);
8639 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8640 for (int i = 0; i < 16; ++i)
8641 if (Mask[i] != -1) {
8642 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8643 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8644 if (PostDupI16Shuffle[i / 2] == -1)
8645 PostDupI16Shuffle[i / 2] = MappedMask;
8647 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8648 "Conflicting entrties in the original shuffle!");
8651 ISD::BITCAST, DL, MVT::v16i8,
8652 DAG.getVectorShuffle(MVT::v8i16, DL,
8653 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8654 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8656 if (SDValue V = tryToWidenViaDuplication())
8660 // Use dedicated unpack instructions for masks that match their pattern.
8661 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8662 0, 16, 1, 17, 2, 18, 3, 19,
8664 4, 20, 5, 21, 6, 22, 7, 23}))
8665 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8666 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8667 8, 24, 9, 25, 10, 26, 11, 27,
8669 12, 28, 13, 29, 14, 30, 15, 31}))
8670 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8672 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8673 // with PSHUFB. It is important to do this before we attempt to generate any
8674 // blends but after all of the single-input lowerings. If the single input
8675 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8676 // want to preserve that and we can DAG combine any longer sequences into
8677 // a PSHUFB in the end. But once we start blending from multiple inputs,
8678 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8679 // and there are *very* few patterns that would actually be faster than the
8680 // PSHUFB approach because of its ability to zero lanes.
8682 // FIXME: The only exceptions to the above are blends which are exact
8683 // interleavings with direct instructions supporting them. We currently don't
8684 // handle those well here.
8685 if (Subtarget->hasSSSE3()) {
8686 bool V1InUse = false;
8687 bool V2InUse = false;
8689 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8690 DAG, V1InUse, V2InUse);
8692 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8693 // do so. This avoids using them to handle blends-with-zero which is
8694 // important as a single pshufb is significantly faster for that.
8695 if (V1InUse && V2InUse) {
8696 if (Subtarget->hasSSE41())
8697 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8698 Mask, Subtarget, DAG))
8701 // We can use an unpack to do the blending rather than an or in some
8702 // cases. Even though the or may be (very minorly) more efficient, we
8703 // preference this lowering because there are common cases where part of
8704 // the complexity of the shuffles goes away when we do the final blend as
8706 // FIXME: It might be worth trying to detect if the unpack-feeding
8707 // shuffles will both be pshufb, in which case we shouldn't bother with
8709 if (SDValue Unpack =
8710 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8717 // There are special ways we can lower some single-element blends.
8718 if (NumV2Elements == 1)
8719 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8720 Mask, Subtarget, DAG))
8723 if (SDValue BitBlend =
8724 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8727 // Check whether a compaction lowering can be done. This handles shuffles
8728 // which take every Nth element for some even N. See the helper function for
8731 // We special case these as they can be particularly efficiently handled with
8732 // the PACKUSB instruction on x86 and they show up in common patterns of
8733 // rearranging bytes to truncate wide elements.
8734 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8735 // NumEvenDrops is the power of two stride of the elements. Another way of
8736 // thinking about it is that we need to drop the even elements this many
8737 // times to get the original input.
8738 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8740 // First we need to zero all the dropped bytes.
8741 assert(NumEvenDrops <= 3 &&
8742 "No support for dropping even elements more than 3 times.");
8743 // We use the mask type to pick which bytes are preserved based on how many
8744 // elements are dropped.
8745 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8746 SDValue ByteClearMask =
8747 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8748 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8749 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8751 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8753 // Now pack things back together.
8754 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8755 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8756 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8757 for (int i = 1; i < NumEvenDrops; ++i) {
8758 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8759 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8765 // Handle multi-input cases by blending single-input shuffles.
8766 if (NumV2Elements > 0)
8767 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8770 // The fallback path for single-input shuffles widens this into two v8i16
8771 // vectors with unpacks, shuffles those, and then pulls them back together
8775 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8776 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8777 for (int i = 0; i < 16; ++i)
8779 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8781 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8783 SDValue VLoHalf, VHiHalf;
8784 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8785 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8787 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8788 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8789 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8790 [](int M) { return M >= 0 && M % 2 == 1; })) {
8791 // Use a mask to drop the high bytes.
8792 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8793 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8794 DAG.getConstant(0x00FF, MVT::v8i16));
8796 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8797 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8799 // Squash the masks to point directly into VLoHalf.
8800 for (int &M : LoBlendMask)
8803 for (int &M : HiBlendMask)
8807 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8808 // VHiHalf so that we can blend them as i16s.
8809 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8810 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8811 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8812 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8815 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8816 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8818 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8821 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8823 /// This routine breaks down the specific type of 128-bit shuffle and
8824 /// dispatches to the lowering routines accordingly.
8825 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8826 MVT VT, const X86Subtarget *Subtarget,
8827 SelectionDAG &DAG) {
8828 switch (VT.SimpleTy) {
8830 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8832 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8834 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8836 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8838 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8840 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8843 llvm_unreachable("Unimplemented!");
8847 /// \brief Helper function to test whether a shuffle mask could be
8848 /// simplified by widening the elements being shuffled.
8850 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8851 /// leaves it in an unspecified state.
8853 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8854 /// shuffle masks. The latter have the special property of a '-2' representing
8855 /// a zero-ed lane of a vector.
8856 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8857 SmallVectorImpl<int> &WidenedMask) {
8858 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8859 // If both elements are undef, its trivial.
8860 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8861 WidenedMask.push_back(SM_SentinelUndef);
8865 // Check for an undef mask and a mask value properly aligned to fit with
8866 // a pair of values. If we find such a case, use the non-undef mask's value.
8867 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8868 WidenedMask.push_back(Mask[i + 1] / 2);
8871 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8872 WidenedMask.push_back(Mask[i] / 2);
8876 // When zeroing, we need to spread the zeroing across both lanes to widen.
8877 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8878 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8879 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8880 WidenedMask.push_back(SM_SentinelZero);
8886 // Finally check if the two mask values are adjacent and aligned with
8888 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
8889 WidenedMask.push_back(Mask[i] / 2);
8893 // Otherwise we can't safely widen the elements used in this shuffle.
8896 assert(WidenedMask.size() == Mask.size() / 2 &&
8897 "Incorrect size of mask after widening the elements!");
8902 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
8904 /// This routine just extracts two subvectors, shuffles them independently, and
8905 /// then concatenates them back together. This should work effectively with all
8906 /// AVX vector shuffle types.
8907 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8908 SDValue V2, ArrayRef<int> Mask,
8909 SelectionDAG &DAG) {
8910 assert(VT.getSizeInBits() >= 256 &&
8911 "Only for 256-bit or wider vector shuffles!");
8912 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8913 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8915 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8916 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
8918 int NumElements = VT.getVectorNumElements();
8919 int SplitNumElements = NumElements / 2;
8920 MVT ScalarVT = VT.getScalarType();
8921 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8923 // Rather than splitting build-vectors, just build two narrower build
8924 // vectors. This helps shuffling with splats and zeros.
8925 auto SplitVector = [&](SDValue V) {
8926 while (V.getOpcode() == ISD::BITCAST)
8927 V = V->getOperand(0);
8929 MVT OrigVT = V.getSimpleValueType();
8930 int OrigNumElements = OrigVT.getVectorNumElements();
8931 int OrigSplitNumElements = OrigNumElements / 2;
8932 MVT OrigScalarVT = OrigVT.getScalarType();
8933 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
8937 auto *BV = dyn_cast<BuildVectorSDNode>(V);
8939 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8940 DAG.getIntPtrConstant(0));
8941 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8942 DAG.getIntPtrConstant(OrigSplitNumElements));
8945 SmallVector<SDValue, 16> LoOps, HiOps;
8946 for (int i = 0; i < OrigSplitNumElements; ++i) {
8947 LoOps.push_back(BV->getOperand(i));
8948 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
8950 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
8951 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
8953 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
8954 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
8957 SDValue LoV1, HiV1, LoV2, HiV2;
8958 std::tie(LoV1, HiV1) = SplitVector(V1);
8959 std::tie(LoV2, HiV2) = SplitVector(V2);
8961 // Now create two 4-way blends of these half-width vectors.
8962 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8963 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
8964 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
8965 for (int i = 0; i < SplitNumElements; ++i) {
8966 int M = HalfMask[i];
8967 if (M >= NumElements) {
8968 if (M >= NumElements + SplitNumElements)
8972 V2BlendMask.push_back(M - NumElements);
8973 V1BlendMask.push_back(-1);
8974 BlendMask.push_back(SplitNumElements + i);
8975 } else if (M >= 0) {
8976 if (M >= SplitNumElements)
8980 V2BlendMask.push_back(-1);
8981 V1BlendMask.push_back(M);
8982 BlendMask.push_back(i);
8984 V2BlendMask.push_back(-1);
8985 V1BlendMask.push_back(-1);
8986 BlendMask.push_back(-1);
8990 // Because the lowering happens after all combining takes place, we need to
8991 // manually combine these blend masks as much as possible so that we create
8992 // a minimal number of high-level vector shuffle nodes.
8994 // First try just blending the halves of V1 or V2.
8995 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
8996 return DAG.getUNDEF(SplitVT);
8997 if (!UseLoV2 && !UseHiV2)
8998 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8999 if (!UseLoV1 && !UseHiV1)
9000 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9002 SDValue V1Blend, V2Blend;
9003 if (UseLoV1 && UseHiV1) {
9005 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9007 // We only use half of V1 so map the usage down into the final blend mask.
9008 V1Blend = UseLoV1 ? LoV1 : HiV1;
9009 for (int i = 0; i < SplitNumElements; ++i)
9010 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9011 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9013 if (UseLoV2 && UseHiV2) {
9015 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9017 // We only use half of V2 so map the usage down into the final blend mask.
9018 V2Blend = UseLoV2 ? LoV2 : HiV2;
9019 for (int i = 0; i < SplitNumElements; ++i)
9020 if (BlendMask[i] >= SplitNumElements)
9021 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9023 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9025 SDValue Lo = HalfBlend(LoMask);
9026 SDValue Hi = HalfBlend(HiMask);
9027 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9030 /// \brief Either split a vector in halves or decompose the shuffles and the
9033 /// This is provided as a good fallback for many lowerings of non-single-input
9034 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9035 /// between splitting the shuffle into 128-bit components and stitching those
9036 /// back together vs. extracting the single-input shuffles and blending those
9038 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9039 SDValue V2, ArrayRef<int> Mask,
9040 SelectionDAG &DAG) {
9041 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9042 "lower single-input shuffles as it "
9043 "could then recurse on itself.");
9044 int Size = Mask.size();
9046 // If this can be modeled as a broadcast of two elements followed by a blend,
9047 // prefer that lowering. This is especially important because broadcasts can
9048 // often fold with memory operands.
9049 auto DoBothBroadcast = [&] {
9050 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9053 if (V2BroadcastIdx == -1)
9054 V2BroadcastIdx = M - Size;
9055 else if (M - Size != V2BroadcastIdx)
9057 } else if (M >= 0) {
9058 if (V1BroadcastIdx == -1)
9060 else if (M != V1BroadcastIdx)
9065 if (DoBothBroadcast())
9066 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9069 // If the inputs all stem from a single 128-bit lane of each input, then we
9070 // split them rather than blending because the split will decompose to
9071 // unusually few instructions.
9072 int LaneCount = VT.getSizeInBits() / 128;
9073 int LaneSize = Size / LaneCount;
9074 SmallBitVector LaneInputs[2];
9075 LaneInputs[0].resize(LaneCount, false);
9076 LaneInputs[1].resize(LaneCount, false);
9077 for (int i = 0; i < Size; ++i)
9079 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9080 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9081 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9083 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9084 // that the decomposed single-input shuffles don't end up here.
9085 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9088 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9089 /// a permutation and blend of those lanes.
9091 /// This essentially blends the out-of-lane inputs to each lane into the lane
9092 /// from a permuted copy of the vector. This lowering strategy results in four
9093 /// instructions in the worst case for a single-input cross lane shuffle which
9094 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9095 /// of. Special cases for each particular shuffle pattern should be handled
9096 /// prior to trying this lowering.
9097 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9098 SDValue V1, SDValue V2,
9100 SelectionDAG &DAG) {
9101 // FIXME: This should probably be generalized for 512-bit vectors as well.
9102 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9103 int LaneSize = Mask.size() / 2;
9105 // If there are only inputs from one 128-bit lane, splitting will in fact be
9106 // less expensive. The flags track whether the given lane contains an element
9107 // that crosses to another lane.
9108 bool LaneCrossing[2] = {false, false};
9109 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9110 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9111 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9112 if (!LaneCrossing[0] || !LaneCrossing[1])
9113 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9115 if (isSingleInputShuffleMask(Mask)) {
9116 SmallVector<int, 32> FlippedBlendMask;
9117 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9118 FlippedBlendMask.push_back(
9119 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9121 : Mask[i] % LaneSize +
9122 (i / LaneSize) * LaneSize + Size));
9124 // Flip the vector, and blend the results which should now be in-lane. The
9125 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9126 // 5 for the high source. The value 3 selects the high half of source 2 and
9127 // the value 2 selects the low half of source 2. We only use source 2 to
9128 // allow folding it into a memory operand.
9129 unsigned PERMMask = 3 | 2 << 4;
9130 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9131 V1, DAG.getConstant(PERMMask, MVT::i8));
9132 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9135 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9136 // will be handled by the above logic and a blend of the results, much like
9137 // other patterns in AVX.
9138 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9141 /// \brief Handle lowering 2-lane 128-bit shuffles.
9142 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9143 SDValue V2, ArrayRef<int> Mask,
9144 const X86Subtarget *Subtarget,
9145 SelectionDAG &DAG) {
9146 // TODO: If minimizing size and one of the inputs is a zero vector and the
9147 // the zero vector has only one use, we could use a VPERM2X128 to save the
9148 // instruction bytes needed to explicitly generate the zero vector.
9150 // Blends are faster and handle all the non-lane-crossing cases.
9151 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9155 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9156 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9158 // If either input operand is a zero vector, use VPERM2X128 because its mask
9159 // allows us to replace the zero input with an implicit zero.
9160 if (!IsV1Zero && !IsV2Zero) {
9161 // Check for patterns which can be matched with a single insert of a 128-bit
9163 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9164 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9165 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9166 VT.getVectorNumElements() / 2);
9167 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9168 DAG.getIntPtrConstant(0));
9169 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9170 OnlyUsesV1 ? V1 : V2, DAG.getIntPtrConstant(0));
9171 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9175 // Otherwise form a 128-bit permutation. After accounting for undefs,
9176 // convert the 64-bit shuffle mask selection values into 128-bit
9177 // selection bits by dividing the indexes by 2 and shifting into positions
9178 // defined by a vperm2*128 instruction's immediate control byte.
9180 // The immediate permute control byte looks like this:
9181 // [1:0] - select 128 bits from sources for low half of destination
9183 // [3] - zero low half of destination
9184 // [5:4] - select 128 bits from sources for high half of destination
9186 // [7] - zero high half of destination
9188 int MaskLO = Mask[0];
9189 if (MaskLO == SM_SentinelUndef)
9190 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9192 int MaskHI = Mask[2];
9193 if (MaskHI == SM_SentinelUndef)
9194 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9196 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9198 // If either input is a zero vector, replace it with an undef input.
9199 // Shuffle mask values < 4 are selecting elements of V1.
9200 // Shuffle mask values >= 4 are selecting elements of V2.
9201 // Adjust each half of the permute mask by clearing the half that was
9202 // selecting the zero vector and setting the zero mask bit.
9204 V1 = DAG.getUNDEF(VT);
9206 PermMask = (PermMask & 0xf0) | 0x08;
9208 PermMask = (PermMask & 0x0f) | 0x80;
9211 V2 = DAG.getUNDEF(VT);
9213 PermMask = (PermMask & 0xf0) | 0x08;
9215 PermMask = (PermMask & 0x0f) | 0x80;
9218 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9219 DAG.getConstant(PermMask, MVT::i8));
9222 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9223 /// shuffling each lane.
9225 /// This will only succeed when the result of fixing the 128-bit lanes results
9226 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9227 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9228 /// the lane crosses early and then use simpler shuffles within each lane.
9230 /// FIXME: It might be worthwhile at some point to support this without
9231 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9232 /// in x86 only floating point has interesting non-repeating shuffles, and even
9233 /// those are still *marginally* more expensive.
9234 static SDValue lowerVectorShuffleByMerging128BitLanes(
9235 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9236 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9237 assert(!isSingleInputShuffleMask(Mask) &&
9238 "This is only useful with multiple inputs.");
9240 int Size = Mask.size();
9241 int LaneSize = 128 / VT.getScalarSizeInBits();
9242 int NumLanes = Size / LaneSize;
9243 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9245 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9246 // check whether the in-128-bit lane shuffles share a repeating pattern.
9247 SmallVector<int, 4> Lanes;
9248 Lanes.resize(NumLanes, -1);
9249 SmallVector<int, 4> InLaneMask;
9250 InLaneMask.resize(LaneSize, -1);
9251 for (int i = 0; i < Size; ++i) {
9255 int j = i / LaneSize;
9258 // First entry we've seen for this lane.
9259 Lanes[j] = Mask[i] / LaneSize;
9260 } else if (Lanes[j] != Mask[i] / LaneSize) {
9261 // This doesn't match the lane selected previously!
9265 // Check that within each lane we have a consistent shuffle mask.
9266 int k = i % LaneSize;
9267 if (InLaneMask[k] < 0) {
9268 InLaneMask[k] = Mask[i] % LaneSize;
9269 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9270 // This doesn't fit a repeating in-lane mask.
9275 // First shuffle the lanes into place.
9276 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9277 VT.getSizeInBits() / 64);
9278 SmallVector<int, 8> LaneMask;
9279 LaneMask.resize(NumLanes * 2, -1);
9280 for (int i = 0; i < NumLanes; ++i)
9281 if (Lanes[i] >= 0) {
9282 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9283 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9286 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9287 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9288 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9290 // Cast it back to the type we actually want.
9291 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9293 // Now do a simple shuffle that isn't lane crossing.
9294 SmallVector<int, 8> NewMask;
9295 NewMask.resize(Size, -1);
9296 for (int i = 0; i < Size; ++i)
9298 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9299 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9300 "Must not introduce lane crosses at this point!");
9302 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9305 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9308 /// This returns true if the elements from a particular input are already in the
9309 /// slot required by the given mask and require no permutation.
9310 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9311 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9312 int Size = Mask.size();
9313 for (int i = 0; i < Size; ++i)
9314 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9320 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9322 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9323 /// isn't available.
9324 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9325 const X86Subtarget *Subtarget,
9326 SelectionDAG &DAG) {
9328 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9329 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9330 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9331 ArrayRef<int> Mask = SVOp->getMask();
9332 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9334 SmallVector<int, 4> WidenedMask;
9335 if (canWidenShuffleElements(Mask, WidenedMask))
9336 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9339 if (isSingleInputShuffleMask(Mask)) {
9340 // Check for being able to broadcast a single element.
9341 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9342 Mask, Subtarget, DAG))
9345 // Use low duplicate instructions for masks that match their pattern.
9346 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9347 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9349 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9350 // Non-half-crossing single input shuffles can be lowerid with an
9351 // interleaved permutation.
9352 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9353 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9354 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9355 DAG.getConstant(VPERMILPMask, MVT::i8));
9358 // With AVX2 we have direct support for this permutation.
9359 if (Subtarget->hasAVX2())
9360 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9361 getV4X86ShuffleImm8ForMask(Mask, DAG));
9363 // Otherwise, fall back.
9364 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9368 // X86 has dedicated unpack instructions that can handle specific blend
9369 // operations: UNPCKH and UNPCKL.
9370 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9371 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9372 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9373 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9374 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9375 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9376 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9377 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9379 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9383 // Check if the blend happens to exactly fit that of SHUFPD.
9384 if ((Mask[0] == -1 || Mask[0] < 2) &&
9385 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9386 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9387 (Mask[3] == -1 || Mask[3] >= 6)) {
9388 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9389 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9390 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9391 DAG.getConstant(SHUFPDMask, MVT::i8));
9393 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9394 (Mask[1] == -1 || Mask[1] < 2) &&
9395 (Mask[2] == -1 || Mask[2] >= 6) &&
9396 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9397 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9398 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9399 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9400 DAG.getConstant(SHUFPDMask, MVT::i8));
9403 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9404 // shuffle. However, if we have AVX2 and either inputs are already in place,
9405 // we will be able to shuffle even across lanes the other input in a single
9406 // instruction so skip this pattern.
9407 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9408 isShuffleMaskInputInPlace(1, Mask))))
9409 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9410 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9413 // If we have AVX2 then we always want to lower with a blend because an v4 we
9414 // can fully permute the elements.
9415 if (Subtarget->hasAVX2())
9416 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9419 // Otherwise fall back on generic lowering.
9420 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9423 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9425 /// This routine is only called when we have AVX2 and thus a reasonable
9426 /// instruction set for v4i64 shuffling..
9427 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9428 const X86Subtarget *Subtarget,
9429 SelectionDAG &DAG) {
9431 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9432 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9433 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9434 ArrayRef<int> Mask = SVOp->getMask();
9435 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9436 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9438 SmallVector<int, 4> WidenedMask;
9439 if (canWidenShuffleElements(Mask, WidenedMask))
9440 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9443 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9447 // Check for being able to broadcast a single element.
9448 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9449 Mask, Subtarget, DAG))
9452 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9453 // use lower latency instructions that will operate on both 128-bit lanes.
9454 SmallVector<int, 2> RepeatedMask;
9455 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9456 if (isSingleInputShuffleMask(Mask)) {
9457 int PSHUFDMask[] = {-1, -1, -1, -1};
9458 for (int i = 0; i < 2; ++i)
9459 if (RepeatedMask[i] >= 0) {
9460 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9461 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9464 ISD::BITCAST, DL, MVT::v4i64,
9465 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9466 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9467 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9471 // AVX2 provides a direct instruction for permuting a single input across
9473 if (isSingleInputShuffleMask(Mask))
9474 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9475 getV4X86ShuffleImm8ForMask(Mask, DAG));
9477 // Try to use shift instructions.
9479 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9482 // Use dedicated unpack instructions for masks that match their pattern.
9483 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9484 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9485 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9486 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9487 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9488 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9489 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9490 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9492 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9493 // shuffle. However, if we have AVX2 and either inputs are already in place,
9494 // we will be able to shuffle even across lanes the other input in a single
9495 // instruction so skip this pattern.
9496 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9497 isShuffleMaskInputInPlace(1, Mask))))
9498 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9499 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9502 // Otherwise fall back on generic blend lowering.
9503 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9507 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9509 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9510 /// isn't available.
9511 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9512 const X86Subtarget *Subtarget,
9513 SelectionDAG &DAG) {
9515 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9516 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9517 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9518 ArrayRef<int> Mask = SVOp->getMask();
9519 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9521 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9525 // Check for being able to broadcast a single element.
9526 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9527 Mask, Subtarget, DAG))
9530 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9531 // options to efficiently lower the shuffle.
9532 SmallVector<int, 4> RepeatedMask;
9533 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9534 assert(RepeatedMask.size() == 4 &&
9535 "Repeated masks must be half the mask width!");
9537 // Use even/odd duplicate instructions for masks that match their pattern.
9538 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9539 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9540 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9541 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9543 if (isSingleInputShuffleMask(Mask))
9544 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9545 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9547 // Use dedicated unpack instructions for masks that match their pattern.
9548 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9549 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9550 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9551 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9552 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9553 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9554 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9555 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9557 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9558 // have already handled any direct blends. We also need to squash the
9559 // repeated mask into a simulated v4f32 mask.
9560 for (int i = 0; i < 4; ++i)
9561 if (RepeatedMask[i] >= 8)
9562 RepeatedMask[i] -= 4;
9563 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9566 // If we have a single input shuffle with different shuffle patterns in the
9567 // two 128-bit lanes use the variable mask to VPERMILPS.
9568 if (isSingleInputShuffleMask(Mask)) {
9569 SDValue VPermMask[8];
9570 for (int i = 0; i < 8; ++i)
9571 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9572 : DAG.getConstant(Mask[i], MVT::i32);
9573 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9575 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9576 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9578 if (Subtarget->hasAVX2())
9579 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9580 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9581 DAG.getNode(ISD::BUILD_VECTOR, DL,
9582 MVT::v8i32, VPermMask)),
9585 // Otherwise, fall back.
9586 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9590 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9592 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9593 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9596 // If we have AVX2 then we always want to lower with a blend because at v8 we
9597 // can fully permute the elements.
9598 if (Subtarget->hasAVX2())
9599 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9602 // Otherwise fall back on generic lowering.
9603 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9606 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9608 /// This routine is only called when we have AVX2 and thus a reasonable
9609 /// instruction set for v8i32 shuffling..
9610 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9611 const X86Subtarget *Subtarget,
9612 SelectionDAG &DAG) {
9614 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9615 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9616 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9617 ArrayRef<int> Mask = SVOp->getMask();
9618 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9619 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9621 // Whenever we can lower this as a zext, that instruction is strictly faster
9622 // than any alternative. It also allows us to fold memory operands into the
9623 // shuffle in many cases.
9624 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9625 Mask, Subtarget, DAG))
9628 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9632 // Check for being able to broadcast a single element.
9633 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9634 Mask, Subtarget, DAG))
9637 // If the shuffle mask is repeated in each 128-bit lane we can use more
9638 // efficient instructions that mirror the shuffles across the two 128-bit
9640 SmallVector<int, 4> RepeatedMask;
9641 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9642 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9643 if (isSingleInputShuffleMask(Mask))
9644 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9645 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9647 // Use dedicated unpack instructions for masks that match their pattern.
9648 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9649 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9650 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9651 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9652 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9653 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9654 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9655 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9658 // Try to use shift instructions.
9660 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9663 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9664 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9667 // If the shuffle patterns aren't repeated but it is a single input, directly
9668 // generate a cross-lane VPERMD instruction.
9669 if (isSingleInputShuffleMask(Mask)) {
9670 SDValue VPermMask[8];
9671 for (int i = 0; i < 8; ++i)
9672 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9673 : DAG.getConstant(Mask[i], MVT::i32);
9675 X86ISD::VPERMV, DL, MVT::v8i32,
9676 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9679 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9681 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9682 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9685 // Otherwise fall back on generic blend lowering.
9686 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9690 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9692 /// This routine is only called when we have AVX2 and thus a reasonable
9693 /// instruction set for v16i16 shuffling..
9694 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9695 const X86Subtarget *Subtarget,
9696 SelectionDAG &DAG) {
9698 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9699 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9700 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9701 ArrayRef<int> Mask = SVOp->getMask();
9702 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9703 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9705 // Whenever we can lower this as a zext, that instruction is strictly faster
9706 // than any alternative. It also allows us to fold memory operands into the
9707 // shuffle in many cases.
9708 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9709 Mask, Subtarget, DAG))
9712 // Check for being able to broadcast a single element.
9713 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9714 Mask, Subtarget, DAG))
9717 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9721 // Use dedicated unpack instructions for masks that match their pattern.
9722 if (isShuffleEquivalent(V1, V2, Mask,
9723 {// First 128-bit lane:
9724 0, 16, 1, 17, 2, 18, 3, 19,
9725 // Second 128-bit lane:
9726 8, 24, 9, 25, 10, 26, 11, 27}))
9727 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9728 if (isShuffleEquivalent(V1, V2, Mask,
9729 {// First 128-bit lane:
9730 4, 20, 5, 21, 6, 22, 7, 23,
9731 // Second 128-bit lane:
9732 12, 28, 13, 29, 14, 30, 15, 31}))
9733 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9735 // Try to use shift instructions.
9737 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9740 // Try to use byte rotation instructions.
9741 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9742 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9745 if (isSingleInputShuffleMask(Mask)) {
9746 // There are no generalized cross-lane shuffle operations available on i16
9748 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9749 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9752 SmallVector<int, 8> RepeatedMask;
9753 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9754 // As this is a single-input shuffle, the repeated mask should be
9755 // a strictly valid v8i16 mask that we can pass through to the v8i16
9756 // lowering to handle even the v16 case.
9757 return lowerV8I16GeneralSingleInputVectorShuffle(
9758 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9761 SDValue PSHUFBMask[32];
9762 for (int i = 0; i < 16; ++i) {
9763 if (Mask[i] == -1) {
9764 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9768 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9769 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9770 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9771 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9774 ISD::BITCAST, DL, MVT::v16i16,
9776 X86ISD::PSHUFB, DL, MVT::v32i8,
9777 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9778 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9781 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9783 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9784 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9787 // Otherwise fall back on generic lowering.
9788 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9791 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9793 /// This routine is only called when we have AVX2 and thus a reasonable
9794 /// instruction set for v32i8 shuffling..
9795 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9796 const X86Subtarget *Subtarget,
9797 SelectionDAG &DAG) {
9799 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9800 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9801 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9802 ArrayRef<int> Mask = SVOp->getMask();
9803 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9804 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9806 // Whenever we can lower this as a zext, that instruction is strictly faster
9807 // than any alternative. It also allows us to fold memory operands into the
9808 // shuffle in many cases.
9809 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9810 Mask, Subtarget, DAG))
9813 // Check for being able to broadcast a single element.
9814 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9815 Mask, Subtarget, DAG))
9818 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9822 // Use dedicated unpack instructions for masks that match their pattern.
9823 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9825 if (isShuffleEquivalent(
9827 {// First 128-bit lane:
9828 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9829 // Second 128-bit lane:
9830 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9831 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9832 if (isShuffleEquivalent(
9834 {// First 128-bit lane:
9835 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9836 // Second 128-bit lane:
9837 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9838 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9840 // Try to use shift instructions.
9842 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9845 // Try to use byte rotation instructions.
9846 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9847 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9850 if (isSingleInputShuffleMask(Mask)) {
9851 // There are no generalized cross-lane shuffle operations available on i8
9853 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9854 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9857 SDValue PSHUFBMask[32];
9858 for (int i = 0; i < 32; ++i)
9861 ? DAG.getUNDEF(MVT::i8)
9862 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9865 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9866 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9869 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9871 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9872 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9875 // Otherwise fall back on generic lowering.
9876 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
9879 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9881 /// This routine either breaks down the specific type of a 256-bit x86 vector
9882 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9883 /// together based on the available instructions.
9884 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9885 MVT VT, const X86Subtarget *Subtarget,
9886 SelectionDAG &DAG) {
9888 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9889 ArrayRef<int> Mask = SVOp->getMask();
9891 // If we have a single input to the zero element, insert that into V1 if we
9892 // can do so cheaply.
9893 int NumElts = VT.getVectorNumElements();
9894 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
9895 return M >= NumElts;
9898 if (NumV2Elements == 1 && Mask[0] >= NumElts)
9899 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9900 DL, VT, V1, V2, Mask, Subtarget, DAG))
9903 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9904 // check for those subtargets here and avoid much of the subtarget querying in
9905 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9906 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9907 // floating point types there eventually, just immediately cast everything to
9908 // a float and operate entirely in that domain.
9909 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9910 int ElementBits = VT.getScalarSizeInBits();
9911 if (ElementBits < 32)
9912 // No floating point type available, decompose into 128-bit vectors.
9913 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9915 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9916 VT.getVectorNumElements());
9917 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9918 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9919 return DAG.getNode(ISD::BITCAST, DL, VT,
9920 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9923 switch (VT.SimpleTy) {
9925 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9927 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9929 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9931 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9933 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9935 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9938 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9942 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9943 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9944 const X86Subtarget *Subtarget,
9945 SelectionDAG &DAG) {
9947 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9948 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9949 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9950 ArrayRef<int> Mask = SVOp->getMask();
9951 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9953 // X86 has dedicated unpack instructions that can handle specific blend
9954 // operations: UNPCKH and UNPCKL.
9955 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9956 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
9957 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9958 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
9960 // FIXME: Implement direct support for this type!
9961 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9964 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9965 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9966 const X86Subtarget *Subtarget,
9967 SelectionDAG &DAG) {
9969 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9970 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9971 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9972 ArrayRef<int> Mask = SVOp->getMask();
9973 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9975 // Use dedicated unpack instructions for masks that match their pattern.
9976 if (isShuffleEquivalent(V1, V2, Mask,
9977 {// First 128-bit lane.
9978 0, 16, 1, 17, 4, 20, 5, 21,
9979 // Second 128-bit lane.
9980 8, 24, 9, 25, 12, 28, 13, 29}))
9981 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
9982 if (isShuffleEquivalent(V1, V2, Mask,
9983 {// First 128-bit lane.
9984 2, 18, 3, 19, 6, 22, 7, 23,
9985 // Second 128-bit lane.
9986 10, 26, 11, 27, 14, 30, 15, 31}))
9987 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
9989 // FIXME: Implement direct support for this type!
9990 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
9993 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
9994 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9995 const X86Subtarget *Subtarget,
9996 SelectionDAG &DAG) {
9998 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9999 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10000 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10001 ArrayRef<int> Mask = SVOp->getMask();
10002 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10004 // X86 has dedicated unpack instructions that can handle specific blend
10005 // operations: UNPCKH and UNPCKL.
10006 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10007 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10008 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10009 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10011 // FIXME: Implement direct support for this type!
10012 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10015 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10016 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10017 const X86Subtarget *Subtarget,
10018 SelectionDAG &DAG) {
10020 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10021 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10022 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10023 ArrayRef<int> Mask = SVOp->getMask();
10024 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10026 // Use dedicated unpack instructions for masks that match their pattern.
10027 if (isShuffleEquivalent(V1, V2, Mask,
10028 {// First 128-bit lane.
10029 0, 16, 1, 17, 4, 20, 5, 21,
10030 // Second 128-bit lane.
10031 8, 24, 9, 25, 12, 28, 13, 29}))
10032 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10033 if (isShuffleEquivalent(V1, V2, Mask,
10034 {// First 128-bit lane.
10035 2, 18, 3, 19, 6, 22, 7, 23,
10036 // Second 128-bit lane.
10037 10, 26, 11, 27, 14, 30, 15, 31}))
10038 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10040 // FIXME: Implement direct support for this type!
10041 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10044 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10045 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10046 const X86Subtarget *Subtarget,
10047 SelectionDAG &DAG) {
10049 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10050 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10052 ArrayRef<int> Mask = SVOp->getMask();
10053 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10054 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10056 // FIXME: Implement direct support for this type!
10057 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10060 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10061 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10062 const X86Subtarget *Subtarget,
10063 SelectionDAG &DAG) {
10065 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10066 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10067 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10068 ArrayRef<int> Mask = SVOp->getMask();
10069 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10070 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10072 // FIXME: Implement direct support for this type!
10073 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10076 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10078 /// This routine either breaks down the specific type of a 512-bit x86 vector
10079 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10080 /// together based on the available instructions.
10081 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10082 MVT VT, const X86Subtarget *Subtarget,
10083 SelectionDAG &DAG) {
10085 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10086 ArrayRef<int> Mask = SVOp->getMask();
10087 assert(Subtarget->hasAVX512() &&
10088 "Cannot lower 512-bit vectors w/ basic ISA!");
10090 // Check for being able to broadcast a single element.
10091 if (SDValue Broadcast =
10092 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10095 // Dispatch to each element type for lowering. If we don't have supprot for
10096 // specific element type shuffles at 512 bits, immediately split them and
10097 // lower them. Each lowering routine of a given type is allowed to assume that
10098 // the requisite ISA extensions for that element type are available.
10099 switch (VT.SimpleTy) {
10101 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10103 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10105 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10107 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10109 if (Subtarget->hasBWI())
10110 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10113 if (Subtarget->hasBWI())
10114 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10118 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10121 // Otherwise fall back on splitting.
10122 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10125 /// \brief Top-level lowering for x86 vector shuffles.
10127 /// This handles decomposition, canonicalization, and lowering of all x86
10128 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10129 /// above in helper routines. The canonicalization attempts to widen shuffles
10130 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10131 /// s.t. only one of the two inputs needs to be tested, etc.
10132 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10133 SelectionDAG &DAG) {
10134 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10135 ArrayRef<int> Mask = SVOp->getMask();
10136 SDValue V1 = Op.getOperand(0);
10137 SDValue V2 = Op.getOperand(1);
10138 MVT VT = Op.getSimpleValueType();
10139 int NumElements = VT.getVectorNumElements();
10142 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10144 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10145 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10146 if (V1IsUndef && V2IsUndef)
10147 return DAG.getUNDEF(VT);
10149 // When we create a shuffle node we put the UNDEF node to second operand,
10150 // but in some cases the first operand may be transformed to UNDEF.
10151 // In this case we should just commute the node.
10153 return DAG.getCommutedVectorShuffle(*SVOp);
10155 // Check for non-undef masks pointing at an undef vector and make the masks
10156 // undef as well. This makes it easier to match the shuffle based solely on
10160 if (M >= NumElements) {
10161 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10162 for (int &M : NewMask)
10163 if (M >= NumElements)
10165 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10168 // We actually see shuffles that are entirely re-arrangements of a set of
10169 // zero inputs. This mostly happens while decomposing complex shuffles into
10170 // simple ones. Directly lower these as a buildvector of zeros.
10171 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10172 if (Zeroable.all())
10173 return getZeroVector(VT, Subtarget, DAG, dl);
10175 // Try to collapse shuffles into using a vector type with fewer elements but
10176 // wider element types. We cap this to not form integers or floating point
10177 // elements wider than 64 bits, but it might be interesting to form i128
10178 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10179 SmallVector<int, 16> WidenedMask;
10180 if (VT.getScalarSizeInBits() < 64 &&
10181 canWidenShuffleElements(Mask, WidenedMask)) {
10182 MVT NewEltVT = VT.isFloatingPoint()
10183 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10184 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10185 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10186 // Make sure that the new vector type is legal. For example, v2f64 isn't
10188 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10189 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10190 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10191 return DAG.getNode(ISD::BITCAST, dl, VT,
10192 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10196 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10197 for (int M : SVOp->getMask())
10199 ++NumUndefElements;
10200 else if (M < NumElements)
10205 // Commute the shuffle as needed such that more elements come from V1 than
10206 // V2. This allows us to match the shuffle pattern strictly on how many
10207 // elements come from V1 without handling the symmetric cases.
10208 if (NumV2Elements > NumV1Elements)
10209 return DAG.getCommutedVectorShuffle(*SVOp);
10211 // When the number of V1 and V2 elements are the same, try to minimize the
10212 // number of uses of V2 in the low half of the vector. When that is tied,
10213 // ensure that the sum of indices for V1 is equal to or lower than the sum
10214 // indices for V2. When those are equal, try to ensure that the number of odd
10215 // indices for V1 is lower than the number of odd indices for V2.
10216 if (NumV1Elements == NumV2Elements) {
10217 int LowV1Elements = 0, LowV2Elements = 0;
10218 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10219 if (M >= NumElements)
10223 if (LowV2Elements > LowV1Elements) {
10224 return DAG.getCommutedVectorShuffle(*SVOp);
10225 } else if (LowV2Elements == LowV1Elements) {
10226 int SumV1Indices = 0, SumV2Indices = 0;
10227 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10228 if (SVOp->getMask()[i] >= NumElements)
10230 else if (SVOp->getMask()[i] >= 0)
10232 if (SumV2Indices < SumV1Indices) {
10233 return DAG.getCommutedVectorShuffle(*SVOp);
10234 } else if (SumV2Indices == SumV1Indices) {
10235 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10236 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10237 if (SVOp->getMask()[i] >= NumElements)
10238 NumV2OddIndices += i % 2;
10239 else if (SVOp->getMask()[i] >= 0)
10240 NumV1OddIndices += i % 2;
10241 if (NumV2OddIndices < NumV1OddIndices)
10242 return DAG.getCommutedVectorShuffle(*SVOp);
10247 // For each vector width, delegate to a specialized lowering routine.
10248 if (VT.getSizeInBits() == 128)
10249 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10251 if (VT.getSizeInBits() == 256)
10252 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10254 // Force AVX-512 vectors to be scalarized for now.
10255 // FIXME: Implement AVX-512 support!
10256 if (VT.getSizeInBits() == 512)
10257 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10259 llvm_unreachable("Unimplemented!");
10262 // This function assumes its argument is a BUILD_VECTOR of constants or
10263 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10265 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10266 unsigned &MaskValue) {
10268 unsigned NumElems = BuildVector->getNumOperands();
10269 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10270 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10271 unsigned NumElemsInLane = NumElems / NumLanes;
10273 // Blend for v16i16 should be symetric for the both lanes.
10274 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10275 SDValue EltCond = BuildVector->getOperand(i);
10276 SDValue SndLaneEltCond =
10277 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10279 int Lane1Cond = -1, Lane2Cond = -1;
10280 if (isa<ConstantSDNode>(EltCond))
10281 Lane1Cond = !isZero(EltCond);
10282 if (isa<ConstantSDNode>(SndLaneEltCond))
10283 Lane2Cond = !isZero(SndLaneEltCond);
10285 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10286 // Lane1Cond != 0, means we want the first argument.
10287 // Lane1Cond == 0, means we want the second argument.
10288 // The encoding of this argument is 0 for the first argument, 1
10289 // for the second. Therefore, invert the condition.
10290 MaskValue |= !Lane1Cond << i;
10291 else if (Lane1Cond < 0)
10292 MaskValue |= !Lane2Cond << i;
10299 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10300 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10301 const X86Subtarget *Subtarget,
10302 SelectionDAG &DAG) {
10303 SDValue Cond = Op.getOperand(0);
10304 SDValue LHS = Op.getOperand(1);
10305 SDValue RHS = Op.getOperand(2);
10307 MVT VT = Op.getSimpleValueType();
10309 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10311 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10313 // Only non-legal VSELECTs reach this lowering, convert those into generic
10314 // shuffles and re-use the shuffle lowering path for blends.
10315 SmallVector<int, 32> Mask;
10316 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10317 SDValue CondElt = CondBV->getOperand(i);
10319 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10321 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10324 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10325 // A vselect where all conditions and data are constants can be optimized into
10326 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10327 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10328 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10329 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10332 // Try to lower this to a blend-style vector shuffle. This can handle all
10333 // constant condition cases.
10334 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10337 // Variable blends are only legal from SSE4.1 onward.
10338 if (!Subtarget->hasSSE41())
10341 // Only some types will be legal on some subtargets. If we can emit a legal
10342 // VSELECT-matching blend, return Op, and but if we need to expand, return
10344 switch (Op.getSimpleValueType().SimpleTy) {
10346 // Most of the vector types have blends past SSE4.1.
10350 // The byte blends for AVX vectors were introduced only in AVX2.
10351 if (Subtarget->hasAVX2())
10358 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10359 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10362 // FIXME: We should custom lower this by fixing the condition and using i8
10368 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10369 MVT VT = Op.getSimpleValueType();
10372 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10375 if (VT.getSizeInBits() == 8) {
10376 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10377 Op.getOperand(0), Op.getOperand(1));
10378 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10379 DAG.getValueType(VT));
10380 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10383 if (VT.getSizeInBits() == 16) {
10384 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10385 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10387 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10388 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10389 DAG.getNode(ISD::BITCAST, dl,
10392 Op.getOperand(1)));
10393 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10394 Op.getOperand(0), Op.getOperand(1));
10395 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10396 DAG.getValueType(VT));
10397 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10400 if (VT == MVT::f32) {
10401 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10402 // the result back to FR32 register. It's only worth matching if the
10403 // result has a single use which is a store or a bitcast to i32. And in
10404 // the case of a store, it's not worth it if the index is a constant 0,
10405 // because a MOVSSmr can be used instead, which is smaller and faster.
10406 if (!Op.hasOneUse())
10408 SDNode *User = *Op.getNode()->use_begin();
10409 if ((User->getOpcode() != ISD::STORE ||
10410 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10411 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10412 (User->getOpcode() != ISD::BITCAST ||
10413 User->getValueType(0) != MVT::i32))
10415 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10416 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10419 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10422 if (VT == MVT::i32 || VT == MVT::i64) {
10423 // ExtractPS/pextrq works with constant index.
10424 if (isa<ConstantSDNode>(Op.getOperand(1)))
10430 /// Extract one bit from mask vector, like v16i1 or v8i1.
10431 /// AVX-512 feature.
10433 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10434 SDValue Vec = Op.getOperand(0);
10436 MVT VecVT = Vec.getSimpleValueType();
10437 SDValue Idx = Op.getOperand(1);
10438 MVT EltVT = Op.getSimpleValueType();
10440 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10441 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10442 "Unexpected vector type in ExtractBitFromMaskVector");
10444 // variable index can't be handled in mask registers,
10445 // extend vector to VR512
10446 if (!isa<ConstantSDNode>(Idx)) {
10447 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10448 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10449 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10450 ExtVT.getVectorElementType(), Ext, Idx);
10451 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10454 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10455 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10456 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10457 rc = getRegClassFor(MVT::v16i1);
10458 unsigned MaxSift = rc->getSize()*8 - 1;
10459 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10460 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10461 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10462 DAG.getConstant(MaxSift, MVT::i8));
10463 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10464 DAG.getIntPtrConstant(0));
10468 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10469 SelectionDAG &DAG) const {
10471 SDValue Vec = Op.getOperand(0);
10472 MVT VecVT = Vec.getSimpleValueType();
10473 SDValue Idx = Op.getOperand(1);
10475 if (Op.getSimpleValueType() == MVT::i1)
10476 return ExtractBitFromMaskVector(Op, DAG);
10478 if (!isa<ConstantSDNode>(Idx)) {
10479 if (VecVT.is512BitVector() ||
10480 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10481 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10484 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10485 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10486 MaskEltVT.getSizeInBits());
10488 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10489 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10490 getZeroVector(MaskVT, Subtarget, DAG, dl),
10491 Idx, DAG.getConstant(0, getPointerTy()));
10492 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10493 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10494 Perm, DAG.getConstant(0, getPointerTy()));
10499 // If this is a 256-bit vector result, first extract the 128-bit vector and
10500 // then extract the element from the 128-bit vector.
10501 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10503 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10504 // Get the 128-bit vector.
10505 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10506 MVT EltVT = VecVT.getVectorElementType();
10508 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10510 //if (IdxVal >= NumElems/2)
10511 // IdxVal -= NumElems/2;
10512 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10513 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10514 DAG.getConstant(IdxVal, MVT::i32));
10517 assert(VecVT.is128BitVector() && "Unexpected vector length");
10519 if (Subtarget->hasSSE41()) {
10520 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10525 MVT VT = Op.getSimpleValueType();
10526 // TODO: handle v16i8.
10527 if (VT.getSizeInBits() == 16) {
10528 SDValue Vec = Op.getOperand(0);
10529 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10531 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10532 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10533 DAG.getNode(ISD::BITCAST, dl,
10535 Op.getOperand(1)));
10536 // Transform it so it match pextrw which produces a 32-bit result.
10537 MVT EltVT = MVT::i32;
10538 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10539 Op.getOperand(0), Op.getOperand(1));
10540 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10541 DAG.getValueType(VT));
10542 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10545 if (VT.getSizeInBits() == 32) {
10546 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10550 // SHUFPS the element to the lowest double word, then movss.
10551 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10552 MVT VVT = Op.getOperand(0).getSimpleValueType();
10553 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10554 DAG.getUNDEF(VVT), Mask);
10555 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10556 DAG.getIntPtrConstant(0));
10559 if (VT.getSizeInBits() == 64) {
10560 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10561 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10562 // to match extract_elt for f64.
10563 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10567 // UNPCKHPD the element to the lowest double word, then movsd.
10568 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10569 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10570 int Mask[2] = { 1, -1 };
10571 MVT VVT = Op.getOperand(0).getSimpleValueType();
10572 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10573 DAG.getUNDEF(VVT), Mask);
10574 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10575 DAG.getIntPtrConstant(0));
10581 /// Insert one bit to mask vector, like v16i1 or v8i1.
10582 /// AVX-512 feature.
10584 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10586 SDValue Vec = Op.getOperand(0);
10587 SDValue Elt = Op.getOperand(1);
10588 SDValue Idx = Op.getOperand(2);
10589 MVT VecVT = Vec.getSimpleValueType();
10591 if (!isa<ConstantSDNode>(Idx)) {
10592 // Non constant index. Extend source and destination,
10593 // insert element and then truncate the result.
10594 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10595 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10596 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10597 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10598 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10599 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10602 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10603 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10604 if (Vec.getOpcode() == ISD::UNDEF)
10605 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10606 DAG.getConstant(IdxVal, MVT::i8));
10607 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10608 unsigned MaxSift = rc->getSize()*8 - 1;
10609 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10610 DAG.getConstant(MaxSift, MVT::i8));
10611 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10612 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10613 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10616 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10617 SelectionDAG &DAG) const {
10618 MVT VT = Op.getSimpleValueType();
10619 MVT EltVT = VT.getVectorElementType();
10621 if (EltVT == MVT::i1)
10622 return InsertBitToMaskVector(Op, DAG);
10625 SDValue N0 = Op.getOperand(0);
10626 SDValue N1 = Op.getOperand(1);
10627 SDValue N2 = Op.getOperand(2);
10628 if (!isa<ConstantSDNode>(N2))
10630 auto *N2C = cast<ConstantSDNode>(N2);
10631 unsigned IdxVal = N2C->getZExtValue();
10633 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10634 // into that, and then insert the subvector back into the result.
10635 if (VT.is256BitVector() || VT.is512BitVector()) {
10636 // With a 256-bit vector, we can insert into the zero element efficiently
10637 // using a blend if we have AVX or AVX2 and the right data type.
10638 if (VT.is256BitVector() && IdxVal == 0) {
10639 // TODO: It is worthwhile to cast integer to floating point and back
10640 // and incur a domain crossing penalty if that's what we'll end up
10641 // doing anyway after extracting to a 128-bit vector.
10642 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10643 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10644 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10645 N2 = DAG.getIntPtrConstant(1);
10646 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10650 // Get the desired 128-bit vector chunk.
10651 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10653 // Insert the element into the desired chunk.
10654 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10655 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10657 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10658 DAG.getConstant(IdxIn128, MVT::i32));
10660 // Insert the changed part back into the bigger vector
10661 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10663 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10665 if (Subtarget->hasSSE41()) {
10666 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10668 if (VT == MVT::v8i16) {
10669 Opc = X86ISD::PINSRW;
10671 assert(VT == MVT::v16i8);
10672 Opc = X86ISD::PINSRB;
10675 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10677 if (N1.getValueType() != MVT::i32)
10678 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10679 if (N2.getValueType() != MVT::i32)
10680 N2 = DAG.getIntPtrConstant(IdxVal);
10681 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10684 if (EltVT == MVT::f32) {
10685 // Bits [7:6] of the constant are the source select. This will always be
10686 // zero here. The DAG Combiner may combine an extract_elt index into
10687 // these bits. For example (insert (extract, 3), 2) could be matched by
10688 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10689 // Bits [5:4] of the constant are the destination select. This is the
10690 // value of the incoming immediate.
10691 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10692 // combine either bitwise AND or insert of float 0.0 to set these bits.
10694 const Function *F = DAG.getMachineFunction().getFunction();
10695 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10696 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10697 // If this is an insertion of 32-bits into the low 32-bits of
10698 // a vector, we prefer to generate a blend with immediate rather
10699 // than an insertps. Blends are simpler operations in hardware and so
10700 // will always have equal or better performance than insertps.
10701 // But if optimizing for size and there's a load folding opportunity,
10702 // generate insertps because blendps does not have a 32-bit memory
10704 N2 = DAG.getIntPtrConstant(1);
10705 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10706 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10708 N2 = DAG.getIntPtrConstant(IdxVal << 4);
10709 // Create this as a scalar to vector..
10710 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10711 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10714 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10715 // PINSR* works with constant index.
10720 if (EltVT == MVT::i8)
10723 if (EltVT.getSizeInBits() == 16) {
10724 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10725 // as its second argument.
10726 if (N1.getValueType() != MVT::i32)
10727 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10728 if (N2.getValueType() != MVT::i32)
10729 N2 = DAG.getIntPtrConstant(IdxVal);
10730 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10735 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10737 MVT OpVT = Op.getSimpleValueType();
10739 // If this is a 256-bit vector result, first insert into a 128-bit
10740 // vector and then insert into the 256-bit vector.
10741 if (!OpVT.is128BitVector()) {
10742 // Insert into a 128-bit vector.
10743 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10744 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10745 OpVT.getVectorNumElements() / SizeFactor);
10747 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10749 // Insert the 128-bit vector.
10750 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10753 if (OpVT == MVT::v1i64 &&
10754 Op.getOperand(0).getValueType() == MVT::i64)
10755 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10757 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10758 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10759 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10760 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10763 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10764 // a simple subregister reference or explicit instructions to grab
10765 // upper bits of a vector.
10766 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10767 SelectionDAG &DAG) {
10769 SDValue In = Op.getOperand(0);
10770 SDValue Idx = Op.getOperand(1);
10771 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10772 MVT ResVT = Op.getSimpleValueType();
10773 MVT InVT = In.getSimpleValueType();
10775 if (Subtarget->hasFp256()) {
10776 if (ResVT.is128BitVector() &&
10777 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10778 isa<ConstantSDNode>(Idx)) {
10779 return Extract128BitVector(In, IdxVal, DAG, dl);
10781 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10782 isa<ConstantSDNode>(Idx)) {
10783 return Extract256BitVector(In, IdxVal, DAG, dl);
10789 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10790 // simple superregister reference or explicit instructions to insert
10791 // the upper bits of a vector.
10792 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10793 SelectionDAG &DAG) {
10794 if (!Subtarget->hasAVX())
10798 SDValue Vec = Op.getOperand(0);
10799 SDValue SubVec = Op.getOperand(1);
10800 SDValue Idx = Op.getOperand(2);
10802 if (!isa<ConstantSDNode>(Idx))
10805 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10806 MVT OpVT = Op.getSimpleValueType();
10807 MVT SubVecVT = SubVec.getSimpleValueType();
10809 // Fold two 16-byte subvector loads into one 32-byte load:
10810 // (insert_subvector (insert_subvector undef, (load addr), 0),
10811 // (load addr + 16), Elts/2)
10813 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10814 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10815 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10816 !Subtarget->isUnalignedMem32Slow()) {
10817 SDValue SubVec2 = Vec.getOperand(1);
10818 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10819 if (Idx2->getZExtValue() == 0) {
10820 SDValue Ops[] = { SubVec2, SubVec };
10821 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10828 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10829 SubVecVT.is128BitVector())
10830 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10832 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10833 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10835 if (OpVT.getVectorElementType() == MVT::i1) {
10836 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10838 SDValue ZeroIdx = DAG.getIntPtrConstant(0);
10839 SDValue Undef = DAG.getUNDEF(OpVT);
10840 unsigned NumElems = OpVT.getVectorNumElements();
10841 SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);
10843 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10844 // Zero upper bits of the Vec
10845 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10846 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10848 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10850 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10851 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10854 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10856 // Zero upper bits of the Vec2
10857 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10858 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10859 // Zero lower bits of the Vec
10860 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10861 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10862 // Merge them together
10863 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10869 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10870 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10871 // one of the above mentioned nodes. It has to be wrapped because otherwise
10872 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10873 // be used to form addressing mode. These wrapped nodes will be selected
10876 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10877 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10879 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10880 // global base reg.
10881 unsigned char OpFlag = 0;
10882 unsigned WrapperKind = X86ISD::Wrapper;
10883 CodeModel::Model M = DAG.getTarget().getCodeModel();
10885 if (Subtarget->isPICStyleRIPRel() &&
10886 (M == CodeModel::Small || M == CodeModel::Kernel))
10887 WrapperKind = X86ISD::WrapperRIP;
10888 else if (Subtarget->isPICStyleGOT())
10889 OpFlag = X86II::MO_GOTOFF;
10890 else if (Subtarget->isPICStyleStubPIC())
10891 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10893 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10894 CP->getAlignment(),
10895 CP->getOffset(), OpFlag);
10897 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10898 // With PIC, the address is actually $g + Offset.
10900 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10901 DAG.getNode(X86ISD::GlobalBaseReg,
10902 SDLoc(), getPointerTy()),
10909 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10910 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10912 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10913 // global base reg.
10914 unsigned char OpFlag = 0;
10915 unsigned WrapperKind = X86ISD::Wrapper;
10916 CodeModel::Model M = DAG.getTarget().getCodeModel();
10918 if (Subtarget->isPICStyleRIPRel() &&
10919 (M == CodeModel::Small || M == CodeModel::Kernel))
10920 WrapperKind = X86ISD::WrapperRIP;
10921 else if (Subtarget->isPICStyleGOT())
10922 OpFlag = X86II::MO_GOTOFF;
10923 else if (Subtarget->isPICStyleStubPIC())
10924 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10926 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10929 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10931 // With PIC, the address is actually $g + Offset.
10933 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10934 DAG.getNode(X86ISD::GlobalBaseReg,
10935 SDLoc(), getPointerTy()),
10942 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10943 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10945 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10946 // global base reg.
10947 unsigned char OpFlag = 0;
10948 unsigned WrapperKind = X86ISD::Wrapper;
10949 CodeModel::Model M = DAG.getTarget().getCodeModel();
10951 if (Subtarget->isPICStyleRIPRel() &&
10952 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10953 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10954 OpFlag = X86II::MO_GOTPCREL;
10955 WrapperKind = X86ISD::WrapperRIP;
10956 } else if (Subtarget->isPICStyleGOT()) {
10957 OpFlag = X86II::MO_GOT;
10958 } else if (Subtarget->isPICStyleStubPIC()) {
10959 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10960 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10961 OpFlag = X86II::MO_DARWIN_NONLAZY;
10964 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10967 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10969 // With PIC, the address is actually $g + Offset.
10970 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10971 !Subtarget->is64Bit()) {
10972 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10973 DAG.getNode(X86ISD::GlobalBaseReg,
10974 SDLoc(), getPointerTy()),
10978 // For symbols that require a load from a stub to get the address, emit the
10980 if (isGlobalStubReference(OpFlag))
10981 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10982 MachinePointerInfo::getGOT(), false, false, false, 0);
10988 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10989 // Create the TargetBlockAddressAddress node.
10990 unsigned char OpFlags =
10991 Subtarget->ClassifyBlockAddressReference();
10992 CodeModel::Model M = DAG.getTarget().getCodeModel();
10993 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10994 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10996 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10999 if (Subtarget->isPICStyleRIPRel() &&
11000 (M == CodeModel::Small || M == CodeModel::Kernel))
11001 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11003 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11005 // With PIC, the address is actually $g + Offset.
11006 if (isGlobalRelativeToPICBase(OpFlags)) {
11007 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11008 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11016 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11017 int64_t Offset, SelectionDAG &DAG) const {
11018 // Create the TargetGlobalAddress node, folding in the constant
11019 // offset if it is legal.
11020 unsigned char OpFlags =
11021 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11022 CodeModel::Model M = DAG.getTarget().getCodeModel();
11024 if (OpFlags == X86II::MO_NO_FLAG &&
11025 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11026 // A direct static reference to a global.
11027 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11030 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11033 if (Subtarget->isPICStyleRIPRel() &&
11034 (M == CodeModel::Small || M == CodeModel::Kernel))
11035 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11037 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11039 // With PIC, the address is actually $g + Offset.
11040 if (isGlobalRelativeToPICBase(OpFlags)) {
11041 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11042 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11046 // For globals that require a load from a stub to get the address, emit the
11048 if (isGlobalStubReference(OpFlags))
11049 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11050 MachinePointerInfo::getGOT(), false, false, false, 0);
11052 // If there was a non-zero offset that we didn't fold, create an explicit
11053 // addition for it.
11055 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11056 DAG.getConstant(Offset, getPointerTy()));
11062 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11063 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11064 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11065 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11069 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11070 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11071 unsigned char OperandFlags, bool LocalDynamic = false) {
11072 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11073 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11075 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11076 GA->getValueType(0),
11080 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11084 SDValue Ops[] = { Chain, TGA, *InFlag };
11085 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11087 SDValue Ops[] = { Chain, TGA };
11088 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11091 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11092 MFI->setAdjustsStack(true);
11093 MFI->setHasCalls(true);
11095 SDValue Flag = Chain.getValue(1);
11096 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11099 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11101 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11104 SDLoc dl(GA); // ? function entry point might be better
11105 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11106 DAG.getNode(X86ISD::GlobalBaseReg,
11107 SDLoc(), PtrVT), InFlag);
11108 InFlag = Chain.getValue(1);
11110 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11113 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11115 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11117 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11118 X86::RAX, X86II::MO_TLSGD);
11121 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11127 // Get the start address of the TLS block for this module.
11128 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11129 .getInfo<X86MachineFunctionInfo>();
11130 MFI->incNumLocalDynamicTLSAccesses();
11134 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11135 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11138 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11139 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11140 InFlag = Chain.getValue(1);
11141 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11142 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11145 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11149 unsigned char OperandFlags = X86II::MO_DTPOFF;
11150 unsigned WrapperKind = X86ISD::Wrapper;
11151 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11152 GA->getValueType(0),
11153 GA->getOffset(), OperandFlags);
11154 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11156 // Add x@dtpoff with the base.
11157 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11160 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11161 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11162 const EVT PtrVT, TLSModel::Model model,
11163 bool is64Bit, bool isPIC) {
11166 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11167 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11168 is64Bit ? 257 : 256));
11170 SDValue ThreadPointer =
11171 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11172 MachinePointerInfo(Ptr), false, false, false, 0);
11174 unsigned char OperandFlags = 0;
11175 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11177 unsigned WrapperKind = X86ISD::Wrapper;
11178 if (model == TLSModel::LocalExec) {
11179 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11180 } else if (model == TLSModel::InitialExec) {
11182 OperandFlags = X86II::MO_GOTTPOFF;
11183 WrapperKind = X86ISD::WrapperRIP;
11185 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11188 llvm_unreachable("Unexpected model");
11191 // emit "addl x@ntpoff,%eax" (local exec)
11192 // or "addl x@indntpoff,%eax" (initial exec)
11193 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11195 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11196 GA->getOffset(), OperandFlags);
11197 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11199 if (model == TLSModel::InitialExec) {
11200 if (isPIC && !is64Bit) {
11201 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11202 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11206 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11207 MachinePointerInfo::getGOT(), false, false, false, 0);
11210 // The address of the thread local variable is the add of the thread
11211 // pointer with the offset of the variable.
11212 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11216 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11218 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11219 const GlobalValue *GV = GA->getGlobal();
11221 if (Subtarget->isTargetELF()) {
11222 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11225 case TLSModel::GeneralDynamic:
11226 if (Subtarget->is64Bit())
11227 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11228 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11229 case TLSModel::LocalDynamic:
11230 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11231 Subtarget->is64Bit());
11232 case TLSModel::InitialExec:
11233 case TLSModel::LocalExec:
11234 return LowerToTLSExecModel(
11235 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11236 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11238 llvm_unreachable("Unknown TLS model.");
11241 if (Subtarget->isTargetDarwin()) {
11242 // Darwin only has one model of TLS. Lower to that.
11243 unsigned char OpFlag = 0;
11244 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11245 X86ISD::WrapperRIP : X86ISD::Wrapper;
11247 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11248 // global base reg.
11249 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11250 !Subtarget->is64Bit();
11252 OpFlag = X86II::MO_TLVP_PIC_BASE;
11254 OpFlag = X86II::MO_TLVP;
11256 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11257 GA->getValueType(0),
11258 GA->getOffset(), OpFlag);
11259 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11261 // With PIC32, the address is actually $g + Offset.
11263 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11264 DAG.getNode(X86ISD::GlobalBaseReg,
11265 SDLoc(), getPointerTy()),
11268 // Lowering the machine isd will make sure everything is in the right
11270 SDValue Chain = DAG.getEntryNode();
11271 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11272 SDValue Args[] = { Chain, Offset };
11273 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11275 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11276 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11277 MFI->setAdjustsStack(true);
11279 // And our return value (tls address) is in the standard call return value
11281 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11282 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11283 Chain.getValue(1));
11286 if (Subtarget->isTargetKnownWindowsMSVC() ||
11287 Subtarget->isTargetWindowsGNU()) {
11288 // Just use the implicit TLS architecture
11289 // Need to generate someting similar to:
11290 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11292 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11293 // mov rcx, qword [rdx+rcx*8]
11294 // mov eax, .tls$:tlsvar
11295 // [rax+rcx] contains the address
11296 // Windows 64bit: gs:0x58
11297 // Windows 32bit: fs:__tls_array
11300 SDValue Chain = DAG.getEntryNode();
11302 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11303 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11304 // use its literal value of 0x2C.
11305 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11306 ? Type::getInt8PtrTy(*DAG.getContext(),
11308 : Type::getInt32PtrTy(*DAG.getContext(),
11312 Subtarget->is64Bit()
11313 ? DAG.getIntPtrConstant(0x58)
11314 : (Subtarget->isTargetWindowsGNU()
11315 ? DAG.getIntPtrConstant(0x2C)
11316 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11318 SDValue ThreadPointer =
11319 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11320 MachinePointerInfo(Ptr), false, false, false, 0);
11322 // Load the _tls_index variable
11323 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11324 if (Subtarget->is64Bit())
11325 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11326 IDX, MachinePointerInfo(), MVT::i32,
11327 false, false, false, 0);
11329 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11330 false, false, false, 0);
11332 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11334 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11336 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11337 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11338 false, false, false, 0);
11340 // Get the offset of start of .tls section
11341 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11342 GA->getValueType(0),
11343 GA->getOffset(), X86II::MO_SECREL);
11344 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11346 // The address of the thread local variable is the add of the thread
11347 // pointer with the offset of the variable.
11348 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11351 llvm_unreachable("TLS not implemented for this target.");
11354 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11355 /// and take a 2 x i32 value to shift plus a shift amount.
11356 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11357 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11358 MVT VT = Op.getSimpleValueType();
11359 unsigned VTBits = VT.getSizeInBits();
11361 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11362 SDValue ShOpLo = Op.getOperand(0);
11363 SDValue ShOpHi = Op.getOperand(1);
11364 SDValue ShAmt = Op.getOperand(2);
11365 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11366 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11368 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11369 DAG.getConstant(VTBits - 1, MVT::i8));
11370 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11371 DAG.getConstant(VTBits - 1, MVT::i8))
11372 : DAG.getConstant(0, VT);
11374 SDValue Tmp2, Tmp3;
11375 if (Op.getOpcode() == ISD::SHL_PARTS) {
11376 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11377 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11379 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11380 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11383 // If the shift amount is larger or equal than the width of a part we can't
11384 // rely on the results of shld/shrd. Insert a test and select the appropriate
11385 // values for large shift amounts.
11386 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11387 DAG.getConstant(VTBits, MVT::i8));
11388 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11389 AndNode, DAG.getConstant(0, MVT::i8));
11392 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11393 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11394 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11396 if (Op.getOpcode() == ISD::SHL_PARTS) {
11397 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11398 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11400 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11401 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11404 SDValue Ops[2] = { Lo, Hi };
11405 return DAG.getMergeValues(Ops, dl);
11408 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11409 SelectionDAG &DAG) const {
11410 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11413 if (SrcVT.isVector()) {
11414 if (SrcVT.getVectorElementType() == MVT::i1) {
11415 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11416 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11417 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11418 Op.getOperand(0)));
11423 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11424 "Unknown SINT_TO_FP to lower!");
11426 // These are really Legal; return the operand so the caller accepts it as
11428 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11430 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11431 Subtarget->is64Bit()) {
11435 unsigned Size = SrcVT.getSizeInBits()/8;
11436 MachineFunction &MF = DAG.getMachineFunction();
11437 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11438 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11439 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11441 MachinePointerInfo::getFixedStack(SSFI),
11443 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11446 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11448 SelectionDAG &DAG) const {
11452 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11454 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11456 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11458 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11460 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11461 MachineMemOperand *MMO;
11463 int SSFI = FI->getIndex();
11465 DAG.getMachineFunction()
11466 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11467 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11469 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11470 StackSlot = StackSlot.getOperand(1);
11472 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11473 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11475 Tys, Ops, SrcVT, MMO);
11478 Chain = Result.getValue(1);
11479 SDValue InFlag = Result.getValue(2);
11481 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11482 // shouldn't be necessary except that RFP cannot be live across
11483 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11484 MachineFunction &MF = DAG.getMachineFunction();
11485 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11486 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11487 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11488 Tys = DAG.getVTList(MVT::Other);
11490 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11492 MachineMemOperand *MMO =
11493 DAG.getMachineFunction()
11494 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11495 MachineMemOperand::MOStore, SSFISize, SSFISize);
11497 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11498 Ops, Op.getValueType(), MMO);
11499 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11500 MachinePointerInfo::getFixedStack(SSFI),
11501 false, false, false, 0);
11507 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11508 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11509 SelectionDAG &DAG) const {
11510 // This algorithm is not obvious. Here it is what we're trying to output:
11513 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11514 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11516 haddpd %xmm0, %xmm0
11518 pshufd $0x4e, %xmm0, %xmm1
11524 LLVMContext *Context = DAG.getContext();
11526 // Build some magic constants.
11527 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11528 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11529 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11531 SmallVector<Constant*,2> CV1;
11533 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11534 APInt(64, 0x4330000000000000ULL))));
11536 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11537 APInt(64, 0x4530000000000000ULL))));
11538 Constant *C1 = ConstantVector::get(CV1);
11539 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11541 // Load the 64-bit value into an XMM register.
11542 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11544 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11545 MachinePointerInfo::getConstantPool(),
11546 false, false, false, 16);
11547 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11548 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11551 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11552 MachinePointerInfo::getConstantPool(),
11553 false, false, false, 16);
11554 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11555 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11558 if (Subtarget->hasSSE3()) {
11559 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11560 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11562 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11563 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11565 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11566 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11570 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11571 DAG.getIntPtrConstant(0));
11574 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11575 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11576 SelectionDAG &DAG) const {
11578 // FP constant to bias correct the final result.
11579 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11582 // Load the 32-bit value into an XMM register.
11583 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11586 // Zero out the upper parts of the register.
11587 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11589 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11590 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11591 DAG.getIntPtrConstant(0));
11593 // Or the load with the bias.
11594 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11595 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11596 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11597 MVT::v2f64, Load)),
11598 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11599 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11600 MVT::v2f64, Bias)));
11601 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11602 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11603 DAG.getIntPtrConstant(0));
11605 // Subtract the bias.
11606 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11608 // Handle final rounding.
11609 EVT DestVT = Op.getValueType();
11611 if (DestVT.bitsLT(MVT::f64))
11612 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11613 DAG.getIntPtrConstant(0));
11614 if (DestVT.bitsGT(MVT::f64))
11615 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11617 // Handle final rounding.
11621 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11622 const X86Subtarget &Subtarget) {
11623 // The algorithm is the following:
11624 // #ifdef __SSE4_1__
11625 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11626 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11627 // (uint4) 0x53000000, 0xaa);
11629 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11630 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11632 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11633 // return (float4) lo + fhi;
11636 SDValue V = Op->getOperand(0);
11637 EVT VecIntVT = V.getValueType();
11638 bool Is128 = VecIntVT == MVT::v4i32;
11639 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11640 // If we convert to something else than the supported type, e.g., to v4f64,
11642 if (VecFloatVT != Op->getValueType(0))
11645 unsigned NumElts = VecIntVT.getVectorNumElements();
11646 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11647 "Unsupported custom type");
11648 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11650 // In the #idef/#else code, we have in common:
11651 // - The vector of constants:
11657 // Create the splat vector for 0x4b000000.
11658 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
11659 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11660 CstLow, CstLow, CstLow, CstLow};
11661 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11662 makeArrayRef(&CstLowArray[0], NumElts));
11663 // Create the splat vector for 0x53000000.
11664 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
11665 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11666 CstHigh, CstHigh, CstHigh, CstHigh};
11667 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11668 makeArrayRef(&CstHighArray[0], NumElts));
11670 // Create the right shift.
11671 SDValue CstShift = DAG.getConstant(16, MVT::i32);
11672 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11673 CstShift, CstShift, CstShift, CstShift};
11674 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11675 makeArrayRef(&CstShiftArray[0], NumElts));
11676 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11679 if (Subtarget.hasSSE41()) {
11680 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11681 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11682 SDValue VecCstLowBitcast =
11683 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11684 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11685 // Low will be bitcasted right away, so do not bother bitcasting back to its
11687 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11688 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
11689 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11690 // (uint4) 0x53000000, 0xaa);
11691 SDValue VecCstHighBitcast =
11692 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11693 SDValue VecShiftBitcast =
11694 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11695 // High will be bitcasted right away, so do not bother bitcasting back to
11696 // its original type.
11697 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11698 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
11700 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
11701 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11702 CstMask, CstMask, CstMask);
11703 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11704 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11705 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11707 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11708 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11711 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11712 SDValue CstFAdd = DAG.getConstantFP(
11713 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
11714 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11715 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11716 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11717 makeArrayRef(&CstFAddArray[0], NumElts));
11719 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11720 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11722 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11723 // return (float4) lo + fhi;
11724 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11725 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11728 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11729 SelectionDAG &DAG) const {
11730 SDValue N0 = Op.getOperand(0);
11731 MVT SVT = N0.getSimpleValueType();
11734 switch (SVT.SimpleTy) {
11736 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11741 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11742 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11743 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11747 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11749 llvm_unreachable(nullptr);
11752 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11753 SelectionDAG &DAG) const {
11754 SDValue N0 = Op.getOperand(0);
11757 if (Op.getValueType().isVector())
11758 return lowerUINT_TO_FP_vec(Op, DAG);
11760 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11761 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11762 // the optimization here.
11763 if (DAG.SignBitIsZero(N0))
11764 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11766 MVT SrcVT = N0.getSimpleValueType();
11767 MVT DstVT = Op.getSimpleValueType();
11768 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11769 return LowerUINT_TO_FP_i64(Op, DAG);
11770 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11771 return LowerUINT_TO_FP_i32(Op, DAG);
11772 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11775 // Make a 64-bit buffer, and use it to build an FILD.
11776 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11777 if (SrcVT == MVT::i32) {
11778 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11779 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11780 getPointerTy(), StackSlot, WordOff);
11781 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11782 StackSlot, MachinePointerInfo(),
11784 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11785 OffsetSlot, MachinePointerInfo(),
11787 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11791 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11792 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11793 StackSlot, MachinePointerInfo(),
11795 // For i64 source, we need to add the appropriate power of 2 if the input
11796 // was negative. This is the same as the optimization in
11797 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11798 // we must be careful to do the computation in x87 extended precision, not
11799 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11800 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11801 MachineMemOperand *MMO =
11802 DAG.getMachineFunction()
11803 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11804 MachineMemOperand::MOLoad, 8, 8);
11806 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11807 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11808 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11811 APInt FF(32, 0x5F800000ULL);
11813 // Check whether the sign bit is set.
11814 SDValue SignSet = DAG.getSetCC(dl,
11815 getSetCCResultType(*DAG.getContext(), MVT::i64),
11816 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11819 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11820 SDValue FudgePtr = DAG.getConstantPool(
11821 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11824 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11825 SDValue Zero = DAG.getIntPtrConstant(0);
11826 SDValue Four = DAG.getIntPtrConstant(4);
11827 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11829 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11831 // Load the value out, extending it from f32 to f80.
11832 // FIXME: Avoid the extend by constructing the right constant pool?
11833 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11834 FudgePtr, MachinePointerInfo::getConstantPool(),
11835 MVT::f32, false, false, false, 4);
11836 // Extend everything to 80 bits to force it to be done on x87.
11837 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11838 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11841 std::pair<SDValue,SDValue>
11842 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11843 bool IsSigned, bool IsReplace) const {
11846 EVT DstTy = Op.getValueType();
11848 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11849 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11853 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11854 DstTy.getSimpleVT() >= MVT::i16 &&
11855 "Unknown FP_TO_INT to lower!");
11857 // These are really Legal.
11858 if (DstTy == MVT::i32 &&
11859 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11860 return std::make_pair(SDValue(), SDValue());
11861 if (Subtarget->is64Bit() &&
11862 DstTy == MVT::i64 &&
11863 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11864 return std::make_pair(SDValue(), SDValue());
11866 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11867 // stack slot, or into the FTOL runtime function.
11868 MachineFunction &MF = DAG.getMachineFunction();
11869 unsigned MemSize = DstTy.getSizeInBits()/8;
11870 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11871 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11874 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11875 Opc = X86ISD::WIN_FTOL;
11877 switch (DstTy.getSimpleVT().SimpleTy) {
11878 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11879 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11880 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11881 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11884 SDValue Chain = DAG.getEntryNode();
11885 SDValue Value = Op.getOperand(0);
11886 EVT TheVT = Op.getOperand(0).getValueType();
11887 // FIXME This causes a redundant load/store if the SSE-class value is already
11888 // in memory, such as if it is on the callstack.
11889 if (isScalarFPTypeInSSEReg(TheVT)) {
11890 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11891 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11892 MachinePointerInfo::getFixedStack(SSFI),
11894 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11896 Chain, StackSlot, DAG.getValueType(TheVT)
11899 MachineMemOperand *MMO =
11900 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11901 MachineMemOperand::MOLoad, MemSize, MemSize);
11902 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11903 Chain = Value.getValue(1);
11904 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11905 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11908 MachineMemOperand *MMO =
11909 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11910 MachineMemOperand::MOStore, MemSize, MemSize);
11912 if (Opc != X86ISD::WIN_FTOL) {
11913 // Build the FP_TO_INT*_IN_MEM
11914 SDValue Ops[] = { Chain, Value, StackSlot };
11915 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11917 return std::make_pair(FIST, StackSlot);
11919 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11920 DAG.getVTList(MVT::Other, MVT::Glue),
11922 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11923 MVT::i32, ftol.getValue(1));
11924 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11925 MVT::i32, eax.getValue(2));
11926 SDValue Ops[] = { eax, edx };
11927 SDValue pair = IsReplace
11928 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11929 : DAG.getMergeValues(Ops, DL);
11930 return std::make_pair(pair, SDValue());
11934 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11935 const X86Subtarget *Subtarget) {
11936 MVT VT = Op->getSimpleValueType(0);
11937 SDValue In = Op->getOperand(0);
11938 MVT InVT = In.getSimpleValueType();
11941 // Optimize vectors in AVX mode:
11944 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11945 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11946 // Concat upper and lower parts.
11949 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11950 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11951 // Concat upper and lower parts.
11954 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11955 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11956 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11959 if (Subtarget->hasInt256())
11960 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11962 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11963 SDValue Undef = DAG.getUNDEF(InVT);
11964 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11965 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11966 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11968 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11969 VT.getVectorNumElements()/2);
11971 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11972 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11974 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11977 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11978 SelectionDAG &DAG) {
11979 MVT VT = Op->getSimpleValueType(0);
11980 SDValue In = Op->getOperand(0);
11981 MVT InVT = In.getSimpleValueType();
11983 unsigned int NumElts = VT.getVectorNumElements();
11984 if (NumElts != 8 && NumElts != 16)
11987 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11988 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11990 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11991 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11992 // Now we have only mask extension
11993 assert(InVT.getVectorElementType() == MVT::i1);
11994 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11995 const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();
11996 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11997 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11998 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11999 MachinePointerInfo::getConstantPool(),
12000 false, false, false, Alignment);
12002 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12003 if (VT.is512BitVector())
12005 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12008 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12009 SelectionDAG &DAG) {
12010 if (Subtarget->hasFp256()) {
12011 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12019 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12020 SelectionDAG &DAG) {
12022 MVT VT = Op.getSimpleValueType();
12023 SDValue In = Op.getOperand(0);
12024 MVT SVT = In.getSimpleValueType();
12026 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12027 return LowerZERO_EXTEND_AVX512(Op, DAG);
12029 if (Subtarget->hasFp256()) {
12030 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12035 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12036 VT.getVectorNumElements() != SVT.getVectorNumElements());
12040 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12042 MVT VT = Op.getSimpleValueType();
12043 SDValue In = Op.getOperand(0);
12044 MVT InVT = In.getSimpleValueType();
12046 if (VT == MVT::i1) {
12047 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12048 "Invalid scalar TRUNCATE operation");
12049 if (InVT.getSizeInBits() >= 32)
12051 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12052 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12054 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12055 "Invalid TRUNCATE operation");
12057 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12058 if (VT.getVectorElementType().getSizeInBits() >=8)
12059 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12061 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12062 unsigned NumElts = InVT.getVectorNumElements();
12063 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12064 if (InVT.getSizeInBits() < 512) {
12065 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12066 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12070 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12071 const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();
12072 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12073 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12074 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12075 MachinePointerInfo::getConstantPool(),
12076 false, false, false, Alignment);
12077 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12078 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12079 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12082 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12083 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12084 if (Subtarget->hasInt256()) {
12085 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12086 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12087 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12089 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12090 DAG.getIntPtrConstant(0));
12093 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12094 DAG.getIntPtrConstant(0));
12095 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12096 DAG.getIntPtrConstant(2));
12097 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12098 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12099 static const int ShufMask[] = {0, 2, 4, 6};
12100 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12103 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12104 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12105 if (Subtarget->hasInt256()) {
12106 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12108 SmallVector<SDValue,32> pshufbMask;
12109 for (unsigned i = 0; i < 2; ++i) {
12110 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12111 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12112 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12113 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12114 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12115 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12116 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12117 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12118 for (unsigned j = 0; j < 8; ++j)
12119 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12121 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12122 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12123 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12125 static const int ShufMask[] = {0, 2, -1, -1};
12126 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12128 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12129 DAG.getIntPtrConstant(0));
12130 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12133 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12134 DAG.getIntPtrConstant(0));
12136 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12137 DAG.getIntPtrConstant(4));
12139 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12140 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12142 // The PSHUFB mask:
12143 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12144 -1, -1, -1, -1, -1, -1, -1, -1};
12146 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12147 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12148 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12150 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12151 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12153 // The MOVLHPS Mask:
12154 static const int ShufMask2[] = {0, 1, 4, 5};
12155 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12156 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12159 // Handle truncation of V256 to V128 using shuffles.
12160 if (!VT.is128BitVector() || !InVT.is256BitVector())
12163 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12165 unsigned NumElems = VT.getVectorNumElements();
12166 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12168 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12169 // Prepare truncation shuffle mask
12170 for (unsigned i = 0; i != NumElems; ++i)
12171 MaskVec[i] = i * 2;
12172 SDValue V = DAG.getVectorShuffle(NVT, DL,
12173 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12174 DAG.getUNDEF(NVT), &MaskVec[0]);
12175 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12176 DAG.getIntPtrConstant(0));
12179 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12180 SelectionDAG &DAG) const {
12181 assert(!Op.getSimpleValueType().isVector());
12183 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12184 /*IsSigned=*/ true, /*IsReplace=*/ false);
12185 SDValue FIST = Vals.first, StackSlot = Vals.second;
12186 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12187 if (!FIST.getNode()) return Op;
12189 if (StackSlot.getNode())
12190 // Load the result.
12191 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12192 FIST, StackSlot, MachinePointerInfo(),
12193 false, false, false, 0);
12195 // The node is the result.
12199 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12200 SelectionDAG &DAG) const {
12201 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12202 /*IsSigned=*/ false, /*IsReplace=*/ false);
12203 SDValue FIST = Vals.first, StackSlot = Vals.second;
12204 assert(FIST.getNode() && "Unexpected failure");
12206 if (StackSlot.getNode())
12207 // Load the result.
12208 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12209 FIST, StackSlot, MachinePointerInfo(),
12210 false, false, false, 0);
12212 // The node is the result.
12216 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12218 MVT VT = Op.getSimpleValueType();
12219 SDValue In = Op.getOperand(0);
12220 MVT SVT = In.getSimpleValueType();
12222 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12224 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12225 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12226 In, DAG.getUNDEF(SVT)));
12229 /// The only differences between FABS and FNEG are the mask and the logic op.
12230 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12231 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12232 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12233 "Wrong opcode for lowering FABS or FNEG.");
12235 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12237 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12238 // into an FNABS. We'll lower the FABS after that if it is still in use.
12240 for (SDNode *User : Op->uses())
12241 if (User->getOpcode() == ISD::FNEG)
12244 SDValue Op0 = Op.getOperand(0);
12245 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12248 MVT VT = Op.getSimpleValueType();
12249 // Assume scalar op for initialization; update for vector if needed.
12250 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12251 // generate a 16-byte vector constant and logic op even for the scalar case.
12252 // Using a 16-byte mask allows folding the load of the mask with
12253 // the logic op, so it can save (~4 bytes) on code size.
12255 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12256 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12257 // decide if we should generate a 16-byte constant mask when we only need 4 or
12258 // 8 bytes for the scalar case.
12259 if (VT.isVector()) {
12260 EltVT = VT.getVectorElementType();
12261 NumElts = VT.getVectorNumElements();
12264 unsigned EltBits = EltVT.getSizeInBits();
12265 LLVMContext *Context = DAG.getContext();
12266 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12268 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12269 Constant *C = ConstantInt::get(*Context, MaskElt);
12270 C = ConstantVector::getSplat(NumElts, C);
12271 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12272 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12273 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12274 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12275 MachinePointerInfo::getConstantPool(),
12276 false, false, false, Alignment);
12278 if (VT.isVector()) {
12279 // For a vector, cast operands to a vector type, perform the logic op,
12280 // and cast the result back to the original value type.
12281 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12282 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12283 SDValue Operand = IsFNABS ?
12284 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12285 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12286 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12287 return DAG.getNode(ISD::BITCAST, dl, VT,
12288 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12291 // If not vector, then scalar.
12292 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12293 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12294 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12297 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12299 LLVMContext *Context = DAG.getContext();
12300 SDValue Op0 = Op.getOperand(0);
12301 SDValue Op1 = Op.getOperand(1);
12303 MVT VT = Op.getSimpleValueType();
12304 MVT SrcVT = Op1.getSimpleValueType();
12306 // If second operand is smaller, extend it first.
12307 if (SrcVT.bitsLT(VT)) {
12308 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12311 // And if it is bigger, shrink it first.
12312 if (SrcVT.bitsGT(VT)) {
12313 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12317 // At this point the operands and the result should have the same
12318 // type, and that won't be f80 since that is not custom lowered.
12320 const fltSemantics &Sem =
12321 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12322 const unsigned SizeInBits = VT.getSizeInBits();
12324 SmallVector<Constant *, 4> CV(
12325 VT == MVT::f64 ? 2 : 4,
12326 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12328 // First, clear all bits but the sign bit from the second operand (sign).
12329 CV[0] = ConstantFP::get(*Context,
12330 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12331 Constant *C = ConstantVector::get(CV);
12332 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12333 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12334 MachinePointerInfo::getConstantPool(),
12335 false, false, false, 16);
12336 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12338 // Next, clear the sign bit from the first operand (magnitude).
12339 // If it's a constant, we can clear it here.
12340 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12341 APFloat APF = Op0CN->getValueAPF();
12342 // If the magnitude is a positive zero, the sign bit alone is enough.
12343 if (APF.isPosZero())
12346 CV[0] = ConstantFP::get(*Context, APF);
12348 CV[0] = ConstantFP::get(
12350 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12352 C = ConstantVector::get(CV);
12353 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12354 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12355 MachinePointerInfo::getConstantPool(),
12356 false, false, false, 16);
12357 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12358 if (!isa<ConstantFPSDNode>(Op0))
12359 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12361 // OR the magnitude value with the sign bit.
12362 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12365 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12366 SDValue N0 = Op.getOperand(0);
12368 MVT VT = Op.getSimpleValueType();
12370 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12371 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12372 DAG.getConstant(1, VT));
12373 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12376 // Check whether an OR'd tree is PTEST-able.
12377 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12378 SelectionDAG &DAG) {
12379 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12381 if (!Subtarget->hasSSE41())
12384 if (!Op->hasOneUse())
12387 SDNode *N = Op.getNode();
12390 SmallVector<SDValue, 8> Opnds;
12391 DenseMap<SDValue, unsigned> VecInMap;
12392 SmallVector<SDValue, 8> VecIns;
12393 EVT VT = MVT::Other;
12395 // Recognize a special case where a vector is casted into wide integer to
12397 Opnds.push_back(N->getOperand(0));
12398 Opnds.push_back(N->getOperand(1));
12400 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12401 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12402 // BFS traverse all OR'd operands.
12403 if (I->getOpcode() == ISD::OR) {
12404 Opnds.push_back(I->getOperand(0));
12405 Opnds.push_back(I->getOperand(1));
12406 // Re-evaluate the number of nodes to be traversed.
12407 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12411 // Quit if a non-EXTRACT_VECTOR_ELT
12412 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12415 // Quit if without a constant index.
12416 SDValue Idx = I->getOperand(1);
12417 if (!isa<ConstantSDNode>(Idx))
12420 SDValue ExtractedFromVec = I->getOperand(0);
12421 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12422 if (M == VecInMap.end()) {
12423 VT = ExtractedFromVec.getValueType();
12424 // Quit if not 128/256-bit vector.
12425 if (!VT.is128BitVector() && !VT.is256BitVector())
12427 // Quit if not the same type.
12428 if (VecInMap.begin() != VecInMap.end() &&
12429 VT != VecInMap.begin()->first.getValueType())
12431 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12432 VecIns.push_back(ExtractedFromVec);
12434 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12437 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12438 "Not extracted from 128-/256-bit vector.");
12440 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12442 for (DenseMap<SDValue, unsigned>::const_iterator
12443 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12444 // Quit if not all elements are used.
12445 if (I->second != FullMask)
12449 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12451 // Cast all vectors into TestVT for PTEST.
12452 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12453 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12455 // If more than one full vectors are evaluated, OR them first before PTEST.
12456 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12457 // Each iteration will OR 2 nodes and append the result until there is only
12458 // 1 node left, i.e. the final OR'd value of all vectors.
12459 SDValue LHS = VecIns[Slot];
12460 SDValue RHS = VecIns[Slot + 1];
12461 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12464 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12465 VecIns.back(), VecIns.back());
12468 /// \brief return true if \c Op has a use that doesn't just read flags.
12469 static bool hasNonFlagsUse(SDValue Op) {
12470 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12472 SDNode *User = *UI;
12473 unsigned UOpNo = UI.getOperandNo();
12474 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12475 // Look pass truncate.
12476 UOpNo = User->use_begin().getOperandNo();
12477 User = *User->use_begin();
12480 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12481 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12487 /// Emit nodes that will be selected as "test Op0,Op0", or something
12489 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12490 SelectionDAG &DAG) const {
12491 if (Op.getValueType() == MVT::i1) {
12492 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12493 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12494 DAG.getConstant(0, MVT::i8));
12496 // CF and OF aren't always set the way we want. Determine which
12497 // of these we need.
12498 bool NeedCF = false;
12499 bool NeedOF = false;
12502 case X86::COND_A: case X86::COND_AE:
12503 case X86::COND_B: case X86::COND_BE:
12506 case X86::COND_G: case X86::COND_GE:
12507 case X86::COND_L: case X86::COND_LE:
12508 case X86::COND_O: case X86::COND_NO: {
12509 // Check if we really need to set the
12510 // Overflow flag. If NoSignedWrap is present
12511 // that is not actually needed.
12512 switch (Op->getOpcode()) {
12517 const BinaryWithFlagsSDNode *BinNode =
12518 cast<BinaryWithFlagsSDNode>(Op.getNode());
12519 if (BinNode->hasNoSignedWrap())
12529 // See if we can use the EFLAGS value from the operand instead of
12530 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12531 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12532 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12533 // Emit a CMP with 0, which is the TEST pattern.
12534 //if (Op.getValueType() == MVT::i1)
12535 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12536 // DAG.getConstant(0, MVT::i1));
12537 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12538 DAG.getConstant(0, Op.getValueType()));
12540 unsigned Opcode = 0;
12541 unsigned NumOperands = 0;
12543 // Truncate operations may prevent the merge of the SETCC instruction
12544 // and the arithmetic instruction before it. Attempt to truncate the operands
12545 // of the arithmetic instruction and use a reduced bit-width instruction.
12546 bool NeedTruncation = false;
12547 SDValue ArithOp = Op;
12548 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12549 SDValue Arith = Op->getOperand(0);
12550 // Both the trunc and the arithmetic op need to have one user each.
12551 if (Arith->hasOneUse())
12552 switch (Arith.getOpcode()) {
12559 NeedTruncation = true;
12565 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12566 // which may be the result of a CAST. We use the variable 'Op', which is the
12567 // non-casted variable when we check for possible users.
12568 switch (ArithOp.getOpcode()) {
12570 // Due to an isel shortcoming, be conservative if this add is likely to be
12571 // selected as part of a load-modify-store instruction. When the root node
12572 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12573 // uses of other nodes in the match, such as the ADD in this case. This
12574 // leads to the ADD being left around and reselected, with the result being
12575 // two adds in the output. Alas, even if none our users are stores, that
12576 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12577 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12578 // climbing the DAG back to the root, and it doesn't seem to be worth the
12580 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12581 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12582 if (UI->getOpcode() != ISD::CopyToReg &&
12583 UI->getOpcode() != ISD::SETCC &&
12584 UI->getOpcode() != ISD::STORE)
12587 if (ConstantSDNode *C =
12588 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12589 // An add of one will be selected as an INC.
12590 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12591 Opcode = X86ISD::INC;
12596 // An add of negative one (subtract of one) will be selected as a DEC.
12597 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12598 Opcode = X86ISD::DEC;
12604 // Otherwise use a regular EFLAGS-setting add.
12605 Opcode = X86ISD::ADD;
12610 // If we have a constant logical shift that's only used in a comparison
12611 // against zero turn it into an equivalent AND. This allows turning it into
12612 // a TEST instruction later.
12613 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12614 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12615 EVT VT = Op.getValueType();
12616 unsigned BitWidth = VT.getSizeInBits();
12617 unsigned ShAmt = Op->getConstantOperandVal(1);
12618 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12620 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12621 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12622 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12623 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12625 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12626 DAG.getConstant(Mask, VT));
12627 DAG.ReplaceAllUsesWith(Op, New);
12633 // If the primary and result isn't used, don't bother using X86ISD::AND,
12634 // because a TEST instruction will be better.
12635 if (!hasNonFlagsUse(Op))
12641 // Due to the ISEL shortcoming noted above, be conservative if this op is
12642 // likely to be selected as part of a load-modify-store instruction.
12643 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12644 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12645 if (UI->getOpcode() == ISD::STORE)
12648 // Otherwise use a regular EFLAGS-setting instruction.
12649 switch (ArithOp.getOpcode()) {
12650 default: llvm_unreachable("unexpected operator!");
12651 case ISD::SUB: Opcode = X86ISD::SUB; break;
12652 case ISD::XOR: Opcode = X86ISD::XOR; break;
12653 case ISD::AND: Opcode = X86ISD::AND; break;
12655 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12656 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12657 if (EFLAGS.getNode())
12660 Opcode = X86ISD::OR;
12674 return SDValue(Op.getNode(), 1);
12680 // If we found that truncation is beneficial, perform the truncation and
12682 if (NeedTruncation) {
12683 EVT VT = Op.getValueType();
12684 SDValue WideVal = Op->getOperand(0);
12685 EVT WideVT = WideVal.getValueType();
12686 unsigned ConvertedOp = 0;
12687 // Use a target machine opcode to prevent further DAGCombine
12688 // optimizations that may separate the arithmetic operations
12689 // from the setcc node.
12690 switch (WideVal.getOpcode()) {
12692 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12693 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12694 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12695 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12696 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12700 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12701 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12702 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12703 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12704 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12710 // Emit a CMP with 0, which is the TEST pattern.
12711 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12712 DAG.getConstant(0, Op.getValueType()));
12714 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12715 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12717 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12718 DAG.ReplaceAllUsesWith(Op, New);
12719 return SDValue(New.getNode(), 1);
12722 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12724 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12725 SDLoc dl, SelectionDAG &DAG) const {
12726 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12727 if (C->getAPIntValue() == 0)
12728 return EmitTest(Op0, X86CC, dl, DAG);
12730 if (Op0.getValueType() == MVT::i1)
12731 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12734 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12735 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12736 // Do the comparison at i32 if it's smaller, besides the Atom case.
12737 // This avoids subregister aliasing issues. Keep the smaller reference
12738 // if we're optimizing for size, however, as that'll allow better folding
12739 // of memory operations.
12740 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12741 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12742 Attribute::MinSize) &&
12743 !Subtarget->isAtom()) {
12744 unsigned ExtendOp =
12745 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12746 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12747 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12749 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12750 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12751 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12753 return SDValue(Sub.getNode(), 1);
12755 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12758 /// Convert a comparison if required by the subtarget.
12759 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12760 SelectionDAG &DAG) const {
12761 // If the subtarget does not support the FUCOMI instruction, floating-point
12762 // comparisons have to be converted.
12763 if (Subtarget->hasCMov() ||
12764 Cmp.getOpcode() != X86ISD::CMP ||
12765 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12766 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12769 // The instruction selector will select an FUCOM instruction instead of
12770 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12771 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12772 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12774 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12775 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12776 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12777 DAG.getConstant(8, MVT::i8));
12778 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12779 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12782 /// The minimum architected relative accuracy is 2^-12. We need one
12783 /// Newton-Raphson step to have a good float result (24 bits of precision).
12784 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12785 DAGCombinerInfo &DCI,
12786 unsigned &RefinementSteps,
12787 bool &UseOneConstNR) const {
12788 // FIXME: We should use instruction latency models to calculate the cost of
12789 // each potential sequence, but this is very hard to do reliably because
12790 // at least Intel's Core* chips have variable timing based on the number of
12791 // significant digits in the divisor and/or sqrt operand.
12792 if (!Subtarget->useSqrtEst())
12795 EVT VT = Op.getValueType();
12797 // SSE1 has rsqrtss and rsqrtps.
12798 // TODO: Add support for AVX512 (v16f32).
12799 // It is likely not profitable to do this for f64 because a double-precision
12800 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12801 // instructions: convert to single, rsqrtss, convert back to double, refine
12802 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12803 // along with FMA, this could be a throughput win.
12804 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12805 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12806 RefinementSteps = 1;
12807 UseOneConstNR = false;
12808 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12813 /// The minimum architected relative accuracy is 2^-12. We need one
12814 /// Newton-Raphson step to have a good float result (24 bits of precision).
12815 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12816 DAGCombinerInfo &DCI,
12817 unsigned &RefinementSteps) const {
12818 // FIXME: We should use instruction latency models to calculate the cost of
12819 // each potential sequence, but this is very hard to do reliably because
12820 // at least Intel's Core* chips have variable timing based on the number of
12821 // significant digits in the divisor.
12822 if (!Subtarget->useReciprocalEst())
12825 EVT VT = Op.getValueType();
12827 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12828 // TODO: Add support for AVX512 (v16f32).
12829 // It is likely not profitable to do this for f64 because a double-precision
12830 // reciprocal estimate with refinement on x86 prior to FMA requires
12831 // 15 instructions: convert to single, rcpss, convert back to double, refine
12832 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12833 // along with FMA, this could be a throughput win.
12834 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12835 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12836 RefinementSteps = ReciprocalEstimateRefinementSteps;
12837 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12842 /// If we have at least two divisions that use the same divisor, convert to
12843 /// multplication by a reciprocal. This may need to be adjusted for a given
12844 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12845 /// This is because we still need one division to calculate the reciprocal and
12846 /// then we need two multiplies by that reciprocal as replacements for the
12847 /// original divisions.
12848 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
12849 return NumUsers > 1;
12852 static bool isAllOnes(SDValue V) {
12853 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12854 return C && C->isAllOnesValue();
12857 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12858 /// if it's possible.
12859 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12860 SDLoc dl, SelectionDAG &DAG) const {
12861 SDValue Op0 = And.getOperand(0);
12862 SDValue Op1 = And.getOperand(1);
12863 if (Op0.getOpcode() == ISD::TRUNCATE)
12864 Op0 = Op0.getOperand(0);
12865 if (Op1.getOpcode() == ISD::TRUNCATE)
12866 Op1 = Op1.getOperand(0);
12869 if (Op1.getOpcode() == ISD::SHL)
12870 std::swap(Op0, Op1);
12871 if (Op0.getOpcode() == ISD::SHL) {
12872 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12873 if (And00C->getZExtValue() == 1) {
12874 // If we looked past a truncate, check that it's only truncating away
12876 unsigned BitWidth = Op0.getValueSizeInBits();
12877 unsigned AndBitWidth = And.getValueSizeInBits();
12878 if (BitWidth > AndBitWidth) {
12880 DAG.computeKnownBits(Op0, Zeros, Ones);
12881 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12885 RHS = Op0.getOperand(1);
12887 } else if (Op1.getOpcode() == ISD::Constant) {
12888 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12889 uint64_t AndRHSVal = AndRHS->getZExtValue();
12890 SDValue AndLHS = Op0;
12892 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12893 LHS = AndLHS.getOperand(0);
12894 RHS = AndLHS.getOperand(1);
12897 // Use BT if the immediate can't be encoded in a TEST instruction.
12898 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12900 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12904 if (LHS.getNode()) {
12905 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12906 // instruction. Since the shift amount is in-range-or-undefined, we know
12907 // that doing a bittest on the i32 value is ok. We extend to i32 because
12908 // the encoding for the i16 version is larger than the i32 version.
12909 // Also promote i16 to i32 for performance / code size reason.
12910 if (LHS.getValueType() == MVT::i8 ||
12911 LHS.getValueType() == MVT::i16)
12912 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12914 // If the operand types disagree, extend the shift amount to match. Since
12915 // BT ignores high bits (like shifts) we can use anyextend.
12916 if (LHS.getValueType() != RHS.getValueType())
12917 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12919 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12920 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12921 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12922 DAG.getConstant(Cond, MVT::i8), BT);
12928 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12930 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12935 // SSE Condition code mapping:
12944 switch (SetCCOpcode) {
12945 default: llvm_unreachable("Unexpected SETCC condition");
12947 case ISD::SETEQ: SSECC = 0; break;
12949 case ISD::SETGT: Swap = true; // Fallthrough
12951 case ISD::SETOLT: SSECC = 1; break;
12953 case ISD::SETGE: Swap = true; // Fallthrough
12955 case ISD::SETOLE: SSECC = 2; break;
12956 case ISD::SETUO: SSECC = 3; break;
12958 case ISD::SETNE: SSECC = 4; break;
12959 case ISD::SETULE: Swap = true; // Fallthrough
12960 case ISD::SETUGE: SSECC = 5; break;
12961 case ISD::SETULT: Swap = true; // Fallthrough
12962 case ISD::SETUGT: SSECC = 6; break;
12963 case ISD::SETO: SSECC = 7; break;
12965 case ISD::SETONE: SSECC = 8; break;
12968 std::swap(Op0, Op1);
12973 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12974 // ones, and then concatenate the result back.
12975 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12976 MVT VT = Op.getSimpleValueType();
12978 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12979 "Unsupported value type for operation");
12981 unsigned NumElems = VT.getVectorNumElements();
12983 SDValue CC = Op.getOperand(2);
12985 // Extract the LHS vectors
12986 SDValue LHS = Op.getOperand(0);
12987 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12988 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12990 // Extract the RHS vectors
12991 SDValue RHS = Op.getOperand(1);
12992 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12993 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12995 // Issue the operation on the smaller types and concatenate the result back
12996 MVT EltVT = VT.getVectorElementType();
12997 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12998 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12999 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13000 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13003 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13004 const X86Subtarget *Subtarget) {
13005 SDValue Op0 = Op.getOperand(0);
13006 SDValue Op1 = Op.getOperand(1);
13007 SDValue CC = Op.getOperand(2);
13008 MVT VT = Op.getSimpleValueType();
13011 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13012 Op.getValueType().getScalarType() == MVT::i1 &&
13013 "Cannot set masked compare for this operation");
13015 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13017 bool Unsigned = false;
13020 switch (SetCCOpcode) {
13021 default: llvm_unreachable("Unexpected SETCC condition");
13022 case ISD::SETNE: SSECC = 4; break;
13023 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13024 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13025 case ISD::SETLT: Swap = true; //fall-through
13026 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13027 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13028 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13029 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13030 case ISD::SETULE: Unsigned = true; //fall-through
13031 case ISD::SETLE: SSECC = 2; break;
13035 std::swap(Op0, Op1);
13037 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13038 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13039 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13040 DAG.getConstant(SSECC, MVT::i8));
13043 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13044 /// operand \p Op1. If non-trivial (for example because it's not constant)
13045 /// return an empty value.
13046 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13048 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13052 MVT VT = Op1.getSimpleValueType();
13053 MVT EVT = VT.getVectorElementType();
13054 unsigned n = VT.getVectorNumElements();
13055 SmallVector<SDValue, 8> ULTOp1;
13057 for (unsigned i = 0; i < n; ++i) {
13058 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13059 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13062 // Avoid underflow.
13063 APInt Val = Elt->getAPIntValue();
13067 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13070 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13073 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13074 SelectionDAG &DAG) {
13075 SDValue Op0 = Op.getOperand(0);
13076 SDValue Op1 = Op.getOperand(1);
13077 SDValue CC = Op.getOperand(2);
13078 MVT VT = Op.getSimpleValueType();
13079 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13080 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13085 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13086 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13089 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13090 unsigned Opc = X86ISD::CMPP;
13091 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13092 assert(VT.getVectorNumElements() <= 16);
13093 Opc = X86ISD::CMPM;
13095 // In the two special cases we can't handle, emit two comparisons.
13098 unsigned CombineOpc;
13099 if (SetCCOpcode == ISD::SETUEQ) {
13100 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13102 assert(SetCCOpcode == ISD::SETONE);
13103 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13106 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13107 DAG.getConstant(CC0, MVT::i8));
13108 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13109 DAG.getConstant(CC1, MVT::i8));
13110 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13112 // Handle all other FP comparisons here.
13113 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13114 DAG.getConstant(SSECC, MVT::i8));
13117 // Break 256-bit integer vector compare into smaller ones.
13118 if (VT.is256BitVector() && !Subtarget->hasInt256())
13119 return Lower256IntVSETCC(Op, DAG);
13121 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13122 EVT OpVT = Op1.getValueType();
13123 if (Subtarget->hasAVX512()) {
13124 if (Op1.getValueType().is512BitVector() ||
13125 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13126 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13127 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13129 // In AVX-512 architecture setcc returns mask with i1 elements,
13130 // But there is no compare instruction for i8 and i16 elements in KNL.
13131 // We are not talking about 512-bit operands in this case, these
13132 // types are illegal.
13134 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13135 OpVT.getVectorElementType().getSizeInBits() >= 8))
13136 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13137 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13140 // We are handling one of the integer comparisons here. Since SSE only has
13141 // GT and EQ comparisons for integer, swapping operands and multiple
13142 // operations may be required for some comparisons.
13144 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13145 bool Subus = false;
13147 switch (SetCCOpcode) {
13148 default: llvm_unreachable("Unexpected SETCC condition");
13149 case ISD::SETNE: Invert = true;
13150 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13151 case ISD::SETLT: Swap = true;
13152 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13153 case ISD::SETGE: Swap = true;
13154 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13155 Invert = true; break;
13156 case ISD::SETULT: Swap = true;
13157 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13158 FlipSigns = true; break;
13159 case ISD::SETUGE: Swap = true;
13160 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13161 FlipSigns = true; Invert = true; break;
13164 // Special case: Use min/max operations for SETULE/SETUGE
13165 MVT VET = VT.getVectorElementType();
13167 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13168 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13171 switch (SetCCOpcode) {
13173 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13174 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13177 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13180 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13181 if (!MinMax && hasSubus) {
13182 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13184 // t = psubus Op0, Op1
13185 // pcmpeq t, <0..0>
13186 switch (SetCCOpcode) {
13188 case ISD::SETULT: {
13189 // If the comparison is against a constant we can turn this into a
13190 // setule. With psubus, setule does not require a swap. This is
13191 // beneficial because the constant in the register is no longer
13192 // destructed as the destination so it can be hoisted out of a loop.
13193 // Only do this pre-AVX since vpcmp* is no longer destructive.
13194 if (Subtarget->hasAVX())
13196 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13197 if (ULEOp1.getNode()) {
13199 Subus = true; Invert = false; Swap = false;
13203 // Psubus is better than flip-sign because it requires no inversion.
13204 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13205 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13209 Opc = X86ISD::SUBUS;
13215 std::swap(Op0, Op1);
13217 // Check that the operation in question is available (most are plain SSE2,
13218 // but PCMPGTQ and PCMPEQQ have different requirements).
13219 if (VT == MVT::v2i64) {
13220 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13221 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13223 // First cast everything to the right type.
13224 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13225 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13227 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13228 // bits of the inputs before performing those operations. The lower
13229 // compare is always unsigned.
13232 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13234 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13235 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13236 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13237 Sign, Zero, Sign, Zero);
13239 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13240 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13242 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13243 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13244 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13246 // Create masks for only the low parts/high parts of the 64 bit integers.
13247 static const int MaskHi[] = { 1, 1, 3, 3 };
13248 static const int MaskLo[] = { 0, 0, 2, 2 };
13249 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13250 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13251 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13253 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13254 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13257 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13259 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13262 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13263 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13264 // pcmpeqd + pshufd + pand.
13265 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13267 // First cast everything to the right type.
13268 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13269 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13272 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13274 // Make sure the lower and upper halves are both all-ones.
13275 static const int Mask[] = { 1, 0, 3, 2 };
13276 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13277 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13280 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13282 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13286 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13287 // bits of the inputs before performing those operations.
13289 EVT EltVT = VT.getVectorElementType();
13290 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13291 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13292 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13295 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13297 // If the logical-not of the result is required, perform that now.
13299 Result = DAG.getNOT(dl, Result, VT);
13302 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13305 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13306 getZeroVector(VT, Subtarget, DAG, dl));
13311 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13313 MVT VT = Op.getSimpleValueType();
13315 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13317 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13318 && "SetCC type must be 8-bit or 1-bit integer");
13319 SDValue Op0 = Op.getOperand(0);
13320 SDValue Op1 = Op.getOperand(1);
13322 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13324 // Optimize to BT if possible.
13325 // Lower (X & (1 << N)) == 0 to BT(X, N).
13326 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13327 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13328 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13329 Op1.getOpcode() == ISD::Constant &&
13330 cast<ConstantSDNode>(Op1)->isNullValue() &&
13331 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13332 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13333 if (NewSetCC.getNode()) {
13335 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13340 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13342 if (Op1.getOpcode() == ISD::Constant &&
13343 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13344 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13345 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13347 // If the input is a setcc, then reuse the input setcc or use a new one with
13348 // the inverted condition.
13349 if (Op0.getOpcode() == X86ISD::SETCC) {
13350 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13351 bool Invert = (CC == ISD::SETNE) ^
13352 cast<ConstantSDNode>(Op1)->isNullValue();
13356 CCode = X86::GetOppositeBranchCondition(CCode);
13357 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13358 DAG.getConstant(CCode, MVT::i8),
13359 Op0.getOperand(1));
13361 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13365 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13366 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13367 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13369 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13370 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13373 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13374 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13375 if (X86CC == X86::COND_INVALID)
13378 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13379 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13380 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13381 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13383 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13387 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13388 static bool isX86LogicalCmp(SDValue Op) {
13389 unsigned Opc = Op.getNode()->getOpcode();
13390 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13391 Opc == X86ISD::SAHF)
13393 if (Op.getResNo() == 1 &&
13394 (Opc == X86ISD::ADD ||
13395 Opc == X86ISD::SUB ||
13396 Opc == X86ISD::ADC ||
13397 Opc == X86ISD::SBB ||
13398 Opc == X86ISD::SMUL ||
13399 Opc == X86ISD::UMUL ||
13400 Opc == X86ISD::INC ||
13401 Opc == X86ISD::DEC ||
13402 Opc == X86ISD::OR ||
13403 Opc == X86ISD::XOR ||
13404 Opc == X86ISD::AND))
13407 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13413 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13414 if (V.getOpcode() != ISD::TRUNCATE)
13417 SDValue VOp0 = V.getOperand(0);
13418 unsigned InBits = VOp0.getValueSizeInBits();
13419 unsigned Bits = V.getValueSizeInBits();
13420 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13423 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13424 bool addTest = true;
13425 SDValue Cond = Op.getOperand(0);
13426 SDValue Op1 = Op.getOperand(1);
13427 SDValue Op2 = Op.getOperand(2);
13429 EVT VT = Op1.getValueType();
13432 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13433 // are available or VBLENDV if AVX is available.
13434 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13435 if (Cond.getOpcode() == ISD::SETCC &&
13436 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13437 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13438 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13439 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13440 int SSECC = translateX86FSETCC(
13441 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13444 if (Subtarget->hasAVX512()) {
13445 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13446 DAG.getConstant(SSECC, MVT::i8));
13447 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13450 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13451 DAG.getConstant(SSECC, MVT::i8));
13453 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13454 // of 3 logic instructions for size savings and potentially speed.
13455 // Unfortunately, there is no scalar form of VBLENDV.
13457 // If either operand is a constant, don't try this. We can expect to
13458 // optimize away at least one of the logic instructions later in that
13459 // case, so that sequence would be faster than a variable blend.
13461 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13462 // uses XMM0 as the selection register. That may need just as many
13463 // instructions as the AND/ANDN/OR sequence due to register moves, so
13466 if (Subtarget->hasAVX() &&
13467 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13469 // Convert to vectors, do a VSELECT, and convert back to scalar.
13470 // All of the conversions should be optimized away.
13472 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13473 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13474 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13475 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13477 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13478 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13480 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13482 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13483 VSel, DAG.getIntPtrConstant(0));
13485 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13486 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13487 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13491 if (Cond.getOpcode() == ISD::SETCC) {
13492 SDValue NewCond = LowerSETCC(Cond, DAG);
13493 if (NewCond.getNode())
13497 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13498 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13499 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13500 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13501 if (Cond.getOpcode() == X86ISD::SETCC &&
13502 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13503 isZero(Cond.getOperand(1).getOperand(1))) {
13504 SDValue Cmp = Cond.getOperand(1);
13506 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13508 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13509 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13510 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13512 SDValue CmpOp0 = Cmp.getOperand(0);
13513 // Apply further optimizations for special cases
13514 // (select (x != 0), -1, 0) -> neg & sbb
13515 // (select (x == 0), 0, -1) -> neg & sbb
13516 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13517 if (YC->isNullValue() &&
13518 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13519 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13520 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13521 DAG.getConstant(0, CmpOp0.getValueType()),
13523 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13524 DAG.getConstant(X86::COND_B, MVT::i8),
13525 SDValue(Neg.getNode(), 1));
13529 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13530 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13531 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13533 SDValue Res = // Res = 0 or -1.
13534 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13535 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13537 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13538 Res = DAG.getNOT(DL, Res, Res.getValueType());
13540 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13541 if (!N2C || !N2C->isNullValue())
13542 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13547 // Look past (and (setcc_carry (cmp ...)), 1).
13548 if (Cond.getOpcode() == ISD::AND &&
13549 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13550 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13551 if (C && C->getAPIntValue() == 1)
13552 Cond = Cond.getOperand(0);
13555 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13556 // setting operand in place of the X86ISD::SETCC.
13557 unsigned CondOpcode = Cond.getOpcode();
13558 if (CondOpcode == X86ISD::SETCC ||
13559 CondOpcode == X86ISD::SETCC_CARRY) {
13560 CC = Cond.getOperand(0);
13562 SDValue Cmp = Cond.getOperand(1);
13563 unsigned Opc = Cmp.getOpcode();
13564 MVT VT = Op.getSimpleValueType();
13566 bool IllegalFPCMov = false;
13567 if (VT.isFloatingPoint() && !VT.isVector() &&
13568 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13569 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13571 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13572 Opc == X86ISD::BT) { // FIXME
13576 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13577 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13578 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13579 Cond.getOperand(0).getValueType() != MVT::i8)) {
13580 SDValue LHS = Cond.getOperand(0);
13581 SDValue RHS = Cond.getOperand(1);
13582 unsigned X86Opcode;
13585 switch (CondOpcode) {
13586 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13587 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13588 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13589 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13590 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13591 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13592 default: llvm_unreachable("unexpected overflowing operator");
13594 if (CondOpcode == ISD::UMULO)
13595 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13598 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13600 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13602 if (CondOpcode == ISD::UMULO)
13603 Cond = X86Op.getValue(2);
13605 Cond = X86Op.getValue(1);
13607 CC = DAG.getConstant(X86Cond, MVT::i8);
13612 // Look pass the truncate if the high bits are known zero.
13613 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13614 Cond = Cond.getOperand(0);
13616 // We know the result of AND is compared against zero. Try to match
13618 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13619 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13620 if (NewSetCC.getNode()) {
13621 CC = NewSetCC.getOperand(0);
13622 Cond = NewSetCC.getOperand(1);
13629 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13630 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13633 // a < b ? -1 : 0 -> RES = ~setcc_carry
13634 // a < b ? 0 : -1 -> RES = setcc_carry
13635 // a >= b ? -1 : 0 -> RES = setcc_carry
13636 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13637 if (Cond.getOpcode() == X86ISD::SUB) {
13638 Cond = ConvertCmpIfNecessary(Cond, DAG);
13639 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13641 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13642 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13643 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13644 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13645 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13646 return DAG.getNOT(DL, Res, Res.getValueType());
13651 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13652 // widen the cmov and push the truncate through. This avoids introducing a new
13653 // branch during isel and doesn't add any extensions.
13654 if (Op.getValueType() == MVT::i8 &&
13655 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13656 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13657 if (T1.getValueType() == T2.getValueType() &&
13658 // Blacklist CopyFromReg to avoid partial register stalls.
13659 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13660 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13661 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13662 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13666 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13667 // condition is true.
13668 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13669 SDValue Ops[] = { Op2, Op1, CC, Cond };
13670 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13673 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
13674 SelectionDAG &DAG) {
13675 MVT VT = Op->getSimpleValueType(0);
13676 SDValue In = Op->getOperand(0);
13677 MVT InVT = In.getSimpleValueType();
13678 MVT VTElt = VT.getVectorElementType();
13679 MVT InVTElt = InVT.getVectorElementType();
13683 if ((InVTElt == MVT::i1) &&
13684 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13685 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13687 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13688 VTElt.getSizeInBits() <= 16)) ||
13690 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13691 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13693 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13694 VTElt.getSizeInBits() >= 32))))
13695 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13697 unsigned int NumElts = VT.getVectorNumElements();
13699 if (NumElts != 8 && NumElts != 16)
13702 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13703 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13704 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13705 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13708 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13709 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13711 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13712 Constant *C = ConstantInt::get(*DAG.getContext(),
13713 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13715 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13716 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13717 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13718 MachinePointerInfo::getConstantPool(),
13719 false, false, false, Alignment);
13720 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13721 if (VT.is512BitVector())
13723 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13726 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13727 SelectionDAG &DAG) {
13728 MVT VT = Op->getSimpleValueType(0);
13729 SDValue In = Op->getOperand(0);
13730 MVT InVT = In.getSimpleValueType();
13733 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13734 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
13736 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13737 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13738 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13741 if (Subtarget->hasInt256())
13742 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13744 // Optimize vectors in AVX mode
13745 // Sign extend v8i16 to v8i32 and
13748 // Divide input vector into two parts
13749 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13750 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13751 // concat the vectors to original VT
13753 unsigned NumElems = InVT.getVectorNumElements();
13754 SDValue Undef = DAG.getUNDEF(InVT);
13756 SmallVector<int,8> ShufMask1(NumElems, -1);
13757 for (unsigned i = 0; i != NumElems/2; ++i)
13760 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13762 SmallVector<int,8> ShufMask2(NumElems, -1);
13763 for (unsigned i = 0; i != NumElems/2; ++i)
13764 ShufMask2[i] = i + NumElems/2;
13766 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13768 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13769 VT.getVectorNumElements()/2);
13771 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13772 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13774 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13777 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13778 // may emit an illegal shuffle but the expansion is still better than scalar
13779 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13780 // we'll emit a shuffle and a arithmetic shift.
13781 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
13782 // TODO: It is possible to support ZExt by zeroing the undef values during
13783 // the shuffle phase or after the shuffle.
13784 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13785 SelectionDAG &DAG) {
13786 MVT RegVT = Op.getSimpleValueType();
13787 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13788 assert(RegVT.isInteger() &&
13789 "We only custom lower integer vector sext loads.");
13791 // Nothing useful we can do without SSE2 shuffles.
13792 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13794 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13796 EVT MemVT = Ld->getMemoryVT();
13797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13798 unsigned RegSz = RegVT.getSizeInBits();
13800 ISD::LoadExtType Ext = Ld->getExtensionType();
13802 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13803 && "Only anyext and sext are currently implemented.");
13804 assert(MemVT != RegVT && "Cannot extend to the same type");
13805 assert(MemVT.isVector() && "Must load a vector from memory");
13807 unsigned NumElems = RegVT.getVectorNumElements();
13808 unsigned MemSz = MemVT.getSizeInBits();
13809 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13811 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13812 // The only way in which we have a legal 256-bit vector result but not the
13813 // integer 256-bit operations needed to directly lower a sextload is if we
13814 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13815 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13816 // correctly legalized. We do this late to allow the canonical form of
13817 // sextload to persist throughout the rest of the DAG combiner -- it wants
13818 // to fold together any extensions it can, and so will fuse a sign_extend
13819 // of an sextload into a sextload targeting a wider value.
13821 if (MemSz == 128) {
13822 // Just switch this to a normal load.
13823 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13824 "it must be a legal 128-bit vector "
13826 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13827 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13828 Ld->isInvariant(), Ld->getAlignment());
13830 assert(MemSz < 128 &&
13831 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13832 // Do an sext load to a 128-bit vector type. We want to use the same
13833 // number of elements, but elements half as wide. This will end up being
13834 // recursively lowered by this routine, but will succeed as we definitely
13835 // have all the necessary features if we're using AVX1.
13837 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13838 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13840 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13841 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13842 Ld->isNonTemporal(), Ld->isInvariant(),
13843 Ld->getAlignment());
13846 // Replace chain users with the new chain.
13847 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13848 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13850 // Finally, do a normal sign-extend to the desired register.
13851 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13854 // All sizes must be a power of two.
13855 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13856 "Non-power-of-two elements are not custom lowered!");
13858 // Attempt to load the original value using scalar loads.
13859 // Find the largest scalar type that divides the total loaded size.
13860 MVT SclrLoadTy = MVT::i8;
13861 for (MVT Tp : MVT::integer_valuetypes()) {
13862 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13867 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13868 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13870 SclrLoadTy = MVT::f64;
13872 // Calculate the number of scalar loads that we need to perform
13873 // in order to load our vector from memory.
13874 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13876 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13877 "Can only lower sext loads with a single scalar load!");
13879 unsigned loadRegZize = RegSz;
13880 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13883 // Represent our vector as a sequence of elements which are the
13884 // largest scalar that we can load.
13885 EVT LoadUnitVecVT = EVT::getVectorVT(
13886 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13888 // Represent the data using the same element type that is stored in
13889 // memory. In practice, we ''widen'' MemVT.
13891 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13892 loadRegZize / MemVT.getScalarType().getSizeInBits());
13894 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13895 "Invalid vector type");
13897 // We can't shuffle using an illegal type.
13898 assert(TLI.isTypeLegal(WideVecVT) &&
13899 "We only lower types that form legal widened vector types");
13901 SmallVector<SDValue, 8> Chains;
13902 SDValue Ptr = Ld->getBasePtr();
13903 SDValue Increment =
13904 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13905 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13907 for (unsigned i = 0; i < NumLoads; ++i) {
13908 // Perform a single load.
13909 SDValue ScalarLoad =
13910 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13911 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13912 Ld->getAlignment());
13913 Chains.push_back(ScalarLoad.getValue(1));
13914 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13915 // another round of DAGCombining.
13917 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13919 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13920 ScalarLoad, DAG.getIntPtrConstant(i));
13922 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13925 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13927 // Bitcast the loaded value to a vector of the original element type, in
13928 // the size of the target vector type.
13929 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13930 unsigned SizeRatio = RegSz / MemSz;
13932 if (Ext == ISD::SEXTLOAD) {
13933 // If we have SSE4.1, we can directly emit a VSEXT node.
13934 if (Subtarget->hasSSE41()) {
13935 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13936 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13940 // Otherwise we'll shuffle the small elements in the high bits of the
13941 // larger type and perform an arithmetic shift. If the shift is not legal
13942 // it's better to scalarize.
13943 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13944 "We can't implement a sext load without an arithmetic right shift!");
13946 // Redistribute the loaded elements into the different locations.
13947 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13948 for (unsigned i = 0; i != NumElems; ++i)
13949 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13951 SDValue Shuff = DAG.getVectorShuffle(
13952 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13954 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13956 // Build the arithmetic shift.
13957 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13958 MemVT.getVectorElementType().getSizeInBits();
13960 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13962 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13966 // Redistribute the loaded elements into the different locations.
13967 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13968 for (unsigned i = 0; i != NumElems; ++i)
13969 ShuffleVec[i * SizeRatio] = i;
13971 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13972 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13974 // Bitcast to the requested type.
13975 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13976 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13980 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13981 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13982 // from the AND / OR.
13983 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13984 Opc = Op.getOpcode();
13985 if (Opc != ISD::OR && Opc != ISD::AND)
13987 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13988 Op.getOperand(0).hasOneUse() &&
13989 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13990 Op.getOperand(1).hasOneUse());
13993 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13994 // 1 and that the SETCC node has a single use.
13995 static bool isXor1OfSetCC(SDValue Op) {
13996 if (Op.getOpcode() != ISD::XOR)
13998 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13999 if (N1C && N1C->getAPIntValue() == 1) {
14000 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14001 Op.getOperand(0).hasOneUse();
14006 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14007 bool addTest = true;
14008 SDValue Chain = Op.getOperand(0);
14009 SDValue Cond = Op.getOperand(1);
14010 SDValue Dest = Op.getOperand(2);
14013 bool Inverted = false;
14015 if (Cond.getOpcode() == ISD::SETCC) {
14016 // Check for setcc([su]{add,sub,mul}o == 0).
14017 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14018 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14019 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14020 Cond.getOperand(0).getResNo() == 1 &&
14021 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14022 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14023 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14024 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14025 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14026 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14028 Cond = Cond.getOperand(0);
14030 SDValue NewCond = LowerSETCC(Cond, DAG);
14031 if (NewCond.getNode())
14036 // FIXME: LowerXALUO doesn't handle these!!
14037 else if (Cond.getOpcode() == X86ISD::ADD ||
14038 Cond.getOpcode() == X86ISD::SUB ||
14039 Cond.getOpcode() == X86ISD::SMUL ||
14040 Cond.getOpcode() == X86ISD::UMUL)
14041 Cond = LowerXALUO(Cond, DAG);
14044 // Look pass (and (setcc_carry (cmp ...)), 1).
14045 if (Cond.getOpcode() == ISD::AND &&
14046 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14047 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14048 if (C && C->getAPIntValue() == 1)
14049 Cond = Cond.getOperand(0);
14052 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14053 // setting operand in place of the X86ISD::SETCC.
14054 unsigned CondOpcode = Cond.getOpcode();
14055 if (CondOpcode == X86ISD::SETCC ||
14056 CondOpcode == X86ISD::SETCC_CARRY) {
14057 CC = Cond.getOperand(0);
14059 SDValue Cmp = Cond.getOperand(1);
14060 unsigned Opc = Cmp.getOpcode();
14061 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14062 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14066 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14070 // These can only come from an arithmetic instruction with overflow,
14071 // e.g. SADDO, UADDO.
14072 Cond = Cond.getNode()->getOperand(1);
14078 CondOpcode = Cond.getOpcode();
14079 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14080 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14081 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14082 Cond.getOperand(0).getValueType() != MVT::i8)) {
14083 SDValue LHS = Cond.getOperand(0);
14084 SDValue RHS = Cond.getOperand(1);
14085 unsigned X86Opcode;
14088 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14089 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14091 switch (CondOpcode) {
14092 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14094 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14096 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14099 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14100 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14102 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14104 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14107 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14108 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14109 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14110 default: llvm_unreachable("unexpected overflowing operator");
14113 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14114 if (CondOpcode == ISD::UMULO)
14115 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14118 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14120 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14122 if (CondOpcode == ISD::UMULO)
14123 Cond = X86Op.getValue(2);
14125 Cond = X86Op.getValue(1);
14127 CC = DAG.getConstant(X86Cond, MVT::i8);
14131 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14132 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14133 if (CondOpc == ISD::OR) {
14134 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14135 // two branches instead of an explicit OR instruction with a
14137 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14138 isX86LogicalCmp(Cmp)) {
14139 CC = Cond.getOperand(0).getOperand(0);
14140 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14141 Chain, Dest, CC, Cmp);
14142 CC = Cond.getOperand(1).getOperand(0);
14146 } else { // ISD::AND
14147 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14148 // two branches instead of an explicit AND instruction with a
14149 // separate test. However, we only do this if this block doesn't
14150 // have a fall-through edge, because this requires an explicit
14151 // jmp when the condition is false.
14152 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14153 isX86LogicalCmp(Cmp) &&
14154 Op.getNode()->hasOneUse()) {
14155 X86::CondCode CCode =
14156 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14157 CCode = X86::GetOppositeBranchCondition(CCode);
14158 CC = DAG.getConstant(CCode, MVT::i8);
14159 SDNode *User = *Op.getNode()->use_begin();
14160 // Look for an unconditional branch following this conditional branch.
14161 // We need this because we need to reverse the successors in order
14162 // to implement FCMP_OEQ.
14163 if (User->getOpcode() == ISD::BR) {
14164 SDValue FalseBB = User->getOperand(1);
14166 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14167 assert(NewBR == User);
14171 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14172 Chain, Dest, CC, Cmp);
14173 X86::CondCode CCode =
14174 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14175 CCode = X86::GetOppositeBranchCondition(CCode);
14176 CC = DAG.getConstant(CCode, MVT::i8);
14182 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14183 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14184 // It should be transformed during dag combiner except when the condition
14185 // is set by a arithmetics with overflow node.
14186 X86::CondCode CCode =
14187 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14188 CCode = X86::GetOppositeBranchCondition(CCode);
14189 CC = DAG.getConstant(CCode, MVT::i8);
14190 Cond = Cond.getOperand(0).getOperand(1);
14192 } else if (Cond.getOpcode() == ISD::SETCC &&
14193 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14194 // For FCMP_OEQ, we can emit
14195 // two branches instead of an explicit AND instruction with a
14196 // separate test. However, we only do this if this block doesn't
14197 // have a fall-through edge, because this requires an explicit
14198 // jmp when the condition is false.
14199 if (Op.getNode()->hasOneUse()) {
14200 SDNode *User = *Op.getNode()->use_begin();
14201 // Look for an unconditional branch following this conditional branch.
14202 // We need this because we need to reverse the successors in order
14203 // to implement FCMP_OEQ.
14204 if (User->getOpcode() == ISD::BR) {
14205 SDValue FalseBB = User->getOperand(1);
14207 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14208 assert(NewBR == User);
14212 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14213 Cond.getOperand(0), Cond.getOperand(1));
14214 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14215 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14216 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14217 Chain, Dest, CC, Cmp);
14218 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14223 } else if (Cond.getOpcode() == ISD::SETCC &&
14224 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14225 // For FCMP_UNE, we can emit
14226 // two branches instead of an explicit AND instruction with a
14227 // separate test. However, we only do this if this block doesn't
14228 // have a fall-through edge, because this requires an explicit
14229 // jmp when the condition is false.
14230 if (Op.getNode()->hasOneUse()) {
14231 SDNode *User = *Op.getNode()->use_begin();
14232 // Look for an unconditional branch following this conditional branch.
14233 // We need this because we need to reverse the successors in order
14234 // to implement FCMP_UNE.
14235 if (User->getOpcode() == ISD::BR) {
14236 SDValue FalseBB = User->getOperand(1);
14238 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14239 assert(NewBR == User);
14242 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14243 Cond.getOperand(0), Cond.getOperand(1));
14244 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14245 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14246 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14247 Chain, Dest, CC, Cmp);
14248 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14258 // Look pass the truncate if the high bits are known zero.
14259 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14260 Cond = Cond.getOperand(0);
14262 // We know the result of AND is compared against zero. Try to match
14264 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14265 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14266 if (NewSetCC.getNode()) {
14267 CC = NewSetCC.getOperand(0);
14268 Cond = NewSetCC.getOperand(1);
14275 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14276 CC = DAG.getConstant(X86Cond, MVT::i8);
14277 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14279 Cond = ConvertCmpIfNecessary(Cond, DAG);
14280 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14281 Chain, Dest, CC, Cond);
14284 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14285 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14286 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14287 // that the guard pages used by the OS virtual memory manager are allocated in
14288 // correct sequence.
14290 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14291 SelectionDAG &DAG) const {
14292 MachineFunction &MF = DAG.getMachineFunction();
14293 bool SplitStack = MF.shouldSplitStack();
14294 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14299 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14300 SDNode* Node = Op.getNode();
14302 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14303 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14304 " not tell us which reg is the stack pointer!");
14305 EVT VT = Node->getValueType(0);
14306 SDValue Tmp1 = SDValue(Node, 0);
14307 SDValue Tmp2 = SDValue(Node, 1);
14308 SDValue Tmp3 = Node->getOperand(2);
14309 SDValue Chain = Tmp1.getOperand(0);
14311 // Chain the dynamic stack allocation so that it doesn't modify the stack
14312 // pointer when other instructions are using the stack.
14313 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14316 SDValue Size = Tmp2.getOperand(1);
14317 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14318 Chain = SP.getValue(1);
14319 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14320 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14321 unsigned StackAlign = TFI.getStackAlignment();
14322 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14323 if (Align > StackAlign)
14324 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14325 DAG.getConstant(-(uint64_t)Align, VT));
14326 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14328 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14329 DAG.getIntPtrConstant(0, true), SDValue(),
14332 SDValue Ops[2] = { Tmp1, Tmp2 };
14333 return DAG.getMergeValues(Ops, dl);
14337 SDValue Chain = Op.getOperand(0);
14338 SDValue Size = Op.getOperand(1);
14339 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14340 EVT VT = Op.getNode()->getValueType(0);
14342 bool Is64Bit = Subtarget->is64Bit();
14343 EVT SPTy = getPointerTy();
14346 MachineRegisterInfo &MRI = MF.getRegInfo();
14349 // The 64 bit implementation of segmented stacks needs to clobber both r10
14350 // r11. This makes it impossible to use it along with nested parameters.
14351 const Function *F = MF.getFunction();
14353 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14355 if (I->hasNestAttr())
14356 report_fatal_error("Cannot use segmented stacks with functions that "
14357 "have nested arguments.");
14360 const TargetRegisterClass *AddrRegClass =
14361 getRegClassFor(getPointerTy());
14362 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14363 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14364 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14365 DAG.getRegister(Vreg, SPTy));
14366 SDValue Ops1[2] = { Value, Chain };
14367 return DAG.getMergeValues(Ops1, dl);
14370 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14372 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14373 Flag = Chain.getValue(1);
14374 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14376 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14378 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14379 unsigned SPReg = RegInfo->getStackRegister();
14380 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14381 Chain = SP.getValue(1);
14384 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14385 DAG.getConstant(-(uint64_t)Align, VT));
14386 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14389 SDValue Ops1[2] = { SP, Chain };
14390 return DAG.getMergeValues(Ops1, dl);
14394 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14395 MachineFunction &MF = DAG.getMachineFunction();
14396 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14398 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14401 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14402 // vastart just stores the address of the VarArgsFrameIndex slot into the
14403 // memory location argument.
14404 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14406 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14407 MachinePointerInfo(SV), false, false, 0);
14411 // gp_offset (0 - 6 * 8)
14412 // fp_offset (48 - 48 + 8 * 16)
14413 // overflow_arg_area (point to parameters coming in memory).
14415 SmallVector<SDValue, 8> MemOps;
14416 SDValue FIN = Op.getOperand(1);
14418 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14419 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14421 FIN, MachinePointerInfo(SV), false, false, 0);
14422 MemOps.push_back(Store);
14425 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14426 FIN, DAG.getIntPtrConstant(4));
14427 Store = DAG.getStore(Op.getOperand(0), DL,
14428 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14430 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14431 MemOps.push_back(Store);
14433 // Store ptr to overflow_arg_area
14434 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14435 FIN, DAG.getIntPtrConstant(4));
14436 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14438 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14439 MachinePointerInfo(SV, 8),
14441 MemOps.push_back(Store);
14443 // Store ptr to reg_save_area.
14444 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14445 FIN, DAG.getIntPtrConstant(8));
14446 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14448 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14449 MachinePointerInfo(SV, 16), false, false, 0);
14450 MemOps.push_back(Store);
14451 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14454 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14455 assert(Subtarget->is64Bit() &&
14456 "LowerVAARG only handles 64-bit va_arg!");
14457 assert((Subtarget->isTargetLinux() ||
14458 Subtarget->isTargetDarwin()) &&
14459 "Unhandled target in LowerVAARG");
14460 assert(Op.getNode()->getNumOperands() == 4);
14461 SDValue Chain = Op.getOperand(0);
14462 SDValue SrcPtr = Op.getOperand(1);
14463 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14464 unsigned Align = Op.getConstantOperandVal(3);
14467 EVT ArgVT = Op.getNode()->getValueType(0);
14468 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14469 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14472 // Decide which area this value should be read from.
14473 // TODO: Implement the AMD64 ABI in its entirety. This simple
14474 // selection mechanism works only for the basic types.
14475 if (ArgVT == MVT::f80) {
14476 llvm_unreachable("va_arg for f80 not yet implemented");
14477 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14478 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14479 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14480 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14482 llvm_unreachable("Unhandled argument type in LowerVAARG");
14485 if (ArgMode == 2) {
14486 // Sanity Check: Make sure using fp_offset makes sense.
14487 assert(!DAG.getTarget().Options.UseSoftFloat &&
14488 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14489 Attribute::NoImplicitFloat)) &&
14490 Subtarget->hasSSE1());
14493 // Insert VAARG_64 node into the DAG
14494 // VAARG_64 returns two values: Variable Argument Address, Chain
14495 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, MVT::i32),
14496 DAG.getConstant(ArgMode, MVT::i8),
14497 DAG.getConstant(Align, MVT::i32)};
14498 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14499 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14500 VTs, InstOps, MVT::i64,
14501 MachinePointerInfo(SV),
14503 /*Volatile=*/false,
14505 /*WriteMem=*/true);
14506 Chain = VAARG.getValue(1);
14508 // Load the next argument and return it
14509 return DAG.getLoad(ArgVT, dl,
14512 MachinePointerInfo(),
14513 false, false, false, 0);
14516 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14517 SelectionDAG &DAG) {
14518 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14519 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14520 SDValue Chain = Op.getOperand(0);
14521 SDValue DstPtr = Op.getOperand(1);
14522 SDValue SrcPtr = Op.getOperand(2);
14523 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14524 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14527 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14528 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14530 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14533 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14534 // amount is a constant. Takes immediate version of shift as input.
14535 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14536 SDValue SrcOp, uint64_t ShiftAmt,
14537 SelectionDAG &DAG) {
14538 MVT ElementType = VT.getVectorElementType();
14540 // Fold this packed shift into its first operand if ShiftAmt is 0.
14544 // Check for ShiftAmt >= element width
14545 if (ShiftAmt >= ElementType.getSizeInBits()) {
14546 if (Opc == X86ISD::VSRAI)
14547 ShiftAmt = ElementType.getSizeInBits() - 1;
14549 return DAG.getConstant(0, VT);
14552 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14553 && "Unknown target vector shift-by-constant node");
14555 // Fold this packed vector shift into a build vector if SrcOp is a
14556 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14557 if (VT == SrcOp.getSimpleValueType() &&
14558 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14559 SmallVector<SDValue, 8> Elts;
14560 unsigned NumElts = SrcOp->getNumOperands();
14561 ConstantSDNode *ND;
14564 default: llvm_unreachable(nullptr);
14565 case X86ISD::VSHLI:
14566 for (unsigned i=0; i!=NumElts; ++i) {
14567 SDValue CurrentOp = SrcOp->getOperand(i);
14568 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14569 Elts.push_back(CurrentOp);
14572 ND = cast<ConstantSDNode>(CurrentOp);
14573 const APInt &C = ND->getAPIntValue();
14574 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14577 case X86ISD::VSRLI:
14578 for (unsigned i=0; i!=NumElts; ++i) {
14579 SDValue CurrentOp = SrcOp->getOperand(i);
14580 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14581 Elts.push_back(CurrentOp);
14584 ND = cast<ConstantSDNode>(CurrentOp);
14585 const APInt &C = ND->getAPIntValue();
14586 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14589 case X86ISD::VSRAI:
14590 for (unsigned i=0; i!=NumElts; ++i) {
14591 SDValue CurrentOp = SrcOp->getOperand(i);
14592 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14593 Elts.push_back(CurrentOp);
14596 ND = cast<ConstantSDNode>(CurrentOp);
14597 const APInt &C = ND->getAPIntValue();
14598 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14603 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14606 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14609 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14610 // may or may not be a constant. Takes immediate version of shift as input.
14611 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14612 SDValue SrcOp, SDValue ShAmt,
14613 SelectionDAG &DAG) {
14614 MVT SVT = ShAmt.getSimpleValueType();
14615 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14617 // Catch shift-by-constant.
14618 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14619 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14620 CShAmt->getZExtValue(), DAG);
14622 // Change opcode to non-immediate version
14624 default: llvm_unreachable("Unknown target vector shift node");
14625 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14626 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14627 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14630 const X86Subtarget &Subtarget =
14631 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14632 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14633 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14634 // Let the shuffle legalizer expand this shift amount node.
14635 SDValue Op0 = ShAmt.getOperand(0);
14636 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14637 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14639 // Need to build a vector containing shift amount.
14640 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14641 SmallVector<SDValue, 4> ShOps;
14642 ShOps.push_back(ShAmt);
14643 if (SVT == MVT::i32) {
14644 ShOps.push_back(DAG.getConstant(0, SVT));
14645 ShOps.push_back(DAG.getUNDEF(SVT));
14647 ShOps.push_back(DAG.getUNDEF(SVT));
14649 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14650 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14653 // The return type has to be a 128-bit type with the same element
14654 // type as the input type.
14655 MVT EltVT = VT.getVectorElementType();
14656 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14658 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14659 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14662 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14663 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14664 /// necessary casting for \p Mask when lowering masking intrinsics.
14665 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14666 SDValue PreservedSrc,
14667 const X86Subtarget *Subtarget,
14668 SelectionDAG &DAG) {
14669 EVT VT = Op.getValueType();
14670 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14671 MVT::i1, VT.getVectorNumElements());
14672 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14673 Mask.getValueType().getSizeInBits());
14676 assert(MaskVT.isSimple() && "invalid mask type");
14678 if (isAllOnes(Mask))
14681 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14682 // are extracted by EXTRACT_SUBVECTOR.
14683 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14684 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14685 DAG.getIntPtrConstant(0));
14687 switch (Op.getOpcode()) {
14689 case X86ISD::PCMPEQM:
14690 case X86ISD::PCMPGTM:
14692 case X86ISD::CMPMU:
14693 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14695 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14696 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14697 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14700 /// \brief Creates an SDNode for a predicated scalar operation.
14701 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14702 /// The mask is comming as MVT::i8 and it should be truncated
14703 /// to MVT::i1 while lowering masking intrinsics.
14704 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14705 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14706 /// a scalar instruction.
14707 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14708 SDValue PreservedSrc,
14709 const X86Subtarget *Subtarget,
14710 SelectionDAG &DAG) {
14711 if (isAllOnes(Mask))
14714 EVT VT = Op.getValueType();
14716 // The mask should be of type MVT::i1
14717 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14719 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14720 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14721 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14724 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14725 SelectionDAG &DAG) {
14727 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14728 EVT VT = Op.getValueType();
14729 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14731 switch(IntrData->Type) {
14732 case INTR_TYPE_1OP:
14733 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14734 case INTR_TYPE_2OP:
14735 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14737 case INTR_TYPE_3OP:
14738 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14739 Op.getOperand(2), Op.getOperand(3));
14740 case INTR_TYPE_1OP_MASK_RM: {
14741 SDValue Src = Op.getOperand(1);
14742 SDValue Src0 = Op.getOperand(2);
14743 SDValue Mask = Op.getOperand(3);
14744 SDValue RoundingMode = Op.getOperand(4);
14745 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
14747 Mask, Src0, Subtarget, DAG);
14749 case INTR_TYPE_SCALAR_MASK_RM: {
14750 SDValue Src1 = Op.getOperand(1);
14751 SDValue Src2 = Op.getOperand(2);
14752 SDValue Src0 = Op.getOperand(3);
14753 SDValue Mask = Op.getOperand(4);
14754 // There are 2 kinds of intrinsics in this group:
14755 // (1) With supress-all-exceptions (sae) - 6 operands
14756 // (2) With rounding mode and sae - 7 operands.
14757 if (Op.getNumOperands() == 6) {
14758 SDValue Sae = Op.getOperand(5);
14759 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14761 Mask, Src0, Subtarget, DAG);
14763 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
14764 SDValue RoundingMode = Op.getOperand(5);
14765 SDValue Sae = Op.getOperand(6);
14766 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14767 RoundingMode, Sae),
14768 Mask, Src0, Subtarget, DAG);
14770 case INTR_TYPE_2OP_MASK: {
14771 SDValue Src1 = Op.getOperand(1);
14772 SDValue Src2 = Op.getOperand(2);
14773 SDValue PassThru = Op.getOperand(3);
14774 SDValue Mask = Op.getOperand(4);
14775 // We specify 2 possible opcodes for intrinsics with rounding modes.
14776 // First, we check if the intrinsic may have non-default rounding mode,
14777 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14778 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14779 if (IntrWithRoundingModeOpcode != 0) {
14780 SDValue Rnd = Op.getOperand(5);
14781 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
14782 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
14783 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14784 dl, Op.getValueType(),
14786 Mask, PassThru, Subtarget, DAG);
14789 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
14791 Mask, PassThru, Subtarget, DAG);
14793 case FMA_OP_MASK: {
14794 SDValue Src1 = Op.getOperand(1);
14795 SDValue Src2 = Op.getOperand(2);
14796 SDValue Src3 = Op.getOperand(3);
14797 SDValue Mask = Op.getOperand(4);
14798 // We specify 2 possible opcodes for intrinsics with rounding modes.
14799 // First, we check if the intrinsic may have non-default rounding mode,
14800 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14801 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14802 if (IntrWithRoundingModeOpcode != 0) {
14803 SDValue Rnd = Op.getOperand(5);
14804 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14805 X86::STATIC_ROUNDING::CUR_DIRECTION)
14806 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14807 dl, Op.getValueType(),
14808 Src1, Src2, Src3, Rnd),
14809 Mask, Src1, Subtarget, DAG);
14811 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
14812 dl, Op.getValueType(),
14814 Mask, Src1, Subtarget, DAG);
14817 case CMP_MASK_CC: {
14818 // Comparison intrinsics with masks.
14819 // Example of transformation:
14820 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
14821 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
14823 // (v8i1 (insert_subvector undef,
14824 // (v2i1 (and (PCMPEQM %a, %b),
14825 // (extract_subvector
14826 // (v8i1 (bitcast %mask)), 0))), 0))))
14827 EVT VT = Op.getOperand(1).getValueType();
14828 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14829 VT.getVectorNumElements());
14830 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
14831 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14832 Mask.getValueType().getSizeInBits());
14834 if (IntrData->Type == CMP_MASK_CC) {
14835 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14836 Op.getOperand(2), Op.getOperand(3));
14838 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
14839 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14842 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
14843 DAG.getTargetConstant(0, MaskVT),
14845 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
14846 DAG.getUNDEF(BitcastVT), CmpMask,
14847 DAG.getIntPtrConstant(0));
14848 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
14850 case COMI: { // Comparison intrinsics
14851 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
14852 SDValue LHS = Op.getOperand(1);
14853 SDValue RHS = Op.getOperand(2);
14854 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14855 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14856 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
14857 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14858 DAG.getConstant(X86CC, MVT::i8), Cond);
14859 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14862 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
14863 Op.getOperand(1), Op.getOperand(2), DAG);
14865 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
14866 Op.getSimpleValueType(),
14868 Op.getOperand(2), DAG),
14869 Op.getOperand(4), Op.getOperand(3), Subtarget,
14871 case COMPRESS_EXPAND_IN_REG: {
14872 SDValue Mask = Op.getOperand(3);
14873 SDValue DataToCompress = Op.getOperand(1);
14874 SDValue PassThru = Op.getOperand(2);
14875 if (isAllOnes(Mask)) // return data as is
14876 return Op.getOperand(1);
14877 EVT VT = Op.getValueType();
14878 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14879 VT.getVectorNumElements());
14880 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14881 Mask.getValueType().getSizeInBits());
14883 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14884 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14885 DAG.getIntPtrConstant(0));
14887 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
14891 SDValue Mask = Op.getOperand(3);
14892 EVT VT = Op.getValueType();
14893 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14894 VT.getVectorNumElements());
14895 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14896 Mask.getValueType().getSizeInBits());
14898 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14899 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14900 DAG.getIntPtrConstant(0));
14901 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
14910 default: return SDValue(); // Don't custom lower most intrinsics.
14912 case Intrinsic::x86_avx2_permd:
14913 case Intrinsic::x86_avx2_permps:
14914 // Operands intentionally swapped. Mask is last operand to intrinsic,
14915 // but second operand for node/instruction.
14916 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14917 Op.getOperand(2), Op.getOperand(1));
14919 case Intrinsic::x86_avx512_mask_valign_q_512:
14920 case Intrinsic::x86_avx512_mask_valign_d_512:
14921 // Vector source operands are swapped.
14922 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14923 Op.getValueType(), Op.getOperand(2),
14926 Op.getOperand(5), Op.getOperand(4),
14929 // ptest and testp intrinsics. The intrinsic these come from are designed to
14930 // return an integer value, not just an instruction so lower it to the ptest
14931 // or testp pattern and a setcc for the result.
14932 case Intrinsic::x86_sse41_ptestz:
14933 case Intrinsic::x86_sse41_ptestc:
14934 case Intrinsic::x86_sse41_ptestnzc:
14935 case Intrinsic::x86_avx_ptestz_256:
14936 case Intrinsic::x86_avx_ptestc_256:
14937 case Intrinsic::x86_avx_ptestnzc_256:
14938 case Intrinsic::x86_avx_vtestz_ps:
14939 case Intrinsic::x86_avx_vtestc_ps:
14940 case Intrinsic::x86_avx_vtestnzc_ps:
14941 case Intrinsic::x86_avx_vtestz_pd:
14942 case Intrinsic::x86_avx_vtestc_pd:
14943 case Intrinsic::x86_avx_vtestnzc_pd:
14944 case Intrinsic::x86_avx_vtestz_ps_256:
14945 case Intrinsic::x86_avx_vtestc_ps_256:
14946 case Intrinsic::x86_avx_vtestnzc_ps_256:
14947 case Intrinsic::x86_avx_vtestz_pd_256:
14948 case Intrinsic::x86_avx_vtestc_pd_256:
14949 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14950 bool IsTestPacked = false;
14953 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14954 case Intrinsic::x86_avx_vtestz_ps:
14955 case Intrinsic::x86_avx_vtestz_pd:
14956 case Intrinsic::x86_avx_vtestz_ps_256:
14957 case Intrinsic::x86_avx_vtestz_pd_256:
14958 IsTestPacked = true; // Fallthrough
14959 case Intrinsic::x86_sse41_ptestz:
14960 case Intrinsic::x86_avx_ptestz_256:
14962 X86CC = X86::COND_E;
14964 case Intrinsic::x86_avx_vtestc_ps:
14965 case Intrinsic::x86_avx_vtestc_pd:
14966 case Intrinsic::x86_avx_vtestc_ps_256:
14967 case Intrinsic::x86_avx_vtestc_pd_256:
14968 IsTestPacked = true; // Fallthrough
14969 case Intrinsic::x86_sse41_ptestc:
14970 case Intrinsic::x86_avx_ptestc_256:
14972 X86CC = X86::COND_B;
14974 case Intrinsic::x86_avx_vtestnzc_ps:
14975 case Intrinsic::x86_avx_vtestnzc_pd:
14976 case Intrinsic::x86_avx_vtestnzc_ps_256:
14977 case Intrinsic::x86_avx_vtestnzc_pd_256:
14978 IsTestPacked = true; // Fallthrough
14979 case Intrinsic::x86_sse41_ptestnzc:
14980 case Intrinsic::x86_avx_ptestnzc_256:
14982 X86CC = X86::COND_A;
14986 SDValue LHS = Op.getOperand(1);
14987 SDValue RHS = Op.getOperand(2);
14988 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14989 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14990 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14991 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14992 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14994 case Intrinsic::x86_avx512_kortestz_w:
14995 case Intrinsic::x86_avx512_kortestc_w: {
14996 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14997 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14998 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14999 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15000 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15001 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15002 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15005 case Intrinsic::x86_sse42_pcmpistria128:
15006 case Intrinsic::x86_sse42_pcmpestria128:
15007 case Intrinsic::x86_sse42_pcmpistric128:
15008 case Intrinsic::x86_sse42_pcmpestric128:
15009 case Intrinsic::x86_sse42_pcmpistrio128:
15010 case Intrinsic::x86_sse42_pcmpestrio128:
15011 case Intrinsic::x86_sse42_pcmpistris128:
15012 case Intrinsic::x86_sse42_pcmpestris128:
15013 case Intrinsic::x86_sse42_pcmpistriz128:
15014 case Intrinsic::x86_sse42_pcmpestriz128: {
15018 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15019 case Intrinsic::x86_sse42_pcmpistria128:
15020 Opcode = X86ISD::PCMPISTRI;
15021 X86CC = X86::COND_A;
15023 case Intrinsic::x86_sse42_pcmpestria128:
15024 Opcode = X86ISD::PCMPESTRI;
15025 X86CC = X86::COND_A;
15027 case Intrinsic::x86_sse42_pcmpistric128:
15028 Opcode = X86ISD::PCMPISTRI;
15029 X86CC = X86::COND_B;
15031 case Intrinsic::x86_sse42_pcmpestric128:
15032 Opcode = X86ISD::PCMPESTRI;
15033 X86CC = X86::COND_B;
15035 case Intrinsic::x86_sse42_pcmpistrio128:
15036 Opcode = X86ISD::PCMPISTRI;
15037 X86CC = X86::COND_O;
15039 case Intrinsic::x86_sse42_pcmpestrio128:
15040 Opcode = X86ISD::PCMPESTRI;
15041 X86CC = X86::COND_O;
15043 case Intrinsic::x86_sse42_pcmpistris128:
15044 Opcode = X86ISD::PCMPISTRI;
15045 X86CC = X86::COND_S;
15047 case Intrinsic::x86_sse42_pcmpestris128:
15048 Opcode = X86ISD::PCMPESTRI;
15049 X86CC = X86::COND_S;
15051 case Intrinsic::x86_sse42_pcmpistriz128:
15052 Opcode = X86ISD::PCMPISTRI;
15053 X86CC = X86::COND_E;
15055 case Intrinsic::x86_sse42_pcmpestriz128:
15056 Opcode = X86ISD::PCMPESTRI;
15057 X86CC = X86::COND_E;
15060 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15061 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15062 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15063 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15064 DAG.getConstant(X86CC, MVT::i8),
15065 SDValue(PCMP.getNode(), 1));
15066 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15069 case Intrinsic::x86_sse42_pcmpistri128:
15070 case Intrinsic::x86_sse42_pcmpestri128: {
15072 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15073 Opcode = X86ISD::PCMPISTRI;
15075 Opcode = X86ISD::PCMPESTRI;
15077 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15078 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15079 return DAG.getNode(Opcode, dl, VTs, NewOps);
15084 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15085 SDValue Src, SDValue Mask, SDValue Base,
15086 SDValue Index, SDValue ScaleOp, SDValue Chain,
15087 const X86Subtarget * Subtarget) {
15089 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15090 assert(C && "Invalid scale type");
15091 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15092 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15093 Index.getSimpleValueType().getVectorNumElements());
15095 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15097 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15099 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15100 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15101 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15102 SDValue Segment = DAG.getRegister(0, MVT::i32);
15103 if (Src.getOpcode() == ISD::UNDEF)
15104 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15105 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15106 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15107 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15108 return DAG.getMergeValues(RetOps, dl);
15111 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15112 SDValue Src, SDValue Mask, SDValue Base,
15113 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15115 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15116 assert(C && "Invalid scale type");
15117 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15118 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15119 SDValue Segment = DAG.getRegister(0, MVT::i32);
15120 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15121 Index.getSimpleValueType().getVectorNumElements());
15123 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15125 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15127 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15128 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15129 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15130 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15131 return SDValue(Res, 1);
15134 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15135 SDValue Mask, SDValue Base, SDValue Index,
15136 SDValue ScaleOp, SDValue Chain) {
15138 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15139 assert(C && "Invalid scale type");
15140 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15141 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15142 SDValue Segment = DAG.getRegister(0, MVT::i32);
15144 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15146 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15148 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15150 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15151 //SDVTList VTs = DAG.getVTList(MVT::Other);
15152 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15153 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15154 return SDValue(Res, 0);
15157 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15158 // read performance monitor counters (x86_rdpmc).
15159 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15160 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15161 SmallVectorImpl<SDValue> &Results) {
15162 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15163 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15166 // The ECX register is used to select the index of the performance counter
15168 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15170 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15172 // Reads the content of a 64-bit performance counter and returns it in the
15173 // registers EDX:EAX.
15174 if (Subtarget->is64Bit()) {
15175 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15176 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15179 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15180 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15183 Chain = HI.getValue(1);
15185 if (Subtarget->is64Bit()) {
15186 // The EAX register is loaded with the low-order 32 bits. The EDX register
15187 // is loaded with the supported high-order bits of the counter.
15188 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15189 DAG.getConstant(32, MVT::i8));
15190 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15191 Results.push_back(Chain);
15195 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15196 SDValue Ops[] = { LO, HI };
15197 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15198 Results.push_back(Pair);
15199 Results.push_back(Chain);
15202 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15203 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15204 // also used to custom lower READCYCLECOUNTER nodes.
15205 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15206 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15207 SmallVectorImpl<SDValue> &Results) {
15208 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15209 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15212 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15213 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15214 // and the EAX register is loaded with the low-order 32 bits.
15215 if (Subtarget->is64Bit()) {
15216 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15217 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15220 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15221 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15224 SDValue Chain = HI.getValue(1);
15226 if (Opcode == X86ISD::RDTSCP_DAG) {
15227 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15229 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15230 // the ECX register. Add 'ecx' explicitly to the chain.
15231 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15233 // Explicitly store the content of ECX at the location passed in input
15234 // to the 'rdtscp' intrinsic.
15235 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15236 MachinePointerInfo(), false, false, 0);
15239 if (Subtarget->is64Bit()) {
15240 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15241 // the EAX register is loaded with the low-order 32 bits.
15242 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15243 DAG.getConstant(32, MVT::i8));
15244 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15245 Results.push_back(Chain);
15249 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15250 SDValue Ops[] = { LO, HI };
15251 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15252 Results.push_back(Pair);
15253 Results.push_back(Chain);
15256 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15257 SelectionDAG &DAG) {
15258 SmallVector<SDValue, 2> Results;
15260 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15262 return DAG.getMergeValues(Results, DL);
15266 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15267 SelectionDAG &DAG) {
15268 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15270 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15275 switch(IntrData->Type) {
15277 llvm_unreachable("Unknown Intrinsic Type");
15281 // Emit the node with the right value type.
15282 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15283 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15285 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15286 // Otherwise return the value from Rand, which is always 0, casted to i32.
15287 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15288 DAG.getConstant(1, Op->getValueType(1)),
15289 DAG.getConstant(X86::COND_B, MVT::i32),
15290 SDValue(Result.getNode(), 1) };
15291 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15292 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15295 // Return { result, isValid, chain }.
15296 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15297 SDValue(Result.getNode(), 2));
15300 //gather(v1, mask, index, base, scale);
15301 SDValue Chain = Op.getOperand(0);
15302 SDValue Src = Op.getOperand(2);
15303 SDValue Base = Op.getOperand(3);
15304 SDValue Index = Op.getOperand(4);
15305 SDValue Mask = Op.getOperand(5);
15306 SDValue Scale = Op.getOperand(6);
15307 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15311 //scatter(base, mask, index, v1, scale);
15312 SDValue Chain = Op.getOperand(0);
15313 SDValue Base = Op.getOperand(2);
15314 SDValue Mask = Op.getOperand(3);
15315 SDValue Index = Op.getOperand(4);
15316 SDValue Src = Op.getOperand(5);
15317 SDValue Scale = Op.getOperand(6);
15318 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15321 SDValue Hint = Op.getOperand(6);
15322 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15323 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15324 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15325 SDValue Chain = Op.getOperand(0);
15326 SDValue Mask = Op.getOperand(2);
15327 SDValue Index = Op.getOperand(3);
15328 SDValue Base = Op.getOperand(4);
15329 SDValue Scale = Op.getOperand(5);
15330 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15332 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15334 SmallVector<SDValue, 2> Results;
15335 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15336 return DAG.getMergeValues(Results, dl);
15338 // Read Performance Monitoring Counters.
15340 SmallVector<SDValue, 2> Results;
15341 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15342 return DAG.getMergeValues(Results, dl);
15344 // XTEST intrinsics.
15346 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15347 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15348 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15349 DAG.getConstant(X86::COND_NE, MVT::i8),
15351 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15352 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15353 Ret, SDValue(InTrans.getNode(), 1));
15357 SmallVector<SDValue, 2> Results;
15358 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15359 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15360 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15361 DAG.getConstant(-1, MVT::i8));
15362 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15363 Op.getOperand(4), GenCF.getValue(1));
15364 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15365 Op.getOperand(5), MachinePointerInfo(),
15367 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15368 DAG.getConstant(X86::COND_B, MVT::i8),
15370 Results.push_back(SetCC);
15371 Results.push_back(Store);
15372 return DAG.getMergeValues(Results, dl);
15374 case COMPRESS_TO_MEM: {
15376 SDValue Mask = Op.getOperand(4);
15377 SDValue DataToCompress = Op.getOperand(3);
15378 SDValue Addr = Op.getOperand(2);
15379 SDValue Chain = Op.getOperand(0);
15381 if (isAllOnes(Mask)) // return just a store
15382 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15383 MachinePointerInfo(), false, false, 0);
15385 EVT VT = DataToCompress.getValueType();
15386 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15387 VT.getVectorNumElements());
15388 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15389 Mask.getValueType().getSizeInBits());
15390 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15391 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15392 DAG.getIntPtrConstant(0));
15394 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15395 DataToCompress, DAG.getUNDEF(VT));
15396 return DAG.getStore(Chain, dl, Compressed, Addr,
15397 MachinePointerInfo(), false, false, 0);
15399 case EXPAND_FROM_MEM: {
15401 SDValue Mask = Op.getOperand(4);
15402 SDValue PathThru = Op.getOperand(3);
15403 SDValue Addr = Op.getOperand(2);
15404 SDValue Chain = Op.getOperand(0);
15405 EVT VT = Op.getValueType();
15407 if (isAllOnes(Mask)) // return just a load
15408 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15410 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15411 VT.getVectorNumElements());
15412 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15413 Mask.getValueType().getSizeInBits());
15414 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15415 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15416 DAG.getIntPtrConstant(0));
15418 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15419 false, false, false, 0);
15421 SDValue Results[] = {
15422 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15424 return DAG.getMergeValues(Results, dl);
15429 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15430 SelectionDAG &DAG) const {
15431 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15432 MFI->setReturnAddressIsTaken(true);
15434 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15437 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15439 EVT PtrVT = getPointerTy();
15442 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15443 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15444 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15445 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15446 DAG.getNode(ISD::ADD, dl, PtrVT,
15447 FrameAddr, Offset),
15448 MachinePointerInfo(), false, false, false, 0);
15451 // Just load the return address.
15452 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15453 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15454 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15457 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15458 MachineFunction &MF = DAG.getMachineFunction();
15459 MachineFrameInfo *MFI = MF.getFrameInfo();
15460 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15461 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15462 EVT VT = Op.getValueType();
15464 MFI->setFrameAddressIsTaken(true);
15466 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15467 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15468 // is not possible to crawl up the stack without looking at the unwind codes
15470 int FrameAddrIndex = FuncInfo->getFAIndex();
15471 if (!FrameAddrIndex) {
15472 // Set up a frame object for the return address.
15473 unsigned SlotSize = RegInfo->getSlotSize();
15474 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15475 SlotSize, /*Offset=*/INT64_MIN, /*IsImmutable=*/false);
15476 FuncInfo->setFAIndex(FrameAddrIndex);
15478 return DAG.getFrameIndex(FrameAddrIndex, VT);
15481 unsigned FrameReg =
15482 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15483 SDLoc dl(Op); // FIXME probably not meaningful
15484 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15485 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15486 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15487 "Invalid Frame Register!");
15488 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15490 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15491 MachinePointerInfo(),
15492 false, false, false, 0);
15496 // FIXME? Maybe this could be a TableGen attribute on some registers and
15497 // this table could be generated automatically from RegInfo.
15498 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15500 unsigned Reg = StringSwitch<unsigned>(RegName)
15501 .Case("esp", X86::ESP)
15502 .Case("rsp", X86::RSP)
15506 report_fatal_error("Invalid register name global variable");
15509 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15510 SelectionDAG &DAG) const {
15511 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15512 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15515 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15516 SDValue Chain = Op.getOperand(0);
15517 SDValue Offset = Op.getOperand(1);
15518 SDValue Handler = Op.getOperand(2);
15521 EVT PtrVT = getPointerTy();
15522 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15523 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15524 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15525 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15526 "Invalid Frame Register!");
15527 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15528 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15530 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15531 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15532 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15533 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15535 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15537 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15538 DAG.getRegister(StoreAddrReg, PtrVT));
15541 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15542 SelectionDAG &DAG) const {
15544 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15545 DAG.getVTList(MVT::i32, MVT::Other),
15546 Op.getOperand(0), Op.getOperand(1));
15549 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15550 SelectionDAG &DAG) const {
15552 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15553 Op.getOperand(0), Op.getOperand(1));
15556 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15557 return Op.getOperand(0);
15560 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15561 SelectionDAG &DAG) const {
15562 SDValue Root = Op.getOperand(0);
15563 SDValue Trmp = Op.getOperand(1); // trampoline
15564 SDValue FPtr = Op.getOperand(2); // nested function
15565 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15568 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15569 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15571 if (Subtarget->is64Bit()) {
15572 SDValue OutChains[6];
15574 // Large code-model.
15575 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15576 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15578 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15579 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15581 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15583 // Load the pointer to the nested function into R11.
15584 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15585 SDValue Addr = Trmp;
15586 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15587 Addr, MachinePointerInfo(TrmpAddr),
15590 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15591 DAG.getConstant(2, MVT::i64));
15592 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15593 MachinePointerInfo(TrmpAddr, 2),
15596 // Load the 'nest' parameter value into R10.
15597 // R10 is specified in X86CallingConv.td
15598 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15599 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15600 DAG.getConstant(10, MVT::i64));
15601 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15602 Addr, MachinePointerInfo(TrmpAddr, 10),
15605 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15606 DAG.getConstant(12, MVT::i64));
15607 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15608 MachinePointerInfo(TrmpAddr, 12),
15611 // Jump to the nested function.
15612 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15613 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15614 DAG.getConstant(20, MVT::i64));
15615 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15616 Addr, MachinePointerInfo(TrmpAddr, 20),
15619 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15620 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15621 DAG.getConstant(22, MVT::i64));
15622 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15623 MachinePointerInfo(TrmpAddr, 22),
15626 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15628 const Function *Func =
15629 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15630 CallingConv::ID CC = Func->getCallingConv();
15635 llvm_unreachable("Unsupported calling convention");
15636 case CallingConv::C:
15637 case CallingConv::X86_StdCall: {
15638 // Pass 'nest' parameter in ECX.
15639 // Must be kept in sync with X86CallingConv.td
15640 NestReg = X86::ECX;
15642 // Check that ECX wasn't needed by an 'inreg' parameter.
15643 FunctionType *FTy = Func->getFunctionType();
15644 const AttributeSet &Attrs = Func->getAttributes();
15646 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15647 unsigned InRegCount = 0;
15650 for (FunctionType::param_iterator I = FTy->param_begin(),
15651 E = FTy->param_end(); I != E; ++I, ++Idx)
15652 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15653 // FIXME: should only count parameters that are lowered to integers.
15654 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15656 if (InRegCount > 2) {
15657 report_fatal_error("Nest register in use - reduce number of inreg"
15663 case CallingConv::X86_FastCall:
15664 case CallingConv::X86_ThisCall:
15665 case CallingConv::Fast:
15666 // Pass 'nest' parameter in EAX.
15667 // Must be kept in sync with X86CallingConv.td
15668 NestReg = X86::EAX;
15672 SDValue OutChains[4];
15673 SDValue Addr, Disp;
15675 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15676 DAG.getConstant(10, MVT::i32));
15677 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15679 // This is storing the opcode for MOV32ri.
15680 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15681 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15682 OutChains[0] = DAG.getStore(Root, dl,
15683 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15684 Trmp, MachinePointerInfo(TrmpAddr),
15687 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15688 DAG.getConstant(1, MVT::i32));
15689 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15690 MachinePointerInfo(TrmpAddr, 1),
15693 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15694 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15695 DAG.getConstant(5, MVT::i32));
15696 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15697 MachinePointerInfo(TrmpAddr, 5),
15700 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15701 DAG.getConstant(6, MVT::i32));
15702 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15703 MachinePointerInfo(TrmpAddr, 6),
15706 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15710 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15711 SelectionDAG &DAG) const {
15713 The rounding mode is in bits 11:10 of FPSR, and has the following
15715 00 Round to nearest
15720 FLT_ROUNDS, on the other hand, expects the following:
15727 To perform the conversion, we do:
15728 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15731 MachineFunction &MF = DAG.getMachineFunction();
15732 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15733 unsigned StackAlignment = TFI.getStackAlignment();
15734 MVT VT = Op.getSimpleValueType();
15737 // Save FP Control Word to stack slot
15738 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15739 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15741 MachineMemOperand *MMO =
15742 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15743 MachineMemOperand::MOStore, 2, 2);
15745 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15746 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15747 DAG.getVTList(MVT::Other),
15748 Ops, MVT::i16, MMO);
15750 // Load FP Control Word from stack slot
15751 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15752 MachinePointerInfo(), false, false, false, 0);
15754 // Transform as necessary
15756 DAG.getNode(ISD::SRL, DL, MVT::i16,
15757 DAG.getNode(ISD::AND, DL, MVT::i16,
15758 CWD, DAG.getConstant(0x800, MVT::i16)),
15759 DAG.getConstant(11, MVT::i8));
15761 DAG.getNode(ISD::SRL, DL, MVT::i16,
15762 DAG.getNode(ISD::AND, DL, MVT::i16,
15763 CWD, DAG.getConstant(0x400, MVT::i16)),
15764 DAG.getConstant(9, MVT::i8));
15767 DAG.getNode(ISD::AND, DL, MVT::i16,
15768 DAG.getNode(ISD::ADD, DL, MVT::i16,
15769 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15770 DAG.getConstant(1, MVT::i16)),
15771 DAG.getConstant(3, MVT::i16));
15773 return DAG.getNode((VT.getSizeInBits() < 16 ?
15774 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15777 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15778 MVT VT = Op.getSimpleValueType();
15780 unsigned NumBits = VT.getSizeInBits();
15783 Op = Op.getOperand(0);
15784 if (VT == MVT::i8) {
15785 // Zero extend to i32 since there is not an i8 bsr.
15787 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15790 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15791 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15792 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15794 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15797 DAG.getConstant(NumBits+NumBits-1, OpVT),
15798 DAG.getConstant(X86::COND_E, MVT::i8),
15801 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15803 // Finally xor with NumBits-1.
15804 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15807 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15811 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15812 MVT VT = Op.getSimpleValueType();
15814 unsigned NumBits = VT.getSizeInBits();
15817 Op = Op.getOperand(0);
15818 if (VT == MVT::i8) {
15819 // Zero extend to i32 since there is not an i8 bsr.
15821 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15824 // Issue a bsr (scan bits in reverse).
15825 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15826 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15828 // And xor with NumBits-1.
15829 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15832 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15836 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15837 MVT VT = Op.getSimpleValueType();
15838 unsigned NumBits = VT.getSizeInBits();
15840 Op = Op.getOperand(0);
15842 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15843 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15844 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15846 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15849 DAG.getConstant(NumBits, VT),
15850 DAG.getConstant(X86::COND_E, MVT::i8),
15853 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15856 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15857 // ones, and then concatenate the result back.
15858 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15859 MVT VT = Op.getSimpleValueType();
15861 assert(VT.is256BitVector() && VT.isInteger() &&
15862 "Unsupported value type for operation");
15864 unsigned NumElems = VT.getVectorNumElements();
15867 // Extract the LHS vectors
15868 SDValue LHS = Op.getOperand(0);
15869 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15870 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15872 // Extract the RHS vectors
15873 SDValue RHS = Op.getOperand(1);
15874 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15875 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15877 MVT EltVT = VT.getVectorElementType();
15878 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15880 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15881 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15882 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15885 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15886 assert(Op.getSimpleValueType().is256BitVector() &&
15887 Op.getSimpleValueType().isInteger() &&
15888 "Only handle AVX 256-bit vector integer operation");
15889 return Lower256IntArith(Op, DAG);
15892 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15893 assert(Op.getSimpleValueType().is256BitVector() &&
15894 Op.getSimpleValueType().isInteger() &&
15895 "Only handle AVX 256-bit vector integer operation");
15896 return Lower256IntArith(Op, DAG);
15899 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15900 SelectionDAG &DAG) {
15902 MVT VT = Op.getSimpleValueType();
15904 // Decompose 256-bit ops into smaller 128-bit ops.
15905 if (VT.is256BitVector() && !Subtarget->hasInt256())
15906 return Lower256IntArith(Op, DAG);
15908 SDValue A = Op.getOperand(0);
15909 SDValue B = Op.getOperand(1);
15911 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15912 if (VT == MVT::v4i32) {
15913 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15914 "Should not custom lower when pmuldq is available!");
15916 // Extract the odd parts.
15917 static const int UnpackMask[] = { 1, -1, 3, -1 };
15918 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15919 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15921 // Multiply the even parts.
15922 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15923 // Now multiply odd parts.
15924 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15926 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15927 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15929 // Merge the two vectors back together with a shuffle. This expands into 2
15931 static const int ShufMask[] = { 0, 4, 2, 6 };
15932 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15935 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15936 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15938 // Ahi = psrlqi(a, 32);
15939 // Bhi = psrlqi(b, 32);
15941 // AloBlo = pmuludq(a, b);
15942 // AloBhi = pmuludq(a, Bhi);
15943 // AhiBlo = pmuludq(Ahi, b);
15945 // AloBhi = psllqi(AloBhi, 32);
15946 // AhiBlo = psllqi(AhiBlo, 32);
15947 // return AloBlo + AloBhi + AhiBlo;
15949 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15950 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15952 // Bit cast to 32-bit vectors for MULUDQ
15953 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15954 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15955 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15956 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15957 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15958 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15960 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15961 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15962 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15964 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15965 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15967 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15968 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15971 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15972 assert(Subtarget->isTargetWin64() && "Unexpected target");
15973 EVT VT = Op.getValueType();
15974 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15975 "Unexpected return type for lowering");
15979 switch (Op->getOpcode()) {
15980 default: llvm_unreachable("Unexpected request for libcall!");
15981 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15982 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15983 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15984 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15985 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15986 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15990 SDValue InChain = DAG.getEntryNode();
15992 TargetLowering::ArgListTy Args;
15993 TargetLowering::ArgListEntry Entry;
15994 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15995 EVT ArgVT = Op->getOperand(i).getValueType();
15996 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15997 "Unexpected argument type for lowering");
15998 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15999 Entry.Node = StackPtr;
16000 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16002 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16003 Entry.Ty = PointerType::get(ArgTy,0);
16004 Entry.isSExt = false;
16005 Entry.isZExt = false;
16006 Args.push_back(Entry);
16009 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16012 TargetLowering::CallLoweringInfo CLI(DAG);
16013 CLI.setDebugLoc(dl).setChain(InChain)
16014 .setCallee(getLibcallCallingConv(LC),
16015 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16016 Callee, std::move(Args), 0)
16017 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16019 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16020 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16023 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16024 SelectionDAG &DAG) {
16025 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16026 EVT VT = Op0.getValueType();
16029 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16030 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16032 // PMULxD operations multiply each even value (starting at 0) of LHS with
16033 // the related value of RHS and produce a widen result.
16034 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16035 // => <2 x i64> <ae|cg>
16037 // In other word, to have all the results, we need to perform two PMULxD:
16038 // 1. one with the even values.
16039 // 2. one with the odd values.
16040 // To achieve #2, with need to place the odd values at an even position.
16042 // Place the odd value at an even position (basically, shift all values 1
16043 // step to the left):
16044 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16045 // <a|b|c|d> => <b|undef|d|undef>
16046 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16047 // <e|f|g|h> => <f|undef|h|undef>
16048 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16050 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16052 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16053 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16055 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16056 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16057 // => <2 x i64> <ae|cg>
16058 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16059 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16060 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16061 // => <2 x i64> <bf|dh>
16062 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16063 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16065 // Shuffle it back into the right order.
16066 SDValue Highs, Lows;
16067 if (VT == MVT::v8i32) {
16068 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16069 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16070 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16071 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16073 const int HighMask[] = {1, 5, 3, 7};
16074 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16075 const int LowMask[] = {0, 4, 2, 6};
16076 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16079 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16080 // unsigned multiply.
16081 if (IsSigned && !Subtarget->hasSSE41()) {
16083 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16084 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16085 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16086 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16087 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16089 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16090 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16093 // The first result of MUL_LOHI is actually the low value, followed by the
16095 SDValue Ops[] = {Lows, Highs};
16096 return DAG.getMergeValues(Ops, dl);
16099 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16100 const X86Subtarget *Subtarget) {
16101 MVT VT = Op.getSimpleValueType();
16103 SDValue R = Op.getOperand(0);
16104 SDValue Amt = Op.getOperand(1);
16106 // Optimize shl/srl/sra with constant shift amount.
16107 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16108 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16109 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16111 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16112 (Subtarget->hasInt256() &&
16113 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16114 (Subtarget->hasAVX512() &&
16115 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16116 if (Op.getOpcode() == ISD::SHL)
16117 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16119 if (Op.getOpcode() == ISD::SRL)
16120 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16122 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16123 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16127 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16128 unsigned NumElts = VT.getVectorNumElements();
16129 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16131 if (Op.getOpcode() == ISD::SHL) {
16132 // Make a large shift.
16133 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16135 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16136 // Zero out the rightmost bits.
16137 SmallVector<SDValue, 32> V(
16138 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), MVT::i8));
16139 return DAG.getNode(ISD::AND, dl, VT, SHL,
16140 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16142 if (Op.getOpcode() == ISD::SRL) {
16143 // Make a large shift.
16144 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16146 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16147 // Zero out the leftmost bits.
16148 SmallVector<SDValue, 32> V(
16149 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, MVT::i8));
16150 return DAG.getNode(ISD::AND, dl, VT, SRL,
16151 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16153 if (Op.getOpcode() == ISD::SRA) {
16154 if (ShiftAmt == 7) {
16155 // R s>> 7 === R s< 0
16156 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16157 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16160 // R s>> a === ((R u>> a) ^ m) - m
16161 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16162 SmallVector<SDValue, 32> V(NumElts,
16163 DAG.getConstant(128 >> ShiftAmt, MVT::i8));
16164 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16165 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16166 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16169 llvm_unreachable("Unknown shift opcode.");
16174 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16175 if (!Subtarget->is64Bit() &&
16176 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16177 Amt.getOpcode() == ISD::BITCAST &&
16178 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16179 Amt = Amt.getOperand(0);
16180 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16181 VT.getVectorNumElements();
16182 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16183 uint64_t ShiftAmt = 0;
16184 for (unsigned i = 0; i != Ratio; ++i) {
16185 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16189 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16191 // Check remaining shift amounts.
16192 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16193 uint64_t ShAmt = 0;
16194 for (unsigned j = 0; j != Ratio; ++j) {
16195 ConstantSDNode *C =
16196 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16200 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16202 if (ShAmt != ShiftAmt)
16205 switch (Op.getOpcode()) {
16207 llvm_unreachable("Unknown shift opcode!");
16209 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16212 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16215 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16223 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16224 const X86Subtarget* Subtarget) {
16225 MVT VT = Op.getSimpleValueType();
16227 SDValue R = Op.getOperand(0);
16228 SDValue Amt = Op.getOperand(1);
16230 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16231 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16232 (Subtarget->hasInt256() &&
16233 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16234 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16235 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16237 EVT EltVT = VT.getVectorElementType();
16239 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16240 // Check if this build_vector node is doing a splat.
16241 // If so, then set BaseShAmt equal to the splat value.
16242 BaseShAmt = BV->getSplatValue();
16243 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16244 BaseShAmt = SDValue();
16246 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16247 Amt = Amt.getOperand(0);
16249 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16250 if (SVN && SVN->isSplat()) {
16251 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16252 SDValue InVec = Amt.getOperand(0);
16253 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16254 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16255 "Unexpected shuffle index found!");
16256 BaseShAmt = InVec.getOperand(SplatIdx);
16257 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16258 if (ConstantSDNode *C =
16259 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16260 if (C->getZExtValue() == SplatIdx)
16261 BaseShAmt = InVec.getOperand(1);
16266 // Avoid introducing an extract element from a shuffle.
16267 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16268 DAG.getIntPtrConstant(SplatIdx));
16272 if (BaseShAmt.getNode()) {
16273 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16274 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16275 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16276 else if (EltVT.bitsLT(MVT::i32))
16277 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16279 switch (Op.getOpcode()) {
16281 llvm_unreachable("Unknown shift opcode!");
16283 switch (VT.SimpleTy) {
16284 default: return SDValue();
16293 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16296 switch (VT.SimpleTy) {
16297 default: return SDValue();
16304 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16307 switch (VT.SimpleTy) {
16308 default: return SDValue();
16317 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16323 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16324 if (!Subtarget->is64Bit() &&
16325 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16326 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16327 Amt.getOpcode() == ISD::BITCAST &&
16328 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16329 Amt = Amt.getOperand(0);
16330 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16331 VT.getVectorNumElements();
16332 std::vector<SDValue> Vals(Ratio);
16333 for (unsigned i = 0; i != Ratio; ++i)
16334 Vals[i] = Amt.getOperand(i);
16335 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16336 for (unsigned j = 0; j != Ratio; ++j)
16337 if (Vals[j] != Amt.getOperand(i + j))
16340 switch (Op.getOpcode()) {
16342 llvm_unreachable("Unknown shift opcode!");
16344 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16346 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16348 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16355 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16356 SelectionDAG &DAG) {
16357 MVT VT = Op.getSimpleValueType();
16359 SDValue R = Op.getOperand(0);
16360 SDValue Amt = Op.getOperand(1);
16362 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16363 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16365 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16368 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16371 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16374 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16375 if (Subtarget->hasInt256()) {
16376 if (Op.getOpcode() == ISD::SRL &&
16377 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16378 VT == MVT::v4i64 || VT == MVT::v8i32))
16380 if (Op.getOpcode() == ISD::SHL &&
16381 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16382 VT == MVT::v4i64 || VT == MVT::v8i32))
16384 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16388 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16389 // shifts per-lane and then shuffle the partial results back together.
16390 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16391 // Splat the shift amounts so the scalar shifts above will catch it.
16392 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16393 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16394 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16395 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16396 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16399 // If possible, lower this packed shift into a vector multiply instead of
16400 // expanding it into a sequence of scalar shifts.
16401 // Do this only if the vector shift count is a constant build_vector.
16402 if (Op.getOpcode() == ISD::SHL &&
16403 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16404 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16405 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16406 SmallVector<SDValue, 8> Elts;
16407 EVT SVT = VT.getScalarType();
16408 unsigned SVTBits = SVT.getSizeInBits();
16409 const APInt &One = APInt(SVTBits, 1);
16410 unsigned NumElems = VT.getVectorNumElements();
16412 for (unsigned i=0; i !=NumElems; ++i) {
16413 SDValue Op = Amt->getOperand(i);
16414 if (Op->getOpcode() == ISD::UNDEF) {
16415 Elts.push_back(Op);
16419 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16420 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16421 uint64_t ShAmt = C.getZExtValue();
16422 if (ShAmt >= SVTBits) {
16423 Elts.push_back(DAG.getUNDEF(SVT));
16426 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16428 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16429 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16432 // Lower SHL with variable shift amount.
16433 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16434 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16436 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16437 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16438 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16439 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16442 // If possible, lower this shift as a sequence of two shifts by
16443 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16445 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16447 // Could be rewritten as:
16448 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16450 // The advantage is that the two shifts from the example would be
16451 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16452 // the vector shift into four scalar shifts plus four pairs of vector
16454 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16455 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16456 unsigned TargetOpcode = X86ISD::MOVSS;
16457 bool CanBeSimplified;
16458 // The splat value for the first packed shift (the 'X' from the example).
16459 SDValue Amt1 = Amt->getOperand(0);
16460 // The splat value for the second packed shift (the 'Y' from the example).
16461 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16462 Amt->getOperand(2);
16464 // See if it is possible to replace this node with a sequence of
16465 // two shifts followed by a MOVSS/MOVSD
16466 if (VT == MVT::v4i32) {
16467 // Check if it is legal to use a MOVSS.
16468 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16469 Amt2 == Amt->getOperand(3);
16470 if (!CanBeSimplified) {
16471 // Otherwise, check if we can still simplify this node using a MOVSD.
16472 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16473 Amt->getOperand(2) == Amt->getOperand(3);
16474 TargetOpcode = X86ISD::MOVSD;
16475 Amt2 = Amt->getOperand(2);
16478 // Do similar checks for the case where the machine value type
16480 CanBeSimplified = Amt1 == Amt->getOperand(1);
16481 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16482 CanBeSimplified = Amt2 == Amt->getOperand(i);
16484 if (!CanBeSimplified) {
16485 TargetOpcode = X86ISD::MOVSD;
16486 CanBeSimplified = true;
16487 Amt2 = Amt->getOperand(4);
16488 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16489 CanBeSimplified = Amt1 == Amt->getOperand(i);
16490 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16491 CanBeSimplified = Amt2 == Amt->getOperand(j);
16495 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16496 isa<ConstantSDNode>(Amt2)) {
16497 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16498 EVT CastVT = MVT::v4i32;
16500 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16501 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16503 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16504 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16505 if (TargetOpcode == X86ISD::MOVSD)
16506 CastVT = MVT::v2i64;
16507 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16508 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16509 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16511 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16515 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16516 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16519 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16520 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16522 // Turn 'a' into a mask suitable for VSELECT
16523 SDValue VSelM = DAG.getConstant(0x80, VT);
16524 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16525 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16527 SDValue CM1 = DAG.getConstant(0x0f, VT);
16528 SDValue CM2 = DAG.getConstant(0x3f, VT);
16530 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16531 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16532 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16533 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16534 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16537 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16538 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16539 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16541 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16542 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16543 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16544 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16545 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16548 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16549 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16550 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16552 // return VSELECT(r, r+r, a);
16553 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16554 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16558 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16559 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16560 // solution better.
16561 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16562 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16564 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16565 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16566 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16567 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16568 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16571 // Decompose 256-bit shifts into smaller 128-bit shifts.
16572 if (VT.is256BitVector()) {
16573 unsigned NumElems = VT.getVectorNumElements();
16574 MVT EltVT = VT.getVectorElementType();
16575 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16577 // Extract the two vectors
16578 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16579 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16581 // Recreate the shift amount vectors
16582 SDValue Amt1, Amt2;
16583 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16584 // Constant shift amount
16585 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16586 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16587 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16589 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16590 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16592 // Variable shift amount
16593 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16594 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16597 // Issue new vector shifts for the smaller types
16598 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16599 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16601 // Concatenate the result back
16602 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16608 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16609 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16610 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16611 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16612 // has only one use.
16613 SDNode *N = Op.getNode();
16614 SDValue LHS = N->getOperand(0);
16615 SDValue RHS = N->getOperand(1);
16616 unsigned BaseOp = 0;
16619 switch (Op.getOpcode()) {
16620 default: llvm_unreachable("Unknown ovf instruction!");
16622 // A subtract of one will be selected as a INC. Note that INC doesn't
16623 // set CF, so we can't do this for UADDO.
16624 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16626 BaseOp = X86ISD::INC;
16627 Cond = X86::COND_O;
16630 BaseOp = X86ISD::ADD;
16631 Cond = X86::COND_O;
16634 BaseOp = X86ISD::ADD;
16635 Cond = X86::COND_B;
16638 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16639 // set CF, so we can't do this for USUBO.
16640 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16642 BaseOp = X86ISD::DEC;
16643 Cond = X86::COND_O;
16646 BaseOp = X86ISD::SUB;
16647 Cond = X86::COND_O;
16650 BaseOp = X86ISD::SUB;
16651 Cond = X86::COND_B;
16654 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
16655 Cond = X86::COND_O;
16657 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16658 if (N->getValueType(0) == MVT::i8) {
16659 BaseOp = X86ISD::UMUL8;
16660 Cond = X86::COND_O;
16663 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16665 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16668 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16669 DAG.getConstant(X86::COND_O, MVT::i32),
16670 SDValue(Sum.getNode(), 2));
16672 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16676 // Also sets EFLAGS.
16677 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16678 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16681 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16682 DAG.getConstant(Cond, MVT::i32),
16683 SDValue(Sum.getNode(), 1));
16685 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16688 /// Returns true if the operand type is exactly twice the native width, and
16689 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
16690 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
16691 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
16692 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
16693 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
16696 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
16697 else if (OpWidth == 128)
16698 return Subtarget->hasCmpxchg16b();
16703 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
16704 return needsCmpXchgNb(SI->getValueOperand()->getType());
16707 // Note: this turns large loads into lock cmpxchg8b/16b.
16708 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
16709 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
16710 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
16711 return needsCmpXchgNb(PTy->getElementType());
16714 TargetLoweringBase::AtomicRMWExpansionKind
16715 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
16716 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16717 const Type *MemType = AI->getType();
16719 // If the operand is too big, we must see if cmpxchg8/16b is available
16720 // and default to library calls otherwise.
16721 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
16722 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
16723 : AtomicRMWExpansionKind::None;
16726 AtomicRMWInst::BinOp Op = AI->getOperation();
16729 llvm_unreachable("Unknown atomic operation");
16730 case AtomicRMWInst::Xchg:
16731 case AtomicRMWInst::Add:
16732 case AtomicRMWInst::Sub:
16733 // It's better to use xadd, xsub or xchg for these in all cases.
16734 return AtomicRMWExpansionKind::None;
16735 case AtomicRMWInst::Or:
16736 case AtomicRMWInst::And:
16737 case AtomicRMWInst::Xor:
16738 // If the atomicrmw's result isn't actually used, we can just add a "lock"
16739 // prefix to a normal instruction for these operations.
16740 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
16741 : AtomicRMWExpansionKind::None;
16742 case AtomicRMWInst::Nand:
16743 case AtomicRMWInst::Max:
16744 case AtomicRMWInst::Min:
16745 case AtomicRMWInst::UMax:
16746 case AtomicRMWInst::UMin:
16747 // These always require a non-trivial set of data operations on x86. We must
16748 // use a cmpxchg loop.
16749 return AtomicRMWExpansionKind::CmpXChg;
16753 static bool hasMFENCE(const X86Subtarget& Subtarget) {
16754 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16755 // no-sse2). There isn't any reason to disable it if the target processor
16757 return Subtarget.hasSSE2() || Subtarget.is64Bit();
16761 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
16762 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16763 const Type *MemType = AI->getType();
16764 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
16765 // there is no benefit in turning such RMWs into loads, and it is actually
16766 // harmful as it introduces a mfence.
16767 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16770 auto Builder = IRBuilder<>(AI);
16771 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
16772 auto SynchScope = AI->getSynchScope();
16773 // We must restrict the ordering to avoid generating loads with Release or
16774 // ReleaseAcquire orderings.
16775 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
16776 auto Ptr = AI->getPointerOperand();
16778 // Before the load we need a fence. Here is an example lifted from
16779 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
16782 // x.store(1, relaxed);
16783 // r1 = y.fetch_add(0, release);
16785 // y.fetch_add(42, acquire);
16786 // r2 = x.load(relaxed);
16787 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
16788 // lowered to just a load without a fence. A mfence flushes the store buffer,
16789 // making the optimization clearly correct.
16790 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
16791 // otherwise, we might be able to be more agressive on relaxed idempotent
16792 // rmw. In practice, they do not look useful, so we don't try to be
16793 // especially clever.
16794 if (SynchScope == SingleThread) {
16795 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
16796 // the IR level, so we must wrap it in an intrinsic.
16798 } else if (hasMFENCE(*Subtarget)) {
16799 Function *MFence = llvm::Intrinsic::getDeclaration(M,
16800 Intrinsic::x86_sse2_mfence);
16801 Builder.CreateCall(MFence);
16803 // FIXME: it might make sense to use a locked operation here but on a
16804 // different cache-line to prevent cache-line bouncing. In practice it
16805 // is probably a small win, and x86 processors without mfence are rare
16806 // enough that we do not bother.
16810 // Finally we can emit the atomic load.
16811 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
16812 AI->getType()->getPrimitiveSizeInBits());
16813 Loaded->setAtomic(Order, SynchScope);
16814 AI->replaceAllUsesWith(Loaded);
16815 AI->eraseFromParent();
16819 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16820 SelectionDAG &DAG) {
16822 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16823 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16824 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16825 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16827 // The only fence that needs an instruction is a sequentially-consistent
16828 // cross-thread fence.
16829 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16830 if (hasMFENCE(*Subtarget))
16831 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16833 SDValue Chain = Op.getOperand(0);
16834 SDValue Zero = DAG.getConstant(0, MVT::i32);
16836 DAG.getRegister(X86::ESP, MVT::i32), // Base
16837 DAG.getTargetConstant(1, MVT::i8), // Scale
16838 DAG.getRegister(0, MVT::i32), // Index
16839 DAG.getTargetConstant(0, MVT::i32), // Disp
16840 DAG.getRegister(0, MVT::i32), // Segment.
16844 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16845 return SDValue(Res, 0);
16848 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16849 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16852 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16853 SelectionDAG &DAG) {
16854 MVT T = Op.getSimpleValueType();
16858 switch(T.SimpleTy) {
16859 default: llvm_unreachable("Invalid value type!");
16860 case MVT::i8: Reg = X86::AL; size = 1; break;
16861 case MVT::i16: Reg = X86::AX; size = 2; break;
16862 case MVT::i32: Reg = X86::EAX; size = 4; break;
16864 assert(Subtarget->is64Bit() && "Node not type legal!");
16865 Reg = X86::RAX; size = 8;
16868 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16869 Op.getOperand(2), SDValue());
16870 SDValue Ops[] = { cpIn.getValue(0),
16873 DAG.getTargetConstant(size, MVT::i8),
16874 cpIn.getValue(1) };
16875 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16876 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16877 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16881 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16882 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16883 MVT::i32, cpOut.getValue(2));
16884 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16885 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16887 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16888 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16889 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16893 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16894 SelectionDAG &DAG) {
16895 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16896 MVT DstVT = Op.getSimpleValueType();
16898 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16899 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16900 if (DstVT != MVT::f64)
16901 // This conversion needs to be expanded.
16904 SDValue InVec = Op->getOperand(0);
16906 unsigned NumElts = SrcVT.getVectorNumElements();
16907 EVT SVT = SrcVT.getVectorElementType();
16909 // Widen the vector in input in the case of MVT::v2i32.
16910 // Example: from MVT::v2i32 to MVT::v4i32.
16911 SmallVector<SDValue, 16> Elts;
16912 for (unsigned i = 0, e = NumElts; i != e; ++i)
16913 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16914 DAG.getIntPtrConstant(i)));
16916 // Explicitly mark the extra elements as Undef.
16917 Elts.append(NumElts, DAG.getUNDEF(SVT));
16919 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16920 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16921 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16922 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16923 DAG.getIntPtrConstant(0));
16926 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16927 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16928 assert((DstVT == MVT::i64 ||
16929 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16930 "Unexpected custom BITCAST");
16931 // i64 <=> MMX conversions are Legal.
16932 if (SrcVT==MVT::i64 && DstVT.isVector())
16934 if (DstVT==MVT::i64 && SrcVT.isVector())
16936 // MMX <=> MMX conversions are Legal.
16937 if (SrcVT.isVector() && DstVT.isVector())
16939 // All other conversions need to be expanded.
16943 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
16944 SelectionDAG &DAG) {
16945 SDNode *Node = Op.getNode();
16948 Op = Op.getOperand(0);
16949 EVT VT = Op.getValueType();
16950 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16951 "CTPOP lowering only implemented for 128/256-bit wide vector types");
16953 unsigned NumElts = VT.getVectorNumElements();
16954 EVT EltVT = VT.getVectorElementType();
16955 unsigned Len = EltVT.getSizeInBits();
16957 // This is the vectorized version of the "best" algorithm from
16958 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
16959 // with a minor tweak to use a series of adds + shifts instead of vector
16960 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
16962 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
16963 // v8i32 => Always profitable
16965 // FIXME: There a couple of possible improvements:
16967 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
16968 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
16970 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
16971 "CTPOP not implemented for this vector element type.");
16973 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
16974 // extra legalization.
16975 bool NeedsBitcast = EltVT == MVT::i32;
16976 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
16978 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
16979 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
16980 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
16982 // v = v - ((v >> 1) & 0x55555555...)
16983 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
16984 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
16985 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
16987 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
16989 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
16990 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
16992 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
16994 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
16995 if (VT != And.getValueType())
16996 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
16997 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
16999 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17000 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
17001 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
17002 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
17003 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
17005 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
17006 if (NeedsBitcast) {
17007 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17008 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
17009 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
17012 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
17013 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
17014 if (VT != AndRHS.getValueType()) {
17015 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
17016 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
17018 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
17020 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17021 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
17022 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
17023 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
17024 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17026 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
17027 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
17028 if (NeedsBitcast) {
17029 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17030 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
17032 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
17033 if (VT != And.getValueType())
17034 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17036 // The algorithm mentioned above uses:
17037 // v = (v * 0x01010101...) >> (Len - 8)
17039 // Change it to use vector adds + vector shifts which yield faster results on
17040 // Haswell than using vector integer multiplication.
17042 // For i32 elements:
17043 // v = v + (v >> 8)
17044 // v = v + (v >> 16)
17046 // For i64 elements:
17047 // v = v + (v >> 8)
17048 // v = v + (v >> 16)
17049 // v = v + (v >> 32)
17052 SmallVector<SDValue, 8> Csts;
17053 for (unsigned i = 8; i <= Len/2; i *= 2) {
17054 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
17055 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
17056 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
17057 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17061 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
17062 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
17063 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
17064 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
17065 if (NeedsBitcast) {
17066 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17067 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
17069 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
17070 if (VT != And.getValueType())
17071 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17076 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17077 SDNode *Node = Op.getNode();
17079 EVT T = Node->getValueType(0);
17080 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17081 DAG.getConstant(0, T), Node->getOperand(2));
17082 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17083 cast<AtomicSDNode>(Node)->getMemoryVT(),
17084 Node->getOperand(0),
17085 Node->getOperand(1), negOp,
17086 cast<AtomicSDNode>(Node)->getMemOperand(),
17087 cast<AtomicSDNode>(Node)->getOrdering(),
17088 cast<AtomicSDNode>(Node)->getSynchScope());
17091 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17092 SDNode *Node = Op.getNode();
17094 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17096 // Convert seq_cst store -> xchg
17097 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17098 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17099 // (The only way to get a 16-byte store is cmpxchg16b)
17100 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17101 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17102 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17103 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17104 cast<AtomicSDNode>(Node)->getMemoryVT(),
17105 Node->getOperand(0),
17106 Node->getOperand(1), Node->getOperand(2),
17107 cast<AtomicSDNode>(Node)->getMemOperand(),
17108 cast<AtomicSDNode>(Node)->getOrdering(),
17109 cast<AtomicSDNode>(Node)->getSynchScope());
17110 return Swap.getValue(1);
17112 // Other atomic stores have a simple pattern.
17116 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17117 EVT VT = Op.getNode()->getSimpleValueType(0);
17119 // Let legalize expand this if it isn't a legal type yet.
17120 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17123 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17126 bool ExtraOp = false;
17127 switch (Op.getOpcode()) {
17128 default: llvm_unreachable("Invalid code");
17129 case ISD::ADDC: Opc = X86ISD::ADD; break;
17130 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17131 case ISD::SUBC: Opc = X86ISD::SUB; break;
17132 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17136 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17138 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17139 Op.getOperand(1), Op.getOperand(2));
17142 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17143 SelectionDAG &DAG) {
17144 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17146 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17147 // which returns the values as { float, float } (in XMM0) or
17148 // { double, double } (which is returned in XMM0, XMM1).
17150 SDValue Arg = Op.getOperand(0);
17151 EVT ArgVT = Arg.getValueType();
17152 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17154 TargetLowering::ArgListTy Args;
17155 TargetLowering::ArgListEntry Entry;
17159 Entry.isSExt = false;
17160 Entry.isZExt = false;
17161 Args.push_back(Entry);
17163 bool isF64 = ArgVT == MVT::f64;
17164 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17165 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17166 // the results are returned via SRet in memory.
17167 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17168 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17169 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17171 Type *RetTy = isF64
17172 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17173 : (Type*)VectorType::get(ArgTy, 4);
17175 TargetLowering::CallLoweringInfo CLI(DAG);
17176 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17177 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17179 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17182 // Returned in xmm0 and xmm1.
17183 return CallResult.first;
17185 // Returned in bits 0:31 and 32:64 xmm0.
17186 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17187 CallResult.first, DAG.getIntPtrConstant(0));
17188 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17189 CallResult.first, DAG.getIntPtrConstant(1));
17190 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17191 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17194 /// LowerOperation - Provide custom lowering hooks for some operations.
17196 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17197 switch (Op.getOpcode()) {
17198 default: llvm_unreachable("Should not custom lower this!");
17199 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17200 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17201 return LowerCMP_SWAP(Op, Subtarget, DAG);
17202 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17203 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17204 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17205 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17206 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17207 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17208 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17209 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17210 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17211 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17212 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17213 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17214 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17215 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17216 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17217 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17218 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17219 case ISD::SHL_PARTS:
17220 case ISD::SRA_PARTS:
17221 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17222 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17223 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17224 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17225 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17226 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17227 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17228 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17229 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17230 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17231 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17233 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17234 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17235 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17236 case ISD::SETCC: return LowerSETCC(Op, DAG);
17237 case ISD::SELECT: return LowerSELECT(Op, DAG);
17238 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17239 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17240 case ISD::VASTART: return LowerVASTART(Op, DAG);
17241 case ISD::VAARG: return LowerVAARG(Op, DAG);
17242 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17243 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17244 case ISD::INTRINSIC_VOID:
17245 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17246 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17247 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17248 case ISD::FRAME_TO_ARGS_OFFSET:
17249 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17250 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17251 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17252 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17253 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17254 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17255 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17256 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17257 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17258 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17259 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17260 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17261 case ISD::UMUL_LOHI:
17262 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17265 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17271 case ISD::UMULO: return LowerXALUO(Op, DAG);
17272 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17273 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17277 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17278 case ISD::ADD: return LowerADD(Op, DAG);
17279 case ISD::SUB: return LowerSUB(Op, DAG);
17280 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17284 /// ReplaceNodeResults - Replace a node with an illegal result type
17285 /// with a new node built out of custom code.
17286 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17287 SmallVectorImpl<SDValue>&Results,
17288 SelectionDAG &DAG) const {
17290 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17291 switch (N->getOpcode()) {
17293 llvm_unreachable("Do not know how to custom type legalize this operation!");
17294 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17295 case X86ISD::FMINC:
17297 case X86ISD::FMAXC:
17298 case X86ISD::FMAX: {
17299 EVT VT = N->getValueType(0);
17300 if (VT != MVT::v2f32)
17301 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17302 SDValue UNDEF = DAG.getUNDEF(VT);
17303 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17304 N->getOperand(0), UNDEF);
17305 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17306 N->getOperand(1), UNDEF);
17307 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17310 case ISD::SIGN_EXTEND_INREG:
17315 // We don't want to expand or promote these.
17322 case ISD::UDIVREM: {
17323 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17324 Results.push_back(V);
17327 case ISD::FP_TO_SINT:
17328 case ISD::FP_TO_UINT: {
17329 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17331 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17334 std::pair<SDValue,SDValue> Vals =
17335 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17336 SDValue FIST = Vals.first, StackSlot = Vals.second;
17337 if (FIST.getNode()) {
17338 EVT VT = N->getValueType(0);
17339 // Return a load from the stack slot.
17340 if (StackSlot.getNode())
17341 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17342 MachinePointerInfo(),
17343 false, false, false, 0));
17345 Results.push_back(FIST);
17349 case ISD::UINT_TO_FP: {
17350 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17351 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17352 N->getValueType(0) != MVT::v2f32)
17354 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17356 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17358 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17359 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17360 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17361 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17362 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17363 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17366 case ISD::FP_ROUND: {
17367 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17369 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17370 Results.push_back(V);
17373 case ISD::INTRINSIC_W_CHAIN: {
17374 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17376 default : llvm_unreachable("Do not know how to custom type "
17377 "legalize this intrinsic operation!");
17378 case Intrinsic::x86_rdtsc:
17379 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17381 case Intrinsic::x86_rdtscp:
17382 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17384 case Intrinsic::x86_rdpmc:
17385 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17388 case ISD::READCYCLECOUNTER: {
17389 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17392 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17393 EVT T = N->getValueType(0);
17394 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17395 bool Regs64bit = T == MVT::i128;
17396 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17397 SDValue cpInL, cpInH;
17398 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17399 DAG.getConstant(0, HalfT));
17400 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17401 DAG.getConstant(1, HalfT));
17402 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17403 Regs64bit ? X86::RAX : X86::EAX,
17405 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17406 Regs64bit ? X86::RDX : X86::EDX,
17407 cpInH, cpInL.getValue(1));
17408 SDValue swapInL, swapInH;
17409 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17410 DAG.getConstant(0, HalfT));
17411 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17412 DAG.getConstant(1, HalfT));
17413 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17414 Regs64bit ? X86::RBX : X86::EBX,
17415 swapInL, cpInH.getValue(1));
17416 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17417 Regs64bit ? X86::RCX : X86::ECX,
17418 swapInH, swapInL.getValue(1));
17419 SDValue Ops[] = { swapInH.getValue(0),
17421 swapInH.getValue(1) };
17422 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17423 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17424 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17425 X86ISD::LCMPXCHG8_DAG;
17426 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17427 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17428 Regs64bit ? X86::RAX : X86::EAX,
17429 HalfT, Result.getValue(1));
17430 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17431 Regs64bit ? X86::RDX : X86::EDX,
17432 HalfT, cpOutL.getValue(2));
17433 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17435 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17436 MVT::i32, cpOutH.getValue(2));
17438 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17439 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17440 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17442 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17443 Results.push_back(Success);
17444 Results.push_back(EFLAGS.getValue(1));
17447 case ISD::ATOMIC_SWAP:
17448 case ISD::ATOMIC_LOAD_ADD:
17449 case ISD::ATOMIC_LOAD_SUB:
17450 case ISD::ATOMIC_LOAD_AND:
17451 case ISD::ATOMIC_LOAD_OR:
17452 case ISD::ATOMIC_LOAD_XOR:
17453 case ISD::ATOMIC_LOAD_NAND:
17454 case ISD::ATOMIC_LOAD_MIN:
17455 case ISD::ATOMIC_LOAD_MAX:
17456 case ISD::ATOMIC_LOAD_UMIN:
17457 case ISD::ATOMIC_LOAD_UMAX:
17458 case ISD::ATOMIC_LOAD: {
17459 // Delegate to generic TypeLegalization. Situations we can really handle
17460 // should have already been dealt with by AtomicExpandPass.cpp.
17463 case ISD::BITCAST: {
17464 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17465 EVT DstVT = N->getValueType(0);
17466 EVT SrcVT = N->getOperand(0)->getValueType(0);
17468 if (SrcVT != MVT::f64 ||
17469 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17472 unsigned NumElts = DstVT.getVectorNumElements();
17473 EVT SVT = DstVT.getVectorElementType();
17474 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17475 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17476 MVT::v2f64, N->getOperand(0));
17477 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17479 if (ExperimentalVectorWideningLegalization) {
17480 // If we are legalizing vectors by widening, we already have the desired
17481 // legal vector type, just return it.
17482 Results.push_back(ToVecInt);
17486 SmallVector<SDValue, 8> Elts;
17487 for (unsigned i = 0, e = NumElts; i != e; ++i)
17488 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17489 ToVecInt, DAG.getIntPtrConstant(i)));
17491 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17496 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17498 default: return nullptr;
17499 case X86ISD::BSF: return "X86ISD::BSF";
17500 case X86ISD::BSR: return "X86ISD::BSR";
17501 case X86ISD::SHLD: return "X86ISD::SHLD";
17502 case X86ISD::SHRD: return "X86ISD::SHRD";
17503 case X86ISD::FAND: return "X86ISD::FAND";
17504 case X86ISD::FANDN: return "X86ISD::FANDN";
17505 case X86ISD::FOR: return "X86ISD::FOR";
17506 case X86ISD::FXOR: return "X86ISD::FXOR";
17507 case X86ISD::FSRL: return "X86ISD::FSRL";
17508 case X86ISD::FILD: return "X86ISD::FILD";
17509 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17510 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17511 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17512 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17513 case X86ISD::FLD: return "X86ISD::FLD";
17514 case X86ISD::FST: return "X86ISD::FST";
17515 case X86ISD::CALL: return "X86ISD::CALL";
17516 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17517 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17518 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17519 case X86ISD::BT: return "X86ISD::BT";
17520 case X86ISD::CMP: return "X86ISD::CMP";
17521 case X86ISD::COMI: return "X86ISD::COMI";
17522 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17523 case X86ISD::CMPM: return "X86ISD::CMPM";
17524 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17525 case X86ISD::SETCC: return "X86ISD::SETCC";
17526 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17527 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17528 case X86ISD::CMOV: return "X86ISD::CMOV";
17529 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17530 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17531 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17532 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17533 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17534 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17535 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17536 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17537 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17538 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17539 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17540 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17541 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17542 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17543 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17544 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17545 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
17546 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17547 case X86ISD::HADD: return "X86ISD::HADD";
17548 case X86ISD::HSUB: return "X86ISD::HSUB";
17549 case X86ISD::FHADD: return "X86ISD::FHADD";
17550 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17551 case X86ISD::UMAX: return "X86ISD::UMAX";
17552 case X86ISD::UMIN: return "X86ISD::UMIN";
17553 case X86ISD::SMAX: return "X86ISD::SMAX";
17554 case X86ISD::SMIN: return "X86ISD::SMIN";
17555 case X86ISD::FMAX: return "X86ISD::FMAX";
17556 case X86ISD::FMIN: return "X86ISD::FMIN";
17557 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17558 case X86ISD::FMINC: return "X86ISD::FMINC";
17559 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17560 case X86ISD::FRCP: return "X86ISD::FRCP";
17561 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17562 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17563 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17564 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17565 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17566 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17567 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17568 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17569 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17570 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17571 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17572 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17573 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17574 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17575 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17576 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17577 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17578 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17579 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17580 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17581 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17582 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17583 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17584 case X86ISD::VSHL: return "X86ISD::VSHL";
17585 case X86ISD::VSRL: return "X86ISD::VSRL";
17586 case X86ISD::VSRA: return "X86ISD::VSRA";
17587 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17588 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17589 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17590 case X86ISD::CMPP: return "X86ISD::CMPP";
17591 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17592 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17593 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17594 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17595 case X86ISD::ADD: return "X86ISD::ADD";
17596 case X86ISD::SUB: return "X86ISD::SUB";
17597 case X86ISD::ADC: return "X86ISD::ADC";
17598 case X86ISD::SBB: return "X86ISD::SBB";
17599 case X86ISD::SMUL: return "X86ISD::SMUL";
17600 case X86ISD::UMUL: return "X86ISD::UMUL";
17601 case X86ISD::SMUL8: return "X86ISD::SMUL8";
17602 case X86ISD::UMUL8: return "X86ISD::UMUL8";
17603 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
17604 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
17605 case X86ISD::INC: return "X86ISD::INC";
17606 case X86ISD::DEC: return "X86ISD::DEC";
17607 case X86ISD::OR: return "X86ISD::OR";
17608 case X86ISD::XOR: return "X86ISD::XOR";
17609 case X86ISD::AND: return "X86ISD::AND";
17610 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17611 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17612 case X86ISD::PTEST: return "X86ISD::PTEST";
17613 case X86ISD::TESTP: return "X86ISD::TESTP";
17614 case X86ISD::TESTM: return "X86ISD::TESTM";
17615 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17616 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17617 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17618 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17619 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17620 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17621 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17622 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17623 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17624 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17625 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17626 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17627 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17628 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17629 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17630 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17631 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17632 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17633 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17634 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17635 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17636 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17637 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17638 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17639 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17640 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
17641 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17642 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17643 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17644 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17645 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17646 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17647 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17648 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17649 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17650 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17651 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17652 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17653 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17654 case X86ISD::SAHF: return "X86ISD::SAHF";
17655 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17656 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17657 case X86ISD::FMADD: return "X86ISD::FMADD";
17658 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17659 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17660 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17661 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17662 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17663 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17664 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17665 case X86ISD::XTEST: return "X86ISD::XTEST";
17666 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
17667 case X86ISD::EXPAND: return "X86ISD::EXPAND";
17668 case X86ISD::SELECT: return "X86ISD::SELECT";
17669 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
17670 case X86ISD::RCP28: return "X86ISD::RCP28";
17671 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
17672 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
17673 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
17674 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
17675 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
17679 // isLegalAddressingMode - Return true if the addressing mode represented
17680 // by AM is legal for this target, for a load/store of the specified type.
17681 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17683 // X86 supports extremely general addressing modes.
17684 CodeModel::Model M = getTargetMachine().getCodeModel();
17685 Reloc::Model R = getTargetMachine().getRelocationModel();
17687 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17688 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17693 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17695 // If a reference to this global requires an extra load, we can't fold it.
17696 if (isGlobalStubReference(GVFlags))
17699 // If BaseGV requires a register for the PIC base, we cannot also have a
17700 // BaseReg specified.
17701 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17704 // If lower 4G is not available, then we must use rip-relative addressing.
17705 if ((M != CodeModel::Small || R != Reloc::Static) &&
17706 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17710 switch (AM.Scale) {
17716 // These scales always work.
17721 // These scales are formed with basereg+scalereg. Only accept if there is
17726 default: // Other stuff never works.
17733 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17734 unsigned Bits = Ty->getScalarSizeInBits();
17736 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17737 // particularly cheaper than those without.
17741 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17742 // variable shifts just as cheap as scalar ones.
17743 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17746 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17747 // fully general vector.
17751 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17752 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17754 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17755 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17756 return NumBits1 > NumBits2;
17759 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17760 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17763 if (!isTypeLegal(EVT::getEVT(Ty1)))
17766 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17768 // Assuming the caller doesn't have a zeroext or signext return parameter,
17769 // truncation all the way down to i1 is valid.
17773 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17774 return isInt<32>(Imm);
17777 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17778 // Can also use sub to handle negated immediates.
17779 return isInt<32>(Imm);
17782 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17783 if (!VT1.isInteger() || !VT2.isInteger())
17785 unsigned NumBits1 = VT1.getSizeInBits();
17786 unsigned NumBits2 = VT2.getSizeInBits();
17787 return NumBits1 > NumBits2;
17790 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17791 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17792 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17795 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17796 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17797 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17800 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17801 EVT VT1 = Val.getValueType();
17802 if (isZExtFree(VT1, VT2))
17805 if (Val.getOpcode() != ISD::LOAD)
17808 if (!VT1.isSimple() || !VT1.isInteger() ||
17809 !VT2.isSimple() || !VT2.isInteger())
17812 switch (VT1.getSimpleVT().SimpleTy) {
17817 // X86 has 8, 16, and 32-bit zero-extending loads.
17824 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
17827 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17828 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17831 VT = VT.getScalarType();
17833 if (!VT.isSimple())
17836 switch (VT.getSimpleVT().SimpleTy) {
17847 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17848 // i16 instructions are longer (0x66 prefix) and potentially slower.
17849 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17852 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17853 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17854 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17855 /// are assumed to be legal.
17857 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17859 if (!VT.isSimple())
17862 // Very little shuffling can be done for 64-bit vectors right now.
17863 if (VT.getSizeInBits() == 64)
17866 // We only care that the types being shuffled are legal. The lowering can
17867 // handle any possible shuffle mask that results.
17868 return isTypeLegal(VT.getSimpleVT());
17872 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17874 // Just delegate to the generic legality, clear masks aren't special.
17875 return isShuffleMaskLegal(Mask, VT);
17878 //===----------------------------------------------------------------------===//
17879 // X86 Scheduler Hooks
17880 //===----------------------------------------------------------------------===//
17882 /// Utility function to emit xbegin specifying the start of an RTM region.
17883 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17884 const TargetInstrInfo *TII) {
17885 DebugLoc DL = MI->getDebugLoc();
17887 const BasicBlock *BB = MBB->getBasicBlock();
17888 MachineFunction::iterator I = MBB;
17891 // For the v = xbegin(), we generate
17902 MachineBasicBlock *thisMBB = MBB;
17903 MachineFunction *MF = MBB->getParent();
17904 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17905 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17906 MF->insert(I, mainMBB);
17907 MF->insert(I, sinkMBB);
17909 // Transfer the remainder of BB and its successor edges to sinkMBB.
17910 sinkMBB->splice(sinkMBB->begin(), MBB,
17911 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17912 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17916 // # fallthrough to mainMBB
17917 // # abortion to sinkMBB
17918 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17919 thisMBB->addSuccessor(mainMBB);
17920 thisMBB->addSuccessor(sinkMBB);
17924 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17925 mainMBB->addSuccessor(sinkMBB);
17928 // EAX is live into the sinkMBB
17929 sinkMBB->addLiveIn(X86::EAX);
17930 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17931 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17934 MI->eraseFromParent();
17938 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17939 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17940 // in the .td file.
17941 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17942 const TargetInstrInfo *TII) {
17944 switch (MI->getOpcode()) {
17945 default: llvm_unreachable("illegal opcode!");
17946 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17947 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17948 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17949 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17950 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17951 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17952 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17953 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17956 DebugLoc dl = MI->getDebugLoc();
17957 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17959 unsigned NumArgs = MI->getNumOperands();
17960 for (unsigned i = 1; i < NumArgs; ++i) {
17961 MachineOperand &Op = MI->getOperand(i);
17962 if (!(Op.isReg() && Op.isImplicit()))
17963 MIB.addOperand(Op);
17965 if (MI->hasOneMemOperand())
17966 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17968 BuildMI(*BB, MI, dl,
17969 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17970 .addReg(X86::XMM0);
17972 MI->eraseFromParent();
17976 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17977 // defs in an instruction pattern
17978 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17979 const TargetInstrInfo *TII) {
17981 switch (MI->getOpcode()) {
17982 default: llvm_unreachable("illegal opcode!");
17983 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17984 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17985 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17986 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17987 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17988 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17989 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17990 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17993 DebugLoc dl = MI->getDebugLoc();
17994 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17996 unsigned NumArgs = MI->getNumOperands(); // remove the results
17997 for (unsigned i = 1; i < NumArgs; ++i) {
17998 MachineOperand &Op = MI->getOperand(i);
17999 if (!(Op.isReg() && Op.isImplicit()))
18000 MIB.addOperand(Op);
18002 if (MI->hasOneMemOperand())
18003 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18005 BuildMI(*BB, MI, dl,
18006 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18009 MI->eraseFromParent();
18013 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18014 const X86Subtarget *Subtarget) {
18015 DebugLoc dl = MI->getDebugLoc();
18016 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18017 // Address into RAX/EAX, other two args into ECX, EDX.
18018 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18019 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18020 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18021 for (int i = 0; i < X86::AddrNumOperands; ++i)
18022 MIB.addOperand(MI->getOperand(i));
18024 unsigned ValOps = X86::AddrNumOperands;
18025 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18026 .addReg(MI->getOperand(ValOps).getReg());
18027 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18028 .addReg(MI->getOperand(ValOps+1).getReg());
18030 // The instruction doesn't actually take any operands though.
18031 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18033 MI->eraseFromParent(); // The pseudo is gone now.
18037 MachineBasicBlock *
18038 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18039 MachineBasicBlock *MBB) const {
18040 // Emit va_arg instruction on X86-64.
18042 // Operands to this pseudo-instruction:
18043 // 0 ) Output : destination address (reg)
18044 // 1-5) Input : va_list address (addr, i64mem)
18045 // 6 ) ArgSize : Size (in bytes) of vararg type
18046 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18047 // 8 ) Align : Alignment of type
18048 // 9 ) EFLAGS (implicit-def)
18050 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18051 static_assert(X86::AddrNumOperands == 5,
18052 "VAARG_64 assumes 5 address operands");
18054 unsigned DestReg = MI->getOperand(0).getReg();
18055 MachineOperand &Base = MI->getOperand(1);
18056 MachineOperand &Scale = MI->getOperand(2);
18057 MachineOperand &Index = MI->getOperand(3);
18058 MachineOperand &Disp = MI->getOperand(4);
18059 MachineOperand &Segment = MI->getOperand(5);
18060 unsigned ArgSize = MI->getOperand(6).getImm();
18061 unsigned ArgMode = MI->getOperand(7).getImm();
18062 unsigned Align = MI->getOperand(8).getImm();
18064 // Memory Reference
18065 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18066 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18067 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18069 // Machine Information
18070 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18071 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18072 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18073 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18074 DebugLoc DL = MI->getDebugLoc();
18076 // struct va_list {
18079 // i64 overflow_area (address)
18080 // i64 reg_save_area (address)
18082 // sizeof(va_list) = 24
18083 // alignment(va_list) = 8
18085 unsigned TotalNumIntRegs = 6;
18086 unsigned TotalNumXMMRegs = 8;
18087 bool UseGPOffset = (ArgMode == 1);
18088 bool UseFPOffset = (ArgMode == 2);
18089 unsigned MaxOffset = TotalNumIntRegs * 8 +
18090 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18092 /* Align ArgSize to a multiple of 8 */
18093 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18094 bool NeedsAlign = (Align > 8);
18096 MachineBasicBlock *thisMBB = MBB;
18097 MachineBasicBlock *overflowMBB;
18098 MachineBasicBlock *offsetMBB;
18099 MachineBasicBlock *endMBB;
18101 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18102 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18103 unsigned OffsetReg = 0;
18105 if (!UseGPOffset && !UseFPOffset) {
18106 // If we only pull from the overflow region, we don't create a branch.
18107 // We don't need to alter control flow.
18108 OffsetDestReg = 0; // unused
18109 OverflowDestReg = DestReg;
18111 offsetMBB = nullptr;
18112 overflowMBB = thisMBB;
18115 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18116 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18117 // If not, pull from overflow_area. (branch to overflowMBB)
18122 // offsetMBB overflowMBB
18127 // Registers for the PHI in endMBB
18128 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18129 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18131 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18132 MachineFunction *MF = MBB->getParent();
18133 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18134 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18135 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18137 MachineFunction::iterator MBBIter = MBB;
18140 // Insert the new basic blocks
18141 MF->insert(MBBIter, offsetMBB);
18142 MF->insert(MBBIter, overflowMBB);
18143 MF->insert(MBBIter, endMBB);
18145 // Transfer the remainder of MBB and its successor edges to endMBB.
18146 endMBB->splice(endMBB->begin(), thisMBB,
18147 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18148 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18150 // Make offsetMBB and overflowMBB successors of thisMBB
18151 thisMBB->addSuccessor(offsetMBB);
18152 thisMBB->addSuccessor(overflowMBB);
18154 // endMBB is a successor of both offsetMBB and overflowMBB
18155 offsetMBB->addSuccessor(endMBB);
18156 overflowMBB->addSuccessor(endMBB);
18158 // Load the offset value into a register
18159 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18160 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18164 .addDisp(Disp, UseFPOffset ? 4 : 0)
18165 .addOperand(Segment)
18166 .setMemRefs(MMOBegin, MMOEnd);
18168 // Check if there is enough room left to pull this argument.
18169 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18171 .addImm(MaxOffset + 8 - ArgSizeA8);
18173 // Branch to "overflowMBB" if offset >= max
18174 // Fall through to "offsetMBB" otherwise
18175 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18176 .addMBB(overflowMBB);
18179 // In offsetMBB, emit code to use the reg_save_area.
18181 assert(OffsetReg != 0);
18183 // Read the reg_save_area address.
18184 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18185 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18190 .addOperand(Segment)
18191 .setMemRefs(MMOBegin, MMOEnd);
18193 // Zero-extend the offset
18194 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18195 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18198 .addImm(X86::sub_32bit);
18200 // Add the offset to the reg_save_area to get the final address.
18201 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18202 .addReg(OffsetReg64)
18203 .addReg(RegSaveReg);
18205 // Compute the offset for the next argument
18206 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18207 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18209 .addImm(UseFPOffset ? 16 : 8);
18211 // Store it back into the va_list.
18212 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18216 .addDisp(Disp, UseFPOffset ? 4 : 0)
18217 .addOperand(Segment)
18218 .addReg(NextOffsetReg)
18219 .setMemRefs(MMOBegin, MMOEnd);
18222 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18227 // Emit code to use overflow area
18230 // Load the overflow_area address into a register.
18231 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18232 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18237 .addOperand(Segment)
18238 .setMemRefs(MMOBegin, MMOEnd);
18240 // If we need to align it, do so. Otherwise, just copy the address
18241 // to OverflowDestReg.
18243 // Align the overflow address
18244 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18245 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18247 // aligned_addr = (addr + (align-1)) & ~(align-1)
18248 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18249 .addReg(OverflowAddrReg)
18252 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18254 .addImm(~(uint64_t)(Align-1));
18256 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18257 .addReg(OverflowAddrReg);
18260 // Compute the next overflow address after this argument.
18261 // (the overflow address should be kept 8-byte aligned)
18262 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18263 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18264 .addReg(OverflowDestReg)
18265 .addImm(ArgSizeA8);
18267 // Store the new overflow address.
18268 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18273 .addOperand(Segment)
18274 .addReg(NextAddrReg)
18275 .setMemRefs(MMOBegin, MMOEnd);
18277 // If we branched, emit the PHI to the front of endMBB.
18279 BuildMI(*endMBB, endMBB->begin(), DL,
18280 TII->get(X86::PHI), DestReg)
18281 .addReg(OffsetDestReg).addMBB(offsetMBB)
18282 .addReg(OverflowDestReg).addMBB(overflowMBB);
18285 // Erase the pseudo instruction
18286 MI->eraseFromParent();
18291 MachineBasicBlock *
18292 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18294 MachineBasicBlock *MBB) const {
18295 // Emit code to save XMM registers to the stack. The ABI says that the
18296 // number of registers to save is given in %al, so it's theoretically
18297 // possible to do an indirect jump trick to avoid saving all of them,
18298 // however this code takes a simpler approach and just executes all
18299 // of the stores if %al is non-zero. It's less code, and it's probably
18300 // easier on the hardware branch predictor, and stores aren't all that
18301 // expensive anyway.
18303 // Create the new basic blocks. One block contains all the XMM stores,
18304 // and one block is the final destination regardless of whether any
18305 // stores were performed.
18306 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18307 MachineFunction *F = MBB->getParent();
18308 MachineFunction::iterator MBBIter = MBB;
18310 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18311 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18312 F->insert(MBBIter, XMMSaveMBB);
18313 F->insert(MBBIter, EndMBB);
18315 // Transfer the remainder of MBB and its successor edges to EndMBB.
18316 EndMBB->splice(EndMBB->begin(), MBB,
18317 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18318 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18320 // The original block will now fall through to the XMM save block.
18321 MBB->addSuccessor(XMMSaveMBB);
18322 // The XMMSaveMBB will fall through to the end block.
18323 XMMSaveMBB->addSuccessor(EndMBB);
18325 // Now add the instructions.
18326 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18327 DebugLoc DL = MI->getDebugLoc();
18329 unsigned CountReg = MI->getOperand(0).getReg();
18330 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18331 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18333 if (!Subtarget->isTargetWin64()) {
18334 // If %al is 0, branch around the XMM save block.
18335 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18336 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18337 MBB->addSuccessor(EndMBB);
18340 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18341 // that was just emitted, but clearly shouldn't be "saved".
18342 assert((MI->getNumOperands() <= 3 ||
18343 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18344 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18345 && "Expected last argument to be EFLAGS");
18346 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18347 // In the XMM save block, save all the XMM argument registers.
18348 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18349 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18350 MachineMemOperand *MMO =
18351 F->getMachineMemOperand(
18352 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18353 MachineMemOperand::MOStore,
18354 /*Size=*/16, /*Align=*/16);
18355 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18356 .addFrameIndex(RegSaveFrameIndex)
18357 .addImm(/*Scale=*/1)
18358 .addReg(/*IndexReg=*/0)
18359 .addImm(/*Disp=*/Offset)
18360 .addReg(/*Segment=*/0)
18361 .addReg(MI->getOperand(i).getReg())
18362 .addMemOperand(MMO);
18365 MI->eraseFromParent(); // The pseudo instruction is gone now.
18370 // The EFLAGS operand of SelectItr might be missing a kill marker
18371 // because there were multiple uses of EFLAGS, and ISel didn't know
18372 // which to mark. Figure out whether SelectItr should have had a
18373 // kill marker, and set it if it should. Returns the correct kill
18375 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18376 MachineBasicBlock* BB,
18377 const TargetRegisterInfo* TRI) {
18378 // Scan forward through BB for a use/def of EFLAGS.
18379 MachineBasicBlock::iterator miI(std::next(SelectItr));
18380 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18381 const MachineInstr& mi = *miI;
18382 if (mi.readsRegister(X86::EFLAGS))
18384 if (mi.definesRegister(X86::EFLAGS))
18385 break; // Should have kill-flag - update below.
18388 // If we hit the end of the block, check whether EFLAGS is live into a
18390 if (miI == BB->end()) {
18391 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18392 sEnd = BB->succ_end();
18393 sItr != sEnd; ++sItr) {
18394 MachineBasicBlock* succ = *sItr;
18395 if (succ->isLiveIn(X86::EFLAGS))
18400 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18401 // out. SelectMI should have a kill flag on EFLAGS.
18402 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18406 MachineBasicBlock *
18407 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18408 MachineBasicBlock *BB) const {
18409 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18410 DebugLoc DL = MI->getDebugLoc();
18412 // To "insert" a SELECT_CC instruction, we actually have to insert the
18413 // diamond control-flow pattern. The incoming instruction knows the
18414 // destination vreg to set, the condition code register to branch on, the
18415 // true/false values to select between, and a branch opcode to use.
18416 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18417 MachineFunction::iterator It = BB;
18423 // cmpTY ccX, r1, r2
18425 // fallthrough --> copy0MBB
18426 MachineBasicBlock *thisMBB = BB;
18427 MachineFunction *F = BB->getParent();
18429 // We also lower double CMOVs:
18430 // (CMOV (CMOV F, T, cc1), T, cc2)
18431 // to two successives branches. For that, we look for another CMOV as the
18432 // following instruction.
18434 // Without this, we would add a PHI between the two jumps, which ends up
18435 // creating a few copies all around. For instance, for
18437 // (sitofp (zext (fcmp une)))
18439 // we would generate:
18441 // ucomiss %xmm1, %xmm0
18442 // movss <1.0f>, %xmm0
18443 // movaps %xmm0, %xmm1
18445 // xorps %xmm1, %xmm1
18448 // movaps %xmm1, %xmm0
18452 // because this custom-inserter would have generated:
18464 // A: X = ...; Y = ...
18466 // C: Z = PHI [X, A], [Y, B]
18468 // E: PHI [X, C], [Z, D]
18470 // If we lower both CMOVs in a single step, we can instead generate:
18482 // A: X = ...; Y = ...
18484 // E: PHI [X, A], [X, C], [Y, D]
18486 // Which, in our sitofp/fcmp example, gives us something like:
18488 // ucomiss %xmm1, %xmm0
18489 // movss <1.0f>, %xmm0
18492 // xorps %xmm0, %xmm0
18496 MachineInstr *NextCMOV = nullptr;
18497 MachineBasicBlock::iterator NextMIIt =
18498 std::next(MachineBasicBlock::iterator(MI));
18499 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
18500 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
18501 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
18502 NextCMOV = &*NextMIIt;
18504 MachineBasicBlock *jcc1MBB = nullptr;
18506 // If we have a double CMOV, we lower it to two successive branches to
18507 // the same block. EFLAGS is used by both, so mark it as live in the second.
18509 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
18510 F->insert(It, jcc1MBB);
18511 jcc1MBB->addLiveIn(X86::EFLAGS);
18514 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18515 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18516 F->insert(It, copy0MBB);
18517 F->insert(It, sinkMBB);
18519 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18520 // live into the sink and copy blocks.
18521 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
18523 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
18524 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
18525 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
18526 copy0MBB->addLiveIn(X86::EFLAGS);
18527 sinkMBB->addLiveIn(X86::EFLAGS);
18530 // Transfer the remainder of BB and its successor edges to sinkMBB.
18531 sinkMBB->splice(sinkMBB->begin(), BB,
18532 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18533 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18535 // Add the true and fallthrough blocks as its successors.
18537 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
18538 BB->addSuccessor(jcc1MBB);
18540 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
18541 // jump to the sinkMBB.
18542 jcc1MBB->addSuccessor(copy0MBB);
18543 jcc1MBB->addSuccessor(sinkMBB);
18545 BB->addSuccessor(copy0MBB);
18548 // The true block target of the first (or only) branch is always sinkMBB.
18549 BB->addSuccessor(sinkMBB);
18551 // Create the conditional branch instruction.
18553 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18554 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18557 unsigned Opc2 = X86::GetCondBranchFromCond(
18558 (X86::CondCode)NextCMOV->getOperand(3).getImm());
18559 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
18563 // %FalseValue = ...
18564 // # fallthrough to sinkMBB
18565 copy0MBB->addSuccessor(sinkMBB);
18568 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18570 MachineInstrBuilder MIB =
18571 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
18572 MI->getOperand(0).getReg())
18573 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18574 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18576 // If we have a double CMOV, the second Jcc provides the same incoming
18577 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
18579 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
18580 // Copy the PHI result to the register defined by the second CMOV.
18581 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
18582 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
18583 .addReg(MI->getOperand(0).getReg());
18584 NextCMOV->eraseFromParent();
18587 MI->eraseFromParent(); // The pseudo instruction is gone now.
18591 MachineBasicBlock *
18592 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
18593 MachineBasicBlock *BB) const {
18594 MachineFunction *MF = BB->getParent();
18595 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18596 DebugLoc DL = MI->getDebugLoc();
18597 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18599 assert(MF->shouldSplitStack());
18601 const bool Is64Bit = Subtarget->is64Bit();
18602 const bool IsLP64 = Subtarget->isTarget64BitLP64();
18604 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18605 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
18608 // ... [Till the alloca]
18609 // If stacklet is not large enough, jump to mallocMBB
18612 // Allocate by subtracting from RSP
18613 // Jump to continueMBB
18616 // Allocate by call to runtime
18620 // [rest of original BB]
18623 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18624 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18625 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18627 MachineRegisterInfo &MRI = MF->getRegInfo();
18628 const TargetRegisterClass *AddrRegClass =
18629 getRegClassFor(getPointerTy());
18631 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18632 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18633 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18634 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18635 sizeVReg = MI->getOperand(1).getReg(),
18636 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
18638 MachineFunction::iterator MBBIter = BB;
18641 MF->insert(MBBIter, bumpMBB);
18642 MF->insert(MBBIter, mallocMBB);
18643 MF->insert(MBBIter, continueMBB);
18645 continueMBB->splice(continueMBB->begin(), BB,
18646 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18647 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18649 // Add code to the main basic block to check if the stack limit has been hit,
18650 // and if so, jump to mallocMBB otherwise to bumpMBB.
18651 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18652 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18653 .addReg(tmpSPVReg).addReg(sizeVReg);
18654 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
18655 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18656 .addReg(SPLimitVReg);
18657 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
18659 // bumpMBB simply decreases the stack pointer, since we know the current
18660 // stacklet has enough space.
18661 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18662 .addReg(SPLimitVReg);
18663 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18664 .addReg(SPLimitVReg);
18665 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18667 // Calls into a routine in libgcc to allocate more space from the heap.
18668 const uint32_t *RegMask =
18669 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
18671 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18673 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18674 .addExternalSymbol("__morestack_allocate_stack_space")
18675 .addRegMask(RegMask)
18676 .addReg(X86::RDI, RegState::Implicit)
18677 .addReg(X86::RAX, RegState::ImplicitDefine);
18678 } else if (Is64Bit) {
18679 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
18681 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18682 .addExternalSymbol("__morestack_allocate_stack_space")
18683 .addRegMask(RegMask)
18684 .addReg(X86::EDI, RegState::Implicit)
18685 .addReg(X86::EAX, RegState::ImplicitDefine);
18687 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18689 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18690 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18691 .addExternalSymbol("__morestack_allocate_stack_space")
18692 .addRegMask(RegMask)
18693 .addReg(X86::EAX, RegState::ImplicitDefine);
18697 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18700 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18701 .addReg(IsLP64 ? X86::RAX : X86::EAX);
18702 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18704 // Set up the CFG correctly.
18705 BB->addSuccessor(bumpMBB);
18706 BB->addSuccessor(mallocMBB);
18707 mallocMBB->addSuccessor(continueMBB);
18708 bumpMBB->addSuccessor(continueMBB);
18710 // Take care of the PHI nodes.
18711 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18712 MI->getOperand(0).getReg())
18713 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18714 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18716 // Delete the original pseudo instruction.
18717 MI->eraseFromParent();
18720 return continueMBB;
18723 MachineBasicBlock *
18724 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18725 MachineBasicBlock *BB) const {
18726 DebugLoc DL = MI->getDebugLoc();
18728 assert(!Subtarget->isTargetMachO());
18730 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
18732 MI->eraseFromParent(); // The pseudo instruction is gone now.
18736 MachineBasicBlock *
18737 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18738 MachineBasicBlock *BB) const {
18739 // This is pretty easy. We're taking the value that we received from
18740 // our load from the relocation, sticking it in either RDI (x86-64)
18741 // or EAX and doing an indirect call. The return value will then
18742 // be in the normal return register.
18743 MachineFunction *F = BB->getParent();
18744 const X86InstrInfo *TII = Subtarget->getInstrInfo();
18745 DebugLoc DL = MI->getDebugLoc();
18747 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18748 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18750 // Get a register mask for the lowered call.
18751 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18752 // proper register mask.
18753 const uint32_t *RegMask =
18754 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
18755 if (Subtarget->is64Bit()) {
18756 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18757 TII->get(X86::MOV64rm), X86::RDI)
18759 .addImm(0).addReg(0)
18760 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18761 MI->getOperand(3).getTargetFlags())
18763 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18764 addDirectMem(MIB, X86::RDI);
18765 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18766 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18767 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18768 TII->get(X86::MOV32rm), X86::EAX)
18770 .addImm(0).addReg(0)
18771 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18772 MI->getOperand(3).getTargetFlags())
18774 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18775 addDirectMem(MIB, X86::EAX);
18776 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18778 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18779 TII->get(X86::MOV32rm), X86::EAX)
18780 .addReg(TII->getGlobalBaseReg(F))
18781 .addImm(0).addReg(0)
18782 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18783 MI->getOperand(3).getTargetFlags())
18785 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18786 addDirectMem(MIB, X86::EAX);
18787 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18790 MI->eraseFromParent(); // The pseudo instruction is gone now.
18794 MachineBasicBlock *
18795 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18796 MachineBasicBlock *MBB) const {
18797 DebugLoc DL = MI->getDebugLoc();
18798 MachineFunction *MF = MBB->getParent();
18799 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18800 MachineRegisterInfo &MRI = MF->getRegInfo();
18802 const BasicBlock *BB = MBB->getBasicBlock();
18803 MachineFunction::iterator I = MBB;
18806 // Memory Reference
18807 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18808 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18811 unsigned MemOpndSlot = 0;
18813 unsigned CurOp = 0;
18815 DstReg = MI->getOperand(CurOp++).getReg();
18816 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18817 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18818 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18819 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18821 MemOpndSlot = CurOp;
18823 MVT PVT = getPointerTy();
18824 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18825 "Invalid Pointer Size!");
18827 // For v = setjmp(buf), we generate
18830 // buf[LabelOffset] = restoreMBB
18831 // SjLjSetup restoreMBB
18837 // v = phi(main, restore)
18840 // if base pointer being used, load it from frame
18843 MachineBasicBlock *thisMBB = MBB;
18844 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18845 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18846 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18847 MF->insert(I, mainMBB);
18848 MF->insert(I, sinkMBB);
18849 MF->push_back(restoreMBB);
18851 MachineInstrBuilder MIB;
18853 // Transfer the remainder of BB and its successor edges to sinkMBB.
18854 sinkMBB->splice(sinkMBB->begin(), MBB,
18855 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18856 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18859 unsigned PtrStoreOpc = 0;
18860 unsigned LabelReg = 0;
18861 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18862 Reloc::Model RM = MF->getTarget().getRelocationModel();
18863 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18864 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18866 // Prepare IP either in reg or imm.
18867 if (!UseImmLabel) {
18868 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18869 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18870 LabelReg = MRI.createVirtualRegister(PtrRC);
18871 if (Subtarget->is64Bit()) {
18872 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18876 .addMBB(restoreMBB)
18879 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18880 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18881 .addReg(XII->getGlobalBaseReg(MF))
18884 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18888 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18890 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18891 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18892 if (i == X86::AddrDisp)
18893 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18895 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18898 MIB.addReg(LabelReg);
18900 MIB.addMBB(restoreMBB);
18901 MIB.setMemRefs(MMOBegin, MMOEnd);
18903 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18904 .addMBB(restoreMBB);
18906 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18907 MIB.addRegMask(RegInfo->getNoPreservedMask());
18908 thisMBB->addSuccessor(mainMBB);
18909 thisMBB->addSuccessor(restoreMBB);
18913 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18914 mainMBB->addSuccessor(sinkMBB);
18917 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18918 TII->get(X86::PHI), DstReg)
18919 .addReg(mainDstReg).addMBB(mainMBB)
18920 .addReg(restoreDstReg).addMBB(restoreMBB);
18923 if (RegInfo->hasBasePointer(*MF)) {
18924 const bool Uses64BitFramePtr =
18925 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
18926 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
18927 X86FI->setRestoreBasePointer(MF);
18928 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
18929 unsigned BasePtr = RegInfo->getBaseRegister();
18930 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
18931 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
18932 FramePtr, true, X86FI->getRestoreBasePointerOffset())
18933 .setMIFlag(MachineInstr::FrameSetup);
18935 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18936 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
18937 restoreMBB->addSuccessor(sinkMBB);
18939 MI->eraseFromParent();
18943 MachineBasicBlock *
18944 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18945 MachineBasicBlock *MBB) const {
18946 DebugLoc DL = MI->getDebugLoc();
18947 MachineFunction *MF = MBB->getParent();
18948 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18949 MachineRegisterInfo &MRI = MF->getRegInfo();
18951 // Memory Reference
18952 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18953 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18955 MVT PVT = getPointerTy();
18956 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18957 "Invalid Pointer Size!");
18959 const TargetRegisterClass *RC =
18960 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18961 unsigned Tmp = MRI.createVirtualRegister(RC);
18962 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18963 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18964 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18965 unsigned SP = RegInfo->getStackRegister();
18967 MachineInstrBuilder MIB;
18969 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18970 const int64_t SPOffset = 2 * PVT.getStoreSize();
18972 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18973 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18976 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18977 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18978 MIB.addOperand(MI->getOperand(i));
18979 MIB.setMemRefs(MMOBegin, MMOEnd);
18981 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18982 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18983 if (i == X86::AddrDisp)
18984 MIB.addDisp(MI->getOperand(i), LabelOffset);
18986 MIB.addOperand(MI->getOperand(i));
18988 MIB.setMemRefs(MMOBegin, MMOEnd);
18990 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18991 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18992 if (i == X86::AddrDisp)
18993 MIB.addDisp(MI->getOperand(i), SPOffset);
18995 MIB.addOperand(MI->getOperand(i));
18997 MIB.setMemRefs(MMOBegin, MMOEnd);
18999 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19001 MI->eraseFromParent();
19005 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19006 // accumulator loops. Writing back to the accumulator allows the coalescer
19007 // to remove extra copies in the loop.
19008 MachineBasicBlock *
19009 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19010 MachineBasicBlock *MBB) const {
19011 MachineOperand &AddendOp = MI->getOperand(3);
19013 // Bail out early if the addend isn't a register - we can't switch these.
19014 if (!AddendOp.isReg())
19017 MachineFunction &MF = *MBB->getParent();
19018 MachineRegisterInfo &MRI = MF.getRegInfo();
19020 // Check whether the addend is defined by a PHI:
19021 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19022 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19023 if (!AddendDef.isPHI())
19026 // Look for the following pattern:
19028 // %addend = phi [%entry, 0], [%loop, %result]
19030 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19034 // %addend = phi [%entry, 0], [%loop, %result]
19036 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19038 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19039 assert(AddendDef.getOperand(i).isReg());
19040 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19041 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19042 if (&PHISrcInst == MI) {
19043 // Found a matching instruction.
19044 unsigned NewFMAOpc = 0;
19045 switch (MI->getOpcode()) {
19046 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19047 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19048 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19049 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19050 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19051 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19052 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19053 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19054 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19055 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19056 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19057 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19058 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19059 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19060 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19061 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19062 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19063 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19064 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19065 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19067 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19068 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19069 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19070 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19071 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19072 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19073 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19074 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19075 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19076 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19077 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19078 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19079 default: llvm_unreachable("Unrecognized FMA variant.");
19082 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19083 MachineInstrBuilder MIB =
19084 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19085 .addOperand(MI->getOperand(0))
19086 .addOperand(MI->getOperand(3))
19087 .addOperand(MI->getOperand(2))
19088 .addOperand(MI->getOperand(1));
19089 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19090 MI->eraseFromParent();
19097 MachineBasicBlock *
19098 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19099 MachineBasicBlock *BB) const {
19100 switch (MI->getOpcode()) {
19101 default: llvm_unreachable("Unexpected instr type to insert");
19102 case X86::TAILJMPd64:
19103 case X86::TAILJMPr64:
19104 case X86::TAILJMPm64:
19105 case X86::TAILJMPd64_REX:
19106 case X86::TAILJMPr64_REX:
19107 case X86::TAILJMPm64_REX:
19108 llvm_unreachable("TAILJMP64 would not be touched here.");
19109 case X86::TCRETURNdi64:
19110 case X86::TCRETURNri64:
19111 case X86::TCRETURNmi64:
19113 case X86::WIN_ALLOCA:
19114 return EmitLoweredWinAlloca(MI, BB);
19115 case X86::SEG_ALLOCA_32:
19116 case X86::SEG_ALLOCA_64:
19117 return EmitLoweredSegAlloca(MI, BB);
19118 case X86::TLSCall_32:
19119 case X86::TLSCall_64:
19120 return EmitLoweredTLSCall(MI, BB);
19121 case X86::CMOV_GR8:
19122 case X86::CMOV_FR32:
19123 case X86::CMOV_FR64:
19124 case X86::CMOV_V4F32:
19125 case X86::CMOV_V2F64:
19126 case X86::CMOV_V2I64:
19127 case X86::CMOV_V8F32:
19128 case X86::CMOV_V4F64:
19129 case X86::CMOV_V4I64:
19130 case X86::CMOV_V16F32:
19131 case X86::CMOV_V8F64:
19132 case X86::CMOV_V8I64:
19133 case X86::CMOV_GR16:
19134 case X86::CMOV_GR32:
19135 case X86::CMOV_RFP32:
19136 case X86::CMOV_RFP64:
19137 case X86::CMOV_RFP80:
19138 return EmitLoweredSelect(MI, BB);
19140 case X86::FP32_TO_INT16_IN_MEM:
19141 case X86::FP32_TO_INT32_IN_MEM:
19142 case X86::FP32_TO_INT64_IN_MEM:
19143 case X86::FP64_TO_INT16_IN_MEM:
19144 case X86::FP64_TO_INT32_IN_MEM:
19145 case X86::FP64_TO_INT64_IN_MEM:
19146 case X86::FP80_TO_INT16_IN_MEM:
19147 case X86::FP80_TO_INT32_IN_MEM:
19148 case X86::FP80_TO_INT64_IN_MEM: {
19149 MachineFunction *F = BB->getParent();
19150 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19151 DebugLoc DL = MI->getDebugLoc();
19153 // Change the floating point control register to use "round towards zero"
19154 // mode when truncating to an integer value.
19155 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19156 addFrameReference(BuildMI(*BB, MI, DL,
19157 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19159 // Load the old value of the high byte of the control word...
19161 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19162 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19165 // Set the high part to be round to zero...
19166 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19169 // Reload the modified control word now...
19170 addFrameReference(BuildMI(*BB, MI, DL,
19171 TII->get(X86::FLDCW16m)), CWFrameIdx);
19173 // Restore the memory image of control word to original value
19174 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19177 // Get the X86 opcode to use.
19179 switch (MI->getOpcode()) {
19180 default: llvm_unreachable("illegal opcode!");
19181 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19182 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19183 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19184 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19185 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19186 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19187 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19188 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19189 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19193 MachineOperand &Op = MI->getOperand(0);
19195 AM.BaseType = X86AddressMode::RegBase;
19196 AM.Base.Reg = Op.getReg();
19198 AM.BaseType = X86AddressMode::FrameIndexBase;
19199 AM.Base.FrameIndex = Op.getIndex();
19201 Op = MI->getOperand(1);
19203 AM.Scale = Op.getImm();
19204 Op = MI->getOperand(2);
19206 AM.IndexReg = Op.getImm();
19207 Op = MI->getOperand(3);
19208 if (Op.isGlobal()) {
19209 AM.GV = Op.getGlobal();
19211 AM.Disp = Op.getImm();
19213 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19214 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19216 // Reload the original control word now.
19217 addFrameReference(BuildMI(*BB, MI, DL,
19218 TII->get(X86::FLDCW16m)), CWFrameIdx);
19220 MI->eraseFromParent(); // The pseudo instruction is gone now.
19223 // String/text processing lowering.
19224 case X86::PCMPISTRM128REG:
19225 case X86::VPCMPISTRM128REG:
19226 case X86::PCMPISTRM128MEM:
19227 case X86::VPCMPISTRM128MEM:
19228 case X86::PCMPESTRM128REG:
19229 case X86::VPCMPESTRM128REG:
19230 case X86::PCMPESTRM128MEM:
19231 case X86::VPCMPESTRM128MEM:
19232 assert(Subtarget->hasSSE42() &&
19233 "Target must have SSE4.2 or AVX features enabled");
19234 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19236 // String/text processing lowering.
19237 case X86::PCMPISTRIREG:
19238 case X86::VPCMPISTRIREG:
19239 case X86::PCMPISTRIMEM:
19240 case X86::VPCMPISTRIMEM:
19241 case X86::PCMPESTRIREG:
19242 case X86::VPCMPESTRIREG:
19243 case X86::PCMPESTRIMEM:
19244 case X86::VPCMPESTRIMEM:
19245 assert(Subtarget->hasSSE42() &&
19246 "Target must have SSE4.2 or AVX features enabled");
19247 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19249 // Thread synchronization.
19251 return EmitMonitor(MI, BB, Subtarget);
19255 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19257 case X86::VASTART_SAVE_XMM_REGS:
19258 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19260 case X86::VAARG_64:
19261 return EmitVAARG64WithCustomInserter(MI, BB);
19263 case X86::EH_SjLj_SetJmp32:
19264 case X86::EH_SjLj_SetJmp64:
19265 return emitEHSjLjSetJmp(MI, BB);
19267 case X86::EH_SjLj_LongJmp32:
19268 case X86::EH_SjLj_LongJmp64:
19269 return emitEHSjLjLongJmp(MI, BB);
19271 case TargetOpcode::STATEPOINT:
19272 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19273 // this point in the process. We diverge later.
19274 return emitPatchPoint(MI, BB);
19276 case TargetOpcode::STACKMAP:
19277 case TargetOpcode::PATCHPOINT:
19278 return emitPatchPoint(MI, BB);
19280 case X86::VFMADDPDr213r:
19281 case X86::VFMADDPSr213r:
19282 case X86::VFMADDSDr213r:
19283 case X86::VFMADDSSr213r:
19284 case X86::VFMSUBPDr213r:
19285 case X86::VFMSUBPSr213r:
19286 case X86::VFMSUBSDr213r:
19287 case X86::VFMSUBSSr213r:
19288 case X86::VFNMADDPDr213r:
19289 case X86::VFNMADDPSr213r:
19290 case X86::VFNMADDSDr213r:
19291 case X86::VFNMADDSSr213r:
19292 case X86::VFNMSUBPDr213r:
19293 case X86::VFNMSUBPSr213r:
19294 case X86::VFNMSUBSDr213r:
19295 case X86::VFNMSUBSSr213r:
19296 case X86::VFMADDSUBPDr213r:
19297 case X86::VFMADDSUBPSr213r:
19298 case X86::VFMSUBADDPDr213r:
19299 case X86::VFMSUBADDPSr213r:
19300 case X86::VFMADDPDr213rY:
19301 case X86::VFMADDPSr213rY:
19302 case X86::VFMSUBPDr213rY:
19303 case X86::VFMSUBPSr213rY:
19304 case X86::VFNMADDPDr213rY:
19305 case X86::VFNMADDPSr213rY:
19306 case X86::VFNMSUBPDr213rY:
19307 case X86::VFNMSUBPSr213rY:
19308 case X86::VFMADDSUBPDr213rY:
19309 case X86::VFMADDSUBPSr213rY:
19310 case X86::VFMSUBADDPDr213rY:
19311 case X86::VFMSUBADDPSr213rY:
19312 return emitFMA3Instr(MI, BB);
19316 //===----------------------------------------------------------------------===//
19317 // X86 Optimization Hooks
19318 //===----------------------------------------------------------------------===//
19320 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19323 const SelectionDAG &DAG,
19324 unsigned Depth) const {
19325 unsigned BitWidth = KnownZero.getBitWidth();
19326 unsigned Opc = Op.getOpcode();
19327 assert((Opc >= ISD::BUILTIN_OP_END ||
19328 Opc == ISD::INTRINSIC_WO_CHAIN ||
19329 Opc == ISD::INTRINSIC_W_CHAIN ||
19330 Opc == ISD::INTRINSIC_VOID) &&
19331 "Should use MaskedValueIsZero if you don't know whether Op"
19332 " is a target node!");
19334 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19348 // These nodes' second result is a boolean.
19349 if (Op.getResNo() == 0)
19352 case X86ISD::SETCC:
19353 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19355 case ISD::INTRINSIC_WO_CHAIN: {
19356 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19357 unsigned NumLoBits = 0;
19360 case Intrinsic::x86_sse_movmsk_ps:
19361 case Intrinsic::x86_avx_movmsk_ps_256:
19362 case Intrinsic::x86_sse2_movmsk_pd:
19363 case Intrinsic::x86_avx_movmsk_pd_256:
19364 case Intrinsic::x86_mmx_pmovmskb:
19365 case Intrinsic::x86_sse2_pmovmskb_128:
19366 case Intrinsic::x86_avx2_pmovmskb: {
19367 // High bits of movmskp{s|d}, pmovmskb are known zero.
19369 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19370 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19371 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19372 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19373 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19374 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19375 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19376 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19378 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19387 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19389 const SelectionDAG &,
19390 unsigned Depth) const {
19391 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19392 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19393 return Op.getValueType().getScalarType().getSizeInBits();
19399 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19400 /// node is a GlobalAddress + offset.
19401 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19402 const GlobalValue* &GA,
19403 int64_t &Offset) const {
19404 if (N->getOpcode() == X86ISD::Wrapper) {
19405 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19406 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19407 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19411 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19414 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19415 /// same as extracting the high 128-bit part of 256-bit vector and then
19416 /// inserting the result into the low part of a new 256-bit vector
19417 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19418 EVT VT = SVOp->getValueType(0);
19419 unsigned NumElems = VT.getVectorNumElements();
19421 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19422 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19423 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19424 SVOp->getMaskElt(j) >= 0)
19430 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19431 /// same as extracting the low 128-bit part of 256-bit vector and then
19432 /// inserting the result into the high part of a new 256-bit vector
19433 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19434 EVT VT = SVOp->getValueType(0);
19435 unsigned NumElems = VT.getVectorNumElements();
19437 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19438 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19439 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19440 SVOp->getMaskElt(j) >= 0)
19446 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19447 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19448 TargetLowering::DAGCombinerInfo &DCI,
19449 const X86Subtarget* Subtarget) {
19451 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19452 SDValue V1 = SVOp->getOperand(0);
19453 SDValue V2 = SVOp->getOperand(1);
19454 EVT VT = SVOp->getValueType(0);
19455 unsigned NumElems = VT.getVectorNumElements();
19457 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19458 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19462 // V UNDEF BUILD_VECTOR UNDEF
19464 // CONCAT_VECTOR CONCAT_VECTOR
19467 // RESULT: V + zero extended
19469 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19470 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19471 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19474 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19477 // To match the shuffle mask, the first half of the mask should
19478 // be exactly the first vector, and all the rest a splat with the
19479 // first element of the second one.
19480 for (unsigned i = 0; i != NumElems/2; ++i)
19481 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19482 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19485 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19486 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19487 if (Ld->hasNUsesOfValue(1, 0)) {
19488 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19489 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19491 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19493 Ld->getPointerInfo(),
19494 Ld->getAlignment(),
19495 false/*isVolatile*/, true/*ReadMem*/,
19496 false/*WriteMem*/);
19498 // Make sure the newly-created LOAD is in the same position as Ld in
19499 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19500 // and update uses of Ld's output chain to use the TokenFactor.
19501 if (Ld->hasAnyUseOfValue(1)) {
19502 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19503 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19504 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19505 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19506 SDValue(ResNode.getNode(), 1));
19509 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19513 // Emit a zeroed vector and insert the desired subvector on its
19515 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19516 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19517 return DCI.CombineTo(N, InsV);
19520 //===--------------------------------------------------------------------===//
19521 // Combine some shuffles into subvector extracts and inserts:
19524 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19525 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19526 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19527 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19528 return DCI.CombineTo(N, InsV);
19531 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19532 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19533 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19534 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19535 return DCI.CombineTo(N, InsV);
19541 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19544 /// This is the leaf of the recursive combinine below. When we have found some
19545 /// chain of single-use x86 shuffle instructions and accumulated the combined
19546 /// shuffle mask represented by them, this will try to pattern match that mask
19547 /// into either a single instruction if there is a special purpose instruction
19548 /// for this operation, or into a PSHUFB instruction which is a fully general
19549 /// instruction but should only be used to replace chains over a certain depth.
19550 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19551 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19552 TargetLowering::DAGCombinerInfo &DCI,
19553 const X86Subtarget *Subtarget) {
19554 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19556 // Find the operand that enters the chain. Note that multiple uses are OK
19557 // here, we're not going to remove the operand we find.
19558 SDValue Input = Op.getOperand(0);
19559 while (Input.getOpcode() == ISD::BITCAST)
19560 Input = Input.getOperand(0);
19562 MVT VT = Input.getSimpleValueType();
19563 MVT RootVT = Root.getSimpleValueType();
19566 // Just remove no-op shuffle masks.
19567 if (Mask.size() == 1) {
19568 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19573 // Use the float domain if the operand type is a floating point type.
19574 bool FloatDomain = VT.isFloatingPoint();
19576 // For floating point shuffles, we don't have free copies in the shuffle
19577 // instructions or the ability to load as part of the instruction, so
19578 // canonicalize their shuffles to UNPCK or MOV variants.
19580 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19581 // vectors because it can have a load folded into it that UNPCK cannot. This
19582 // doesn't preclude something switching to the shorter encoding post-RA.
19584 // FIXME: Should teach these routines about AVX vector widths.
19585 if (FloatDomain && VT.getSizeInBits() == 128) {
19586 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
19587 bool Lo = Mask.equals({0, 0});
19590 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19591 // is no slower than UNPCKLPD but has the option to fold the input operand
19592 // into even an unaligned memory load.
19593 if (Lo && Subtarget->hasSSE3()) {
19594 Shuffle = X86ISD::MOVDDUP;
19595 ShuffleVT = MVT::v2f64;
19597 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19598 // than the UNPCK variants.
19599 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19600 ShuffleVT = MVT::v4f32;
19602 if (Depth == 1 && Root->getOpcode() == Shuffle)
19603 return false; // Nothing to do!
19604 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19605 DCI.AddToWorklist(Op.getNode());
19606 if (Shuffle == X86ISD::MOVDDUP)
19607 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19609 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19610 DCI.AddToWorklist(Op.getNode());
19611 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19615 if (Subtarget->hasSSE3() &&
19616 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
19617 bool Lo = Mask.equals({0, 0, 2, 2});
19618 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19619 MVT ShuffleVT = MVT::v4f32;
19620 if (Depth == 1 && Root->getOpcode() == Shuffle)
19621 return false; // Nothing to do!
19622 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19623 DCI.AddToWorklist(Op.getNode());
19624 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19625 DCI.AddToWorklist(Op.getNode());
19626 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19630 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
19631 bool Lo = Mask.equals({0, 0, 1, 1});
19632 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19633 MVT ShuffleVT = MVT::v4f32;
19634 if (Depth == 1 && Root->getOpcode() == Shuffle)
19635 return false; // Nothing to do!
19636 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19637 DCI.AddToWorklist(Op.getNode());
19638 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19639 DCI.AddToWorklist(Op.getNode());
19640 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19646 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19647 // variants as none of these have single-instruction variants that are
19648 // superior to the UNPCK formulation.
19649 if (!FloatDomain && VT.getSizeInBits() == 128 &&
19650 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
19651 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
19652 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
19654 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
19655 bool Lo = Mask[0] == 0;
19656 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19657 if (Depth == 1 && Root->getOpcode() == Shuffle)
19658 return false; // Nothing to do!
19660 switch (Mask.size()) {
19662 ShuffleVT = MVT::v8i16;
19665 ShuffleVT = MVT::v16i8;
19668 llvm_unreachable("Impossible mask size!");
19670 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19671 DCI.AddToWorklist(Op.getNode());
19672 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19673 DCI.AddToWorklist(Op.getNode());
19674 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19679 // Don't try to re-form single instruction chains under any circumstances now
19680 // that we've done encoding canonicalization for them.
19684 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19685 // can replace them with a single PSHUFB instruction profitably. Intel's
19686 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19687 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19688 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19689 SmallVector<SDValue, 16> PSHUFBMask;
19690 int NumBytes = VT.getSizeInBits() / 8;
19691 int Ratio = NumBytes / Mask.size();
19692 for (int i = 0; i < NumBytes; ++i) {
19693 if (Mask[i / Ratio] == SM_SentinelUndef) {
19694 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
19697 int M = Mask[i / Ratio] != SM_SentinelZero
19698 ? Ratio * Mask[i / Ratio] + i % Ratio
19700 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19702 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
19703 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
19704 DCI.AddToWorklist(Op.getNode());
19705 SDValue PSHUFBMaskOp =
19706 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
19707 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19708 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
19709 DCI.AddToWorklist(Op.getNode());
19710 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19715 // Failed to find any combines.
19719 /// \brief Fully generic combining of x86 shuffle instructions.
19721 /// This should be the last combine run over the x86 shuffle instructions. Once
19722 /// they have been fully optimized, this will recursively consider all chains
19723 /// of single-use shuffle instructions, build a generic model of the cumulative
19724 /// shuffle operation, and check for simpler instructions which implement this
19725 /// operation. We use this primarily for two purposes:
19727 /// 1) Collapse generic shuffles to specialized single instructions when
19728 /// equivalent. In most cases, this is just an encoding size win, but
19729 /// sometimes we will collapse multiple generic shuffles into a single
19730 /// special-purpose shuffle.
19731 /// 2) Look for sequences of shuffle instructions with 3 or more total
19732 /// instructions, and replace them with the slightly more expensive SSSE3
19733 /// PSHUFB instruction if available. We do this as the last combining step
19734 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19735 /// a suitable short sequence of other instructions. The PHUFB will either
19736 /// use a register or have to read from memory and so is slightly (but only
19737 /// slightly) more expensive than the other shuffle instructions.
19739 /// Because this is inherently a quadratic operation (for each shuffle in
19740 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19741 /// This should never be an issue in practice as the shuffle lowering doesn't
19742 /// produce sequences of more than 8 instructions.
19744 /// FIXME: We will currently miss some cases where the redundant shuffling
19745 /// would simplify under the threshold for PSHUFB formation because of
19746 /// combine-ordering. To fix this, we should do the redundant instruction
19747 /// combining in this recursive walk.
19748 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19749 ArrayRef<int> RootMask,
19750 int Depth, bool HasPSHUFB,
19752 TargetLowering::DAGCombinerInfo &DCI,
19753 const X86Subtarget *Subtarget) {
19754 // Bound the depth of our recursive combine because this is ultimately
19755 // quadratic in nature.
19759 // Directly rip through bitcasts to find the underlying operand.
19760 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19761 Op = Op.getOperand(0);
19763 MVT VT = Op.getSimpleValueType();
19764 if (!VT.isVector())
19765 return false; // Bail if we hit a non-vector.
19767 assert(Root.getSimpleValueType().isVector() &&
19768 "Shuffles operate on vector types!");
19769 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19770 "Can only combine shuffles of the same vector register size.");
19772 if (!isTargetShuffle(Op.getOpcode()))
19774 SmallVector<int, 16> OpMask;
19776 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19777 // We only can combine unary shuffles which we can decode the mask for.
19778 if (!HaveMask || !IsUnary)
19781 assert(VT.getVectorNumElements() == OpMask.size() &&
19782 "Different mask size from vector size!");
19783 assert(((RootMask.size() > OpMask.size() &&
19784 RootMask.size() % OpMask.size() == 0) ||
19785 (OpMask.size() > RootMask.size() &&
19786 OpMask.size() % RootMask.size() == 0) ||
19787 OpMask.size() == RootMask.size()) &&
19788 "The smaller number of elements must divide the larger.");
19789 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19790 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19791 assert(((RootRatio == 1 && OpRatio == 1) ||
19792 (RootRatio == 1) != (OpRatio == 1)) &&
19793 "Must not have a ratio for both incoming and op masks!");
19795 SmallVector<int, 16> Mask;
19796 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19798 // Merge this shuffle operation's mask into our accumulated mask. Note that
19799 // this shuffle's mask will be the first applied to the input, followed by the
19800 // root mask to get us all the way to the root value arrangement. The reason
19801 // for this order is that we are recursing up the operation chain.
19802 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19803 int RootIdx = i / RootRatio;
19804 if (RootMask[RootIdx] < 0) {
19805 // This is a zero or undef lane, we're done.
19806 Mask.push_back(RootMask[RootIdx]);
19810 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19811 int OpIdx = RootMaskedIdx / OpRatio;
19812 if (OpMask[OpIdx] < 0) {
19813 // The incoming lanes are zero or undef, it doesn't matter which ones we
19815 Mask.push_back(OpMask[OpIdx]);
19819 // Ok, we have non-zero lanes, map them through.
19820 Mask.push_back(OpMask[OpIdx] * OpRatio +
19821 RootMaskedIdx % OpRatio);
19824 // See if we can recurse into the operand to combine more things.
19825 switch (Op.getOpcode()) {
19826 case X86ISD::PSHUFB:
19828 case X86ISD::PSHUFD:
19829 case X86ISD::PSHUFHW:
19830 case X86ISD::PSHUFLW:
19831 if (Op.getOperand(0).hasOneUse() &&
19832 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19833 HasPSHUFB, DAG, DCI, Subtarget))
19837 case X86ISD::UNPCKL:
19838 case X86ISD::UNPCKH:
19839 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19840 // We can't check for single use, we have to check that this shuffle is the only user.
19841 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19842 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19843 HasPSHUFB, DAG, DCI, Subtarget))
19848 // Minor canonicalization of the accumulated shuffle mask to make it easier
19849 // to match below. All this does is detect masks with squential pairs of
19850 // elements, and shrink them to the half-width mask. It does this in a loop
19851 // so it will reduce the size of the mask to the minimal width mask which
19852 // performs an equivalent shuffle.
19853 SmallVector<int, 16> WidenedMask;
19854 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
19855 Mask = std::move(WidenedMask);
19856 WidenedMask.clear();
19859 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19863 /// \brief Get the PSHUF-style mask from PSHUF node.
19865 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19866 /// PSHUF-style masks that can be reused with such instructions.
19867 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19868 MVT VT = N.getSimpleValueType();
19869 SmallVector<int, 4> Mask;
19871 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
19875 // If we have more than 128-bits, only the low 128-bits of shuffle mask
19876 // matter. Check that the upper masks are repeats and remove them.
19877 if (VT.getSizeInBits() > 128) {
19878 int LaneElts = 128 / VT.getScalarSizeInBits();
19880 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
19881 for (int j = 0; j < LaneElts; ++j)
19882 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
19883 "Mask doesn't repeat in high 128-bit lanes!");
19885 Mask.resize(LaneElts);
19888 switch (N.getOpcode()) {
19889 case X86ISD::PSHUFD:
19891 case X86ISD::PSHUFLW:
19894 case X86ISD::PSHUFHW:
19895 Mask.erase(Mask.begin(), Mask.begin() + 4);
19896 for (int &M : Mask)
19900 llvm_unreachable("No valid shuffle instruction found!");
19904 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19906 /// We walk up the chain and look for a combinable shuffle, skipping over
19907 /// shuffles that we could hoist this shuffle's transformation past without
19908 /// altering anything.
19910 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19912 TargetLowering::DAGCombinerInfo &DCI) {
19913 assert(N.getOpcode() == X86ISD::PSHUFD &&
19914 "Called with something other than an x86 128-bit half shuffle!");
19917 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
19918 // of the shuffles in the chain so that we can form a fresh chain to replace
19920 SmallVector<SDValue, 8> Chain;
19921 SDValue V = N.getOperand(0);
19922 for (; V.hasOneUse(); V = V.getOperand(0)) {
19923 switch (V.getOpcode()) {
19925 return SDValue(); // Nothing combined!
19928 // Skip bitcasts as we always know the type for the target specific
19932 case X86ISD::PSHUFD:
19933 // Found another dword shuffle.
19936 case X86ISD::PSHUFLW:
19937 // Check that the low words (being shuffled) are the identity in the
19938 // dword shuffle, and the high words are self-contained.
19939 if (Mask[0] != 0 || Mask[1] != 1 ||
19940 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19943 Chain.push_back(V);
19946 case X86ISD::PSHUFHW:
19947 // Check that the high words (being shuffled) are the identity in the
19948 // dword shuffle, and the low words are self-contained.
19949 if (Mask[2] != 2 || Mask[3] != 3 ||
19950 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19953 Chain.push_back(V);
19956 case X86ISD::UNPCKL:
19957 case X86ISD::UNPCKH:
19958 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19959 // shuffle into a preceding word shuffle.
19960 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
19961 V.getSimpleValueType().getScalarType() != MVT::i16)
19964 // Search for a half-shuffle which we can combine with.
19965 unsigned CombineOp =
19966 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19967 if (V.getOperand(0) != V.getOperand(1) ||
19968 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19970 Chain.push_back(V);
19971 V = V.getOperand(0);
19973 switch (V.getOpcode()) {
19975 return SDValue(); // Nothing to combine.
19977 case X86ISD::PSHUFLW:
19978 case X86ISD::PSHUFHW:
19979 if (V.getOpcode() == CombineOp)
19982 Chain.push_back(V);
19986 V = V.getOperand(0);
19990 } while (V.hasOneUse());
19993 // Break out of the loop if we break out of the switch.
19997 if (!V.hasOneUse())
19998 // We fell out of the loop without finding a viable combining instruction.
20001 // Merge this node's mask and our incoming mask.
20002 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20003 for (int &M : Mask)
20005 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20006 getV4X86ShuffleImm8ForMask(Mask, DAG));
20008 // Rebuild the chain around this new shuffle.
20009 while (!Chain.empty()) {
20010 SDValue W = Chain.pop_back_val();
20012 if (V.getValueType() != W.getOperand(0).getValueType())
20013 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20015 switch (W.getOpcode()) {
20017 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20019 case X86ISD::UNPCKL:
20020 case X86ISD::UNPCKH:
20021 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20024 case X86ISD::PSHUFD:
20025 case X86ISD::PSHUFLW:
20026 case X86ISD::PSHUFHW:
20027 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20031 if (V.getValueType() != N.getValueType())
20032 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20034 // Return the new chain to replace N.
20038 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20040 /// We walk up the chain, skipping shuffles of the other half and looking
20041 /// through shuffles which switch halves trying to find a shuffle of the same
20042 /// pair of dwords.
20043 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20045 TargetLowering::DAGCombinerInfo &DCI) {
20047 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20048 "Called with something other than an x86 128-bit half shuffle!");
20050 unsigned CombineOpcode = N.getOpcode();
20052 // Walk up a single-use chain looking for a combinable shuffle.
20053 SDValue V = N.getOperand(0);
20054 for (; V.hasOneUse(); V = V.getOperand(0)) {
20055 switch (V.getOpcode()) {
20057 return false; // Nothing combined!
20060 // Skip bitcasts as we always know the type for the target specific
20064 case X86ISD::PSHUFLW:
20065 case X86ISD::PSHUFHW:
20066 if (V.getOpcode() == CombineOpcode)
20069 // Other-half shuffles are no-ops.
20072 // Break out of the loop if we break out of the switch.
20076 if (!V.hasOneUse())
20077 // We fell out of the loop without finding a viable combining instruction.
20080 // Combine away the bottom node as its shuffle will be accumulated into
20081 // a preceding shuffle.
20082 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20084 // Record the old value.
20087 // Merge this node's mask and our incoming mask (adjusted to account for all
20088 // the pshufd instructions encountered).
20089 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20090 for (int &M : Mask)
20092 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20093 getV4X86ShuffleImm8ForMask(Mask, DAG));
20095 // Check that the shuffles didn't cancel each other out. If not, we need to
20096 // combine to the new one.
20098 // Replace the combinable shuffle with the combined one, updating all users
20099 // so that we re-evaluate the chain here.
20100 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20105 /// \brief Try to combine x86 target specific shuffles.
20106 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20107 TargetLowering::DAGCombinerInfo &DCI,
20108 const X86Subtarget *Subtarget) {
20110 MVT VT = N.getSimpleValueType();
20111 SmallVector<int, 4> Mask;
20113 switch (N.getOpcode()) {
20114 case X86ISD::PSHUFD:
20115 case X86ISD::PSHUFLW:
20116 case X86ISD::PSHUFHW:
20117 Mask = getPSHUFShuffleMask(N);
20118 assert(Mask.size() == 4);
20124 // Nuke no-op shuffles that show up after combining.
20125 if (isNoopShuffleMask(Mask))
20126 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20128 // Look for simplifications involving one or two shuffle instructions.
20129 SDValue V = N.getOperand(0);
20130 switch (N.getOpcode()) {
20133 case X86ISD::PSHUFLW:
20134 case X86ISD::PSHUFHW:
20135 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20137 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20138 return SDValue(); // We combined away this shuffle, so we're done.
20140 // See if this reduces to a PSHUFD which is no more expensive and can
20141 // combine with more operations. Note that it has to at least flip the
20142 // dwords as otherwise it would have been removed as a no-op.
20143 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20144 int DMask[] = {0, 1, 2, 3};
20145 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20146 DMask[DOffset + 0] = DOffset + 1;
20147 DMask[DOffset + 1] = DOffset + 0;
20148 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20149 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20150 DCI.AddToWorklist(V.getNode());
20151 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20152 getV4X86ShuffleImm8ForMask(DMask, DAG));
20153 DCI.AddToWorklist(V.getNode());
20154 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20157 // Look for shuffle patterns which can be implemented as a single unpack.
20158 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20159 // only works when we have a PSHUFD followed by two half-shuffles.
20160 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20161 (V.getOpcode() == X86ISD::PSHUFLW ||
20162 V.getOpcode() == X86ISD::PSHUFHW) &&
20163 V.getOpcode() != N.getOpcode() &&
20165 SDValue D = V.getOperand(0);
20166 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20167 D = D.getOperand(0);
20168 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20169 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20170 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20171 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20172 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20174 for (int i = 0; i < 4; ++i) {
20175 WordMask[i + NOffset] = Mask[i] + NOffset;
20176 WordMask[i + VOffset] = VMask[i] + VOffset;
20178 // Map the word mask through the DWord mask.
20180 for (int i = 0; i < 8; ++i)
20181 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20182 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20183 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20184 // We can replace all three shuffles with an unpack.
20185 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20186 DCI.AddToWorklist(V.getNode());
20187 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20196 case X86ISD::PSHUFD:
20197 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20206 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20208 /// We combine this directly on the abstract vector shuffle nodes so it is
20209 /// easier to generically match. We also insert dummy vector shuffle nodes for
20210 /// the operands which explicitly discard the lanes which are unused by this
20211 /// operation to try to flow through the rest of the combiner the fact that
20212 /// they're unused.
20213 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20215 EVT VT = N->getValueType(0);
20217 // We only handle target-independent shuffles.
20218 // FIXME: It would be easy and harmless to use the target shuffle mask
20219 // extraction tool to support more.
20220 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20223 auto *SVN = cast<ShuffleVectorSDNode>(N);
20224 ArrayRef<int> Mask = SVN->getMask();
20225 SDValue V1 = N->getOperand(0);
20226 SDValue V2 = N->getOperand(1);
20228 // We require the first shuffle operand to be the SUB node, and the second to
20229 // be the ADD node.
20230 // FIXME: We should support the commuted patterns.
20231 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20234 // If there are other uses of these operations we can't fold them.
20235 if (!V1->hasOneUse() || !V2->hasOneUse())
20238 // Ensure that both operations have the same operands. Note that we can
20239 // commute the FADD operands.
20240 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20241 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20242 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20245 // We're looking for blends between FADD and FSUB nodes. We insist on these
20246 // nodes being lined up in a specific expected pattern.
20247 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20248 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20249 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20252 // Only specific types are legal at this point, assert so we notice if and
20253 // when these change.
20254 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20255 VT == MVT::v4f64) &&
20256 "Unknown vector type encountered!");
20258 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20261 /// PerformShuffleCombine - Performs several different shuffle combines.
20262 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20263 TargetLowering::DAGCombinerInfo &DCI,
20264 const X86Subtarget *Subtarget) {
20266 SDValue N0 = N->getOperand(0);
20267 SDValue N1 = N->getOperand(1);
20268 EVT VT = N->getValueType(0);
20270 // Don't create instructions with illegal types after legalize types has run.
20271 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20272 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20275 // If we have legalized the vector types, look for blends of FADD and FSUB
20276 // nodes that we can fuse into an ADDSUB node.
20277 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20278 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20281 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20282 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20283 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20284 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20286 // During Type Legalization, when promoting illegal vector types,
20287 // the backend might introduce new shuffle dag nodes and bitcasts.
20289 // This code performs the following transformation:
20290 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20291 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20293 // We do this only if both the bitcast and the BINOP dag nodes have
20294 // one use. Also, perform this transformation only if the new binary
20295 // operation is legal. This is to avoid introducing dag nodes that
20296 // potentially need to be further expanded (or custom lowered) into a
20297 // less optimal sequence of dag nodes.
20298 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20299 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20300 N0.getOpcode() == ISD::BITCAST) {
20301 SDValue BC0 = N0.getOperand(0);
20302 EVT SVT = BC0.getValueType();
20303 unsigned Opcode = BC0.getOpcode();
20304 unsigned NumElts = VT.getVectorNumElements();
20306 if (BC0.hasOneUse() && SVT.isVector() &&
20307 SVT.getVectorNumElements() * 2 == NumElts &&
20308 TLI.isOperationLegal(Opcode, VT)) {
20309 bool CanFold = false;
20321 unsigned SVTNumElts = SVT.getVectorNumElements();
20322 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20323 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20324 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20325 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20326 CanFold = SVOp->getMaskElt(i) < 0;
20329 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20330 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20331 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20332 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20337 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20338 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20339 // consecutive, non-overlapping, and in the right order.
20340 SmallVector<SDValue, 16> Elts;
20341 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20342 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20344 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20348 if (isTargetShuffle(N->getOpcode())) {
20350 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20351 if (Shuffle.getNode())
20354 // Try recursively combining arbitrary sequences of x86 shuffle
20355 // instructions into higher-order shuffles. We do this after combining
20356 // specific PSHUF instruction sequences into their minimal form so that we
20357 // can evaluate how many specialized shuffle instructions are involved in
20358 // a particular chain.
20359 SmallVector<int, 1> NonceMask; // Just a placeholder.
20360 NonceMask.push_back(0);
20361 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20362 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20364 return SDValue(); // This routine will use CombineTo to replace N.
20370 /// PerformTruncateCombine - Converts truncate operation to
20371 /// a sequence of vector shuffle operations.
20372 /// It is possible when we truncate 256-bit vector to 128-bit vector
20373 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20374 TargetLowering::DAGCombinerInfo &DCI,
20375 const X86Subtarget *Subtarget) {
20379 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20380 /// specific shuffle of a load can be folded into a single element load.
20381 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20382 /// shuffles have been custom lowered so we need to handle those here.
20383 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20384 TargetLowering::DAGCombinerInfo &DCI) {
20385 if (DCI.isBeforeLegalizeOps())
20388 SDValue InVec = N->getOperand(0);
20389 SDValue EltNo = N->getOperand(1);
20391 if (!isa<ConstantSDNode>(EltNo))
20394 EVT OriginalVT = InVec.getValueType();
20396 if (InVec.getOpcode() == ISD::BITCAST) {
20397 // Don't duplicate a load with other uses.
20398 if (!InVec.hasOneUse())
20400 EVT BCVT = InVec.getOperand(0).getValueType();
20401 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
20403 InVec = InVec.getOperand(0);
20406 EVT CurrentVT = InVec.getValueType();
20408 if (!isTargetShuffle(InVec.getOpcode()))
20411 // Don't duplicate a load with other uses.
20412 if (!InVec.hasOneUse())
20415 SmallVector<int, 16> ShuffleMask;
20417 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
20418 ShuffleMask, UnaryShuffle))
20421 // Select the input vector, guarding against out of range extract vector.
20422 unsigned NumElems = CurrentVT.getVectorNumElements();
20423 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20424 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20425 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20426 : InVec.getOperand(1);
20428 // If inputs to shuffle are the same for both ops, then allow 2 uses
20429 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20430 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20432 if (LdNode.getOpcode() == ISD::BITCAST) {
20433 // Don't duplicate a load with other uses.
20434 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20437 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20438 LdNode = LdNode.getOperand(0);
20441 if (!ISD::isNormalLoad(LdNode.getNode()))
20444 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20446 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20449 EVT EltVT = N->getValueType(0);
20450 // If there's a bitcast before the shuffle, check if the load type and
20451 // alignment is valid.
20452 unsigned Align = LN0->getAlignment();
20453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20454 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20455 EltVT.getTypeForEVT(*DAG.getContext()));
20457 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20460 // All checks match so transform back to vector_shuffle so that DAG combiner
20461 // can finish the job
20464 // Create shuffle node taking into account the case that its a unary shuffle
20465 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20466 : InVec.getOperand(1);
20467 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20468 InVec.getOperand(0), Shuffle,
20470 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20471 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20475 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
20476 /// special and don't usually play with other vector types, it's better to
20477 /// handle them early to be sure we emit efficient code by avoiding
20478 /// store-load conversions.
20479 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
20480 if (N->getValueType(0) != MVT::x86mmx ||
20481 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
20482 N->getOperand(0)->getValueType(0) != MVT::v2i32)
20485 SDValue V = N->getOperand(0);
20486 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
20487 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
20488 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
20489 N->getValueType(0), V.getOperand(0));
20494 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20495 /// generation and convert it from being a bunch of shuffles and extracts
20496 /// into a somewhat faster sequence. For i686, the best sequence is apparently
20497 /// storing the value and loading scalars back, while for x64 we should
20498 /// use 64-bit extracts and shifts.
20499 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20500 TargetLowering::DAGCombinerInfo &DCI) {
20501 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20502 if (NewOp.getNode())
20505 SDValue InputVector = N->getOperand(0);
20507 // Detect mmx to i32 conversion through a v2i32 elt extract.
20508 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
20509 N->getValueType(0) == MVT::i32 &&
20510 InputVector.getValueType() == MVT::v2i32) {
20512 // The bitcast source is a direct mmx result.
20513 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
20514 if (MMXSrc.getValueType() == MVT::x86mmx)
20515 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20516 N->getValueType(0),
20517 InputVector.getNode()->getOperand(0));
20519 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
20520 SDValue MMXSrcOp = MMXSrc.getOperand(0);
20521 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
20522 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
20523 MMXSrcOp.getOpcode() == ISD::BITCAST &&
20524 MMXSrcOp.getValueType() == MVT::v1i64 &&
20525 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
20526 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20527 N->getValueType(0),
20528 MMXSrcOp.getOperand(0));
20531 // Only operate on vectors of 4 elements, where the alternative shuffling
20532 // gets to be more expensive.
20533 if (InputVector.getValueType() != MVT::v4i32)
20536 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20537 // single use which is a sign-extend or zero-extend, and all elements are
20539 SmallVector<SDNode *, 4> Uses;
20540 unsigned ExtractedElements = 0;
20541 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20542 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20543 if (UI.getUse().getResNo() != InputVector.getResNo())
20546 SDNode *Extract = *UI;
20547 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20550 if (Extract->getValueType(0) != MVT::i32)
20552 if (!Extract->hasOneUse())
20554 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20555 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20557 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20560 // Record which element was extracted.
20561 ExtractedElements |=
20562 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20564 Uses.push_back(Extract);
20567 // If not all the elements were used, this may not be worthwhile.
20568 if (ExtractedElements != 15)
20571 // Ok, we've now decided to do the transformation.
20572 // If 64-bit shifts are legal, use the extract-shift sequence,
20573 // otherwise bounce the vector off the cache.
20574 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20576 SDLoc dl(InputVector);
20578 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
20579 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
20580 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
20581 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20582 DAG.getConstant(0, VecIdxTy));
20583 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20584 DAG.getConstant(1, VecIdxTy));
20586 SDValue ShAmt = DAG.getConstant(32,
20587 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
20588 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
20589 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20590 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
20591 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
20592 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20593 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
20595 // Store the value to a temporary stack slot.
20596 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20597 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20598 MachinePointerInfo(), false, false, 0);
20600 EVT ElementType = InputVector.getValueType().getVectorElementType();
20601 unsigned EltSize = ElementType.getSizeInBits() / 8;
20603 // Replace each use (extract) with a load of the appropriate element.
20604 for (unsigned i = 0; i < 4; ++i) {
20605 uint64_t Offset = EltSize * i;
20606 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20608 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20609 StackPtr, OffsetVal);
20611 // Load the scalar.
20612 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
20613 ScalarAddr, MachinePointerInfo(),
20614 false, false, false, 0);
20619 // Replace the extracts
20620 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20621 UE = Uses.end(); UI != UE; ++UI) {
20622 SDNode *Extract = *UI;
20624 SDValue Idx = Extract->getOperand(1);
20625 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
20626 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
20629 // The replacement was made in place; don't return anything.
20633 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20634 static std::pair<unsigned, bool>
20635 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20636 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20637 if (!VT.isVector())
20638 return std::make_pair(0, false);
20640 bool NeedSplit = false;
20641 switch (VT.getSimpleVT().SimpleTy) {
20642 default: return std::make_pair(0, false);
20645 if (!Subtarget->hasVLX())
20646 return std::make_pair(0, false);
20650 if (!Subtarget->hasBWI())
20651 return std::make_pair(0, false);
20655 if (!Subtarget->hasAVX512())
20656 return std::make_pair(0, false);
20661 if (!Subtarget->hasAVX2())
20663 if (!Subtarget->hasAVX())
20664 return std::make_pair(0, false);
20669 if (!Subtarget->hasSSE2())
20670 return std::make_pair(0, false);
20673 // SSE2 has only a small subset of the operations.
20674 bool hasUnsigned = Subtarget->hasSSE41() ||
20675 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20676 bool hasSigned = Subtarget->hasSSE41() ||
20677 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20679 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20682 // Check for x CC y ? x : y.
20683 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20684 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20689 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20692 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20695 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20698 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20700 // Check for x CC y ? y : x -- a min/max with reversed arms.
20701 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20702 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20707 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20710 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20713 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20716 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20720 return std::make_pair(Opc, NeedSplit);
20724 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20725 const X86Subtarget *Subtarget) {
20727 SDValue Cond = N->getOperand(0);
20728 SDValue LHS = N->getOperand(1);
20729 SDValue RHS = N->getOperand(2);
20731 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20732 SDValue CondSrc = Cond->getOperand(0);
20733 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20734 Cond = CondSrc->getOperand(0);
20737 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20740 // A vselect where all conditions and data are constants can be optimized into
20741 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20742 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20743 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20746 unsigned MaskValue = 0;
20747 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20750 MVT VT = N->getSimpleValueType(0);
20751 unsigned NumElems = VT.getVectorNumElements();
20752 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20753 for (unsigned i = 0; i < NumElems; ++i) {
20754 // Be sure we emit undef where we can.
20755 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20756 ShuffleMask[i] = -1;
20758 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20762 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
20764 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20767 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20769 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20770 TargetLowering::DAGCombinerInfo &DCI,
20771 const X86Subtarget *Subtarget) {
20773 SDValue Cond = N->getOperand(0);
20774 // Get the LHS/RHS of the select.
20775 SDValue LHS = N->getOperand(1);
20776 SDValue RHS = N->getOperand(2);
20777 EVT VT = LHS.getValueType();
20778 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20780 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20781 // instructions match the semantics of the common C idiom x<y?x:y but not
20782 // x<=y?x:y, because of how they handle negative zero (which can be
20783 // ignored in unsafe-math mode).
20784 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
20785 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20786 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
20787 (Subtarget->hasSSE2() ||
20788 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20789 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20791 unsigned Opcode = 0;
20792 // Check for x CC y ? x : y.
20793 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20794 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20798 // Converting this to a min would handle NaNs incorrectly, and swapping
20799 // the operands would cause it to handle comparisons between positive
20800 // and negative zero incorrectly.
20801 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20802 if (!DAG.getTarget().Options.UnsafeFPMath &&
20803 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20805 std::swap(LHS, RHS);
20807 Opcode = X86ISD::FMIN;
20810 // Converting this to a min would handle comparisons between positive
20811 // and negative zero incorrectly.
20812 if (!DAG.getTarget().Options.UnsafeFPMath &&
20813 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20815 Opcode = X86ISD::FMIN;
20818 // Converting this to a min would handle both negative zeros and NaNs
20819 // incorrectly, but we can swap the operands to fix both.
20820 std::swap(LHS, RHS);
20824 Opcode = X86ISD::FMIN;
20828 // Converting this to a max would handle comparisons between positive
20829 // and negative zero incorrectly.
20830 if (!DAG.getTarget().Options.UnsafeFPMath &&
20831 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20833 Opcode = X86ISD::FMAX;
20836 // Converting this to a max would handle NaNs incorrectly, and swapping
20837 // the operands would cause it to handle comparisons between positive
20838 // and negative zero incorrectly.
20839 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20840 if (!DAG.getTarget().Options.UnsafeFPMath &&
20841 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20843 std::swap(LHS, RHS);
20845 Opcode = X86ISD::FMAX;
20848 // Converting this to a max would handle both negative zeros and NaNs
20849 // incorrectly, but we can swap the operands to fix both.
20850 std::swap(LHS, RHS);
20854 Opcode = X86ISD::FMAX;
20857 // Check for x CC y ? y : x -- a min/max with reversed arms.
20858 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20859 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20863 // Converting this to a min would handle comparisons between positive
20864 // and negative zero incorrectly, and swapping the operands would
20865 // cause it to handle NaNs incorrectly.
20866 if (!DAG.getTarget().Options.UnsafeFPMath &&
20867 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20868 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20870 std::swap(LHS, RHS);
20872 Opcode = X86ISD::FMIN;
20875 // Converting this to a min would handle NaNs incorrectly.
20876 if (!DAG.getTarget().Options.UnsafeFPMath &&
20877 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20879 Opcode = X86ISD::FMIN;
20882 // Converting this to a min would handle both negative zeros and NaNs
20883 // incorrectly, but we can swap the operands to fix both.
20884 std::swap(LHS, RHS);
20888 Opcode = X86ISD::FMIN;
20892 // Converting this to a max would handle NaNs incorrectly.
20893 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20895 Opcode = X86ISD::FMAX;
20898 // Converting this to a max would handle comparisons between positive
20899 // and negative zero incorrectly, and swapping the operands would
20900 // cause it to handle NaNs incorrectly.
20901 if (!DAG.getTarget().Options.UnsafeFPMath &&
20902 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20903 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20905 std::swap(LHS, RHS);
20907 Opcode = X86ISD::FMAX;
20910 // Converting this to a max would handle both negative zeros and NaNs
20911 // incorrectly, but we can swap the operands to fix both.
20912 std::swap(LHS, RHS);
20916 Opcode = X86ISD::FMAX;
20922 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20925 EVT CondVT = Cond.getValueType();
20926 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20927 CondVT.getVectorElementType() == MVT::i1) {
20928 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20929 // lowering on KNL. In this case we convert it to
20930 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20931 // The same situation for all 128 and 256-bit vectors of i8 and i16.
20932 // Since SKX these selects have a proper lowering.
20933 EVT OpVT = LHS.getValueType();
20934 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20935 (OpVT.getVectorElementType() == MVT::i8 ||
20936 OpVT.getVectorElementType() == MVT::i16) &&
20937 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
20938 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20939 DCI.AddToWorklist(Cond.getNode());
20940 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20943 // If this is a select between two integer constants, try to do some
20945 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20946 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20947 // Don't do this for crazy integer types.
20948 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20949 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20950 // so that TrueC (the true value) is larger than FalseC.
20951 bool NeedsCondInvert = false;
20953 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20954 // Efficiently invertible.
20955 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20956 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20957 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20958 NeedsCondInvert = true;
20959 std::swap(TrueC, FalseC);
20962 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20963 if (FalseC->getAPIntValue() == 0 &&
20964 TrueC->getAPIntValue().isPowerOf2()) {
20965 if (NeedsCondInvert) // Invert the condition if needed.
20966 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20967 DAG.getConstant(1, Cond.getValueType()));
20969 // Zero extend the condition if needed.
20970 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20972 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20973 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20974 DAG.getConstant(ShAmt, MVT::i8));
20977 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20978 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20979 if (NeedsCondInvert) // Invert the condition if needed.
20980 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20981 DAG.getConstant(1, Cond.getValueType()));
20983 // Zero extend the condition if needed.
20984 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20985 FalseC->getValueType(0), Cond);
20986 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20987 SDValue(FalseC, 0));
20990 // Optimize cases that will turn into an LEA instruction. This requires
20991 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20992 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20993 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20994 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20996 bool isFastMultiplier = false;
20998 switch ((unsigned char)Diff) {
21000 case 1: // result = add base, cond
21001 case 2: // result = lea base( , cond*2)
21002 case 3: // result = lea base(cond, cond*2)
21003 case 4: // result = lea base( , cond*4)
21004 case 5: // result = lea base(cond, cond*4)
21005 case 8: // result = lea base( , cond*8)
21006 case 9: // result = lea base(cond, cond*8)
21007 isFastMultiplier = true;
21012 if (isFastMultiplier) {
21013 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21014 if (NeedsCondInvert) // Invert the condition if needed.
21015 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21016 DAG.getConstant(1, Cond.getValueType()));
21018 // Zero extend the condition if needed.
21019 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21021 // Scale the condition by the difference.
21023 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21024 DAG.getConstant(Diff, Cond.getValueType()));
21026 // Add the base if non-zero.
21027 if (FalseC->getAPIntValue() != 0)
21028 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21029 SDValue(FalseC, 0));
21036 // Canonicalize max and min:
21037 // (x > y) ? x : y -> (x >= y) ? x : y
21038 // (x < y) ? x : y -> (x <= y) ? x : y
21039 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21040 // the need for an extra compare
21041 // against zero. e.g.
21042 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21044 // testl %edi, %edi
21046 // cmovgl %edi, %eax
21050 // cmovsl %eax, %edi
21051 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21052 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21053 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21054 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21059 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21060 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21061 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21062 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21067 // Early exit check
21068 if (!TLI.isTypeLegal(VT))
21071 // Match VSELECTs into subs with unsigned saturation.
21072 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21073 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21074 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21075 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21076 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21078 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21079 // left side invert the predicate to simplify logic below.
21081 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21083 CC = ISD::getSetCCInverse(CC, true);
21084 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21088 if (Other.getNode() && Other->getNumOperands() == 2 &&
21089 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21090 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21091 SDValue CondRHS = Cond->getOperand(1);
21093 // Look for a general sub with unsigned saturation first.
21094 // x >= y ? x-y : 0 --> subus x, y
21095 // x > y ? x-y : 0 --> subus x, y
21096 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21097 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21098 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21100 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21101 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21102 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21103 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21104 // If the RHS is a constant we have to reverse the const
21105 // canonicalization.
21106 // x > C-1 ? x+-C : 0 --> subus x, C
21107 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21108 CondRHSConst->getAPIntValue() ==
21109 (-OpRHSConst->getAPIntValue() - 1))
21110 return DAG.getNode(
21111 X86ISD::SUBUS, DL, VT, OpLHS,
21112 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21114 // Another special case: If C was a sign bit, the sub has been
21115 // canonicalized into a xor.
21116 // FIXME: Would it be better to use computeKnownBits to determine
21117 // whether it's safe to decanonicalize the xor?
21118 // x s< 0 ? x^C : 0 --> subus x, C
21119 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21120 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21121 OpRHSConst->getAPIntValue().isSignBit())
21122 // Note that we have to rebuild the RHS constant here to ensure we
21123 // don't rely on particular values of undef lanes.
21124 return DAG.getNode(
21125 X86ISD::SUBUS, DL, VT, OpLHS,
21126 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21131 // Try to match a min/max vector operation.
21132 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21133 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21134 unsigned Opc = ret.first;
21135 bool NeedSplit = ret.second;
21137 if (Opc && NeedSplit) {
21138 unsigned NumElems = VT.getVectorNumElements();
21139 // Extract the LHS vectors
21140 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21141 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21143 // Extract the RHS vectors
21144 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21145 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21147 // Create min/max for each subvector
21148 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21149 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21151 // Merge the result
21152 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21154 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21157 // Simplify vector selection if condition value type matches vselect
21159 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21160 assert(Cond.getValueType().isVector() &&
21161 "vector select expects a vector selector!");
21163 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21164 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21166 // Try invert the condition if true value is not all 1s and false value
21168 if (!TValIsAllOnes && !FValIsAllZeros &&
21169 // Check if the selector will be produced by CMPP*/PCMP*
21170 Cond.getOpcode() == ISD::SETCC &&
21171 // Check if SETCC has already been promoted
21172 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21173 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21174 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21176 if (TValIsAllZeros || FValIsAllOnes) {
21177 SDValue CC = Cond.getOperand(2);
21178 ISD::CondCode NewCC =
21179 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21180 Cond.getOperand(0).getValueType().isInteger());
21181 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21182 std::swap(LHS, RHS);
21183 TValIsAllOnes = FValIsAllOnes;
21184 FValIsAllZeros = TValIsAllZeros;
21188 if (TValIsAllOnes || FValIsAllZeros) {
21191 if (TValIsAllOnes && FValIsAllZeros)
21193 else if (TValIsAllOnes)
21194 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21195 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21196 else if (FValIsAllZeros)
21197 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21198 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21200 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21204 // We should generate an X86ISD::BLENDI from a vselect if its argument
21205 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21206 // constants. This specific pattern gets generated when we split a
21207 // selector for a 512 bit vector in a machine without AVX512 (but with
21208 // 256-bit vectors), during legalization:
21210 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21212 // Iff we find this pattern and the build_vectors are built from
21213 // constants, we translate the vselect into a shuffle_vector that we
21214 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21215 if ((N->getOpcode() == ISD::VSELECT ||
21216 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21217 !DCI.isBeforeLegalize()) {
21218 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21219 if (Shuffle.getNode())
21223 // If this is a *dynamic* select (non-constant condition) and we can match
21224 // this node with one of the variable blend instructions, restructure the
21225 // condition so that the blends can use the high bit of each element and use
21226 // SimplifyDemandedBits to simplify the condition operand.
21227 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21228 !DCI.isBeforeLegalize() &&
21229 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21230 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21232 // Don't optimize vector selects that map to mask-registers.
21236 // We can only handle the cases where VSELECT is directly legal on the
21237 // subtarget. We custom lower VSELECT nodes with constant conditions and
21238 // this makes it hard to see whether a dynamic VSELECT will correctly
21239 // lower, so we both check the operation's status and explicitly handle the
21240 // cases where a *dynamic* blend will fail even though a constant-condition
21241 // blend could be custom lowered.
21242 // FIXME: We should find a better way to handle this class of problems.
21243 // Potentially, we should combine constant-condition vselect nodes
21244 // pre-legalization into shuffles and not mark as many types as custom
21246 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21248 // FIXME: We don't support i16-element blends currently. We could and
21249 // should support them by making *all* the bits in the condition be set
21250 // rather than just the high bit and using an i8-element blend.
21251 if (VT.getScalarType() == MVT::i16)
21253 // Dynamic blending was only available from SSE4.1 onward.
21254 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21256 // Byte blends are only available in AVX2
21257 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21258 !Subtarget->hasAVX2())
21261 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21262 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21264 APInt KnownZero, KnownOne;
21265 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21266 DCI.isBeforeLegalizeOps());
21267 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21268 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21270 // If we changed the computation somewhere in the DAG, this change
21271 // will affect all users of Cond.
21272 // Make sure it is fine and update all the nodes so that we do not
21273 // use the generic VSELECT anymore. Otherwise, we may perform
21274 // wrong optimizations as we messed up with the actual expectation
21275 // for the vector boolean values.
21276 if (Cond != TLO.Old) {
21277 // Check all uses of that condition operand to check whether it will be
21278 // consumed by non-BLEND instructions, which may depend on all bits are
21280 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21282 if (I->getOpcode() != ISD::VSELECT)
21283 // TODO: Add other opcodes eventually lowered into BLEND.
21286 // Update all the users of the condition, before committing the change,
21287 // so that the VSELECT optimizations that expect the correct vector
21288 // boolean value will not be triggered.
21289 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21291 DAG.ReplaceAllUsesOfValueWith(
21293 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21294 Cond, I->getOperand(1), I->getOperand(2)));
21295 DCI.CommitTargetLoweringOpt(TLO);
21298 // At this point, only Cond is changed. Change the condition
21299 // just for N to keep the opportunity to optimize all other
21300 // users their own way.
21301 DAG.ReplaceAllUsesOfValueWith(
21303 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21304 TLO.New, N->getOperand(1), N->getOperand(2)));
21312 // Check whether a boolean test is testing a boolean value generated by
21313 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21316 // Simplify the following patterns:
21317 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21318 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21319 // to (Op EFLAGS Cond)
21321 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21322 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21323 // to (Op EFLAGS !Cond)
21325 // where Op could be BRCOND or CMOV.
21327 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21328 // Quit if not CMP and SUB with its value result used.
21329 if (Cmp.getOpcode() != X86ISD::CMP &&
21330 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21333 // Quit if not used as a boolean value.
21334 if (CC != X86::COND_E && CC != X86::COND_NE)
21337 // Check CMP operands. One of them should be 0 or 1 and the other should be
21338 // an SetCC or extended from it.
21339 SDValue Op1 = Cmp.getOperand(0);
21340 SDValue Op2 = Cmp.getOperand(1);
21343 const ConstantSDNode* C = nullptr;
21344 bool needOppositeCond = (CC == X86::COND_E);
21345 bool checkAgainstTrue = false; // Is it a comparison against 1?
21347 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21349 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21351 else // Quit if all operands are not constants.
21354 if (C->getZExtValue() == 1) {
21355 needOppositeCond = !needOppositeCond;
21356 checkAgainstTrue = true;
21357 } else if (C->getZExtValue() != 0)
21358 // Quit if the constant is neither 0 or 1.
21361 bool truncatedToBoolWithAnd = false;
21362 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21363 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21364 SetCC.getOpcode() == ISD::TRUNCATE ||
21365 SetCC.getOpcode() == ISD::AND) {
21366 if (SetCC.getOpcode() == ISD::AND) {
21368 ConstantSDNode *CS;
21369 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21370 CS->getZExtValue() == 1)
21372 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21373 CS->getZExtValue() == 1)
21377 SetCC = SetCC.getOperand(OpIdx);
21378 truncatedToBoolWithAnd = true;
21380 SetCC = SetCC.getOperand(0);
21383 switch (SetCC.getOpcode()) {
21384 case X86ISD::SETCC_CARRY:
21385 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21386 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21387 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21388 // truncated to i1 using 'and'.
21389 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21391 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21392 "Invalid use of SETCC_CARRY!");
21394 case X86ISD::SETCC:
21395 // Set the condition code or opposite one if necessary.
21396 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21397 if (needOppositeCond)
21398 CC = X86::GetOppositeBranchCondition(CC);
21399 return SetCC.getOperand(1);
21400 case X86ISD::CMOV: {
21401 // Check whether false/true value has canonical one, i.e. 0 or 1.
21402 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21403 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21404 // Quit if true value is not a constant.
21407 // Quit if false value is not a constant.
21409 SDValue Op = SetCC.getOperand(0);
21410 // Skip 'zext' or 'trunc' node.
21411 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21412 Op.getOpcode() == ISD::TRUNCATE)
21413 Op = Op.getOperand(0);
21414 // A special case for rdrand/rdseed, where 0 is set if false cond is
21416 if ((Op.getOpcode() != X86ISD::RDRAND &&
21417 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21420 // Quit if false value is not the constant 0 or 1.
21421 bool FValIsFalse = true;
21422 if (FVal && FVal->getZExtValue() != 0) {
21423 if (FVal->getZExtValue() != 1)
21425 // If FVal is 1, opposite cond is needed.
21426 needOppositeCond = !needOppositeCond;
21427 FValIsFalse = false;
21429 // Quit if TVal is not the constant opposite of FVal.
21430 if (FValIsFalse && TVal->getZExtValue() != 1)
21432 if (!FValIsFalse && TVal->getZExtValue() != 0)
21434 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21435 if (needOppositeCond)
21436 CC = X86::GetOppositeBranchCondition(CC);
21437 return SetCC.getOperand(3);
21444 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
21446 /// (X86or (X86setcc) (X86setcc))
21447 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
21448 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
21449 X86::CondCode &CC1, SDValue &Flags,
21451 if (Cond->getOpcode() == X86ISD::CMP) {
21452 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
21453 if (!CondOp1C || !CondOp1C->isNullValue())
21456 Cond = Cond->getOperand(0);
21461 SDValue SetCC0, SetCC1;
21462 switch (Cond->getOpcode()) {
21463 default: return false;
21470 SetCC0 = Cond->getOperand(0);
21471 SetCC1 = Cond->getOperand(1);
21475 // Make sure we have SETCC nodes, using the same flags value.
21476 if (SetCC0.getOpcode() != X86ISD::SETCC ||
21477 SetCC1.getOpcode() != X86ISD::SETCC ||
21478 SetCC0->getOperand(1) != SetCC1->getOperand(1))
21481 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
21482 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
21483 Flags = SetCC0->getOperand(1);
21487 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21488 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21489 TargetLowering::DAGCombinerInfo &DCI,
21490 const X86Subtarget *Subtarget) {
21493 // If the flag operand isn't dead, don't touch this CMOV.
21494 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21497 SDValue FalseOp = N->getOperand(0);
21498 SDValue TrueOp = N->getOperand(1);
21499 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21500 SDValue Cond = N->getOperand(3);
21502 if (CC == X86::COND_E || CC == X86::COND_NE) {
21503 switch (Cond.getOpcode()) {
21507 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21508 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21509 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21515 Flags = checkBoolTestSetCCCombine(Cond, CC);
21516 if (Flags.getNode() &&
21517 // Extra check as FCMOV only supports a subset of X86 cond.
21518 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21519 SDValue Ops[] = { FalseOp, TrueOp,
21520 DAG.getConstant(CC, MVT::i8), Flags };
21521 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21524 // If this is a select between two integer constants, try to do some
21525 // optimizations. Note that the operands are ordered the opposite of SELECT
21527 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21528 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21529 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21530 // larger than FalseC (the false value).
21531 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21532 CC = X86::GetOppositeBranchCondition(CC);
21533 std::swap(TrueC, FalseC);
21534 std::swap(TrueOp, FalseOp);
21537 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21538 // This is efficient for any integer data type (including i8/i16) and
21540 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21541 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21542 DAG.getConstant(CC, MVT::i8), Cond);
21544 // Zero extend the condition if needed.
21545 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21547 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21548 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21549 DAG.getConstant(ShAmt, MVT::i8));
21550 if (N->getNumValues() == 2) // Dead flag value?
21551 return DCI.CombineTo(N, Cond, SDValue());
21555 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21556 // for any integer data type, including i8/i16.
21557 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21558 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21559 DAG.getConstant(CC, MVT::i8), Cond);
21561 // Zero extend the condition if needed.
21562 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21563 FalseC->getValueType(0), Cond);
21564 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21565 SDValue(FalseC, 0));
21567 if (N->getNumValues() == 2) // Dead flag value?
21568 return DCI.CombineTo(N, Cond, SDValue());
21572 // Optimize cases that will turn into an LEA instruction. This requires
21573 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21574 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21575 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21576 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21578 bool isFastMultiplier = false;
21580 switch ((unsigned char)Diff) {
21582 case 1: // result = add base, cond
21583 case 2: // result = lea base( , cond*2)
21584 case 3: // result = lea base(cond, cond*2)
21585 case 4: // result = lea base( , cond*4)
21586 case 5: // result = lea base(cond, cond*4)
21587 case 8: // result = lea base( , cond*8)
21588 case 9: // result = lea base(cond, cond*8)
21589 isFastMultiplier = true;
21594 if (isFastMultiplier) {
21595 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21596 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21597 DAG.getConstant(CC, MVT::i8), Cond);
21598 // Zero extend the condition if needed.
21599 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21601 // Scale the condition by the difference.
21603 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21604 DAG.getConstant(Diff, Cond.getValueType()));
21606 // Add the base if non-zero.
21607 if (FalseC->getAPIntValue() != 0)
21608 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21609 SDValue(FalseC, 0));
21610 if (N->getNumValues() == 2) // Dead flag value?
21611 return DCI.CombineTo(N, Cond, SDValue());
21618 // Handle these cases:
21619 // (select (x != c), e, c) -> select (x != c), e, x),
21620 // (select (x == c), c, e) -> select (x == c), x, e)
21621 // where the c is an integer constant, and the "select" is the combination
21622 // of CMOV and CMP.
21624 // The rationale for this change is that the conditional-move from a constant
21625 // needs two instructions, however, conditional-move from a register needs
21626 // only one instruction.
21628 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21629 // some instruction-combining opportunities. This opt needs to be
21630 // postponed as late as possible.
21632 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21633 // the DCI.xxxx conditions are provided to postpone the optimization as
21634 // late as possible.
21636 ConstantSDNode *CmpAgainst = nullptr;
21637 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21638 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21639 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21641 if (CC == X86::COND_NE &&
21642 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21643 CC = X86::GetOppositeBranchCondition(CC);
21644 std::swap(TrueOp, FalseOp);
21647 if (CC == X86::COND_E &&
21648 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21649 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21650 DAG.getConstant(CC, MVT::i8), Cond };
21651 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21656 // Fold and/or of setcc's to double CMOV:
21657 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
21658 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
21660 // This combine lets us generate:
21661 // cmovcc1 (jcc1 if we don't have CMOV)
21667 // cmovne (jne if we don't have CMOV)
21668 // When we can't use the CMOV instruction, it might increase branch
21670 // When we can use CMOV, or when there is no mispredict, this improves
21671 // throughput and reduces register pressure.
21673 if (CC == X86::COND_NE) {
21675 X86::CondCode CC0, CC1;
21677 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
21679 std::swap(FalseOp, TrueOp);
21680 CC0 = X86::GetOppositeBranchCondition(CC0);
21681 CC1 = X86::GetOppositeBranchCondition(CC1);
21684 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, MVT::i8),
21686 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
21687 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, MVT::i8), Flags};
21688 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21689 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
21697 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21698 const X86Subtarget *Subtarget) {
21699 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21701 default: return SDValue();
21702 // SSE/AVX/AVX2 blend intrinsics.
21703 case Intrinsic::x86_avx2_pblendvb:
21704 // Don't try to simplify this intrinsic if we don't have AVX2.
21705 if (!Subtarget->hasAVX2())
21708 case Intrinsic::x86_avx_blendv_pd_256:
21709 case Intrinsic::x86_avx_blendv_ps_256:
21710 // Don't try to simplify this intrinsic if we don't have AVX.
21711 if (!Subtarget->hasAVX())
21714 case Intrinsic::x86_sse41_blendvps:
21715 case Intrinsic::x86_sse41_blendvpd:
21716 case Intrinsic::x86_sse41_pblendvb: {
21717 SDValue Op0 = N->getOperand(1);
21718 SDValue Op1 = N->getOperand(2);
21719 SDValue Mask = N->getOperand(3);
21721 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21722 if (!Subtarget->hasSSE41())
21725 // fold (blend A, A, Mask) -> A
21728 // fold (blend A, B, allZeros) -> A
21729 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21731 // fold (blend A, B, allOnes) -> B
21732 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21735 // Simplify the case where the mask is a constant i32 value.
21736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21737 if (C->isNullValue())
21739 if (C->isAllOnesValue())
21746 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21747 case Intrinsic::x86_sse2_psrai_w:
21748 case Intrinsic::x86_sse2_psrai_d:
21749 case Intrinsic::x86_avx2_psrai_w:
21750 case Intrinsic::x86_avx2_psrai_d:
21751 case Intrinsic::x86_sse2_psra_w:
21752 case Intrinsic::x86_sse2_psra_d:
21753 case Intrinsic::x86_avx2_psra_w:
21754 case Intrinsic::x86_avx2_psra_d: {
21755 SDValue Op0 = N->getOperand(1);
21756 SDValue Op1 = N->getOperand(2);
21757 EVT VT = Op0.getValueType();
21758 assert(VT.isVector() && "Expected a vector type!");
21760 if (isa<BuildVectorSDNode>(Op1))
21761 Op1 = Op1.getOperand(0);
21763 if (!isa<ConstantSDNode>(Op1))
21766 EVT SVT = VT.getVectorElementType();
21767 unsigned SVTBits = SVT.getSizeInBits();
21769 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21770 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21771 uint64_t ShAmt = C.getZExtValue();
21773 // Don't try to convert this shift into a ISD::SRA if the shift
21774 // count is bigger than or equal to the element size.
21775 if (ShAmt >= SVTBits)
21778 // Trivial case: if the shift count is zero, then fold this
21779 // into the first operand.
21783 // Replace this packed shift intrinsic with a target independent
21785 SDValue Splat = DAG.getConstant(C, VT);
21786 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21791 /// PerformMulCombine - Optimize a single multiply with constant into two
21792 /// in order to implement it with two cheaper instructions, e.g.
21793 /// LEA + SHL, LEA + LEA.
21794 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21795 TargetLowering::DAGCombinerInfo &DCI) {
21796 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21799 EVT VT = N->getValueType(0);
21800 if (VT != MVT::i64 && VT != MVT::i32)
21803 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21806 uint64_t MulAmt = C->getZExtValue();
21807 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21810 uint64_t MulAmt1 = 0;
21811 uint64_t MulAmt2 = 0;
21812 if ((MulAmt % 9) == 0) {
21814 MulAmt2 = MulAmt / 9;
21815 } else if ((MulAmt % 5) == 0) {
21817 MulAmt2 = MulAmt / 5;
21818 } else if ((MulAmt % 3) == 0) {
21820 MulAmt2 = MulAmt / 3;
21823 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21826 if (isPowerOf2_64(MulAmt2) &&
21827 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21828 // If second multiplifer is pow2, issue it first. We want the multiply by
21829 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21831 std::swap(MulAmt1, MulAmt2);
21834 if (isPowerOf2_64(MulAmt1))
21835 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21836 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21838 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21839 DAG.getConstant(MulAmt1, VT));
21841 if (isPowerOf2_64(MulAmt2))
21842 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21843 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21845 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21846 DAG.getConstant(MulAmt2, VT));
21848 // Do not add new nodes to DAG combiner worklist.
21849 DCI.CombineTo(N, NewMul, false);
21854 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21855 SDValue N0 = N->getOperand(0);
21856 SDValue N1 = N->getOperand(1);
21857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21858 EVT VT = N0.getValueType();
21860 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21861 // since the result of setcc_c is all zero's or all ones.
21862 if (VT.isInteger() && !VT.isVector() &&
21863 N1C && N0.getOpcode() == ISD::AND &&
21864 N0.getOperand(1).getOpcode() == ISD::Constant) {
21865 SDValue N00 = N0.getOperand(0);
21866 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21867 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21868 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21869 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21870 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21871 APInt ShAmt = N1C->getAPIntValue();
21872 Mask = Mask.shl(ShAmt);
21874 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21875 N00, DAG.getConstant(Mask, VT));
21879 // Hardware support for vector shifts is sparse which makes us scalarize the
21880 // vector operations in many cases. Also, on sandybridge ADD is faster than
21882 // (shl V, 1) -> add V,V
21883 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21884 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21885 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21886 // We shift all of the values by one. In many cases we do not have
21887 // hardware support for this operation. This is better expressed as an ADD
21889 if (N1SplatC->getZExtValue() == 1)
21890 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21896 /// \brief Returns a vector of 0s if the node in input is a vector logical
21897 /// shift by a constant amount which is known to be bigger than or equal
21898 /// to the vector element size in bits.
21899 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21900 const X86Subtarget *Subtarget) {
21901 EVT VT = N->getValueType(0);
21903 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21904 (!Subtarget->hasInt256() ||
21905 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21908 SDValue Amt = N->getOperand(1);
21910 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21911 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21912 APInt ShiftAmt = AmtSplat->getAPIntValue();
21913 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21915 // SSE2/AVX2 logical shifts always return a vector of 0s
21916 // if the shift amount is bigger than or equal to
21917 // the element size. The constant shift amount will be
21918 // encoded as a 8-bit immediate.
21919 if (ShiftAmt.trunc(8).uge(MaxAmount))
21920 return getZeroVector(VT, Subtarget, DAG, DL);
21926 /// PerformShiftCombine - Combine shifts.
21927 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21928 TargetLowering::DAGCombinerInfo &DCI,
21929 const X86Subtarget *Subtarget) {
21930 if (N->getOpcode() == ISD::SHL) {
21931 SDValue V = PerformSHLCombine(N, DAG);
21932 if (V.getNode()) return V;
21935 if (N->getOpcode() != ISD::SRA) {
21936 // Try to fold this logical shift into a zero vector.
21937 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21938 if (V.getNode()) return V;
21944 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21945 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21946 // and friends. Likewise for OR -> CMPNEQSS.
21947 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21948 TargetLowering::DAGCombinerInfo &DCI,
21949 const X86Subtarget *Subtarget) {
21952 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21953 // we're requiring SSE2 for both.
21954 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21955 SDValue N0 = N->getOperand(0);
21956 SDValue N1 = N->getOperand(1);
21957 SDValue CMP0 = N0->getOperand(1);
21958 SDValue CMP1 = N1->getOperand(1);
21961 // The SETCCs should both refer to the same CMP.
21962 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21965 SDValue CMP00 = CMP0->getOperand(0);
21966 SDValue CMP01 = CMP0->getOperand(1);
21967 EVT VT = CMP00.getValueType();
21969 if (VT == MVT::f32 || VT == MVT::f64) {
21970 bool ExpectingFlags = false;
21971 // Check for any users that want flags:
21972 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21973 !ExpectingFlags && UI != UE; ++UI)
21974 switch (UI->getOpcode()) {
21979 ExpectingFlags = true;
21981 case ISD::CopyToReg:
21982 case ISD::SIGN_EXTEND:
21983 case ISD::ZERO_EXTEND:
21984 case ISD::ANY_EXTEND:
21988 if (!ExpectingFlags) {
21989 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21990 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21992 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21993 X86::CondCode tmp = cc0;
21998 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21999 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22000 // FIXME: need symbolic constants for these magic numbers.
22001 // See X86ATTInstPrinter.cpp:printSSECC().
22002 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22003 if (Subtarget->hasAVX512()) {
22004 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22005 CMP01, DAG.getConstant(x86cc, MVT::i8));
22006 if (N->getValueType(0) != MVT::i1)
22007 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22011 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22012 CMP00.getValueType(), CMP00, CMP01,
22013 DAG.getConstant(x86cc, MVT::i8));
22015 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22016 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22018 if (is64BitFP && !Subtarget->is64Bit()) {
22019 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22020 // 64-bit integer, since that's not a legal type. Since
22021 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22022 // bits, but can do this little dance to extract the lowest 32 bits
22023 // and work with those going forward.
22024 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22026 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22028 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22029 Vector32, DAG.getIntPtrConstant(0));
22033 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22034 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22035 DAG.getConstant(1, IntVT));
22036 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22037 return OneBitOfTruth;
22045 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22046 /// so it can be folded inside ANDNP.
22047 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22048 EVT VT = N->getValueType(0);
22050 // Match direct AllOnes for 128 and 256-bit vectors
22051 if (ISD::isBuildVectorAllOnes(N))
22054 // Look through a bit convert.
22055 if (N->getOpcode() == ISD::BITCAST)
22056 N = N->getOperand(0).getNode();
22058 // Sometimes the operand may come from a insert_subvector building a 256-bit
22060 if (VT.is256BitVector() &&
22061 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22062 SDValue V1 = N->getOperand(0);
22063 SDValue V2 = N->getOperand(1);
22065 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22066 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22067 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22068 ISD::isBuildVectorAllOnes(V2.getNode()))
22075 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22076 // register. In most cases we actually compare or select YMM-sized registers
22077 // and mixing the two types creates horrible code. This method optimizes
22078 // some of the transition sequences.
22079 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22080 TargetLowering::DAGCombinerInfo &DCI,
22081 const X86Subtarget *Subtarget) {
22082 EVT VT = N->getValueType(0);
22083 if (!VT.is256BitVector())
22086 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22087 N->getOpcode() == ISD::ZERO_EXTEND ||
22088 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22090 SDValue Narrow = N->getOperand(0);
22091 EVT NarrowVT = Narrow->getValueType(0);
22092 if (!NarrowVT.is128BitVector())
22095 if (Narrow->getOpcode() != ISD::XOR &&
22096 Narrow->getOpcode() != ISD::AND &&
22097 Narrow->getOpcode() != ISD::OR)
22100 SDValue N0 = Narrow->getOperand(0);
22101 SDValue N1 = Narrow->getOperand(1);
22104 // The Left side has to be a trunc.
22105 if (N0.getOpcode() != ISD::TRUNCATE)
22108 // The type of the truncated inputs.
22109 EVT WideVT = N0->getOperand(0)->getValueType(0);
22113 // The right side has to be a 'trunc' or a constant vector.
22114 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22115 ConstantSDNode *RHSConstSplat = nullptr;
22116 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22117 RHSConstSplat = RHSBV->getConstantSplatNode();
22118 if (!RHSTrunc && !RHSConstSplat)
22121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22123 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22126 // Set N0 and N1 to hold the inputs to the new wide operation.
22127 N0 = N0->getOperand(0);
22128 if (RHSConstSplat) {
22129 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22130 SDValue(RHSConstSplat, 0));
22131 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22132 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22133 } else if (RHSTrunc) {
22134 N1 = N1->getOperand(0);
22137 // Generate the wide operation.
22138 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22139 unsigned Opcode = N->getOpcode();
22141 case ISD::ANY_EXTEND:
22143 case ISD::ZERO_EXTEND: {
22144 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22145 APInt Mask = APInt::getAllOnesValue(InBits);
22146 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22147 return DAG.getNode(ISD::AND, DL, VT,
22148 Op, DAG.getConstant(Mask, VT));
22150 case ISD::SIGN_EXTEND:
22151 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22152 Op, DAG.getValueType(NarrowVT));
22154 llvm_unreachable("Unexpected opcode");
22158 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22159 TargetLowering::DAGCombinerInfo &DCI,
22160 const X86Subtarget *Subtarget) {
22161 SDValue N0 = N->getOperand(0);
22162 SDValue N1 = N->getOperand(1);
22165 // A vector zext_in_reg may be represented as a shuffle,
22166 // feeding into a bitcast (this represents anyext) feeding into
22167 // an and with a mask.
22168 // We'd like to try to combine that into a shuffle with zero
22169 // plus a bitcast, removing the and.
22170 if (N0.getOpcode() != ISD::BITCAST ||
22171 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22174 // The other side of the AND should be a splat of 2^C, where C
22175 // is the number of bits in the source type.
22176 if (N1.getOpcode() == ISD::BITCAST)
22177 N1 = N1.getOperand(0);
22178 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22180 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22182 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22183 EVT SrcType = Shuffle->getValueType(0);
22185 // We expect a single-source shuffle
22186 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22189 unsigned SrcSize = SrcType.getScalarSizeInBits();
22191 APInt SplatValue, SplatUndef;
22192 unsigned SplatBitSize;
22194 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22195 SplatBitSize, HasAnyUndefs))
22198 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22199 // Make sure the splat matches the mask we expect
22200 if (SplatBitSize > ResSize ||
22201 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22204 // Make sure the input and output size make sense
22205 if (SrcSize >= ResSize || ResSize % SrcSize)
22208 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22209 // The number of u's between each two values depends on the ratio between
22210 // the source and dest type.
22211 unsigned ZextRatio = ResSize / SrcSize;
22212 bool IsZext = true;
22213 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22214 if (i % ZextRatio) {
22215 if (Shuffle->getMaskElt(i) > 0) {
22221 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22222 // Expected element number
22232 // Ok, perform the transformation - replace the shuffle with
22233 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22234 // (instead of undef) where the k elements come from the zero vector.
22235 SmallVector<int, 8> Mask;
22236 unsigned NumElems = SrcType.getVectorNumElements();
22237 for (unsigned i = 0; i < NumElems; ++i)
22239 Mask.push_back(NumElems);
22241 Mask.push_back(i / ZextRatio);
22243 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22244 Shuffle->getOperand(0), DAG.getConstant(0, SrcType), Mask);
22245 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22248 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22249 TargetLowering::DAGCombinerInfo &DCI,
22250 const X86Subtarget *Subtarget) {
22251 if (DCI.isBeforeLegalizeOps())
22254 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22257 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22260 EVT VT = N->getValueType(0);
22261 SDValue N0 = N->getOperand(0);
22262 SDValue N1 = N->getOperand(1);
22265 // Create BEXTR instructions
22266 // BEXTR is ((X >> imm) & (2**size-1))
22267 if (VT == MVT::i32 || VT == MVT::i64) {
22268 // Check for BEXTR.
22269 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22270 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22271 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22272 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22273 if (MaskNode && ShiftNode) {
22274 uint64_t Mask = MaskNode->getZExtValue();
22275 uint64_t Shift = ShiftNode->getZExtValue();
22276 if (isMask_64(Mask)) {
22277 uint64_t MaskSize = countPopulation(Mask);
22278 if (Shift + MaskSize <= VT.getSizeInBits())
22279 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22280 DAG.getConstant(Shift | (MaskSize << 8), VT));
22288 // Want to form ANDNP nodes:
22289 // 1) In the hopes of then easily combining them with OR and AND nodes
22290 // to form PBLEND/PSIGN.
22291 // 2) To match ANDN packed intrinsics
22292 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22295 // Check LHS for vnot
22296 if (N0.getOpcode() == ISD::XOR &&
22297 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22298 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22299 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22301 // Check RHS for vnot
22302 if (N1.getOpcode() == ISD::XOR &&
22303 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22304 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22305 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22310 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22311 TargetLowering::DAGCombinerInfo &DCI,
22312 const X86Subtarget *Subtarget) {
22313 if (DCI.isBeforeLegalizeOps())
22316 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22320 SDValue N0 = N->getOperand(0);
22321 SDValue N1 = N->getOperand(1);
22322 EVT VT = N->getValueType(0);
22324 // look for psign/blend
22325 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22326 if (!Subtarget->hasSSSE3() ||
22327 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22330 // Canonicalize pandn to RHS
22331 if (N0.getOpcode() == X86ISD::ANDNP)
22333 // or (and (m, y), (pandn m, x))
22334 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22335 SDValue Mask = N1.getOperand(0);
22336 SDValue X = N1.getOperand(1);
22338 if (N0.getOperand(0) == Mask)
22339 Y = N0.getOperand(1);
22340 if (N0.getOperand(1) == Mask)
22341 Y = N0.getOperand(0);
22343 // Check to see if the mask appeared in both the AND and ANDNP and
22347 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22348 // Look through mask bitcast.
22349 if (Mask.getOpcode() == ISD::BITCAST)
22350 Mask = Mask.getOperand(0);
22351 if (X.getOpcode() == ISD::BITCAST)
22352 X = X.getOperand(0);
22353 if (Y.getOpcode() == ISD::BITCAST)
22354 Y = Y.getOperand(0);
22356 EVT MaskVT = Mask.getValueType();
22358 // Validate that the Mask operand is a vector sra node.
22359 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22360 // there is no psrai.b
22361 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22362 unsigned SraAmt = ~0;
22363 if (Mask.getOpcode() == ISD::SRA) {
22364 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22365 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22366 SraAmt = AmtConst->getZExtValue();
22367 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22368 SDValue SraC = Mask.getOperand(1);
22369 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22371 if ((SraAmt + 1) != EltBits)
22376 // Now we know we at least have a plendvb with the mask val. See if
22377 // we can form a psignb/w/d.
22378 // psign = x.type == y.type == mask.type && y = sub(0, x);
22379 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22380 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22381 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22382 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22383 "Unsupported VT for PSIGN");
22384 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22385 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22387 // PBLENDVB only available on SSE 4.1
22388 if (!Subtarget->hasSSE41())
22391 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22393 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22394 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22395 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22396 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22397 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22401 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22404 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22405 MachineFunction &MF = DAG.getMachineFunction();
22407 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
22409 // SHLD/SHRD instructions have lower register pressure, but on some
22410 // platforms they have higher latency than the equivalent
22411 // series of shifts/or that would otherwise be generated.
22412 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22413 // have higher latencies and we are not optimizing for size.
22414 if (!OptForSize && Subtarget->isSHLDSlow())
22417 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22419 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22421 if (!N0.hasOneUse() || !N1.hasOneUse())
22424 SDValue ShAmt0 = N0.getOperand(1);
22425 if (ShAmt0.getValueType() != MVT::i8)
22427 SDValue ShAmt1 = N1.getOperand(1);
22428 if (ShAmt1.getValueType() != MVT::i8)
22430 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22431 ShAmt0 = ShAmt0.getOperand(0);
22432 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22433 ShAmt1 = ShAmt1.getOperand(0);
22436 unsigned Opc = X86ISD::SHLD;
22437 SDValue Op0 = N0.getOperand(0);
22438 SDValue Op1 = N1.getOperand(0);
22439 if (ShAmt0.getOpcode() == ISD::SUB) {
22440 Opc = X86ISD::SHRD;
22441 std::swap(Op0, Op1);
22442 std::swap(ShAmt0, ShAmt1);
22445 unsigned Bits = VT.getSizeInBits();
22446 if (ShAmt1.getOpcode() == ISD::SUB) {
22447 SDValue Sum = ShAmt1.getOperand(0);
22448 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22449 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22450 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22451 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22452 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22453 return DAG.getNode(Opc, DL, VT,
22455 DAG.getNode(ISD::TRUNCATE, DL,
22458 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22459 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22461 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22462 return DAG.getNode(Opc, DL, VT,
22463 N0.getOperand(0), N1.getOperand(0),
22464 DAG.getNode(ISD::TRUNCATE, DL,
22471 // Generate NEG and CMOV for integer abs.
22472 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22473 EVT VT = N->getValueType(0);
22475 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22476 // 8-bit integer abs to NEG and CMOV.
22477 if (VT.isInteger() && VT.getSizeInBits() == 8)
22480 SDValue N0 = N->getOperand(0);
22481 SDValue N1 = N->getOperand(1);
22484 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22485 // and change it to SUB and CMOV.
22486 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22487 N0.getOpcode() == ISD::ADD &&
22488 N0.getOperand(1) == N1 &&
22489 N1.getOpcode() == ISD::SRA &&
22490 N1.getOperand(0) == N0.getOperand(0))
22491 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22492 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22493 // Generate SUB & CMOV.
22494 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22495 DAG.getConstant(0, VT), N0.getOperand(0));
22497 SDValue Ops[] = { N0.getOperand(0), Neg,
22498 DAG.getConstant(X86::COND_GE, MVT::i8),
22499 SDValue(Neg.getNode(), 1) };
22500 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22505 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22506 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22507 TargetLowering::DAGCombinerInfo &DCI,
22508 const X86Subtarget *Subtarget) {
22509 if (DCI.isBeforeLegalizeOps())
22512 if (Subtarget->hasCMov()) {
22513 SDValue RV = performIntegerAbsCombine(N, DAG);
22521 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22522 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22523 TargetLowering::DAGCombinerInfo &DCI,
22524 const X86Subtarget *Subtarget) {
22525 LoadSDNode *Ld = cast<LoadSDNode>(N);
22526 EVT RegVT = Ld->getValueType(0);
22527 EVT MemVT = Ld->getMemoryVT();
22529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22531 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
22532 // into two 16-byte operations.
22533 ISD::LoadExtType Ext = Ld->getExtensionType();
22534 unsigned Alignment = Ld->getAlignment();
22535 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22536 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22537 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22538 unsigned NumElems = RegVT.getVectorNumElements();
22542 SDValue Ptr = Ld->getBasePtr();
22543 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22545 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22547 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22548 Ld->getPointerInfo(), Ld->isVolatile(),
22549 Ld->isNonTemporal(), Ld->isInvariant(),
22551 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22552 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22553 Ld->getPointerInfo(), Ld->isVolatile(),
22554 Ld->isNonTemporal(), Ld->isInvariant(),
22555 std::min(16U, Alignment));
22556 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22558 Load2.getValue(1));
22560 SDValue NewVec = DAG.getUNDEF(RegVT);
22561 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22562 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22563 return DCI.CombineTo(N, NewVec, TF, true);
22569 /// PerformMLOADCombine - Resolve extending loads
22570 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
22571 TargetLowering::DAGCombinerInfo &DCI,
22572 const X86Subtarget *Subtarget) {
22573 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
22574 if (Mld->getExtensionType() != ISD::SEXTLOAD)
22577 EVT VT = Mld->getValueType(0);
22578 unsigned NumElems = VT.getVectorNumElements();
22579 EVT LdVT = Mld->getMemoryVT();
22582 assert(LdVT != VT && "Cannot extend to the same type");
22583 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
22584 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
22585 // From, To sizes and ElemCount must be pow of two
22586 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22587 "Unexpected size for extending masked load");
22589 unsigned SizeRatio = ToSz / FromSz;
22590 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
22592 // Create a type on which we perform the shuffle
22593 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22594 LdVT.getScalarType(), NumElems*SizeRatio);
22595 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22597 // Convert Src0 value
22598 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
22599 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
22600 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22601 for (unsigned i = 0; i != NumElems; ++i)
22602 ShuffleVec[i] = i * SizeRatio;
22604 // Can't shuffle using an illegal type.
22605 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22606 && "WideVecVT should be legal");
22607 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
22608 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
22610 // Prepare the new mask
22612 SDValue Mask = Mld->getMask();
22613 if (Mask.getValueType() == VT) {
22614 // Mask and original value have the same type
22615 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22616 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22617 for (unsigned i = 0; i != NumElems; ++i)
22618 ShuffleVec[i] = i * SizeRatio;
22619 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22620 ShuffleVec[i] = NumElems*SizeRatio;
22621 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22622 DAG.getConstant(0, WideVecVT),
22626 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22627 unsigned WidenNumElts = NumElems*SizeRatio;
22628 unsigned MaskNumElts = VT.getVectorNumElements();
22629 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22632 unsigned NumConcat = WidenNumElts / MaskNumElts;
22633 SmallVector<SDValue, 16> Ops(NumConcat);
22634 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22636 for (unsigned i = 1; i != NumConcat; ++i)
22639 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22642 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
22643 Mld->getBasePtr(), NewMask, WideSrc0,
22644 Mld->getMemoryVT(), Mld->getMemOperand(),
22646 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
22647 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
22650 /// PerformMSTORECombine - Resolve truncating stores
22651 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
22652 const X86Subtarget *Subtarget) {
22653 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
22654 if (!Mst->isTruncatingStore())
22657 EVT VT = Mst->getValue().getValueType();
22658 unsigned NumElems = VT.getVectorNumElements();
22659 EVT StVT = Mst->getMemoryVT();
22662 assert(StVT != VT && "Cannot truncate to the same type");
22663 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22664 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22666 // From, To sizes and ElemCount must be pow of two
22667 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22668 "Unexpected size for truncating masked store");
22669 // We are going to use the original vector elt for storing.
22670 // Accumulated smaller vector elements must be a multiple of the store size.
22671 assert (((NumElems * FromSz) % ToSz) == 0 &&
22672 "Unexpected ratio for truncating masked store");
22674 unsigned SizeRatio = FromSz / ToSz;
22675 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22677 // Create a type on which we perform the shuffle
22678 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22679 StVT.getScalarType(), NumElems*SizeRatio);
22681 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22683 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
22684 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22685 for (unsigned i = 0; i != NumElems; ++i)
22686 ShuffleVec[i] = i * SizeRatio;
22688 // Can't shuffle using an illegal type.
22689 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22690 && "WideVecVT should be legal");
22692 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22693 DAG.getUNDEF(WideVecVT),
22697 SDValue Mask = Mst->getMask();
22698 if (Mask.getValueType() == VT) {
22699 // Mask and original value have the same type
22700 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22701 for (unsigned i = 0; i != NumElems; ++i)
22702 ShuffleVec[i] = i * SizeRatio;
22703 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22704 ShuffleVec[i] = NumElems*SizeRatio;
22705 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22706 DAG.getConstant(0, WideVecVT),
22710 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22711 unsigned WidenNumElts = NumElems*SizeRatio;
22712 unsigned MaskNumElts = VT.getVectorNumElements();
22713 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22716 unsigned NumConcat = WidenNumElts / MaskNumElts;
22717 SmallVector<SDValue, 16> Ops(NumConcat);
22718 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22720 for (unsigned i = 1; i != NumConcat; ++i)
22723 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22726 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
22727 NewMask, StVT, Mst->getMemOperand(), false);
22729 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22730 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22731 const X86Subtarget *Subtarget) {
22732 StoreSDNode *St = cast<StoreSDNode>(N);
22733 EVT VT = St->getValue().getValueType();
22734 EVT StVT = St->getMemoryVT();
22736 SDValue StoredVal = St->getOperand(1);
22737 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22739 // If we are saving a concatenation of two XMM registers and 32-byte stores
22740 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
22741 unsigned Alignment = St->getAlignment();
22742 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22743 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22744 StVT == VT && !IsAligned) {
22745 unsigned NumElems = VT.getVectorNumElements();
22749 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22750 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22752 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22753 SDValue Ptr0 = St->getBasePtr();
22754 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22756 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22757 St->getPointerInfo(), St->isVolatile(),
22758 St->isNonTemporal(), Alignment);
22759 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22760 St->getPointerInfo(), St->isVolatile(),
22761 St->isNonTemporal(),
22762 std::min(16U, Alignment));
22763 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22766 // Optimize trunc store (of multiple scalars) to shuffle and store.
22767 // First, pack all of the elements in one place. Next, store to memory
22768 // in fewer chunks.
22769 if (St->isTruncatingStore() && VT.isVector()) {
22770 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22771 unsigned NumElems = VT.getVectorNumElements();
22772 assert(StVT != VT && "Cannot truncate to the same type");
22773 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22774 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22776 // From, To sizes and ElemCount must be pow of two
22777 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22778 // We are going to use the original vector elt for storing.
22779 // Accumulated smaller vector elements must be a multiple of the store size.
22780 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22782 unsigned SizeRatio = FromSz / ToSz;
22784 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22786 // Create a type on which we perform the shuffle
22787 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22788 StVT.getScalarType(), NumElems*SizeRatio);
22790 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22792 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22793 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22794 for (unsigned i = 0; i != NumElems; ++i)
22795 ShuffleVec[i] = i * SizeRatio;
22797 // Can't shuffle using an illegal type.
22798 if (!TLI.isTypeLegal(WideVecVT))
22801 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22802 DAG.getUNDEF(WideVecVT),
22804 // At this point all of the data is stored at the bottom of the
22805 // register. We now need to save it to mem.
22807 // Find the largest store unit
22808 MVT StoreType = MVT::i8;
22809 for (MVT Tp : MVT::integer_valuetypes()) {
22810 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22814 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22815 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22816 (64 <= NumElems * ToSz))
22817 StoreType = MVT::f64;
22819 // Bitcast the original vector into a vector of store-size units
22820 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22821 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22822 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22823 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22824 SmallVector<SDValue, 8> Chains;
22825 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22826 TLI.getPointerTy());
22827 SDValue Ptr = St->getBasePtr();
22829 // Perform one or more big stores into memory.
22830 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22831 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22832 StoreType, ShuffWide,
22833 DAG.getIntPtrConstant(i));
22834 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22835 St->getPointerInfo(), St->isVolatile(),
22836 St->isNonTemporal(), St->getAlignment());
22837 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22838 Chains.push_back(Ch);
22841 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22844 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22845 // the FP state in cases where an emms may be missing.
22846 // A preferable solution to the general problem is to figure out the right
22847 // places to insert EMMS. This qualifies as a quick hack.
22849 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22850 if (VT.getSizeInBits() != 64)
22853 const Function *F = DAG.getMachineFunction().getFunction();
22854 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
22855 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22856 && Subtarget->hasSSE2();
22857 if ((VT.isVector() ||
22858 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22859 isa<LoadSDNode>(St->getValue()) &&
22860 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22861 St->getChain().hasOneUse() && !St->isVolatile()) {
22862 SDNode* LdVal = St->getValue().getNode();
22863 LoadSDNode *Ld = nullptr;
22864 int TokenFactorIndex = -1;
22865 SmallVector<SDValue, 8> Ops;
22866 SDNode* ChainVal = St->getChain().getNode();
22867 // Must be a store of a load. We currently handle two cases: the load
22868 // is a direct child, and it's under an intervening TokenFactor. It is
22869 // possible to dig deeper under nested TokenFactors.
22870 if (ChainVal == LdVal)
22871 Ld = cast<LoadSDNode>(St->getChain());
22872 else if (St->getValue().hasOneUse() &&
22873 ChainVal->getOpcode() == ISD::TokenFactor) {
22874 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22875 if (ChainVal->getOperand(i).getNode() == LdVal) {
22876 TokenFactorIndex = i;
22877 Ld = cast<LoadSDNode>(St->getValue());
22879 Ops.push_back(ChainVal->getOperand(i));
22883 if (!Ld || !ISD::isNormalLoad(Ld))
22886 // If this is not the MMX case, i.e. we are just turning i64 load/store
22887 // into f64 load/store, avoid the transformation if there are multiple
22888 // uses of the loaded value.
22889 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22894 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22895 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22897 if (Subtarget->is64Bit() || F64IsLegal) {
22898 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22899 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22900 Ld->getPointerInfo(), Ld->isVolatile(),
22901 Ld->isNonTemporal(), Ld->isInvariant(),
22902 Ld->getAlignment());
22903 SDValue NewChain = NewLd.getValue(1);
22904 if (TokenFactorIndex != -1) {
22905 Ops.push_back(NewChain);
22906 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22908 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22909 St->getPointerInfo(),
22910 St->isVolatile(), St->isNonTemporal(),
22911 St->getAlignment());
22914 // Otherwise, lower to two pairs of 32-bit loads / stores.
22915 SDValue LoAddr = Ld->getBasePtr();
22916 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22917 DAG.getConstant(4, MVT::i32));
22919 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22920 Ld->getPointerInfo(),
22921 Ld->isVolatile(), Ld->isNonTemporal(),
22922 Ld->isInvariant(), Ld->getAlignment());
22923 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22924 Ld->getPointerInfo().getWithOffset(4),
22925 Ld->isVolatile(), Ld->isNonTemporal(),
22927 MinAlign(Ld->getAlignment(), 4));
22929 SDValue NewChain = LoLd.getValue(1);
22930 if (TokenFactorIndex != -1) {
22931 Ops.push_back(LoLd);
22932 Ops.push_back(HiLd);
22933 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22936 LoAddr = St->getBasePtr();
22937 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22938 DAG.getConstant(4, MVT::i32));
22940 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22941 St->getPointerInfo(),
22942 St->isVolatile(), St->isNonTemporal(),
22943 St->getAlignment());
22944 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22945 St->getPointerInfo().getWithOffset(4),
22947 St->isNonTemporal(),
22948 MinAlign(St->getAlignment(), 4));
22949 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22952 // This is similar to the above case, but here we handle a scalar 64-bit
22953 // integer store that is extracted from a vector on a 32-bit target.
22954 // If we have SSE2, then we can treat it like a floating-point double
22955 // to get past legalization. The execution dependencies fixup pass will
22956 // choose the optimal machine instruction for the store if this really is
22957 // an integer or v2f32 rather than an f64.
22958 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
22959 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
22960 SDValue OldExtract = St->getOperand(1);
22961 SDValue ExtOp0 = OldExtract.getOperand(0);
22962 unsigned VecSize = ExtOp0.getValueSizeInBits();
22963 MVT VecVT = MVT::getVectorVT(MVT::f64, VecSize / 64);
22964 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
22965 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
22966 BitCast, OldExtract.getOperand(1));
22967 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
22968 St->getPointerInfo(), St->isVolatile(),
22969 St->isNonTemporal(), St->getAlignment());
22975 /// Return 'true' if this vector operation is "horizontal"
22976 /// and return the operands for the horizontal operation in LHS and RHS. A
22977 /// horizontal operation performs the binary operation on successive elements
22978 /// of its first operand, then on successive elements of its second operand,
22979 /// returning the resulting values in a vector. For example, if
22980 /// A = < float a0, float a1, float a2, float a3 >
22982 /// B = < float b0, float b1, float b2, float b3 >
22983 /// then the result of doing a horizontal operation on A and B is
22984 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22985 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22986 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22987 /// set to A, RHS to B, and the routine returns 'true'.
22988 /// Note that the binary operation should have the property that if one of the
22989 /// operands is UNDEF then the result is UNDEF.
22990 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22991 // Look for the following pattern: if
22992 // A = < float a0, float a1, float a2, float a3 >
22993 // B = < float b0, float b1, float b2, float b3 >
22995 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22996 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22997 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22998 // which is A horizontal-op B.
23000 // At least one of the operands should be a vector shuffle.
23001 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23002 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23005 MVT VT = LHS.getSimpleValueType();
23007 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23008 "Unsupported vector type for horizontal add/sub");
23010 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23011 // operate independently on 128-bit lanes.
23012 unsigned NumElts = VT.getVectorNumElements();
23013 unsigned NumLanes = VT.getSizeInBits()/128;
23014 unsigned NumLaneElts = NumElts / NumLanes;
23015 assert((NumLaneElts % 2 == 0) &&
23016 "Vector type should have an even number of elements in each lane");
23017 unsigned HalfLaneElts = NumLaneElts/2;
23019 // View LHS in the form
23020 // LHS = VECTOR_SHUFFLE A, B, LMask
23021 // If LHS is not a shuffle then pretend it is the shuffle
23022 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23023 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23026 SmallVector<int, 16> LMask(NumElts);
23027 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23028 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23029 A = LHS.getOperand(0);
23030 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23031 B = LHS.getOperand(1);
23032 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23033 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23035 if (LHS.getOpcode() != ISD::UNDEF)
23037 for (unsigned i = 0; i != NumElts; ++i)
23041 // Likewise, view RHS in the form
23042 // RHS = VECTOR_SHUFFLE C, D, RMask
23044 SmallVector<int, 16> RMask(NumElts);
23045 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23046 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23047 C = RHS.getOperand(0);
23048 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23049 D = RHS.getOperand(1);
23050 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23051 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23053 if (RHS.getOpcode() != ISD::UNDEF)
23055 for (unsigned i = 0; i != NumElts; ++i)
23059 // Check that the shuffles are both shuffling the same vectors.
23060 if (!(A == C && B == D) && !(A == D && B == C))
23063 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23064 if (!A.getNode() && !B.getNode())
23067 // If A and B occur in reverse order in RHS, then "swap" them (which means
23068 // rewriting the mask).
23070 ShuffleVectorSDNode::commuteMask(RMask);
23072 // At this point LHS and RHS are equivalent to
23073 // LHS = VECTOR_SHUFFLE A, B, LMask
23074 // RHS = VECTOR_SHUFFLE A, B, RMask
23075 // Check that the masks correspond to performing a horizontal operation.
23076 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23077 for (unsigned i = 0; i != NumLaneElts; ++i) {
23078 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23080 // Ignore any UNDEF components.
23081 if (LIdx < 0 || RIdx < 0 ||
23082 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23083 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23086 // Check that successive elements are being operated on. If not, this is
23087 // not a horizontal operation.
23088 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23089 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23090 if (!(LIdx == Index && RIdx == Index + 1) &&
23091 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23096 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23097 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23101 /// Do target-specific dag combines on floating point adds.
23102 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23103 const X86Subtarget *Subtarget) {
23104 EVT VT = N->getValueType(0);
23105 SDValue LHS = N->getOperand(0);
23106 SDValue RHS = N->getOperand(1);
23108 // Try to synthesize horizontal adds from adds of shuffles.
23109 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23110 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23111 isHorizontalBinOp(LHS, RHS, true))
23112 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23116 /// Do target-specific dag combines on floating point subs.
23117 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23118 const X86Subtarget *Subtarget) {
23119 EVT VT = N->getValueType(0);
23120 SDValue LHS = N->getOperand(0);
23121 SDValue RHS = N->getOperand(1);
23123 // Try to synthesize horizontal subs from subs of shuffles.
23124 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23125 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23126 isHorizontalBinOp(LHS, RHS, false))
23127 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23131 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23132 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23133 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23135 // F[X]OR(0.0, x) -> x
23136 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23137 if (C->getValueAPF().isPosZero())
23138 return N->getOperand(1);
23140 // F[X]OR(x, 0.0) -> x
23141 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23142 if (C->getValueAPF().isPosZero())
23143 return N->getOperand(0);
23147 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23148 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23149 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23151 // Only perform optimizations if UnsafeMath is used.
23152 if (!DAG.getTarget().Options.UnsafeFPMath)
23155 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23156 // into FMINC and FMAXC, which are Commutative operations.
23157 unsigned NewOp = 0;
23158 switch (N->getOpcode()) {
23159 default: llvm_unreachable("unknown opcode");
23160 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23161 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23164 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23165 N->getOperand(0), N->getOperand(1));
23168 /// Do target-specific dag combines on X86ISD::FAND nodes.
23169 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23170 // FAND(0.0, x) -> 0.0
23171 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23172 if (C->getValueAPF().isPosZero())
23173 return N->getOperand(0);
23175 // FAND(x, 0.0) -> 0.0
23176 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23177 if (C->getValueAPF().isPosZero())
23178 return N->getOperand(1);
23183 /// Do target-specific dag combines on X86ISD::FANDN nodes
23184 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23185 // FANDN(0.0, x) -> x
23186 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23187 if (C->getValueAPF().isPosZero())
23188 return N->getOperand(1);
23190 // FANDN(x, 0.0) -> 0.0
23191 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23192 if (C->getValueAPF().isPosZero())
23193 return N->getOperand(1);
23198 static SDValue PerformBTCombine(SDNode *N,
23200 TargetLowering::DAGCombinerInfo &DCI) {
23201 // BT ignores high bits in the bit index operand.
23202 SDValue Op1 = N->getOperand(1);
23203 if (Op1.hasOneUse()) {
23204 unsigned BitWidth = Op1.getValueSizeInBits();
23205 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23206 APInt KnownZero, KnownOne;
23207 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23208 !DCI.isBeforeLegalizeOps());
23209 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23210 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23211 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23212 DCI.CommitTargetLoweringOpt(TLO);
23217 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23218 SDValue Op = N->getOperand(0);
23219 if (Op.getOpcode() == ISD::BITCAST)
23220 Op = Op.getOperand(0);
23221 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23222 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23223 VT.getVectorElementType().getSizeInBits() ==
23224 OpVT.getVectorElementType().getSizeInBits()) {
23225 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23230 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23231 const X86Subtarget *Subtarget) {
23232 EVT VT = N->getValueType(0);
23233 if (!VT.isVector())
23236 SDValue N0 = N->getOperand(0);
23237 SDValue N1 = N->getOperand(1);
23238 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23241 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23242 // both SSE and AVX2 since there is no sign-extended shift right
23243 // operation on a vector with 64-bit elements.
23244 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23245 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23246 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23247 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23248 SDValue N00 = N0.getOperand(0);
23250 // EXTLOAD has a better solution on AVX2,
23251 // it may be replaced with X86ISD::VSEXT node.
23252 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23253 if (!ISD::isNormalLoad(N00.getNode()))
23256 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23257 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23259 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23265 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23266 TargetLowering::DAGCombinerInfo &DCI,
23267 const X86Subtarget *Subtarget) {
23268 SDValue N0 = N->getOperand(0);
23269 EVT VT = N->getValueType(0);
23271 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23272 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23273 // This exposes the sext to the sdivrem lowering, so that it directly extends
23274 // from AH (which we otherwise need to do contortions to access).
23275 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23276 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
23278 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23279 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
23280 N0.getOperand(0), N0.getOperand(1));
23281 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23282 return R.getValue(1);
23285 if (!DCI.isBeforeLegalizeOps())
23288 if (!Subtarget->hasFp256())
23291 if (VT.isVector() && VT.getSizeInBits() == 256) {
23292 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23300 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23301 const X86Subtarget* Subtarget) {
23303 EVT VT = N->getValueType(0);
23305 // Let legalize expand this if it isn't a legal type yet.
23306 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23309 EVT ScalarVT = VT.getScalarType();
23310 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23311 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23314 SDValue A = N->getOperand(0);
23315 SDValue B = N->getOperand(1);
23316 SDValue C = N->getOperand(2);
23318 bool NegA = (A.getOpcode() == ISD::FNEG);
23319 bool NegB = (B.getOpcode() == ISD::FNEG);
23320 bool NegC = (C.getOpcode() == ISD::FNEG);
23322 // Negative multiplication when NegA xor NegB
23323 bool NegMul = (NegA != NegB);
23325 A = A.getOperand(0);
23327 B = B.getOperand(0);
23329 C = C.getOperand(0);
23333 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23335 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23337 return DAG.getNode(Opcode, dl, VT, A, B, C);
23340 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23341 TargetLowering::DAGCombinerInfo &DCI,
23342 const X86Subtarget *Subtarget) {
23343 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23344 // (and (i32 x86isd::setcc_carry), 1)
23345 // This eliminates the zext. This transformation is necessary because
23346 // ISD::SETCC is always legalized to i8.
23348 SDValue N0 = N->getOperand(0);
23349 EVT VT = N->getValueType(0);
23351 if (N0.getOpcode() == ISD::AND &&
23353 N0.getOperand(0).hasOneUse()) {
23354 SDValue N00 = N0.getOperand(0);
23355 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23356 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23357 if (!C || C->getZExtValue() != 1)
23359 return DAG.getNode(ISD::AND, dl, VT,
23360 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23361 N00.getOperand(0), N00.getOperand(1)),
23362 DAG.getConstant(1, VT));
23366 if (N0.getOpcode() == ISD::TRUNCATE &&
23368 N0.getOperand(0).hasOneUse()) {
23369 SDValue N00 = N0.getOperand(0);
23370 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23371 return DAG.getNode(ISD::AND, dl, VT,
23372 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23373 N00.getOperand(0), N00.getOperand(1)),
23374 DAG.getConstant(1, VT));
23377 if (VT.is256BitVector()) {
23378 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23383 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
23384 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
23385 // This exposes the zext to the udivrem lowering, so that it directly extends
23386 // from AH (which we otherwise need to do contortions to access).
23387 if (N0.getOpcode() == ISD::UDIVREM &&
23388 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
23389 (VT == MVT::i32 || VT == MVT::i64)) {
23390 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23391 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
23392 N0.getOperand(0), N0.getOperand(1));
23393 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23394 return R.getValue(1);
23400 // Optimize x == -y --> x+y == 0
23401 // x != -y --> x+y != 0
23402 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23403 const X86Subtarget* Subtarget) {
23404 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23405 SDValue LHS = N->getOperand(0);
23406 SDValue RHS = N->getOperand(1);
23407 EVT VT = N->getValueType(0);
23410 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23411 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23412 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23413 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), LHS.getValueType(), RHS,
23414 LHS.getOperand(1));
23415 return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
23416 DAG.getConstant(0, addV.getValueType()), CC);
23418 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23419 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23420 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23421 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), RHS.getValueType(), LHS,
23422 RHS.getOperand(1));
23423 return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
23424 DAG.getConstant(0, addV.getValueType()), CC);
23427 if (VT.getScalarType() == MVT::i1 &&
23428 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
23430 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23431 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23432 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23434 if (!IsSEXT0 || !IsVZero1) {
23435 // Swap the operands and update the condition code.
23436 std::swap(LHS, RHS);
23437 CC = ISD::getSetCCSwappedOperands(CC);
23439 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23440 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23441 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23444 if (IsSEXT0 && IsVZero1) {
23445 assert(VT == LHS.getOperand(0).getValueType() &&
23446 "Uexpected operand type");
23447 if (CC == ISD::SETGT)
23448 return DAG.getConstant(0, VT);
23449 if (CC == ISD::SETLE)
23450 return DAG.getConstant(1, VT);
23451 if (CC == ISD::SETEQ || CC == ISD::SETGE)
23452 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23454 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
23455 "Unexpected condition code!");
23456 return LHS.getOperand(0);
23463 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
23464 SelectionDAG &DAG) {
23466 MVT VT = Load->getSimpleValueType(0);
23467 MVT EVT = VT.getVectorElementType();
23468 SDValue Addr = Load->getOperand(1);
23469 SDValue NewAddr = DAG.getNode(
23470 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
23471 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
23474 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
23475 DAG.getMachineFunction().getMachineMemOperand(
23476 Load->getMemOperand(), 0, EVT.getStoreSize()));
23480 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23481 const X86Subtarget *Subtarget) {
23483 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23484 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23485 "X86insertps is only defined for v4x32");
23487 SDValue Ld = N->getOperand(1);
23488 if (MayFoldLoad(Ld)) {
23489 // Extract the countS bits from the immediate so we can get the proper
23490 // address when narrowing the vector load to a specific element.
23491 // When the second source op is a memory address, insertps doesn't use
23492 // countS and just gets an f32 from that address.
23493 unsigned DestIndex =
23494 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23496 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23498 // Create this as a scalar to vector to match the instruction pattern.
23499 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23500 // countS bits are ignored when loading from memory on insertps, which
23501 // means we don't need to explicitly set them to 0.
23502 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23503 LoadScalarToVector, N->getOperand(2));
23508 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
23509 SDValue V0 = N->getOperand(0);
23510 SDValue V1 = N->getOperand(1);
23512 EVT VT = N->getValueType(0);
23514 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
23515 // operands and changing the mask to 1. This saves us a bunch of
23516 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
23517 // x86InstrInfo knows how to commute this back after instruction selection
23518 // if it would help register allocation.
23520 // TODO: If optimizing for size or a processor that doesn't suffer from
23521 // partial register update stalls, this should be transformed into a MOVSD
23522 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
23524 if (VT == MVT::v2f64)
23525 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23526 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23527 SDValue NewMask = DAG.getConstant(1, MVT::i8);
23528 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23534 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23535 // as "sbb reg,reg", since it can be extended without zext and produces
23536 // an all-ones bit which is more useful than 0/1 in some cases.
23537 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23540 return DAG.getNode(ISD::AND, DL, VT,
23541 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23542 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23543 DAG.getConstant(1, VT));
23544 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23545 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23546 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23547 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23550 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23551 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23552 TargetLowering::DAGCombinerInfo &DCI,
23553 const X86Subtarget *Subtarget) {
23555 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23556 SDValue EFLAGS = N->getOperand(1);
23558 if (CC == X86::COND_A) {
23559 // Try to convert COND_A into COND_B in an attempt to facilitate
23560 // materializing "setb reg".
23562 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23563 // cannot take an immediate as its first operand.
23565 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23566 EFLAGS.getValueType().isInteger() &&
23567 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23568 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23569 EFLAGS.getNode()->getVTList(),
23570 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23571 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23572 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23576 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23577 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23579 if (CC == X86::COND_B)
23580 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23584 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23585 if (Flags.getNode()) {
23586 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23587 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23593 // Optimize branch condition evaluation.
23595 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23596 TargetLowering::DAGCombinerInfo &DCI,
23597 const X86Subtarget *Subtarget) {
23599 SDValue Chain = N->getOperand(0);
23600 SDValue Dest = N->getOperand(1);
23601 SDValue EFLAGS = N->getOperand(3);
23602 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23606 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23607 if (Flags.getNode()) {
23608 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23609 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23616 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23617 SelectionDAG &DAG) {
23618 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23619 // optimize away operation when it's from a constant.
23621 // The general transformation is:
23622 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23623 // AND(VECTOR_CMP(x,y), constant2)
23624 // constant2 = UNARYOP(constant)
23626 // Early exit if this isn't a vector operation, the operand of the
23627 // unary operation isn't a bitwise AND, or if the sizes of the operations
23628 // aren't the same.
23629 EVT VT = N->getValueType(0);
23630 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23631 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23632 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23635 // Now check that the other operand of the AND is a constant. We could
23636 // make the transformation for non-constant splats as well, but it's unclear
23637 // that would be a benefit as it would not eliminate any operations, just
23638 // perform one more step in scalar code before moving to the vector unit.
23639 if (BuildVectorSDNode *BV =
23640 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23641 // Bail out if the vector isn't a constant.
23642 if (!BV->isConstant())
23645 // Everything checks out. Build up the new and improved node.
23647 EVT IntVT = BV->getValueType(0);
23648 // Create a new constant of the appropriate type for the transformed
23650 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23651 // The AND node needs bitcasts to/from an integer vector type around it.
23652 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23653 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23654 N->getOperand(0)->getOperand(0), MaskConst);
23655 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23662 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23663 const X86Subtarget *Subtarget) {
23664 // First try to optimize away the conversion entirely when it's
23665 // conditionally from a constant. Vectors only.
23666 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23667 if (Res != SDValue())
23670 // Now move on to more general possibilities.
23671 SDValue Op0 = N->getOperand(0);
23672 EVT InVT = Op0->getValueType(0);
23674 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23675 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23677 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23678 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23679 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23682 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23683 // a 32-bit target where SSE doesn't support i64->FP operations.
23684 if (Op0.getOpcode() == ISD::LOAD) {
23685 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23686 EVT VT = Ld->getValueType(0);
23687 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23688 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23689 !Subtarget->is64Bit() && VT == MVT::i64) {
23690 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
23691 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
23692 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23699 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23700 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23701 X86TargetLowering::DAGCombinerInfo &DCI) {
23702 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23703 // the result is either zero or one (depending on the input carry bit).
23704 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23705 if (X86::isZeroNode(N->getOperand(0)) &&
23706 X86::isZeroNode(N->getOperand(1)) &&
23707 // We don't have a good way to replace an EFLAGS use, so only do this when
23709 SDValue(N, 1).use_empty()) {
23711 EVT VT = N->getValueType(0);
23712 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23713 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23714 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23715 DAG.getConstant(X86::COND_B,MVT::i8),
23717 DAG.getConstant(1, VT));
23718 return DCI.CombineTo(N, Res1, CarryOut);
23724 // fold (add Y, (sete X, 0)) -> adc 0, Y
23725 // (add Y, (setne X, 0)) -> sbb -1, Y
23726 // (sub (sete X, 0), Y) -> sbb 0, Y
23727 // (sub (setne X, 0), Y) -> adc -1, Y
23728 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23731 // Look through ZExts.
23732 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23733 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23736 SDValue SetCC = Ext.getOperand(0);
23737 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23740 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23741 if (CC != X86::COND_E && CC != X86::COND_NE)
23744 SDValue Cmp = SetCC.getOperand(1);
23745 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23746 !X86::isZeroNode(Cmp.getOperand(1)) ||
23747 !Cmp.getOperand(0).getValueType().isInteger())
23750 SDValue CmpOp0 = Cmp.getOperand(0);
23751 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23752 DAG.getConstant(1, CmpOp0.getValueType()));
23754 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23755 if (CC == X86::COND_NE)
23756 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23757 DL, OtherVal.getValueType(), OtherVal,
23758 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23759 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23760 DL, OtherVal.getValueType(), OtherVal,
23761 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23764 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23765 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23766 const X86Subtarget *Subtarget) {
23767 EVT VT = N->getValueType(0);
23768 SDValue Op0 = N->getOperand(0);
23769 SDValue Op1 = N->getOperand(1);
23771 // Try to synthesize horizontal adds from adds of shuffles.
23772 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23773 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23774 isHorizontalBinOp(Op0, Op1, true))
23775 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23777 return OptimizeConditionalInDecrement(N, DAG);
23780 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23781 const X86Subtarget *Subtarget) {
23782 SDValue Op0 = N->getOperand(0);
23783 SDValue Op1 = N->getOperand(1);
23785 // X86 can't encode an immediate LHS of a sub. See if we can push the
23786 // negation into a preceding instruction.
23787 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23788 // If the RHS of the sub is a XOR with one use and a constant, invert the
23789 // immediate. Then add one to the LHS of the sub so we can turn
23790 // X-Y -> X+~Y+1, saving one register.
23791 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23792 isa<ConstantSDNode>(Op1.getOperand(1))) {
23793 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23794 EVT VT = Op0.getValueType();
23795 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23797 DAG.getConstant(~XorC, VT));
23798 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23799 DAG.getConstant(C->getAPIntValue()+1, VT));
23803 // Try to synthesize horizontal adds from adds of shuffles.
23804 EVT VT = N->getValueType(0);
23805 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23806 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23807 isHorizontalBinOp(Op0, Op1, true))
23808 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23810 return OptimizeConditionalInDecrement(N, DAG);
23813 /// performVZEXTCombine - Performs build vector combines
23814 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23815 TargetLowering::DAGCombinerInfo &DCI,
23816 const X86Subtarget *Subtarget) {
23818 MVT VT = N->getSimpleValueType(0);
23819 SDValue Op = N->getOperand(0);
23820 MVT OpVT = Op.getSimpleValueType();
23821 MVT OpEltVT = OpVT.getVectorElementType();
23822 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
23824 // (vzext (bitcast (vzext (x)) -> (vzext x)
23826 while (V.getOpcode() == ISD::BITCAST)
23827 V = V.getOperand(0);
23829 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
23830 MVT InnerVT = V.getSimpleValueType();
23831 MVT InnerEltVT = InnerVT.getVectorElementType();
23833 // If the element sizes match exactly, we can just do one larger vzext. This
23834 // is always an exact type match as vzext operates on integer types.
23835 if (OpEltVT == InnerEltVT) {
23836 assert(OpVT == InnerVT && "Types must match for vzext!");
23837 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
23840 // The only other way we can combine them is if only a single element of the
23841 // inner vzext is used in the input to the outer vzext.
23842 if (InnerEltVT.getSizeInBits() < InputBits)
23845 // In this case, the inner vzext is completely dead because we're going to
23846 // only look at bits inside of the low element. Just do the outer vzext on
23847 // a bitcast of the input to the inner.
23848 return DAG.getNode(X86ISD::VZEXT, DL, VT,
23849 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
23852 // Check if we can bypass extracting and re-inserting an element of an input
23853 // vector. Essentialy:
23854 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
23855 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
23856 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
23857 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
23858 SDValue ExtractedV = V.getOperand(0);
23859 SDValue OrigV = ExtractedV.getOperand(0);
23860 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
23861 if (ExtractIdx->getZExtValue() == 0) {
23862 MVT OrigVT = OrigV.getSimpleValueType();
23863 // Extract a subvector if necessary...
23864 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
23865 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
23866 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
23867 OrigVT.getVectorNumElements() / Ratio);
23868 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
23869 DAG.getIntPtrConstant(0));
23871 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
23872 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
23879 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23880 DAGCombinerInfo &DCI) const {
23881 SelectionDAG &DAG = DCI.DAG;
23882 switch (N->getOpcode()) {
23884 case ISD::EXTRACT_VECTOR_ELT:
23885 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23888 case X86ISD::SHRUNKBLEND:
23889 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23890 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
23891 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23892 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23893 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23894 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23895 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23898 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23899 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23900 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23901 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23902 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23903 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
23904 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23905 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
23906 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
23907 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23908 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23910 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23912 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23913 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23914 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23915 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23916 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23917 case ISD::ANY_EXTEND:
23918 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23919 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23920 case ISD::SIGN_EXTEND_INREG:
23921 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23922 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23923 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23924 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23925 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23926 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23927 case X86ISD::SHUFP: // Handle all target specific shuffles
23928 case X86ISD::PALIGNR:
23929 case X86ISD::UNPCKH:
23930 case X86ISD::UNPCKL:
23931 case X86ISD::MOVHLPS:
23932 case X86ISD::MOVLHPS:
23933 case X86ISD::PSHUFB:
23934 case X86ISD::PSHUFD:
23935 case X86ISD::PSHUFHW:
23936 case X86ISD::PSHUFLW:
23937 case X86ISD::MOVSS:
23938 case X86ISD::MOVSD:
23939 case X86ISD::VPERMILPI:
23940 case X86ISD::VPERM2X128:
23941 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23942 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23943 case ISD::INTRINSIC_WO_CHAIN:
23944 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23945 case X86ISD::INSERTPS: {
23946 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
23947 return PerformINSERTPSCombine(N, DAG, Subtarget);
23950 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
23956 /// isTypeDesirableForOp - Return true if the target has native support for
23957 /// the specified value type and it is 'desirable' to use the type for the
23958 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23959 /// instruction encodings are longer and some i16 instructions are slow.
23960 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23961 if (!isTypeLegal(VT))
23963 if (VT != MVT::i16)
23970 case ISD::SIGN_EXTEND:
23971 case ISD::ZERO_EXTEND:
23972 case ISD::ANY_EXTEND:
23985 /// IsDesirableToPromoteOp - This method query the target whether it is
23986 /// beneficial for dag combiner to promote the specified node. If true, it
23987 /// should return the desired promotion type by reference.
23988 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23989 EVT VT = Op.getValueType();
23990 if (VT != MVT::i16)
23993 bool Promote = false;
23994 bool Commute = false;
23995 switch (Op.getOpcode()) {
23998 LoadSDNode *LD = cast<LoadSDNode>(Op);
23999 // If the non-extending load has a single use and it's not live out, then it
24000 // might be folded.
24001 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24002 Op.hasOneUse()*/) {
24003 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24004 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24005 // The only case where we'd want to promote LOAD (rather then it being
24006 // promoted as an operand is when it's only use is liveout.
24007 if (UI->getOpcode() != ISD::CopyToReg)
24014 case ISD::SIGN_EXTEND:
24015 case ISD::ZERO_EXTEND:
24016 case ISD::ANY_EXTEND:
24021 SDValue N0 = Op.getOperand(0);
24022 // Look out for (store (shl (load), x)).
24023 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24036 SDValue N0 = Op.getOperand(0);
24037 SDValue N1 = Op.getOperand(1);
24038 if (!Commute && MayFoldLoad(N1))
24040 // Avoid disabling potential load folding opportunities.
24041 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24043 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24053 //===----------------------------------------------------------------------===//
24054 // X86 Inline Assembly Support
24055 //===----------------------------------------------------------------------===//
24057 // Helper to match a string separated by whitespace.
24058 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24059 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24061 for (StringRef Piece : Pieces) {
24062 if (!S.startswith(Piece)) // Check if the piece matches.
24065 S = S.substr(Piece.size());
24066 StringRef::size_type Pos = S.find_first_not_of(" \t");
24067 if (Pos == 0) // We matched a prefix.
24076 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24078 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24079 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24080 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24081 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24083 if (AsmPieces.size() == 3)
24085 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24092 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24093 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24095 std::string AsmStr = IA->getAsmString();
24097 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24098 if (!Ty || Ty->getBitWidth() % 16 != 0)
24101 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24102 SmallVector<StringRef, 4> AsmPieces;
24103 SplitString(AsmStr, AsmPieces, ";\n");
24105 switch (AsmPieces.size()) {
24106 default: return false;
24108 // FIXME: this should verify that we are targeting a 486 or better. If not,
24109 // we will turn this bswap into something that will be lowered to logical
24110 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24111 // lower so don't worry about this.
24113 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24114 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24115 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24116 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24117 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24118 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24119 // No need to check constraints, nothing other than the equivalent of
24120 // "=r,0" would be valid here.
24121 return IntrinsicLowering::LowerToByteSwap(CI);
24124 // rorw $$8, ${0:w} --> llvm.bswap.i16
24125 if (CI->getType()->isIntegerTy(16) &&
24126 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24127 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24128 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24130 const std::string &ConstraintsStr = IA->getConstraintString();
24131 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24132 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24133 if (clobbersFlagRegisters(AsmPieces))
24134 return IntrinsicLowering::LowerToByteSwap(CI);
24138 if (CI->getType()->isIntegerTy(32) &&
24139 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24140 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24141 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24142 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24144 const std::string &ConstraintsStr = IA->getConstraintString();
24145 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24146 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24147 if (clobbersFlagRegisters(AsmPieces))
24148 return IntrinsicLowering::LowerToByteSwap(CI);
24151 if (CI->getType()->isIntegerTy(64)) {
24152 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24153 if (Constraints.size() >= 2 &&
24154 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24155 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24156 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24157 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24158 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24159 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24160 return IntrinsicLowering::LowerToByteSwap(CI);
24168 /// getConstraintType - Given a constraint letter, return the type of
24169 /// constraint it is for this target.
24170 X86TargetLowering::ConstraintType
24171 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24172 if (Constraint.size() == 1) {
24173 switch (Constraint[0]) {
24184 return C_RegisterClass;
24208 return TargetLowering::getConstraintType(Constraint);
24211 /// Examine constraint type and operand type and determine a weight value.
24212 /// This object must already have been set up with the operand type
24213 /// and the current alternative constraint selected.
24214 TargetLowering::ConstraintWeight
24215 X86TargetLowering::getSingleConstraintMatchWeight(
24216 AsmOperandInfo &info, const char *constraint) const {
24217 ConstraintWeight weight = CW_Invalid;
24218 Value *CallOperandVal = info.CallOperandVal;
24219 // If we don't have a value, we can't do a match,
24220 // but allow it at the lowest weight.
24221 if (!CallOperandVal)
24223 Type *type = CallOperandVal->getType();
24224 // Look at the constraint type.
24225 switch (*constraint) {
24227 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24238 if (CallOperandVal->getType()->isIntegerTy())
24239 weight = CW_SpecificReg;
24244 if (type->isFloatingPointTy())
24245 weight = CW_SpecificReg;
24248 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24249 weight = CW_SpecificReg;
24253 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24254 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24255 weight = CW_Register;
24258 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24259 if (C->getZExtValue() <= 31)
24260 weight = CW_Constant;
24264 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24265 if (C->getZExtValue() <= 63)
24266 weight = CW_Constant;
24270 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24271 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24272 weight = CW_Constant;
24276 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24277 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24278 weight = CW_Constant;
24282 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24283 if (C->getZExtValue() <= 3)
24284 weight = CW_Constant;
24288 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24289 if (C->getZExtValue() <= 0xff)
24290 weight = CW_Constant;
24295 if (isa<ConstantFP>(CallOperandVal)) {
24296 weight = CW_Constant;
24300 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24301 if ((C->getSExtValue() >= -0x80000000LL) &&
24302 (C->getSExtValue() <= 0x7fffffffLL))
24303 weight = CW_Constant;
24307 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24308 if (C->getZExtValue() <= 0xffffffff)
24309 weight = CW_Constant;
24316 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24317 /// with another that has more specific requirements based on the type of the
24318 /// corresponding operand.
24319 const char *X86TargetLowering::
24320 LowerXConstraint(EVT ConstraintVT) const {
24321 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24322 // 'f' like normal targets.
24323 if (ConstraintVT.isFloatingPoint()) {
24324 if (Subtarget->hasSSE2())
24326 if (Subtarget->hasSSE1())
24330 return TargetLowering::LowerXConstraint(ConstraintVT);
24333 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24334 /// vector. If it is invalid, don't add anything to Ops.
24335 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24336 std::string &Constraint,
24337 std::vector<SDValue>&Ops,
24338 SelectionDAG &DAG) const {
24341 // Only support length 1 constraints for now.
24342 if (Constraint.length() > 1) return;
24344 char ConstraintLetter = Constraint[0];
24345 switch (ConstraintLetter) {
24348 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24349 if (C->getZExtValue() <= 31) {
24350 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24356 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24357 if (C->getZExtValue() <= 63) {
24358 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24364 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24365 if (isInt<8>(C->getSExtValue())) {
24366 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24373 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
24374 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
24375 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
24381 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24382 if (C->getZExtValue() <= 3) {
24383 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24389 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24390 if (C->getZExtValue() <= 255) {
24391 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24398 if (C->getZExtValue() <= 127) {
24399 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24405 // 32-bit signed value
24406 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24407 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24408 C->getSExtValue())) {
24409 // Widen to 64 bits here to get it sign extended.
24410 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24413 // FIXME gcc accepts some relocatable values here too, but only in certain
24414 // memory models; it's complicated.
24419 // 32-bit unsigned value
24420 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24421 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24422 C->getZExtValue())) {
24423 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24427 // FIXME gcc accepts some relocatable values here too, but only in certain
24428 // memory models; it's complicated.
24432 // Literal immediates are always ok.
24433 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24434 // Widen to 64 bits here to get it sign extended.
24435 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24439 // In any sort of PIC mode addresses need to be computed at runtime by
24440 // adding in a register or some sort of table lookup. These can't
24441 // be used as immediates.
24442 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24445 // If we are in non-pic codegen mode, we allow the address of a global (with
24446 // an optional displacement) to be used with 'i'.
24447 GlobalAddressSDNode *GA = nullptr;
24448 int64_t Offset = 0;
24450 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24452 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24453 Offset += GA->getOffset();
24455 } else if (Op.getOpcode() == ISD::ADD) {
24456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24457 Offset += C->getZExtValue();
24458 Op = Op.getOperand(0);
24461 } else if (Op.getOpcode() == ISD::SUB) {
24462 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24463 Offset += -C->getZExtValue();
24464 Op = Op.getOperand(0);
24469 // Otherwise, this isn't something we can handle, reject it.
24473 const GlobalValue *GV = GA->getGlobal();
24474 // If we require an extra load to get this address, as in PIC mode, we
24475 // can't accept it.
24476 if (isGlobalStubReference(
24477 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24480 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24481 GA->getValueType(0), Offset);
24486 if (Result.getNode()) {
24487 Ops.push_back(Result);
24490 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24493 std::pair<unsigned, const TargetRegisterClass *>
24494 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
24495 const std::string &Constraint,
24497 // First, see if this is a constraint that directly corresponds to an LLVM
24499 if (Constraint.size() == 1) {
24500 // GCC Constraint Letters
24501 switch (Constraint[0]) {
24503 // TODO: Slight differences here in allocation order and leaving
24504 // RIP in the class. Do they matter any more here than they do
24505 // in the normal allocation?
24506 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24507 if (Subtarget->is64Bit()) {
24508 if (VT == MVT::i32 || VT == MVT::f32)
24509 return std::make_pair(0U, &X86::GR32RegClass);
24510 if (VT == MVT::i16)
24511 return std::make_pair(0U, &X86::GR16RegClass);
24512 if (VT == MVT::i8 || VT == MVT::i1)
24513 return std::make_pair(0U, &X86::GR8RegClass);
24514 if (VT == MVT::i64 || VT == MVT::f64)
24515 return std::make_pair(0U, &X86::GR64RegClass);
24518 // 32-bit fallthrough
24519 case 'Q': // Q_REGS
24520 if (VT == MVT::i32 || VT == MVT::f32)
24521 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24522 if (VT == MVT::i16)
24523 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24524 if (VT == MVT::i8 || VT == MVT::i1)
24525 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24526 if (VT == MVT::i64)
24527 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24529 case 'r': // GENERAL_REGS
24530 case 'l': // INDEX_REGS
24531 if (VT == MVT::i8 || VT == MVT::i1)
24532 return std::make_pair(0U, &X86::GR8RegClass);
24533 if (VT == MVT::i16)
24534 return std::make_pair(0U, &X86::GR16RegClass);
24535 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24536 return std::make_pair(0U, &X86::GR32RegClass);
24537 return std::make_pair(0U, &X86::GR64RegClass);
24538 case 'R': // LEGACY_REGS
24539 if (VT == MVT::i8 || VT == MVT::i1)
24540 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24541 if (VT == MVT::i16)
24542 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24543 if (VT == MVT::i32 || !Subtarget->is64Bit())
24544 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24545 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24546 case 'f': // FP Stack registers.
24547 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24548 // value to the correct fpstack register class.
24549 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24550 return std::make_pair(0U, &X86::RFP32RegClass);
24551 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24552 return std::make_pair(0U, &X86::RFP64RegClass);
24553 return std::make_pair(0U, &X86::RFP80RegClass);
24554 case 'y': // MMX_REGS if MMX allowed.
24555 if (!Subtarget->hasMMX()) break;
24556 return std::make_pair(0U, &X86::VR64RegClass);
24557 case 'Y': // SSE_REGS if SSE2 allowed
24558 if (!Subtarget->hasSSE2()) break;
24560 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24561 if (!Subtarget->hasSSE1()) break;
24563 switch (VT.SimpleTy) {
24565 // Scalar SSE types.
24568 return std::make_pair(0U, &X86::FR32RegClass);
24571 return std::make_pair(0U, &X86::FR64RegClass);
24579 return std::make_pair(0U, &X86::VR128RegClass);
24587 return std::make_pair(0U, &X86::VR256RegClass);
24592 return std::make_pair(0U, &X86::VR512RegClass);
24598 // Use the default implementation in TargetLowering to convert the register
24599 // constraint into a member of a register class.
24600 std::pair<unsigned, const TargetRegisterClass*> Res;
24601 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
24603 // Not found as a standard register?
24605 // Map st(0) -> st(7) -> ST0
24606 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24607 tolower(Constraint[1]) == 's' &&
24608 tolower(Constraint[2]) == 't' &&
24609 Constraint[3] == '(' &&
24610 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24611 Constraint[5] == ')' &&
24612 Constraint[6] == '}') {
24614 Res.first = X86::FP0+Constraint[4]-'0';
24615 Res.second = &X86::RFP80RegClass;
24619 // GCC allows "st(0)" to be called just plain "st".
24620 if (StringRef("{st}").equals_lower(Constraint)) {
24621 Res.first = X86::FP0;
24622 Res.second = &X86::RFP80RegClass;
24627 if (StringRef("{flags}").equals_lower(Constraint)) {
24628 Res.first = X86::EFLAGS;
24629 Res.second = &X86::CCRRegClass;
24633 // 'A' means EAX + EDX.
24634 if (Constraint == "A") {
24635 Res.first = X86::EAX;
24636 Res.second = &X86::GR32_ADRegClass;
24642 // Otherwise, check to see if this is a register class of the wrong value
24643 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24644 // turn into {ax},{dx}.
24645 if (Res.second->hasType(VT))
24646 return Res; // Correct type already, nothing to do.
24648 // All of the single-register GCC register classes map their values onto
24649 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24650 // really want an 8-bit or 32-bit register, map to the appropriate register
24651 // class and return the appropriate register.
24652 if (Res.second == &X86::GR16RegClass) {
24653 if (VT == MVT::i8 || VT == MVT::i1) {
24654 unsigned DestReg = 0;
24655 switch (Res.first) {
24657 case X86::AX: DestReg = X86::AL; break;
24658 case X86::DX: DestReg = X86::DL; break;
24659 case X86::CX: DestReg = X86::CL; break;
24660 case X86::BX: DestReg = X86::BL; break;
24663 Res.first = DestReg;
24664 Res.second = &X86::GR8RegClass;
24666 } else if (VT == MVT::i32 || VT == MVT::f32) {
24667 unsigned DestReg = 0;
24668 switch (Res.first) {
24670 case X86::AX: DestReg = X86::EAX; break;
24671 case X86::DX: DestReg = X86::EDX; break;
24672 case X86::CX: DestReg = X86::ECX; break;
24673 case X86::BX: DestReg = X86::EBX; break;
24674 case X86::SI: DestReg = X86::ESI; break;
24675 case X86::DI: DestReg = X86::EDI; break;
24676 case X86::BP: DestReg = X86::EBP; break;
24677 case X86::SP: DestReg = X86::ESP; break;
24680 Res.first = DestReg;
24681 Res.second = &X86::GR32RegClass;
24683 } else if (VT == MVT::i64 || VT == MVT::f64) {
24684 unsigned DestReg = 0;
24685 switch (Res.first) {
24687 case X86::AX: DestReg = X86::RAX; break;
24688 case X86::DX: DestReg = X86::RDX; break;
24689 case X86::CX: DestReg = X86::RCX; break;
24690 case X86::BX: DestReg = X86::RBX; break;
24691 case X86::SI: DestReg = X86::RSI; break;
24692 case X86::DI: DestReg = X86::RDI; break;
24693 case X86::BP: DestReg = X86::RBP; break;
24694 case X86::SP: DestReg = X86::RSP; break;
24697 Res.first = DestReg;
24698 Res.second = &X86::GR64RegClass;
24701 } else if (Res.second == &X86::FR32RegClass ||
24702 Res.second == &X86::FR64RegClass ||
24703 Res.second == &X86::VR128RegClass ||
24704 Res.second == &X86::VR256RegClass ||
24705 Res.second == &X86::FR32XRegClass ||
24706 Res.second == &X86::FR64XRegClass ||
24707 Res.second == &X86::VR128XRegClass ||
24708 Res.second == &X86::VR256XRegClass ||
24709 Res.second == &X86::VR512RegClass) {
24710 // Handle references to XMM physical registers that got mapped into the
24711 // wrong class. This can happen with constraints like {xmm0} where the
24712 // target independent register mapper will just pick the first match it can
24713 // find, ignoring the required type.
24715 if (VT == MVT::f32 || VT == MVT::i32)
24716 Res.second = &X86::FR32RegClass;
24717 else if (VT == MVT::f64 || VT == MVT::i64)
24718 Res.second = &X86::FR64RegClass;
24719 else if (X86::VR128RegClass.hasType(VT))
24720 Res.second = &X86::VR128RegClass;
24721 else if (X86::VR256RegClass.hasType(VT))
24722 Res.second = &X86::VR256RegClass;
24723 else if (X86::VR512RegClass.hasType(VT))
24724 Res.second = &X86::VR512RegClass;
24730 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24732 // Scaling factors are not free at all.
24733 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24734 // will take 2 allocations in the out of order engine instead of 1
24735 // for plain addressing mode, i.e. inst (reg1).
24737 // vaddps (%rsi,%drx), %ymm0, %ymm1
24738 // Requires two allocations (one for the load, one for the computation)
24740 // vaddps (%rsi), %ymm0, %ymm1
24741 // Requires just 1 allocation, i.e., freeing allocations for other operations
24742 // and having less micro operations to execute.
24744 // For some X86 architectures, this is even worse because for instance for
24745 // stores, the complex addressing mode forces the instruction to use the
24746 // "load" ports instead of the dedicated "store" port.
24747 // E.g., on Haswell:
24748 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24749 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24750 if (isLegalAddressingMode(AM, Ty))
24751 // Scale represents reg2 * scale, thus account for 1
24752 // as soon as we use a second register.
24753 return AM.Scale != 0;
24757 bool X86TargetLowering::isTargetFTOL() const {
24758 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();