1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 // Forward declarations.
71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
74 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
75 const X86Subtarget &STI)
76 : TargetLowering(TM), Subtarget(&STI) {
77 X86ScalarSSEf64 = Subtarget->hasSSE2();
78 X86ScalarSSEf32 = Subtarget->hasSSE1();
79 TD = TM.getDataLayout();
81 // Set up the TargetLowering object.
82 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
84 // X86 is weird. It always uses i8 for shift amounts and setcc results.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // For 64-bit, since we have so many registers, use the ILP scheduler.
90 // For 32-bit, use the register pressure specific scheduling.
91 // For Atom, always use ILP scheduling.
92 if (Subtarget->isAtom())
93 setSchedulingPreference(Sched::ILP);
94 else if (Subtarget->is64Bit())
95 setSchedulingPreference(Sched::ILP);
97 setSchedulingPreference(Sched::RegPressure);
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
99 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
101 // Bypass expensive divides on Atom when compiling with O2.
102 if (TM.getOptLevel() >= CodeGenOpt::Default) {
103 if (Subtarget->hasSlowDivide32())
104 addBypassSlowDiv(32, 8);
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
106 addBypassSlowDiv(64, 16);
109 if (Subtarget->isTargetKnownWindowsMSVC()) {
110 // Setup Windows compiler runtime calls.
111 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
112 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
113 setLibcallName(RTLIB::SREM_I64, "_allrem");
114 setLibcallName(RTLIB::UREM_I64, "_aullrem");
115 setLibcallName(RTLIB::MUL_I64, "_allmul");
116 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
118 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
119 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
120 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
122 // The _ftol2 runtime function has an unusual calling conv, which
123 // is modeled by a special pseudo-instruction.
124 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
125 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
126 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
127 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
130 if (Subtarget->isTargetDarwin()) {
131 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(false);
133 setUseUnderscoreLongJmp(false);
134 } else if (Subtarget->isTargetWindowsGNU()) {
135 // MS runtime is weird: it exports _setjmp, but longjmp!
136 setUseUnderscoreSetJmp(true);
137 setUseUnderscoreLongJmp(false);
139 setUseUnderscoreSetJmp(true);
140 setUseUnderscoreLongJmp(true);
143 // Set up the register classes.
144 addRegisterClass(MVT::i8, &X86::GR8RegClass);
145 addRegisterClass(MVT::i16, &X86::GR16RegClass);
146 addRegisterClass(MVT::i32, &X86::GR32RegClass);
147 if (Subtarget->is64Bit())
148 addRegisterClass(MVT::i64, &X86::GR64RegClass);
150 for (MVT VT : MVT::integer_valuetypes())
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
153 // We don't accept any truncstore of integer registers.
154 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
155 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
156 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
157 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
159 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163 // SETOEQ and SETUNE require checking two conditions.
164 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
165 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
166 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
171 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
177 if (Subtarget->is64Bit()) {
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 } else if (!Subtarget->useSoftFloat()) {
181 // We have an algorithm for SSE2->double, and we turn this into a
182 // 64-bit FILD followed by conditional FADD for other targets.
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
184 // We have an algorithm for SSE2, and we turn this into a 64-bit
185 // FILD for other targets.
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
189 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
191 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
194 if (!Subtarget->useSoftFloat()) {
195 // SSE has no i16 to fp conversion, only i32
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
206 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
216 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
219 if (X86ScalarSSEf32) {
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
221 // f32 and f64 cases are Legal, f80 case is not
222 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
237 } else if (!Subtarget->useSoftFloat()) {
238 // Since AVX is a superset of SSE3, only check for SSE here.
239 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
240 // Expand FP_TO_UINT into a select.
241 // FIXME: We would like to use a Custom expander here eventually to do
242 // the optimal thing for SSE vs. the default expansion in the legalizer.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
250 if (isTargetFTOL()) {
251 // Use the _ftol2 runtime function, which has a pseudo-instruction
252 // to handle its weird calling convention.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
256 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
257 if (!X86ScalarSSEf64) {
258 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
259 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
262 // Without SSE, i64->f64 goes through memory.
263 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
267 // Scalar integer divide and remainder are lowered to use operations that
268 // produce two results, to match the available instructions. This exposes
269 // the two-result form to trivial CSE, which is able to combine x/y and x%y
270 // into a single instruction.
272 // Scalar integer multiply-high is also lowered to use two-result
273 // operations, to match the available instructions. However, plain multiply
274 // (low) operations are left as Legal, as there are single-result
275 // instructions for this in x86. Using the two-result multiply instructions
276 // when both high and low results are needed must be arranged by dagcombine.
277 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
279 setOperationAction(ISD::MULHS, VT, Expand);
280 setOperationAction(ISD::MULHU, VT, Expand);
281 setOperationAction(ISD::SDIV, VT, Expand);
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SREM, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
286 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
287 setOperationAction(ISD::ADDC, VT, Custom);
288 setOperationAction(ISD::ADDE, VT, Custom);
289 setOperationAction(ISD::SUBC, VT, Custom);
290 setOperationAction(ISD::SUBE, VT, Custom);
293 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
294 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
295 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
309 if (Subtarget->is64Bit())
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
314 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
316 setOperationAction(ISD::FREM , MVT::f64 , Expand);
317 setOperationAction(ISD::FREM , MVT::f80 , Expand);
318 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
320 // Promote the i8 variants and force them on up to i32 which has a shorter
322 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
323 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
326 if (Subtarget->hasBMI()) {
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
332 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
333 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
334 if (Subtarget->is64Bit())
335 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
338 if (Subtarget->hasLZCNT()) {
339 // When promoting the i8 variants, force them to i32 for a shorter
341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
356 if (Subtarget->is64Bit()) {
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
362 // Special handling for half-precision floating point conversions.
363 // If we don't have F16C support, then lower half float conversions
364 // into library calls.
365 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
366 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
370 // There's never any support for operations beyond MVT::f32.
371 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
372 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
379 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
380 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
383 if (Subtarget->hasPOPCNT()) {
384 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
386 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
387 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
388 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
393 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
395 if (!Subtarget->hasMOVBE())
396 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
398 // These should be promoted to a larger select which is supported.
399 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
400 // X86 wants to expand cmov itself.
401 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
402 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
403 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
404 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
405 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
407 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
408 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
410 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
411 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
417 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
418 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
419 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
420 // support continuation, user-level threading, and etc.. As a result, no
421 // other SjLj exception interfaces are implemented and please don't build
422 // your own exception handling based on them.
423 // LLVM/Clang supports zero-cost DWARF exception handling.
424 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
425 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasSSE1())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // Expand certain atomics
459 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
461 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
462 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
463 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
466 if (Subtarget->hasCmpxchg16b()) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
470 // FIXME - use subtarget debug flags
471 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
472 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
473 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
476 if (Subtarget->is64Bit()) {
477 setExceptionPointerRegister(X86::RAX);
478 setExceptionSelectorRegister(X86::RDX);
480 setExceptionPointerRegister(X86::EAX);
481 setExceptionSelectorRegister(X86::EDX);
483 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
484 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
486 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
487 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::TRAP, MVT::Other, Legal);
490 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
492 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
493 setOperationAction(ISD::VASTART , MVT::Other, Custom);
494 setOperationAction(ISD::VAEND , MVT::Other, Expand);
495 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
496 // TargetInfo::X86_64ABIBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Custom);
498 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
500 // TargetInfo::CharPtrBuiltinVaList
501 setOperationAction(ISD::VAARG , MVT::Other, Expand);
502 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
505 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
506 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
508 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(*TD), Custom);
510 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
511 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
512 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
514 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
515 // f32 and f64 use SSE.
516 // Set up the FP register classes.
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::FR64RegClass);
520 // Use ANDPD to simulate FABS.
521 setOperationAction(ISD::FABS , MVT::f64, Custom);
522 setOperationAction(ISD::FABS , MVT::f32, Custom);
524 // Use XORP to simulate FNEG.
525 setOperationAction(ISD::FNEG , MVT::f64, Custom);
526 setOperationAction(ISD::FNEG , MVT::f32, Custom);
528 // Use ANDPD and ORPD to simulate FCOPYSIGN.
529 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
530 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
532 // Lower this to FGETSIGNx86 plus an AND.
533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
536 // We don't support sin/cos/fmod
537 setOperationAction(ISD::FSIN , MVT::f64, Expand);
538 setOperationAction(ISD::FCOS , MVT::f64, Expand);
539 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
540 setOperationAction(ISD::FSIN , MVT::f32, Expand);
541 setOperationAction(ISD::FCOS , MVT::f32, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
544 // Expand FP immediates into loads from the stack, except for the special
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578 if (!TM.Options.UnsafeFPMath) {
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (!Subtarget->useSoftFloat()) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
589 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
590 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
594 if (!TM.Options.UnsafeFPMath) {
595 setOperationAction(ISD::FSIN , MVT::f64, Expand);
596 setOperationAction(ISD::FSIN , MVT::f32, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FCOS , MVT::f32, Expand);
599 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
602 addLegalFPImmediate(APFloat(+0.0)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
612 // We don't support FMA.
613 setOperationAction(ISD::FMA, MVT::f64, Expand);
614 setOperationAction(ISD::FMA, MVT::f32, Expand);
616 // Long double always uses X87.
617 if (!Subtarget->useSoftFloat()) {
618 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
619 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
622 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
623 addLegalFPImmediate(TmpFlt); // FLD0
625 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
628 APFloat TmpFlt2(+1.0);
629 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
631 addLegalFPImmediate(TmpFlt2); // FLD1
632 TmpFlt2.changeSign();
633 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
636 if (!TM.Options.UnsafeFPMath) {
637 setOperationAction(ISD::FSIN , MVT::f80, Expand);
638 setOperationAction(ISD::FCOS , MVT::f80, Expand);
639 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
642 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
643 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
644 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
645 setOperationAction(ISD::FRINT, MVT::f80, Expand);
646 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
647 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 // Always use a library call for pow.
651 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
652 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
655 setOperationAction(ISD::FLOG, MVT::f80, Expand);
656 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
658 setOperationAction(ISD::FEXP, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
661 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
663 // First set operation action for all vector types to either promote
664 // (for widening) or expand (for scalarization). Then we will selectively
665 // turn on ones that can be effectively codegen'd.
666 for (MVT VT : MVT::vector_valuetypes()) {
667 setOperationAction(ISD::ADD , VT, Expand);
668 setOperationAction(ISD::SUB , VT, Expand);
669 setOperationAction(ISD::FADD, VT, Expand);
670 setOperationAction(ISD::FNEG, VT, Expand);
671 setOperationAction(ISD::FSUB, VT, Expand);
672 setOperationAction(ISD::MUL , VT, Expand);
673 setOperationAction(ISD::FMUL, VT, Expand);
674 setOperationAction(ISD::SDIV, VT, Expand);
675 setOperationAction(ISD::UDIV, VT, Expand);
676 setOperationAction(ISD::FDIV, VT, Expand);
677 setOperationAction(ISD::SREM, VT, Expand);
678 setOperationAction(ISD::UREM, VT, Expand);
679 setOperationAction(ISD::LOAD, VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::FABS, VT, Expand);
686 setOperationAction(ISD::FSIN, VT, Expand);
687 setOperationAction(ISD::FSINCOS, VT, Expand);
688 setOperationAction(ISD::FCOS, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FREM, VT, Expand);
691 setOperationAction(ISD::FMA, VT, Expand);
692 setOperationAction(ISD::FPOWI, VT, Expand);
693 setOperationAction(ISD::FSQRT, VT, Expand);
694 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::FPOW, VT, Expand);
707 setOperationAction(ISD::CTPOP, VT, Expand);
708 setOperationAction(ISD::CTTZ, VT, Expand);
709 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
710 setOperationAction(ISD::CTLZ, VT, Expand);
711 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::SHL, VT, Expand);
713 setOperationAction(ISD::SRA, VT, Expand);
714 setOperationAction(ISD::SRL, VT, Expand);
715 setOperationAction(ISD::ROTL, VT, Expand);
716 setOperationAction(ISD::ROTR, VT, Expand);
717 setOperationAction(ISD::BSWAP, VT, Expand);
718 setOperationAction(ISD::SETCC, VT, Expand);
719 setOperationAction(ISD::FLOG, VT, Expand);
720 setOperationAction(ISD::FLOG2, VT, Expand);
721 setOperationAction(ISD::FLOG10, VT, Expand);
722 setOperationAction(ISD::FEXP, VT, Expand);
723 setOperationAction(ISD::FEXP2, VT, Expand);
724 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
725 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
727 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
729 setOperationAction(ISD::TRUNCATE, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
731 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
732 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
733 setOperationAction(ISD::VSELECT, VT, Expand);
734 setOperationAction(ISD::SELECT_CC, VT, Expand);
735 for (MVT InnerVT : MVT::vector_valuetypes()) {
736 setTruncStoreAction(InnerVT, VT, Expand);
738 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
741 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
742 // types, we have to deal with them whether we ask for Expansion or not.
743 // Setting Expand causes its own optimisation problems though, so leave
745 if (VT.getVectorElementType() == MVT::i1)
746 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
748 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
749 // split/scalarized right now.
750 if (VT.getVectorElementType() == MVT::f16)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
756 // with -msoft-float, disable use of MMX as well.
757 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
758 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
759 // No operations on x86mmx supported, everything uses intrinsics.
762 // MMX-sized vectors (other than x86mmx) are expected to be expanded
763 // into smaller operations.
764 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
765 setOperationAction(ISD::MULHS, MMXTy, Expand);
766 setOperationAction(ISD::AND, MMXTy, Expand);
767 setOperationAction(ISD::OR, MMXTy, Expand);
768 setOperationAction(ISD::XOR, MMXTy, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
770 setOperationAction(ISD::SELECT, MMXTy, Expand);
771 setOperationAction(ISD::BITCAST, MMXTy, Expand);
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
775 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
776 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
788 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
795 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
797 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
798 // registers cannot be used even for integer operations.
799 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
800 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
801 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
802 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
804 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
805 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
806 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
807 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
808 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
809 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
812 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
814 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
816 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
818 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
819 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
826 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
828 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
829 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
830 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
831 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
833 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
835 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
836 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
844 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
845 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
849 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
850 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
851 MVT VT = (MVT::SimpleValueType)i;
852 // Do not attempt to custom lower non-power-of-2 vectors
853 if (!isPowerOf2_32(VT.getVectorNumElements()))
855 // Do not attempt to custom lower non-128-bit vectors
856 if (!VT.is128BitVector())
858 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
859 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
860 setOperationAction(ISD::VSELECT, VT, Custom);
861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
864 // We support custom legalizing of sext and anyext loads for specific
865 // memory vector types which we can load as a scalar (or sequence of
866 // scalars) and extend in-register to a legal 128-bit vector type. For sext
867 // loads these must work with a single scalar load.
868 for (MVT VT : MVT::integer_vector_valuetypes()) {
869 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
870 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
871 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
873 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
874 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
880 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
881 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
882 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
884 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
885 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
886 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
887 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
889 if (Subtarget->is64Bit()) {
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
894 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
895 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
896 MVT VT = (MVT::SimpleValueType)i;
898 // Do not attempt to promote non-128-bit vectors
899 if (!VT.is128BitVector())
902 setOperationAction(ISD::AND, VT, Promote);
903 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
904 setOperationAction(ISD::OR, VT, Promote);
905 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
906 setOperationAction(ISD::XOR, VT, Promote);
907 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
908 setOperationAction(ISD::LOAD, VT, Promote);
909 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
910 setOperationAction(ISD::SELECT, VT, Promote);
911 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
914 // Custom lower v2i64 and v2f64 selects.
915 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
916 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
917 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
918 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
920 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
921 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
925 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
926 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
927 // As there is no 64-bit GPR available, we need build a special custom
928 // sequence to convert from v2i32 to v2f32.
929 if (!Subtarget->is64Bit())
930 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
932 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
933 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
935 for (MVT VT : MVT::fp_vector_valuetypes())
936 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
938 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
939 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
940 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
943 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
944 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
945 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
946 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
947 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
948 setOperationAction(ISD::FRINT, RoundedTy, Legal);
949 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
952 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
953 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
954 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
955 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
957 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
958 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
959 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
961 // FIXME: Do we need to handle scalar-to-vector here?
962 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
964 // We directly match byte blends in the backend as they match the VSELECT
966 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
968 // SSE41 brings specific instructions for doing vector sign extend even in
969 // cases where we don't have SRA.
970 for (MVT VT : MVT::integer_vector_valuetypes()) {
971 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
972 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
976 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
991 // i8 and i16 vectors are custom because the source register and source
992 // source memory operand types are not the same width. f32 vectors are
993 // custom since the immediate controlling the insert encodes additional
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1005 // FIXME: these should be Legal, but that's only for the case where
1006 // the index is constant. For now custom expand to deal with that.
1007 if (Subtarget->is64Bit()) {
1008 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1013 if (Subtarget->hasSSE2()) {
1014 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1015 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1018 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1019 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1021 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1022 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1024 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1025 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1027 // In the customized shift lowering, the legal cases in AVX2 will be
1029 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1030 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1032 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1033 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1035 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1036 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1039 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1040 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1041 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1042 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1043 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1044 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1045 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1047 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1048 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1049 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1051 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1052 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1053 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1054 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1055 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1056 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1057 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1058 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1059 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1060 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1062 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1064 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1075 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1077 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1078 // even though v8i16 is a legal type.
1079 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1080 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1081 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1083 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1084 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1085 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1087 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1088 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1090 for (MVT VT : MVT::fp_vector_valuetypes())
1091 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1093 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1102 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1103 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1104 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1105 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1107 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1108 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1109 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1111 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1112 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1114 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1115 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1116 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1117 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1118 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1119 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1120 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1121 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1122 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1124 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1125 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1126 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1127 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1129 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1130 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1132 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1133 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1134 setOperationAction(ISD::FMA, MVT::f32, Legal);
1135 setOperationAction(ISD::FMA, MVT::f64, Legal);
1138 if (Subtarget->hasInt256()) {
1139 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1140 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1141 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1142 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1144 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1145 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1146 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1147 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1149 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1150 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1151 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1152 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1154 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1155 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1156 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1157 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1159 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1160 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1161 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1162 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1163 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1164 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1165 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1167 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1168 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1169 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1170 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1172 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1173 // when we have a 256bit-wide blend with immediate.
1174 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1176 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1177 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1178 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1179 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1180 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1181 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1182 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1184 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1185 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1186 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1187 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1188 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1189 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1191 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1192 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1193 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1196 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1197 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1198 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1199 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1201 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1202 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1203 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1204 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1207 // In the customized shift lowering, the legal cases in AVX2 will be
1209 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1210 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1212 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1213 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1215 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1216 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1218 // Custom lower several nodes for 256-bit types.
1219 for (MVT VT : MVT::vector_valuetypes()) {
1220 if (VT.getScalarSizeInBits() >= 32) {
1221 setOperationAction(ISD::MLOAD, VT, Legal);
1222 setOperationAction(ISD::MSTORE, VT, Legal);
1224 // Extract subvector is special because the value type
1225 // (result) is 128-bit but the source is 256-bit wide.
1226 if (VT.is128BitVector()) {
1227 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1229 // Do not attempt to custom lower other non-256-bit vectors
1230 if (!VT.is256BitVector())
1233 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1234 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1235 setOperationAction(ISD::VSELECT, VT, Custom);
1236 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1237 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1238 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1239 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1240 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1243 if (Subtarget->hasInt256())
1244 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1247 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1248 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1249 MVT VT = (MVT::SimpleValueType)i;
1251 // Do not attempt to promote non-256-bit vectors
1252 if (!VT.is256BitVector())
1255 setOperationAction(ISD::AND, VT, Promote);
1256 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1257 setOperationAction(ISD::OR, VT, Promote);
1258 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1259 setOperationAction(ISD::XOR, VT, Promote);
1260 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1261 setOperationAction(ISD::LOAD, VT, Promote);
1262 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1263 setOperationAction(ISD::SELECT, VT, Promote);
1264 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1268 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1269 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1270 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1271 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1272 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1274 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1275 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1276 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1278 for (MVT VT : MVT::fp_vector_valuetypes())
1279 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1281 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1282 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1283 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1284 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1285 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1286 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1287 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1288 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1289 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1290 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1291 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1292 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1294 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1295 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1296 setOperationAction(ISD::XOR, MVT::i1, Legal);
1297 setOperationAction(ISD::OR, MVT::i1, Legal);
1298 setOperationAction(ISD::AND, MVT::i1, Legal);
1299 setOperationAction(ISD::SUB, MVT::i1, Custom);
1300 setOperationAction(ISD::ADD, MVT::i1, Custom);
1301 setOperationAction(ISD::MUL, MVT::i1, Custom);
1302 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1303 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1304 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1305 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1306 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1308 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1309 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1310 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1311 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1312 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1313 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1315 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1316 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1317 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1318 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1319 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1320 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1321 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1322 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1325 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1326 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1327 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1328 if (Subtarget->is64Bit()) {
1329 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1330 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1331 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1332 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1337 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1338 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1339 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1340 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1341 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1342 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1343 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1345 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1346 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1347 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1348 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1349 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1351 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1352 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1353 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1354 if (Subtarget->hasDQI()) {
1355 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1356 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1358 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1359 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1360 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1361 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1362 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1363 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1364 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1365 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1367 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1368 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1369 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1370 if (Subtarget->hasDQI()) {
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1374 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1375 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1376 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1377 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1378 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1379 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1380 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1381 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1382 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1385 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1386 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1387 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1388 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1389 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1391 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1392 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1394 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1396 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1398 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1399 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1400 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1401 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1402 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1403 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1404 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1405 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1406 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1408 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1409 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1410 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1411 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1412 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1414 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1415 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1417 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1418 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1420 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1421 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1423 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1425 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1426 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1428 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1429 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1431 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1434 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1435 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1436 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1437 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1438 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1439 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1441 if (Subtarget->hasCDI()) {
1442 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1443 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1445 if (Subtarget->hasDQI()) {
1446 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1447 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1450 // Custom lower several nodes.
1451 for (MVT VT : MVT::vector_valuetypes()) {
1452 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1454 setOperationAction(ISD::AND, VT, Legal);
1455 setOperationAction(ISD::OR, VT, Legal);
1456 setOperationAction(ISD::XOR, VT, Legal);
1458 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1459 setOperationAction(ISD::MGATHER, VT, Custom);
1460 setOperationAction(ISD::MSCATTER, VT, Custom);
1462 // Extract subvector is special because the value type
1463 // (result) is 256/128-bit but the source is 512-bit wide.
1464 if (VT.is128BitVector() || VT.is256BitVector()) {
1465 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1467 if (VT.getVectorElementType() == MVT::i1)
1468 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1470 // Do not attempt to custom lower other non-512-bit vectors
1471 if (!VT.is512BitVector())
1474 if (EltSize >= 32) {
1475 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1476 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1477 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1478 setOperationAction(ISD::VSELECT, VT, Legal);
1479 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1480 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1481 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1482 setOperationAction(ISD::MLOAD, VT, Legal);
1483 setOperationAction(ISD::MSTORE, VT, Legal);
1486 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1487 MVT VT = (MVT::SimpleValueType)i;
1489 // Do not attempt to promote non-512-bit vectors.
1490 if (!VT.is512BitVector())
1493 setOperationAction(ISD::SELECT, VT, Promote);
1494 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1498 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1499 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1500 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1502 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1503 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1505 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1506 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1507 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1508 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1509 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1510 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1511 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1512 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1513 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1514 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1515 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1516 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1517 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1518 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1519 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1520 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1521 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1522 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1523 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1524 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1525 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1526 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1527 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1528 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1529 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1530 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1531 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1532 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1533 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1535 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1536 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1537 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1538 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1539 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1540 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1541 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1542 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1544 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1545 const MVT VT = (MVT::SimpleValueType)i;
1547 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1549 // Do not attempt to promote non-512-bit vectors.
1550 if (!VT.is512BitVector())
1554 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1555 setOperationAction(ISD::VSELECT, VT, Legal);
1560 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1561 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1562 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1564 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1565 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1566 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1567 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1568 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1569 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1570 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1571 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1572 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1573 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1575 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1576 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1577 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1578 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1579 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1580 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1581 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1582 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1584 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1585 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1586 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1587 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1588 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1589 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1590 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1591 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1594 // We want to custom lower some of our intrinsics.
1595 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1596 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1597 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1598 if (!Subtarget->is64Bit())
1599 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1601 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1602 // handle type legalization for these operations here.
1604 // FIXME: We really should do custom legalization for addition and
1605 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1606 // than generic legalization for 64-bit multiplication-with-overflow, though.
1607 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1608 // Add/Sub/Mul with overflow operations are custom lowered.
1610 setOperationAction(ISD::SADDO, VT, Custom);
1611 setOperationAction(ISD::UADDO, VT, Custom);
1612 setOperationAction(ISD::SSUBO, VT, Custom);
1613 setOperationAction(ISD::USUBO, VT, Custom);
1614 setOperationAction(ISD::SMULO, VT, Custom);
1615 setOperationAction(ISD::UMULO, VT, Custom);
1619 if (!Subtarget->is64Bit()) {
1620 // These libcalls are not available in 32-bit.
1621 setLibcallName(RTLIB::SHL_I128, nullptr);
1622 setLibcallName(RTLIB::SRL_I128, nullptr);
1623 setLibcallName(RTLIB::SRA_I128, nullptr);
1626 // Combine sin / cos into one node or libcall if possible.
1627 if (Subtarget->hasSinCos()) {
1628 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1629 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1630 if (Subtarget->isTargetDarwin()) {
1631 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1632 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1633 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1634 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1638 if (Subtarget->isTargetWin64()) {
1639 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1640 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1641 setOperationAction(ISD::SREM, MVT::i128, Custom);
1642 setOperationAction(ISD::UREM, MVT::i128, Custom);
1643 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1644 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1647 // We have target-specific dag combine patterns for the following nodes:
1648 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1649 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1650 setTargetDAGCombine(ISD::BITCAST);
1651 setTargetDAGCombine(ISD::VSELECT);
1652 setTargetDAGCombine(ISD::SELECT);
1653 setTargetDAGCombine(ISD::SHL);
1654 setTargetDAGCombine(ISD::SRA);
1655 setTargetDAGCombine(ISD::SRL);
1656 setTargetDAGCombine(ISD::OR);
1657 setTargetDAGCombine(ISD::AND);
1658 setTargetDAGCombine(ISD::ADD);
1659 setTargetDAGCombine(ISD::FADD);
1660 setTargetDAGCombine(ISD::FSUB);
1661 setTargetDAGCombine(ISD::FMA);
1662 setTargetDAGCombine(ISD::SUB);
1663 setTargetDAGCombine(ISD::LOAD);
1664 setTargetDAGCombine(ISD::MLOAD);
1665 setTargetDAGCombine(ISD::STORE);
1666 setTargetDAGCombine(ISD::MSTORE);
1667 setTargetDAGCombine(ISD::ZERO_EXTEND);
1668 setTargetDAGCombine(ISD::ANY_EXTEND);
1669 setTargetDAGCombine(ISD::SIGN_EXTEND);
1670 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1671 setTargetDAGCombine(ISD::SINT_TO_FP);
1672 setTargetDAGCombine(ISD::UINT_TO_FP);
1673 setTargetDAGCombine(ISD::SETCC);
1674 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1675 setTargetDAGCombine(ISD::BUILD_VECTOR);
1676 setTargetDAGCombine(ISD::MUL);
1677 setTargetDAGCombine(ISD::XOR);
1679 computeRegisterProperties(Subtarget->getRegisterInfo());
1681 // On Darwin, -Os means optimize for size without hurting performance,
1682 // do not reduce the limit.
1683 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1684 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1685 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1686 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1687 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1688 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1689 setPrefLoopAlignment(4); // 2^4 bytes.
1691 // Predictable cmov don't hurt on atom because it's in-order.
1692 PredictableSelectIsExpensive = !Subtarget->isAtom();
1693 EnableExtLdPromotion = true;
1694 setPrefFunctionAlignment(4); // 2^4 bytes.
1696 verifyIntrinsicTables();
1699 // This has so far only been implemented for 64-bit MachO.
1700 bool X86TargetLowering::useLoadStackGuardNode() const {
1701 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1704 TargetLoweringBase::LegalizeTypeAction
1705 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1706 if (ExperimentalVectorWideningLegalization &&
1707 VT.getVectorNumElements() != 1 &&
1708 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1709 return TypeWidenVector;
1711 return TargetLoweringBase::getPreferredVectorAction(VT);
1714 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1717 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1719 const unsigned NumElts = VT.getVectorNumElements();
1720 const EVT EltVT = VT.getVectorElementType();
1721 if (VT.is512BitVector()) {
1722 if (Subtarget->hasAVX512())
1723 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1724 EltVT == MVT::f32 || EltVT == MVT::f64)
1726 case 8: return MVT::v8i1;
1727 case 16: return MVT::v16i1;
1729 if (Subtarget->hasBWI())
1730 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1732 case 32: return MVT::v32i1;
1733 case 64: return MVT::v64i1;
1737 if (VT.is256BitVector() || VT.is128BitVector()) {
1738 if (Subtarget->hasVLX())
1739 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1740 EltVT == MVT::f32 || EltVT == MVT::f64)
1742 case 2: return MVT::v2i1;
1743 case 4: return MVT::v4i1;
1744 case 8: return MVT::v8i1;
1746 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1747 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1749 case 8: return MVT::v8i1;
1750 case 16: return MVT::v16i1;
1751 case 32: return MVT::v32i1;
1755 return VT.changeVectorElementTypeToInteger();
1758 /// Helper for getByValTypeAlignment to determine
1759 /// the desired ByVal argument alignment.
1760 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1763 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1764 if (VTy->getBitWidth() == 128)
1766 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1767 unsigned EltAlign = 0;
1768 getMaxByValAlign(ATy->getElementType(), EltAlign);
1769 if (EltAlign > MaxAlign)
1770 MaxAlign = EltAlign;
1771 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1772 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1773 unsigned EltAlign = 0;
1774 getMaxByValAlign(STy->getElementType(i), EltAlign);
1775 if (EltAlign > MaxAlign)
1776 MaxAlign = EltAlign;
1783 /// Return the desired alignment for ByVal aggregate
1784 /// function arguments in the caller parameter area. For X86, aggregates
1785 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1786 /// are at 4-byte boundaries.
1787 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1788 if (Subtarget->is64Bit()) {
1789 // Max of 8 and alignment of type.
1790 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1797 if (Subtarget->hasSSE1())
1798 getMaxByValAlign(Ty, Align);
1802 /// Returns the target specific optimal type for load
1803 /// and store operations as a result of memset, memcpy, and memmove
1804 /// lowering. If DstAlign is zero that means it's safe to destination
1805 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1806 /// means there isn't a need to check it against alignment requirement,
1807 /// probably because the source does not need to be loaded. If 'IsMemset' is
1808 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1809 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1810 /// source is constant so it does not need to be loaded.
1811 /// It returns EVT::Other if the type should be determined using generic
1812 /// target-independent logic.
1814 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1815 unsigned DstAlign, unsigned SrcAlign,
1816 bool IsMemset, bool ZeroMemset,
1818 MachineFunction &MF) const {
1819 const Function *F = MF.getFunction();
1820 if ((!IsMemset || ZeroMemset) &&
1821 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1823 (Subtarget->isUnalignedMemAccessFast() ||
1824 ((DstAlign == 0 || DstAlign >= 16) &&
1825 (SrcAlign == 0 || SrcAlign >= 16)))) {
1827 if (Subtarget->hasInt256())
1829 if (Subtarget->hasFp256())
1832 if (Subtarget->hasSSE2())
1834 if (Subtarget->hasSSE1())
1836 } else if (!MemcpyStrSrc && Size >= 8 &&
1837 !Subtarget->is64Bit() &&
1838 Subtarget->hasSSE2()) {
1839 // Do not use f64 to lower memcpy if source is string constant. It's
1840 // better to use i32 to avoid the loads.
1844 if (Subtarget->is64Bit() && Size >= 8)
1849 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1851 return X86ScalarSSEf32;
1852 else if (VT == MVT::f64)
1853 return X86ScalarSSEf64;
1858 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1863 *Fast = Subtarget->isUnalignedMemAccessFast();
1867 /// Return the entry encoding for a jump table in the
1868 /// current function. The returned value is a member of the
1869 /// MachineJumpTableInfo::JTEntryKind enum.
1870 unsigned X86TargetLowering::getJumpTableEncoding() const {
1871 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1873 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1874 Subtarget->isPICStyleGOT())
1875 return MachineJumpTableInfo::EK_Custom32;
1877 // Otherwise, use the normal jump table encoding heuristics.
1878 return TargetLowering::getJumpTableEncoding();
1881 bool X86TargetLowering::useSoftFloat() const {
1882 return Subtarget->useSoftFloat();
1886 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1887 const MachineBasicBlock *MBB,
1888 unsigned uid,MCContext &Ctx) const{
1889 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1890 Subtarget->isPICStyleGOT());
1891 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1893 return MCSymbolRefExpr::create(MBB->getSymbol(),
1894 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1897 /// Returns relocation base for the given PIC jumptable.
1898 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1899 SelectionDAG &DAG) const {
1900 if (!Subtarget->is64Bit())
1901 // This doesn't have SDLoc associated with it, but is not really the
1902 // same as a Register.
1903 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
1904 getPointerTy(DAG.getDataLayout()));
1908 /// This returns the relocation base for the given PIC jumptable,
1909 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1910 const MCExpr *X86TargetLowering::
1911 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1912 MCContext &Ctx) const {
1913 // X86-64 uses RIP relative addressing based on the jump table label.
1914 if (Subtarget->isPICStyleRIPRel())
1915 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1917 // Otherwise, the reference is relative to the PIC base.
1918 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1921 std::pair<const TargetRegisterClass *, uint8_t>
1922 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1924 const TargetRegisterClass *RRC = nullptr;
1926 switch (VT.SimpleTy) {
1928 return TargetLowering::findRepresentativeClass(TRI, VT);
1929 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1930 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1933 RRC = &X86::VR64RegClass;
1935 case MVT::f32: case MVT::f64:
1936 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1937 case MVT::v4f32: case MVT::v2f64:
1938 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1940 RRC = &X86::VR128RegClass;
1943 return std::make_pair(RRC, Cost);
1946 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1947 unsigned &Offset) const {
1948 if (!Subtarget->isTargetLinux())
1951 if (Subtarget->is64Bit()) {
1952 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1954 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1966 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1967 unsigned DestAS) const {
1968 assert(SrcAS != DestAS && "Expected different address spaces!");
1970 return SrcAS < 256 && DestAS < 256;
1973 //===----------------------------------------------------------------------===//
1974 // Return Value Calling Convention Implementation
1975 //===----------------------------------------------------------------------===//
1977 #include "X86GenCallingConv.inc"
1980 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1981 MachineFunction &MF, bool isVarArg,
1982 const SmallVectorImpl<ISD::OutputArg> &Outs,
1983 LLVMContext &Context) const {
1984 SmallVector<CCValAssign, 16> RVLocs;
1985 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1986 return CCInfo.CheckReturn(Outs, RetCC_X86);
1989 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1990 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1995 X86TargetLowering::LowerReturn(SDValue Chain,
1996 CallingConv::ID CallConv, bool isVarArg,
1997 const SmallVectorImpl<ISD::OutputArg> &Outs,
1998 const SmallVectorImpl<SDValue> &OutVals,
1999 SDLoc dl, SelectionDAG &DAG) const {
2000 MachineFunction &MF = DAG.getMachineFunction();
2001 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2003 SmallVector<CCValAssign, 16> RVLocs;
2004 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2005 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2008 SmallVector<SDValue, 6> RetOps;
2009 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2010 // Operand #1 = Bytes To Pop
2011 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2014 // Copy the result values into the output registers.
2015 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2016 CCValAssign &VA = RVLocs[i];
2017 assert(VA.isRegLoc() && "Can only return in registers!");
2018 SDValue ValToCopy = OutVals[i];
2019 EVT ValVT = ValToCopy.getValueType();
2021 // Promote values to the appropriate types.
2022 if (VA.getLocInfo() == CCValAssign::SExt)
2023 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2024 else if (VA.getLocInfo() == CCValAssign::ZExt)
2025 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2026 else if (VA.getLocInfo() == CCValAssign::AExt) {
2027 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2028 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2030 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2032 else if (VA.getLocInfo() == CCValAssign::BCvt)
2033 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2035 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2036 "Unexpected FP-extend for return value.");
2038 // If this is x86-64, and we disabled SSE, we can't return FP values,
2039 // or SSE or MMX vectors.
2040 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2041 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2042 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2043 report_fatal_error("SSE register return with SSE disabled");
2045 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2046 // llvm-gcc has never done it right and no one has noticed, so this
2047 // should be OK for now.
2048 if (ValVT == MVT::f64 &&
2049 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2050 report_fatal_error("SSE2 register return with SSE2 disabled");
2052 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2053 // the RET instruction and handled by the FP Stackifier.
2054 if (VA.getLocReg() == X86::FP0 ||
2055 VA.getLocReg() == X86::FP1) {
2056 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2057 // change the value to the FP stack register class.
2058 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2059 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2060 RetOps.push_back(ValToCopy);
2061 // Don't emit a copytoreg.
2065 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2066 // which is returned in RAX / RDX.
2067 if (Subtarget->is64Bit()) {
2068 if (ValVT == MVT::x86mmx) {
2069 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2070 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2071 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2073 // If we don't have SSE2 available, convert to v4f32 so the generated
2074 // register is legal.
2075 if (!Subtarget->hasSSE2())
2076 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2081 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2082 Flag = Chain.getValue(1);
2083 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2086 // All x86 ABIs require that for returning structs by value we copy
2087 // the sret argument into %rax/%eax (depending on ABI) for the return.
2088 // We saved the argument into a virtual register in the entry block,
2089 // so now we copy the value out and into %rax/%eax.
2091 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2092 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2093 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2094 // either case FuncInfo->setSRetReturnReg() will have been called.
2095 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2096 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2097 getPointerTy(MF.getDataLayout()));
2100 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2101 X86::RAX : X86::EAX;
2102 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2103 Flag = Chain.getValue(1);
2105 // RAX/EAX now acts like a return value.
2107 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2110 RetOps[0] = Chain; // Update chain.
2112 // Add the flag if we have it.
2114 RetOps.push_back(Flag);
2116 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2119 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2120 if (N->getNumValues() != 1)
2122 if (!N->hasNUsesOfValue(1, 0))
2125 SDValue TCChain = Chain;
2126 SDNode *Copy = *N->use_begin();
2127 if (Copy->getOpcode() == ISD::CopyToReg) {
2128 // If the copy has a glue operand, we conservatively assume it isn't safe to
2129 // perform a tail call.
2130 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2132 TCChain = Copy->getOperand(0);
2133 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2136 bool HasRet = false;
2137 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2139 if (UI->getOpcode() != X86ISD::RET_FLAG)
2141 // If we are returning more than one value, we can definitely
2142 // not make a tail call see PR19530
2143 if (UI->getNumOperands() > 4)
2145 if (UI->getNumOperands() == 4 &&
2146 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2159 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2160 ISD::NodeType ExtendKind) const {
2162 // TODO: Is this also valid on 32-bit?
2163 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2164 ReturnMVT = MVT::i8;
2166 ReturnMVT = MVT::i32;
2168 EVT MinVT = getRegisterType(Context, ReturnMVT);
2169 return VT.bitsLT(MinVT) ? MinVT : VT;
2172 /// Lower the result values of a call into the
2173 /// appropriate copies out of appropriate physical registers.
2176 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2177 CallingConv::ID CallConv, bool isVarArg,
2178 const SmallVectorImpl<ISD::InputArg> &Ins,
2179 SDLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2182 // Assign locations to each value returned by this call.
2183 SmallVector<CCValAssign, 16> RVLocs;
2184 bool Is64Bit = Subtarget->is64Bit();
2185 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2187 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2189 // Copy all of the result registers out of their specified physreg.
2190 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2191 CCValAssign &VA = RVLocs[i];
2192 EVT CopyVT = VA.getLocVT();
2194 // If this is x86-64, and we disabled SSE, we can't return FP values
2195 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2196 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2197 report_fatal_error("SSE register return with SSE disabled");
2200 // If we prefer to use the value in xmm registers, copy it out as f80 and
2201 // use a truncate to move it from fp stack reg to xmm reg.
2202 bool RoundAfterCopy = false;
2203 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2204 isScalarFPTypeInSSEReg(VA.getValVT())) {
2206 RoundAfterCopy = (CopyVT != VA.getLocVT());
2209 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2210 CopyVT, InFlag).getValue(1);
2211 SDValue Val = Chain.getValue(0);
2214 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2215 // This truncation won't change the value.
2216 DAG.getIntPtrConstant(1, dl));
2218 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2219 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2221 InFlag = Chain.getValue(2);
2222 InVals.push_back(Val);
2228 //===----------------------------------------------------------------------===//
2229 // C & StdCall & Fast Calling Convention implementation
2230 //===----------------------------------------------------------------------===//
2231 // StdCall calling convention seems to be standard for many Windows' API
2232 // routines and around. It differs from C calling convention just a little:
2233 // callee should clean up the stack, not caller. Symbols should be also
2234 // decorated in some fancy way :) It doesn't support any vector arguments.
2235 // For info on fast calling convention see Fast Calling Convention (tail call)
2236 // implementation LowerX86_32FastCCCallTo.
2238 /// CallIsStructReturn - Determines whether a call uses struct return
2240 enum StructReturnType {
2245 static StructReturnType
2246 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2248 return NotStructReturn;
2250 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2251 if (!Flags.isSRet())
2252 return NotStructReturn;
2253 if (Flags.isInReg())
2254 return RegStructReturn;
2255 return StackStructReturn;
2258 /// Determines whether a function uses struct return semantics.
2259 static StructReturnType
2260 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2262 return NotStructReturn;
2264 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2265 if (!Flags.isSRet())
2266 return NotStructReturn;
2267 if (Flags.isInReg())
2268 return RegStructReturn;
2269 return StackStructReturn;
2272 /// Make a copy of an aggregate at address specified by "Src" to address
2273 /// "Dst" with size and alignment information specified by the specific
2274 /// parameter attribute. The copy will be passed as a byval function parameter.
2276 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2277 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2279 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2281 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2282 /*isVolatile*/false, /*AlwaysInline=*/true,
2283 /*isTailCall*/false,
2284 MachinePointerInfo(), MachinePointerInfo());
2287 /// Return true if the calling convention is one that
2288 /// supports tail call optimization.
2289 static bool IsTailCallConvention(CallingConv::ID CC) {
2290 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2291 CC == CallingConv::HiPE);
2294 /// \brief Return true if the calling convention is a C calling convention.
2295 static bool IsCCallConvention(CallingConv::ID CC) {
2296 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2297 CC == CallingConv::X86_64_SysV);
2300 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2302 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2303 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2307 CallingConv::ID CalleeCC = CS.getCallingConv();
2308 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2314 /// Return true if the function is being made into
2315 /// a tailcall target by changing its ABI.
2316 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2317 bool GuaranteedTailCallOpt) {
2318 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2322 X86TargetLowering::LowerMemArgument(SDValue Chain,
2323 CallingConv::ID CallConv,
2324 const SmallVectorImpl<ISD::InputArg> &Ins,
2325 SDLoc dl, SelectionDAG &DAG,
2326 const CCValAssign &VA,
2327 MachineFrameInfo *MFI,
2329 // Create the nodes corresponding to a load from this parameter slot.
2330 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2331 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2332 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2333 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2336 // If value is passed by pointer we have address passed instead of the value
2338 bool ExtendedInMem = VA.isExtInLoc() &&
2339 VA.getValVT().getScalarType() == MVT::i1;
2341 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2342 ValVT = VA.getLocVT();
2344 ValVT = VA.getValVT();
2346 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2347 // changed with more analysis.
2348 // In case of tail call optimization mark all arguments mutable. Since they
2349 // could be overwritten by lowering of arguments in case of a tail call.
2350 if (Flags.isByVal()) {
2351 unsigned Bytes = Flags.getByValSize();
2352 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2353 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2354 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2356 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2357 VA.getLocMemOffset(), isImmutable);
2358 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2359 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2360 MachinePointerInfo::getFixedStack(FI),
2361 false, false, false, 0);
2362 return ExtendedInMem ?
2363 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2367 // FIXME: Get this from tablegen.
2368 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2369 const X86Subtarget *Subtarget) {
2370 assert(Subtarget->is64Bit());
2372 if (Subtarget->isCallingConvWin64(CallConv)) {
2373 static const MCPhysReg GPR64ArgRegsWin64[] = {
2374 X86::RCX, X86::RDX, X86::R8, X86::R9
2376 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2379 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2380 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2382 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2385 // FIXME: Get this from tablegen.
2386 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2387 CallingConv::ID CallConv,
2388 const X86Subtarget *Subtarget) {
2389 assert(Subtarget->is64Bit());
2390 if (Subtarget->isCallingConvWin64(CallConv)) {
2391 // The XMM registers which might contain var arg parameters are shadowed
2392 // in their paired GPR. So we only need to save the GPR to their home
2394 // TODO: __vectorcall will change this.
2398 const Function *Fn = MF.getFunction();
2399 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2400 bool isSoftFloat = Subtarget->useSoftFloat();
2401 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2402 "SSE register cannot be used when SSE is disabled!");
2403 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2404 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2408 static const MCPhysReg XMMArgRegs64Bit[] = {
2409 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2410 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2412 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2416 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2417 CallingConv::ID CallConv,
2419 const SmallVectorImpl<ISD::InputArg> &Ins,
2422 SmallVectorImpl<SDValue> &InVals)
2424 MachineFunction &MF = DAG.getMachineFunction();
2425 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2426 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2428 const Function* Fn = MF.getFunction();
2429 if (Fn->hasExternalLinkage() &&
2430 Subtarget->isTargetCygMing() &&
2431 Fn->getName() == "main")
2432 FuncInfo->setForceFramePointer(true);
2434 MachineFrameInfo *MFI = MF.getFrameInfo();
2435 bool Is64Bit = Subtarget->is64Bit();
2436 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2438 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2439 "Var args not supported with calling convention fastcc, ghc or hipe");
2441 // Assign locations to all of the incoming arguments.
2442 SmallVector<CCValAssign, 16> ArgLocs;
2443 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2445 // Allocate shadow area for Win64
2447 CCInfo.AllocateStack(32, 8);
2449 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2451 unsigned LastVal = ~0U;
2453 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2454 CCValAssign &VA = ArgLocs[i];
2455 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2457 assert(VA.getValNo() != LastVal &&
2458 "Don't support value assigned to multiple locs yet");
2460 LastVal = VA.getValNo();
2462 if (VA.isRegLoc()) {
2463 EVT RegVT = VA.getLocVT();
2464 const TargetRegisterClass *RC;
2465 if (RegVT == MVT::i32)
2466 RC = &X86::GR32RegClass;
2467 else if (Is64Bit && RegVT == MVT::i64)
2468 RC = &X86::GR64RegClass;
2469 else if (RegVT == MVT::f32)
2470 RC = &X86::FR32RegClass;
2471 else if (RegVT == MVT::f64)
2472 RC = &X86::FR64RegClass;
2473 else if (RegVT.is512BitVector())
2474 RC = &X86::VR512RegClass;
2475 else if (RegVT.is256BitVector())
2476 RC = &X86::VR256RegClass;
2477 else if (RegVT.is128BitVector())
2478 RC = &X86::VR128RegClass;
2479 else if (RegVT == MVT::x86mmx)
2480 RC = &X86::VR64RegClass;
2481 else if (RegVT == MVT::i1)
2482 RC = &X86::VK1RegClass;
2483 else if (RegVT == MVT::v8i1)
2484 RC = &X86::VK8RegClass;
2485 else if (RegVT == MVT::v16i1)
2486 RC = &X86::VK16RegClass;
2487 else if (RegVT == MVT::v32i1)
2488 RC = &X86::VK32RegClass;
2489 else if (RegVT == MVT::v64i1)
2490 RC = &X86::VK64RegClass;
2492 llvm_unreachable("Unknown argument type!");
2494 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2495 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2497 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2498 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2500 if (VA.getLocInfo() == CCValAssign::SExt)
2501 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2502 DAG.getValueType(VA.getValVT()));
2503 else if (VA.getLocInfo() == CCValAssign::ZExt)
2504 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2505 DAG.getValueType(VA.getValVT()));
2506 else if (VA.getLocInfo() == CCValAssign::BCvt)
2507 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2509 if (VA.isExtInLoc()) {
2510 // Handle MMX values passed in XMM regs.
2511 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2512 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2514 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2517 assert(VA.isMemLoc());
2518 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2521 // If value is passed via pointer - do a load.
2522 if (VA.getLocInfo() == CCValAssign::Indirect)
2523 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2524 MachinePointerInfo(), false, false, false, 0);
2526 InVals.push_back(ArgValue);
2529 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2530 // All x86 ABIs require that for returning structs by value we copy the
2531 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2532 // the argument into a virtual register so that we can access it from the
2534 if (Ins[i].Flags.isSRet()) {
2535 unsigned Reg = FuncInfo->getSRetReturnReg();
2537 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2538 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2539 FuncInfo->setSRetReturnReg(Reg);
2541 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2542 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2547 unsigned StackSize = CCInfo.getNextStackOffset();
2548 // Align stack specially for tail calls.
2549 if (FuncIsMadeTailCallSafe(CallConv,
2550 MF.getTarget().Options.GuaranteedTailCallOpt))
2551 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2553 // If the function takes variable number of arguments, make a frame index for
2554 // the start of the first vararg value... for expansion of llvm.va_start. We
2555 // can skip this if there are no va_start calls.
2556 if (MFI->hasVAStart() &&
2557 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2558 CallConv != CallingConv::X86_ThisCall))) {
2559 FuncInfo->setVarArgsFrameIndex(
2560 MFI->CreateFixedObject(1, StackSize, true));
2563 MachineModuleInfo &MMI = MF.getMMI();
2564 const Function *WinEHParent = nullptr;
2565 if (MMI.hasWinEHFuncInfo(Fn))
2566 WinEHParent = MMI.getWinEHParent(Fn);
2567 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2568 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2570 // Figure out if XMM registers are in use.
2571 assert(!(Subtarget->useSoftFloat() &&
2572 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2573 "SSE register cannot be used when SSE is disabled!");
2575 // 64-bit calling conventions support varargs and register parameters, so we
2576 // have to do extra work to spill them in the prologue.
2577 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2578 // Find the first unallocated argument registers.
2579 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2580 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2581 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2582 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2583 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2584 "SSE register cannot be used when SSE is disabled!");
2586 // Gather all the live in physical registers.
2587 SmallVector<SDValue, 6> LiveGPRs;
2588 SmallVector<SDValue, 8> LiveXMMRegs;
2590 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2591 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2593 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2595 if (!ArgXMMs.empty()) {
2596 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2597 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2598 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2599 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2600 LiveXMMRegs.push_back(
2601 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2606 // Get to the caller-allocated home save location. Add 8 to account
2607 // for the return address.
2608 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2609 FuncInfo->setRegSaveFrameIndex(
2610 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2611 // Fixup to set vararg frame on shadow area (4 x i64).
2613 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2615 // For X86-64, if there are vararg parameters that are passed via
2616 // registers, then we must store them to their spots on the stack so
2617 // they may be loaded by deferencing the result of va_next.
2618 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2619 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2620 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2621 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2624 // Store the integer parameter registers.
2625 SmallVector<SDValue, 8> MemOps;
2626 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2627 getPointerTy(DAG.getDataLayout()));
2628 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2629 for (SDValue Val : LiveGPRs) {
2630 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2631 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2633 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2634 MachinePointerInfo::getFixedStack(
2635 FuncInfo->getRegSaveFrameIndex(), Offset),
2637 MemOps.push_back(Store);
2641 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2642 // Now store the XMM (fp + vector) parameter registers.
2643 SmallVector<SDValue, 12> SaveXMMOps;
2644 SaveXMMOps.push_back(Chain);
2645 SaveXMMOps.push_back(ALVal);
2646 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2647 FuncInfo->getRegSaveFrameIndex(), dl));
2648 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2649 FuncInfo->getVarArgsFPOffset(), dl));
2650 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2652 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2653 MVT::Other, SaveXMMOps));
2656 if (!MemOps.empty())
2657 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2658 } else if (IsWin64 && IsWinEHOutlined) {
2659 // Get to the caller-allocated home save location. Add 8 to account
2660 // for the return address.
2661 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2662 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2663 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2665 MMI.getWinEHFuncInfo(Fn)
2666 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2667 FuncInfo->getRegSaveFrameIndex();
2669 // Store the second integer parameter (rdx) into rsp+16 relative to the
2670 // stack pointer at the entry of the function.
2671 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2672 getPointerTy(DAG.getDataLayout()));
2673 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2674 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2675 Chain = DAG.getStore(
2676 Val.getValue(1), dl, Val, RSFIN,
2677 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2678 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2681 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2682 // Find the largest legal vector type.
2683 MVT VecVT = MVT::Other;
2684 // FIXME: Only some x86_32 calling conventions support AVX512.
2685 if (Subtarget->hasAVX512() &&
2686 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2687 CallConv == CallingConv::Intel_OCL_BI)))
2688 VecVT = MVT::v16f32;
2689 else if (Subtarget->hasAVX())
2691 else if (Subtarget->hasSSE2())
2694 // We forward some GPRs and some vector types.
2695 SmallVector<MVT, 2> RegParmTypes;
2696 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2697 RegParmTypes.push_back(IntVT);
2698 if (VecVT != MVT::Other)
2699 RegParmTypes.push_back(VecVT);
2701 // Compute the set of forwarded registers. The rest are scratch.
2702 SmallVectorImpl<ForwardedRegister> &Forwards =
2703 FuncInfo->getForwardedMustTailRegParms();
2704 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2706 // Conservatively forward AL on x86_64, since it might be used for varargs.
2707 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2708 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2709 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2712 // Copy all forwards from physical to virtual registers.
2713 for (ForwardedRegister &F : Forwards) {
2714 // FIXME: Can we use a less constrained schedule?
2715 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2716 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2717 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2721 // Some CCs need callee pop.
2722 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2723 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2724 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2726 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2727 // If this is an sret function, the return should pop the hidden pointer.
2728 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2729 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2730 argsAreStructReturn(Ins) == StackStructReturn)
2731 FuncInfo->setBytesToPopOnReturn(4);
2735 // RegSaveFrameIndex is X86-64 only.
2736 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2737 if (CallConv == CallingConv::X86_FastCall ||
2738 CallConv == CallingConv::X86_ThisCall)
2739 // fastcc functions can't have varargs.
2740 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2743 FuncInfo->setArgumentStackSize(StackSize);
2745 if (IsWinEHParent) {
2747 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2748 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2749 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2750 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2751 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2752 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2753 /*isVolatile=*/true,
2754 /*isNonTemporal=*/false, /*Alignment=*/0);
2756 // Functions using Win32 EH are considered to have opaque SP adjustments
2757 // to force local variables to be addressed from the frame or base
2759 MFI->setHasOpaqueSPAdjustment(true);
2767 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2768 SDValue StackPtr, SDValue Arg,
2769 SDLoc dl, SelectionDAG &DAG,
2770 const CCValAssign &VA,
2771 ISD::ArgFlagsTy Flags) const {
2772 unsigned LocMemOffset = VA.getLocMemOffset();
2773 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2774 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2776 if (Flags.isByVal())
2777 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2779 return DAG.getStore(Chain, dl, Arg, PtrOff,
2780 MachinePointerInfo::getStack(LocMemOffset),
2784 /// Emit a load of return address if tail call
2785 /// optimization is performed and it is required.
2787 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2788 SDValue &OutRetAddr, SDValue Chain,
2789 bool IsTailCall, bool Is64Bit,
2790 int FPDiff, SDLoc dl) const {
2791 // Adjust the Return address stack slot.
2792 EVT VT = getPointerTy(DAG.getDataLayout());
2793 OutRetAddr = getReturnAddressFrameIndex(DAG);
2795 // Load the "old" Return address.
2796 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2797 false, false, false, 0);
2798 return SDValue(OutRetAddr.getNode(), 1);
2801 /// Emit a store of the return address if tail call
2802 /// optimization is performed and it is required (FPDiff!=0).
2803 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2804 SDValue Chain, SDValue RetAddrFrIdx,
2805 EVT PtrVT, unsigned SlotSize,
2806 int FPDiff, SDLoc dl) {
2807 // Store the return address to the appropriate stack slot.
2808 if (!FPDiff) return Chain;
2809 // Calculate the new stack slot for the return address.
2810 int NewReturnAddrFI =
2811 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2813 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2814 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2815 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2821 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2822 SmallVectorImpl<SDValue> &InVals) const {
2823 SelectionDAG &DAG = CLI.DAG;
2825 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2826 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2827 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2828 SDValue Chain = CLI.Chain;
2829 SDValue Callee = CLI.Callee;
2830 CallingConv::ID CallConv = CLI.CallConv;
2831 bool &isTailCall = CLI.IsTailCall;
2832 bool isVarArg = CLI.IsVarArg;
2834 MachineFunction &MF = DAG.getMachineFunction();
2835 bool Is64Bit = Subtarget->is64Bit();
2836 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2837 StructReturnType SR = callIsStructReturn(Outs);
2838 bool IsSibcall = false;
2839 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2840 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2842 if (Attr.getValueAsString() == "true")
2845 if (Subtarget->isPICStyleGOT() &&
2846 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2847 // If we are using a GOT, disable tail calls to external symbols with
2848 // default visibility. Tail calling such a symbol requires using a GOT
2849 // relocation, which forces early binding of the symbol. This breaks code
2850 // that require lazy function symbol resolution. Using musttail or
2851 // GuaranteedTailCallOpt will override this.
2852 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2853 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2854 G->getGlobal()->hasDefaultVisibility()))
2858 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2860 // Force this to be a tail call. The verifier rules are enough to ensure
2861 // that we can lower this successfully without moving the return address
2864 } else if (isTailCall) {
2865 // Check if it's really possible to do a tail call.
2866 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2867 isVarArg, SR != NotStructReturn,
2868 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2869 Outs, OutVals, Ins, DAG);
2871 // Sibcalls are automatically detected tailcalls which do not require
2873 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2880 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2881 "Var args not supported with calling convention fastcc, ghc or hipe");
2883 // Analyze operands of the call, assigning locations to each operand.
2884 SmallVector<CCValAssign, 16> ArgLocs;
2885 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2887 // Allocate shadow area for Win64
2889 CCInfo.AllocateStack(32, 8);
2891 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2893 // Get a count of how many bytes are to be pushed on the stack.
2894 unsigned NumBytes = CCInfo.getNextStackOffset();
2896 // This is a sibcall. The memory operands are available in caller's
2897 // own caller's stack.
2899 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2900 IsTailCallConvention(CallConv))
2901 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2904 if (isTailCall && !IsSibcall && !IsMustTail) {
2905 // Lower arguments at fp - stackoffset + fpdiff.
2906 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2908 FPDiff = NumBytesCallerPushed - NumBytes;
2910 // Set the delta of movement of the returnaddr stackslot.
2911 // But only set if delta is greater than previous delta.
2912 if (FPDiff < X86Info->getTCReturnAddrDelta())
2913 X86Info->setTCReturnAddrDelta(FPDiff);
2916 unsigned NumBytesToPush = NumBytes;
2917 unsigned NumBytesToPop = NumBytes;
2919 // If we have an inalloca argument, all stack space has already been allocated
2920 // for us and be right at the top of the stack. We don't support multiple
2921 // arguments passed in memory when using inalloca.
2922 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2924 if (!ArgLocs.back().isMemLoc())
2925 report_fatal_error("cannot use inalloca attribute on a register "
2927 if (ArgLocs.back().getLocMemOffset() != 0)
2928 report_fatal_error("any parameter with the inalloca attribute must be "
2929 "the only memory argument");
2933 Chain = DAG.getCALLSEQ_START(
2934 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2936 SDValue RetAddrFrIdx;
2937 // Load return address for tail calls.
2938 if (isTailCall && FPDiff)
2939 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2940 Is64Bit, FPDiff, dl);
2942 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2943 SmallVector<SDValue, 8> MemOpChains;
2946 // Walk the register/memloc assignments, inserting copies/loads. In the case
2947 // of tail call optimization arguments are handle later.
2948 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2949 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2950 // Skip inalloca arguments, they have already been written.
2951 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2952 if (Flags.isInAlloca())
2955 CCValAssign &VA = ArgLocs[i];
2956 EVT RegVT = VA.getLocVT();
2957 SDValue Arg = OutVals[i];
2958 bool isByVal = Flags.isByVal();
2960 // Promote the value if needed.
2961 switch (VA.getLocInfo()) {
2962 default: llvm_unreachable("Unknown loc info!");
2963 case CCValAssign::Full: break;
2964 case CCValAssign::SExt:
2965 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2967 case CCValAssign::ZExt:
2968 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2970 case CCValAssign::AExt:
2971 if (Arg.getValueType().isVector() &&
2972 Arg.getValueType().getScalarType() == MVT::i1)
2973 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2974 else if (RegVT.is128BitVector()) {
2975 // Special case: passing MMX values in XMM registers.
2976 Arg = DAG.getBitcast(MVT::i64, Arg);
2977 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2978 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2980 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2982 case CCValAssign::BCvt:
2983 Arg = DAG.getBitcast(RegVT, Arg);
2985 case CCValAssign::Indirect: {
2986 // Store the argument.
2987 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2988 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2989 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2990 MachinePointerInfo::getFixedStack(FI),
2997 if (VA.isRegLoc()) {
2998 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2999 if (isVarArg && IsWin64) {
3000 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3001 // shadow reg if callee is a varargs function.
3002 unsigned ShadowReg = 0;
3003 switch (VA.getLocReg()) {
3004 case X86::XMM0: ShadowReg = X86::RCX; break;
3005 case X86::XMM1: ShadowReg = X86::RDX; break;
3006 case X86::XMM2: ShadowReg = X86::R8; break;
3007 case X86::XMM3: ShadowReg = X86::R9; break;
3010 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3012 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3013 assert(VA.isMemLoc());
3014 if (!StackPtr.getNode())
3015 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3016 getPointerTy(DAG.getDataLayout()));
3017 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3018 dl, DAG, VA, Flags));
3022 if (!MemOpChains.empty())
3023 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3025 if (Subtarget->isPICStyleGOT()) {
3026 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3029 RegsToPass.push_back(std::make_pair(
3030 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3031 getPointerTy(DAG.getDataLayout()))));
3033 // If we are tail calling and generating PIC/GOT style code load the
3034 // address of the callee into ECX. The value in ecx is used as target of
3035 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3036 // for tail calls on PIC/GOT architectures. Normally we would just put the
3037 // address of GOT into ebx and then call target@PLT. But for tail calls
3038 // ebx would be restored (since ebx is callee saved) before jumping to the
3041 // Note: The actual moving to ECX is done further down.
3042 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3043 if (G && !G->getGlobal()->hasLocalLinkage() &&
3044 G->getGlobal()->hasDefaultVisibility())
3045 Callee = LowerGlobalAddress(Callee, DAG);
3046 else if (isa<ExternalSymbolSDNode>(Callee))
3047 Callee = LowerExternalSymbol(Callee, DAG);
3051 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3052 // From AMD64 ABI document:
3053 // For calls that may call functions that use varargs or stdargs
3054 // (prototype-less calls or calls to functions containing ellipsis (...) in
3055 // the declaration) %al is used as hidden argument to specify the number
3056 // of SSE registers used. The contents of %al do not need to match exactly
3057 // the number of registers, but must be an ubound on the number of SSE
3058 // registers used and is in the range 0 - 8 inclusive.
3060 // Count the number of XMM registers allocated.
3061 static const MCPhysReg XMMArgRegs[] = {
3062 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3063 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3065 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3066 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3067 && "SSE registers cannot be used when SSE is disabled");
3069 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3070 DAG.getConstant(NumXMMRegs, dl,
3074 if (isVarArg && IsMustTail) {
3075 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3076 for (const auto &F : Forwards) {
3077 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3078 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3082 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3083 // don't need this because the eligibility check rejects calls that require
3084 // shuffling arguments passed in memory.
3085 if (!IsSibcall && isTailCall) {
3086 // Force all the incoming stack arguments to be loaded from the stack
3087 // before any new outgoing arguments are stored to the stack, because the
3088 // outgoing stack slots may alias the incoming argument stack slots, and
3089 // the alias isn't otherwise explicit. This is slightly more conservative
3090 // than necessary, because it means that each store effectively depends
3091 // on every argument instead of just those arguments it would clobber.
3092 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3094 SmallVector<SDValue, 8> MemOpChains2;
3097 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3098 CCValAssign &VA = ArgLocs[i];
3101 assert(VA.isMemLoc());
3102 SDValue Arg = OutVals[i];
3103 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3104 // Skip inalloca arguments. They don't require any work.
3105 if (Flags.isInAlloca())
3107 // Create frame index.
3108 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3109 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3110 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3111 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3113 if (Flags.isByVal()) {
3114 // Copy relative to framepointer.
3115 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3116 if (!StackPtr.getNode())
3117 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3118 getPointerTy(DAG.getDataLayout()));
3119 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3122 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3126 // Store relative to framepointer.
3127 MemOpChains2.push_back(
3128 DAG.getStore(ArgChain, dl, Arg, FIN,
3129 MachinePointerInfo::getFixedStack(FI),
3134 if (!MemOpChains2.empty())
3135 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3137 // Store the return address to the appropriate stack slot.
3138 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3139 getPointerTy(DAG.getDataLayout()),
3140 RegInfo->getSlotSize(), FPDiff, dl);
3143 // Build a sequence of copy-to-reg nodes chained together with token chain
3144 // and flag operands which copy the outgoing args into registers.
3146 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3147 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3148 RegsToPass[i].second, InFlag);
3149 InFlag = Chain.getValue(1);
3152 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3153 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3154 // In the 64-bit large code model, we have to make all calls
3155 // through a register, since the call instruction's 32-bit
3156 // pc-relative offset may not be large enough to hold the whole
3158 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3159 // If the callee is a GlobalAddress node (quite common, every direct call
3160 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3162 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3164 // We should use extra load for direct calls to dllimported functions in
3166 const GlobalValue *GV = G->getGlobal();
3167 if (!GV->hasDLLImportStorageClass()) {
3168 unsigned char OpFlags = 0;
3169 bool ExtraLoad = false;
3170 unsigned WrapperKind = ISD::DELETED_NODE;
3172 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3173 // external symbols most go through the PLT in PIC mode. If the symbol
3174 // has hidden or protected visibility, or if it is static or local, then
3175 // we don't need to use the PLT - we can directly call it.
3176 if (Subtarget->isTargetELF() &&
3177 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3178 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3179 OpFlags = X86II::MO_PLT;
3180 } else if (Subtarget->isPICStyleStubAny() &&
3181 !GV->isStrongDefinitionForLinker() &&
3182 (!Subtarget->getTargetTriple().isMacOSX() ||
3183 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3184 // PC-relative references to external symbols should go through $stub,
3185 // unless we're building with the leopard linker or later, which
3186 // automatically synthesizes these stubs.
3187 OpFlags = X86II::MO_DARWIN_STUB;
3188 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3189 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3190 // If the function is marked as non-lazy, generate an indirect call
3191 // which loads from the GOT directly. This avoids runtime overhead
3192 // at the cost of eager binding (and one extra byte of encoding).
3193 OpFlags = X86II::MO_GOTPCREL;
3194 WrapperKind = X86ISD::WrapperRIP;
3198 Callee = DAG.getTargetGlobalAddress(
3199 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3201 // Add a wrapper if needed.
3202 if (WrapperKind != ISD::DELETED_NODE)
3203 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3204 getPointerTy(DAG.getDataLayout()), Callee);
3205 // Add extra indirection if needed.
3207 Callee = DAG.getLoad(
3208 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3209 MachinePointerInfo::getGOT(), false, false, false, 0);
3211 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3212 unsigned char OpFlags = 0;
3214 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3215 // external symbols should go through the PLT.
3216 if (Subtarget->isTargetELF() &&
3217 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3218 OpFlags = X86II::MO_PLT;
3219 } else if (Subtarget->isPICStyleStubAny() &&
3220 (!Subtarget->getTargetTriple().isMacOSX() ||
3221 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3222 // PC-relative references to external symbols should go through $stub,
3223 // unless we're building with the leopard linker or later, which
3224 // automatically synthesizes these stubs.
3225 OpFlags = X86II::MO_DARWIN_STUB;
3228 Callee = DAG.getTargetExternalSymbol(
3229 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3230 } else if (Subtarget->isTarget64BitILP32() &&
3231 Callee->getValueType(0) == MVT::i32) {
3232 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3233 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3236 // Returns a chain & a flag for retval copy to use.
3237 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3238 SmallVector<SDValue, 8> Ops;
3240 if (!IsSibcall && isTailCall) {
3241 Chain = DAG.getCALLSEQ_END(Chain,
3242 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3243 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3244 InFlag = Chain.getValue(1);
3247 Ops.push_back(Chain);
3248 Ops.push_back(Callee);
3251 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3253 // Add argument registers to the end of the list so that they are known live
3255 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3256 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3257 RegsToPass[i].second.getValueType()));
3259 // Add a register mask operand representing the call-preserved registers.
3260 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3261 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3262 assert(Mask && "Missing call preserved mask for calling convention");
3263 Ops.push_back(DAG.getRegisterMask(Mask));
3265 if (InFlag.getNode())
3266 Ops.push_back(InFlag);
3270 //// If this is the first return lowered for this function, add the regs
3271 //// to the liveout set for the function.
3272 // This isn't right, although it's probably harmless on x86; liveouts
3273 // should be computed from returns not tail calls. Consider a void
3274 // function making a tail call to a function returning int.
3275 MF.getFrameInfo()->setHasTailCall();
3276 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3279 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3280 InFlag = Chain.getValue(1);
3282 // Create the CALLSEQ_END node.
3283 unsigned NumBytesForCalleeToPop;
3284 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3285 DAG.getTarget().Options.GuaranteedTailCallOpt))
3286 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3287 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3288 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3289 SR == StackStructReturn)
3290 // If this is a call to a struct-return function, the callee
3291 // pops the hidden struct pointer, so we have to push it back.
3292 // This is common for Darwin/X86, Linux & Mingw32 targets.
3293 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3294 NumBytesForCalleeToPop = 4;
3296 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3298 // Returns a flag for retval copy to use.
3300 Chain = DAG.getCALLSEQ_END(Chain,
3301 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3302 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3305 InFlag = Chain.getValue(1);
3308 // Handle result values, copying them out of physregs into vregs that we
3310 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3311 Ins, dl, DAG, InVals);
3314 //===----------------------------------------------------------------------===//
3315 // Fast Calling Convention (tail call) implementation
3316 //===----------------------------------------------------------------------===//
3318 // Like std call, callee cleans arguments, convention except that ECX is
3319 // reserved for storing the tail called function address. Only 2 registers are
3320 // free for argument passing (inreg). Tail call optimization is performed
3322 // * tailcallopt is enabled
3323 // * caller/callee are fastcc
3324 // On X86_64 architecture with GOT-style position independent code only local
3325 // (within module) calls are supported at the moment.
3326 // To keep the stack aligned according to platform abi the function
3327 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3328 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3329 // If a tail called function callee has more arguments than the caller the
3330 // caller needs to make sure that there is room to move the RETADDR to. This is
3331 // achieved by reserving an area the size of the argument delta right after the
3332 // original RETADDR, but before the saved framepointer or the spilled registers
3333 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3345 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3346 /// for a 16 byte align requirement.
3348 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3349 SelectionDAG& DAG) const {
3350 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3351 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3352 unsigned StackAlignment = TFI.getStackAlignment();
3353 uint64_t AlignMask = StackAlignment - 1;
3354 int64_t Offset = StackSize;
3355 unsigned SlotSize = RegInfo->getSlotSize();
3356 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3357 // Number smaller than 12 so just add the difference.
3358 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3360 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3361 Offset = ((~AlignMask) & Offset) + StackAlignment +
3362 (StackAlignment-SlotSize);
3367 /// MatchingStackOffset - Return true if the given stack call argument is
3368 /// already available in the same position (relatively) of the caller's
3369 /// incoming argument stack.
3371 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3372 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3373 const X86InstrInfo *TII) {
3374 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3376 if (Arg.getOpcode() == ISD::CopyFromReg) {
3377 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3378 if (!TargetRegisterInfo::isVirtualRegister(VR))
3380 MachineInstr *Def = MRI->getVRegDef(VR);
3383 if (!Flags.isByVal()) {
3384 if (!TII->isLoadFromStackSlot(Def, FI))
3387 unsigned Opcode = Def->getOpcode();
3388 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3389 Opcode == X86::LEA64_32r) &&
3390 Def->getOperand(1).isFI()) {
3391 FI = Def->getOperand(1).getIndex();
3392 Bytes = Flags.getByValSize();
3396 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3397 if (Flags.isByVal())
3398 // ByVal argument is passed in as a pointer but it's now being
3399 // dereferenced. e.g.
3400 // define @foo(%struct.X* %A) {
3401 // tail call @bar(%struct.X* byval %A)
3404 SDValue Ptr = Ld->getBasePtr();
3405 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3408 FI = FINode->getIndex();
3409 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3410 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3411 FI = FINode->getIndex();
3412 Bytes = Flags.getByValSize();
3416 assert(FI != INT_MAX);
3417 if (!MFI->isFixedObjectIndex(FI))
3419 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3422 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3423 /// for tail call optimization. Targets which want to do tail call
3424 /// optimization should implement this function.
3426 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3427 CallingConv::ID CalleeCC,
3429 bool isCalleeStructRet,
3430 bool isCallerStructRet,
3432 const SmallVectorImpl<ISD::OutputArg> &Outs,
3433 const SmallVectorImpl<SDValue> &OutVals,
3434 const SmallVectorImpl<ISD::InputArg> &Ins,
3435 SelectionDAG &DAG) const {
3436 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3439 // If -tailcallopt is specified, make fastcc functions tail-callable.
3440 const MachineFunction &MF = DAG.getMachineFunction();
3441 const Function *CallerF = MF.getFunction();
3443 // If the function return type is x86_fp80 and the callee return type is not,
3444 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3445 // perform a tailcall optimization here.
3446 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3449 CallingConv::ID CallerCC = CallerF->getCallingConv();
3450 bool CCMatch = CallerCC == CalleeCC;
3451 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3452 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3454 // Win64 functions have extra shadow space for argument homing. Don't do the
3455 // sibcall if the caller and callee have mismatched expectations for this
3457 if (IsCalleeWin64 != IsCallerWin64)
3460 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3461 if (IsTailCallConvention(CalleeCC) && CCMatch)
3466 // Look for obvious safe cases to perform tail call optimization that do not
3467 // require ABI changes. This is what gcc calls sibcall.
3469 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3470 // emit a special epilogue.
3471 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3472 if (RegInfo->needsStackRealignment(MF))
3475 // Also avoid sibcall optimization if either caller or callee uses struct
3476 // return semantics.
3477 if (isCalleeStructRet || isCallerStructRet)
3480 // An stdcall/thiscall caller is expected to clean up its arguments; the
3481 // callee isn't going to do that.
3482 // FIXME: this is more restrictive than needed. We could produce a tailcall
3483 // when the stack adjustment matches. For example, with a thiscall that takes
3484 // only one argument.
3485 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3486 CallerCC == CallingConv::X86_ThisCall))
3489 // Do not sibcall optimize vararg calls unless all arguments are passed via
3491 if (isVarArg && !Outs.empty()) {
3493 // Optimizing for varargs on Win64 is unlikely to be safe without
3494 // additional testing.
3495 if (IsCalleeWin64 || IsCallerWin64)
3498 SmallVector<CCValAssign, 16> ArgLocs;
3499 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3502 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3504 if (!ArgLocs[i].isRegLoc())
3508 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3509 // stack. Therefore, if it's not used by the call it is not safe to optimize
3510 // this into a sibcall.
3511 bool Unused = false;
3512 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3519 SmallVector<CCValAssign, 16> RVLocs;
3520 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3522 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3523 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3524 CCValAssign &VA = RVLocs[i];
3525 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3530 // If the calling conventions do not match, then we'd better make sure the
3531 // results are returned in the same way as what the caller expects.
3533 SmallVector<CCValAssign, 16> RVLocs1;
3534 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3536 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3538 SmallVector<CCValAssign, 16> RVLocs2;
3539 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3541 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3543 if (RVLocs1.size() != RVLocs2.size())
3545 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3546 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3548 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3550 if (RVLocs1[i].isRegLoc()) {
3551 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3554 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3560 // If the callee takes no arguments then go on to check the results of the
3562 if (!Outs.empty()) {
3563 // Check if stack adjustment is needed. For now, do not do this if any
3564 // argument is passed on the stack.
3565 SmallVector<CCValAssign, 16> ArgLocs;
3566 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3569 // Allocate shadow area for Win64
3571 CCInfo.AllocateStack(32, 8);
3573 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3574 if (CCInfo.getNextStackOffset()) {
3575 MachineFunction &MF = DAG.getMachineFunction();
3576 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3579 // Check if the arguments are already laid out in the right way as
3580 // the caller's fixed stack objects.
3581 MachineFrameInfo *MFI = MF.getFrameInfo();
3582 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3583 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3584 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3585 CCValAssign &VA = ArgLocs[i];
3586 SDValue Arg = OutVals[i];
3587 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3588 if (VA.getLocInfo() == CCValAssign::Indirect)
3590 if (!VA.isRegLoc()) {
3591 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3598 // If the tailcall address may be in a register, then make sure it's
3599 // possible to register allocate for it. In 32-bit, the call address can
3600 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3601 // callee-saved registers are restored. These happen to be the same
3602 // registers used to pass 'inreg' arguments so watch out for those.
3603 if (!Subtarget->is64Bit() &&
3604 ((!isa<GlobalAddressSDNode>(Callee) &&
3605 !isa<ExternalSymbolSDNode>(Callee)) ||
3606 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3607 unsigned NumInRegs = 0;
3608 // In PIC we need an extra register to formulate the address computation
3610 unsigned MaxInRegs =
3611 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3613 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3614 CCValAssign &VA = ArgLocs[i];
3617 unsigned Reg = VA.getLocReg();
3620 case X86::EAX: case X86::EDX: case X86::ECX:
3621 if (++NumInRegs == MaxInRegs)
3633 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3634 const TargetLibraryInfo *libInfo) const {
3635 return X86::createFastISel(funcInfo, libInfo);
3638 //===----------------------------------------------------------------------===//
3639 // Other Lowering Hooks
3640 //===----------------------------------------------------------------------===//
3642 static bool MayFoldLoad(SDValue Op) {
3643 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3646 static bool MayFoldIntoStore(SDValue Op) {
3647 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3650 static bool isTargetShuffle(unsigned Opcode) {
3652 default: return false;
3653 case X86ISD::BLENDI:
3654 case X86ISD::PSHUFB:
3655 case X86ISD::PSHUFD:
3656 case X86ISD::PSHUFHW:
3657 case X86ISD::PSHUFLW:
3659 case X86ISD::PALIGNR:
3660 case X86ISD::MOVLHPS:
3661 case X86ISD::MOVLHPD:
3662 case X86ISD::MOVHLPS:
3663 case X86ISD::MOVLPS:
3664 case X86ISD::MOVLPD:
3665 case X86ISD::MOVSHDUP:
3666 case X86ISD::MOVSLDUP:
3667 case X86ISD::MOVDDUP:
3670 case X86ISD::UNPCKL:
3671 case X86ISD::UNPCKH:
3672 case X86ISD::VPERMILPI:
3673 case X86ISD::VPERM2X128:
3674 case X86ISD::VPERMI:
3679 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3680 SDValue V1, unsigned TargetMask,
3681 SelectionDAG &DAG) {
3683 default: llvm_unreachable("Unknown x86 shuffle node");
3684 case X86ISD::PSHUFD:
3685 case X86ISD::PSHUFHW:
3686 case X86ISD::PSHUFLW:
3687 case X86ISD::VPERMILPI:
3688 case X86ISD::VPERMI:
3689 return DAG.getNode(Opc, dl, VT, V1,
3690 DAG.getConstant(TargetMask, dl, MVT::i8));
3694 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3695 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3697 default: llvm_unreachable("Unknown x86 shuffle node");
3698 case X86ISD::MOVLHPS:
3699 case X86ISD::MOVLHPD:
3700 case X86ISD::MOVHLPS:
3701 case X86ISD::MOVLPS:
3702 case X86ISD::MOVLPD:
3705 case X86ISD::UNPCKL:
3706 case X86ISD::UNPCKH:
3707 return DAG.getNode(Opc, dl, VT, V1, V2);
3711 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3712 MachineFunction &MF = DAG.getMachineFunction();
3713 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3714 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3715 int ReturnAddrIndex = FuncInfo->getRAIndex();
3717 if (ReturnAddrIndex == 0) {
3718 // Set up a frame object for the return address.
3719 unsigned SlotSize = RegInfo->getSlotSize();
3720 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3723 FuncInfo->setRAIndex(ReturnAddrIndex);
3726 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3729 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3730 bool hasSymbolicDisplacement) {
3731 // Offset should fit into 32 bit immediate field.
3732 if (!isInt<32>(Offset))
3735 // If we don't have a symbolic displacement - we don't have any extra
3737 if (!hasSymbolicDisplacement)
3740 // FIXME: Some tweaks might be needed for medium code model.
3741 if (M != CodeModel::Small && M != CodeModel::Kernel)
3744 // For small code model we assume that latest object is 16MB before end of 31
3745 // bits boundary. We may also accept pretty large negative constants knowing
3746 // that all objects are in the positive half of address space.
3747 if (M == CodeModel::Small && Offset < 16*1024*1024)
3750 // For kernel code model we know that all object resist in the negative half
3751 // of 32bits address space. We may not accept negative offsets, since they may
3752 // be just off and we may accept pretty large positive ones.
3753 if (M == CodeModel::Kernel && Offset >= 0)
3759 /// isCalleePop - Determines whether the callee is required to pop its
3760 /// own arguments. Callee pop is necessary to support tail calls.
3761 bool X86::isCalleePop(CallingConv::ID CallingConv,
3762 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3763 switch (CallingConv) {
3766 case CallingConv::X86_StdCall:
3767 case CallingConv::X86_FastCall:
3768 case CallingConv::X86_ThisCall:
3770 case CallingConv::Fast:
3771 case CallingConv::GHC:
3772 case CallingConv::HiPE:
3779 /// \brief Return true if the condition is an unsigned comparison operation.
3780 static bool isX86CCUnsigned(unsigned X86CC) {
3782 default: llvm_unreachable("Invalid integer condition!");
3783 case X86::COND_E: return true;
3784 case X86::COND_G: return false;
3785 case X86::COND_GE: return false;
3786 case X86::COND_L: return false;
3787 case X86::COND_LE: return false;
3788 case X86::COND_NE: return true;
3789 case X86::COND_B: return true;
3790 case X86::COND_A: return true;
3791 case X86::COND_BE: return true;
3792 case X86::COND_AE: return true;
3794 llvm_unreachable("covered switch fell through?!");
3797 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3798 /// specific condition code, returning the condition code and the LHS/RHS of the
3799 /// comparison to make.
3800 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3801 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3803 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3804 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3805 // X > -1 -> X == 0, jump !sign.
3806 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3807 return X86::COND_NS;
3809 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3810 // X < 0 -> X == 0, jump on sign.
3813 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3815 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3816 return X86::COND_LE;
3820 switch (SetCCOpcode) {
3821 default: llvm_unreachable("Invalid integer condition!");
3822 case ISD::SETEQ: return X86::COND_E;
3823 case ISD::SETGT: return X86::COND_G;
3824 case ISD::SETGE: return X86::COND_GE;
3825 case ISD::SETLT: return X86::COND_L;
3826 case ISD::SETLE: return X86::COND_LE;
3827 case ISD::SETNE: return X86::COND_NE;
3828 case ISD::SETULT: return X86::COND_B;
3829 case ISD::SETUGT: return X86::COND_A;
3830 case ISD::SETULE: return X86::COND_BE;
3831 case ISD::SETUGE: return X86::COND_AE;
3835 // First determine if it is required or is profitable to flip the operands.
3837 // If LHS is a foldable load, but RHS is not, flip the condition.
3838 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3839 !ISD::isNON_EXTLoad(RHS.getNode())) {
3840 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3841 std::swap(LHS, RHS);
3844 switch (SetCCOpcode) {
3850 std::swap(LHS, RHS);
3854 // On a floating point condition, the flags are set as follows:
3856 // 0 | 0 | 0 | X > Y
3857 // 0 | 0 | 1 | X < Y
3858 // 1 | 0 | 0 | X == Y
3859 // 1 | 1 | 1 | unordered
3860 switch (SetCCOpcode) {
3861 default: llvm_unreachable("Condcode should be pre-legalized away");
3863 case ISD::SETEQ: return X86::COND_E;
3864 case ISD::SETOLT: // flipped
3866 case ISD::SETGT: return X86::COND_A;
3867 case ISD::SETOLE: // flipped
3869 case ISD::SETGE: return X86::COND_AE;
3870 case ISD::SETUGT: // flipped
3872 case ISD::SETLT: return X86::COND_B;
3873 case ISD::SETUGE: // flipped
3875 case ISD::SETLE: return X86::COND_BE;
3877 case ISD::SETNE: return X86::COND_NE;
3878 case ISD::SETUO: return X86::COND_P;
3879 case ISD::SETO: return X86::COND_NP;
3881 case ISD::SETUNE: return X86::COND_INVALID;
3885 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3886 /// code. Current x86 isa includes the following FP cmov instructions:
3887 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3888 static bool hasFPCMov(unsigned X86CC) {
3904 /// isFPImmLegal - Returns true if the target can instruction select the
3905 /// specified FP immediate natively. If false, the legalizer will
3906 /// materialize the FP immediate as a load from a constant pool.
3907 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3908 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3909 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3915 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3916 ISD::LoadExtType ExtTy,
3918 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3919 // relocation target a movq or addq instruction: don't let the load shrink.
3920 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3921 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3922 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3923 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3927 /// \brief Returns true if it is beneficial to convert a load of a constant
3928 /// to just the constant itself.
3929 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3931 assert(Ty->isIntegerTy());
3933 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3934 if (BitSize == 0 || BitSize > 64)
3939 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3940 unsigned Index) const {
3941 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3944 return (Index == 0 || Index == ResVT.getVectorNumElements());
3947 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3948 // Speculate cttz only if we can directly use TZCNT.
3949 return Subtarget->hasBMI();
3952 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3953 // Speculate ctlz only if we can directly use LZCNT.
3954 return Subtarget->hasLZCNT();
3957 /// isUndefInRange - Return true if every element in Mask, beginning
3958 /// from position Pos and ending in Pos+Size is undef.
3959 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
3960 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
3966 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3967 /// the specified range (L, H].
3968 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3969 return (Val < 0) || (Val >= Low && Val < Hi);
3972 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3973 /// specified value.
3974 static bool isUndefOrEqual(int Val, int CmpVal) {
3975 return (Val < 0 || Val == CmpVal);
3978 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3979 /// from position Pos and ending in Pos+Size, falls within the specified
3980 /// sequential range (Low, Low+Size]. or is undef.
3981 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3982 unsigned Pos, unsigned Size, int Low) {
3983 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3984 if (!isUndefOrEqual(Mask[i], Low))
3989 /// isVEXTRACTIndex - Return true if the specified
3990 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3991 /// suitable for instruction that extract 128 or 256 bit vectors
3992 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3993 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3994 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3997 // The index should be aligned on a vecWidth-bit boundary.
3999 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4001 MVT VT = N->getSimpleValueType(0);
4002 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4003 bool Result = (Index * ElSize) % vecWidth == 0;
4008 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4009 /// operand specifies a subvector insert that is suitable for input to
4010 /// insertion of 128 or 256-bit subvectors
4011 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4012 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4013 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4015 // The index should be aligned on a vecWidth-bit boundary.
4017 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4019 MVT VT = N->getSimpleValueType(0);
4020 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4021 bool Result = (Index * ElSize) % vecWidth == 0;
4026 bool X86::isVINSERT128Index(SDNode *N) {
4027 return isVINSERTIndex(N, 128);
4030 bool X86::isVINSERT256Index(SDNode *N) {
4031 return isVINSERTIndex(N, 256);
4034 bool X86::isVEXTRACT128Index(SDNode *N) {
4035 return isVEXTRACTIndex(N, 128);
4038 bool X86::isVEXTRACT256Index(SDNode *N) {
4039 return isVEXTRACTIndex(N, 256);
4042 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4043 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4044 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4045 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4048 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4050 MVT VecVT = N->getOperand(0).getSimpleValueType();
4051 MVT ElVT = VecVT.getVectorElementType();
4053 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4054 return Index / NumElemsPerChunk;
4057 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4058 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4059 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4060 llvm_unreachable("Illegal insert subvector for VINSERT");
4063 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4065 MVT VecVT = N->getSimpleValueType(0);
4066 MVT ElVT = VecVT.getVectorElementType();
4068 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4069 return Index / NumElemsPerChunk;
4072 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4073 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4074 /// and VINSERTI128 instructions.
4075 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4076 return getExtractVEXTRACTImmediate(N, 128);
4079 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4080 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4081 /// and VINSERTI64x4 instructions.
4082 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4083 return getExtractVEXTRACTImmediate(N, 256);
4086 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4087 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4088 /// and VINSERTI128 instructions.
4089 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4090 return getInsertVINSERTImmediate(N, 128);
4093 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4094 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4095 /// and VINSERTI64x4 instructions.
4096 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4097 return getInsertVINSERTImmediate(N, 256);
4100 /// isZero - Returns true if Elt is a constant integer zero
4101 static bool isZero(SDValue V) {
4102 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4103 return C && C->isNullValue();
4106 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4108 bool X86::isZeroNode(SDValue Elt) {
4111 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4112 return CFP->getValueAPF().isPosZero();
4116 /// getZeroVector - Returns a vector of specified type with all zero elements.
4118 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4119 SelectionDAG &DAG, SDLoc dl) {
4120 assert(VT.isVector() && "Expected a vector type");
4122 // Always build SSE zero vectors as <4 x i32> bitcasted
4123 // to their dest type. This ensures they get CSE'd.
4125 if (VT.is128BitVector()) { // SSE
4126 if (Subtarget->hasSSE2()) { // SSE2
4127 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4128 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4130 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4131 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4133 } else if (VT.is256BitVector()) { // AVX
4134 if (Subtarget->hasInt256()) { // AVX2
4135 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4136 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4137 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4139 // 256-bit logic and arithmetic instructions in AVX are all
4140 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4141 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4142 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4143 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4145 } else if (VT.is512BitVector()) { // AVX-512
4146 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4147 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4148 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4149 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4150 } else if (VT.getScalarType() == MVT::i1) {
4152 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4153 && "Unexpected vector type");
4154 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4155 && "Unexpected vector type");
4156 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4157 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4158 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4160 llvm_unreachable("Unexpected vector type");
4162 return DAG.getBitcast(VT, Vec);
4165 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4166 SelectionDAG &DAG, SDLoc dl,
4167 unsigned vectorWidth) {
4168 assert((vectorWidth == 128 || vectorWidth == 256) &&
4169 "Unsupported vector width");
4170 EVT VT = Vec.getValueType();
4171 EVT ElVT = VT.getVectorElementType();
4172 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4173 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4174 VT.getVectorNumElements()/Factor);
4176 // Extract from UNDEF is UNDEF.
4177 if (Vec.getOpcode() == ISD::UNDEF)
4178 return DAG.getUNDEF(ResultVT);
4180 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4181 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4183 // This is the index of the first element of the vectorWidth-bit chunk
4185 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4188 // If the input is a buildvector just emit a smaller one.
4189 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4190 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4191 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4194 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4195 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4198 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4199 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4200 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4201 /// instructions or a simple subregister reference. Idx is an index in the
4202 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4203 /// lowering EXTRACT_VECTOR_ELT operations easier.
4204 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4205 SelectionDAG &DAG, SDLoc dl) {
4206 assert((Vec.getValueType().is256BitVector() ||
4207 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4208 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4211 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4212 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4213 SelectionDAG &DAG, SDLoc dl) {
4214 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4215 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4218 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4219 unsigned IdxVal, SelectionDAG &DAG,
4220 SDLoc dl, unsigned vectorWidth) {
4221 assert((vectorWidth == 128 || vectorWidth == 256) &&
4222 "Unsupported vector width");
4223 // Inserting UNDEF is Result
4224 if (Vec.getOpcode() == ISD::UNDEF)
4226 EVT VT = Vec.getValueType();
4227 EVT ElVT = VT.getVectorElementType();
4228 EVT ResultVT = Result.getValueType();
4230 // Insert the relevant vectorWidth bits.
4231 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4233 // This is the index of the first element of the vectorWidth-bit chunk
4235 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4238 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4239 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4242 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4243 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4244 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4245 /// simple superregister reference. Idx is an index in the 128 bits
4246 /// we want. It need not be aligned to a 128-bit boundary. That makes
4247 /// lowering INSERT_VECTOR_ELT operations easier.
4248 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4249 SelectionDAG &DAG, SDLoc dl) {
4250 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4252 // For insertion into the zero index (low half) of a 256-bit vector, it is
4253 // more efficient to generate a blend with immediate instead of an insert*128.
4254 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4255 // extend the subvector to the size of the result vector. Make sure that
4256 // we are not recursing on that node by checking for undef here.
4257 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4258 Result.getOpcode() != ISD::UNDEF) {
4259 EVT ResultVT = Result.getValueType();
4260 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4261 SDValue Undef = DAG.getUNDEF(ResultVT);
4262 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4265 // The blend instruction, and therefore its mask, depend on the data type.
4266 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4267 if (ScalarType.isFloatingPoint()) {
4268 // Choose either vblendps (float) or vblendpd (double).
4269 unsigned ScalarSize = ScalarType.getSizeInBits();
4270 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4271 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4272 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4273 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4276 const X86Subtarget &Subtarget =
4277 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4279 // AVX2 is needed for 256-bit integer blend support.
4280 // Integers must be cast to 32-bit because there is only vpblendd;
4281 // vpblendw can't be used for this because it has a handicapped mask.
4283 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4284 // is still more efficient than using the wrong domain vinsertf128 that
4285 // will be created by InsertSubVector().
4286 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4288 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4289 Vec256 = DAG.getBitcast(CastVT, Vec256);
4290 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4291 return DAG.getBitcast(ResultVT, Vec256);
4294 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4297 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4298 SelectionDAG &DAG, SDLoc dl) {
4299 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4300 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4303 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4304 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4305 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4306 /// large BUILD_VECTORS.
4307 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4308 unsigned NumElems, SelectionDAG &DAG,
4310 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4311 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4314 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4315 unsigned NumElems, SelectionDAG &DAG,
4317 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4318 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4321 /// getOnesVector - Returns a vector of specified type with all bits set.
4322 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4323 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4324 /// Then bitcast to their original type, ensuring they get CSE'd.
4325 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4327 assert(VT.isVector() && "Expected a vector type");
4329 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4331 if (VT.is256BitVector()) {
4332 if (HasInt256) { // AVX2
4333 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4334 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4336 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4337 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4339 } else if (VT.is128BitVector()) {
4340 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4342 llvm_unreachable("Unexpected vector type");
4344 return DAG.getBitcast(VT, Vec);
4347 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4348 /// operation of specified width.
4349 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4351 unsigned NumElems = VT.getVectorNumElements();
4352 SmallVector<int, 8> Mask;
4353 Mask.push_back(NumElems);
4354 for (unsigned i = 1; i != NumElems; ++i)
4356 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4359 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4360 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4362 unsigned NumElems = VT.getVectorNumElements();
4363 SmallVector<int, 8> Mask;
4364 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4366 Mask.push_back(i + NumElems);
4368 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4371 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4372 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4374 unsigned NumElems = VT.getVectorNumElements();
4375 SmallVector<int, 8> Mask;
4376 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4377 Mask.push_back(i + Half);
4378 Mask.push_back(i + NumElems + Half);
4380 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4383 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4384 /// vector of zero or undef vector. This produces a shuffle where the low
4385 /// element of V2 is swizzled into the zero/undef vector, landing at element
4386 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4387 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4389 const X86Subtarget *Subtarget,
4390 SelectionDAG &DAG) {
4391 MVT VT = V2.getSimpleValueType();
4393 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4394 unsigned NumElems = VT.getVectorNumElements();
4395 SmallVector<int, 16> MaskVec;
4396 for (unsigned i = 0; i != NumElems; ++i)
4397 // If this is the insertion idx, put the low elt of V2 here.
4398 MaskVec.push_back(i == Idx ? NumElems : i);
4399 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4402 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4403 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4404 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4405 /// shuffles which use a single input multiple times, and in those cases it will
4406 /// adjust the mask to only have indices within that single input.
4407 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4408 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4409 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4410 unsigned NumElems = VT.getVectorNumElements();
4414 bool IsFakeUnary = false;
4415 switch(N->getOpcode()) {
4416 case X86ISD::BLENDI:
4417 ImmN = N->getOperand(N->getNumOperands()-1);
4418 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4421 ImmN = N->getOperand(N->getNumOperands()-1);
4422 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4423 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4425 case X86ISD::UNPCKH:
4426 DecodeUNPCKHMask(VT, Mask);
4427 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4429 case X86ISD::UNPCKL:
4430 DecodeUNPCKLMask(VT, Mask);
4431 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4433 case X86ISD::MOVHLPS:
4434 DecodeMOVHLPSMask(NumElems, Mask);
4435 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4437 case X86ISD::MOVLHPS:
4438 DecodeMOVLHPSMask(NumElems, Mask);
4439 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4441 case X86ISD::PALIGNR:
4442 ImmN = N->getOperand(N->getNumOperands()-1);
4443 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4445 case X86ISD::PSHUFD:
4446 case X86ISD::VPERMILPI:
4447 ImmN = N->getOperand(N->getNumOperands()-1);
4448 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4451 case X86ISD::PSHUFHW:
4452 ImmN = N->getOperand(N->getNumOperands()-1);
4453 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4456 case X86ISD::PSHUFLW:
4457 ImmN = N->getOperand(N->getNumOperands()-1);
4458 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4461 case X86ISD::PSHUFB: {
4463 SDValue MaskNode = N->getOperand(1);
4464 while (MaskNode->getOpcode() == ISD::BITCAST)
4465 MaskNode = MaskNode->getOperand(0);
4467 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4468 // If we have a build-vector, then things are easy.
4469 EVT VT = MaskNode.getValueType();
4470 assert(VT.isVector() &&
4471 "Can't produce a non-vector with a build_vector!");
4472 if (!VT.isInteger())
4475 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4477 SmallVector<uint64_t, 32> RawMask;
4478 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4479 SDValue Op = MaskNode->getOperand(i);
4480 if (Op->getOpcode() == ISD::UNDEF) {
4481 RawMask.push_back((uint64_t)SM_SentinelUndef);
4484 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4487 APInt MaskElement = CN->getAPIntValue();
4489 // We now have to decode the element which could be any integer size and
4490 // extract each byte of it.
4491 for (int j = 0; j < NumBytesPerElement; ++j) {
4492 // Note that this is x86 and so always little endian: the low byte is
4493 // the first byte of the mask.
4494 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4495 MaskElement = MaskElement.lshr(8);
4498 DecodePSHUFBMask(RawMask, Mask);
4502 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4506 SDValue Ptr = MaskLoad->getBasePtr();
4507 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4508 Ptr->getOpcode() == X86ISD::WrapperRIP)
4509 Ptr = Ptr->getOperand(0);
4511 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4512 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4515 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4516 DecodePSHUFBMask(C, Mask);
4524 case X86ISD::VPERMI:
4525 ImmN = N->getOperand(N->getNumOperands()-1);
4526 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4531 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4533 case X86ISD::VPERM2X128:
4534 ImmN = N->getOperand(N->getNumOperands()-1);
4535 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4536 if (Mask.empty()) return false;
4537 // Mask only contains negative index if an element is zero.
4538 if (std::any_of(Mask.begin(), Mask.end(),
4539 [](int M){ return M == SM_SentinelZero; }))
4542 case X86ISD::MOVSLDUP:
4543 DecodeMOVSLDUPMask(VT, Mask);
4546 case X86ISD::MOVSHDUP:
4547 DecodeMOVSHDUPMask(VT, Mask);
4550 case X86ISD::MOVDDUP:
4551 DecodeMOVDDUPMask(VT, Mask);
4554 case X86ISD::MOVLHPD:
4555 case X86ISD::MOVLPD:
4556 case X86ISD::MOVLPS:
4557 // Not yet implemented
4559 default: llvm_unreachable("unknown target shuffle node");
4562 // If we have a fake unary shuffle, the shuffle mask is spread across two
4563 // inputs that are actually the same node. Re-map the mask to always point
4564 // into the first input.
4567 if (M >= (int)Mask.size())
4573 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4574 /// element of the result of the vector shuffle.
4575 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4578 return SDValue(); // Limit search depth.
4580 SDValue V = SDValue(N, 0);
4581 EVT VT = V.getValueType();
4582 unsigned Opcode = V.getOpcode();
4584 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4585 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4586 int Elt = SV->getMaskElt(Index);
4589 return DAG.getUNDEF(VT.getVectorElementType());
4591 unsigned NumElems = VT.getVectorNumElements();
4592 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4593 : SV->getOperand(1);
4594 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4597 // Recurse into target specific vector shuffles to find scalars.
4598 if (isTargetShuffle(Opcode)) {
4599 MVT ShufVT = V.getSimpleValueType();
4600 unsigned NumElems = ShufVT.getVectorNumElements();
4601 SmallVector<int, 16> ShuffleMask;
4604 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4607 int Elt = ShuffleMask[Index];
4609 return DAG.getUNDEF(ShufVT.getVectorElementType());
4611 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4613 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4617 // Actual nodes that may contain scalar elements
4618 if (Opcode == ISD::BITCAST) {
4619 V = V.getOperand(0);
4620 EVT SrcVT = V.getValueType();
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4627 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4628 return (Index == 0) ? V.getOperand(0)
4629 : DAG.getUNDEF(VT.getVectorElementType());
4631 if (V.getOpcode() == ISD::BUILD_VECTOR)
4632 return V.getOperand(Index);
4637 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4639 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4640 unsigned NumNonZero, unsigned NumZero,
4642 const X86Subtarget* Subtarget,
4643 const TargetLowering &TLI) {
4651 // SSE4.1 - use PINSRB to insert each byte directly.
4652 if (Subtarget->hasSSE41()) {
4653 for (unsigned i = 0; i < 16; ++i) {
4654 bool isNonZero = (NonZeros & (1 << i)) != 0;
4658 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4660 V = DAG.getUNDEF(MVT::v16i8);
4663 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4664 MVT::v16i8, V, Op.getOperand(i),
4665 DAG.getIntPtrConstant(i, dl));
4672 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4673 for (unsigned i = 0; i < 16; ++i) {
4674 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4675 if (ThisIsNonZero && First) {
4677 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4679 V = DAG.getUNDEF(MVT::v8i16);
4684 SDValue ThisElt, LastElt;
4685 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4686 if (LastIsNonZero) {
4687 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4688 MVT::i16, Op.getOperand(i-1));
4690 if (ThisIsNonZero) {
4691 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4692 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4693 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4695 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4699 if (ThisElt.getNode())
4700 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4701 DAG.getIntPtrConstant(i/2, dl));
4705 return DAG.getBitcast(MVT::v16i8, V);
4708 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4710 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4711 unsigned NumNonZero, unsigned NumZero,
4713 const X86Subtarget* Subtarget,
4714 const TargetLowering &TLI) {
4721 for (unsigned i = 0; i < 8; ++i) {
4722 bool isNonZero = (NonZeros & (1 << i)) != 0;
4726 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4728 V = DAG.getUNDEF(MVT::v8i16);
4731 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4732 MVT::v8i16, V, Op.getOperand(i),
4733 DAG.getIntPtrConstant(i, dl));
4740 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4741 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4742 const X86Subtarget *Subtarget,
4743 const TargetLowering &TLI) {
4744 // Find all zeroable elements.
4745 std::bitset<4> Zeroable;
4746 for (int i=0; i < 4; ++i) {
4747 SDValue Elt = Op->getOperand(i);
4748 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4750 assert(Zeroable.size() - Zeroable.count() > 1 &&
4751 "We expect at least two non-zero elements!");
4753 // We only know how to deal with build_vector nodes where elements are either
4754 // zeroable or extract_vector_elt with constant index.
4755 SDValue FirstNonZero;
4756 unsigned FirstNonZeroIdx;
4757 for (unsigned i=0; i < 4; ++i) {
4760 SDValue Elt = Op->getOperand(i);
4761 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4762 !isa<ConstantSDNode>(Elt.getOperand(1)))
4764 // Make sure that this node is extracting from a 128-bit vector.
4765 MVT VT = Elt.getOperand(0).getSimpleValueType();
4766 if (!VT.is128BitVector())
4768 if (!FirstNonZero.getNode()) {
4770 FirstNonZeroIdx = i;
4774 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4775 SDValue V1 = FirstNonZero.getOperand(0);
4776 MVT VT = V1.getSimpleValueType();
4778 // See if this build_vector can be lowered as a blend with zero.
4780 unsigned EltMaskIdx, EltIdx;
4782 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4783 if (Zeroable[EltIdx]) {
4784 // The zero vector will be on the right hand side.
4785 Mask[EltIdx] = EltIdx+4;
4789 Elt = Op->getOperand(EltIdx);
4790 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4791 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4792 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4794 Mask[EltIdx] = EltIdx;
4798 // Let the shuffle legalizer deal with blend operations.
4799 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4800 if (V1.getSimpleValueType() != VT)
4801 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4802 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4805 // See if we can lower this build_vector to a INSERTPS.
4806 if (!Subtarget->hasSSE41())
4809 SDValue V2 = Elt.getOperand(0);
4810 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4813 bool CanFold = true;
4814 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4818 SDValue Current = Op->getOperand(i);
4819 SDValue SrcVector = Current->getOperand(0);
4822 CanFold = SrcVector == V1 &&
4823 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4829 assert(V1.getNode() && "Expected at least two non-zero elements!");
4830 if (V1.getSimpleValueType() != MVT::v4f32)
4831 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4832 if (V2.getSimpleValueType() != MVT::v4f32)
4833 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4835 // Ok, we can emit an INSERTPS instruction.
4836 unsigned ZMask = Zeroable.to_ulong();
4838 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4839 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4841 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4842 DAG.getIntPtrConstant(InsertPSMask, DL));
4843 return DAG.getBitcast(VT, Result);
4846 /// Return a vector logical shift node.
4847 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4848 unsigned NumBits, SelectionDAG &DAG,
4849 const TargetLowering &TLI, SDLoc dl) {
4850 assert(VT.is128BitVector() && "Unknown type for VShift");
4851 MVT ShVT = MVT::v2i64;
4852 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4853 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4854 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout());
4855 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4856 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4857 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4861 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4863 // Check if the scalar load can be widened into a vector load. And if
4864 // the address is "base + cst" see if the cst can be "absorbed" into
4865 // the shuffle mask.
4866 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4867 SDValue Ptr = LD->getBasePtr();
4868 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4870 EVT PVT = LD->getValueType(0);
4871 if (PVT != MVT::i32 && PVT != MVT::f32)
4876 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4877 FI = FINode->getIndex();
4879 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4880 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4881 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4882 Offset = Ptr.getConstantOperandVal(1);
4883 Ptr = Ptr.getOperand(0);
4888 // FIXME: 256-bit vector instructions don't require a strict alignment,
4889 // improve this code to support it better.
4890 unsigned RequiredAlign = VT.getSizeInBits()/8;
4891 SDValue Chain = LD->getChain();
4892 // Make sure the stack object alignment is at least 16 or 32.
4893 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4894 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4895 if (MFI->isFixedObjectIndex(FI)) {
4896 // Can't change the alignment. FIXME: It's possible to compute
4897 // the exact stack offset and reference FI + adjust offset instead.
4898 // If someone *really* cares about this. That's the way to implement it.
4901 MFI->setObjectAlignment(FI, RequiredAlign);
4905 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4906 // Ptr + (Offset & ~15).
4909 if ((Offset % RequiredAlign) & 3)
4911 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4914 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4915 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4918 int EltNo = (Offset - StartOffset) >> 2;
4919 unsigned NumElems = VT.getVectorNumElements();
4921 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4922 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4923 LD->getPointerInfo().getWithOffset(StartOffset),
4924 false, false, false, 0);
4926 SmallVector<int, 8> Mask(NumElems, EltNo);
4928 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4934 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4935 /// elements can be replaced by a single large load which has the same value as
4936 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4938 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4940 /// FIXME: we'd also like to handle the case where the last elements are zero
4941 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4942 /// There's even a handy isZeroNode for that purpose.
4943 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4944 SDLoc &DL, SelectionDAG &DAG,
4945 bool isAfterLegalize) {
4946 unsigned NumElems = Elts.size();
4948 LoadSDNode *LDBase = nullptr;
4949 unsigned LastLoadedElt = -1U;
4951 // For each element in the initializer, see if we've found a load or an undef.
4952 // If we don't find an initial load element, or later load elements are
4953 // non-consecutive, bail out.
4954 for (unsigned i = 0; i < NumElems; ++i) {
4955 SDValue Elt = Elts[i];
4956 // Look through a bitcast.
4957 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4958 Elt = Elt.getOperand(0);
4959 if (!Elt.getNode() ||
4960 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4963 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4965 LDBase = cast<LoadSDNode>(Elt.getNode());
4969 if (Elt.getOpcode() == ISD::UNDEF)
4972 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4973 EVT LdVT = Elt.getValueType();
4974 // Each loaded element must be the correct fractional portion of the
4975 // requested vector load.
4976 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4978 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4983 // If we have found an entire vector of loads and undefs, then return a large
4984 // load of the entire vector width starting at the base pointer. If we found
4985 // consecutive loads for the low half, generate a vzext_load node.
4986 if (LastLoadedElt == NumElems - 1) {
4987 assert(LDBase && "Did not find base load for merging consecutive loads");
4988 EVT EltVT = LDBase->getValueType(0);
4989 // Ensure that the input vector size for the merged loads matches the
4990 // cumulative size of the input elements.
4991 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4994 if (isAfterLegalize &&
4995 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4998 SDValue NewLd = SDValue();
5000 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5001 LDBase->getPointerInfo(), LDBase->isVolatile(),
5002 LDBase->isNonTemporal(), LDBase->isInvariant(),
5003 LDBase->getAlignment());
5005 if (LDBase->hasAnyUseOfValue(1)) {
5006 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5008 SDValue(NewLd.getNode(), 1));
5009 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5010 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5011 SDValue(NewLd.getNode(), 1));
5017 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5018 //of a v4i32 / v4f32. It's probably worth generalizing.
5019 EVT EltVT = VT.getVectorElementType();
5020 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5021 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5022 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5023 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5025 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5026 LDBase->getPointerInfo(),
5027 LDBase->getAlignment(),
5028 false/*isVolatile*/, true/*ReadMem*/,
5031 // Make sure the newly-created LOAD is in the same position as LDBase in
5032 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5033 // update uses of LDBase's output chain to use the TokenFactor.
5034 if (LDBase->hasAnyUseOfValue(1)) {
5035 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5036 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5037 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5038 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5039 SDValue(ResNode.getNode(), 1));
5042 return DAG.getBitcast(VT, ResNode);
5047 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5048 /// to generate a splat value for the following cases:
5049 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5050 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5051 /// a scalar load, or a constant.
5052 /// The VBROADCAST node is returned when a pattern is found,
5053 /// or SDValue() otherwise.
5054 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5055 SelectionDAG &DAG) {
5056 // VBROADCAST requires AVX.
5057 // TODO: Splats could be generated for non-AVX CPUs using SSE
5058 // instructions, but there's less potential gain for only 128-bit vectors.
5059 if (!Subtarget->hasAVX())
5062 MVT VT = Op.getSimpleValueType();
5065 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5066 "Unsupported vector type for broadcast.");
5071 switch (Op.getOpcode()) {
5073 // Unknown pattern found.
5076 case ISD::BUILD_VECTOR: {
5077 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5078 BitVector UndefElements;
5079 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5081 // We need a splat of a single value to use broadcast, and it doesn't
5082 // make any sense if the value is only in one element of the vector.
5083 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5087 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5088 Ld.getOpcode() == ISD::ConstantFP);
5090 // Make sure that all of the users of a non-constant load are from the
5091 // BUILD_VECTOR node.
5092 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5097 case ISD::VECTOR_SHUFFLE: {
5098 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5100 // Shuffles must have a splat mask where the first element is
5102 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5105 SDValue Sc = Op.getOperand(0);
5106 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5107 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5109 if (!Subtarget->hasInt256())
5112 // Use the register form of the broadcast instruction available on AVX2.
5113 if (VT.getSizeInBits() >= 256)
5114 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5115 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5118 Ld = Sc.getOperand(0);
5119 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5120 Ld.getOpcode() == ISD::ConstantFP);
5122 // The scalar_to_vector node and the suspected
5123 // load node must have exactly one user.
5124 // Constants may have multiple users.
5126 // AVX-512 has register version of the broadcast
5127 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5128 Ld.getValueType().getSizeInBits() >= 32;
5129 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5136 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5137 bool IsGE256 = (VT.getSizeInBits() >= 256);
5139 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5140 // instruction to save 8 or more bytes of constant pool data.
5141 // TODO: If multiple splats are generated to load the same constant,
5142 // it may be detrimental to overall size. There needs to be a way to detect
5143 // that condition to know if this is truly a size win.
5144 const Function *F = DAG.getMachineFunction().getFunction();
5145 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5147 // Handle broadcasting a single constant scalar from the constant pool
5149 // On Sandybridge (no AVX2), it is still better to load a constant vector
5150 // from the constant pool and not to broadcast it from a scalar.
5151 // But override that restriction when optimizing for size.
5152 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5153 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5154 EVT CVT = Ld.getValueType();
5155 assert(!CVT.isVector() && "Must not broadcast a vector type");
5157 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5158 // For size optimization, also splat v2f64 and v2i64, and for size opt
5159 // with AVX2, also splat i8 and i16.
5160 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5161 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5162 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5163 const Constant *C = nullptr;
5164 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5165 C = CI->getConstantIntValue();
5166 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5167 C = CF->getConstantFPValue();
5169 assert(C && "Invalid constant type");
5171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5173 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5174 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5175 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5176 MachinePointerInfo::getConstantPool(),
5177 false, false, false, Alignment);
5179 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5183 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5185 // Handle AVX2 in-register broadcasts.
5186 if (!IsLoad && Subtarget->hasInt256() &&
5187 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5188 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5190 // The scalar source must be a normal load.
5194 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5195 (Subtarget->hasVLX() && ScalarSize == 64))
5196 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5198 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5199 // double since there is no vbroadcastsd xmm
5200 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5201 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5202 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5205 // Unsupported broadcast.
5209 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5210 /// underlying vector and index.
5212 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5214 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5216 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5217 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5220 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5222 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5224 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5225 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5228 // In this case the vector is the extract_subvector expression and the index
5229 // is 2, as specified by the shuffle.
5230 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5231 SDValue ShuffleVec = SVOp->getOperand(0);
5232 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5233 assert(ShuffleVecVT.getVectorElementType() ==
5234 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5236 int ShuffleIdx = SVOp->getMaskElt(Idx);
5237 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5238 ExtractedFromVec = ShuffleVec;
5244 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5245 MVT VT = Op.getSimpleValueType();
5247 // Skip if insert_vec_elt is not supported.
5248 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5249 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5253 unsigned NumElems = Op.getNumOperands();
5257 SmallVector<unsigned, 4> InsertIndices;
5258 SmallVector<int, 8> Mask(NumElems, -1);
5260 for (unsigned i = 0; i != NumElems; ++i) {
5261 unsigned Opc = Op.getOperand(i).getOpcode();
5263 if (Opc == ISD::UNDEF)
5266 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5267 // Quit if more than 1 elements need inserting.
5268 if (InsertIndices.size() > 1)
5271 InsertIndices.push_back(i);
5275 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5276 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5277 // Quit if non-constant index.
5278 if (!isa<ConstantSDNode>(ExtIdx))
5280 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5282 // Quit if extracted from vector of different type.
5283 if (ExtractedFromVec.getValueType() != VT)
5286 if (!VecIn1.getNode())
5287 VecIn1 = ExtractedFromVec;
5288 else if (VecIn1 != ExtractedFromVec) {
5289 if (!VecIn2.getNode())
5290 VecIn2 = ExtractedFromVec;
5291 else if (VecIn2 != ExtractedFromVec)
5292 // Quit if more than 2 vectors to shuffle
5296 if (ExtractedFromVec == VecIn1)
5298 else if (ExtractedFromVec == VecIn2)
5299 Mask[i] = Idx + NumElems;
5302 if (!VecIn1.getNode())
5305 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5306 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5307 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5308 unsigned Idx = InsertIndices[i];
5309 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5310 DAG.getIntPtrConstant(Idx, DL));
5316 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5317 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5318 Op.getScalarValueSizeInBits() == 1 &&
5319 "Can not convert non-constant vector");
5320 uint64_t Immediate = 0;
5321 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5322 SDValue In = Op.getOperand(idx);
5323 if (In.getOpcode() != ISD::UNDEF)
5324 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5328 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5329 return DAG.getConstant(Immediate, dl, VT);
5331 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5333 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5335 MVT VT = Op.getSimpleValueType();
5336 assert((VT.getVectorElementType() == MVT::i1) &&
5337 "Unexpected type in LowerBUILD_VECTORvXi1!");
5340 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5341 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5342 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5343 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5346 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5347 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5348 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5349 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5352 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5353 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5354 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5355 return DAG.getBitcast(VT, Imm);
5356 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5357 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5358 DAG.getIntPtrConstant(0, dl));
5361 // Vector has one or more non-const elements
5362 uint64_t Immediate = 0;
5363 SmallVector<unsigned, 16> NonConstIdx;
5364 bool IsSplat = true;
5365 bool HasConstElts = false;
5367 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5368 SDValue In = Op.getOperand(idx);
5369 if (In.getOpcode() == ISD::UNDEF)
5371 if (!isa<ConstantSDNode>(In))
5372 NonConstIdx.push_back(idx);
5374 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5375 HasConstElts = true;
5379 else if (In != Op.getOperand(SplatIdx))
5383 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5385 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5386 DAG.getConstant(1, dl, VT),
5387 DAG.getConstant(0, dl, VT));
5389 // insert elements one by one
5393 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5394 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5396 else if (HasConstElts)
5397 Imm = DAG.getConstant(0, dl, VT);
5399 Imm = DAG.getUNDEF(VT);
5400 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5401 DstVec = DAG.getBitcast(VT, Imm);
5403 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5404 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5405 DAG.getIntPtrConstant(0, dl));
5408 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5409 unsigned InsertIdx = NonConstIdx[i];
5410 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5411 Op.getOperand(InsertIdx),
5412 DAG.getIntPtrConstant(InsertIdx, dl));
5417 /// \brief Return true if \p N implements a horizontal binop and return the
5418 /// operands for the horizontal binop into V0 and V1.
5420 /// This is a helper function of LowerToHorizontalOp().
5421 /// This function checks that the build_vector \p N in input implements a
5422 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5423 /// operation to match.
5424 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5425 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5426 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5429 /// This function only analyzes elements of \p N whose indices are
5430 /// in range [BaseIdx, LastIdx).
5431 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5433 unsigned BaseIdx, unsigned LastIdx,
5434 SDValue &V0, SDValue &V1) {
5435 EVT VT = N->getValueType(0);
5437 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5438 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5439 "Invalid Vector in input!");
5441 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5442 bool CanFold = true;
5443 unsigned ExpectedVExtractIdx = BaseIdx;
5444 unsigned NumElts = LastIdx - BaseIdx;
5445 V0 = DAG.getUNDEF(VT);
5446 V1 = DAG.getUNDEF(VT);
5448 // Check if N implements a horizontal binop.
5449 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5450 SDValue Op = N->getOperand(i + BaseIdx);
5453 if (Op->getOpcode() == ISD::UNDEF) {
5454 // Update the expected vector extract index.
5455 if (i * 2 == NumElts)
5456 ExpectedVExtractIdx = BaseIdx;
5457 ExpectedVExtractIdx += 2;
5461 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5466 SDValue Op0 = Op.getOperand(0);
5467 SDValue Op1 = Op.getOperand(1);
5469 // Try to match the following pattern:
5470 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5471 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5472 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5473 Op0.getOperand(0) == Op1.getOperand(0) &&
5474 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5475 isa<ConstantSDNode>(Op1.getOperand(1)));
5479 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5480 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5482 if (i * 2 < NumElts) {
5483 if (V0.getOpcode() == ISD::UNDEF) {
5484 V0 = Op0.getOperand(0);
5485 if (V0.getValueType() != VT)
5489 if (V1.getOpcode() == ISD::UNDEF) {
5490 V1 = Op0.getOperand(0);
5491 if (V1.getValueType() != VT)
5494 if (i * 2 == NumElts)
5495 ExpectedVExtractIdx = BaseIdx;
5498 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5499 if (I0 == ExpectedVExtractIdx)
5500 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5501 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5502 // Try to match the following dag sequence:
5503 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5504 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5508 ExpectedVExtractIdx += 2;
5514 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5515 /// a concat_vector.
5517 /// This is a helper function of LowerToHorizontalOp().
5518 /// This function expects two 256-bit vectors called V0 and V1.
5519 /// At first, each vector is split into two separate 128-bit vectors.
5520 /// Then, the resulting 128-bit vectors are used to implement two
5521 /// horizontal binary operations.
5523 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5525 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5526 /// the two new horizontal binop.
5527 /// When Mode is set, the first horizontal binop dag node would take as input
5528 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5529 /// horizontal binop dag node would take as input the lower 128-bit of V1
5530 /// and the upper 128-bit of V1.
5532 /// HADD V0_LO, V0_HI
5533 /// HADD V1_LO, V1_HI
5535 /// Otherwise, the first horizontal binop dag node takes as input the lower
5536 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5537 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5539 /// HADD V0_LO, V1_LO
5540 /// HADD V0_HI, V1_HI
5542 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5543 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5544 /// the upper 128-bits of the result.
5545 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5546 SDLoc DL, SelectionDAG &DAG,
5547 unsigned X86Opcode, bool Mode,
5548 bool isUndefLO, bool isUndefHI) {
5549 EVT VT = V0.getValueType();
5550 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5551 "Invalid nodes in input!");
5553 unsigned NumElts = VT.getVectorNumElements();
5554 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5555 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5556 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5557 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5558 EVT NewVT = V0_LO.getValueType();
5560 SDValue LO = DAG.getUNDEF(NewVT);
5561 SDValue HI = DAG.getUNDEF(NewVT);
5564 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5565 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5566 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5567 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5568 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5570 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5571 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5572 V1_LO->getOpcode() != ISD::UNDEF))
5573 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5575 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5576 V1_HI->getOpcode() != ISD::UNDEF))
5577 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5580 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5583 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5585 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5586 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5587 EVT VT = BV->getValueType(0);
5588 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5589 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5593 unsigned NumElts = VT.getVectorNumElements();
5594 SDValue InVec0 = DAG.getUNDEF(VT);
5595 SDValue InVec1 = DAG.getUNDEF(VT);
5597 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5598 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5600 // Odd-numbered elements in the input build vector are obtained from
5601 // adding two integer/float elements.
5602 // Even-numbered elements in the input build vector are obtained from
5603 // subtracting two integer/float elements.
5604 unsigned ExpectedOpcode = ISD::FSUB;
5605 unsigned NextExpectedOpcode = ISD::FADD;
5606 bool AddFound = false;
5607 bool SubFound = false;
5609 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5610 SDValue Op = BV->getOperand(i);
5612 // Skip 'undef' values.
5613 unsigned Opcode = Op.getOpcode();
5614 if (Opcode == ISD::UNDEF) {
5615 std::swap(ExpectedOpcode, NextExpectedOpcode);
5619 // Early exit if we found an unexpected opcode.
5620 if (Opcode != ExpectedOpcode)
5623 SDValue Op0 = Op.getOperand(0);
5624 SDValue Op1 = Op.getOperand(1);
5626 // Try to match the following pattern:
5627 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5628 // Early exit if we cannot match that sequence.
5629 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5630 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5631 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5632 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5633 Op0.getOperand(1) != Op1.getOperand(1))
5636 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5640 // We found a valid add/sub node. Update the information accordingly.
5646 // Update InVec0 and InVec1.
5647 if (InVec0.getOpcode() == ISD::UNDEF) {
5648 InVec0 = Op0.getOperand(0);
5649 if (InVec0.getValueType() != VT)
5652 if (InVec1.getOpcode() == ISD::UNDEF) {
5653 InVec1 = Op1.getOperand(0);
5654 if (InVec1.getValueType() != VT)
5658 // Make sure that operands in input to each add/sub node always
5659 // come from a same pair of vectors.
5660 if (InVec0 != Op0.getOperand(0)) {
5661 if (ExpectedOpcode == ISD::FSUB)
5664 // FADD is commutable. Try to commute the operands
5665 // and then test again.
5666 std::swap(Op0, Op1);
5667 if (InVec0 != Op0.getOperand(0))
5671 if (InVec1 != Op1.getOperand(0))
5674 // Update the pair of expected opcodes.
5675 std::swap(ExpectedOpcode, NextExpectedOpcode);
5678 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5679 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5680 InVec1.getOpcode() != ISD::UNDEF)
5681 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5686 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5687 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5688 const X86Subtarget *Subtarget,
5689 SelectionDAG &DAG) {
5690 EVT VT = BV->getValueType(0);
5691 unsigned NumElts = VT.getVectorNumElements();
5692 unsigned NumUndefsLO = 0;
5693 unsigned NumUndefsHI = 0;
5694 unsigned Half = NumElts/2;
5696 // Count the number of UNDEF operands in the build_vector in input.
5697 for (unsigned i = 0, e = Half; i != e; ++i)
5698 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5701 for (unsigned i = Half, e = NumElts; i != e; ++i)
5702 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5705 // Early exit if this is either a build_vector of all UNDEFs or all the
5706 // operands but one are UNDEF.
5707 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5711 SDValue InVec0, InVec1;
5712 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5713 // Try to match an SSE3 float HADD/HSUB.
5714 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5715 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5717 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5718 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5719 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5720 // Try to match an SSSE3 integer HADD/HSUB.
5721 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5722 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5724 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5725 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5728 if (!Subtarget->hasAVX())
5731 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5732 // Try to match an AVX horizontal add/sub of packed single/double
5733 // precision floating point values from 256-bit vectors.
5734 SDValue InVec2, InVec3;
5735 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5736 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5737 ((InVec0.getOpcode() == ISD::UNDEF ||
5738 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5739 ((InVec1.getOpcode() == ISD::UNDEF ||
5740 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5741 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5743 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5744 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5745 ((InVec0.getOpcode() == ISD::UNDEF ||
5746 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5747 ((InVec1.getOpcode() == ISD::UNDEF ||
5748 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5749 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5750 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5751 // Try to match an AVX2 horizontal add/sub of signed integers.
5752 SDValue InVec2, InVec3;
5754 bool CanFold = true;
5756 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5757 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5758 ((InVec0.getOpcode() == ISD::UNDEF ||
5759 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5760 ((InVec1.getOpcode() == ISD::UNDEF ||
5761 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5762 X86Opcode = X86ISD::HADD;
5763 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5764 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5765 ((InVec0.getOpcode() == ISD::UNDEF ||
5766 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5767 ((InVec1.getOpcode() == ISD::UNDEF ||
5768 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5769 X86Opcode = X86ISD::HSUB;
5774 // Fold this build_vector into a single horizontal add/sub.
5775 // Do this only if the target has AVX2.
5776 if (Subtarget->hasAVX2())
5777 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5779 // Do not try to expand this build_vector into a pair of horizontal
5780 // add/sub if we can emit a pair of scalar add/sub.
5781 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5784 // Convert this build_vector into a pair of horizontal binop followed by
5786 bool isUndefLO = NumUndefsLO == Half;
5787 bool isUndefHI = NumUndefsHI == Half;
5788 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5789 isUndefLO, isUndefHI);
5793 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5794 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5796 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5797 X86Opcode = X86ISD::HADD;
5798 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5799 X86Opcode = X86ISD::HSUB;
5800 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5801 X86Opcode = X86ISD::FHADD;
5802 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5803 X86Opcode = X86ISD::FHSUB;
5807 // Don't try to expand this build_vector into a pair of horizontal add/sub
5808 // if we can simply emit a pair of scalar add/sub.
5809 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5812 // Convert this build_vector into two horizontal add/sub followed by
5814 bool isUndefLO = NumUndefsLO == Half;
5815 bool isUndefHI = NumUndefsHI == Half;
5816 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5817 isUndefLO, isUndefHI);
5824 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5827 MVT VT = Op.getSimpleValueType();
5828 MVT ExtVT = VT.getVectorElementType();
5829 unsigned NumElems = Op.getNumOperands();
5831 // Generate vectors for predicate vectors.
5832 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5833 return LowerBUILD_VECTORvXi1(Op, DAG);
5835 // Vectors containing all zeros can be matched by pxor and xorps later
5836 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5837 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5838 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5839 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5842 return getZeroVector(VT, Subtarget, DAG, dl);
5845 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5846 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5847 // vpcmpeqd on 256-bit vectors.
5848 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5849 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5852 if (!VT.is512BitVector())
5853 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5856 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5857 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5859 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5860 return HorizontalOp;
5861 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5864 unsigned EVTBits = ExtVT.getSizeInBits();
5866 unsigned NumZero = 0;
5867 unsigned NumNonZero = 0;
5868 unsigned NonZeros = 0;
5869 bool IsAllConstants = true;
5870 SmallSet<SDValue, 8> Values;
5871 for (unsigned i = 0; i < NumElems; ++i) {
5872 SDValue Elt = Op.getOperand(i);
5873 if (Elt.getOpcode() == ISD::UNDEF)
5876 if (Elt.getOpcode() != ISD::Constant &&
5877 Elt.getOpcode() != ISD::ConstantFP)
5878 IsAllConstants = false;
5879 if (X86::isZeroNode(Elt))
5882 NonZeros |= (1 << i);
5887 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5888 if (NumNonZero == 0)
5889 return DAG.getUNDEF(VT);
5891 // Special case for single non-zero, non-undef, element.
5892 if (NumNonZero == 1) {
5893 unsigned Idx = countTrailingZeros(NonZeros);
5894 SDValue Item = Op.getOperand(Idx);
5896 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5897 // the value are obviously zero, truncate the value to i32 and do the
5898 // insertion that way. Only do this if the value is non-constant or if the
5899 // value is a constant being inserted into element 0. It is cheaper to do
5900 // a constant pool load than it is to do a movd + shuffle.
5901 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5902 (!IsAllConstants || Idx == 0)) {
5903 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5905 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5906 EVT VecVT = MVT::v4i32;
5908 // Truncate the value (which may itself be a constant) to i32, and
5909 // convert it to a vector with movd (S2V+shuffle to zero extend).
5910 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5912 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5913 Item, Idx * 2, true, Subtarget, DAG));
5917 // If we have a constant or non-constant insertion into the low element of
5918 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5919 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5920 // depending on what the source datatype is.
5923 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5925 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5926 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5927 if (VT.is512BitVector()) {
5928 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5929 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5930 Item, DAG.getIntPtrConstant(0, dl));
5932 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5933 "Expected an SSE value type!");
5934 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5935 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5936 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5939 // We can't directly insert an i8 or i16 into a vector, so zero extend
5941 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5942 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5943 if (VT.is256BitVector()) {
5944 if (Subtarget->hasAVX()) {
5945 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5946 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5948 // Without AVX, we need to extend to a 128-bit vector and then
5949 // insert into the 256-bit vector.
5950 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5951 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5952 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5955 assert(VT.is128BitVector() && "Expected an SSE value type!");
5956 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5957 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5959 return DAG.getBitcast(VT, Item);
5963 // Is it a vector logical left shift?
5964 if (NumElems == 2 && Idx == 1 &&
5965 X86::isZeroNode(Op.getOperand(0)) &&
5966 !X86::isZeroNode(Op.getOperand(1))) {
5967 unsigned NumBits = VT.getSizeInBits();
5968 return getVShift(true, VT,
5969 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5970 VT, Op.getOperand(1)),
5971 NumBits/2, DAG, *this, dl);
5974 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5977 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5978 // is a non-constant being inserted into an element other than the low one,
5979 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5980 // movd/movss) to move this into the low element, then shuffle it into
5982 if (EVTBits == 32) {
5983 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5984 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5988 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5989 if (Values.size() == 1) {
5990 if (EVTBits == 32) {
5991 // Instead of a shuffle like this:
5992 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5993 // Check if it's possible to issue this instead.
5994 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5995 unsigned Idx = countTrailingZeros(NonZeros);
5996 SDValue Item = Op.getOperand(Idx);
5997 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5998 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6003 // A vector full of immediates; various special cases are already
6004 // handled, so this is best done with a single constant-pool load.
6008 // For AVX-length vectors, see if we can use a vector load to get all of the
6009 // elements, otherwise build the individual 128-bit pieces and use
6010 // shuffles to put them in place.
6011 if (VT.is256BitVector() || VT.is512BitVector()) {
6012 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6014 // Check for a build vector of consecutive loads.
6015 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6018 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6020 // Build both the lower and upper subvector.
6021 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6022 makeArrayRef(&V[0], NumElems/2));
6023 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6024 makeArrayRef(&V[NumElems / 2], NumElems/2));
6026 // Recreate the wider vector with the lower and upper part.
6027 if (VT.is256BitVector())
6028 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6029 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6032 // Let legalizer expand 2-wide build_vectors.
6033 if (EVTBits == 64) {
6034 if (NumNonZero == 1) {
6035 // One half is zero or undef.
6036 unsigned Idx = countTrailingZeros(NonZeros);
6037 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6038 Op.getOperand(Idx));
6039 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6044 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6045 if (EVTBits == 8 && NumElems == 16)
6046 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6050 if (EVTBits == 16 && NumElems == 8)
6051 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6055 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6056 if (EVTBits == 32 && NumElems == 4)
6057 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6060 // If element VT is == 32 bits, turn it into a number of shuffles.
6061 SmallVector<SDValue, 8> V(NumElems);
6062 if (NumElems == 4 && NumZero > 0) {
6063 for (unsigned i = 0; i < 4; ++i) {
6064 bool isZero = !(NonZeros & (1 << i));
6066 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6068 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6071 for (unsigned i = 0; i < 2; ++i) {
6072 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6075 V[i] = V[i*2]; // Must be a zero vector.
6078 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6081 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6084 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6089 bool Reverse1 = (NonZeros & 0x3) == 2;
6090 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6094 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6095 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6097 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6100 if (Values.size() > 1 && VT.is128BitVector()) {
6101 // Check for a build vector of consecutive loads.
6102 for (unsigned i = 0; i < NumElems; ++i)
6103 V[i] = Op.getOperand(i);
6105 // Check for elements which are consecutive loads.
6106 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6109 // Check for a build vector from mostly shuffle plus few inserting.
6110 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6113 // For SSE 4.1, use insertps to put the high elements into the low element.
6114 if (Subtarget->hasSSE41()) {
6116 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6117 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6119 Result = DAG.getUNDEF(VT);
6121 for (unsigned i = 1; i < NumElems; ++i) {
6122 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6123 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6124 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6129 // Otherwise, expand into a number of unpckl*, start by extending each of
6130 // our (non-undef) elements to the full vector width with the element in the
6131 // bottom slot of the vector (which generates no code for SSE).
6132 for (unsigned i = 0; i < NumElems; ++i) {
6133 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6134 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6136 V[i] = DAG.getUNDEF(VT);
6139 // Next, we iteratively mix elements, e.g. for v4f32:
6140 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6141 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6142 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6143 unsigned EltStride = NumElems >> 1;
6144 while (EltStride != 0) {
6145 for (unsigned i = 0; i < EltStride; ++i) {
6146 // If V[i+EltStride] is undef and this is the first round of mixing,
6147 // then it is safe to just drop this shuffle: V[i] is already in the
6148 // right place, the one element (since it's the first round) being
6149 // inserted as undef can be dropped. This isn't safe for successive
6150 // rounds because they will permute elements within both vectors.
6151 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6152 EltStride == NumElems/2)
6155 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6164 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6165 // to create 256-bit vectors from two other 128-bit ones.
6166 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6168 MVT ResVT = Op.getSimpleValueType();
6170 assert((ResVT.is256BitVector() ||
6171 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6173 SDValue V1 = Op.getOperand(0);
6174 SDValue V2 = Op.getOperand(1);
6175 unsigned NumElems = ResVT.getVectorNumElements();
6176 if (ResVT.is256BitVector())
6177 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6179 if (Op.getNumOperands() == 4) {
6180 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6181 ResVT.getVectorNumElements()/2);
6182 SDValue V3 = Op.getOperand(2);
6183 SDValue V4 = Op.getOperand(3);
6184 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6185 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6187 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6190 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6191 const X86Subtarget *Subtarget,
6192 SelectionDAG & DAG) {
6194 MVT ResVT = Op.getSimpleValueType();
6195 unsigned NumOfOperands = Op.getNumOperands();
6197 assert(isPowerOf2_32(NumOfOperands) &&
6198 "Unexpected number of operands in CONCAT_VECTORS");
6200 if (NumOfOperands > 2) {
6201 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6202 ResVT.getVectorNumElements()/2);
6203 SmallVector<SDValue, 2> Ops;
6204 for (unsigned i = 0; i < NumOfOperands/2; i++)
6205 Ops.push_back(Op.getOperand(i));
6206 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6208 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6209 Ops.push_back(Op.getOperand(i));
6210 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6211 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6214 SDValue V1 = Op.getOperand(0);
6215 SDValue V2 = Op.getOperand(1);
6216 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6217 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6219 if (IsZeroV1 && IsZeroV2)
6220 return getZeroVector(ResVT, Subtarget, DAG, dl);
6222 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6223 SDValue Undef = DAG.getUNDEF(ResVT);
6224 unsigned NumElems = ResVT.getVectorNumElements();
6225 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6227 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6228 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6232 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6233 // Zero the upper bits of V1
6234 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6235 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6238 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6241 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6242 const X86Subtarget *Subtarget,
6243 SelectionDAG &DAG) {
6244 MVT VT = Op.getSimpleValueType();
6245 if (VT.getVectorElementType() == MVT::i1)
6246 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6248 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6249 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6250 Op.getNumOperands() == 4)));
6252 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6253 // from two other 128-bit ones.
6255 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6256 return LowerAVXCONCAT_VECTORS(Op, DAG);
6260 //===----------------------------------------------------------------------===//
6261 // Vector shuffle lowering
6263 // This is an experimental code path for lowering vector shuffles on x86. It is
6264 // designed to handle arbitrary vector shuffles and blends, gracefully
6265 // degrading performance as necessary. It works hard to recognize idiomatic
6266 // shuffles and lower them to optimal instruction patterns without leaving
6267 // a framework that allows reasonably efficient handling of all vector shuffle
6269 //===----------------------------------------------------------------------===//
6271 /// \brief Tiny helper function to identify a no-op mask.
6273 /// This is a somewhat boring predicate function. It checks whether the mask
6274 /// array input, which is assumed to be a single-input shuffle mask of the kind
6275 /// used by the X86 shuffle instructions (not a fully general
6276 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6277 /// in-place shuffle are 'no-op's.
6278 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6279 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6280 if (Mask[i] != -1 && Mask[i] != i)
6285 /// \brief Helper function to classify a mask as a single-input mask.
6287 /// This isn't a generic single-input test because in the vector shuffle
6288 /// lowering we canonicalize single inputs to be the first input operand. This
6289 /// means we can more quickly test for a single input by only checking whether
6290 /// an input from the second operand exists. We also assume that the size of
6291 /// mask corresponds to the size of the input vectors which isn't true in the
6292 /// fully general case.
6293 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6295 if (M >= (int)Mask.size())
6300 /// \brief Test whether there are elements crossing 128-bit lanes in this
6303 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6304 /// and we routinely test for these.
6305 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6306 int LaneSize = 128 / VT.getScalarSizeInBits();
6307 int Size = Mask.size();
6308 for (int i = 0; i < Size; ++i)
6309 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6314 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6316 /// This checks a shuffle mask to see if it is performing the same
6317 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6318 /// that it is also not lane-crossing. It may however involve a blend from the
6319 /// same lane of a second vector.
6321 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6322 /// non-trivial to compute in the face of undef lanes. The representation is
6323 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6324 /// entries from both V1 and V2 inputs to the wider mask.
6326 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6327 SmallVectorImpl<int> &RepeatedMask) {
6328 int LaneSize = 128 / VT.getScalarSizeInBits();
6329 RepeatedMask.resize(LaneSize, -1);
6330 int Size = Mask.size();
6331 for (int i = 0; i < Size; ++i) {
6334 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6335 // This entry crosses lanes, so there is no way to model this shuffle.
6338 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6339 if (RepeatedMask[i % LaneSize] == -1)
6340 // This is the first non-undef entry in this slot of a 128-bit lane.
6341 RepeatedMask[i % LaneSize] =
6342 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6343 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6344 // Found a mismatch with the repeated mask.
6350 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6353 /// This is a fast way to test a shuffle mask against a fixed pattern:
6355 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6357 /// It returns true if the mask is exactly as wide as the argument list, and
6358 /// each element of the mask is either -1 (signifying undef) or the value given
6359 /// in the argument.
6360 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6361 ArrayRef<int> ExpectedMask) {
6362 if (Mask.size() != ExpectedMask.size())
6365 int Size = Mask.size();
6367 // If the values are build vectors, we can look through them to find
6368 // equivalent inputs that make the shuffles equivalent.
6369 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6370 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6372 for (int i = 0; i < Size; ++i)
6373 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6374 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6375 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6376 if (!MaskBV || !ExpectedBV ||
6377 MaskBV->getOperand(Mask[i] % Size) !=
6378 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6385 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6387 /// This helper function produces an 8-bit shuffle immediate corresponding to
6388 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6389 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6392 /// NB: We rely heavily on "undef" masks preserving the input lane.
6393 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6394 SelectionDAG &DAG) {
6395 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6396 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6397 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6398 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6399 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6402 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6403 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6404 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6405 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6406 return DAG.getConstant(Imm, DL, MVT::i8);
6409 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6411 /// This is used as a fallback approach when first class blend instructions are
6412 /// unavailable. Currently it is only suitable for integer vectors, but could
6413 /// be generalized for floating point vectors if desirable.
6414 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6415 SDValue V2, ArrayRef<int> Mask,
6416 SelectionDAG &DAG) {
6417 assert(VT.isInteger() && "Only supports integer vector types!");
6418 MVT EltVT = VT.getScalarType();
6419 int NumEltBits = EltVT.getSizeInBits();
6420 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6421 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6423 SmallVector<SDValue, 16> MaskOps;
6424 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6425 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6426 return SDValue(); // Shuffled input!
6427 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6430 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6431 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6432 // We have to cast V2 around.
6433 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6434 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6435 DAG.getBitcast(MaskVT, V1Mask),
6436 DAG.getBitcast(MaskVT, V2)));
6437 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6440 /// \brief Try to emit a blend instruction for a shuffle.
6442 /// This doesn't do any checks for the availability of instructions for blending
6443 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6444 /// be matched in the backend with the type given. What it does check for is
6445 /// that the shuffle mask is in fact a blend.
6446 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6447 SDValue V2, ArrayRef<int> Mask,
6448 const X86Subtarget *Subtarget,
6449 SelectionDAG &DAG) {
6450 unsigned BlendMask = 0;
6451 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6452 if (Mask[i] >= Size) {
6453 if (Mask[i] != i + Size)
6454 return SDValue(); // Shuffled V2 input!
6455 BlendMask |= 1u << i;
6458 if (Mask[i] >= 0 && Mask[i] != i)
6459 return SDValue(); // Shuffled V1 input!
6461 switch (VT.SimpleTy) {
6466 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6467 DAG.getConstant(BlendMask, DL, MVT::i8));
6471 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6475 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6476 // that instruction.
6477 if (Subtarget->hasAVX2()) {
6478 // Scale the blend by the number of 32-bit dwords per element.
6479 int Scale = VT.getScalarSizeInBits() / 32;
6481 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6482 if (Mask[i] >= Size)
6483 for (int j = 0; j < Scale; ++j)
6484 BlendMask |= 1u << (i * Scale + j);
6486 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6487 V1 = DAG.getBitcast(BlendVT, V1);
6488 V2 = DAG.getBitcast(BlendVT, V2);
6489 return DAG.getBitcast(
6490 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6491 DAG.getConstant(BlendMask, DL, MVT::i8)));
6495 // For integer shuffles we need to expand the mask and cast the inputs to
6496 // v8i16s prior to blending.
6497 int Scale = 8 / VT.getVectorNumElements();
6499 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6500 if (Mask[i] >= Size)
6501 for (int j = 0; j < Scale; ++j)
6502 BlendMask |= 1u << (i * Scale + j);
6504 V1 = DAG.getBitcast(MVT::v8i16, V1);
6505 V2 = DAG.getBitcast(MVT::v8i16, V2);
6506 return DAG.getBitcast(VT,
6507 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6508 DAG.getConstant(BlendMask, DL, MVT::i8)));
6512 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6513 SmallVector<int, 8> RepeatedMask;
6514 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6515 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6516 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6518 for (int i = 0; i < 8; ++i)
6519 if (RepeatedMask[i] >= 16)
6520 BlendMask |= 1u << i;
6521 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6522 DAG.getConstant(BlendMask, DL, MVT::i8));
6528 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6529 "256-bit byte-blends require AVX2 support!");
6531 // Scale the blend by the number of bytes per element.
6532 int Scale = VT.getScalarSizeInBits() / 8;
6534 // This form of blend is always done on bytes. Compute the byte vector
6536 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6538 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6539 // mix of LLVM's code generator and the x86 backend. We tell the code
6540 // generator that boolean values in the elements of an x86 vector register
6541 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6542 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6543 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6544 // of the element (the remaining are ignored) and 0 in that high bit would
6545 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6546 // the LLVM model for boolean values in vector elements gets the relevant
6547 // bit set, it is set backwards and over constrained relative to x86's
6549 SmallVector<SDValue, 32> VSELECTMask;
6550 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6551 for (int j = 0; j < Scale; ++j)
6552 VSELECTMask.push_back(
6553 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6554 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6557 V1 = DAG.getBitcast(BlendVT, V1);
6558 V2 = DAG.getBitcast(BlendVT, V2);
6559 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6560 DAG.getNode(ISD::BUILD_VECTOR, DL,
6561 BlendVT, VSELECTMask),
6566 llvm_unreachable("Not a supported integer vector type!");
6570 /// \brief Try to lower as a blend of elements from two inputs followed by
6571 /// a single-input permutation.
6573 /// This matches the pattern where we can blend elements from two inputs and
6574 /// then reduce the shuffle to a single-input permutation.
6575 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6578 SelectionDAG &DAG) {
6579 // We build up the blend mask while checking whether a blend is a viable way
6580 // to reduce the shuffle.
6581 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6582 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6584 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6588 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6590 if (BlendMask[Mask[i] % Size] == -1)
6591 BlendMask[Mask[i] % Size] = Mask[i];
6592 else if (BlendMask[Mask[i] % Size] != Mask[i])
6593 return SDValue(); // Can't blend in the needed input!
6595 PermuteMask[i] = Mask[i] % Size;
6598 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6599 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6602 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6603 /// blends and permutes.
6605 /// This matches the extremely common pattern for handling combined
6606 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6607 /// operations. It will try to pick the best arrangement of shuffles and
6609 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6613 SelectionDAG &DAG) {
6614 // Shuffle the input elements into the desired positions in V1 and V2 and
6615 // blend them together.
6616 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6617 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6618 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6619 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6620 if (Mask[i] >= 0 && Mask[i] < Size) {
6621 V1Mask[i] = Mask[i];
6623 } else if (Mask[i] >= Size) {
6624 V2Mask[i] = Mask[i] - Size;
6625 BlendMask[i] = i + Size;
6628 // Try to lower with the simpler initial blend strategy unless one of the
6629 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6630 // shuffle may be able to fold with a load or other benefit. However, when
6631 // we'll have to do 2x as many shuffles in order to achieve this, blending
6632 // first is a better strategy.
6633 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6634 if (SDValue BlendPerm =
6635 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6638 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6639 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6640 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6643 /// \brief Try to lower a vector shuffle as a byte rotation.
6645 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6646 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6647 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6648 /// try to generically lower a vector shuffle through such an pattern. It
6649 /// does not check for the profitability of lowering either as PALIGNR or
6650 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6651 /// This matches shuffle vectors that look like:
6653 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6655 /// Essentially it concatenates V1 and V2, shifts right by some number of
6656 /// elements, and takes the low elements as the result. Note that while this is
6657 /// specified as a *right shift* because x86 is little-endian, it is a *left
6658 /// rotate* of the vector lanes.
6659 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6662 const X86Subtarget *Subtarget,
6663 SelectionDAG &DAG) {
6664 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6666 int NumElts = Mask.size();
6667 int NumLanes = VT.getSizeInBits() / 128;
6668 int NumLaneElts = NumElts / NumLanes;
6670 // We need to detect various ways of spelling a rotation:
6671 // [11, 12, 13, 14, 15, 0, 1, 2]
6672 // [-1, 12, 13, 14, -1, -1, 1, -1]
6673 // [-1, -1, -1, -1, -1, -1, 1, 2]
6674 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6675 // [-1, 4, 5, 6, -1, -1, 9, -1]
6676 // [-1, 4, 5, 6, -1, -1, -1, -1]
6679 for (int l = 0; l < NumElts; l += NumLaneElts) {
6680 for (int i = 0; i < NumLaneElts; ++i) {
6681 if (Mask[l + i] == -1)
6683 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6685 // Get the mod-Size index and lane correct it.
6686 int LaneIdx = (Mask[l + i] % NumElts) - l;
6687 // Make sure it was in this lane.
6688 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6691 // Determine where a rotated vector would have started.
6692 int StartIdx = i - LaneIdx;
6694 // The identity rotation isn't interesting, stop.
6697 // If we found the tail of a vector the rotation must be the missing
6698 // front. If we found the head of a vector, it must be how much of the
6700 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6703 Rotation = CandidateRotation;
6704 else if (Rotation != CandidateRotation)
6705 // The rotations don't match, so we can't match this mask.
6708 // Compute which value this mask is pointing at.
6709 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6711 // Compute which of the two target values this index should be assigned
6712 // to. This reflects whether the high elements are remaining or the low
6713 // elements are remaining.
6714 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6716 // Either set up this value if we've not encountered it before, or check
6717 // that it remains consistent.
6720 else if (TargetV != MaskV)
6721 // This may be a rotation, but it pulls from the inputs in some
6722 // unsupported interleaving.
6727 // Check that we successfully analyzed the mask, and normalize the results.
6728 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6729 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6735 // The actual rotate instruction rotates bytes, so we need to scale the
6736 // rotation based on how many bytes are in the vector lane.
6737 int Scale = 16 / NumLaneElts;
6739 // SSSE3 targets can use the palignr instruction.
6740 if (Subtarget->hasSSSE3()) {
6741 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6742 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6743 Lo = DAG.getBitcast(AlignVT, Lo);
6744 Hi = DAG.getBitcast(AlignVT, Hi);
6746 return DAG.getBitcast(
6747 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6748 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6751 assert(VT.getSizeInBits() == 128 &&
6752 "Rotate-based lowering only supports 128-bit lowering!");
6753 assert(Mask.size() <= 16 &&
6754 "Can shuffle at most 16 bytes in a 128-bit vector!");
6756 // Default SSE2 implementation
6757 int LoByteShift = 16 - Rotation * Scale;
6758 int HiByteShift = Rotation * Scale;
6760 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6761 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6762 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6764 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6765 DAG.getConstant(LoByteShift, DL, MVT::i8));
6766 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6767 DAG.getConstant(HiByteShift, DL, MVT::i8));
6768 return DAG.getBitcast(VT,
6769 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6772 /// \brief Compute whether each element of a shuffle is zeroable.
6774 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6775 /// Either it is an undef element in the shuffle mask, the element of the input
6776 /// referenced is undef, or the element of the input referenced is known to be
6777 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6778 /// as many lanes with this technique as possible to simplify the remaining
6780 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6781 SDValue V1, SDValue V2) {
6782 SmallBitVector Zeroable(Mask.size(), false);
6784 while (V1.getOpcode() == ISD::BITCAST)
6785 V1 = V1->getOperand(0);
6786 while (V2.getOpcode() == ISD::BITCAST)
6787 V2 = V2->getOperand(0);
6789 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6790 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6792 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6794 // Handle the easy cases.
6795 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6800 // If this is an index into a build_vector node (which has the same number
6801 // of elements), dig out the input value and use it.
6802 SDValue V = M < Size ? V1 : V2;
6803 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6806 SDValue Input = V.getOperand(M % Size);
6807 // The UNDEF opcode check really should be dead code here, but not quite
6808 // worth asserting on (it isn't invalid, just unexpected).
6809 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6816 /// \brief Try to emit a bitmask instruction for a shuffle.
6818 /// This handles cases where we can model a blend exactly as a bitmask due to
6819 /// one of the inputs being zeroable.
6820 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6821 SDValue V2, ArrayRef<int> Mask,
6822 SelectionDAG &DAG) {
6823 MVT EltVT = VT.getScalarType();
6824 int NumEltBits = EltVT.getSizeInBits();
6825 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6826 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6827 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6829 if (EltVT.isFloatingPoint()) {
6830 Zero = DAG.getBitcast(EltVT, Zero);
6831 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6833 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6834 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6836 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6839 if (Mask[i] % Size != i)
6840 return SDValue(); // Not a blend.
6842 V = Mask[i] < Size ? V1 : V2;
6843 else if (V != (Mask[i] < Size ? V1 : V2))
6844 return SDValue(); // Can only let one input through the mask.
6846 VMaskOps[i] = AllOnes;
6849 return SDValue(); // No non-zeroable elements!
6851 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6852 V = DAG.getNode(VT.isFloatingPoint()
6853 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6858 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6860 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6861 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6862 /// matches elements from one of the input vectors shuffled to the left or
6863 /// right with zeroable elements 'shifted in'. It handles both the strictly
6864 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6867 /// PSHL : (little-endian) left bit shift.
6868 /// [ zz, 0, zz, 2 ]
6869 /// [ -1, 4, zz, -1 ]
6870 /// PSRL : (little-endian) right bit shift.
6872 /// [ -1, -1, 7, zz]
6873 /// PSLLDQ : (little-endian) left byte shift
6874 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6875 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6876 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6877 /// PSRLDQ : (little-endian) right byte shift
6878 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6879 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6880 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6881 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6882 SDValue V2, ArrayRef<int> Mask,
6883 SelectionDAG &DAG) {
6884 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6886 int Size = Mask.size();
6887 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6889 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6890 for (int i = 0; i < Size; i += Scale)
6891 for (int j = 0; j < Shift; ++j)
6892 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6898 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6899 for (int i = 0; i != Size; i += Scale) {
6900 unsigned Pos = Left ? i + Shift : i;
6901 unsigned Low = Left ? i : i + Shift;
6902 unsigned Len = Scale - Shift;
6903 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6904 Low + (V == V1 ? 0 : Size)))
6908 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6909 bool ByteShift = ShiftEltBits > 64;
6910 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6911 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6912 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6914 // Normalize the scale for byte shifts to still produce an i64 element
6916 Scale = ByteShift ? Scale / 2 : Scale;
6918 // We need to round trip through the appropriate type for the shift.
6919 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6920 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6921 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6922 "Illegal integer vector type");
6923 V = DAG.getBitcast(ShiftVT, V);
6925 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6926 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6927 return DAG.getBitcast(VT, V);
6930 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6931 // keep doubling the size of the integer elements up to that. We can
6932 // then shift the elements of the integer vector by whole multiples of
6933 // their width within the elements of the larger integer vector. Test each
6934 // multiple to see if we can find a match with the moved element indices
6935 // and that the shifted in elements are all zeroable.
6936 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6937 for (int Shift = 1; Shift != Scale; ++Shift)
6938 for (bool Left : {true, false})
6939 if (CheckZeros(Shift, Scale, Left))
6940 for (SDValue V : {V1, V2})
6941 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6948 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
6949 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
6950 SDValue V2, ArrayRef<int> Mask,
6951 SelectionDAG &DAG) {
6952 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6953 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
6955 int Size = Mask.size();
6956 int HalfSize = Size / 2;
6957 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6959 // Upper half must be undefined.
6960 if (!isUndefInRange(Mask, HalfSize, HalfSize))
6963 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
6964 // Remainder of lower half result is zero and upper half is all undef.
6965 auto LowerAsEXTRQ = [&]() {
6966 // Determine the extraction length from the part of the
6967 // lower half that isn't zeroable.
6969 for (; Len >= 0; --Len)
6970 if (!Zeroable[Len - 1])
6972 assert(Len > 0 && "Zeroable shuffle mask");
6974 // Attempt to match first Len sequential elements from the lower half.
6977 for (int i = 0; i != Len; ++i) {
6981 SDValue &V = (M < Size ? V1 : V2);
6984 // All mask elements must be in the lower half.
6988 if (Idx < 0 || (Src == V && Idx == (M - i))) {
6999 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7000 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7001 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7002 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7003 DAG.getConstant(BitLen, DL, MVT::i8),
7004 DAG.getConstant(BitIdx, DL, MVT::i8));
7007 if (SDValue ExtrQ = LowerAsEXTRQ())
7010 // INSERTQ: Extract lowest Len elements from lower half of second source and
7011 // insert over first source, starting at Idx.
7012 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7013 auto LowerAsInsertQ = [&]() {
7014 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7017 // Attempt to match first source from mask before insertion point.
7018 if (isUndefInRange(Mask, 0, Idx)) {
7020 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7022 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7028 // Extend the extraction length looking to match both the insertion of
7029 // the second source and the remaining elements of the first.
7030 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7035 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7037 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7043 // Match the remaining elements of the lower half.
7044 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7046 } else if ((!Base || (Base == V1)) &&
7047 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7049 } else if ((!Base || (Base == V2)) &&
7050 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7057 // We may not have a base (first source) - this can safely be undefined.
7059 Base = DAG.getUNDEF(VT);
7061 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7062 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7063 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7064 DAG.getConstant(BitLen, DL, MVT::i8),
7065 DAG.getConstant(BitIdx, DL, MVT::i8));
7072 if (SDValue InsertQ = LowerAsInsertQ())
7078 /// \brief Lower a vector shuffle as a zero or any extension.
7080 /// Given a specific number of elements, element bit width, and extension
7081 /// stride, produce either a zero or any extension based on the available
7082 /// features of the subtarget.
7083 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7084 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
7085 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7086 assert(Scale > 1 && "Need a scale to extend.");
7087 int NumElements = VT.getVectorNumElements();
7088 int EltBits = VT.getScalarSizeInBits();
7089 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7090 "Only 8, 16, and 32 bit elements can be extended.");
7091 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7093 // Found a valid zext mask! Try various lowering strategies based on the
7094 // input type and available ISA extensions.
7095 if (Subtarget->hasSSE41()) {
7096 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7097 NumElements / Scale);
7098 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7101 // For any extends we can cheat for larger element sizes and use shuffle
7102 // instructions that can fold with a load and/or copy.
7103 if (AnyExt && EltBits == 32) {
7104 int PSHUFDMask[4] = {0, -1, 1, -1};
7105 return DAG.getBitcast(
7106 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7107 DAG.getBitcast(MVT::v4i32, InputV),
7108 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7110 if (AnyExt && EltBits == 16 && Scale > 2) {
7111 int PSHUFDMask[4] = {0, -1, 0, -1};
7112 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7113 DAG.getBitcast(MVT::v4i32, InputV),
7114 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7115 int PSHUFHWMask[4] = {1, -1, -1, -1};
7116 return DAG.getBitcast(
7117 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7118 DAG.getBitcast(MVT::v8i16, InputV),
7119 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
7122 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7124 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7125 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7126 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7128 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7129 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7130 DAG.getConstant(EltBits, DL, MVT::i8),
7131 DAG.getConstant(0, DL, MVT::i8)));
7132 if (isUndefInRange(Mask, NumElements/2, NumElements/2))
7133 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7136 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7137 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7138 DAG.getConstant(EltBits, DL, MVT::i8),
7139 DAG.getConstant(EltBits, DL, MVT::i8)));
7140 return DAG.getNode(ISD::BITCAST, DL, VT,
7141 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7144 // If this would require more than 2 unpack instructions to expand, use
7145 // pshufb when available. We can only use more than 2 unpack instructions
7146 // when zero extending i8 elements which also makes it easier to use pshufb.
7147 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7148 assert(NumElements == 16 && "Unexpected byte vector width!");
7149 SDValue PSHUFBMask[16];
7150 for (int i = 0; i < 16; ++i)
7152 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
7153 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7154 return DAG.getBitcast(VT,
7155 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7156 DAG.getNode(ISD::BUILD_VECTOR, DL,
7157 MVT::v16i8, PSHUFBMask)));
7160 // Otherwise emit a sequence of unpacks.
7162 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7163 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7164 : getZeroVector(InputVT, Subtarget, DAG, DL);
7165 InputV = DAG.getBitcast(InputVT, InputV);
7166 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7170 } while (Scale > 1);
7171 return DAG.getBitcast(VT, InputV);
7174 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7176 /// This routine will try to do everything in its power to cleverly lower
7177 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7178 /// check for the profitability of this lowering, it tries to aggressively
7179 /// match this pattern. It will use all of the micro-architectural details it
7180 /// can to emit an efficient lowering. It handles both blends with all-zero
7181 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7182 /// masking out later).
7184 /// The reason we have dedicated lowering for zext-style shuffles is that they
7185 /// are both incredibly common and often quite performance sensitive.
7186 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7187 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7188 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7189 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7191 int Bits = VT.getSizeInBits();
7192 int NumElements = VT.getVectorNumElements();
7193 assert(VT.getScalarSizeInBits() <= 32 &&
7194 "Exceeds 32-bit integer zero extension limit");
7195 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7197 // Define a helper function to check a particular ext-scale and lower to it if
7199 auto Lower = [&](int Scale) -> SDValue {
7202 for (int i = 0; i < NumElements; ++i) {
7204 continue; // Valid anywhere but doesn't tell us anything.
7205 if (i % Scale != 0) {
7206 // Each of the extended elements need to be zeroable.
7210 // We no longer are in the anyext case.
7215 // Each of the base elements needs to be consecutive indices into the
7216 // same input vector.
7217 SDValue V = Mask[i] < NumElements ? V1 : V2;
7220 else if (InputV != V)
7221 return SDValue(); // Flip-flopping inputs.
7223 if (Mask[i] % NumElements != i / Scale)
7224 return SDValue(); // Non-consecutive strided elements.
7227 // If we fail to find an input, we have a zero-shuffle which should always
7228 // have already been handled.
7229 // FIXME: Maybe handle this here in case during blending we end up with one?
7233 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7234 DL, VT, Scale, AnyExt, InputV, Mask, Subtarget, DAG);
7237 // The widest scale possible for extending is to a 64-bit integer.
7238 assert(Bits % 64 == 0 &&
7239 "The number of bits in a vector must be divisible by 64 on x86!");
7240 int NumExtElements = Bits / 64;
7242 // Each iteration, try extending the elements half as much, but into twice as
7244 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7245 assert(NumElements % NumExtElements == 0 &&
7246 "The input vector size must be divisible by the extended size.");
7247 if (SDValue V = Lower(NumElements / NumExtElements))
7251 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7255 // Returns one of the source operands if the shuffle can be reduced to a
7256 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7257 auto CanZExtLowHalf = [&]() {
7258 for (int i = NumElements / 2; i != NumElements; ++i)
7261 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7263 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7268 if (SDValue V = CanZExtLowHalf()) {
7269 V = DAG.getBitcast(MVT::v2i64, V);
7270 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7271 return DAG.getBitcast(VT, V);
7274 // No viable ext lowering found.
7278 /// \brief Try to get a scalar value for a specific element of a vector.
7280 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7281 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7282 SelectionDAG &DAG) {
7283 MVT VT = V.getSimpleValueType();
7284 MVT EltVT = VT.getVectorElementType();
7285 while (V.getOpcode() == ISD::BITCAST)
7286 V = V.getOperand(0);
7287 // If the bitcasts shift the element size, we can't extract an equivalent
7289 MVT NewVT = V.getSimpleValueType();
7290 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7293 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7294 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7295 // Ensure the scalar operand is the same size as the destination.
7296 // FIXME: Add support for scalar truncation where possible.
7297 SDValue S = V.getOperand(Idx);
7298 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7299 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7305 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7307 /// This is particularly important because the set of instructions varies
7308 /// significantly based on whether the operand is a load or not.
7309 static bool isShuffleFoldableLoad(SDValue V) {
7310 while (V.getOpcode() == ISD::BITCAST)
7311 V = V.getOperand(0);
7313 return ISD::isNON_EXTLoad(V.getNode());
7316 /// \brief Try to lower insertion of a single element into a zero vector.
7318 /// This is a common pattern that we have especially efficient patterns to lower
7319 /// across all subtarget feature sets.
7320 static SDValue lowerVectorShuffleAsElementInsertion(
7321 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7322 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7323 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7325 MVT EltVT = VT.getVectorElementType();
7327 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7328 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7330 bool IsV1Zeroable = true;
7331 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7332 if (i != V2Index && !Zeroable[i]) {
7333 IsV1Zeroable = false;
7337 // Check for a single input from a SCALAR_TO_VECTOR node.
7338 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7339 // all the smarts here sunk into that routine. However, the current
7340 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7341 // vector shuffle lowering is dead.
7342 if (SDValue V2S = getScalarValueForVectorElement(
7343 V2, Mask[V2Index] - Mask.size(), DAG)) {
7344 // We need to zext the scalar if it is smaller than an i32.
7345 V2S = DAG.getBitcast(EltVT, V2S);
7346 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7347 // Using zext to expand a narrow element won't work for non-zero
7352 // Zero-extend directly to i32.
7354 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7356 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7357 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7358 EltVT == MVT::i16) {
7359 // Either not inserting from the low element of the input or the input
7360 // element size is too small to use VZEXT_MOVL to clear the high bits.
7364 if (!IsV1Zeroable) {
7365 // If V1 can't be treated as a zero vector we have fewer options to lower
7366 // this. We can't support integer vectors or non-zero targets cheaply, and
7367 // the V1 elements can't be permuted in any way.
7368 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7369 if (!VT.isFloatingPoint() || V2Index != 0)
7371 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7372 V1Mask[V2Index] = -1;
7373 if (!isNoopShuffleMask(V1Mask))
7375 // This is essentially a special case blend operation, but if we have
7376 // general purpose blend operations, they are always faster. Bail and let
7377 // the rest of the lowering handle these as blends.
7378 if (Subtarget->hasSSE41())
7381 // Otherwise, use MOVSD or MOVSS.
7382 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7383 "Only two types of floating point element types to handle!");
7384 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7388 // This lowering only works for the low element with floating point vectors.
7389 if (VT.isFloatingPoint() && V2Index != 0)
7392 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7394 V2 = DAG.getBitcast(VT, V2);
7397 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7398 // the desired position. Otherwise it is more efficient to do a vector
7399 // shift left. We know that we can do a vector shift left because all
7400 // the inputs are zero.
7401 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7402 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7403 V2Shuffle[V2Index] = 0;
7404 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7406 V2 = DAG.getBitcast(MVT::v2i64, V2);
7408 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7409 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7410 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7411 DAG.getDataLayout())));
7412 V2 = DAG.getBitcast(VT, V2);
7418 /// \brief Try to lower broadcast of a single element.
7420 /// For convenience, this code also bundles all of the subtarget feature set
7421 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7422 /// a convenient way to factor it out.
7423 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7425 const X86Subtarget *Subtarget,
7426 SelectionDAG &DAG) {
7427 if (!Subtarget->hasAVX())
7429 if (VT.isInteger() && !Subtarget->hasAVX2())
7432 // Check that the mask is a broadcast.
7433 int BroadcastIdx = -1;
7435 if (M >= 0 && BroadcastIdx == -1)
7437 else if (M >= 0 && M != BroadcastIdx)
7440 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7441 "a sorted mask where the broadcast "
7444 // Go up the chain of (vector) values to find a scalar load that we can
7445 // combine with the broadcast.
7447 switch (V.getOpcode()) {
7448 case ISD::CONCAT_VECTORS: {
7449 int OperandSize = Mask.size() / V.getNumOperands();
7450 V = V.getOperand(BroadcastIdx / OperandSize);
7451 BroadcastIdx %= OperandSize;
7455 case ISD::INSERT_SUBVECTOR: {
7456 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7457 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7461 int BeginIdx = (int)ConstantIdx->getZExtValue();
7463 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7464 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7465 BroadcastIdx -= BeginIdx;
7476 // Check if this is a broadcast of a scalar. We special case lowering
7477 // for scalars so that we can more effectively fold with loads.
7478 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7479 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7480 V = V.getOperand(BroadcastIdx);
7482 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7483 // Only AVX2 has register broadcasts.
7484 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7486 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7487 // We can't broadcast from a vector register without AVX2, and we can only
7488 // broadcast from the zero-element of a vector register.
7492 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7495 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7496 // INSERTPS when the V1 elements are already in the correct locations
7497 // because otherwise we can just always use two SHUFPS instructions which
7498 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7499 // perform INSERTPS if a single V1 element is out of place and all V2
7500 // elements are zeroable.
7501 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7503 SelectionDAG &DAG) {
7504 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7505 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7506 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7507 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7509 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7512 int V1DstIndex = -1;
7513 int V2DstIndex = -1;
7514 bool V1UsedInPlace = false;
7516 for (int i = 0; i < 4; ++i) {
7517 // Synthesize a zero mask from the zeroable elements (includes undefs).
7523 // Flag if we use any V1 inputs in place.
7525 V1UsedInPlace = true;
7529 // We can only insert a single non-zeroable element.
7530 if (V1DstIndex != -1 || V2DstIndex != -1)
7534 // V1 input out of place for insertion.
7537 // V2 input for insertion.
7542 // Don't bother if we have no (non-zeroable) element for insertion.
7543 if (V1DstIndex == -1 && V2DstIndex == -1)
7546 // Determine element insertion src/dst indices. The src index is from the
7547 // start of the inserted vector, not the start of the concatenated vector.
7548 unsigned V2SrcIndex = 0;
7549 if (V1DstIndex != -1) {
7550 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7551 // and don't use the original V2 at all.
7552 V2SrcIndex = Mask[V1DstIndex];
7553 V2DstIndex = V1DstIndex;
7556 V2SrcIndex = Mask[V2DstIndex] - 4;
7559 // If no V1 inputs are used in place, then the result is created only from
7560 // the zero mask and the V2 insertion - so remove V1 dependency.
7562 V1 = DAG.getUNDEF(MVT::v4f32);
7564 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7565 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7567 // Insert the V2 element into the desired position.
7569 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7570 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7573 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7574 /// UNPCK instruction.
7576 /// This specifically targets cases where we end up with alternating between
7577 /// the two inputs, and so can permute them into something that feeds a single
7578 /// UNPCK instruction. Note that this routine only targets integer vectors
7579 /// because for floating point vectors we have a generalized SHUFPS lowering
7580 /// strategy that handles everything that doesn't *exactly* match an unpack,
7581 /// making this clever lowering unnecessary.
7582 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7583 SDValue V2, ArrayRef<int> Mask,
7584 SelectionDAG &DAG) {
7585 assert(!VT.isFloatingPoint() &&
7586 "This routine only supports integer vectors.");
7587 assert(!isSingleInputShuffleMask(Mask) &&
7588 "This routine should only be used when blending two inputs.");
7589 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7591 int Size = Mask.size();
7593 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7594 return M >= 0 && M % Size < Size / 2;
7596 int NumHiInputs = std::count_if(
7597 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7599 bool UnpackLo = NumLoInputs >= NumHiInputs;
7601 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7602 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7603 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7605 for (int i = 0; i < Size; ++i) {
7609 // Each element of the unpack contains Scale elements from this mask.
7610 int UnpackIdx = i / Scale;
7612 // We only handle the case where V1 feeds the first slots of the unpack.
7613 // We rely on canonicalization to ensure this is the case.
7614 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7617 // Setup the mask for this input. The indexing is tricky as we have to
7618 // handle the unpack stride.
7619 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7620 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7624 // If we will have to shuffle both inputs to use the unpack, check whether
7625 // we can just unpack first and shuffle the result. If so, skip this unpack.
7626 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7627 !isNoopShuffleMask(V2Mask))
7630 // Shuffle the inputs into place.
7631 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7632 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7634 // Cast the inputs to the type we will use to unpack them.
7635 V1 = DAG.getBitcast(UnpackVT, V1);
7636 V2 = DAG.getBitcast(UnpackVT, V2);
7638 // Unpack the inputs and cast the result back to the desired type.
7639 return DAG.getBitcast(
7640 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7644 // We try each unpack from the largest to the smallest to try and find one
7645 // that fits this mask.
7646 int OrigNumElements = VT.getVectorNumElements();
7647 int OrigScalarSize = VT.getScalarSizeInBits();
7648 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7649 int Scale = ScalarSize / OrigScalarSize;
7650 int NumElements = OrigNumElements / Scale;
7651 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7652 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7656 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7658 if (NumLoInputs == 0 || NumHiInputs == 0) {
7659 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7660 "We have to have *some* inputs!");
7661 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7663 // FIXME: We could consider the total complexity of the permute of each
7664 // possible unpacking. Or at the least we should consider how many
7665 // half-crossings are created.
7666 // FIXME: We could consider commuting the unpacks.
7668 SmallVector<int, 32> PermMask;
7669 PermMask.assign(Size, -1);
7670 for (int i = 0; i < Size; ++i) {
7674 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7677 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7679 return DAG.getVectorShuffle(
7680 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7682 DAG.getUNDEF(VT), PermMask);
7688 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7690 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7691 /// support for floating point shuffles but not integer shuffles. These
7692 /// instructions will incur a domain crossing penalty on some chips though so
7693 /// it is better to avoid lowering through this for integer vectors where
7695 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7696 const X86Subtarget *Subtarget,
7697 SelectionDAG &DAG) {
7699 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7700 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7701 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7702 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7703 ArrayRef<int> Mask = SVOp->getMask();
7704 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7706 if (isSingleInputShuffleMask(Mask)) {
7707 // Use low duplicate instructions for masks that match their pattern.
7708 if (Subtarget->hasSSE3())
7709 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7710 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7712 // Straight shuffle of a single input vector. Simulate this by using the
7713 // single input as both of the "inputs" to this instruction..
7714 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7716 if (Subtarget->hasAVX()) {
7717 // If we have AVX, we can use VPERMILPS which will allow folding a load
7718 // into the shuffle.
7719 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7720 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7723 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7724 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7726 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7727 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7729 // If we have a single input, insert that into V1 if we can do so cheaply.
7730 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7731 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7732 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7734 // Try inverting the insertion since for v2 masks it is easy to do and we
7735 // can't reliably sort the mask one way or the other.
7736 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7737 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7738 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7739 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7743 // Try to use one of the special instruction patterns to handle two common
7744 // blend patterns if a zero-blend above didn't work.
7745 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7746 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7747 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7748 // We can either use a special instruction to load over the low double or
7749 // to move just the low double.
7751 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7753 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7755 if (Subtarget->hasSSE41())
7756 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7760 // Use dedicated unpack instructions for masks that match their pattern.
7761 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7762 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7763 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7764 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7766 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7767 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7768 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7771 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7773 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7774 /// the integer unit to minimize domain crossing penalties. However, for blends
7775 /// it falls back to the floating point shuffle operation with appropriate bit
7777 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7778 const X86Subtarget *Subtarget,
7779 SelectionDAG &DAG) {
7781 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7782 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7783 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7784 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7785 ArrayRef<int> Mask = SVOp->getMask();
7786 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7788 if (isSingleInputShuffleMask(Mask)) {
7789 // Check for being able to broadcast a single element.
7790 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7791 Mask, Subtarget, DAG))
7794 // Straight shuffle of a single input vector. For everything from SSE2
7795 // onward this has a single fast instruction with no scary immediates.
7796 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7797 V1 = DAG.getBitcast(MVT::v4i32, V1);
7798 int WidenedMask[4] = {
7799 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7800 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7801 return DAG.getBitcast(
7803 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7804 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7806 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7807 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7808 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7809 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7811 // If we have a blend of two PACKUS operations an the blend aligns with the
7812 // low and half halves, we can just merge the PACKUS operations. This is
7813 // particularly important as it lets us merge shuffles that this routine itself
7815 auto GetPackNode = [](SDValue V) {
7816 while (V.getOpcode() == ISD::BITCAST)
7817 V = V.getOperand(0);
7819 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7821 if (SDValue V1Pack = GetPackNode(V1))
7822 if (SDValue V2Pack = GetPackNode(V2))
7823 return DAG.getBitcast(MVT::v2i64,
7824 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7825 Mask[0] == 0 ? V1Pack.getOperand(0)
7826 : V1Pack.getOperand(1),
7827 Mask[1] == 2 ? V2Pack.getOperand(0)
7828 : V2Pack.getOperand(1)));
7830 // Try to use shift instructions.
7832 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7835 // When loading a scalar and then shuffling it into a vector we can often do
7836 // the insertion cheaply.
7837 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7838 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7840 // Try inverting the insertion since for v2 masks it is easy to do and we
7841 // can't reliably sort the mask one way or the other.
7842 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7843 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7844 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7847 // We have different paths for blend lowering, but they all must use the
7848 // *exact* same predicate.
7849 bool IsBlendSupported = Subtarget->hasSSE41();
7850 if (IsBlendSupported)
7851 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7855 // Use dedicated unpack instructions for masks that match their pattern.
7856 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7857 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7858 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7859 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7861 // Try to use byte rotation instructions.
7862 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7863 if (Subtarget->hasSSSE3())
7864 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7865 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7868 // If we have direct support for blends, we should lower by decomposing into
7869 // a permute. That will be faster than the domain cross.
7870 if (IsBlendSupported)
7871 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7874 // We implement this with SHUFPD which is pretty lame because it will likely
7875 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7876 // However, all the alternatives are still more cycles and newer chips don't
7877 // have this problem. It would be really nice if x86 had better shuffles here.
7878 V1 = DAG.getBitcast(MVT::v2f64, V1);
7879 V2 = DAG.getBitcast(MVT::v2f64, V2);
7880 return DAG.getBitcast(MVT::v2i64,
7881 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7884 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7886 /// This is used to disable more specialized lowerings when the shufps lowering
7887 /// will happen to be efficient.
7888 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7889 // This routine only handles 128-bit shufps.
7890 assert(Mask.size() == 4 && "Unsupported mask size!");
7892 // To lower with a single SHUFPS we need to have the low half and high half
7893 // each requiring a single input.
7894 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7896 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7902 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7904 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7905 /// It makes no assumptions about whether this is the *best* lowering, it simply
7907 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7908 ArrayRef<int> Mask, SDValue V1,
7909 SDValue V2, SelectionDAG &DAG) {
7910 SDValue LowV = V1, HighV = V2;
7911 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7914 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7916 if (NumV2Elements == 1) {
7918 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7921 // Compute the index adjacent to V2Index and in the same half by toggling
7923 int V2AdjIndex = V2Index ^ 1;
7925 if (Mask[V2AdjIndex] == -1) {
7926 // Handles all the cases where we have a single V2 element and an undef.
7927 // This will only ever happen in the high lanes because we commute the
7928 // vector otherwise.
7930 std::swap(LowV, HighV);
7931 NewMask[V2Index] -= 4;
7933 // Handle the case where the V2 element ends up adjacent to a V1 element.
7934 // To make this work, blend them together as the first step.
7935 int V1Index = V2AdjIndex;
7936 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7937 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7938 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7940 // Now proceed to reconstruct the final blend as we have the necessary
7941 // high or low half formed.
7948 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7949 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7951 } else if (NumV2Elements == 2) {
7952 if (Mask[0] < 4 && Mask[1] < 4) {
7953 // Handle the easy case where we have V1 in the low lanes and V2 in the
7957 } else if (Mask[2] < 4 && Mask[3] < 4) {
7958 // We also handle the reversed case because this utility may get called
7959 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7960 // arrange things in the right direction.
7966 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7967 // trying to place elements directly, just blend them and set up the final
7968 // shuffle to place them.
7970 // The first two blend mask elements are for V1, the second two are for
7972 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7973 Mask[2] < 4 ? Mask[2] : Mask[3],
7974 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7975 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7976 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7977 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7979 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7982 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7983 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7984 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7985 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7988 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7989 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7992 /// \brief Lower 4-lane 32-bit floating point shuffles.
7994 /// Uses instructions exclusively from the floating point unit to minimize
7995 /// domain crossing penalties, as these are sufficient to implement all v4f32
7997 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7998 const X86Subtarget *Subtarget,
7999 SelectionDAG &DAG) {
8001 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8002 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8003 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8004 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8005 ArrayRef<int> Mask = SVOp->getMask();
8006 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8009 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8011 if (NumV2Elements == 0) {
8012 // Check for being able to broadcast a single element.
8013 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8014 Mask, Subtarget, DAG))
8017 // Use even/odd duplicate instructions for masks that match their pattern.
8018 if (Subtarget->hasSSE3()) {
8019 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8020 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8021 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8022 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8025 if (Subtarget->hasAVX()) {
8026 // If we have AVX, we can use VPERMILPS which will allow folding a load
8027 // into the shuffle.
8028 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8029 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8032 // Otherwise, use a straight shuffle of a single input vector. We pass the
8033 // input vector to both operands to simulate this with a SHUFPS.
8034 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8035 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8038 // There are special ways we can lower some single-element blends. However, we
8039 // have custom ways we can lower more complex single-element blends below that
8040 // we defer to if both this and BLENDPS fail to match, so restrict this to
8041 // when the V2 input is targeting element 0 of the mask -- that is the fast
8043 if (NumV2Elements == 1 && Mask[0] >= 4)
8044 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8045 Mask, Subtarget, DAG))
8048 if (Subtarget->hasSSE41()) {
8049 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8053 // Use INSERTPS if we can complete the shuffle efficiently.
8054 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8057 if (!isSingleSHUFPSMask(Mask))
8058 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8059 DL, MVT::v4f32, V1, V2, Mask, DAG))
8063 // Use dedicated unpack instructions for masks that match their pattern.
8064 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8065 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8066 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8067 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8068 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8069 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8070 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8071 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8073 // Otherwise fall back to a SHUFPS lowering strategy.
8074 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8077 /// \brief Lower 4-lane i32 vector shuffles.
8079 /// We try to handle these with integer-domain shuffles where we can, but for
8080 /// blends we use the floating point domain blend instructions.
8081 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8082 const X86Subtarget *Subtarget,
8083 SelectionDAG &DAG) {
8085 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8086 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8087 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8088 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8089 ArrayRef<int> Mask = SVOp->getMask();
8090 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8092 // Whenever we can lower this as a zext, that instruction is strictly faster
8093 // than any alternative. It also allows us to fold memory operands into the
8094 // shuffle in many cases.
8095 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8096 Mask, Subtarget, DAG))
8100 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8102 if (NumV2Elements == 0) {
8103 // Check for being able to broadcast a single element.
8104 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8105 Mask, Subtarget, DAG))
8108 // Straight shuffle of a single input vector. For everything from SSE2
8109 // onward this has a single fast instruction with no scary immediates.
8110 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8111 // but we aren't actually going to use the UNPCK instruction because doing
8112 // so prevents folding a load into this instruction or making a copy.
8113 const int UnpackLoMask[] = {0, 0, 1, 1};
8114 const int UnpackHiMask[] = {2, 2, 3, 3};
8115 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8116 Mask = UnpackLoMask;
8117 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8118 Mask = UnpackHiMask;
8120 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8121 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8124 // Try to use shift instructions.
8126 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8129 // There are special ways we can lower some single-element blends.
8130 if (NumV2Elements == 1)
8131 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8132 Mask, Subtarget, DAG))
8135 // We have different paths for blend lowering, but they all must use the
8136 // *exact* same predicate.
8137 bool IsBlendSupported = Subtarget->hasSSE41();
8138 if (IsBlendSupported)
8139 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8143 if (SDValue Masked =
8144 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8147 // Use dedicated unpack instructions for masks that match their pattern.
8148 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8149 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8150 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8151 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8152 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8153 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8154 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8155 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8157 // Try to use byte rotation instructions.
8158 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8159 if (Subtarget->hasSSSE3())
8160 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8161 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8164 // If we have direct support for blends, we should lower by decomposing into
8165 // a permute. That will be faster than the domain cross.
8166 if (IsBlendSupported)
8167 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8170 // Try to lower by permuting the inputs into an unpack instruction.
8171 if (SDValue Unpack =
8172 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
8175 // We implement this with SHUFPS because it can blend from two vectors.
8176 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8177 // up the inputs, bypassing domain shift penalties that we would encur if we
8178 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8180 return DAG.getBitcast(
8182 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8183 DAG.getBitcast(MVT::v4f32, V2), Mask));
8186 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8187 /// shuffle lowering, and the most complex part.
8189 /// The lowering strategy is to try to form pairs of input lanes which are
8190 /// targeted at the same half of the final vector, and then use a dword shuffle
8191 /// to place them onto the right half, and finally unpack the paired lanes into
8192 /// their final position.
8194 /// The exact breakdown of how to form these dword pairs and align them on the
8195 /// correct sides is really tricky. See the comments within the function for
8196 /// more of the details.
8198 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8199 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8200 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8201 /// vector, form the analogous 128-bit 8-element Mask.
8202 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8203 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8204 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8205 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8206 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8208 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8209 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8210 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8212 SmallVector<int, 4> LoInputs;
8213 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8214 [](int M) { return M >= 0; });
8215 std::sort(LoInputs.begin(), LoInputs.end());
8216 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8217 SmallVector<int, 4> HiInputs;
8218 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8219 [](int M) { return M >= 0; });
8220 std::sort(HiInputs.begin(), HiInputs.end());
8221 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8223 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8224 int NumHToL = LoInputs.size() - NumLToL;
8226 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8227 int NumHToH = HiInputs.size() - NumLToH;
8228 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8229 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8230 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8231 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8233 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8234 // such inputs we can swap two of the dwords across the half mark and end up
8235 // with <=2 inputs to each half in each half. Once there, we can fall through
8236 // to the generic code below. For example:
8238 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8239 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8241 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8242 // and an existing 2-into-2 on the other half. In this case we may have to
8243 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8244 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8245 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8246 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8247 // half than the one we target for fixing) will be fixed when we re-enter this
8248 // path. We will also combine away any sequence of PSHUFD instructions that
8249 // result into a single instruction. Here is an example of the tricky case:
8251 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8252 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8254 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8256 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8257 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8259 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8260 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8262 // The result is fine to be handled by the generic logic.
8263 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8264 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8265 int AOffset, int BOffset) {
8266 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8267 "Must call this with A having 3 or 1 inputs from the A half.");
8268 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8269 "Must call this with B having 1 or 3 inputs from the B half.");
8270 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8271 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8273 // Compute the index of dword with only one word among the three inputs in
8274 // a half by taking the sum of the half with three inputs and subtracting
8275 // the sum of the actual three inputs. The difference is the remaining
8278 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8279 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8280 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8281 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8282 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8283 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8284 int TripleNonInputIdx =
8285 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8286 TripleDWord = TripleNonInputIdx / 2;
8288 // We use xor with one to compute the adjacent DWord to whichever one the
8290 OneInputDWord = (OneInput / 2) ^ 1;
8292 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8293 // and BToA inputs. If there is also such a problem with the BToB and AToB
8294 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8295 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8296 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8297 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8298 // Compute how many inputs will be flipped by swapping these DWords. We
8300 // to balance this to ensure we don't form a 3-1 shuffle in the other
8302 int NumFlippedAToBInputs =
8303 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8304 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8305 int NumFlippedBToBInputs =
8306 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8307 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8308 if ((NumFlippedAToBInputs == 1 &&
8309 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8310 (NumFlippedBToBInputs == 1 &&
8311 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8312 // We choose whether to fix the A half or B half based on whether that
8313 // half has zero flipped inputs. At zero, we may not be able to fix it
8314 // with that half. We also bias towards fixing the B half because that
8315 // will more commonly be the high half, and we have to bias one way.
8316 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8317 ArrayRef<int> Inputs) {
8318 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8319 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8320 PinnedIdx ^ 1) != Inputs.end();
8321 // Determine whether the free index is in the flipped dword or the
8322 // unflipped dword based on where the pinned index is. We use this bit
8323 // in an xor to conditionally select the adjacent dword.
8324 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8325 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8326 FixFreeIdx) != Inputs.end();
8327 if (IsFixIdxInput == IsFixFreeIdxInput)
8329 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8330 FixFreeIdx) != Inputs.end();
8331 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8332 "We need to be changing the number of flipped inputs!");
8333 int PSHUFHalfMask[] = {0, 1, 2, 3};
8334 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8335 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8337 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8340 if (M != -1 && M == FixIdx)
8342 else if (M != -1 && M == FixFreeIdx)
8345 if (NumFlippedBToBInputs != 0) {
8347 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8348 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8350 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8352 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8353 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8358 int PSHUFDMask[] = {0, 1, 2, 3};
8359 PSHUFDMask[ADWord] = BDWord;
8360 PSHUFDMask[BDWord] = ADWord;
8363 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8364 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8366 // Adjust the mask to match the new locations of A and B.
8368 if (M != -1 && M/2 == ADWord)
8369 M = 2 * BDWord + M % 2;
8370 else if (M != -1 && M/2 == BDWord)
8371 M = 2 * ADWord + M % 2;
8373 // Recurse back into this routine to re-compute state now that this isn't
8374 // a 3 and 1 problem.
8375 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8378 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8379 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8380 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8381 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8383 // At this point there are at most two inputs to the low and high halves from
8384 // each half. That means the inputs can always be grouped into dwords and
8385 // those dwords can then be moved to the correct half with a dword shuffle.
8386 // We use at most one low and one high word shuffle to collect these paired
8387 // inputs into dwords, and finally a dword shuffle to place them.
8388 int PSHUFLMask[4] = {-1, -1, -1, -1};
8389 int PSHUFHMask[4] = {-1, -1, -1, -1};
8390 int PSHUFDMask[4] = {-1, -1, -1, -1};
8392 // First fix the masks for all the inputs that are staying in their
8393 // original halves. This will then dictate the targets of the cross-half
8395 auto fixInPlaceInputs =
8396 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8397 MutableArrayRef<int> SourceHalfMask,
8398 MutableArrayRef<int> HalfMask, int HalfOffset) {
8399 if (InPlaceInputs.empty())
8401 if (InPlaceInputs.size() == 1) {
8402 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8403 InPlaceInputs[0] - HalfOffset;
8404 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8407 if (IncomingInputs.empty()) {
8408 // Just fix all of the in place inputs.
8409 for (int Input : InPlaceInputs) {
8410 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8411 PSHUFDMask[Input / 2] = Input / 2;
8416 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8417 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8418 InPlaceInputs[0] - HalfOffset;
8419 // Put the second input next to the first so that they are packed into
8420 // a dword. We find the adjacent index by toggling the low bit.
8421 int AdjIndex = InPlaceInputs[0] ^ 1;
8422 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8423 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8424 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8426 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8427 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8429 // Now gather the cross-half inputs and place them into a free dword of
8430 // their target half.
8431 // FIXME: This operation could almost certainly be simplified dramatically to
8432 // look more like the 3-1 fixing operation.
8433 auto moveInputsToRightHalf = [&PSHUFDMask](
8434 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8435 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8436 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8438 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8439 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8441 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8443 int LowWord = Word & ~1;
8444 int HighWord = Word | 1;
8445 return isWordClobbered(SourceHalfMask, LowWord) ||
8446 isWordClobbered(SourceHalfMask, HighWord);
8449 if (IncomingInputs.empty())
8452 if (ExistingInputs.empty()) {
8453 // Map any dwords with inputs from them into the right half.
8454 for (int Input : IncomingInputs) {
8455 // If the source half mask maps over the inputs, turn those into
8456 // swaps and use the swapped lane.
8457 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8458 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8459 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8460 Input - SourceOffset;
8461 // We have to swap the uses in our half mask in one sweep.
8462 for (int &M : HalfMask)
8463 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8465 else if (M == Input)
8466 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8468 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8469 Input - SourceOffset &&
8470 "Previous placement doesn't match!");
8472 // Note that this correctly re-maps both when we do a swap and when
8473 // we observe the other side of the swap above. We rely on that to
8474 // avoid swapping the members of the input list directly.
8475 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8478 // Map the input's dword into the correct half.
8479 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8480 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8482 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8484 "Previous placement doesn't match!");
8487 // And just directly shift any other-half mask elements to be same-half
8488 // as we will have mirrored the dword containing the element into the
8489 // same position within that half.
8490 for (int &M : HalfMask)
8491 if (M >= SourceOffset && M < SourceOffset + 4) {
8492 M = M - SourceOffset + DestOffset;
8493 assert(M >= 0 && "This should never wrap below zero!");
8498 // Ensure we have the input in a viable dword of its current half. This
8499 // is particularly tricky because the original position may be clobbered
8500 // by inputs being moved and *staying* in that half.
8501 if (IncomingInputs.size() == 1) {
8502 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8503 int InputFixed = std::find(std::begin(SourceHalfMask),
8504 std::end(SourceHalfMask), -1) -
8505 std::begin(SourceHalfMask) + SourceOffset;
8506 SourceHalfMask[InputFixed - SourceOffset] =
8507 IncomingInputs[0] - SourceOffset;
8508 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8510 IncomingInputs[0] = InputFixed;
8512 } else if (IncomingInputs.size() == 2) {
8513 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8514 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8515 // We have two non-adjacent or clobbered inputs we need to extract from
8516 // the source half. To do this, we need to map them into some adjacent
8517 // dword slot in the source mask.
8518 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8519 IncomingInputs[1] - SourceOffset};
8521 // If there is a free slot in the source half mask adjacent to one of
8522 // the inputs, place the other input in it. We use (Index XOR 1) to
8523 // compute an adjacent index.
8524 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8525 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8526 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8527 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8528 InputsFixed[1] = InputsFixed[0] ^ 1;
8529 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8530 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8531 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8532 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8533 InputsFixed[0] = InputsFixed[1] ^ 1;
8534 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8535 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8536 // The two inputs are in the same DWord but it is clobbered and the
8537 // adjacent DWord isn't used at all. Move both inputs to the free
8539 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8540 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8541 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8542 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8544 // The only way we hit this point is if there is no clobbering
8545 // (because there are no off-half inputs to this half) and there is no
8546 // free slot adjacent to one of the inputs. In this case, we have to
8547 // swap an input with a non-input.
8548 for (int i = 0; i < 4; ++i)
8549 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8550 "We can't handle any clobbers here!");
8551 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8552 "Cannot have adjacent inputs here!");
8554 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8555 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8557 // We also have to update the final source mask in this case because
8558 // it may need to undo the above swap.
8559 for (int &M : FinalSourceHalfMask)
8560 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8561 M = InputsFixed[1] + SourceOffset;
8562 else if (M == InputsFixed[1] + SourceOffset)
8563 M = (InputsFixed[0] ^ 1) + SourceOffset;
8565 InputsFixed[1] = InputsFixed[0] ^ 1;
8568 // Point everything at the fixed inputs.
8569 for (int &M : HalfMask)
8570 if (M == IncomingInputs[0])
8571 M = InputsFixed[0] + SourceOffset;
8572 else if (M == IncomingInputs[1])
8573 M = InputsFixed[1] + SourceOffset;
8575 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8576 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8579 llvm_unreachable("Unhandled input size!");
8582 // Now hoist the DWord down to the right half.
8583 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8584 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8585 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8586 for (int &M : HalfMask)
8587 for (int Input : IncomingInputs)
8589 M = FreeDWord * 2 + Input % 2;
8591 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8592 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8593 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8594 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8596 // Now enact all the shuffles we've computed to move the inputs into their
8598 if (!isNoopShuffleMask(PSHUFLMask))
8599 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8600 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8601 if (!isNoopShuffleMask(PSHUFHMask))
8602 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8603 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8604 if (!isNoopShuffleMask(PSHUFDMask))
8607 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8608 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8610 // At this point, each half should contain all its inputs, and we can then
8611 // just shuffle them into their final position.
8612 assert(std::count_if(LoMask.begin(), LoMask.end(),
8613 [](int M) { return M >= 4; }) == 0 &&
8614 "Failed to lift all the high half inputs to the low mask!");
8615 assert(std::count_if(HiMask.begin(), HiMask.end(),
8616 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8617 "Failed to lift all the low half inputs to the high mask!");
8619 // Do a half shuffle for the low mask.
8620 if (!isNoopShuffleMask(LoMask))
8621 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8622 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8624 // Do a half shuffle with the high mask after shifting its values down.
8625 for (int &M : HiMask)
8628 if (!isNoopShuffleMask(HiMask))
8629 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8630 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8635 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8636 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8637 SDValue V2, ArrayRef<int> Mask,
8638 SelectionDAG &DAG, bool &V1InUse,
8640 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8646 int Size = Mask.size();
8647 int Scale = 16 / Size;
8648 for (int i = 0; i < 16; ++i) {
8649 if (Mask[i / Scale] == -1) {
8650 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8652 const int ZeroMask = 0x80;
8653 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8655 int V2Idx = Mask[i / Scale] < Size
8657 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8658 if (Zeroable[i / Scale])
8659 V1Idx = V2Idx = ZeroMask;
8660 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8661 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8662 V1InUse |= (ZeroMask != V1Idx);
8663 V2InUse |= (ZeroMask != V2Idx);
8668 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8669 DAG.getBitcast(MVT::v16i8, V1),
8670 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8672 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8673 DAG.getBitcast(MVT::v16i8, V2),
8674 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8676 // If we need shuffled inputs from both, blend the two.
8678 if (V1InUse && V2InUse)
8679 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8681 V = V1InUse ? V1 : V2;
8683 // Cast the result back to the correct type.
8684 return DAG.getBitcast(VT, V);
8687 /// \brief Generic lowering of 8-lane i16 shuffles.
8689 /// This handles both single-input shuffles and combined shuffle/blends with
8690 /// two inputs. The single input shuffles are immediately delegated to
8691 /// a dedicated lowering routine.
8693 /// The blends are lowered in one of three fundamental ways. If there are few
8694 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8695 /// of the input is significantly cheaper when lowered as an interleaving of
8696 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8697 /// halves of the inputs separately (making them have relatively few inputs)
8698 /// and then concatenate them.
8699 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8700 const X86Subtarget *Subtarget,
8701 SelectionDAG &DAG) {
8703 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8704 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8705 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8707 ArrayRef<int> OrigMask = SVOp->getMask();
8708 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8709 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8710 MutableArrayRef<int> Mask(MaskStorage);
8712 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8714 // Whenever we can lower this as a zext, that instruction is strictly faster
8715 // than any alternative.
8716 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8717 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8720 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8722 auto isV2 = [](int M) { return M >= 8; };
8724 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8726 if (NumV2Inputs == 0) {
8727 // Check for being able to broadcast a single element.
8728 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8729 Mask, Subtarget, DAG))
8732 // Try to use shift instructions.
8734 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8737 // Use dedicated unpack instructions for masks that match their pattern.
8738 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8739 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8740 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8741 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8743 // Try to use byte rotation instructions.
8744 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8745 Mask, Subtarget, DAG))
8748 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8752 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8753 "All single-input shuffles should be canonicalized to be V1-input "
8756 // Try to use shift instructions.
8758 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8761 // See if we can use SSE4A Extraction / Insertion.
8762 if (Subtarget->hasSSE4A())
8763 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
8766 // There are special ways we can lower some single-element blends.
8767 if (NumV2Inputs == 1)
8768 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8769 Mask, Subtarget, DAG))
8772 // We have different paths for blend lowering, but they all must use the
8773 // *exact* same predicate.
8774 bool IsBlendSupported = Subtarget->hasSSE41();
8775 if (IsBlendSupported)
8776 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8780 if (SDValue Masked =
8781 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8784 // Use dedicated unpack instructions for masks that match their pattern.
8785 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8786 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8787 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8788 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8790 // Try to use byte rotation instructions.
8791 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8792 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8795 if (SDValue BitBlend =
8796 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8799 if (SDValue Unpack =
8800 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8803 // If we can't directly blend but can use PSHUFB, that will be better as it
8804 // can both shuffle and set up the inefficient blend.
8805 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8806 bool V1InUse, V2InUse;
8807 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8811 // We can always bit-blend if we have to so the fallback strategy is to
8812 // decompose into single-input permutes and blends.
8813 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8817 /// \brief Check whether a compaction lowering can be done by dropping even
8818 /// elements and compute how many times even elements must be dropped.
8820 /// This handles shuffles which take every Nth element where N is a power of
8821 /// two. Example shuffle masks:
8823 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8824 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8825 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8826 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8827 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8828 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8830 /// Any of these lanes can of course be undef.
8832 /// This routine only supports N <= 3.
8833 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8836 /// \returns N above, or the number of times even elements must be dropped if
8837 /// there is such a number. Otherwise returns zero.
8838 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8839 // Figure out whether we're looping over two inputs or just one.
8840 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8842 // The modulus for the shuffle vector entries is based on whether this is
8843 // a single input or not.
8844 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8845 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8846 "We should only be called with masks with a power-of-2 size!");
8848 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8850 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8851 // and 2^3 simultaneously. This is because we may have ambiguity with
8852 // partially undef inputs.
8853 bool ViableForN[3] = {true, true, true};
8855 for (int i = 0, e = Mask.size(); i < e; ++i) {
8856 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8861 bool IsAnyViable = false;
8862 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8863 if (ViableForN[j]) {
8866 // The shuffle mask must be equal to (i * 2^N) % M.
8867 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8870 ViableForN[j] = false;
8872 // Early exit if we exhaust the possible powers of two.
8877 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8881 // Return 0 as there is no viable power of two.
8885 /// \brief Generic lowering of v16i8 shuffles.
8887 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8888 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8889 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8890 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8892 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8893 const X86Subtarget *Subtarget,
8894 SelectionDAG &DAG) {
8896 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8897 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8898 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8899 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8900 ArrayRef<int> Mask = SVOp->getMask();
8901 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8903 // Try to use shift instructions.
8905 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8908 // Try to use byte rotation instructions.
8909 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8910 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8913 // Try to use a zext lowering.
8914 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8915 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8918 // See if we can use SSE4A Extraction / Insertion.
8919 if (Subtarget->hasSSE4A())
8920 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
8924 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8926 // For single-input shuffles, there are some nicer lowering tricks we can use.
8927 if (NumV2Elements == 0) {
8928 // Check for being able to broadcast a single element.
8929 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8930 Mask, Subtarget, DAG))
8933 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8934 // Notably, this handles splat and partial-splat shuffles more efficiently.
8935 // However, it only makes sense if the pre-duplication shuffle simplifies
8936 // things significantly. Currently, this means we need to be able to
8937 // express the pre-duplication shuffle as an i16 shuffle.
8939 // FIXME: We should check for other patterns which can be widened into an
8940 // i16 shuffle as well.
8941 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8942 for (int i = 0; i < 16; i += 2)
8943 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8948 auto tryToWidenViaDuplication = [&]() -> SDValue {
8949 if (!canWidenViaDuplication(Mask))
8951 SmallVector<int, 4> LoInputs;
8952 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8953 [](int M) { return M >= 0 && M < 8; });
8954 std::sort(LoInputs.begin(), LoInputs.end());
8955 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8957 SmallVector<int, 4> HiInputs;
8958 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8959 [](int M) { return M >= 8; });
8960 std::sort(HiInputs.begin(), HiInputs.end());
8961 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8964 bool TargetLo = LoInputs.size() >= HiInputs.size();
8965 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8966 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8968 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8969 SmallDenseMap<int, int, 8> LaneMap;
8970 for (int I : InPlaceInputs) {
8971 PreDupI16Shuffle[I/2] = I/2;
8974 int j = TargetLo ? 0 : 4, je = j + 4;
8975 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8976 // Check if j is already a shuffle of this input. This happens when
8977 // there are two adjacent bytes after we move the low one.
8978 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8979 // If we haven't yet mapped the input, search for a slot into which
8981 while (j < je && PreDupI16Shuffle[j] != -1)
8985 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8988 // Map this input with the i16 shuffle.
8989 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8992 // Update the lane map based on the mapping we ended up with.
8993 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8995 V1 = DAG.getBitcast(
8997 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8998 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9000 // Unpack the bytes to form the i16s that will be shuffled into place.
9001 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9002 MVT::v16i8, V1, V1);
9004 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9005 for (int i = 0; i < 16; ++i)
9006 if (Mask[i] != -1) {
9007 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9008 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9009 if (PostDupI16Shuffle[i / 2] == -1)
9010 PostDupI16Shuffle[i / 2] = MappedMask;
9012 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9013 "Conflicting entrties in the original shuffle!");
9015 return DAG.getBitcast(
9017 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9018 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9020 if (SDValue V = tryToWidenViaDuplication())
9024 // Use dedicated unpack instructions for masks that match their pattern.
9025 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9026 0, 16, 1, 17, 2, 18, 3, 19,
9028 4, 20, 5, 21, 6, 22, 7, 23}))
9029 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9030 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9031 8, 24, 9, 25, 10, 26, 11, 27,
9033 12, 28, 13, 29, 14, 30, 15, 31}))
9034 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9036 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9037 // with PSHUFB. It is important to do this before we attempt to generate any
9038 // blends but after all of the single-input lowerings. If the single input
9039 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9040 // want to preserve that and we can DAG combine any longer sequences into
9041 // a PSHUFB in the end. But once we start blending from multiple inputs,
9042 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9043 // and there are *very* few patterns that would actually be faster than the
9044 // PSHUFB approach because of its ability to zero lanes.
9046 // FIXME: The only exceptions to the above are blends which are exact
9047 // interleavings with direct instructions supporting them. We currently don't
9048 // handle those well here.
9049 if (Subtarget->hasSSSE3()) {
9050 bool V1InUse = false;
9051 bool V2InUse = false;
9053 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9054 DAG, V1InUse, V2InUse);
9056 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9057 // do so. This avoids using them to handle blends-with-zero which is
9058 // important as a single pshufb is significantly faster for that.
9059 if (V1InUse && V2InUse) {
9060 if (Subtarget->hasSSE41())
9061 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9062 Mask, Subtarget, DAG))
9065 // We can use an unpack to do the blending rather than an or in some
9066 // cases. Even though the or may be (very minorly) more efficient, we
9067 // preference this lowering because there are common cases where part of
9068 // the complexity of the shuffles goes away when we do the final blend as
9070 // FIXME: It might be worth trying to detect if the unpack-feeding
9071 // shuffles will both be pshufb, in which case we shouldn't bother with
9073 if (SDValue Unpack =
9074 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
9081 // There are special ways we can lower some single-element blends.
9082 if (NumV2Elements == 1)
9083 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9084 Mask, Subtarget, DAG))
9087 if (SDValue BitBlend =
9088 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9091 // Check whether a compaction lowering can be done. This handles shuffles
9092 // which take every Nth element for some even N. See the helper function for
9095 // We special case these as they can be particularly efficiently handled with
9096 // the PACKUSB instruction on x86 and they show up in common patterns of
9097 // rearranging bytes to truncate wide elements.
9098 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9099 // NumEvenDrops is the power of two stride of the elements. Another way of
9100 // thinking about it is that we need to drop the even elements this many
9101 // times to get the original input.
9102 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9104 // First we need to zero all the dropped bytes.
9105 assert(NumEvenDrops <= 3 &&
9106 "No support for dropping even elements more than 3 times.");
9107 // We use the mask type to pick which bytes are preserved based on how many
9108 // elements are dropped.
9109 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9110 SDValue ByteClearMask = DAG.getBitcast(
9111 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9112 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9114 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9116 // Now pack things back together.
9117 V1 = DAG.getBitcast(MVT::v8i16, V1);
9118 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9119 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9120 for (int i = 1; i < NumEvenDrops; ++i) {
9121 Result = DAG.getBitcast(MVT::v8i16, Result);
9122 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9128 // Handle multi-input cases by blending single-input shuffles.
9129 if (NumV2Elements > 0)
9130 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9133 // The fallback path for single-input shuffles widens this into two v8i16
9134 // vectors with unpacks, shuffles those, and then pulls them back together
9138 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9139 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9140 for (int i = 0; i < 16; ++i)
9142 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9144 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9146 SDValue VLoHalf, VHiHalf;
9147 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9148 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9150 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9151 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9152 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9153 [](int M) { return M >= 0 && M % 2 == 1; })) {
9154 // Use a mask to drop the high bytes.
9155 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9156 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9157 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9159 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9160 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9162 // Squash the masks to point directly into VLoHalf.
9163 for (int &M : LoBlendMask)
9166 for (int &M : HiBlendMask)
9170 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9171 // VHiHalf so that we can blend them as i16s.
9172 VLoHalf = DAG.getBitcast(
9173 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9174 VHiHalf = DAG.getBitcast(
9175 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9178 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9179 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9181 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9184 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9186 /// This routine breaks down the specific type of 128-bit shuffle and
9187 /// dispatches to the lowering routines accordingly.
9188 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9189 MVT VT, const X86Subtarget *Subtarget,
9190 SelectionDAG &DAG) {
9191 switch (VT.SimpleTy) {
9193 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9195 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9197 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9199 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9201 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9203 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9206 llvm_unreachable("Unimplemented!");
9210 /// \brief Helper function to test whether a shuffle mask could be
9211 /// simplified by widening the elements being shuffled.
9213 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9214 /// leaves it in an unspecified state.
9216 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9217 /// shuffle masks. The latter have the special property of a '-2' representing
9218 /// a zero-ed lane of a vector.
9219 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9220 SmallVectorImpl<int> &WidenedMask) {
9221 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9222 // If both elements are undef, its trivial.
9223 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9224 WidenedMask.push_back(SM_SentinelUndef);
9228 // Check for an undef mask and a mask value properly aligned to fit with
9229 // a pair of values. If we find such a case, use the non-undef mask's value.
9230 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9231 WidenedMask.push_back(Mask[i + 1] / 2);
9234 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9235 WidenedMask.push_back(Mask[i] / 2);
9239 // When zeroing, we need to spread the zeroing across both lanes to widen.
9240 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9241 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9242 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9243 WidenedMask.push_back(SM_SentinelZero);
9249 // Finally check if the two mask values are adjacent and aligned with
9251 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9252 WidenedMask.push_back(Mask[i] / 2);
9256 // Otherwise we can't safely widen the elements used in this shuffle.
9259 assert(WidenedMask.size() == Mask.size() / 2 &&
9260 "Incorrect size of mask after widening the elements!");
9265 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9267 /// This routine just extracts two subvectors, shuffles them independently, and
9268 /// then concatenates them back together. This should work effectively with all
9269 /// AVX vector shuffle types.
9270 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9271 SDValue V2, ArrayRef<int> Mask,
9272 SelectionDAG &DAG) {
9273 assert(VT.getSizeInBits() >= 256 &&
9274 "Only for 256-bit or wider vector shuffles!");
9275 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9276 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9278 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9279 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9281 int NumElements = VT.getVectorNumElements();
9282 int SplitNumElements = NumElements / 2;
9283 MVT ScalarVT = VT.getScalarType();
9284 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9286 // Rather than splitting build-vectors, just build two narrower build
9287 // vectors. This helps shuffling with splats and zeros.
9288 auto SplitVector = [&](SDValue V) {
9289 while (V.getOpcode() == ISD::BITCAST)
9290 V = V->getOperand(0);
9292 MVT OrigVT = V.getSimpleValueType();
9293 int OrigNumElements = OrigVT.getVectorNumElements();
9294 int OrigSplitNumElements = OrigNumElements / 2;
9295 MVT OrigScalarVT = OrigVT.getScalarType();
9296 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9300 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9302 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9303 DAG.getIntPtrConstant(0, DL));
9304 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9305 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9308 SmallVector<SDValue, 16> LoOps, HiOps;
9309 for (int i = 0; i < OrigSplitNumElements; ++i) {
9310 LoOps.push_back(BV->getOperand(i));
9311 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9313 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9314 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9316 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9317 DAG.getBitcast(SplitVT, HiV));
9320 SDValue LoV1, HiV1, LoV2, HiV2;
9321 std::tie(LoV1, HiV1) = SplitVector(V1);
9322 std::tie(LoV2, HiV2) = SplitVector(V2);
9324 // Now create two 4-way blends of these half-width vectors.
9325 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9326 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9327 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9328 for (int i = 0; i < SplitNumElements; ++i) {
9329 int M = HalfMask[i];
9330 if (M >= NumElements) {
9331 if (M >= NumElements + SplitNumElements)
9335 V2BlendMask.push_back(M - NumElements);
9336 V1BlendMask.push_back(-1);
9337 BlendMask.push_back(SplitNumElements + i);
9338 } else if (M >= 0) {
9339 if (M >= SplitNumElements)
9343 V2BlendMask.push_back(-1);
9344 V1BlendMask.push_back(M);
9345 BlendMask.push_back(i);
9347 V2BlendMask.push_back(-1);
9348 V1BlendMask.push_back(-1);
9349 BlendMask.push_back(-1);
9353 // Because the lowering happens after all combining takes place, we need to
9354 // manually combine these blend masks as much as possible so that we create
9355 // a minimal number of high-level vector shuffle nodes.
9357 // First try just blending the halves of V1 or V2.
9358 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9359 return DAG.getUNDEF(SplitVT);
9360 if (!UseLoV2 && !UseHiV2)
9361 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9362 if (!UseLoV1 && !UseHiV1)
9363 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9365 SDValue V1Blend, V2Blend;
9366 if (UseLoV1 && UseHiV1) {
9368 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9370 // We only use half of V1 so map the usage down into the final blend mask.
9371 V1Blend = UseLoV1 ? LoV1 : HiV1;
9372 for (int i = 0; i < SplitNumElements; ++i)
9373 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9374 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9376 if (UseLoV2 && UseHiV2) {
9378 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9380 // We only use half of V2 so map the usage down into the final blend mask.
9381 V2Blend = UseLoV2 ? LoV2 : HiV2;
9382 for (int i = 0; i < SplitNumElements; ++i)
9383 if (BlendMask[i] >= SplitNumElements)
9384 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9386 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9388 SDValue Lo = HalfBlend(LoMask);
9389 SDValue Hi = HalfBlend(HiMask);
9390 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9393 /// \brief Either split a vector in halves or decompose the shuffles and the
9396 /// This is provided as a good fallback for many lowerings of non-single-input
9397 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9398 /// between splitting the shuffle into 128-bit components and stitching those
9399 /// back together vs. extracting the single-input shuffles and blending those
9401 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9402 SDValue V2, ArrayRef<int> Mask,
9403 SelectionDAG &DAG) {
9404 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9405 "lower single-input shuffles as it "
9406 "could then recurse on itself.");
9407 int Size = Mask.size();
9409 // If this can be modeled as a broadcast of two elements followed by a blend,
9410 // prefer that lowering. This is especially important because broadcasts can
9411 // often fold with memory operands.
9412 auto DoBothBroadcast = [&] {
9413 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9416 if (V2BroadcastIdx == -1)
9417 V2BroadcastIdx = M - Size;
9418 else if (M - Size != V2BroadcastIdx)
9420 } else if (M >= 0) {
9421 if (V1BroadcastIdx == -1)
9423 else if (M != V1BroadcastIdx)
9428 if (DoBothBroadcast())
9429 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9432 // If the inputs all stem from a single 128-bit lane of each input, then we
9433 // split them rather than blending because the split will decompose to
9434 // unusually few instructions.
9435 int LaneCount = VT.getSizeInBits() / 128;
9436 int LaneSize = Size / LaneCount;
9437 SmallBitVector LaneInputs[2];
9438 LaneInputs[0].resize(LaneCount, false);
9439 LaneInputs[1].resize(LaneCount, false);
9440 for (int i = 0; i < Size; ++i)
9442 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9443 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9444 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9446 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9447 // that the decomposed single-input shuffles don't end up here.
9448 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9451 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9452 /// a permutation and blend of those lanes.
9454 /// This essentially blends the out-of-lane inputs to each lane into the lane
9455 /// from a permuted copy of the vector. This lowering strategy results in four
9456 /// instructions in the worst case for a single-input cross lane shuffle which
9457 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9458 /// of. Special cases for each particular shuffle pattern should be handled
9459 /// prior to trying this lowering.
9460 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9461 SDValue V1, SDValue V2,
9463 SelectionDAG &DAG) {
9464 // FIXME: This should probably be generalized for 512-bit vectors as well.
9465 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9466 int LaneSize = Mask.size() / 2;
9468 // If there are only inputs from one 128-bit lane, splitting will in fact be
9469 // less expensive. The flags track whether the given lane contains an element
9470 // that crosses to another lane.
9471 bool LaneCrossing[2] = {false, false};
9472 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9473 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9474 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9475 if (!LaneCrossing[0] || !LaneCrossing[1])
9476 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9478 if (isSingleInputShuffleMask(Mask)) {
9479 SmallVector<int, 32> FlippedBlendMask;
9480 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9481 FlippedBlendMask.push_back(
9482 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9484 : Mask[i] % LaneSize +
9485 (i / LaneSize) * LaneSize + Size));
9487 // Flip the vector, and blend the results which should now be in-lane. The
9488 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9489 // 5 for the high source. The value 3 selects the high half of source 2 and
9490 // the value 2 selects the low half of source 2. We only use source 2 to
9491 // allow folding it into a memory operand.
9492 unsigned PERMMask = 3 | 2 << 4;
9493 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9494 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9495 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9498 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9499 // will be handled by the above logic and a blend of the results, much like
9500 // other patterns in AVX.
9501 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9504 /// \brief Handle lowering 2-lane 128-bit shuffles.
9505 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9506 SDValue V2, ArrayRef<int> Mask,
9507 const X86Subtarget *Subtarget,
9508 SelectionDAG &DAG) {
9509 // TODO: If minimizing size and one of the inputs is a zero vector and the
9510 // the zero vector has only one use, we could use a VPERM2X128 to save the
9511 // instruction bytes needed to explicitly generate the zero vector.
9513 // Blends are faster and handle all the non-lane-crossing cases.
9514 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9518 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9519 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9521 // If either input operand is a zero vector, use VPERM2X128 because its mask
9522 // allows us to replace the zero input with an implicit zero.
9523 if (!IsV1Zero && !IsV2Zero) {
9524 // Check for patterns which can be matched with a single insert of a 128-bit
9526 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9527 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9528 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9529 VT.getVectorNumElements() / 2);
9530 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9531 DAG.getIntPtrConstant(0, DL));
9532 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9533 OnlyUsesV1 ? V1 : V2,
9534 DAG.getIntPtrConstant(0, DL));
9535 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9539 // Otherwise form a 128-bit permutation. After accounting for undefs,
9540 // convert the 64-bit shuffle mask selection values into 128-bit
9541 // selection bits by dividing the indexes by 2 and shifting into positions
9542 // defined by a vperm2*128 instruction's immediate control byte.
9544 // The immediate permute control byte looks like this:
9545 // [1:0] - select 128 bits from sources for low half of destination
9547 // [3] - zero low half of destination
9548 // [5:4] - select 128 bits from sources for high half of destination
9550 // [7] - zero high half of destination
9552 int MaskLO = Mask[0];
9553 if (MaskLO == SM_SentinelUndef)
9554 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9556 int MaskHI = Mask[2];
9557 if (MaskHI == SM_SentinelUndef)
9558 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9560 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9562 // If either input is a zero vector, replace it with an undef input.
9563 // Shuffle mask values < 4 are selecting elements of V1.
9564 // Shuffle mask values >= 4 are selecting elements of V2.
9565 // Adjust each half of the permute mask by clearing the half that was
9566 // selecting the zero vector and setting the zero mask bit.
9568 V1 = DAG.getUNDEF(VT);
9570 PermMask = (PermMask & 0xf0) | 0x08;
9572 PermMask = (PermMask & 0x0f) | 0x80;
9575 V2 = DAG.getUNDEF(VT);
9577 PermMask = (PermMask & 0xf0) | 0x08;
9579 PermMask = (PermMask & 0x0f) | 0x80;
9582 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9583 DAG.getConstant(PermMask, DL, MVT::i8));
9586 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9587 /// shuffling each lane.
9589 /// This will only succeed when the result of fixing the 128-bit lanes results
9590 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9591 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9592 /// the lane crosses early and then use simpler shuffles within each lane.
9594 /// FIXME: It might be worthwhile at some point to support this without
9595 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9596 /// in x86 only floating point has interesting non-repeating shuffles, and even
9597 /// those are still *marginally* more expensive.
9598 static SDValue lowerVectorShuffleByMerging128BitLanes(
9599 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9600 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9601 assert(!isSingleInputShuffleMask(Mask) &&
9602 "This is only useful with multiple inputs.");
9604 int Size = Mask.size();
9605 int LaneSize = 128 / VT.getScalarSizeInBits();
9606 int NumLanes = Size / LaneSize;
9607 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9609 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9610 // check whether the in-128-bit lane shuffles share a repeating pattern.
9611 SmallVector<int, 4> Lanes;
9612 Lanes.resize(NumLanes, -1);
9613 SmallVector<int, 4> InLaneMask;
9614 InLaneMask.resize(LaneSize, -1);
9615 for (int i = 0; i < Size; ++i) {
9619 int j = i / LaneSize;
9622 // First entry we've seen for this lane.
9623 Lanes[j] = Mask[i] / LaneSize;
9624 } else if (Lanes[j] != Mask[i] / LaneSize) {
9625 // This doesn't match the lane selected previously!
9629 // Check that within each lane we have a consistent shuffle mask.
9630 int k = i % LaneSize;
9631 if (InLaneMask[k] < 0) {
9632 InLaneMask[k] = Mask[i] % LaneSize;
9633 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9634 // This doesn't fit a repeating in-lane mask.
9639 // First shuffle the lanes into place.
9640 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9641 VT.getSizeInBits() / 64);
9642 SmallVector<int, 8> LaneMask;
9643 LaneMask.resize(NumLanes * 2, -1);
9644 for (int i = 0; i < NumLanes; ++i)
9645 if (Lanes[i] >= 0) {
9646 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9647 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9650 V1 = DAG.getBitcast(LaneVT, V1);
9651 V2 = DAG.getBitcast(LaneVT, V2);
9652 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9654 // Cast it back to the type we actually want.
9655 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9657 // Now do a simple shuffle that isn't lane crossing.
9658 SmallVector<int, 8> NewMask;
9659 NewMask.resize(Size, -1);
9660 for (int i = 0; i < Size; ++i)
9662 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9663 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9664 "Must not introduce lane crosses at this point!");
9666 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9669 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9672 /// This returns true if the elements from a particular input are already in the
9673 /// slot required by the given mask and require no permutation.
9674 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9675 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9676 int Size = Mask.size();
9677 for (int i = 0; i < Size; ++i)
9678 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9684 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9685 ArrayRef<int> Mask, SDValue V1,
9686 SDValue V2, SelectionDAG &DAG) {
9688 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9689 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9690 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9691 int NumElts = VT.getVectorNumElements();
9692 bool ShufpdMask = true;
9693 bool CommutableMask = true;
9694 unsigned Immediate = 0;
9695 for (int i = 0; i < NumElts; ++i) {
9698 int Val = (i & 6) + NumElts * (i & 1);
9699 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9700 if (Mask[i] < Val || Mask[i] > Val + 1)
9702 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9703 CommutableMask = false;
9704 Immediate |= (Mask[i] % 2) << i;
9707 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9708 DAG.getConstant(Immediate, DL, MVT::i8));
9710 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9711 DAG.getConstant(Immediate, DL, MVT::i8));
9715 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9717 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9718 /// isn't available.
9719 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9720 const X86Subtarget *Subtarget,
9721 SelectionDAG &DAG) {
9723 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9724 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9725 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9726 ArrayRef<int> Mask = SVOp->getMask();
9727 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9729 SmallVector<int, 4> WidenedMask;
9730 if (canWidenShuffleElements(Mask, WidenedMask))
9731 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9734 if (isSingleInputShuffleMask(Mask)) {
9735 // Check for being able to broadcast a single element.
9736 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9737 Mask, Subtarget, DAG))
9740 // Use low duplicate instructions for masks that match their pattern.
9741 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9742 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9744 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9745 // Non-half-crossing single input shuffles can be lowerid with an
9746 // interleaved permutation.
9747 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9748 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9749 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9750 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9753 // With AVX2 we have direct support for this permutation.
9754 if (Subtarget->hasAVX2())
9755 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9756 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9758 // Otherwise, fall back.
9759 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9763 // X86 has dedicated unpack instructions that can handle specific blend
9764 // operations: UNPCKH and UNPCKL.
9765 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9766 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9767 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9768 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9769 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9770 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9771 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9772 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9774 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9778 // Check if the blend happens to exactly fit that of SHUFPD.
9780 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9783 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9784 // shuffle. However, if we have AVX2 and either inputs are already in place,
9785 // we will be able to shuffle even across lanes the other input in a single
9786 // instruction so skip this pattern.
9787 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9788 isShuffleMaskInputInPlace(1, Mask))))
9789 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9790 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9793 // If we have AVX2 then we always want to lower with a blend because an v4 we
9794 // can fully permute the elements.
9795 if (Subtarget->hasAVX2())
9796 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9799 // Otherwise fall back on generic lowering.
9800 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9803 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9805 /// This routine is only called when we have AVX2 and thus a reasonable
9806 /// instruction set for v4i64 shuffling..
9807 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9808 const X86Subtarget *Subtarget,
9809 SelectionDAG &DAG) {
9811 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9812 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9813 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9814 ArrayRef<int> Mask = SVOp->getMask();
9815 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9816 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9818 SmallVector<int, 4> WidenedMask;
9819 if (canWidenShuffleElements(Mask, WidenedMask))
9820 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9823 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9827 // Check for being able to broadcast a single element.
9828 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9829 Mask, Subtarget, DAG))
9832 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9833 // use lower latency instructions that will operate on both 128-bit lanes.
9834 SmallVector<int, 2> RepeatedMask;
9835 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9836 if (isSingleInputShuffleMask(Mask)) {
9837 int PSHUFDMask[] = {-1, -1, -1, -1};
9838 for (int i = 0; i < 2; ++i)
9839 if (RepeatedMask[i] >= 0) {
9840 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9841 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9843 return DAG.getBitcast(
9845 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9846 DAG.getBitcast(MVT::v8i32, V1),
9847 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9851 // AVX2 provides a direct instruction for permuting a single input across
9853 if (isSingleInputShuffleMask(Mask))
9854 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9855 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9857 // Try to use shift instructions.
9859 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9862 // Use dedicated unpack instructions for masks that match their pattern.
9863 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9864 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9865 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9866 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9867 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9868 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9869 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9870 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9872 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9873 // shuffle. However, if we have AVX2 and either inputs are already in place,
9874 // we will be able to shuffle even across lanes the other input in a single
9875 // instruction so skip this pattern.
9876 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9877 isShuffleMaskInputInPlace(1, Mask))))
9878 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9879 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9882 // Otherwise fall back on generic blend lowering.
9883 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9887 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9889 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9890 /// isn't available.
9891 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9892 const X86Subtarget *Subtarget,
9893 SelectionDAG &DAG) {
9895 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9896 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9897 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9898 ArrayRef<int> Mask = SVOp->getMask();
9899 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9901 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9905 // Check for being able to broadcast a single element.
9906 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9907 Mask, Subtarget, DAG))
9910 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9911 // options to efficiently lower the shuffle.
9912 SmallVector<int, 4> RepeatedMask;
9913 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9914 assert(RepeatedMask.size() == 4 &&
9915 "Repeated masks must be half the mask width!");
9917 // Use even/odd duplicate instructions for masks that match their pattern.
9918 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9919 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9920 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9921 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9923 if (isSingleInputShuffleMask(Mask))
9924 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9925 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9927 // Use dedicated unpack instructions for masks that match their pattern.
9928 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9929 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9930 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9931 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9932 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9933 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9934 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9935 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9937 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9938 // have already handled any direct blends. We also need to squash the
9939 // repeated mask into a simulated v4f32 mask.
9940 for (int i = 0; i < 4; ++i)
9941 if (RepeatedMask[i] >= 8)
9942 RepeatedMask[i] -= 4;
9943 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9946 // If we have a single input shuffle with different shuffle patterns in the
9947 // two 128-bit lanes use the variable mask to VPERMILPS.
9948 if (isSingleInputShuffleMask(Mask)) {
9949 SDValue VPermMask[8];
9950 for (int i = 0; i < 8; ++i)
9951 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9952 : DAG.getConstant(Mask[i], DL, MVT::i32);
9953 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9955 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9956 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9958 if (Subtarget->hasAVX2())
9960 X86ISD::VPERMV, DL, MVT::v8f32,
9961 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
9962 MVT::v8i32, VPermMask)),
9965 // Otherwise, fall back.
9966 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9970 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9972 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9973 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9976 // If we have AVX2 then we always want to lower with a blend because at v8 we
9977 // can fully permute the elements.
9978 if (Subtarget->hasAVX2())
9979 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9982 // Otherwise fall back on generic lowering.
9983 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9986 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9988 /// This routine is only called when we have AVX2 and thus a reasonable
9989 /// instruction set for v8i32 shuffling..
9990 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9991 const X86Subtarget *Subtarget,
9992 SelectionDAG &DAG) {
9994 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9995 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9997 ArrayRef<int> Mask = SVOp->getMask();
9998 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9999 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10001 // Whenever we can lower this as a zext, that instruction is strictly faster
10002 // than any alternative. It also allows us to fold memory operands into the
10003 // shuffle in many cases.
10004 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10005 Mask, Subtarget, DAG))
10008 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10012 // Check for being able to broadcast a single element.
10013 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10014 Mask, Subtarget, DAG))
10017 // If the shuffle mask is repeated in each 128-bit lane we can use more
10018 // efficient instructions that mirror the shuffles across the two 128-bit
10020 SmallVector<int, 4> RepeatedMask;
10021 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10022 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10023 if (isSingleInputShuffleMask(Mask))
10024 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10025 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10027 // Use dedicated unpack instructions for masks that match their pattern.
10028 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10029 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10030 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10031 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10032 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10033 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10034 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10035 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10038 // Try to use shift instructions.
10039 if (SDValue Shift =
10040 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10043 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10044 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10047 // If the shuffle patterns aren't repeated but it is a single input, directly
10048 // generate a cross-lane VPERMD instruction.
10049 if (isSingleInputShuffleMask(Mask)) {
10050 SDValue VPermMask[8];
10051 for (int i = 0; i < 8; ++i)
10052 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10053 : DAG.getConstant(Mask[i], DL, MVT::i32);
10054 return DAG.getNode(
10055 X86ISD::VPERMV, DL, MVT::v8i32,
10056 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10059 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10061 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10062 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10065 // Otherwise fall back on generic blend lowering.
10066 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10070 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10072 /// This routine is only called when we have AVX2 and thus a reasonable
10073 /// instruction set for v16i16 shuffling..
10074 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10075 const X86Subtarget *Subtarget,
10076 SelectionDAG &DAG) {
10078 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10079 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10080 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10081 ArrayRef<int> Mask = SVOp->getMask();
10082 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10083 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10085 // Whenever we can lower this as a zext, that instruction is strictly faster
10086 // than any alternative. It also allows us to fold memory operands into the
10087 // shuffle in many cases.
10088 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10089 Mask, Subtarget, DAG))
10092 // Check for being able to broadcast a single element.
10093 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10094 Mask, Subtarget, DAG))
10097 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10101 // Use dedicated unpack instructions for masks that match their pattern.
10102 if (isShuffleEquivalent(V1, V2, Mask,
10103 {// First 128-bit lane:
10104 0, 16, 1, 17, 2, 18, 3, 19,
10105 // Second 128-bit lane:
10106 8, 24, 9, 25, 10, 26, 11, 27}))
10107 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10108 if (isShuffleEquivalent(V1, V2, Mask,
10109 {// First 128-bit lane:
10110 4, 20, 5, 21, 6, 22, 7, 23,
10111 // Second 128-bit lane:
10112 12, 28, 13, 29, 14, 30, 15, 31}))
10113 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10115 // Try to use shift instructions.
10116 if (SDValue Shift =
10117 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10120 // Try to use byte rotation instructions.
10121 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10122 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10125 if (isSingleInputShuffleMask(Mask)) {
10126 // There are no generalized cross-lane shuffle operations available on i16
10128 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10129 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10132 SmallVector<int, 8> RepeatedMask;
10133 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10134 // As this is a single-input shuffle, the repeated mask should be
10135 // a strictly valid v8i16 mask that we can pass through to the v8i16
10136 // lowering to handle even the v16 case.
10137 return lowerV8I16GeneralSingleInputVectorShuffle(
10138 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10141 SDValue PSHUFBMask[32];
10142 for (int i = 0; i < 16; ++i) {
10143 if (Mask[i] == -1) {
10144 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10148 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10149 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10150 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10151 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10153 return DAG.getBitcast(MVT::v16i16,
10154 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10155 DAG.getBitcast(MVT::v32i8, V1),
10156 DAG.getNode(ISD::BUILD_VECTOR, DL,
10157 MVT::v32i8, PSHUFBMask)));
10160 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10162 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10163 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10166 // Otherwise fall back on generic lowering.
10167 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10170 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10172 /// This routine is only called when we have AVX2 and thus a reasonable
10173 /// instruction set for v32i8 shuffling..
10174 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10175 const X86Subtarget *Subtarget,
10176 SelectionDAG &DAG) {
10178 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10179 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10181 ArrayRef<int> Mask = SVOp->getMask();
10182 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10183 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10185 // Whenever we can lower this as a zext, that instruction is strictly faster
10186 // than any alternative. It also allows us to fold memory operands into the
10187 // shuffle in many cases.
10188 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10189 Mask, Subtarget, DAG))
10192 // Check for being able to broadcast a single element.
10193 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10194 Mask, Subtarget, DAG))
10197 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10201 // Use dedicated unpack instructions for masks that match their pattern.
10202 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10204 if (isShuffleEquivalent(
10206 {// First 128-bit lane:
10207 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10208 // Second 128-bit lane:
10209 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10210 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10211 if (isShuffleEquivalent(
10213 {// First 128-bit lane:
10214 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10215 // Second 128-bit lane:
10216 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10217 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10219 // Try to use shift instructions.
10220 if (SDValue Shift =
10221 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10224 // Try to use byte rotation instructions.
10225 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10226 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10229 if (isSingleInputShuffleMask(Mask)) {
10230 // There are no generalized cross-lane shuffle operations available on i8
10232 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10233 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10236 SDValue PSHUFBMask[32];
10237 for (int i = 0; i < 32; ++i)
10240 ? DAG.getUNDEF(MVT::i8)
10241 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10244 return DAG.getNode(
10245 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10246 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10249 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10251 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10252 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10255 // Otherwise fall back on generic lowering.
10256 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10259 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10261 /// This routine either breaks down the specific type of a 256-bit x86 vector
10262 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10263 /// together based on the available instructions.
10264 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10265 MVT VT, const X86Subtarget *Subtarget,
10266 SelectionDAG &DAG) {
10268 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10269 ArrayRef<int> Mask = SVOp->getMask();
10271 // If we have a single input to the zero element, insert that into V1 if we
10272 // can do so cheaply.
10273 int NumElts = VT.getVectorNumElements();
10274 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10275 return M >= NumElts;
10278 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10279 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10280 DL, VT, V1, V2, Mask, Subtarget, DAG))
10283 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10284 // check for those subtargets here and avoid much of the subtarget querying in
10285 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10286 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10287 // floating point types there eventually, just immediately cast everything to
10288 // a float and operate entirely in that domain.
10289 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10290 int ElementBits = VT.getScalarSizeInBits();
10291 if (ElementBits < 32)
10292 // No floating point type available, decompose into 128-bit vectors.
10293 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10295 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10296 VT.getVectorNumElements());
10297 V1 = DAG.getBitcast(FpVT, V1);
10298 V2 = DAG.getBitcast(FpVT, V2);
10299 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10302 switch (VT.SimpleTy) {
10304 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10306 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10308 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10310 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10312 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10314 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10317 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10321 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10322 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10323 const X86Subtarget *Subtarget,
10324 SelectionDAG &DAG) {
10326 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10327 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10328 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10329 ArrayRef<int> Mask = SVOp->getMask();
10330 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10332 // X86 has dedicated unpack instructions that can handle specific blend
10333 // operations: UNPCKH and UNPCKL.
10334 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10335 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10336 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10337 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10339 // FIXME: Implement direct support for this type!
10340 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10343 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10344 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10345 const X86Subtarget *Subtarget,
10346 SelectionDAG &DAG) {
10348 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10349 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10350 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10351 ArrayRef<int> Mask = SVOp->getMask();
10352 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10354 // Use dedicated unpack instructions for masks that match their pattern.
10355 if (isShuffleEquivalent(V1, V2, Mask,
10356 {// First 128-bit lane.
10357 0, 16, 1, 17, 4, 20, 5, 21,
10358 // Second 128-bit lane.
10359 8, 24, 9, 25, 12, 28, 13, 29}))
10360 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10361 if (isShuffleEquivalent(V1, V2, Mask,
10362 {// First 128-bit lane.
10363 2, 18, 3, 19, 6, 22, 7, 23,
10364 // Second 128-bit lane.
10365 10, 26, 11, 27, 14, 30, 15, 31}))
10366 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10368 // FIXME: Implement direct support for this type!
10369 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10372 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10373 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10374 const X86Subtarget *Subtarget,
10375 SelectionDAG &DAG) {
10377 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10378 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10380 ArrayRef<int> Mask = SVOp->getMask();
10381 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10383 // X86 has dedicated unpack instructions that can handle specific blend
10384 // operations: UNPCKH and UNPCKL.
10385 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10386 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10387 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10388 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10390 // FIXME: Implement direct support for this type!
10391 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10394 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10395 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10396 const X86Subtarget *Subtarget,
10397 SelectionDAG &DAG) {
10399 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10400 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10401 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10402 ArrayRef<int> Mask = SVOp->getMask();
10403 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10405 // Use dedicated unpack instructions for masks that match their pattern.
10406 if (isShuffleEquivalent(V1, V2, Mask,
10407 {// First 128-bit lane.
10408 0, 16, 1, 17, 4, 20, 5, 21,
10409 // Second 128-bit lane.
10410 8, 24, 9, 25, 12, 28, 13, 29}))
10411 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10412 if (isShuffleEquivalent(V1, V2, Mask,
10413 {// First 128-bit lane.
10414 2, 18, 3, 19, 6, 22, 7, 23,
10415 // Second 128-bit lane.
10416 10, 26, 11, 27, 14, 30, 15, 31}))
10417 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10419 // FIXME: Implement direct support for this type!
10420 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10423 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10424 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10425 const X86Subtarget *Subtarget,
10426 SelectionDAG &DAG) {
10428 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10429 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10430 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10431 ArrayRef<int> Mask = SVOp->getMask();
10432 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10433 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10435 // FIXME: Implement direct support for this type!
10436 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10439 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10440 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10441 const X86Subtarget *Subtarget,
10442 SelectionDAG &DAG) {
10444 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10445 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10446 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10447 ArrayRef<int> Mask = SVOp->getMask();
10448 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10449 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10451 // FIXME: Implement direct support for this type!
10452 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10455 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10457 /// This routine either breaks down the specific type of a 512-bit x86 vector
10458 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10459 /// together based on the available instructions.
10460 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10461 MVT VT, const X86Subtarget *Subtarget,
10462 SelectionDAG &DAG) {
10464 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10465 ArrayRef<int> Mask = SVOp->getMask();
10466 assert(Subtarget->hasAVX512() &&
10467 "Cannot lower 512-bit vectors w/ basic ISA!");
10469 // Check for being able to broadcast a single element.
10470 if (SDValue Broadcast =
10471 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10474 // Dispatch to each element type for lowering. If we don't have supprot for
10475 // specific element type shuffles at 512 bits, immediately split them and
10476 // lower them. Each lowering routine of a given type is allowed to assume that
10477 // the requisite ISA extensions for that element type are available.
10478 switch (VT.SimpleTy) {
10480 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10482 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10484 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10486 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10488 if (Subtarget->hasBWI())
10489 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10492 if (Subtarget->hasBWI())
10493 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10497 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10500 // Otherwise fall back on splitting.
10501 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10504 /// \brief Top-level lowering for x86 vector shuffles.
10506 /// This handles decomposition, canonicalization, and lowering of all x86
10507 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10508 /// above in helper routines. The canonicalization attempts to widen shuffles
10509 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10510 /// s.t. only one of the two inputs needs to be tested, etc.
10511 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10512 SelectionDAG &DAG) {
10513 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10514 ArrayRef<int> Mask = SVOp->getMask();
10515 SDValue V1 = Op.getOperand(0);
10516 SDValue V2 = Op.getOperand(1);
10517 MVT VT = Op.getSimpleValueType();
10518 int NumElements = VT.getVectorNumElements();
10521 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10523 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10524 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10525 if (V1IsUndef && V2IsUndef)
10526 return DAG.getUNDEF(VT);
10528 // When we create a shuffle node we put the UNDEF node to second operand,
10529 // but in some cases the first operand may be transformed to UNDEF.
10530 // In this case we should just commute the node.
10532 return DAG.getCommutedVectorShuffle(*SVOp);
10534 // Check for non-undef masks pointing at an undef vector and make the masks
10535 // undef as well. This makes it easier to match the shuffle based solely on
10539 if (M >= NumElements) {
10540 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10541 for (int &M : NewMask)
10542 if (M >= NumElements)
10544 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10547 // We actually see shuffles that are entirely re-arrangements of a set of
10548 // zero inputs. This mostly happens while decomposing complex shuffles into
10549 // simple ones. Directly lower these as a buildvector of zeros.
10550 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10551 if (Zeroable.all())
10552 return getZeroVector(VT, Subtarget, DAG, dl);
10554 // Try to collapse shuffles into using a vector type with fewer elements but
10555 // wider element types. We cap this to not form integers or floating point
10556 // elements wider than 64 bits, but it might be interesting to form i128
10557 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10558 SmallVector<int, 16> WidenedMask;
10559 if (VT.getScalarSizeInBits() < 64 &&
10560 canWidenShuffleElements(Mask, WidenedMask)) {
10561 MVT NewEltVT = VT.isFloatingPoint()
10562 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10563 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10564 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10565 // Make sure that the new vector type is legal. For example, v2f64 isn't
10567 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10568 V1 = DAG.getBitcast(NewVT, V1);
10569 V2 = DAG.getBitcast(NewVT, V2);
10570 return DAG.getBitcast(
10571 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10575 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10576 for (int M : SVOp->getMask())
10578 ++NumUndefElements;
10579 else if (M < NumElements)
10584 // Commute the shuffle as needed such that more elements come from V1 than
10585 // V2. This allows us to match the shuffle pattern strictly on how many
10586 // elements come from V1 without handling the symmetric cases.
10587 if (NumV2Elements > NumV1Elements)
10588 return DAG.getCommutedVectorShuffle(*SVOp);
10590 // When the number of V1 and V2 elements are the same, try to minimize the
10591 // number of uses of V2 in the low half of the vector. When that is tied,
10592 // ensure that the sum of indices for V1 is equal to or lower than the sum
10593 // indices for V2. When those are equal, try to ensure that the number of odd
10594 // indices for V1 is lower than the number of odd indices for V2.
10595 if (NumV1Elements == NumV2Elements) {
10596 int LowV1Elements = 0, LowV2Elements = 0;
10597 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10598 if (M >= NumElements)
10602 if (LowV2Elements > LowV1Elements) {
10603 return DAG.getCommutedVectorShuffle(*SVOp);
10604 } else if (LowV2Elements == LowV1Elements) {
10605 int SumV1Indices = 0, SumV2Indices = 0;
10606 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10607 if (SVOp->getMask()[i] >= NumElements)
10609 else if (SVOp->getMask()[i] >= 0)
10611 if (SumV2Indices < SumV1Indices) {
10612 return DAG.getCommutedVectorShuffle(*SVOp);
10613 } else if (SumV2Indices == SumV1Indices) {
10614 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10615 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10616 if (SVOp->getMask()[i] >= NumElements)
10617 NumV2OddIndices += i % 2;
10618 else if (SVOp->getMask()[i] >= 0)
10619 NumV1OddIndices += i % 2;
10620 if (NumV2OddIndices < NumV1OddIndices)
10621 return DAG.getCommutedVectorShuffle(*SVOp);
10626 // For each vector width, delegate to a specialized lowering routine.
10627 if (VT.getSizeInBits() == 128)
10628 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10630 if (VT.getSizeInBits() == 256)
10631 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10633 // Force AVX-512 vectors to be scalarized for now.
10634 // FIXME: Implement AVX-512 support!
10635 if (VT.getSizeInBits() == 512)
10636 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10638 llvm_unreachable("Unimplemented!");
10641 // This function assumes its argument is a BUILD_VECTOR of constants or
10642 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10644 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10645 unsigned &MaskValue) {
10647 unsigned NumElems = BuildVector->getNumOperands();
10648 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10649 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10650 unsigned NumElemsInLane = NumElems / NumLanes;
10652 // Blend for v16i16 should be symetric for the both lanes.
10653 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10654 SDValue EltCond = BuildVector->getOperand(i);
10655 SDValue SndLaneEltCond =
10656 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10658 int Lane1Cond = -1, Lane2Cond = -1;
10659 if (isa<ConstantSDNode>(EltCond))
10660 Lane1Cond = !isZero(EltCond);
10661 if (isa<ConstantSDNode>(SndLaneEltCond))
10662 Lane2Cond = !isZero(SndLaneEltCond);
10664 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10665 // Lane1Cond != 0, means we want the first argument.
10666 // Lane1Cond == 0, means we want the second argument.
10667 // The encoding of this argument is 0 for the first argument, 1
10668 // for the second. Therefore, invert the condition.
10669 MaskValue |= !Lane1Cond << i;
10670 else if (Lane1Cond < 0)
10671 MaskValue |= !Lane2Cond << i;
10678 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10679 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10680 const X86Subtarget *Subtarget,
10681 SelectionDAG &DAG) {
10682 SDValue Cond = Op.getOperand(0);
10683 SDValue LHS = Op.getOperand(1);
10684 SDValue RHS = Op.getOperand(2);
10686 MVT VT = Op.getSimpleValueType();
10688 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10690 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10692 // Only non-legal VSELECTs reach this lowering, convert those into generic
10693 // shuffles and re-use the shuffle lowering path for blends.
10694 SmallVector<int, 32> Mask;
10695 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10696 SDValue CondElt = CondBV->getOperand(i);
10698 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10700 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10703 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10704 // A vselect where all conditions and data are constants can be optimized into
10705 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10706 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10707 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10708 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10711 // Try to lower this to a blend-style vector shuffle. This can handle all
10712 // constant condition cases.
10713 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10716 // Variable blends are only legal from SSE4.1 onward.
10717 if (!Subtarget->hasSSE41())
10720 // Only some types will be legal on some subtargets. If we can emit a legal
10721 // VSELECT-matching blend, return Op, and but if we need to expand, return
10723 switch (Op.getSimpleValueType().SimpleTy) {
10725 // Most of the vector types have blends past SSE4.1.
10729 // The byte blends for AVX vectors were introduced only in AVX2.
10730 if (Subtarget->hasAVX2())
10737 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10738 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10741 // FIXME: We should custom lower this by fixing the condition and using i8
10747 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10748 MVT VT = Op.getSimpleValueType();
10751 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10754 if (VT.getSizeInBits() == 8) {
10755 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10756 Op.getOperand(0), Op.getOperand(1));
10757 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10758 DAG.getValueType(VT));
10759 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10762 if (VT.getSizeInBits() == 16) {
10763 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10764 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10766 return DAG.getNode(
10767 ISD::TRUNCATE, dl, MVT::i16,
10768 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10769 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10770 Op.getOperand(1)));
10771 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10772 Op.getOperand(0), Op.getOperand(1));
10773 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10774 DAG.getValueType(VT));
10775 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10778 if (VT == MVT::f32) {
10779 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10780 // the result back to FR32 register. It's only worth matching if the
10781 // result has a single use which is a store or a bitcast to i32. And in
10782 // the case of a store, it's not worth it if the index is a constant 0,
10783 // because a MOVSSmr can be used instead, which is smaller and faster.
10784 if (!Op.hasOneUse())
10786 SDNode *User = *Op.getNode()->use_begin();
10787 if ((User->getOpcode() != ISD::STORE ||
10788 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10789 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10790 (User->getOpcode() != ISD::BITCAST ||
10791 User->getValueType(0) != MVT::i32))
10793 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10794 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10796 return DAG.getBitcast(MVT::f32, Extract);
10799 if (VT == MVT::i32 || VT == MVT::i64) {
10800 // ExtractPS/pextrq works with constant index.
10801 if (isa<ConstantSDNode>(Op.getOperand(1)))
10807 /// Extract one bit from mask vector, like v16i1 or v8i1.
10808 /// AVX-512 feature.
10810 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10811 SDValue Vec = Op.getOperand(0);
10813 MVT VecVT = Vec.getSimpleValueType();
10814 SDValue Idx = Op.getOperand(1);
10815 MVT EltVT = Op.getSimpleValueType();
10817 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10818 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10819 "Unexpected vector type in ExtractBitFromMaskVector");
10821 // variable index can't be handled in mask registers,
10822 // extend vector to VR512
10823 if (!isa<ConstantSDNode>(Idx)) {
10824 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10825 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10826 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10827 ExtVT.getVectorElementType(), Ext, Idx);
10828 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10831 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10832 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10833 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10834 rc = getRegClassFor(MVT::v16i1);
10835 unsigned MaxSift = rc->getSize()*8 - 1;
10836 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10837 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10838 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10839 DAG.getConstant(MaxSift, dl, MVT::i8));
10840 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10841 DAG.getIntPtrConstant(0, dl));
10845 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10846 SelectionDAG &DAG) const {
10848 SDValue Vec = Op.getOperand(0);
10849 MVT VecVT = Vec.getSimpleValueType();
10850 SDValue Idx = Op.getOperand(1);
10852 if (Op.getSimpleValueType() == MVT::i1)
10853 return ExtractBitFromMaskVector(Op, DAG);
10855 if (!isa<ConstantSDNode>(Idx)) {
10856 if (VecVT.is512BitVector() ||
10857 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10858 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10861 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10862 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10863 MaskEltVT.getSizeInBits());
10865 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10866 auto PtrVT = getPointerTy(DAG.getDataLayout());
10867 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10868 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
10869 DAG.getConstant(0, dl, PtrVT));
10870 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10871 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
10872 DAG.getConstant(0, dl, PtrVT));
10877 // If this is a 256-bit vector result, first extract the 128-bit vector and
10878 // then extract the element from the 128-bit vector.
10879 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10881 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10882 // Get the 128-bit vector.
10883 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10884 MVT EltVT = VecVT.getVectorElementType();
10886 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10888 //if (IdxVal >= NumElems/2)
10889 // IdxVal -= NumElems/2;
10890 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10891 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10892 DAG.getConstant(IdxVal, dl, MVT::i32));
10895 assert(VecVT.is128BitVector() && "Unexpected vector length");
10897 if (Subtarget->hasSSE41())
10898 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
10901 MVT VT = Op.getSimpleValueType();
10902 // TODO: handle v16i8.
10903 if (VT.getSizeInBits() == 16) {
10904 SDValue Vec = Op.getOperand(0);
10905 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10907 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10908 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10909 DAG.getBitcast(MVT::v4i32, Vec),
10910 Op.getOperand(1)));
10911 // Transform it so it match pextrw which produces a 32-bit result.
10912 MVT EltVT = MVT::i32;
10913 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10914 Op.getOperand(0), Op.getOperand(1));
10915 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10916 DAG.getValueType(VT));
10917 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10920 if (VT.getSizeInBits() == 32) {
10921 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10925 // SHUFPS the element to the lowest double word, then movss.
10926 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10927 MVT VVT = Op.getOperand(0).getSimpleValueType();
10928 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10929 DAG.getUNDEF(VVT), Mask);
10930 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10931 DAG.getIntPtrConstant(0, dl));
10934 if (VT.getSizeInBits() == 64) {
10935 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10936 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10937 // to match extract_elt for f64.
10938 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10942 // UNPCKHPD the element to the lowest double word, then movsd.
10943 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10944 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10945 int Mask[2] = { 1, -1 };
10946 MVT VVT = Op.getOperand(0).getSimpleValueType();
10947 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10948 DAG.getUNDEF(VVT), Mask);
10949 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10950 DAG.getIntPtrConstant(0, dl));
10956 /// Insert one bit to mask vector, like v16i1 or v8i1.
10957 /// AVX-512 feature.
10959 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10961 SDValue Vec = Op.getOperand(0);
10962 SDValue Elt = Op.getOperand(1);
10963 SDValue Idx = Op.getOperand(2);
10964 MVT VecVT = Vec.getSimpleValueType();
10966 if (!isa<ConstantSDNode>(Idx)) {
10967 // Non constant index. Extend source and destination,
10968 // insert element and then truncate the result.
10969 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10970 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10971 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10972 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10973 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10974 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10977 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10978 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10980 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10981 DAG.getConstant(IdxVal, dl, MVT::i8));
10982 if (Vec.getOpcode() == ISD::UNDEF)
10984 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10987 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10988 SelectionDAG &DAG) const {
10989 MVT VT = Op.getSimpleValueType();
10990 MVT EltVT = VT.getVectorElementType();
10992 if (EltVT == MVT::i1)
10993 return InsertBitToMaskVector(Op, DAG);
10996 SDValue N0 = Op.getOperand(0);
10997 SDValue N1 = Op.getOperand(1);
10998 SDValue N2 = Op.getOperand(2);
10999 if (!isa<ConstantSDNode>(N2))
11001 auto *N2C = cast<ConstantSDNode>(N2);
11002 unsigned IdxVal = N2C->getZExtValue();
11004 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11005 // into that, and then insert the subvector back into the result.
11006 if (VT.is256BitVector() || VT.is512BitVector()) {
11007 // With a 256-bit vector, we can insert into the zero element efficiently
11008 // using a blend if we have AVX or AVX2 and the right data type.
11009 if (VT.is256BitVector() && IdxVal == 0) {
11010 // TODO: It is worthwhile to cast integer to floating point and back
11011 // and incur a domain crossing penalty if that's what we'll end up
11012 // doing anyway after extracting to a 128-bit vector.
11013 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11014 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11015 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11016 N2 = DAG.getIntPtrConstant(1, dl);
11017 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11021 // Get the desired 128-bit vector chunk.
11022 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11024 // Insert the element into the desired chunk.
11025 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11026 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11028 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11029 DAG.getConstant(IdxIn128, dl, MVT::i32));
11031 // Insert the changed part back into the bigger vector
11032 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11034 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11036 if (Subtarget->hasSSE41()) {
11037 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11039 if (VT == MVT::v8i16) {
11040 Opc = X86ISD::PINSRW;
11042 assert(VT == MVT::v16i8);
11043 Opc = X86ISD::PINSRB;
11046 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11048 if (N1.getValueType() != MVT::i32)
11049 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11050 if (N2.getValueType() != MVT::i32)
11051 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11052 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11055 if (EltVT == MVT::f32) {
11056 // Bits [7:6] of the constant are the source select. This will always be
11057 // zero here. The DAG Combiner may combine an extract_elt index into
11058 // these bits. For example (insert (extract, 3), 2) could be matched by
11059 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11060 // Bits [5:4] of the constant are the destination select. This is the
11061 // value of the incoming immediate.
11062 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11063 // combine either bitwise AND or insert of float 0.0 to set these bits.
11065 const Function *F = DAG.getMachineFunction().getFunction();
11066 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
11067 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11068 // If this is an insertion of 32-bits into the low 32-bits of
11069 // a vector, we prefer to generate a blend with immediate rather
11070 // than an insertps. Blends are simpler operations in hardware and so
11071 // will always have equal or better performance than insertps.
11072 // But if optimizing for size and there's a load folding opportunity,
11073 // generate insertps because blendps does not have a 32-bit memory
11075 N2 = DAG.getIntPtrConstant(1, dl);
11076 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11077 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11079 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11080 // Create this as a scalar to vector..
11081 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11082 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11085 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11086 // PINSR* works with constant index.
11091 if (EltVT == MVT::i8)
11094 if (EltVT.getSizeInBits() == 16) {
11095 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11096 // as its second argument.
11097 if (N1.getValueType() != MVT::i32)
11098 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11099 if (N2.getValueType() != MVT::i32)
11100 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11101 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11106 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11108 MVT OpVT = Op.getSimpleValueType();
11110 // If this is a 256-bit vector result, first insert into a 128-bit
11111 // vector and then insert into the 256-bit vector.
11112 if (!OpVT.is128BitVector()) {
11113 // Insert into a 128-bit vector.
11114 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11115 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11116 OpVT.getVectorNumElements() / SizeFactor);
11118 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11120 // Insert the 128-bit vector.
11121 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11124 if (OpVT == MVT::v1i64 &&
11125 Op.getOperand(0).getValueType() == MVT::i64)
11126 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11128 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11129 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11130 return DAG.getBitcast(
11131 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11134 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11135 // a simple subregister reference or explicit instructions to grab
11136 // upper bits of a vector.
11137 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11138 SelectionDAG &DAG) {
11140 SDValue In = Op.getOperand(0);
11141 SDValue Idx = Op.getOperand(1);
11142 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11143 MVT ResVT = Op.getSimpleValueType();
11144 MVT InVT = In.getSimpleValueType();
11146 if (Subtarget->hasFp256()) {
11147 if (ResVT.is128BitVector() &&
11148 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11149 isa<ConstantSDNode>(Idx)) {
11150 return Extract128BitVector(In, IdxVal, DAG, dl);
11152 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11153 isa<ConstantSDNode>(Idx)) {
11154 return Extract256BitVector(In, IdxVal, DAG, dl);
11160 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11161 // simple superregister reference or explicit instructions to insert
11162 // the upper bits of a vector.
11163 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11164 SelectionDAG &DAG) {
11165 if (!Subtarget->hasAVX())
11169 SDValue Vec = Op.getOperand(0);
11170 SDValue SubVec = Op.getOperand(1);
11171 SDValue Idx = Op.getOperand(2);
11173 if (!isa<ConstantSDNode>(Idx))
11176 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11177 MVT OpVT = Op.getSimpleValueType();
11178 MVT SubVecVT = SubVec.getSimpleValueType();
11180 // Fold two 16-byte subvector loads into one 32-byte load:
11181 // (insert_subvector (insert_subvector undef, (load addr), 0),
11182 // (load addr + 16), Elts/2)
11184 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11185 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11186 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
11187 !Subtarget->isUnalignedMem32Slow()) {
11188 SDValue SubVec2 = Vec.getOperand(1);
11189 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
11190 if (Idx2->getZExtValue() == 0) {
11191 SDValue Ops[] = { SubVec2, SubVec };
11192 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11198 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11199 SubVecVT.is128BitVector())
11200 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11202 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11203 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11205 if (OpVT.getVectorElementType() == MVT::i1) {
11206 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11208 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11209 SDValue Undef = DAG.getUNDEF(OpVT);
11210 unsigned NumElems = OpVT.getVectorNumElements();
11211 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11213 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11214 // Zero upper bits of the Vec
11215 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11216 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11218 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11220 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11221 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11224 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11226 // Zero upper bits of the Vec2
11227 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11228 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11229 // Zero lower bits of the Vec
11230 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11231 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11232 // Merge them together
11233 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11239 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11240 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11241 // one of the above mentioned nodes. It has to be wrapped because otherwise
11242 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11243 // be used to form addressing mode. These wrapped nodes will be selected
11246 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11247 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11249 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11250 // global base reg.
11251 unsigned char OpFlag = 0;
11252 unsigned WrapperKind = X86ISD::Wrapper;
11253 CodeModel::Model M = DAG.getTarget().getCodeModel();
11255 if (Subtarget->isPICStyleRIPRel() &&
11256 (M == CodeModel::Small || M == CodeModel::Kernel))
11257 WrapperKind = X86ISD::WrapperRIP;
11258 else if (Subtarget->isPICStyleGOT())
11259 OpFlag = X86II::MO_GOTOFF;
11260 else if (Subtarget->isPICStyleStubPIC())
11261 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11263 auto PtrVT = getPointerTy(DAG.getDataLayout());
11264 SDValue Result = DAG.getTargetConstantPool(
11265 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11267 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11268 // With PIC, the address is actually $g + Offset.
11271 DAG.getNode(ISD::ADD, DL, PtrVT,
11272 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11278 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11279 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11281 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11282 // global base reg.
11283 unsigned char OpFlag = 0;
11284 unsigned WrapperKind = X86ISD::Wrapper;
11285 CodeModel::Model M = DAG.getTarget().getCodeModel();
11287 if (Subtarget->isPICStyleRIPRel() &&
11288 (M == CodeModel::Small || M == CodeModel::Kernel))
11289 WrapperKind = X86ISD::WrapperRIP;
11290 else if (Subtarget->isPICStyleGOT())
11291 OpFlag = X86II::MO_GOTOFF;
11292 else if (Subtarget->isPICStyleStubPIC())
11293 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11295 auto PtrVT = getPointerTy(DAG.getDataLayout());
11296 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11298 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11300 // With PIC, the address is actually $g + Offset.
11303 DAG.getNode(ISD::ADD, DL, PtrVT,
11304 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11310 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11311 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11313 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11314 // global base reg.
11315 unsigned char OpFlag = 0;
11316 unsigned WrapperKind = X86ISD::Wrapper;
11317 CodeModel::Model M = DAG.getTarget().getCodeModel();
11319 if (Subtarget->isPICStyleRIPRel() &&
11320 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11321 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11322 OpFlag = X86II::MO_GOTPCREL;
11323 WrapperKind = X86ISD::WrapperRIP;
11324 } else if (Subtarget->isPICStyleGOT()) {
11325 OpFlag = X86II::MO_GOT;
11326 } else if (Subtarget->isPICStyleStubPIC()) {
11327 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11328 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11329 OpFlag = X86II::MO_DARWIN_NONLAZY;
11332 auto PtrVT = getPointerTy(DAG.getDataLayout());
11333 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11336 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11338 // With PIC, the address is actually $g + Offset.
11339 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11340 !Subtarget->is64Bit()) {
11342 DAG.getNode(ISD::ADD, DL, PtrVT,
11343 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11346 // For symbols that require a load from a stub to get the address, emit the
11348 if (isGlobalStubReference(OpFlag))
11349 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11350 MachinePointerInfo::getGOT(), false, false, false, 0);
11356 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11357 // Create the TargetBlockAddressAddress node.
11358 unsigned char OpFlags =
11359 Subtarget->ClassifyBlockAddressReference();
11360 CodeModel::Model M = DAG.getTarget().getCodeModel();
11361 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11362 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11364 auto PtrVT = getPointerTy(DAG.getDataLayout());
11365 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11367 if (Subtarget->isPICStyleRIPRel() &&
11368 (M == CodeModel::Small || M == CodeModel::Kernel))
11369 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11371 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11373 // With PIC, the address is actually $g + Offset.
11374 if (isGlobalRelativeToPICBase(OpFlags)) {
11375 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11376 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11383 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11384 int64_t Offset, SelectionDAG &DAG) const {
11385 // Create the TargetGlobalAddress node, folding in the constant
11386 // offset if it is legal.
11387 unsigned char OpFlags =
11388 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11389 CodeModel::Model M = DAG.getTarget().getCodeModel();
11390 auto PtrVT = getPointerTy(DAG.getDataLayout());
11392 if (OpFlags == X86II::MO_NO_FLAG &&
11393 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11394 // A direct static reference to a global.
11395 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11398 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11401 if (Subtarget->isPICStyleRIPRel() &&
11402 (M == CodeModel::Small || M == CodeModel::Kernel))
11403 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11405 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11407 // With PIC, the address is actually $g + Offset.
11408 if (isGlobalRelativeToPICBase(OpFlags)) {
11409 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11410 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11413 // For globals that require a load from a stub to get the address, emit the
11415 if (isGlobalStubReference(OpFlags))
11416 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11417 MachinePointerInfo::getGOT(), false, false, false, 0);
11419 // If there was a non-zero offset that we didn't fold, create an explicit
11420 // addition for it.
11422 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11423 DAG.getConstant(Offset, dl, PtrVT));
11429 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11430 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11431 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11432 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11436 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11437 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11438 unsigned char OperandFlags, bool LocalDynamic = false) {
11439 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11440 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11442 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11443 GA->getValueType(0),
11447 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11451 SDValue Ops[] = { Chain, TGA, *InFlag };
11452 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11454 SDValue Ops[] = { Chain, TGA };
11455 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11458 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11459 MFI->setAdjustsStack(true);
11460 MFI->setHasCalls(true);
11462 SDValue Flag = Chain.getValue(1);
11463 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11466 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11468 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11471 SDLoc dl(GA); // ? function entry point might be better
11472 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11473 DAG.getNode(X86ISD::GlobalBaseReg,
11474 SDLoc(), PtrVT), InFlag);
11475 InFlag = Chain.getValue(1);
11477 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11480 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11482 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11484 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11485 X86::RAX, X86II::MO_TLSGD);
11488 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11494 // Get the start address of the TLS block for this module.
11495 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11496 .getInfo<X86MachineFunctionInfo>();
11497 MFI->incNumLocalDynamicTLSAccesses();
11501 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11502 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11505 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11506 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11507 InFlag = Chain.getValue(1);
11508 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11509 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11512 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11516 unsigned char OperandFlags = X86II::MO_DTPOFF;
11517 unsigned WrapperKind = X86ISD::Wrapper;
11518 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11519 GA->getValueType(0),
11520 GA->getOffset(), OperandFlags);
11521 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11523 // Add x@dtpoff with the base.
11524 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11527 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11528 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11529 const EVT PtrVT, TLSModel::Model model,
11530 bool is64Bit, bool isPIC) {
11533 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11534 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11535 is64Bit ? 257 : 256));
11537 SDValue ThreadPointer =
11538 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11539 MachinePointerInfo(Ptr), false, false, false, 0);
11541 unsigned char OperandFlags = 0;
11542 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11544 unsigned WrapperKind = X86ISD::Wrapper;
11545 if (model == TLSModel::LocalExec) {
11546 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11547 } else if (model == TLSModel::InitialExec) {
11549 OperandFlags = X86II::MO_GOTTPOFF;
11550 WrapperKind = X86ISD::WrapperRIP;
11552 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11555 llvm_unreachable("Unexpected model");
11558 // emit "addl x@ntpoff,%eax" (local exec)
11559 // or "addl x@indntpoff,%eax" (initial exec)
11560 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11562 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11563 GA->getOffset(), OperandFlags);
11564 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11566 if (model == TLSModel::InitialExec) {
11567 if (isPIC && !is64Bit) {
11568 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11569 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11573 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11574 MachinePointerInfo::getGOT(), false, false, false, 0);
11577 // The address of the thread local variable is the add of the thread
11578 // pointer with the offset of the variable.
11579 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11583 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11585 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11586 const GlobalValue *GV = GA->getGlobal();
11587 auto PtrVT = getPointerTy(DAG.getDataLayout());
11589 if (Subtarget->isTargetELF()) {
11590 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11592 case TLSModel::GeneralDynamic:
11593 if (Subtarget->is64Bit())
11594 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
11595 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
11596 case TLSModel::LocalDynamic:
11597 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
11598 Subtarget->is64Bit());
11599 case TLSModel::InitialExec:
11600 case TLSModel::LocalExec:
11601 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
11602 DAG.getTarget().getRelocationModel() ==
11605 llvm_unreachable("Unknown TLS model.");
11608 if (Subtarget->isTargetDarwin()) {
11609 // Darwin only has one model of TLS. Lower to that.
11610 unsigned char OpFlag = 0;
11611 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11612 X86ISD::WrapperRIP : X86ISD::Wrapper;
11614 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11615 // global base reg.
11616 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11617 !Subtarget->is64Bit();
11619 OpFlag = X86II::MO_TLVP_PIC_BASE;
11621 OpFlag = X86II::MO_TLVP;
11623 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11624 GA->getValueType(0),
11625 GA->getOffset(), OpFlag);
11626 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11628 // With PIC32, the address is actually $g + Offset.
11630 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
11631 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11634 // Lowering the machine isd will make sure everything is in the right
11636 SDValue Chain = DAG.getEntryNode();
11637 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11638 SDValue Args[] = { Chain, Offset };
11639 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11641 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11642 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11643 MFI->setAdjustsStack(true);
11645 // And our return value (tls address) is in the standard call return value
11647 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11648 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
11651 if (Subtarget->isTargetKnownWindowsMSVC() ||
11652 Subtarget->isTargetWindowsGNU()) {
11653 // Just use the implicit TLS architecture
11654 // Need to generate someting similar to:
11655 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11657 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11658 // mov rcx, qword [rdx+rcx*8]
11659 // mov eax, .tls$:tlsvar
11660 // [rax+rcx] contains the address
11661 // Windows 64bit: gs:0x58
11662 // Windows 32bit: fs:__tls_array
11665 SDValue Chain = DAG.getEntryNode();
11667 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11668 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11669 // use its literal value of 0x2C.
11670 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11671 ? Type::getInt8PtrTy(*DAG.getContext(),
11673 : Type::getInt32PtrTy(*DAG.getContext(),
11676 SDValue TlsArray = Subtarget->is64Bit()
11677 ? DAG.getIntPtrConstant(0x58, dl)
11678 : (Subtarget->isTargetWindowsGNU()
11679 ? DAG.getIntPtrConstant(0x2C, dl)
11680 : DAG.getExternalSymbol("_tls_array", PtrVT));
11682 SDValue ThreadPointer =
11683 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
11687 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11688 res = ThreadPointer;
11690 // Load the _tls_index variable
11691 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
11692 if (Subtarget->is64Bit())
11693 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
11694 MachinePointerInfo(), MVT::i32, false, false,
11697 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
11700 auto &DL = DAG.getDataLayout();
11702 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
11703 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
11705 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
11708 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
11711 // Get the offset of start of .tls section
11712 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11713 GA->getValueType(0),
11714 GA->getOffset(), X86II::MO_SECREL);
11715 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
11717 // The address of the thread local variable is the add of the thread
11718 // pointer with the offset of the variable.
11719 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
11722 llvm_unreachable("TLS not implemented for this target.");
11725 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11726 /// and take a 2 x i32 value to shift plus a shift amount.
11727 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11728 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11729 MVT VT = Op.getSimpleValueType();
11730 unsigned VTBits = VT.getSizeInBits();
11732 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11733 SDValue ShOpLo = Op.getOperand(0);
11734 SDValue ShOpHi = Op.getOperand(1);
11735 SDValue ShAmt = Op.getOperand(2);
11736 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11737 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11739 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11740 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11741 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11742 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11743 : DAG.getConstant(0, dl, VT);
11745 SDValue Tmp2, Tmp3;
11746 if (Op.getOpcode() == ISD::SHL_PARTS) {
11747 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11748 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11750 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11751 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11754 // If the shift amount is larger or equal than the width of a part we can't
11755 // rely on the results of shld/shrd. Insert a test and select the appropriate
11756 // values for large shift amounts.
11757 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11758 DAG.getConstant(VTBits, dl, MVT::i8));
11759 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11760 AndNode, DAG.getConstant(0, dl, MVT::i8));
11763 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11764 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11765 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11767 if (Op.getOpcode() == ISD::SHL_PARTS) {
11768 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11769 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11771 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11772 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11775 SDValue Ops[2] = { Lo, Hi };
11776 return DAG.getMergeValues(Ops, dl);
11779 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11780 SelectionDAG &DAG) const {
11781 SDValue Src = Op.getOperand(0);
11782 MVT SrcVT = Src.getSimpleValueType();
11783 MVT VT = Op.getSimpleValueType();
11786 if (SrcVT.isVector()) {
11787 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
11788 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
11789 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
11790 DAG.getUNDEF(SrcVT)));
11792 if (SrcVT.getVectorElementType() == MVT::i1) {
11793 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11794 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11795 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
11800 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11801 "Unknown SINT_TO_FP to lower!");
11803 // These are really Legal; return the operand so the caller accepts it as
11805 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11807 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11808 Subtarget->is64Bit()) {
11812 unsigned Size = SrcVT.getSizeInBits()/8;
11813 MachineFunction &MF = DAG.getMachineFunction();
11814 auto PtrVT = getPointerTy(MF.getDataLayout());
11815 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11816 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
11817 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11819 MachinePointerInfo::getFixedStack(SSFI),
11821 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11824 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11826 SelectionDAG &DAG) const {
11830 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11832 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11834 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11836 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11838 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11839 MachineMemOperand *MMO;
11841 int SSFI = FI->getIndex();
11843 DAG.getMachineFunction()
11844 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11845 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11847 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11848 StackSlot = StackSlot.getOperand(1);
11850 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11851 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11853 Tys, Ops, SrcVT, MMO);
11856 Chain = Result.getValue(1);
11857 SDValue InFlag = Result.getValue(2);
11859 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11860 // shouldn't be necessary except that RFP cannot be live across
11861 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11862 MachineFunction &MF = DAG.getMachineFunction();
11863 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11864 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11865 auto PtrVT = getPointerTy(MF.getDataLayout());
11866 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
11867 Tys = DAG.getVTList(MVT::Other);
11869 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11871 MachineMemOperand *MMO =
11872 DAG.getMachineFunction()
11873 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11874 MachineMemOperand::MOStore, SSFISize, SSFISize);
11876 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11877 Ops, Op.getValueType(), MMO);
11878 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11879 MachinePointerInfo::getFixedStack(SSFI),
11880 false, false, false, 0);
11886 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11887 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11888 SelectionDAG &DAG) const {
11889 // This algorithm is not obvious. Here it is what we're trying to output:
11892 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11893 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11895 haddpd %xmm0, %xmm0
11897 pshufd $0x4e, %xmm0, %xmm1
11903 LLVMContext *Context = DAG.getContext();
11905 // Build some magic constants.
11906 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11907 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11908 auto PtrVT = getPointerTy(DAG.getDataLayout());
11909 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
11911 SmallVector<Constant*,2> CV1;
11913 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11914 APInt(64, 0x4330000000000000ULL))));
11916 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11917 APInt(64, 0x4530000000000000ULL))));
11918 Constant *C1 = ConstantVector::get(CV1);
11919 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
11921 // Load the 64-bit value into an XMM register.
11922 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11924 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11925 MachinePointerInfo::getConstantPool(),
11926 false, false, false, 16);
11928 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
11930 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11931 MachinePointerInfo::getConstantPool(),
11932 false, false, false, 16);
11933 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
11934 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11937 if (Subtarget->hasSSE3()) {
11938 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11939 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11941 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
11942 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11944 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11945 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
11948 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11949 DAG.getIntPtrConstant(0, dl));
11952 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11953 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11954 SelectionDAG &DAG) const {
11956 // FP constant to bias correct the final result.
11957 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11960 // Load the 32-bit value into an XMM register.
11961 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11964 // Zero out the upper parts of the register.
11965 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11967 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11968 DAG.getBitcast(MVT::v2f64, Load),
11969 DAG.getIntPtrConstant(0, dl));
11971 // Or the load with the bias.
11972 SDValue Or = DAG.getNode(
11973 ISD::OR, dl, MVT::v2i64,
11974 DAG.getBitcast(MVT::v2i64,
11975 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
11976 DAG.getBitcast(MVT::v2i64,
11977 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
11979 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11980 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
11982 // Subtract the bias.
11983 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11985 // Handle final rounding.
11986 EVT DestVT = Op.getValueType();
11988 if (DestVT.bitsLT(MVT::f64))
11989 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11990 DAG.getIntPtrConstant(0, dl));
11991 if (DestVT.bitsGT(MVT::f64))
11992 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11994 // Handle final rounding.
11998 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11999 const X86Subtarget &Subtarget) {
12000 // The algorithm is the following:
12001 // #ifdef __SSE4_1__
12002 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12003 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12004 // (uint4) 0x53000000, 0xaa);
12006 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12007 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12009 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12010 // return (float4) lo + fhi;
12013 SDValue V = Op->getOperand(0);
12014 EVT VecIntVT = V.getValueType();
12015 bool Is128 = VecIntVT == MVT::v4i32;
12016 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12017 // If we convert to something else than the supported type, e.g., to v4f64,
12019 if (VecFloatVT != Op->getValueType(0))
12022 unsigned NumElts = VecIntVT.getVectorNumElements();
12023 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12024 "Unsupported custom type");
12025 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12027 // In the #idef/#else code, we have in common:
12028 // - The vector of constants:
12034 // Create the splat vector for 0x4b000000.
12035 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12036 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12037 CstLow, CstLow, CstLow, CstLow};
12038 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12039 makeArrayRef(&CstLowArray[0], NumElts));
12040 // Create the splat vector for 0x53000000.
12041 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12042 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12043 CstHigh, CstHigh, CstHigh, CstHigh};
12044 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12045 makeArrayRef(&CstHighArray[0], NumElts));
12047 // Create the right shift.
12048 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12049 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12050 CstShift, CstShift, CstShift, CstShift};
12051 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12052 makeArrayRef(&CstShiftArray[0], NumElts));
12053 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12056 if (Subtarget.hasSSE41()) {
12057 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12058 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12059 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12060 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12061 // Low will be bitcasted right away, so do not bother bitcasting back to its
12063 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12064 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12065 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12066 // (uint4) 0x53000000, 0xaa);
12067 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12068 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12069 // High will be bitcasted right away, so do not bother bitcasting back to
12070 // its original type.
12071 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12072 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12074 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12075 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12076 CstMask, CstMask, CstMask);
12077 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12078 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12079 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12081 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12082 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12085 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12086 SDValue CstFAdd = DAG.getConstantFP(
12087 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12088 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12089 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12090 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12091 makeArrayRef(&CstFAddArray[0], NumElts));
12093 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12094 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12096 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12097 // return (float4) lo + fhi;
12098 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12099 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12102 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12103 SelectionDAG &DAG) const {
12104 SDValue N0 = Op.getOperand(0);
12105 MVT SVT = N0.getSimpleValueType();
12108 switch (SVT.SimpleTy) {
12110 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12115 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12116 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12117 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12121 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12124 if (Subtarget->hasAVX512())
12125 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12126 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12128 llvm_unreachable(nullptr);
12131 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12132 SelectionDAG &DAG) const {
12133 SDValue N0 = Op.getOperand(0);
12135 auto PtrVT = getPointerTy(DAG.getDataLayout());
12137 if (Op.getValueType().isVector())
12138 return lowerUINT_TO_FP_vec(Op, DAG);
12140 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12141 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12142 // the optimization here.
12143 if (DAG.SignBitIsZero(N0))
12144 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12146 MVT SrcVT = N0.getSimpleValueType();
12147 MVT DstVT = Op.getSimpleValueType();
12148 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12149 return LowerUINT_TO_FP_i64(Op, DAG);
12150 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12151 return LowerUINT_TO_FP_i32(Op, DAG);
12152 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12155 // Make a 64-bit buffer, and use it to build an FILD.
12156 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12157 if (SrcVT == MVT::i32) {
12158 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12159 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12160 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12161 StackSlot, MachinePointerInfo(),
12163 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12164 OffsetSlot, MachinePointerInfo(),
12166 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12170 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12171 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12172 StackSlot, MachinePointerInfo(),
12174 // For i64 source, we need to add the appropriate power of 2 if the input
12175 // was negative. This is the same as the optimization in
12176 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12177 // we must be careful to do the computation in x87 extended precision, not
12178 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12179 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12180 MachineMemOperand *MMO =
12181 DAG.getMachineFunction()
12182 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12183 MachineMemOperand::MOLoad, 8, 8);
12185 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12186 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12187 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12190 APInt FF(32, 0x5F800000ULL);
12192 // Check whether the sign bit is set.
12193 SDValue SignSet = DAG.getSetCC(
12194 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12195 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12197 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12198 SDValue FudgePtr = DAG.getConstantPool(
12199 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12201 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12202 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12203 SDValue Four = DAG.getIntPtrConstant(4, dl);
12204 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12206 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12208 // Load the value out, extending it from f32 to f80.
12209 // FIXME: Avoid the extend by constructing the right constant pool?
12210 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12211 FudgePtr, MachinePointerInfo::getConstantPool(),
12212 MVT::f32, false, false, false, 4);
12213 // Extend everything to 80 bits to force it to be done on x87.
12214 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12215 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12216 DAG.getIntPtrConstant(0, dl));
12219 std::pair<SDValue,SDValue>
12220 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12221 bool IsSigned, bool IsReplace) const {
12224 EVT DstTy = Op.getValueType();
12225 auto PtrVT = getPointerTy(DAG.getDataLayout());
12227 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12228 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12232 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12233 DstTy.getSimpleVT() >= MVT::i16 &&
12234 "Unknown FP_TO_INT to lower!");
12236 // These are really Legal.
12237 if (DstTy == MVT::i32 &&
12238 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12239 return std::make_pair(SDValue(), SDValue());
12240 if (Subtarget->is64Bit() &&
12241 DstTy == MVT::i64 &&
12242 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12243 return std::make_pair(SDValue(), SDValue());
12245 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12246 // stack slot, or into the FTOL runtime function.
12247 MachineFunction &MF = DAG.getMachineFunction();
12248 unsigned MemSize = DstTy.getSizeInBits()/8;
12249 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12250 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12253 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12254 Opc = X86ISD::WIN_FTOL;
12256 switch (DstTy.getSimpleVT().SimpleTy) {
12257 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12258 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12259 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12260 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12263 SDValue Chain = DAG.getEntryNode();
12264 SDValue Value = Op.getOperand(0);
12265 EVT TheVT = Op.getOperand(0).getValueType();
12266 // FIXME This causes a redundant load/store if the SSE-class value is already
12267 // in memory, such as if it is on the callstack.
12268 if (isScalarFPTypeInSSEReg(TheVT)) {
12269 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12270 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12271 MachinePointerInfo::getFixedStack(SSFI),
12273 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12275 Chain, StackSlot, DAG.getValueType(TheVT)
12278 MachineMemOperand *MMO =
12279 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12280 MachineMemOperand::MOLoad, MemSize, MemSize);
12281 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12282 Chain = Value.getValue(1);
12283 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12284 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12287 MachineMemOperand *MMO =
12288 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12289 MachineMemOperand::MOStore, MemSize, MemSize);
12291 if (Opc != X86ISD::WIN_FTOL) {
12292 // Build the FP_TO_INT*_IN_MEM
12293 SDValue Ops[] = { Chain, Value, StackSlot };
12294 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12296 return std::make_pair(FIST, StackSlot);
12298 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12299 DAG.getVTList(MVT::Other, MVT::Glue),
12301 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12302 MVT::i32, ftol.getValue(1));
12303 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12304 MVT::i32, eax.getValue(2));
12305 SDValue Ops[] = { eax, edx };
12306 SDValue pair = IsReplace
12307 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12308 : DAG.getMergeValues(Ops, DL);
12309 return std::make_pair(pair, SDValue());
12313 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12314 const X86Subtarget *Subtarget) {
12315 MVT VT = Op->getSimpleValueType(0);
12316 SDValue In = Op->getOperand(0);
12317 MVT InVT = In.getSimpleValueType();
12320 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12321 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12323 // Optimize vectors in AVX mode:
12326 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12327 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12328 // Concat upper and lower parts.
12331 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12332 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12333 // Concat upper and lower parts.
12336 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12337 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12338 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12341 if (Subtarget->hasInt256())
12342 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12344 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12345 SDValue Undef = DAG.getUNDEF(InVT);
12346 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12347 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12348 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12350 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12351 VT.getVectorNumElements()/2);
12353 OpLo = DAG.getBitcast(HVT, OpLo);
12354 OpHi = DAG.getBitcast(HVT, OpHi);
12356 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12359 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12360 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12361 MVT VT = Op->getSimpleValueType(0);
12362 SDValue In = Op->getOperand(0);
12363 MVT InVT = In.getSimpleValueType();
12365 unsigned int NumElts = VT.getVectorNumElements();
12366 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12369 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12370 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12372 assert(InVT.getVectorElementType() == MVT::i1);
12373 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12375 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12377 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12379 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12380 if (VT.is512BitVector())
12382 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12385 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12386 SelectionDAG &DAG) {
12387 if (Subtarget->hasFp256())
12388 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12394 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12395 SelectionDAG &DAG) {
12397 MVT VT = Op.getSimpleValueType();
12398 SDValue In = Op.getOperand(0);
12399 MVT SVT = In.getSimpleValueType();
12401 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12402 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12404 if (Subtarget->hasFp256())
12405 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12408 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12409 VT.getVectorNumElements() != SVT.getVectorNumElements());
12413 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12415 MVT VT = Op.getSimpleValueType();
12416 SDValue In = Op.getOperand(0);
12417 MVT InVT = In.getSimpleValueType();
12419 if (VT == MVT::i1) {
12420 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12421 "Invalid scalar TRUNCATE operation");
12422 if (InVT.getSizeInBits() >= 32)
12424 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12425 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12427 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12428 "Invalid TRUNCATE operation");
12430 // move vector to mask - truncate solution for SKX
12431 if (VT.getVectorElementType() == MVT::i1) {
12432 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12433 Subtarget->hasBWI())
12434 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12435 if ((InVT.is256BitVector() || InVT.is128BitVector())
12436 && InVT.getScalarSizeInBits() <= 16 &&
12437 Subtarget->hasBWI() && Subtarget->hasVLX())
12438 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12439 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12440 Subtarget->hasDQI())
12441 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12442 if ((InVT.is256BitVector() || InVT.is128BitVector())
12443 && InVT.getScalarSizeInBits() >= 32 &&
12444 Subtarget->hasDQI() && Subtarget->hasVLX())
12445 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12447 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12448 if (VT.getVectorElementType().getSizeInBits() >=8)
12449 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12451 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12452 unsigned NumElts = InVT.getVectorNumElements();
12453 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12454 if (InVT.getSizeInBits() < 512) {
12455 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12456 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12461 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12462 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12463 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12466 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12467 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12468 if (Subtarget->hasInt256()) {
12469 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12470 In = DAG.getBitcast(MVT::v8i32, In);
12471 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12473 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12474 DAG.getIntPtrConstant(0, DL));
12477 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12478 DAG.getIntPtrConstant(0, DL));
12479 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12480 DAG.getIntPtrConstant(2, DL));
12481 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12482 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12483 static const int ShufMask[] = {0, 2, 4, 6};
12484 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12487 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12488 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12489 if (Subtarget->hasInt256()) {
12490 In = DAG.getBitcast(MVT::v32i8, In);
12492 SmallVector<SDValue,32> pshufbMask;
12493 for (unsigned i = 0; i < 2; ++i) {
12494 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12495 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12496 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12497 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12498 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12499 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12500 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12501 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12502 for (unsigned j = 0; j < 8; ++j)
12503 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12505 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12506 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12507 In = DAG.getBitcast(MVT::v4i64, In);
12509 static const int ShufMask[] = {0, 2, -1, -1};
12510 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12512 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12513 DAG.getIntPtrConstant(0, DL));
12514 return DAG.getBitcast(VT, In);
12517 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12518 DAG.getIntPtrConstant(0, DL));
12520 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12521 DAG.getIntPtrConstant(4, DL));
12523 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12524 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12526 // The PSHUFB mask:
12527 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12528 -1, -1, -1, -1, -1, -1, -1, -1};
12530 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12531 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12532 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12534 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12535 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12537 // The MOVLHPS Mask:
12538 static const int ShufMask2[] = {0, 1, 4, 5};
12539 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12540 return DAG.getBitcast(MVT::v8i16, res);
12543 // Handle truncation of V256 to V128 using shuffles.
12544 if (!VT.is128BitVector() || !InVT.is256BitVector())
12547 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12549 unsigned NumElems = VT.getVectorNumElements();
12550 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12552 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12553 // Prepare truncation shuffle mask
12554 for (unsigned i = 0; i != NumElems; ++i)
12555 MaskVec[i] = i * 2;
12556 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12557 DAG.getUNDEF(NVT), &MaskVec[0]);
12558 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12559 DAG.getIntPtrConstant(0, DL));
12562 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12563 SelectionDAG &DAG) const {
12564 assert(!Op.getSimpleValueType().isVector());
12566 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12567 /*IsSigned=*/ true, /*IsReplace=*/ false);
12568 SDValue FIST = Vals.first, StackSlot = Vals.second;
12569 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12570 if (!FIST.getNode()) return Op;
12572 if (StackSlot.getNode())
12573 // Load the result.
12574 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12575 FIST, StackSlot, MachinePointerInfo(),
12576 false, false, false, 0);
12578 // The node is the result.
12582 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12583 SelectionDAG &DAG) const {
12584 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12585 /*IsSigned=*/ false, /*IsReplace=*/ false);
12586 SDValue FIST = Vals.first, StackSlot = Vals.second;
12587 assert(FIST.getNode() && "Unexpected failure");
12589 if (StackSlot.getNode())
12590 // Load the result.
12591 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12592 FIST, StackSlot, MachinePointerInfo(),
12593 false, false, false, 0);
12595 // The node is the result.
12599 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12601 MVT VT = Op.getSimpleValueType();
12602 SDValue In = Op.getOperand(0);
12603 MVT SVT = In.getSimpleValueType();
12605 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12607 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12608 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12609 In, DAG.getUNDEF(SVT)));
12612 /// The only differences between FABS and FNEG are the mask and the logic op.
12613 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12614 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12615 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12616 "Wrong opcode for lowering FABS or FNEG.");
12618 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12620 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12621 // into an FNABS. We'll lower the FABS after that if it is still in use.
12623 for (SDNode *User : Op->uses())
12624 if (User->getOpcode() == ISD::FNEG)
12627 SDValue Op0 = Op.getOperand(0);
12628 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12631 MVT VT = Op.getSimpleValueType();
12632 // Assume scalar op for initialization; update for vector if needed.
12633 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12634 // generate a 16-byte vector constant and logic op even for the scalar case.
12635 // Using a 16-byte mask allows folding the load of the mask with
12636 // the logic op, so it can save (~4 bytes) on code size.
12638 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12639 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12640 // decide if we should generate a 16-byte constant mask when we only need 4 or
12641 // 8 bytes for the scalar case.
12642 if (VT.isVector()) {
12643 EltVT = VT.getVectorElementType();
12644 NumElts = VT.getVectorNumElements();
12647 unsigned EltBits = EltVT.getSizeInBits();
12648 LLVMContext *Context = DAG.getContext();
12649 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12651 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12652 Constant *C = ConstantInt::get(*Context, MaskElt);
12653 C = ConstantVector::getSplat(NumElts, C);
12654 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12655 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
12656 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12657 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12658 MachinePointerInfo::getConstantPool(),
12659 false, false, false, Alignment);
12661 if (VT.isVector()) {
12662 // For a vector, cast operands to a vector type, perform the logic op,
12663 // and cast the result back to the original value type.
12664 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12665 SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);
12666 SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))
12667 : DAG.getBitcast(VecVT, Op0);
12668 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12669 return DAG.getBitcast(VT,
12670 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12673 // If not vector, then scalar.
12674 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12675 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12676 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12679 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12680 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12681 LLVMContext *Context = DAG.getContext();
12682 SDValue Op0 = Op.getOperand(0);
12683 SDValue Op1 = Op.getOperand(1);
12685 MVT VT = Op.getSimpleValueType();
12686 MVT SrcVT = Op1.getSimpleValueType();
12688 // If second operand is smaller, extend it first.
12689 if (SrcVT.bitsLT(VT)) {
12690 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12693 // And if it is bigger, shrink it first.
12694 if (SrcVT.bitsGT(VT)) {
12695 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12699 // At this point the operands and the result should have the same
12700 // type, and that won't be f80 since that is not custom lowered.
12702 const fltSemantics &Sem =
12703 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12704 const unsigned SizeInBits = VT.getSizeInBits();
12706 SmallVector<Constant *, 4> CV(
12707 VT == MVT::f64 ? 2 : 4,
12708 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12710 // First, clear all bits but the sign bit from the second operand (sign).
12711 CV[0] = ConstantFP::get(*Context,
12712 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12713 Constant *C = ConstantVector::get(CV);
12714 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
12715 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
12716 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12717 MachinePointerInfo::getConstantPool(),
12718 false, false, false, 16);
12719 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12721 // Next, clear the sign bit from the first operand (magnitude).
12722 // If it's a constant, we can clear it here.
12723 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12724 APFloat APF = Op0CN->getValueAPF();
12725 // If the magnitude is a positive zero, the sign bit alone is enough.
12726 if (APF.isPosZero())
12729 CV[0] = ConstantFP::get(*Context, APF);
12731 CV[0] = ConstantFP::get(
12733 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12735 C = ConstantVector::get(CV);
12736 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
12737 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12738 MachinePointerInfo::getConstantPool(),
12739 false, false, false, 16);
12740 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12741 if (!isa<ConstantFPSDNode>(Op0))
12742 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12744 // OR the magnitude value with the sign bit.
12745 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12748 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12749 SDValue N0 = Op.getOperand(0);
12751 MVT VT = Op.getSimpleValueType();
12753 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12754 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12755 DAG.getConstant(1, dl, VT));
12756 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12759 // Check whether an OR'd tree is PTEST-able.
12760 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12761 SelectionDAG &DAG) {
12762 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12764 if (!Subtarget->hasSSE41())
12767 if (!Op->hasOneUse())
12770 SDNode *N = Op.getNode();
12773 SmallVector<SDValue, 8> Opnds;
12774 DenseMap<SDValue, unsigned> VecInMap;
12775 SmallVector<SDValue, 8> VecIns;
12776 EVT VT = MVT::Other;
12778 // Recognize a special case where a vector is casted into wide integer to
12780 Opnds.push_back(N->getOperand(0));
12781 Opnds.push_back(N->getOperand(1));
12783 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12784 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12785 // BFS traverse all OR'd operands.
12786 if (I->getOpcode() == ISD::OR) {
12787 Opnds.push_back(I->getOperand(0));
12788 Opnds.push_back(I->getOperand(1));
12789 // Re-evaluate the number of nodes to be traversed.
12790 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12794 // Quit if a non-EXTRACT_VECTOR_ELT
12795 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12798 // Quit if without a constant index.
12799 SDValue Idx = I->getOperand(1);
12800 if (!isa<ConstantSDNode>(Idx))
12803 SDValue ExtractedFromVec = I->getOperand(0);
12804 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12805 if (M == VecInMap.end()) {
12806 VT = ExtractedFromVec.getValueType();
12807 // Quit if not 128/256-bit vector.
12808 if (!VT.is128BitVector() && !VT.is256BitVector())
12810 // Quit if not the same type.
12811 if (VecInMap.begin() != VecInMap.end() &&
12812 VT != VecInMap.begin()->first.getValueType())
12814 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12815 VecIns.push_back(ExtractedFromVec);
12817 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12820 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12821 "Not extracted from 128-/256-bit vector.");
12823 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12825 for (DenseMap<SDValue, unsigned>::const_iterator
12826 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12827 // Quit if not all elements are used.
12828 if (I->second != FullMask)
12832 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12834 // Cast all vectors into TestVT for PTEST.
12835 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12836 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12838 // If more than one full vectors are evaluated, OR them first before PTEST.
12839 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12840 // Each iteration will OR 2 nodes and append the result until there is only
12841 // 1 node left, i.e. the final OR'd value of all vectors.
12842 SDValue LHS = VecIns[Slot];
12843 SDValue RHS = VecIns[Slot + 1];
12844 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12847 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12848 VecIns.back(), VecIns.back());
12851 /// \brief return true if \c Op has a use that doesn't just read flags.
12852 static bool hasNonFlagsUse(SDValue Op) {
12853 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12855 SDNode *User = *UI;
12856 unsigned UOpNo = UI.getOperandNo();
12857 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12858 // Look pass truncate.
12859 UOpNo = User->use_begin().getOperandNo();
12860 User = *User->use_begin();
12863 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12864 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12870 /// Emit nodes that will be selected as "test Op0,Op0", or something
12872 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12873 SelectionDAG &DAG) const {
12874 if (Op.getValueType() == MVT::i1) {
12875 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12876 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12877 DAG.getConstant(0, dl, MVT::i8));
12879 // CF and OF aren't always set the way we want. Determine which
12880 // of these we need.
12881 bool NeedCF = false;
12882 bool NeedOF = false;
12885 case X86::COND_A: case X86::COND_AE:
12886 case X86::COND_B: case X86::COND_BE:
12889 case X86::COND_G: case X86::COND_GE:
12890 case X86::COND_L: case X86::COND_LE:
12891 case X86::COND_O: case X86::COND_NO: {
12892 // Check if we really need to set the
12893 // Overflow flag. If NoSignedWrap is present
12894 // that is not actually needed.
12895 switch (Op->getOpcode()) {
12900 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12901 if (BinNode->Flags.hasNoSignedWrap())
12911 // See if we can use the EFLAGS value from the operand instead of
12912 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12913 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12914 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12915 // Emit a CMP with 0, which is the TEST pattern.
12916 //if (Op.getValueType() == MVT::i1)
12917 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12918 // DAG.getConstant(0, MVT::i1));
12919 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12920 DAG.getConstant(0, dl, Op.getValueType()));
12922 unsigned Opcode = 0;
12923 unsigned NumOperands = 0;
12925 // Truncate operations may prevent the merge of the SETCC instruction
12926 // and the arithmetic instruction before it. Attempt to truncate the operands
12927 // of the arithmetic instruction and use a reduced bit-width instruction.
12928 bool NeedTruncation = false;
12929 SDValue ArithOp = Op;
12930 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12931 SDValue Arith = Op->getOperand(0);
12932 // Both the trunc and the arithmetic op need to have one user each.
12933 if (Arith->hasOneUse())
12934 switch (Arith.getOpcode()) {
12941 NeedTruncation = true;
12947 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12948 // which may be the result of a CAST. We use the variable 'Op', which is the
12949 // non-casted variable when we check for possible users.
12950 switch (ArithOp.getOpcode()) {
12952 // Due to an isel shortcoming, be conservative if this add is likely to be
12953 // selected as part of a load-modify-store instruction. When the root node
12954 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12955 // uses of other nodes in the match, such as the ADD in this case. This
12956 // leads to the ADD being left around and reselected, with the result being
12957 // two adds in the output. Alas, even if none our users are stores, that
12958 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12959 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12960 // climbing the DAG back to the root, and it doesn't seem to be worth the
12962 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12963 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12964 if (UI->getOpcode() != ISD::CopyToReg &&
12965 UI->getOpcode() != ISD::SETCC &&
12966 UI->getOpcode() != ISD::STORE)
12969 if (ConstantSDNode *C =
12970 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12971 // An add of one will be selected as an INC.
12972 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12973 Opcode = X86ISD::INC;
12978 // An add of negative one (subtract of one) will be selected as a DEC.
12979 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12980 Opcode = X86ISD::DEC;
12986 // Otherwise use a regular EFLAGS-setting add.
12987 Opcode = X86ISD::ADD;
12992 // If we have a constant logical shift that's only used in a comparison
12993 // against zero turn it into an equivalent AND. This allows turning it into
12994 // a TEST instruction later.
12995 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12996 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12997 EVT VT = Op.getValueType();
12998 unsigned BitWidth = VT.getSizeInBits();
12999 unsigned ShAmt = Op->getConstantOperandVal(1);
13000 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13002 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13003 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13004 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13005 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13007 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13008 DAG.getConstant(Mask, dl, VT));
13009 DAG.ReplaceAllUsesWith(Op, New);
13015 // If the primary and result isn't used, don't bother using X86ISD::AND,
13016 // because a TEST instruction will be better.
13017 if (!hasNonFlagsUse(Op))
13023 // Due to the ISEL shortcoming noted above, be conservative if this op is
13024 // likely to be selected as part of a load-modify-store instruction.
13025 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13026 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13027 if (UI->getOpcode() == ISD::STORE)
13030 // Otherwise use a regular EFLAGS-setting instruction.
13031 switch (ArithOp.getOpcode()) {
13032 default: llvm_unreachable("unexpected operator!");
13033 case ISD::SUB: Opcode = X86ISD::SUB; break;
13034 case ISD::XOR: Opcode = X86ISD::XOR; break;
13035 case ISD::AND: Opcode = X86ISD::AND; break;
13037 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13038 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13039 if (EFLAGS.getNode())
13042 Opcode = X86ISD::OR;
13056 return SDValue(Op.getNode(), 1);
13062 // If we found that truncation is beneficial, perform the truncation and
13064 if (NeedTruncation) {
13065 EVT VT = Op.getValueType();
13066 SDValue WideVal = Op->getOperand(0);
13067 EVT WideVT = WideVal.getValueType();
13068 unsigned ConvertedOp = 0;
13069 // Use a target machine opcode to prevent further DAGCombine
13070 // optimizations that may separate the arithmetic operations
13071 // from the setcc node.
13072 switch (WideVal.getOpcode()) {
13074 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13075 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13076 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13077 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13078 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13083 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13084 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13085 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13086 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13092 // Emit a CMP with 0, which is the TEST pattern.
13093 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13094 DAG.getConstant(0, dl, Op.getValueType()));
13096 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13097 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13099 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13100 DAG.ReplaceAllUsesWith(Op, New);
13101 return SDValue(New.getNode(), 1);
13104 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13106 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13107 SDLoc dl, SelectionDAG &DAG) const {
13108 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13109 if (C->getAPIntValue() == 0)
13110 return EmitTest(Op0, X86CC, dl, DAG);
13112 if (Op0.getValueType() == MVT::i1)
13113 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13116 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13117 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13118 // Do the comparison at i32 if it's smaller, besides the Atom case.
13119 // This avoids subregister aliasing issues. Keep the smaller reference
13120 // if we're optimizing for size, however, as that'll allow better folding
13121 // of memory operations.
13122 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13123 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
13124 Attribute::MinSize) &&
13125 !Subtarget->isAtom()) {
13126 unsigned ExtendOp =
13127 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13128 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13129 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13131 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13132 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13133 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13135 return SDValue(Sub.getNode(), 1);
13137 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13140 /// Convert a comparison if required by the subtarget.
13141 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13142 SelectionDAG &DAG) const {
13143 // If the subtarget does not support the FUCOMI instruction, floating-point
13144 // comparisons have to be converted.
13145 if (Subtarget->hasCMov() ||
13146 Cmp.getOpcode() != X86ISD::CMP ||
13147 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13148 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13151 // The instruction selector will select an FUCOM instruction instead of
13152 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13153 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13154 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13156 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13157 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13158 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13159 DAG.getConstant(8, dl, MVT::i8));
13160 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13161 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13164 /// The minimum architected relative accuracy is 2^-12. We need one
13165 /// Newton-Raphson step to have a good float result (24 bits of precision).
13166 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13167 DAGCombinerInfo &DCI,
13168 unsigned &RefinementSteps,
13169 bool &UseOneConstNR) const {
13170 EVT VT = Op.getValueType();
13171 const char *RecipOp;
13173 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13174 // TODO: Add support for AVX512 (v16f32).
13175 // It is likely not profitable to do this for f64 because a double-precision
13176 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13177 // instructions: convert to single, rsqrtss, convert back to double, refine
13178 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13179 // along with FMA, this could be a throughput win.
13180 if (VT == MVT::f32 && Subtarget->hasSSE1())
13182 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13183 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13184 RecipOp = "vec-sqrtf";
13188 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13189 if (!Recips.isEnabled(RecipOp))
13192 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13193 UseOneConstNR = false;
13194 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13197 /// The minimum architected relative accuracy is 2^-12. We need one
13198 /// Newton-Raphson step to have a good float result (24 bits of precision).
13199 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13200 DAGCombinerInfo &DCI,
13201 unsigned &RefinementSteps) const {
13202 EVT VT = Op.getValueType();
13203 const char *RecipOp;
13205 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13206 // TODO: Add support for AVX512 (v16f32).
13207 // It is likely not profitable to do this for f64 because a double-precision
13208 // reciprocal estimate with refinement on x86 prior to FMA requires
13209 // 15 instructions: convert to single, rcpss, convert back to double, refine
13210 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13211 // along with FMA, this could be a throughput win.
13212 if (VT == MVT::f32 && Subtarget->hasSSE1())
13214 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13215 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13216 RecipOp = "vec-divf";
13220 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13221 if (!Recips.isEnabled(RecipOp))
13224 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13225 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13228 /// If we have at least two divisions that use the same divisor, convert to
13229 /// multplication by a reciprocal. This may need to be adjusted for a given
13230 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13231 /// This is because we still need one division to calculate the reciprocal and
13232 /// then we need two multiplies by that reciprocal as replacements for the
13233 /// original divisions.
13234 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
13235 return NumUsers > 1;
13238 static bool isAllOnes(SDValue V) {
13239 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13240 return C && C->isAllOnesValue();
13243 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13244 /// if it's possible.
13245 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13246 SDLoc dl, SelectionDAG &DAG) const {
13247 SDValue Op0 = And.getOperand(0);
13248 SDValue Op1 = And.getOperand(1);
13249 if (Op0.getOpcode() == ISD::TRUNCATE)
13250 Op0 = Op0.getOperand(0);
13251 if (Op1.getOpcode() == ISD::TRUNCATE)
13252 Op1 = Op1.getOperand(0);
13255 if (Op1.getOpcode() == ISD::SHL)
13256 std::swap(Op0, Op1);
13257 if (Op0.getOpcode() == ISD::SHL) {
13258 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13259 if (And00C->getZExtValue() == 1) {
13260 // If we looked past a truncate, check that it's only truncating away
13262 unsigned BitWidth = Op0.getValueSizeInBits();
13263 unsigned AndBitWidth = And.getValueSizeInBits();
13264 if (BitWidth > AndBitWidth) {
13266 DAG.computeKnownBits(Op0, Zeros, Ones);
13267 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13271 RHS = Op0.getOperand(1);
13273 } else if (Op1.getOpcode() == ISD::Constant) {
13274 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13275 uint64_t AndRHSVal = AndRHS->getZExtValue();
13276 SDValue AndLHS = Op0;
13278 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13279 LHS = AndLHS.getOperand(0);
13280 RHS = AndLHS.getOperand(1);
13283 // Use BT if the immediate can't be encoded in a TEST instruction.
13284 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13286 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13290 if (LHS.getNode()) {
13291 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13292 // instruction. Since the shift amount is in-range-or-undefined, we know
13293 // that doing a bittest on the i32 value is ok. We extend to i32 because
13294 // the encoding for the i16 version is larger than the i32 version.
13295 // Also promote i16 to i32 for performance / code size reason.
13296 if (LHS.getValueType() == MVT::i8 ||
13297 LHS.getValueType() == MVT::i16)
13298 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13300 // If the operand types disagree, extend the shift amount to match. Since
13301 // BT ignores high bits (like shifts) we can use anyextend.
13302 if (LHS.getValueType() != RHS.getValueType())
13303 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13305 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13306 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13307 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13308 DAG.getConstant(Cond, dl, MVT::i8), BT);
13314 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13316 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13321 // SSE Condition code mapping:
13330 switch (SetCCOpcode) {
13331 default: llvm_unreachable("Unexpected SETCC condition");
13333 case ISD::SETEQ: SSECC = 0; break;
13335 case ISD::SETGT: Swap = true; // Fallthrough
13337 case ISD::SETOLT: SSECC = 1; break;
13339 case ISD::SETGE: Swap = true; // Fallthrough
13341 case ISD::SETOLE: SSECC = 2; break;
13342 case ISD::SETUO: SSECC = 3; break;
13344 case ISD::SETNE: SSECC = 4; break;
13345 case ISD::SETULE: Swap = true; // Fallthrough
13346 case ISD::SETUGE: SSECC = 5; break;
13347 case ISD::SETULT: Swap = true; // Fallthrough
13348 case ISD::SETUGT: SSECC = 6; break;
13349 case ISD::SETO: SSECC = 7; break;
13351 case ISD::SETONE: SSECC = 8; break;
13354 std::swap(Op0, Op1);
13359 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13360 // ones, and then concatenate the result back.
13361 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13362 MVT VT = Op.getSimpleValueType();
13364 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13365 "Unsupported value type for operation");
13367 unsigned NumElems = VT.getVectorNumElements();
13369 SDValue CC = Op.getOperand(2);
13371 // Extract the LHS vectors
13372 SDValue LHS = Op.getOperand(0);
13373 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13374 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13376 // Extract the RHS vectors
13377 SDValue RHS = Op.getOperand(1);
13378 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13379 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13381 // Issue the operation on the smaller types and concatenate the result back
13382 MVT EltVT = VT.getVectorElementType();
13383 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13384 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13385 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13386 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13389 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13390 SDValue Op0 = Op.getOperand(0);
13391 SDValue Op1 = Op.getOperand(1);
13392 SDValue CC = Op.getOperand(2);
13393 MVT VT = Op.getSimpleValueType();
13396 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13397 "Unexpected type for boolean compare operation");
13398 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13399 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13400 DAG.getConstant(-1, dl, VT));
13401 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13402 DAG.getConstant(-1, dl, VT));
13403 switch (SetCCOpcode) {
13404 default: llvm_unreachable("Unexpected SETCC condition");
13406 // (x == y) -> ~(x ^ y)
13407 return DAG.getNode(ISD::XOR, dl, VT,
13408 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13409 DAG.getConstant(-1, dl, VT));
13411 // (x != y) -> (x ^ y)
13412 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13415 // (x > y) -> (x & ~y)
13416 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13419 // (x < y) -> (~x & y)
13420 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13423 // (x <= y) -> (~x | y)
13424 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13427 // (x >=y) -> (x | ~y)
13428 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13432 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13433 const X86Subtarget *Subtarget) {
13434 SDValue Op0 = Op.getOperand(0);
13435 SDValue Op1 = Op.getOperand(1);
13436 SDValue CC = Op.getOperand(2);
13437 MVT VT = Op.getSimpleValueType();
13440 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13441 Op.getValueType().getScalarType() == MVT::i1 &&
13442 "Cannot set masked compare for this operation");
13444 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13446 bool Unsigned = false;
13449 switch (SetCCOpcode) {
13450 default: llvm_unreachable("Unexpected SETCC condition");
13451 case ISD::SETNE: SSECC = 4; break;
13452 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13453 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13454 case ISD::SETLT: Swap = true; //fall-through
13455 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13456 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13457 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13458 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13459 case ISD::SETULE: Unsigned = true; //fall-through
13460 case ISD::SETLE: SSECC = 2; break;
13464 std::swap(Op0, Op1);
13466 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13467 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13468 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13469 DAG.getConstant(SSECC, dl, MVT::i8));
13472 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13473 /// operand \p Op1. If non-trivial (for example because it's not constant)
13474 /// return an empty value.
13475 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13477 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13481 MVT VT = Op1.getSimpleValueType();
13482 MVT EVT = VT.getVectorElementType();
13483 unsigned n = VT.getVectorNumElements();
13484 SmallVector<SDValue, 8> ULTOp1;
13486 for (unsigned i = 0; i < n; ++i) {
13487 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13488 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13491 // Avoid underflow.
13492 APInt Val = Elt->getAPIntValue();
13496 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13499 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13502 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13503 SelectionDAG &DAG) {
13504 SDValue Op0 = Op.getOperand(0);
13505 SDValue Op1 = Op.getOperand(1);
13506 SDValue CC = Op.getOperand(2);
13507 MVT VT = Op.getSimpleValueType();
13508 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13509 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13514 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13515 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13518 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13519 unsigned Opc = X86ISD::CMPP;
13520 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13521 assert(VT.getVectorNumElements() <= 16);
13522 Opc = X86ISD::CMPM;
13524 // In the two special cases we can't handle, emit two comparisons.
13527 unsigned CombineOpc;
13528 if (SetCCOpcode == ISD::SETUEQ) {
13529 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13531 assert(SetCCOpcode == ISD::SETONE);
13532 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13535 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13536 DAG.getConstant(CC0, dl, MVT::i8));
13537 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13538 DAG.getConstant(CC1, dl, MVT::i8));
13539 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13541 // Handle all other FP comparisons here.
13542 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13543 DAG.getConstant(SSECC, dl, MVT::i8));
13546 // Break 256-bit integer vector compare into smaller ones.
13547 if (VT.is256BitVector() && !Subtarget->hasInt256())
13548 return Lower256IntVSETCC(Op, DAG);
13550 EVT OpVT = Op1.getValueType();
13551 if (OpVT.getVectorElementType() == MVT::i1)
13552 return LowerBoolVSETCC_AVX512(Op, DAG);
13554 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13555 if (Subtarget->hasAVX512()) {
13556 if (Op1.getValueType().is512BitVector() ||
13557 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13558 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13559 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13561 // In AVX-512 architecture setcc returns mask with i1 elements,
13562 // But there is no compare instruction for i8 and i16 elements in KNL.
13563 // We are not talking about 512-bit operands in this case, these
13564 // types are illegal.
13566 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13567 OpVT.getVectorElementType().getSizeInBits() >= 8))
13568 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13569 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13572 // We are handling one of the integer comparisons here. Since SSE only has
13573 // GT and EQ comparisons for integer, swapping operands and multiple
13574 // operations may be required for some comparisons.
13576 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13577 bool Subus = false;
13579 switch (SetCCOpcode) {
13580 default: llvm_unreachable("Unexpected SETCC condition");
13581 case ISD::SETNE: Invert = true;
13582 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13583 case ISD::SETLT: Swap = true;
13584 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13585 case ISD::SETGE: Swap = true;
13586 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13587 Invert = true; break;
13588 case ISD::SETULT: Swap = true;
13589 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13590 FlipSigns = true; break;
13591 case ISD::SETUGE: Swap = true;
13592 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13593 FlipSigns = true; Invert = true; break;
13596 // Special case: Use min/max operations for SETULE/SETUGE
13597 MVT VET = VT.getVectorElementType();
13599 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13600 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13603 switch (SetCCOpcode) {
13605 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
13606 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
13609 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13612 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13613 if (!MinMax && hasSubus) {
13614 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13616 // t = psubus Op0, Op1
13617 // pcmpeq t, <0..0>
13618 switch (SetCCOpcode) {
13620 case ISD::SETULT: {
13621 // If the comparison is against a constant we can turn this into a
13622 // setule. With psubus, setule does not require a swap. This is
13623 // beneficial because the constant in the register is no longer
13624 // destructed as the destination so it can be hoisted out of a loop.
13625 // Only do this pre-AVX since vpcmp* is no longer destructive.
13626 if (Subtarget->hasAVX())
13628 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13629 if (ULEOp1.getNode()) {
13631 Subus = true; Invert = false; Swap = false;
13635 // Psubus is better than flip-sign because it requires no inversion.
13636 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13637 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13641 Opc = X86ISD::SUBUS;
13647 std::swap(Op0, Op1);
13649 // Check that the operation in question is available (most are plain SSE2,
13650 // but PCMPGTQ and PCMPEQQ have different requirements).
13651 if (VT == MVT::v2i64) {
13652 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13653 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13655 // First cast everything to the right type.
13656 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13657 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13659 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13660 // bits of the inputs before performing those operations. The lower
13661 // compare is always unsigned.
13664 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13666 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13667 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13668 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13669 Sign, Zero, Sign, Zero);
13671 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13672 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13674 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13675 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13676 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13678 // Create masks for only the low parts/high parts of the 64 bit integers.
13679 static const int MaskHi[] = { 1, 1, 3, 3 };
13680 static const int MaskLo[] = { 0, 0, 2, 2 };
13681 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13682 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13683 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13685 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13686 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13689 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13691 return DAG.getBitcast(VT, Result);
13694 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13695 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13696 // pcmpeqd + pshufd + pand.
13697 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13699 // First cast everything to the right type.
13700 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13701 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13704 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13706 // Make sure the lower and upper halves are both all-ones.
13707 static const int Mask[] = { 1, 0, 3, 2 };
13708 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13709 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13712 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13714 return DAG.getBitcast(VT, Result);
13718 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13719 // bits of the inputs before performing those operations.
13721 EVT EltVT = VT.getVectorElementType();
13722 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13724 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13725 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13728 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13730 // If the logical-not of the result is required, perform that now.
13732 Result = DAG.getNOT(dl, Result, VT);
13735 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13738 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13739 getZeroVector(VT, Subtarget, DAG, dl));
13744 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13746 MVT VT = Op.getSimpleValueType();
13748 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13750 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13751 && "SetCC type must be 8-bit or 1-bit integer");
13752 SDValue Op0 = Op.getOperand(0);
13753 SDValue Op1 = Op.getOperand(1);
13755 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13757 // Optimize to BT if possible.
13758 // Lower (X & (1 << N)) == 0 to BT(X, N).
13759 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13760 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13761 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13762 Op1.getOpcode() == ISD::Constant &&
13763 cast<ConstantSDNode>(Op1)->isNullValue() &&
13764 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13765 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13766 if (NewSetCC.getNode()) {
13768 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13773 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13775 if (Op1.getOpcode() == ISD::Constant &&
13776 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13777 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13778 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13780 // If the input is a setcc, then reuse the input setcc or use a new one with
13781 // the inverted condition.
13782 if (Op0.getOpcode() == X86ISD::SETCC) {
13783 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13784 bool Invert = (CC == ISD::SETNE) ^
13785 cast<ConstantSDNode>(Op1)->isNullValue();
13789 CCode = X86::GetOppositeBranchCondition(CCode);
13790 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13791 DAG.getConstant(CCode, dl, MVT::i8),
13792 Op0.getOperand(1));
13794 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13798 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13799 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13800 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13802 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13803 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13806 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13807 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13808 if (X86CC == X86::COND_INVALID)
13811 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13812 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13813 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13814 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13816 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13820 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13821 static bool isX86LogicalCmp(SDValue Op) {
13822 unsigned Opc = Op.getNode()->getOpcode();
13823 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13824 Opc == X86ISD::SAHF)
13826 if (Op.getResNo() == 1 &&
13827 (Opc == X86ISD::ADD ||
13828 Opc == X86ISD::SUB ||
13829 Opc == X86ISD::ADC ||
13830 Opc == X86ISD::SBB ||
13831 Opc == X86ISD::SMUL ||
13832 Opc == X86ISD::UMUL ||
13833 Opc == X86ISD::INC ||
13834 Opc == X86ISD::DEC ||
13835 Opc == X86ISD::OR ||
13836 Opc == X86ISD::XOR ||
13837 Opc == X86ISD::AND))
13840 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13846 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13847 if (V.getOpcode() != ISD::TRUNCATE)
13850 SDValue VOp0 = V.getOperand(0);
13851 unsigned InBits = VOp0.getValueSizeInBits();
13852 unsigned Bits = V.getValueSizeInBits();
13853 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13856 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13857 bool addTest = true;
13858 SDValue Cond = Op.getOperand(0);
13859 SDValue Op1 = Op.getOperand(1);
13860 SDValue Op2 = Op.getOperand(2);
13862 EVT VT = Op1.getValueType();
13865 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13866 // are available or VBLENDV if AVX is available.
13867 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13868 if (Cond.getOpcode() == ISD::SETCC &&
13869 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13870 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13871 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13872 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13873 int SSECC = translateX86FSETCC(
13874 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13877 if (Subtarget->hasAVX512()) {
13878 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13879 DAG.getConstant(SSECC, DL, MVT::i8));
13880 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13883 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13884 DAG.getConstant(SSECC, DL, MVT::i8));
13886 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13887 // of 3 logic instructions for size savings and potentially speed.
13888 // Unfortunately, there is no scalar form of VBLENDV.
13890 // If either operand is a constant, don't try this. We can expect to
13891 // optimize away at least one of the logic instructions later in that
13892 // case, so that sequence would be faster than a variable blend.
13894 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13895 // uses XMM0 as the selection register. That may need just as many
13896 // instructions as the AND/ANDN/OR sequence due to register moves, so
13899 if (Subtarget->hasAVX() &&
13900 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13902 // Convert to vectors, do a VSELECT, and convert back to scalar.
13903 // All of the conversions should be optimized away.
13905 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13906 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13907 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13908 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13910 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13911 VCmp = DAG.getBitcast(VCmpVT, VCmp);
13913 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13915 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13916 VSel, DAG.getIntPtrConstant(0, DL));
13918 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13919 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13920 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13924 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13926 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13927 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13928 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13929 Op1Scalar = Op1.getOperand(0);
13931 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13932 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13933 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13934 Op2Scalar = Op2.getOperand(0);
13935 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13936 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13937 Op1Scalar.getValueType(),
13938 Cond, Op1Scalar, Op2Scalar);
13939 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13940 return DAG.getBitcast(VT, newSelect);
13941 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
13942 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13943 DAG.getIntPtrConstant(0, DL));
13947 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13948 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13949 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13950 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13951 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13952 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13953 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13955 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13958 if (Cond.getOpcode() == ISD::SETCC) {
13959 SDValue NewCond = LowerSETCC(Cond, DAG);
13960 if (NewCond.getNode())
13964 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13965 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13966 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13967 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13968 if (Cond.getOpcode() == X86ISD::SETCC &&
13969 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13970 isZero(Cond.getOperand(1).getOperand(1))) {
13971 SDValue Cmp = Cond.getOperand(1);
13973 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13975 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13976 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13977 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13979 SDValue CmpOp0 = Cmp.getOperand(0);
13980 // Apply further optimizations for special cases
13981 // (select (x != 0), -1, 0) -> neg & sbb
13982 // (select (x == 0), 0, -1) -> neg & sbb
13983 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13984 if (YC->isNullValue() &&
13985 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13986 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13987 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13988 DAG.getConstant(0, DL,
13989 CmpOp0.getValueType()),
13991 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13992 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13993 SDValue(Neg.getNode(), 1));
13997 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13998 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13999 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14001 SDValue Res = // Res = 0 or -1.
14002 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14003 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14005 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14006 Res = DAG.getNOT(DL, Res, Res.getValueType());
14008 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14009 if (!N2C || !N2C->isNullValue())
14010 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14015 // Look past (and (setcc_carry (cmp ...)), 1).
14016 if (Cond.getOpcode() == ISD::AND &&
14017 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14018 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14019 if (C && C->getAPIntValue() == 1)
14020 Cond = Cond.getOperand(0);
14023 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14024 // setting operand in place of the X86ISD::SETCC.
14025 unsigned CondOpcode = Cond.getOpcode();
14026 if (CondOpcode == X86ISD::SETCC ||
14027 CondOpcode == X86ISD::SETCC_CARRY) {
14028 CC = Cond.getOperand(0);
14030 SDValue Cmp = Cond.getOperand(1);
14031 unsigned Opc = Cmp.getOpcode();
14032 MVT VT = Op.getSimpleValueType();
14034 bool IllegalFPCMov = false;
14035 if (VT.isFloatingPoint() && !VT.isVector() &&
14036 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14037 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14039 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14040 Opc == X86ISD::BT) { // FIXME
14044 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14045 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14046 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14047 Cond.getOperand(0).getValueType() != MVT::i8)) {
14048 SDValue LHS = Cond.getOperand(0);
14049 SDValue RHS = Cond.getOperand(1);
14050 unsigned X86Opcode;
14053 switch (CondOpcode) {
14054 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14055 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14056 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14057 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14058 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14059 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14060 default: llvm_unreachable("unexpected overflowing operator");
14062 if (CondOpcode == ISD::UMULO)
14063 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14066 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14068 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14070 if (CondOpcode == ISD::UMULO)
14071 Cond = X86Op.getValue(2);
14073 Cond = X86Op.getValue(1);
14075 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14080 // Look pass the truncate if the high bits are known zero.
14081 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14082 Cond = Cond.getOperand(0);
14084 // We know the result of AND is compared against zero. Try to match
14086 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14087 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14088 if (NewSetCC.getNode()) {
14089 CC = NewSetCC.getOperand(0);
14090 Cond = NewSetCC.getOperand(1);
14097 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14098 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14101 // a < b ? -1 : 0 -> RES = ~setcc_carry
14102 // a < b ? 0 : -1 -> RES = setcc_carry
14103 // a >= b ? -1 : 0 -> RES = setcc_carry
14104 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14105 if (Cond.getOpcode() == X86ISD::SUB) {
14106 Cond = ConvertCmpIfNecessary(Cond, DAG);
14107 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14109 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14110 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14111 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14112 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14114 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14115 return DAG.getNOT(DL, Res, Res.getValueType());
14120 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14121 // widen the cmov and push the truncate through. This avoids introducing a new
14122 // branch during isel and doesn't add any extensions.
14123 if (Op.getValueType() == MVT::i8 &&
14124 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14125 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14126 if (T1.getValueType() == T2.getValueType() &&
14127 // Blacklist CopyFromReg to avoid partial register stalls.
14128 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14129 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14130 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14131 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14135 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14136 // condition is true.
14137 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14138 SDValue Ops[] = { Op2, Op1, CC, Cond };
14139 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14142 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14143 const X86Subtarget *Subtarget,
14144 SelectionDAG &DAG) {
14145 MVT VT = Op->getSimpleValueType(0);
14146 SDValue In = Op->getOperand(0);
14147 MVT InVT = In.getSimpleValueType();
14148 MVT VTElt = VT.getVectorElementType();
14149 MVT InVTElt = InVT.getVectorElementType();
14153 if ((InVTElt == MVT::i1) &&
14154 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14155 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14157 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14158 VTElt.getSizeInBits() <= 16)) ||
14160 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14161 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14163 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14164 VTElt.getSizeInBits() >= 32))))
14165 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14167 unsigned int NumElts = VT.getVectorNumElements();
14169 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14172 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14173 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14174 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14175 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14178 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14179 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14181 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14184 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14186 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14187 if (VT.is512BitVector())
14189 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14192 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14193 const X86Subtarget *Subtarget,
14194 SelectionDAG &DAG) {
14195 SDValue In = Op->getOperand(0);
14196 MVT VT = Op->getSimpleValueType(0);
14197 MVT InVT = In.getSimpleValueType();
14198 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14200 MVT InSVT = InVT.getScalarType();
14201 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14203 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14205 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14210 // SSE41 targets can use the pmovsx* instructions directly.
14211 if (Subtarget->hasSSE41())
14212 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14214 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14218 // As SRAI is only available on i16/i32 types, we expand only up to i32
14219 // and handle i64 separately.
14220 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14221 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14222 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14223 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14224 Curr = DAG.getBitcast(CurrVT, Curr);
14227 SDValue SignExt = Curr;
14228 if (CurrVT != InVT) {
14229 unsigned SignExtShift =
14230 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14231 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14232 DAG.getConstant(SignExtShift, dl, MVT::i8));
14238 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14239 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14240 DAG.getConstant(31, dl, MVT::i8));
14241 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14242 return DAG.getBitcast(VT, Ext);
14248 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14249 SelectionDAG &DAG) {
14250 MVT VT = Op->getSimpleValueType(0);
14251 SDValue In = Op->getOperand(0);
14252 MVT InVT = In.getSimpleValueType();
14255 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14256 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14258 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14259 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14260 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14263 if (Subtarget->hasInt256())
14264 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14266 // Optimize vectors in AVX mode
14267 // Sign extend v8i16 to v8i32 and
14270 // Divide input vector into two parts
14271 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14272 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14273 // concat the vectors to original VT
14275 unsigned NumElems = InVT.getVectorNumElements();
14276 SDValue Undef = DAG.getUNDEF(InVT);
14278 SmallVector<int,8> ShufMask1(NumElems, -1);
14279 for (unsigned i = 0; i != NumElems/2; ++i)
14282 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14284 SmallVector<int,8> ShufMask2(NumElems, -1);
14285 for (unsigned i = 0; i != NumElems/2; ++i)
14286 ShufMask2[i] = i + NumElems/2;
14288 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14290 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14291 VT.getVectorNumElements()/2);
14293 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14294 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14296 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14299 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14300 // may emit an illegal shuffle but the expansion is still better than scalar
14301 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14302 // we'll emit a shuffle and a arithmetic shift.
14303 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14304 // TODO: It is possible to support ZExt by zeroing the undef values during
14305 // the shuffle phase or after the shuffle.
14306 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14307 SelectionDAG &DAG) {
14308 MVT RegVT = Op.getSimpleValueType();
14309 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14310 assert(RegVT.isInteger() &&
14311 "We only custom lower integer vector sext loads.");
14313 // Nothing useful we can do without SSE2 shuffles.
14314 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14316 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14318 EVT MemVT = Ld->getMemoryVT();
14319 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14320 unsigned RegSz = RegVT.getSizeInBits();
14322 ISD::LoadExtType Ext = Ld->getExtensionType();
14324 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14325 && "Only anyext and sext are currently implemented.");
14326 assert(MemVT != RegVT && "Cannot extend to the same type");
14327 assert(MemVT.isVector() && "Must load a vector from memory");
14329 unsigned NumElems = RegVT.getVectorNumElements();
14330 unsigned MemSz = MemVT.getSizeInBits();
14331 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14333 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14334 // The only way in which we have a legal 256-bit vector result but not the
14335 // integer 256-bit operations needed to directly lower a sextload is if we
14336 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14337 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14338 // correctly legalized. We do this late to allow the canonical form of
14339 // sextload to persist throughout the rest of the DAG combiner -- it wants
14340 // to fold together any extensions it can, and so will fuse a sign_extend
14341 // of an sextload into a sextload targeting a wider value.
14343 if (MemSz == 128) {
14344 // Just switch this to a normal load.
14345 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14346 "it must be a legal 128-bit vector "
14348 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14349 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14350 Ld->isInvariant(), Ld->getAlignment());
14352 assert(MemSz < 128 &&
14353 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14354 // Do an sext load to a 128-bit vector type. We want to use the same
14355 // number of elements, but elements half as wide. This will end up being
14356 // recursively lowered by this routine, but will succeed as we definitely
14357 // have all the necessary features if we're using AVX1.
14359 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14360 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14362 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14363 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14364 Ld->isNonTemporal(), Ld->isInvariant(),
14365 Ld->getAlignment());
14368 // Replace chain users with the new chain.
14369 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14370 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14372 // Finally, do a normal sign-extend to the desired register.
14373 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14376 // All sizes must be a power of two.
14377 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14378 "Non-power-of-two elements are not custom lowered!");
14380 // Attempt to load the original value using scalar loads.
14381 // Find the largest scalar type that divides the total loaded size.
14382 MVT SclrLoadTy = MVT::i8;
14383 for (MVT Tp : MVT::integer_valuetypes()) {
14384 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14389 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14390 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14392 SclrLoadTy = MVT::f64;
14394 // Calculate the number of scalar loads that we need to perform
14395 // in order to load our vector from memory.
14396 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14398 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14399 "Can only lower sext loads with a single scalar load!");
14401 unsigned loadRegZize = RegSz;
14402 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14405 // Represent our vector as a sequence of elements which are the
14406 // largest scalar that we can load.
14407 EVT LoadUnitVecVT = EVT::getVectorVT(
14408 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14410 // Represent the data using the same element type that is stored in
14411 // memory. In practice, we ''widen'' MemVT.
14413 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14414 loadRegZize / MemVT.getScalarType().getSizeInBits());
14416 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14417 "Invalid vector type");
14419 // We can't shuffle using an illegal type.
14420 assert(TLI.isTypeLegal(WideVecVT) &&
14421 "We only lower types that form legal widened vector types");
14423 SmallVector<SDValue, 8> Chains;
14424 SDValue Ptr = Ld->getBasePtr();
14425 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
14426 TLI.getPointerTy(DAG.getDataLayout()));
14427 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14429 for (unsigned i = 0; i < NumLoads; ++i) {
14430 // Perform a single load.
14431 SDValue ScalarLoad =
14432 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14433 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14434 Ld->getAlignment());
14435 Chains.push_back(ScalarLoad.getValue(1));
14436 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14437 // another round of DAGCombining.
14439 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14441 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14442 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14444 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14447 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14449 // Bitcast the loaded value to a vector of the original element type, in
14450 // the size of the target vector type.
14451 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14452 unsigned SizeRatio = RegSz / MemSz;
14454 if (Ext == ISD::SEXTLOAD) {
14455 // If we have SSE4.1, we can directly emit a VSEXT node.
14456 if (Subtarget->hasSSE41()) {
14457 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14458 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14462 // Otherwise we'll shuffle the small elements in the high bits of the
14463 // larger type and perform an arithmetic shift. If the shift is not legal
14464 // it's better to scalarize.
14465 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14466 "We can't implement a sext load without an arithmetic right shift!");
14468 // Redistribute the loaded elements into the different locations.
14469 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14470 for (unsigned i = 0; i != NumElems; ++i)
14471 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14473 SDValue Shuff = DAG.getVectorShuffle(
14474 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14476 Shuff = DAG.getBitcast(RegVT, Shuff);
14478 // Build the arithmetic shift.
14479 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14480 MemVT.getVectorElementType().getSizeInBits();
14482 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14483 DAG.getConstant(Amt, dl, RegVT));
14485 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14489 // Redistribute the loaded elements into the different locations.
14490 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14491 for (unsigned i = 0; i != NumElems; ++i)
14492 ShuffleVec[i * SizeRatio] = i;
14494 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14495 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14497 // Bitcast to the requested type.
14498 Shuff = DAG.getBitcast(RegVT, Shuff);
14499 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14503 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14504 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14505 // from the AND / OR.
14506 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14507 Opc = Op.getOpcode();
14508 if (Opc != ISD::OR && Opc != ISD::AND)
14510 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14511 Op.getOperand(0).hasOneUse() &&
14512 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14513 Op.getOperand(1).hasOneUse());
14516 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14517 // 1 and that the SETCC node has a single use.
14518 static bool isXor1OfSetCC(SDValue Op) {
14519 if (Op.getOpcode() != ISD::XOR)
14521 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14522 if (N1C && N1C->getAPIntValue() == 1) {
14523 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14524 Op.getOperand(0).hasOneUse();
14529 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14530 bool addTest = true;
14531 SDValue Chain = Op.getOperand(0);
14532 SDValue Cond = Op.getOperand(1);
14533 SDValue Dest = Op.getOperand(2);
14536 bool Inverted = false;
14538 if (Cond.getOpcode() == ISD::SETCC) {
14539 // Check for setcc([su]{add,sub,mul}o == 0).
14540 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14541 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14542 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14543 Cond.getOperand(0).getResNo() == 1 &&
14544 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14545 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14546 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14547 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14548 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14549 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14551 Cond = Cond.getOperand(0);
14553 SDValue NewCond = LowerSETCC(Cond, DAG);
14554 if (NewCond.getNode())
14559 // FIXME: LowerXALUO doesn't handle these!!
14560 else if (Cond.getOpcode() == X86ISD::ADD ||
14561 Cond.getOpcode() == X86ISD::SUB ||
14562 Cond.getOpcode() == X86ISD::SMUL ||
14563 Cond.getOpcode() == X86ISD::UMUL)
14564 Cond = LowerXALUO(Cond, DAG);
14567 // Look pass (and (setcc_carry (cmp ...)), 1).
14568 if (Cond.getOpcode() == ISD::AND &&
14569 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14570 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14571 if (C && C->getAPIntValue() == 1)
14572 Cond = Cond.getOperand(0);
14575 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14576 // setting operand in place of the X86ISD::SETCC.
14577 unsigned CondOpcode = Cond.getOpcode();
14578 if (CondOpcode == X86ISD::SETCC ||
14579 CondOpcode == X86ISD::SETCC_CARRY) {
14580 CC = Cond.getOperand(0);
14582 SDValue Cmp = Cond.getOperand(1);
14583 unsigned Opc = Cmp.getOpcode();
14584 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14585 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14589 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14593 // These can only come from an arithmetic instruction with overflow,
14594 // e.g. SADDO, UADDO.
14595 Cond = Cond.getNode()->getOperand(1);
14601 CondOpcode = Cond.getOpcode();
14602 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14603 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14604 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14605 Cond.getOperand(0).getValueType() != MVT::i8)) {
14606 SDValue LHS = Cond.getOperand(0);
14607 SDValue RHS = Cond.getOperand(1);
14608 unsigned X86Opcode;
14611 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14612 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14614 switch (CondOpcode) {
14615 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14617 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14619 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14622 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14623 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14627 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14630 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14631 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14632 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14633 default: llvm_unreachable("unexpected overflowing operator");
14636 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14637 if (CondOpcode == ISD::UMULO)
14638 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14641 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14643 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14645 if (CondOpcode == ISD::UMULO)
14646 Cond = X86Op.getValue(2);
14648 Cond = X86Op.getValue(1);
14650 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14654 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14655 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14656 if (CondOpc == ISD::OR) {
14657 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14658 // two branches instead of an explicit OR instruction with a
14660 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14661 isX86LogicalCmp(Cmp)) {
14662 CC = Cond.getOperand(0).getOperand(0);
14663 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14664 Chain, Dest, CC, Cmp);
14665 CC = Cond.getOperand(1).getOperand(0);
14669 } else { // ISD::AND
14670 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14671 // two branches instead of an explicit AND instruction with a
14672 // separate test. However, we only do this if this block doesn't
14673 // have a fall-through edge, because this requires an explicit
14674 // jmp when the condition is false.
14675 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14676 isX86LogicalCmp(Cmp) &&
14677 Op.getNode()->hasOneUse()) {
14678 X86::CondCode CCode =
14679 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14680 CCode = X86::GetOppositeBranchCondition(CCode);
14681 CC = DAG.getConstant(CCode, dl, MVT::i8);
14682 SDNode *User = *Op.getNode()->use_begin();
14683 // Look for an unconditional branch following this conditional branch.
14684 // We need this because we need to reverse the successors in order
14685 // to implement FCMP_OEQ.
14686 if (User->getOpcode() == ISD::BR) {
14687 SDValue FalseBB = User->getOperand(1);
14689 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14690 assert(NewBR == User);
14694 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14695 Chain, Dest, CC, Cmp);
14696 X86::CondCode CCode =
14697 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14698 CCode = X86::GetOppositeBranchCondition(CCode);
14699 CC = DAG.getConstant(CCode, dl, MVT::i8);
14705 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14706 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14707 // It should be transformed during dag combiner except when the condition
14708 // is set by a arithmetics with overflow node.
14709 X86::CondCode CCode =
14710 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14711 CCode = X86::GetOppositeBranchCondition(CCode);
14712 CC = DAG.getConstant(CCode, dl, MVT::i8);
14713 Cond = Cond.getOperand(0).getOperand(1);
14715 } else if (Cond.getOpcode() == ISD::SETCC &&
14716 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14717 // For FCMP_OEQ, we can emit
14718 // two branches instead of an explicit AND instruction with a
14719 // separate test. However, we only do this if this block doesn't
14720 // have a fall-through edge, because this requires an explicit
14721 // jmp when the condition is false.
14722 if (Op.getNode()->hasOneUse()) {
14723 SDNode *User = *Op.getNode()->use_begin();
14724 // Look for an unconditional branch following this conditional branch.
14725 // We need this because we need to reverse the successors in order
14726 // to implement FCMP_OEQ.
14727 if (User->getOpcode() == ISD::BR) {
14728 SDValue FalseBB = User->getOperand(1);
14730 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14731 assert(NewBR == User);
14735 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14736 Cond.getOperand(0), Cond.getOperand(1));
14737 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14738 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14739 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14740 Chain, Dest, CC, Cmp);
14741 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14746 } else if (Cond.getOpcode() == ISD::SETCC &&
14747 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14748 // For FCMP_UNE, we can emit
14749 // two branches instead of an explicit AND instruction with a
14750 // separate test. However, we only do this if this block doesn't
14751 // have a fall-through edge, because this requires an explicit
14752 // jmp when the condition is false.
14753 if (Op.getNode()->hasOneUse()) {
14754 SDNode *User = *Op.getNode()->use_begin();
14755 // Look for an unconditional branch following this conditional branch.
14756 // We need this because we need to reverse the successors in order
14757 // to implement FCMP_UNE.
14758 if (User->getOpcode() == ISD::BR) {
14759 SDValue FalseBB = User->getOperand(1);
14761 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14762 assert(NewBR == User);
14765 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14766 Cond.getOperand(0), Cond.getOperand(1));
14767 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14768 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14769 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14770 Chain, Dest, CC, Cmp);
14771 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14781 // Look pass the truncate if the high bits are known zero.
14782 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14783 Cond = Cond.getOperand(0);
14785 // We know the result of AND is compared against zero. Try to match
14787 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14788 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14789 if (NewSetCC.getNode()) {
14790 CC = NewSetCC.getOperand(0);
14791 Cond = NewSetCC.getOperand(1);
14798 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14799 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14800 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14802 Cond = ConvertCmpIfNecessary(Cond, DAG);
14803 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14804 Chain, Dest, CC, Cond);
14807 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14808 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14809 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14810 // that the guard pages used by the OS virtual memory manager are allocated in
14811 // correct sequence.
14813 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14814 SelectionDAG &DAG) const {
14815 MachineFunction &MF = DAG.getMachineFunction();
14816 bool SplitStack = MF.shouldSplitStack();
14817 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14822 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14823 SDNode* Node = Op.getNode();
14825 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14826 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14827 " not tell us which reg is the stack pointer!");
14828 EVT VT = Node->getValueType(0);
14829 SDValue Tmp1 = SDValue(Node, 0);
14830 SDValue Tmp2 = SDValue(Node, 1);
14831 SDValue Tmp3 = Node->getOperand(2);
14832 SDValue Chain = Tmp1.getOperand(0);
14834 // Chain the dynamic stack allocation so that it doesn't modify the stack
14835 // pointer when other instructions are using the stack.
14836 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14839 SDValue Size = Tmp2.getOperand(1);
14840 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14841 Chain = SP.getValue(1);
14842 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14843 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14844 unsigned StackAlign = TFI.getStackAlignment();
14845 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14846 if (Align > StackAlign)
14847 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14848 DAG.getConstant(-(uint64_t)Align, dl, VT));
14849 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14851 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14852 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14855 SDValue Ops[2] = { Tmp1, Tmp2 };
14856 return DAG.getMergeValues(Ops, dl);
14860 SDValue Chain = Op.getOperand(0);
14861 SDValue Size = Op.getOperand(1);
14862 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14863 EVT VT = Op.getNode()->getValueType(0);
14865 bool Is64Bit = Subtarget->is64Bit();
14866 MVT SPTy = getPointerTy(DAG.getDataLayout());
14869 MachineRegisterInfo &MRI = MF.getRegInfo();
14872 // The 64 bit implementation of segmented stacks needs to clobber both r10
14873 // r11. This makes it impossible to use it along with nested parameters.
14874 const Function *F = MF.getFunction();
14876 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14878 if (I->hasNestAttr())
14879 report_fatal_error("Cannot use segmented stacks with functions that "
14880 "have nested arguments.");
14883 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
14884 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14885 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14886 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14887 DAG.getRegister(Vreg, SPTy));
14888 SDValue Ops1[2] = { Value, Chain };
14889 return DAG.getMergeValues(Ops1, dl);
14892 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14894 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14895 Flag = Chain.getValue(1);
14896 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14898 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14900 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14901 unsigned SPReg = RegInfo->getStackRegister();
14902 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14903 Chain = SP.getValue(1);
14906 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14907 DAG.getConstant(-(uint64_t)Align, dl, VT));
14908 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14911 SDValue Ops1[2] = { SP, Chain };
14912 return DAG.getMergeValues(Ops1, dl);
14916 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14917 MachineFunction &MF = DAG.getMachineFunction();
14918 auto PtrVT = getPointerTy(MF.getDataLayout());
14919 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14921 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14924 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14925 // vastart just stores the address of the VarArgsFrameIndex slot into the
14926 // memory location argument.
14927 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
14928 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14929 MachinePointerInfo(SV), false, false, 0);
14933 // gp_offset (0 - 6 * 8)
14934 // fp_offset (48 - 48 + 8 * 16)
14935 // overflow_arg_area (point to parameters coming in memory).
14937 SmallVector<SDValue, 8> MemOps;
14938 SDValue FIN = Op.getOperand(1);
14940 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14941 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14943 FIN, MachinePointerInfo(SV), false, false, 0);
14944 MemOps.push_back(Store);
14947 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
14948 Store = DAG.getStore(Op.getOperand(0), DL,
14949 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14951 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14952 MemOps.push_back(Store);
14954 // Store ptr to overflow_arg_area
14955 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
14956 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
14957 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14958 MachinePointerInfo(SV, 8),
14960 MemOps.push_back(Store);
14962 // Store ptr to reg_save_area.
14963 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(8, DL));
14964 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
14965 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14966 MachinePointerInfo(SV, 16), false, false, 0);
14967 MemOps.push_back(Store);
14968 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14971 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14972 assert(Subtarget->is64Bit() &&
14973 "LowerVAARG only handles 64-bit va_arg!");
14974 assert((Subtarget->isTargetLinux() ||
14975 Subtarget->isTargetDarwin()) &&
14976 "Unhandled target in LowerVAARG");
14977 assert(Op.getNode()->getNumOperands() == 4);
14978 SDValue Chain = Op.getOperand(0);
14979 SDValue SrcPtr = Op.getOperand(1);
14980 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14981 unsigned Align = Op.getConstantOperandVal(3);
14984 EVT ArgVT = Op.getNode()->getValueType(0);
14985 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14986 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14989 // Decide which area this value should be read from.
14990 // TODO: Implement the AMD64 ABI in its entirety. This simple
14991 // selection mechanism works only for the basic types.
14992 if (ArgVT == MVT::f80) {
14993 llvm_unreachable("va_arg for f80 not yet implemented");
14994 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14995 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14996 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14997 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14999 llvm_unreachable("Unhandled argument type in LowerVAARG");
15002 if (ArgMode == 2) {
15003 // Sanity Check: Make sure using fp_offset makes sense.
15004 assert(!Subtarget->useSoftFloat() &&
15005 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
15006 Attribute::NoImplicitFloat)) &&
15007 Subtarget->hasSSE1());
15010 // Insert VAARG_64 node into the DAG
15011 // VAARG_64 returns two values: Variable Argument Address, Chain
15012 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15013 DAG.getConstant(ArgMode, dl, MVT::i8),
15014 DAG.getConstant(Align, dl, MVT::i32)};
15015 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15016 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15017 VTs, InstOps, MVT::i64,
15018 MachinePointerInfo(SV),
15020 /*Volatile=*/false,
15022 /*WriteMem=*/true);
15023 Chain = VAARG.getValue(1);
15025 // Load the next argument and return it
15026 return DAG.getLoad(ArgVT, dl,
15029 MachinePointerInfo(),
15030 false, false, false, 0);
15033 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15034 SelectionDAG &DAG) {
15035 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15036 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15037 SDValue Chain = Op.getOperand(0);
15038 SDValue DstPtr = Op.getOperand(1);
15039 SDValue SrcPtr = Op.getOperand(2);
15040 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15041 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15044 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15045 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15047 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15050 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15051 // amount is a constant. Takes immediate version of shift as input.
15052 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15053 SDValue SrcOp, uint64_t ShiftAmt,
15054 SelectionDAG &DAG) {
15055 MVT ElementType = VT.getVectorElementType();
15057 // Fold this packed shift into its first operand if ShiftAmt is 0.
15061 // Check for ShiftAmt >= element width
15062 if (ShiftAmt >= ElementType.getSizeInBits()) {
15063 if (Opc == X86ISD::VSRAI)
15064 ShiftAmt = ElementType.getSizeInBits() - 1;
15066 return DAG.getConstant(0, dl, VT);
15069 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15070 && "Unknown target vector shift-by-constant node");
15072 // Fold this packed vector shift into a build vector if SrcOp is a
15073 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15074 if (VT == SrcOp.getSimpleValueType() &&
15075 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15076 SmallVector<SDValue, 8> Elts;
15077 unsigned NumElts = SrcOp->getNumOperands();
15078 ConstantSDNode *ND;
15081 default: llvm_unreachable(nullptr);
15082 case X86ISD::VSHLI:
15083 for (unsigned i=0; i!=NumElts; ++i) {
15084 SDValue CurrentOp = SrcOp->getOperand(i);
15085 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15086 Elts.push_back(CurrentOp);
15089 ND = cast<ConstantSDNode>(CurrentOp);
15090 const APInt &C = ND->getAPIntValue();
15091 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15094 case X86ISD::VSRLI:
15095 for (unsigned i=0; i!=NumElts; ++i) {
15096 SDValue CurrentOp = SrcOp->getOperand(i);
15097 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15098 Elts.push_back(CurrentOp);
15101 ND = cast<ConstantSDNode>(CurrentOp);
15102 const APInt &C = ND->getAPIntValue();
15103 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15106 case X86ISD::VSRAI:
15107 for (unsigned i=0; i!=NumElts; ++i) {
15108 SDValue CurrentOp = SrcOp->getOperand(i);
15109 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15110 Elts.push_back(CurrentOp);
15113 ND = cast<ConstantSDNode>(CurrentOp);
15114 const APInt &C = ND->getAPIntValue();
15115 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15120 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15123 return DAG.getNode(Opc, dl, VT, SrcOp,
15124 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15127 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15128 // may or may not be a constant. Takes immediate version of shift as input.
15129 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15130 SDValue SrcOp, SDValue ShAmt,
15131 SelectionDAG &DAG) {
15132 MVT SVT = ShAmt.getSimpleValueType();
15133 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15135 // Catch shift-by-constant.
15136 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15137 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15138 CShAmt->getZExtValue(), DAG);
15140 // Change opcode to non-immediate version
15142 default: llvm_unreachable("Unknown target vector shift node");
15143 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15144 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15145 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15148 const X86Subtarget &Subtarget =
15149 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15150 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15151 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15152 // Let the shuffle legalizer expand this shift amount node.
15153 SDValue Op0 = ShAmt.getOperand(0);
15154 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15155 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15157 // Need to build a vector containing shift amount.
15158 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15159 SmallVector<SDValue, 4> ShOps;
15160 ShOps.push_back(ShAmt);
15161 if (SVT == MVT::i32) {
15162 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15163 ShOps.push_back(DAG.getUNDEF(SVT));
15165 ShOps.push_back(DAG.getUNDEF(SVT));
15167 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15168 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15171 // The return type has to be a 128-bit type with the same element
15172 // type as the input type.
15173 MVT EltVT = VT.getVectorElementType();
15174 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15176 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15177 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15180 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15181 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15182 /// necessary casting for \p Mask when lowering masking intrinsics.
15183 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15184 SDValue PreservedSrc,
15185 const X86Subtarget *Subtarget,
15186 SelectionDAG &DAG) {
15187 EVT VT = Op.getValueType();
15188 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15189 MVT::i1, VT.getVectorNumElements());
15190 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15191 Mask.getValueType().getSizeInBits());
15194 assert(MaskVT.isSimple() && "invalid mask type");
15196 if (isAllOnes(Mask))
15199 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15200 // are extracted by EXTRACT_SUBVECTOR.
15201 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15202 DAG.getBitcast(BitcastVT, Mask),
15203 DAG.getIntPtrConstant(0, dl));
15205 switch (Op.getOpcode()) {
15207 case X86ISD::PCMPEQM:
15208 case X86ISD::PCMPGTM:
15210 case X86ISD::CMPMU:
15211 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15213 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15214 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15215 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15218 /// \brief Creates an SDNode for a predicated scalar operation.
15219 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15220 /// The mask is comming as MVT::i8 and it should be truncated
15221 /// to MVT::i1 while lowering masking intrinsics.
15222 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15223 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
15224 /// a scalar instruction.
15225 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15226 SDValue PreservedSrc,
15227 const X86Subtarget *Subtarget,
15228 SelectionDAG &DAG) {
15229 if (isAllOnes(Mask))
15232 EVT VT = Op.getValueType();
15234 // The mask should be of type MVT::i1
15235 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15237 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15238 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15239 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15242 static int getSEHRegistrationNodeSize(const Function *Fn) {
15243 if (!Fn->hasPersonalityFn())
15244 report_fatal_error(
15245 "querying registration node size for function without personality");
15246 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15247 // WinEHStatePass for the full struct definition.
15248 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15249 case EHPersonality::MSVC_X86SEH: return 24;
15250 case EHPersonality::MSVC_CXX: return 16;
15253 report_fatal_error("can only recover FP for MSVC EH personality functions");
15256 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15257 /// function or when returning to a parent frame after catching an exception, we
15258 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15259 /// Here's the math:
15260 /// RegNodeBase = EntryEBP - RegNodeSize
15261 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15262 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15263 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15264 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15265 SDValue EntryEBP) {
15266 MachineFunction &MF = DAG.getMachineFunction();
15269 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15270 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15272 // It's possible that the parent function no longer has a personality function
15273 // if the exceptional code was optimized away, in which case we just return
15274 // the incoming EBP.
15275 if (!Fn->hasPersonalityFn())
15278 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15280 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15282 MCSymbol *OffsetSym =
15283 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15284 GlobalValue::getRealLinkageName(Fn->getName()));
15285 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15286 SDValue RegNodeFrameOffset =
15287 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15289 // RegNodeBase = EntryEBP - RegNodeSize
15290 // ParentFP = RegNodeBase - RegNodeFrameOffset
15291 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15292 DAG.getConstant(RegNodeSize, dl, PtrVT));
15293 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15296 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15297 SelectionDAG &DAG) {
15299 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15300 EVT VT = Op.getValueType();
15301 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15303 switch(IntrData->Type) {
15304 case INTR_TYPE_1OP:
15305 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15306 case INTR_TYPE_2OP:
15307 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15309 case INTR_TYPE_3OP:
15310 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15311 Op.getOperand(2), Op.getOperand(3));
15312 case INTR_TYPE_4OP:
15313 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15314 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15315 case INTR_TYPE_1OP_MASK_RM: {
15316 SDValue Src = Op.getOperand(1);
15317 SDValue PassThru = Op.getOperand(2);
15318 SDValue Mask = Op.getOperand(3);
15319 SDValue RoundingMode;
15320 if (Op.getNumOperands() == 4)
15321 RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15323 RoundingMode = Op.getOperand(4);
15324 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15325 if (IntrWithRoundingModeOpcode != 0) {
15326 unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
15327 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
15328 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15329 dl, Op.getValueType(), Src, RoundingMode),
15330 Mask, PassThru, Subtarget, DAG);
15332 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15334 Mask, PassThru, Subtarget, DAG);
15336 case INTR_TYPE_1OP_MASK: {
15337 SDValue Src = Op.getOperand(1);
15338 SDValue Passthru = Op.getOperand(2);
15339 SDValue Mask = Op.getOperand(3);
15340 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15341 Mask, Passthru, Subtarget, DAG);
15343 case INTR_TYPE_SCALAR_MASK_RM: {
15344 SDValue Src1 = Op.getOperand(1);
15345 SDValue Src2 = Op.getOperand(2);
15346 SDValue Src0 = Op.getOperand(3);
15347 SDValue Mask = Op.getOperand(4);
15348 // There are 2 kinds of intrinsics in this group:
15349 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15350 // (2) With rounding mode and sae - 7 operands.
15351 if (Op.getNumOperands() == 6) {
15352 SDValue Sae = Op.getOperand(5);
15353 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15354 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15356 Mask, Src0, Subtarget, DAG);
15358 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15359 SDValue RoundingMode = Op.getOperand(5);
15360 SDValue Sae = Op.getOperand(6);
15361 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15362 RoundingMode, Sae),
15363 Mask, Src0, Subtarget, DAG);
15365 case INTR_TYPE_2OP_MASK: {
15366 SDValue Src1 = Op.getOperand(1);
15367 SDValue Src2 = Op.getOperand(2);
15368 SDValue PassThru = Op.getOperand(3);
15369 SDValue Mask = Op.getOperand(4);
15370 // We specify 2 possible opcodes for intrinsics with rounding modes.
15371 // First, we check if the intrinsic may have non-default rounding mode,
15372 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15373 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15374 if (IntrWithRoundingModeOpcode != 0) {
15375 SDValue Rnd = Op.getOperand(5);
15376 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15377 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15378 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15379 dl, Op.getValueType(),
15381 Mask, PassThru, Subtarget, DAG);
15384 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15386 Mask, PassThru, Subtarget, DAG);
15388 case INTR_TYPE_2OP_MASK_RM: {
15389 SDValue Src1 = Op.getOperand(1);
15390 SDValue Src2 = Op.getOperand(2);
15391 SDValue PassThru = Op.getOperand(3);
15392 SDValue Mask = Op.getOperand(4);
15393 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15394 // First, we check if the intrinsic have rounding mode (6 operands),
15395 // if not, we set rounding mode to "current".
15397 if (Op.getNumOperands() == 6)
15398 Rnd = Op.getOperand(5);
15400 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15401 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15403 Mask, PassThru, Subtarget, DAG);
15405 case INTR_TYPE_3OP_MASK: {
15406 SDValue Src1 = Op.getOperand(1);
15407 SDValue Src2 = Op.getOperand(2);
15408 SDValue Src3 = Op.getOperand(3);
15409 SDValue PassThru = Op.getOperand(4);
15410 SDValue Mask = Op.getOperand(5);
15411 // We specify 2 possible opcodes for intrinsics with rounding modes.
15412 // First, we check if the intrinsic may have non-default rounding mode,
15413 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15414 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15415 if (IntrWithRoundingModeOpcode != 0) {
15416 SDValue Rnd = Op.getOperand(6);
15417 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15418 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15419 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15420 dl, Op.getValueType(),
15421 Src1, Src2, Src3, Rnd),
15422 Mask, PassThru, Subtarget, DAG);
15425 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15427 Mask, PassThru, Subtarget, DAG);
15429 case VPERM_3OP_MASKZ:
15430 case VPERM_3OP_MASK:
15433 case FMA_OP_MASK: {
15434 SDValue Src1 = Op.getOperand(1);
15435 SDValue Src2 = Op.getOperand(2);
15436 SDValue Src3 = Op.getOperand(3);
15437 SDValue Mask = Op.getOperand(4);
15438 EVT VT = Op.getValueType();
15439 SDValue PassThru = SDValue();
15441 // set PassThru element
15442 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
15443 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
15444 else if (IntrData->Type == FMA_OP_MASK3)
15449 // We specify 2 possible opcodes for intrinsics with rounding modes.
15450 // First, we check if the intrinsic may have non-default rounding mode,
15451 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15452 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15453 if (IntrWithRoundingModeOpcode != 0) {
15454 SDValue Rnd = Op.getOperand(5);
15455 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15456 X86::STATIC_ROUNDING::CUR_DIRECTION)
15457 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15458 dl, Op.getValueType(),
15459 Src1, Src2, Src3, Rnd),
15460 Mask, PassThru, Subtarget, DAG);
15462 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15463 dl, Op.getValueType(),
15465 Mask, PassThru, Subtarget, DAG);
15468 case CMP_MASK_CC: {
15469 // Comparison intrinsics with masks.
15470 // Example of transformation:
15471 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15472 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15474 // (v8i1 (insert_subvector undef,
15475 // (v2i1 (and (PCMPEQM %a, %b),
15476 // (extract_subvector
15477 // (v8i1 (bitcast %mask)), 0))), 0))))
15478 EVT VT = Op.getOperand(1).getValueType();
15479 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15480 VT.getVectorNumElements());
15481 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15482 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15483 Mask.getValueType().getSizeInBits());
15485 if (IntrData->Type == CMP_MASK_CC) {
15486 SDValue CC = Op.getOperand(3);
15487 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15488 // We specify 2 possible opcodes for intrinsics with rounding modes.
15489 // First, we check if the intrinsic may have non-default rounding mode,
15490 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15491 if (IntrData->Opc1 != 0) {
15492 SDValue Rnd = Op.getOperand(5);
15493 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15494 X86::STATIC_ROUNDING::CUR_DIRECTION)
15495 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15496 Op.getOperand(2), CC, Rnd);
15498 //default rounding mode
15500 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15501 Op.getOperand(2), CC);
15504 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15505 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15508 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15509 DAG.getTargetConstant(0, dl,
15512 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15513 DAG.getUNDEF(BitcastVT), CmpMask,
15514 DAG.getIntPtrConstant(0, dl));
15515 return DAG.getBitcast(Op.getValueType(), Res);
15517 case COMI: { // Comparison intrinsics
15518 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15519 SDValue LHS = Op.getOperand(1);
15520 SDValue RHS = Op.getOperand(2);
15521 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15522 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15523 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15524 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15525 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15526 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15529 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15530 Op.getOperand(1), Op.getOperand(2), DAG);
15532 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15533 Op.getSimpleValueType(),
15535 Op.getOperand(2), DAG),
15536 Op.getOperand(4), Op.getOperand(3), Subtarget,
15538 case COMPRESS_EXPAND_IN_REG: {
15539 SDValue Mask = Op.getOperand(3);
15540 SDValue DataToCompress = Op.getOperand(1);
15541 SDValue PassThru = Op.getOperand(2);
15542 if (isAllOnes(Mask)) // return data as is
15543 return Op.getOperand(1);
15545 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15547 Mask, PassThru, Subtarget, DAG);
15550 SDValue Mask = Op.getOperand(3);
15551 EVT VT = Op.getValueType();
15552 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15553 VT.getVectorNumElements());
15554 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15555 Mask.getValueType().getSizeInBits());
15557 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15558 DAG.getBitcast(BitcastVT, Mask),
15559 DAG.getIntPtrConstant(0, dl));
15560 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15569 default: return SDValue(); // Don't custom lower most intrinsics.
15571 case Intrinsic::x86_avx2_permd:
15572 case Intrinsic::x86_avx2_permps:
15573 // Operands intentionally swapped. Mask is last operand to intrinsic,
15574 // but second operand for node/instruction.
15575 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15576 Op.getOperand(2), Op.getOperand(1));
15578 // ptest and testp intrinsics. The intrinsic these come from are designed to
15579 // return an integer value, not just an instruction so lower it to the ptest
15580 // or testp pattern and a setcc for the result.
15581 case Intrinsic::x86_sse41_ptestz:
15582 case Intrinsic::x86_sse41_ptestc:
15583 case Intrinsic::x86_sse41_ptestnzc:
15584 case Intrinsic::x86_avx_ptestz_256:
15585 case Intrinsic::x86_avx_ptestc_256:
15586 case Intrinsic::x86_avx_ptestnzc_256:
15587 case Intrinsic::x86_avx_vtestz_ps:
15588 case Intrinsic::x86_avx_vtestc_ps:
15589 case Intrinsic::x86_avx_vtestnzc_ps:
15590 case Intrinsic::x86_avx_vtestz_pd:
15591 case Intrinsic::x86_avx_vtestc_pd:
15592 case Intrinsic::x86_avx_vtestnzc_pd:
15593 case Intrinsic::x86_avx_vtestz_ps_256:
15594 case Intrinsic::x86_avx_vtestc_ps_256:
15595 case Intrinsic::x86_avx_vtestnzc_ps_256:
15596 case Intrinsic::x86_avx_vtestz_pd_256:
15597 case Intrinsic::x86_avx_vtestc_pd_256:
15598 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15599 bool IsTestPacked = false;
15602 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15603 case Intrinsic::x86_avx_vtestz_ps:
15604 case Intrinsic::x86_avx_vtestz_pd:
15605 case Intrinsic::x86_avx_vtestz_ps_256:
15606 case Intrinsic::x86_avx_vtestz_pd_256:
15607 IsTestPacked = true; // Fallthrough
15608 case Intrinsic::x86_sse41_ptestz:
15609 case Intrinsic::x86_avx_ptestz_256:
15611 X86CC = X86::COND_E;
15613 case Intrinsic::x86_avx_vtestc_ps:
15614 case Intrinsic::x86_avx_vtestc_pd:
15615 case Intrinsic::x86_avx_vtestc_ps_256:
15616 case Intrinsic::x86_avx_vtestc_pd_256:
15617 IsTestPacked = true; // Fallthrough
15618 case Intrinsic::x86_sse41_ptestc:
15619 case Intrinsic::x86_avx_ptestc_256:
15621 X86CC = X86::COND_B;
15623 case Intrinsic::x86_avx_vtestnzc_ps:
15624 case Intrinsic::x86_avx_vtestnzc_pd:
15625 case Intrinsic::x86_avx_vtestnzc_ps_256:
15626 case Intrinsic::x86_avx_vtestnzc_pd_256:
15627 IsTestPacked = true; // Fallthrough
15628 case Intrinsic::x86_sse41_ptestnzc:
15629 case Intrinsic::x86_avx_ptestnzc_256:
15631 X86CC = X86::COND_A;
15635 SDValue LHS = Op.getOperand(1);
15636 SDValue RHS = Op.getOperand(2);
15637 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15638 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15639 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15640 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15641 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15643 case Intrinsic::x86_avx512_kortestz_w:
15644 case Intrinsic::x86_avx512_kortestc_w: {
15645 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15646 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15647 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15648 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15649 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15650 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15651 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15654 case Intrinsic::x86_sse42_pcmpistria128:
15655 case Intrinsic::x86_sse42_pcmpestria128:
15656 case Intrinsic::x86_sse42_pcmpistric128:
15657 case Intrinsic::x86_sse42_pcmpestric128:
15658 case Intrinsic::x86_sse42_pcmpistrio128:
15659 case Intrinsic::x86_sse42_pcmpestrio128:
15660 case Intrinsic::x86_sse42_pcmpistris128:
15661 case Intrinsic::x86_sse42_pcmpestris128:
15662 case Intrinsic::x86_sse42_pcmpistriz128:
15663 case Intrinsic::x86_sse42_pcmpestriz128: {
15667 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15668 case Intrinsic::x86_sse42_pcmpistria128:
15669 Opcode = X86ISD::PCMPISTRI;
15670 X86CC = X86::COND_A;
15672 case Intrinsic::x86_sse42_pcmpestria128:
15673 Opcode = X86ISD::PCMPESTRI;
15674 X86CC = X86::COND_A;
15676 case Intrinsic::x86_sse42_pcmpistric128:
15677 Opcode = X86ISD::PCMPISTRI;
15678 X86CC = X86::COND_B;
15680 case Intrinsic::x86_sse42_pcmpestric128:
15681 Opcode = X86ISD::PCMPESTRI;
15682 X86CC = X86::COND_B;
15684 case Intrinsic::x86_sse42_pcmpistrio128:
15685 Opcode = X86ISD::PCMPISTRI;
15686 X86CC = X86::COND_O;
15688 case Intrinsic::x86_sse42_pcmpestrio128:
15689 Opcode = X86ISD::PCMPESTRI;
15690 X86CC = X86::COND_O;
15692 case Intrinsic::x86_sse42_pcmpistris128:
15693 Opcode = X86ISD::PCMPISTRI;
15694 X86CC = X86::COND_S;
15696 case Intrinsic::x86_sse42_pcmpestris128:
15697 Opcode = X86ISD::PCMPESTRI;
15698 X86CC = X86::COND_S;
15700 case Intrinsic::x86_sse42_pcmpistriz128:
15701 Opcode = X86ISD::PCMPISTRI;
15702 X86CC = X86::COND_E;
15704 case Intrinsic::x86_sse42_pcmpestriz128:
15705 Opcode = X86ISD::PCMPESTRI;
15706 X86CC = X86::COND_E;
15709 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15710 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15711 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15712 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15713 DAG.getConstant(X86CC, dl, MVT::i8),
15714 SDValue(PCMP.getNode(), 1));
15715 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15718 case Intrinsic::x86_sse42_pcmpistri128:
15719 case Intrinsic::x86_sse42_pcmpestri128: {
15721 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15722 Opcode = X86ISD::PCMPISTRI;
15724 Opcode = X86ISD::PCMPESTRI;
15726 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15727 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15728 return DAG.getNode(Opcode, dl, VTs, NewOps);
15731 case Intrinsic::x86_seh_lsda: {
15732 // Compute the symbol for the LSDA. We know it'll get emitted later.
15733 MachineFunction &MF = DAG.getMachineFunction();
15734 SDValue Op1 = Op.getOperand(1);
15735 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15736 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15737 GlobalValue::getRealLinkageName(Fn->getName()));
15739 // Generate a simple absolute symbol reference. This intrinsic is only
15740 // supported on 32-bit Windows, which isn't PIC.
15741 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
15742 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15745 case Intrinsic::x86_seh_recoverfp: {
15746 SDValue FnOp = Op.getOperand(1);
15747 SDValue IncomingFPOp = Op.getOperand(2);
15748 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
15749 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
15751 report_fatal_error(
15752 "llvm.x86.seh.recoverfp must take a function as the first argument");
15753 return recoverFramePointer(DAG, Fn, IncomingFPOp);
15756 case Intrinsic::localaddress: {
15757 // Returns one of the stack, base, or frame pointer registers, depending on
15758 // which is used to reference local variables.
15759 MachineFunction &MF = DAG.getMachineFunction();
15760 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15762 if (RegInfo->hasBasePointer(MF))
15763 Reg = RegInfo->getBaseRegister();
15764 else // This function handles the SP or FP case.
15765 Reg = RegInfo->getPtrSizedFrameRegister(MF);
15766 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
15771 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15772 SDValue Src, SDValue Mask, SDValue Base,
15773 SDValue Index, SDValue ScaleOp, SDValue Chain,
15774 const X86Subtarget * Subtarget) {
15776 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15778 llvm_unreachable("Invalid scale type");
15779 unsigned ScaleVal = C->getZExtValue();
15780 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15781 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15783 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15784 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15785 Index.getSimpleValueType().getVectorNumElements());
15787 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15789 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15791 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15792 Mask.getValueType().getSizeInBits());
15794 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15795 // are extracted by EXTRACT_SUBVECTOR.
15796 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15797 DAG.getBitcast(BitcastVT, Mask),
15798 DAG.getIntPtrConstant(0, dl));
15800 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15801 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15802 SDValue Segment = DAG.getRegister(0, MVT::i32);
15803 if (Src.getOpcode() == ISD::UNDEF)
15804 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15805 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15806 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15807 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15808 return DAG.getMergeValues(RetOps, dl);
15811 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15812 SDValue Src, SDValue Mask, SDValue Base,
15813 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15815 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15817 llvm_unreachable("Invalid scale type");
15818 unsigned ScaleVal = C->getZExtValue();
15819 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15820 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15822 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15823 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15824 SDValue Segment = DAG.getRegister(0, MVT::i32);
15825 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15826 Index.getSimpleValueType().getVectorNumElements());
15828 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15830 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15832 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15833 Mask.getValueType().getSizeInBits());
15835 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15836 // are extracted by EXTRACT_SUBVECTOR.
15837 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15838 DAG.getBitcast(BitcastVT, Mask),
15839 DAG.getIntPtrConstant(0, dl));
15841 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15842 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15843 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15844 return SDValue(Res, 1);
15847 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15848 SDValue Mask, SDValue Base, SDValue Index,
15849 SDValue ScaleOp, SDValue Chain) {
15851 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15852 assert(C && "Invalid scale type");
15853 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15854 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15855 SDValue Segment = DAG.getRegister(0, MVT::i32);
15857 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15859 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15861 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15863 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15864 //SDVTList VTs = DAG.getVTList(MVT::Other);
15865 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15866 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15867 return SDValue(Res, 0);
15870 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15871 // read performance monitor counters (x86_rdpmc).
15872 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15873 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15874 SmallVectorImpl<SDValue> &Results) {
15875 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15876 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15879 // The ECX register is used to select the index of the performance counter
15881 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15883 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15885 // Reads the content of a 64-bit performance counter and returns it in the
15886 // registers EDX:EAX.
15887 if (Subtarget->is64Bit()) {
15888 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15889 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15892 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15893 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15896 Chain = HI.getValue(1);
15898 if (Subtarget->is64Bit()) {
15899 // The EAX register is loaded with the low-order 32 bits. The EDX register
15900 // is loaded with the supported high-order bits of the counter.
15901 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15902 DAG.getConstant(32, DL, MVT::i8));
15903 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15904 Results.push_back(Chain);
15908 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15909 SDValue Ops[] = { LO, HI };
15910 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15911 Results.push_back(Pair);
15912 Results.push_back(Chain);
15915 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15916 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15917 // also used to custom lower READCYCLECOUNTER nodes.
15918 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15919 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15920 SmallVectorImpl<SDValue> &Results) {
15921 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15922 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15925 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15926 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15927 // and the EAX register is loaded with the low-order 32 bits.
15928 if (Subtarget->is64Bit()) {
15929 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15930 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15933 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15934 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15937 SDValue Chain = HI.getValue(1);
15939 if (Opcode == X86ISD::RDTSCP_DAG) {
15940 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15942 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15943 // the ECX register. Add 'ecx' explicitly to the chain.
15944 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15946 // Explicitly store the content of ECX at the location passed in input
15947 // to the 'rdtscp' intrinsic.
15948 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15949 MachinePointerInfo(), false, false, 0);
15952 if (Subtarget->is64Bit()) {
15953 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15954 // the EAX register is loaded with the low-order 32 bits.
15955 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15956 DAG.getConstant(32, DL, MVT::i8));
15957 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15958 Results.push_back(Chain);
15962 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15963 SDValue Ops[] = { LO, HI };
15964 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15965 Results.push_back(Pair);
15966 Results.push_back(Chain);
15969 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15970 SelectionDAG &DAG) {
15971 SmallVector<SDValue, 2> Results;
15973 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15975 return DAG.getMergeValues(Results, DL);
15978 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
15979 SelectionDAG &DAG) {
15980 MachineFunction &MF = DAG.getMachineFunction();
15981 const Function *Fn = MF.getFunction();
15983 SDValue Chain = Op.getOperand(0);
15985 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
15986 "using llvm.x86.seh.restoreframe requires a frame pointer");
15988 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15989 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
15991 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15992 unsigned FrameReg =
15993 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15994 unsigned SPReg = RegInfo->getStackRegister();
15995 unsigned SlotSize = RegInfo->getSlotSize();
15997 // Get incoming EBP.
15998 SDValue IncomingEBP =
15999 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16001 // SP is saved in the first field of every registration node, so load
16002 // [EBP-RegNodeSize] into SP.
16003 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16004 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16005 DAG.getConstant(-RegNodeSize, dl, VT));
16007 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16008 false, VT.getScalarSizeInBits() / 8);
16009 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16011 if (!RegInfo->needsStackRealignment(MF)) {
16012 // Adjust EBP to point back to the original frame position.
16013 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16014 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16016 assert(RegInfo->hasBasePointer(MF) &&
16017 "functions with Win32 EH must use frame or base pointer register");
16019 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16020 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16021 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16023 // Reload the spilled EBP value, now that the stack and base pointers are
16025 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16026 X86FI->setHasSEHFramePtrSave(true);
16027 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16028 X86FI->setSEHFramePtrSaveIndex(FI);
16029 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16030 MachinePointerInfo(), false, false, false,
16031 VT.getScalarSizeInBits() / 8);
16032 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16038 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16039 SelectionDAG &DAG) {
16040 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16042 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16044 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16045 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16050 switch(IntrData->Type) {
16052 llvm_unreachable("Unknown Intrinsic Type");
16056 // Emit the node with the right value type.
16057 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16058 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16060 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16061 // Otherwise return the value from Rand, which is always 0, casted to i32.
16062 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16063 DAG.getConstant(1, dl, Op->getValueType(1)),
16064 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16065 SDValue(Result.getNode(), 1) };
16066 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16067 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16070 // Return { result, isValid, chain }.
16071 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16072 SDValue(Result.getNode(), 2));
16075 //gather(v1, mask, index, base, scale);
16076 SDValue Chain = Op.getOperand(0);
16077 SDValue Src = Op.getOperand(2);
16078 SDValue Base = Op.getOperand(3);
16079 SDValue Index = Op.getOperand(4);
16080 SDValue Mask = Op.getOperand(5);
16081 SDValue Scale = Op.getOperand(6);
16082 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16086 //scatter(base, mask, index, v1, scale);
16087 SDValue Chain = Op.getOperand(0);
16088 SDValue Base = Op.getOperand(2);
16089 SDValue Mask = Op.getOperand(3);
16090 SDValue Index = Op.getOperand(4);
16091 SDValue Src = Op.getOperand(5);
16092 SDValue Scale = Op.getOperand(6);
16093 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16097 SDValue Hint = Op.getOperand(6);
16098 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16099 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16100 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16101 SDValue Chain = Op.getOperand(0);
16102 SDValue Mask = Op.getOperand(2);
16103 SDValue Index = Op.getOperand(3);
16104 SDValue Base = Op.getOperand(4);
16105 SDValue Scale = Op.getOperand(5);
16106 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16108 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16110 SmallVector<SDValue, 2> Results;
16111 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16113 return DAG.getMergeValues(Results, dl);
16115 // Read Performance Monitoring Counters.
16117 SmallVector<SDValue, 2> Results;
16118 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16119 return DAG.getMergeValues(Results, dl);
16121 // XTEST intrinsics.
16123 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16124 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16125 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16126 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16128 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16129 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16130 Ret, SDValue(InTrans.getNode(), 1));
16134 SmallVector<SDValue, 2> Results;
16135 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16136 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16137 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16138 DAG.getConstant(-1, dl, MVT::i8));
16139 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16140 Op.getOperand(4), GenCF.getValue(1));
16141 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16142 Op.getOperand(5), MachinePointerInfo(),
16144 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16145 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16147 Results.push_back(SetCC);
16148 Results.push_back(Store);
16149 return DAG.getMergeValues(Results, dl);
16151 case COMPRESS_TO_MEM: {
16153 SDValue Mask = Op.getOperand(4);
16154 SDValue DataToCompress = Op.getOperand(3);
16155 SDValue Addr = Op.getOperand(2);
16156 SDValue Chain = Op.getOperand(0);
16158 EVT VT = DataToCompress.getValueType();
16159 if (isAllOnes(Mask)) // return just a store
16160 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16161 MachinePointerInfo(), false, false,
16162 VT.getScalarSizeInBits()/8);
16164 SDValue Compressed =
16165 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16166 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16167 return DAG.getStore(Chain, dl, Compressed, Addr,
16168 MachinePointerInfo(), false, false,
16169 VT.getScalarSizeInBits()/8);
16171 case EXPAND_FROM_MEM: {
16173 SDValue Mask = Op.getOperand(4);
16174 SDValue PassThru = Op.getOperand(3);
16175 SDValue Addr = Op.getOperand(2);
16176 SDValue Chain = Op.getOperand(0);
16177 EVT VT = Op.getValueType();
16179 if (isAllOnes(Mask)) // return just a load
16180 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16181 false, VT.getScalarSizeInBits()/8);
16183 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16184 false, false, false,
16185 VT.getScalarSizeInBits()/8);
16187 SDValue Results[] = {
16188 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16189 Mask, PassThru, Subtarget, DAG), Chain};
16190 return DAG.getMergeValues(Results, dl);
16195 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16196 SelectionDAG &DAG) const {
16197 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16198 MFI->setReturnAddressIsTaken(true);
16200 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16203 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16205 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16208 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16209 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16210 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16211 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16212 DAG.getNode(ISD::ADD, dl, PtrVT,
16213 FrameAddr, Offset),
16214 MachinePointerInfo(), false, false, false, 0);
16217 // Just load the return address.
16218 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16219 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16220 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16223 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16224 MachineFunction &MF = DAG.getMachineFunction();
16225 MachineFrameInfo *MFI = MF.getFrameInfo();
16226 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16227 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16228 EVT VT = Op.getValueType();
16230 MFI->setFrameAddressIsTaken(true);
16232 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
16233 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
16234 // is not possible to crawl up the stack without looking at the unwind codes
16236 int FrameAddrIndex = FuncInfo->getFAIndex();
16237 if (!FrameAddrIndex) {
16238 // Set up a frame object for the return address.
16239 unsigned SlotSize = RegInfo->getSlotSize();
16240 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
16241 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
16242 FuncInfo->setFAIndex(FrameAddrIndex);
16244 return DAG.getFrameIndex(FrameAddrIndex, VT);
16247 unsigned FrameReg =
16248 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16249 SDLoc dl(Op); // FIXME probably not meaningful
16250 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16251 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16252 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16253 "Invalid Frame Register!");
16254 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16256 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16257 MachinePointerInfo(),
16258 false, false, false, 0);
16262 // FIXME? Maybe this could be a TableGen attribute on some registers and
16263 // this table could be generated automatically from RegInfo.
16264 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16266 unsigned Reg = StringSwitch<unsigned>(RegName)
16267 .Case("esp", X86::ESP)
16268 .Case("rsp", X86::RSP)
16272 report_fatal_error("Invalid register name global variable");
16275 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16276 SelectionDAG &DAG) const {
16277 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16278 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
16281 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16282 SDValue Chain = Op.getOperand(0);
16283 SDValue Offset = Op.getOperand(1);
16284 SDValue Handler = Op.getOperand(2);
16287 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16288 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16289 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16290 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16291 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16292 "Invalid Frame Register!");
16293 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16294 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16296 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16297 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16299 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16300 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16302 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16304 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16305 DAG.getRegister(StoreAddrReg, PtrVT));
16308 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16309 SelectionDAG &DAG) const {
16311 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16312 DAG.getVTList(MVT::i32, MVT::Other),
16313 Op.getOperand(0), Op.getOperand(1));
16316 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16317 SelectionDAG &DAG) const {
16319 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16320 Op.getOperand(0), Op.getOperand(1));
16323 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16324 return Op.getOperand(0);
16327 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16328 SelectionDAG &DAG) const {
16329 SDValue Root = Op.getOperand(0);
16330 SDValue Trmp = Op.getOperand(1); // trampoline
16331 SDValue FPtr = Op.getOperand(2); // nested function
16332 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16335 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16336 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16338 if (Subtarget->is64Bit()) {
16339 SDValue OutChains[6];
16341 // Large code-model.
16342 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16343 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16345 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16346 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16348 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16350 // Load the pointer to the nested function into R11.
16351 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16352 SDValue Addr = Trmp;
16353 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16354 Addr, MachinePointerInfo(TrmpAddr),
16357 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16358 DAG.getConstant(2, dl, MVT::i64));
16359 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16360 MachinePointerInfo(TrmpAddr, 2),
16363 // Load the 'nest' parameter value into R10.
16364 // R10 is specified in X86CallingConv.td
16365 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16366 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16367 DAG.getConstant(10, dl, MVT::i64));
16368 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16369 Addr, MachinePointerInfo(TrmpAddr, 10),
16372 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16373 DAG.getConstant(12, dl, MVT::i64));
16374 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16375 MachinePointerInfo(TrmpAddr, 12),
16378 // Jump to the nested function.
16379 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16380 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16381 DAG.getConstant(20, dl, MVT::i64));
16382 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16383 Addr, MachinePointerInfo(TrmpAddr, 20),
16386 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16387 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16388 DAG.getConstant(22, dl, MVT::i64));
16389 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16390 Addr, MachinePointerInfo(TrmpAddr, 22),
16393 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16395 const Function *Func =
16396 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16397 CallingConv::ID CC = Func->getCallingConv();
16402 llvm_unreachable("Unsupported calling convention");
16403 case CallingConv::C:
16404 case CallingConv::X86_StdCall: {
16405 // Pass 'nest' parameter in ECX.
16406 // Must be kept in sync with X86CallingConv.td
16407 NestReg = X86::ECX;
16409 // Check that ECX wasn't needed by an 'inreg' parameter.
16410 FunctionType *FTy = Func->getFunctionType();
16411 const AttributeSet &Attrs = Func->getAttributes();
16413 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16414 unsigned InRegCount = 0;
16417 for (FunctionType::param_iterator I = FTy->param_begin(),
16418 E = FTy->param_end(); I != E; ++I, ++Idx)
16419 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16420 // FIXME: should only count parameters that are lowered to integers.
16421 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16423 if (InRegCount > 2) {
16424 report_fatal_error("Nest register in use - reduce number of inreg"
16430 case CallingConv::X86_FastCall:
16431 case CallingConv::X86_ThisCall:
16432 case CallingConv::Fast:
16433 // Pass 'nest' parameter in EAX.
16434 // Must be kept in sync with X86CallingConv.td
16435 NestReg = X86::EAX;
16439 SDValue OutChains[4];
16440 SDValue Addr, Disp;
16442 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16443 DAG.getConstant(10, dl, MVT::i32));
16444 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16446 // This is storing the opcode for MOV32ri.
16447 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16448 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16449 OutChains[0] = DAG.getStore(Root, dl,
16450 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16451 Trmp, MachinePointerInfo(TrmpAddr),
16454 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16455 DAG.getConstant(1, dl, MVT::i32));
16456 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16457 MachinePointerInfo(TrmpAddr, 1),
16460 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16461 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16462 DAG.getConstant(5, dl, MVT::i32));
16463 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16464 Addr, MachinePointerInfo(TrmpAddr, 5),
16467 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16468 DAG.getConstant(6, dl, MVT::i32));
16469 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16470 MachinePointerInfo(TrmpAddr, 6),
16473 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16477 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16478 SelectionDAG &DAG) const {
16480 The rounding mode is in bits 11:10 of FPSR, and has the following
16482 00 Round to nearest
16487 FLT_ROUNDS, on the other hand, expects the following:
16494 To perform the conversion, we do:
16495 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16498 MachineFunction &MF = DAG.getMachineFunction();
16499 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16500 unsigned StackAlignment = TFI.getStackAlignment();
16501 MVT VT = Op.getSimpleValueType();
16504 // Save FP Control Word to stack slot
16505 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16506 SDValue StackSlot =
16507 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
16509 MachineMemOperand *MMO =
16510 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16511 MachineMemOperand::MOStore, 2, 2);
16513 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16514 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16515 DAG.getVTList(MVT::Other),
16516 Ops, MVT::i16, MMO);
16518 // Load FP Control Word from stack slot
16519 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16520 MachinePointerInfo(), false, false, false, 0);
16522 // Transform as necessary
16524 DAG.getNode(ISD::SRL, DL, MVT::i16,
16525 DAG.getNode(ISD::AND, DL, MVT::i16,
16526 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16527 DAG.getConstant(11, DL, MVT::i8));
16529 DAG.getNode(ISD::SRL, DL, MVT::i16,
16530 DAG.getNode(ISD::AND, DL, MVT::i16,
16531 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16532 DAG.getConstant(9, DL, MVT::i8));
16535 DAG.getNode(ISD::AND, DL, MVT::i16,
16536 DAG.getNode(ISD::ADD, DL, MVT::i16,
16537 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16538 DAG.getConstant(1, DL, MVT::i16)),
16539 DAG.getConstant(3, DL, MVT::i16));
16541 return DAG.getNode((VT.getSizeInBits() < 16 ?
16542 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16545 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16546 MVT VT = Op.getSimpleValueType();
16548 unsigned NumBits = VT.getSizeInBits();
16551 Op = Op.getOperand(0);
16552 if (VT == MVT::i8) {
16553 // Zero extend to i32 since there is not an i8 bsr.
16555 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16558 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16559 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16560 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16562 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16565 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16566 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16569 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16571 // Finally xor with NumBits-1.
16572 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16573 DAG.getConstant(NumBits - 1, dl, OpVT));
16576 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16580 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16581 MVT VT = Op.getSimpleValueType();
16583 unsigned NumBits = VT.getSizeInBits();
16586 Op = Op.getOperand(0);
16587 if (VT == MVT::i8) {
16588 // Zero extend to i32 since there is not an i8 bsr.
16590 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16593 // Issue a bsr (scan bits in reverse).
16594 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16595 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16597 // And xor with NumBits-1.
16598 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16599 DAG.getConstant(NumBits - 1, dl, OpVT));
16602 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16606 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16607 MVT VT = Op.getSimpleValueType();
16608 unsigned NumBits = VT.getSizeInBits();
16610 Op = Op.getOperand(0);
16612 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16613 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16614 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16616 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16619 DAG.getConstant(NumBits, dl, VT),
16620 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16623 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16626 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16627 // ones, and then concatenate the result back.
16628 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16629 MVT VT = Op.getSimpleValueType();
16631 assert(VT.is256BitVector() && VT.isInteger() &&
16632 "Unsupported value type for operation");
16634 unsigned NumElems = VT.getVectorNumElements();
16637 // Extract the LHS vectors
16638 SDValue LHS = Op.getOperand(0);
16639 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16640 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16642 // Extract the RHS vectors
16643 SDValue RHS = Op.getOperand(1);
16644 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16645 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16647 MVT EltVT = VT.getVectorElementType();
16648 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16650 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16651 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16652 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16655 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16656 if (Op.getValueType() == MVT::i1)
16657 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16658 Op.getOperand(0), Op.getOperand(1));
16659 assert(Op.getSimpleValueType().is256BitVector() &&
16660 Op.getSimpleValueType().isInteger() &&
16661 "Only handle AVX 256-bit vector integer operation");
16662 return Lower256IntArith(Op, DAG);
16665 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16666 if (Op.getValueType() == MVT::i1)
16667 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16668 Op.getOperand(0), Op.getOperand(1));
16669 assert(Op.getSimpleValueType().is256BitVector() &&
16670 Op.getSimpleValueType().isInteger() &&
16671 "Only handle AVX 256-bit vector integer operation");
16672 return Lower256IntArith(Op, DAG);
16675 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16676 SelectionDAG &DAG) {
16678 MVT VT = Op.getSimpleValueType();
16681 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16683 // Decompose 256-bit ops into smaller 128-bit ops.
16684 if (VT.is256BitVector() && !Subtarget->hasInt256())
16685 return Lower256IntArith(Op, DAG);
16687 SDValue A = Op.getOperand(0);
16688 SDValue B = Op.getOperand(1);
16690 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16691 // pairs, multiply and truncate.
16692 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16693 if (Subtarget->hasInt256()) {
16694 if (VT == MVT::v32i8) {
16695 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16696 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16697 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16698 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16699 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16700 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16701 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16702 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16703 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16704 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16707 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16708 return DAG.getNode(
16709 ISD::TRUNCATE, dl, VT,
16710 DAG.getNode(ISD::MUL, dl, ExVT,
16711 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16712 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16715 assert(VT == MVT::v16i8 &&
16716 "Pre-AVX2 support only supports v16i8 multiplication");
16717 MVT ExVT = MVT::v8i16;
16719 // Extract the lo parts and sign extend to i16
16721 if (Subtarget->hasSSE41()) {
16722 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16723 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16725 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16726 -1, 4, -1, 5, -1, 6, -1, 7};
16727 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16728 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16729 ALo = DAG.getBitcast(ExVT, ALo);
16730 BLo = DAG.getBitcast(ExVT, BLo);
16731 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16732 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16735 // Extract the hi parts and sign extend to i16
16737 if (Subtarget->hasSSE41()) {
16738 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16739 -1, -1, -1, -1, -1, -1, -1, -1};
16740 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16741 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16742 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16743 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16745 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16746 -1, 12, -1, 13, -1, 14, -1, 15};
16747 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16748 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16749 AHi = DAG.getBitcast(ExVT, AHi);
16750 BHi = DAG.getBitcast(ExVT, BHi);
16751 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16752 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16755 // Multiply, mask the lower 8bits of the lo/hi results and pack
16756 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16757 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16758 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16759 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16760 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16763 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16764 if (VT == MVT::v4i32) {
16765 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16766 "Should not custom lower when pmuldq is available!");
16768 // Extract the odd parts.
16769 static const int UnpackMask[] = { 1, -1, 3, -1 };
16770 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16771 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16773 // Multiply the even parts.
16774 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16775 // Now multiply odd parts.
16776 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16778 Evens = DAG.getBitcast(VT, Evens);
16779 Odds = DAG.getBitcast(VT, Odds);
16781 // Merge the two vectors back together with a shuffle. This expands into 2
16783 static const int ShufMask[] = { 0, 4, 2, 6 };
16784 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16787 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16788 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16790 // Ahi = psrlqi(a, 32);
16791 // Bhi = psrlqi(b, 32);
16793 // AloBlo = pmuludq(a, b);
16794 // AloBhi = pmuludq(a, Bhi);
16795 // AhiBlo = pmuludq(Ahi, b);
16797 // AloBhi = psllqi(AloBhi, 32);
16798 // AhiBlo = psllqi(AhiBlo, 32);
16799 // return AloBlo + AloBhi + AhiBlo;
16801 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16802 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16804 SDValue AhiBlo = Ahi;
16805 SDValue AloBhi = Bhi;
16806 // Bit cast to 32-bit vectors for MULUDQ
16807 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16808 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16809 A = DAG.getBitcast(MulVT, A);
16810 B = DAG.getBitcast(MulVT, B);
16811 Ahi = DAG.getBitcast(MulVT, Ahi);
16812 Bhi = DAG.getBitcast(MulVT, Bhi);
16814 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16815 // After shifting right const values the result may be all-zero.
16816 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
16817 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16818 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16820 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
16821 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16822 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16825 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16826 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16829 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16830 assert(Subtarget->isTargetWin64() && "Unexpected target");
16831 EVT VT = Op.getValueType();
16832 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16833 "Unexpected return type for lowering");
16837 switch (Op->getOpcode()) {
16838 default: llvm_unreachable("Unexpected request for libcall!");
16839 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16840 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16841 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16842 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16843 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16844 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16848 SDValue InChain = DAG.getEntryNode();
16850 TargetLowering::ArgListTy Args;
16851 TargetLowering::ArgListEntry Entry;
16852 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16853 EVT ArgVT = Op->getOperand(i).getValueType();
16854 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16855 "Unexpected argument type for lowering");
16856 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16857 Entry.Node = StackPtr;
16858 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16860 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16861 Entry.Ty = PointerType::get(ArgTy,0);
16862 Entry.isSExt = false;
16863 Entry.isZExt = false;
16864 Args.push_back(Entry);
16867 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16868 getPointerTy(DAG.getDataLayout()));
16870 TargetLowering::CallLoweringInfo CLI(DAG);
16871 CLI.setDebugLoc(dl).setChain(InChain)
16872 .setCallee(getLibcallCallingConv(LC),
16873 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16874 Callee, std::move(Args), 0)
16875 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16877 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16878 return DAG.getBitcast(VT, CallInfo.first);
16881 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16882 SelectionDAG &DAG) {
16883 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16884 EVT VT = Op0.getValueType();
16887 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16888 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16890 // PMULxD operations multiply each even value (starting at 0) of LHS with
16891 // the related value of RHS and produce a widen result.
16892 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16893 // => <2 x i64> <ae|cg>
16895 // In other word, to have all the results, we need to perform two PMULxD:
16896 // 1. one with the even values.
16897 // 2. one with the odd values.
16898 // To achieve #2, with need to place the odd values at an even position.
16900 // Place the odd value at an even position (basically, shift all values 1
16901 // step to the left):
16902 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16903 // <a|b|c|d> => <b|undef|d|undef>
16904 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16905 // <e|f|g|h> => <f|undef|h|undef>
16906 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16908 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16910 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16911 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16913 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16914 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16915 // => <2 x i64> <ae|cg>
16916 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16917 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16918 // => <2 x i64> <bf|dh>
16919 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16921 // Shuffle it back into the right order.
16922 SDValue Highs, Lows;
16923 if (VT == MVT::v8i32) {
16924 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16925 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16926 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16927 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16929 const int HighMask[] = {1, 5, 3, 7};
16930 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16931 const int LowMask[] = {0, 4, 2, 6};
16932 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16935 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16936 // unsigned multiply.
16937 if (IsSigned && !Subtarget->hasSSE41()) {
16938 SDValue ShAmt = DAG.getConstant(
16940 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
16941 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16942 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16943 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16944 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16946 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16947 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16950 // The first result of MUL_LOHI is actually the low value, followed by the
16952 SDValue Ops[] = {Lows, Highs};
16953 return DAG.getMergeValues(Ops, dl);
16956 // Return true if the requred (according to Opcode) shift-imm form is natively
16957 // supported by the Subtarget
16958 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16960 if (VT.getScalarSizeInBits() < 16)
16963 if (VT.is512BitVector() &&
16964 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16967 bool LShift = VT.is128BitVector() ||
16968 (VT.is256BitVector() && Subtarget->hasInt256());
16970 bool AShift = LShift && (Subtarget->hasVLX() ||
16971 (VT != MVT::v2i64 && VT != MVT::v4i64));
16972 return (Opcode == ISD::SRA) ? AShift : LShift;
16975 // The shift amount is a variable, but it is the same for all vector lanes.
16976 // These instrcutions are defined together with shift-immediate.
16978 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16980 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16983 // Return true if the requred (according to Opcode) variable-shift form is
16984 // natively supported by the Subtarget
16985 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16988 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16991 // vXi16 supported only on AVX-512, BWI
16992 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16995 if (VT.is512BitVector() || Subtarget->hasVLX())
16998 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16999 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17000 return (Opcode == ISD::SRA) ? AShift : LShift;
17003 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17004 const X86Subtarget *Subtarget) {
17005 MVT VT = Op.getSimpleValueType();
17007 SDValue R = Op.getOperand(0);
17008 SDValue Amt = Op.getOperand(1);
17010 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17011 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17013 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17014 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17015 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17016 SDValue Ex = DAG.getBitcast(ExVT, R);
17018 if (ShiftAmt >= 32) {
17019 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17021 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17022 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17023 ShiftAmt - 32, DAG);
17024 if (VT == MVT::v2i64)
17025 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17026 if (VT == MVT::v4i64)
17027 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17028 {9, 1, 11, 3, 13, 5, 15, 7});
17030 // SRA upper i32, SHL whole i64 and select lower i32.
17031 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17034 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17035 Lower = DAG.getBitcast(ExVT, Lower);
17036 if (VT == MVT::v2i64)
17037 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17038 if (VT == MVT::v4i64)
17039 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17040 {8, 1, 10, 3, 12, 5, 14, 7});
17042 return DAG.getBitcast(VT, Ex);
17045 // Optimize shl/srl/sra with constant shift amount.
17046 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17047 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17048 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17050 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17051 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17053 // i64 SRA needs to be performed as partial shifts.
17054 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17055 Op.getOpcode() == ISD::SRA)
17056 return ArithmeticShiftRight64(ShiftAmt);
17058 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17059 unsigned NumElts = VT.getVectorNumElements();
17060 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17062 if (Op.getOpcode() == ISD::SHL) {
17063 // Simple i8 add case
17065 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17067 // Make a large shift.
17068 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17070 SHL = DAG.getBitcast(VT, SHL);
17071 // Zero out the rightmost bits.
17072 SmallVector<SDValue, 32> V(
17073 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17074 return DAG.getNode(ISD::AND, dl, VT, SHL,
17075 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17077 if (Op.getOpcode() == ISD::SRL) {
17078 // Make a large shift.
17079 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17081 SRL = DAG.getBitcast(VT, SRL);
17082 // Zero out the leftmost bits.
17083 SmallVector<SDValue, 32> V(
17084 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17085 return DAG.getNode(ISD::AND, dl, VT, SRL,
17086 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17088 if (Op.getOpcode() == ISD::SRA) {
17089 if (ShiftAmt == 7) {
17090 // R s>> 7 === R s< 0
17091 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17092 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17095 // R s>> a === ((R u>> a) ^ m) - m
17096 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17097 SmallVector<SDValue, 32> V(NumElts,
17098 DAG.getConstant(128 >> ShiftAmt, dl,
17100 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17101 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17102 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17105 llvm_unreachable("Unknown shift opcode.");
17110 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17111 if (!Subtarget->is64Bit() &&
17112 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17113 Amt.getOpcode() == ISD::BITCAST &&
17114 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17115 Amt = Amt.getOperand(0);
17116 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17117 VT.getVectorNumElements();
17118 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17119 uint64_t ShiftAmt = 0;
17120 for (unsigned i = 0; i != Ratio; ++i) {
17121 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17125 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17127 // Check remaining shift amounts.
17128 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17129 uint64_t ShAmt = 0;
17130 for (unsigned j = 0; j != Ratio; ++j) {
17131 ConstantSDNode *C =
17132 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17136 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17138 if (ShAmt != ShiftAmt)
17142 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17143 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17145 if (Op.getOpcode() == ISD::SRA)
17146 return ArithmeticShiftRight64(ShiftAmt);
17152 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17153 const X86Subtarget* Subtarget) {
17154 MVT VT = Op.getSimpleValueType();
17156 SDValue R = Op.getOperand(0);
17157 SDValue Amt = Op.getOperand(1);
17159 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17160 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17162 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
17163 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
17165 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
17167 EVT EltVT = VT.getVectorElementType();
17169 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
17170 // Check if this build_vector node is doing a splat.
17171 // If so, then set BaseShAmt equal to the splat value.
17172 BaseShAmt = BV->getSplatValue();
17173 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
17174 BaseShAmt = SDValue();
17176 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17177 Amt = Amt.getOperand(0);
17179 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
17180 if (SVN && SVN->isSplat()) {
17181 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
17182 SDValue InVec = Amt.getOperand(0);
17183 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17184 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
17185 "Unexpected shuffle index found!");
17186 BaseShAmt = InVec.getOperand(SplatIdx);
17187 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17188 if (ConstantSDNode *C =
17189 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17190 if (C->getZExtValue() == SplatIdx)
17191 BaseShAmt = InVec.getOperand(1);
17196 // Avoid introducing an extract element from a shuffle.
17197 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
17198 DAG.getIntPtrConstant(SplatIdx, dl));
17202 if (BaseShAmt.getNode()) {
17203 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
17204 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
17205 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
17206 else if (EltVT.bitsLT(MVT::i32))
17207 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17209 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
17213 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17214 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
17215 Amt.getOpcode() == ISD::BITCAST &&
17216 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17217 Amt = Amt.getOperand(0);
17218 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17219 VT.getVectorNumElements();
17220 std::vector<SDValue> Vals(Ratio);
17221 for (unsigned i = 0; i != Ratio; ++i)
17222 Vals[i] = Amt.getOperand(i);
17223 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17224 for (unsigned j = 0; j != Ratio; ++j)
17225 if (Vals[j] != Amt.getOperand(i + j))
17229 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
17230 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
17235 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17236 SelectionDAG &DAG) {
17237 MVT VT = Op.getSimpleValueType();
17239 SDValue R = Op.getOperand(0);
17240 SDValue Amt = Op.getOperand(1);
17242 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17243 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17245 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
17248 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
17251 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
17254 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
17255 // shifts per-lane and then shuffle the partial results back together.
17256 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
17257 // Splat the shift amounts so the scalar shifts above will catch it.
17258 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
17259 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
17260 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
17261 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
17262 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
17265 // If possible, lower this packed shift into a vector multiply instead of
17266 // expanding it into a sequence of scalar shifts.
17267 // Do this only if the vector shift count is a constant build_vector.
17268 if (Op.getOpcode() == ISD::SHL &&
17269 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17270 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17271 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17272 SmallVector<SDValue, 8> Elts;
17273 EVT SVT = VT.getScalarType();
17274 unsigned SVTBits = SVT.getSizeInBits();
17275 const APInt &One = APInt(SVTBits, 1);
17276 unsigned NumElems = VT.getVectorNumElements();
17278 for (unsigned i=0; i !=NumElems; ++i) {
17279 SDValue Op = Amt->getOperand(i);
17280 if (Op->getOpcode() == ISD::UNDEF) {
17281 Elts.push_back(Op);
17285 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17286 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17287 uint64_t ShAmt = C.getZExtValue();
17288 if (ShAmt >= SVTBits) {
17289 Elts.push_back(DAG.getUNDEF(SVT));
17292 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
17294 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17295 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17298 // Lower SHL with variable shift amount.
17299 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17300 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
17302 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
17303 DAG.getConstant(0x3f800000U, dl, VT));
17304 Op = DAG.getBitcast(MVT::v4f32, Op);
17305 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17306 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17309 // If possible, lower this shift as a sequence of two shifts by
17310 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17312 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17314 // Could be rewritten as:
17315 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17317 // The advantage is that the two shifts from the example would be
17318 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17319 // the vector shift into four scalar shifts plus four pairs of vector
17321 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17322 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17323 unsigned TargetOpcode = X86ISD::MOVSS;
17324 bool CanBeSimplified;
17325 // The splat value for the first packed shift (the 'X' from the example).
17326 SDValue Amt1 = Amt->getOperand(0);
17327 // The splat value for the second packed shift (the 'Y' from the example).
17328 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17329 Amt->getOperand(2);
17331 // See if it is possible to replace this node with a sequence of
17332 // two shifts followed by a MOVSS/MOVSD
17333 if (VT == MVT::v4i32) {
17334 // Check if it is legal to use a MOVSS.
17335 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17336 Amt2 == Amt->getOperand(3);
17337 if (!CanBeSimplified) {
17338 // Otherwise, check if we can still simplify this node using a MOVSD.
17339 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17340 Amt->getOperand(2) == Amt->getOperand(3);
17341 TargetOpcode = X86ISD::MOVSD;
17342 Amt2 = Amt->getOperand(2);
17345 // Do similar checks for the case where the machine value type
17347 CanBeSimplified = Amt1 == Amt->getOperand(1);
17348 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17349 CanBeSimplified = Amt2 == Amt->getOperand(i);
17351 if (!CanBeSimplified) {
17352 TargetOpcode = X86ISD::MOVSD;
17353 CanBeSimplified = true;
17354 Amt2 = Amt->getOperand(4);
17355 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17356 CanBeSimplified = Amt1 == Amt->getOperand(i);
17357 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17358 CanBeSimplified = Amt2 == Amt->getOperand(j);
17362 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17363 isa<ConstantSDNode>(Amt2)) {
17364 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17365 EVT CastVT = MVT::v4i32;
17367 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
17368 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17370 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
17371 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17372 if (TargetOpcode == X86ISD::MOVSD)
17373 CastVT = MVT::v2i64;
17374 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
17375 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
17376 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17378 return DAG.getBitcast(VT, Result);
17382 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
17383 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
17384 unsigned ShiftOpcode = Op->getOpcode();
17386 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
17387 // On SSE41 targets we make use of the fact that VSELECT lowers
17388 // to PBLENDVB which selects bytes based just on the sign bit.
17389 if (Subtarget->hasSSE41()) {
17390 V0 = DAG.getBitcast(VT, V0);
17391 V1 = DAG.getBitcast(VT, V1);
17392 Sel = DAG.getBitcast(VT, Sel);
17393 return DAG.getBitcast(SelVT,
17394 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
17396 // On pre-SSE41 targets we test for the sign bit by comparing to
17397 // zero - a negative value will set all bits of the lanes to true
17398 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
17399 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
17400 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
17401 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
17404 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
17405 // We can safely do this using i16 shifts as we're only interested in
17406 // the 3 lower bits of each byte.
17407 Amt = DAG.getBitcast(ExtVT, Amt);
17408 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
17409 Amt = DAG.getBitcast(VT, Amt);
17411 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
17412 // r = VSELECT(r, shift(r, 4), a);
17414 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17415 R = SignBitSelect(VT, Amt, M, R);
17418 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17420 // r = VSELECT(r, shift(r, 2), a);
17421 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17422 R = SignBitSelect(VT, Amt, M, R);
17425 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17427 // return VSELECT(r, shift(r, 1), a);
17428 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17429 R = SignBitSelect(VT, Amt, M, R);
17433 if (Op->getOpcode() == ISD::SRA) {
17434 // For SRA we need to unpack each byte to the higher byte of a i16 vector
17435 // so we can correctly sign extend. We don't care what happens to the
17437 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
17438 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
17439 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
17440 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
17441 ALo = DAG.getBitcast(ExtVT, ALo);
17442 AHi = DAG.getBitcast(ExtVT, AHi);
17443 RLo = DAG.getBitcast(ExtVT, RLo);
17444 RHi = DAG.getBitcast(ExtVT, RHi);
17446 // r = VSELECT(r, shift(r, 4), a);
17447 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17448 DAG.getConstant(4, dl, ExtVT));
17449 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17450 DAG.getConstant(4, dl, ExtVT));
17451 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17452 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17455 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17456 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17458 // r = VSELECT(r, shift(r, 2), a);
17459 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17460 DAG.getConstant(2, dl, ExtVT));
17461 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17462 DAG.getConstant(2, dl, ExtVT));
17463 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17464 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17467 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17468 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17470 // r = VSELECT(r, shift(r, 1), a);
17471 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17472 DAG.getConstant(1, dl, ExtVT));
17473 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17474 DAG.getConstant(1, dl, ExtVT));
17475 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17476 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17478 // Logical shift the result back to the lower byte, leaving a zero upper
17480 // meaning that we can safely pack with PACKUSWB.
17482 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
17484 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
17485 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17489 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17490 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17491 // solution better.
17492 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17493 MVT ExtVT = MVT::v8i32;
17495 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17496 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17497 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17498 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17499 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17502 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17503 MVT ExtVT = MVT::v8i32;
17504 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17505 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17506 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17507 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17508 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17509 ALo = DAG.getBitcast(ExtVT, ALo);
17510 AHi = DAG.getBitcast(ExtVT, AHi);
17511 RLo = DAG.getBitcast(ExtVT, RLo);
17512 RHi = DAG.getBitcast(ExtVT, RHi);
17513 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17514 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17515 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17516 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17517 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17520 if (VT == MVT::v8i16) {
17521 unsigned ShiftOpcode = Op->getOpcode();
17523 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
17524 // On SSE41 targets we make use of the fact that VSELECT lowers
17525 // to PBLENDVB which selects bytes based just on the sign bit.
17526 if (Subtarget->hasSSE41()) {
17527 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
17528 V0 = DAG.getBitcast(ExtVT, V0);
17529 V1 = DAG.getBitcast(ExtVT, V1);
17530 Sel = DAG.getBitcast(ExtVT, Sel);
17531 return DAG.getBitcast(
17532 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
17534 // On pre-SSE41 targets we splat the sign bit - a negative value will
17535 // set all bits of the lanes to true and VSELECT uses that in
17536 // its OR(AND(V0,C),AND(V1,~C)) lowering.
17538 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
17539 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
17542 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
17543 if (Subtarget->hasSSE41()) {
17544 // On SSE41 targets we need to replicate the shift mask in both
17545 // bytes for PBLENDVB.
17548 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
17549 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
17551 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
17554 // r = VSELECT(r, shift(r, 8), a);
17555 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
17556 R = SignBitSelect(Amt, M, R);
17559 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17561 // r = VSELECT(r, shift(r, 4), a);
17562 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17563 R = SignBitSelect(Amt, M, R);
17566 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17568 // r = VSELECT(r, shift(r, 2), a);
17569 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17570 R = SignBitSelect(Amt, M, R);
17573 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17575 // return VSELECT(r, shift(r, 1), a);
17576 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17577 R = SignBitSelect(Amt, M, R);
17581 // Decompose 256-bit shifts into smaller 128-bit shifts.
17582 if (VT.is256BitVector()) {
17583 unsigned NumElems = VT.getVectorNumElements();
17584 MVT EltVT = VT.getVectorElementType();
17585 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17587 // Extract the two vectors
17588 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17589 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17591 // Recreate the shift amount vectors
17592 SDValue Amt1, Amt2;
17593 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17594 // Constant shift amount
17595 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17596 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17597 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17599 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17600 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17602 // Variable shift amount
17603 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17604 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17607 // Issue new vector shifts for the smaller types
17608 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17609 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17611 // Concatenate the result back
17612 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17618 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17619 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17620 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17621 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17622 // has only one use.
17623 SDNode *N = Op.getNode();
17624 SDValue LHS = N->getOperand(0);
17625 SDValue RHS = N->getOperand(1);
17626 unsigned BaseOp = 0;
17629 switch (Op.getOpcode()) {
17630 default: llvm_unreachable("Unknown ovf instruction!");
17632 // A subtract of one will be selected as a INC. Note that INC doesn't
17633 // set CF, so we can't do this for UADDO.
17634 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17636 BaseOp = X86ISD::INC;
17637 Cond = X86::COND_O;
17640 BaseOp = X86ISD::ADD;
17641 Cond = X86::COND_O;
17644 BaseOp = X86ISD::ADD;
17645 Cond = X86::COND_B;
17648 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17649 // set CF, so we can't do this for USUBO.
17650 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17652 BaseOp = X86ISD::DEC;
17653 Cond = X86::COND_O;
17656 BaseOp = X86ISD::SUB;
17657 Cond = X86::COND_O;
17660 BaseOp = X86ISD::SUB;
17661 Cond = X86::COND_B;
17664 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17665 Cond = X86::COND_O;
17667 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17668 if (N->getValueType(0) == MVT::i8) {
17669 BaseOp = X86ISD::UMUL8;
17670 Cond = X86::COND_O;
17673 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17675 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17678 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17679 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17680 SDValue(Sum.getNode(), 2));
17682 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17686 // Also sets EFLAGS.
17687 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17688 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17691 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17692 DAG.getConstant(Cond, DL, MVT::i32),
17693 SDValue(Sum.getNode(), 1));
17695 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17698 /// Returns true if the operand type is exactly twice the native width, and
17699 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17700 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17701 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17702 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17703 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17706 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17707 else if (OpWidth == 128)
17708 return Subtarget->hasCmpxchg16b();
17713 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17714 return needsCmpXchgNb(SI->getValueOperand()->getType());
17717 // Note: this turns large loads into lock cmpxchg8b/16b.
17718 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17719 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17720 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17721 return needsCmpXchgNb(PTy->getElementType());
17724 TargetLoweringBase::AtomicRMWExpansionKind
17725 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17726 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17727 const Type *MemType = AI->getType();
17729 // If the operand is too big, we must see if cmpxchg8/16b is available
17730 // and default to library calls otherwise.
17731 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17732 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17733 : AtomicRMWExpansionKind::None;
17736 AtomicRMWInst::BinOp Op = AI->getOperation();
17739 llvm_unreachable("Unknown atomic operation");
17740 case AtomicRMWInst::Xchg:
17741 case AtomicRMWInst::Add:
17742 case AtomicRMWInst::Sub:
17743 // It's better to use xadd, xsub or xchg for these in all cases.
17744 return AtomicRMWExpansionKind::None;
17745 case AtomicRMWInst::Or:
17746 case AtomicRMWInst::And:
17747 case AtomicRMWInst::Xor:
17748 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17749 // prefix to a normal instruction for these operations.
17750 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17751 : AtomicRMWExpansionKind::None;
17752 case AtomicRMWInst::Nand:
17753 case AtomicRMWInst::Max:
17754 case AtomicRMWInst::Min:
17755 case AtomicRMWInst::UMax:
17756 case AtomicRMWInst::UMin:
17757 // These always require a non-trivial set of data operations on x86. We must
17758 // use a cmpxchg loop.
17759 return AtomicRMWExpansionKind::CmpXChg;
17763 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17764 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17765 // no-sse2). There isn't any reason to disable it if the target processor
17767 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17771 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17772 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17773 const Type *MemType = AI->getType();
17774 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17775 // there is no benefit in turning such RMWs into loads, and it is actually
17776 // harmful as it introduces a mfence.
17777 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17780 auto Builder = IRBuilder<>(AI);
17781 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17782 auto SynchScope = AI->getSynchScope();
17783 // We must restrict the ordering to avoid generating loads with Release or
17784 // ReleaseAcquire orderings.
17785 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17786 auto Ptr = AI->getPointerOperand();
17788 // Before the load we need a fence. Here is an example lifted from
17789 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17792 // x.store(1, relaxed);
17793 // r1 = y.fetch_add(0, release);
17795 // y.fetch_add(42, acquire);
17796 // r2 = x.load(relaxed);
17797 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17798 // lowered to just a load without a fence. A mfence flushes the store buffer,
17799 // making the optimization clearly correct.
17800 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17801 // otherwise, we might be able to be more agressive on relaxed idempotent
17802 // rmw. In practice, they do not look useful, so we don't try to be
17803 // especially clever.
17804 if (SynchScope == SingleThread)
17805 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17806 // the IR level, so we must wrap it in an intrinsic.
17809 if (!hasMFENCE(*Subtarget))
17810 // FIXME: it might make sense to use a locked operation here but on a
17811 // different cache-line to prevent cache-line bouncing. In practice it
17812 // is probably a small win, and x86 processors without mfence are rare
17813 // enough that we do not bother.
17817 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17818 Builder.CreateCall(MFence, {});
17820 // Finally we can emit the atomic load.
17821 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17822 AI->getType()->getPrimitiveSizeInBits());
17823 Loaded->setAtomic(Order, SynchScope);
17824 AI->replaceAllUsesWith(Loaded);
17825 AI->eraseFromParent();
17829 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17830 SelectionDAG &DAG) {
17832 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17833 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17834 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17835 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17837 // The only fence that needs an instruction is a sequentially-consistent
17838 // cross-thread fence.
17839 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17840 if (hasMFENCE(*Subtarget))
17841 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17843 SDValue Chain = Op.getOperand(0);
17844 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17846 DAG.getRegister(X86::ESP, MVT::i32), // Base
17847 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17848 DAG.getRegister(0, MVT::i32), // Index
17849 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17850 DAG.getRegister(0, MVT::i32), // Segment.
17854 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17855 return SDValue(Res, 0);
17858 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17859 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17862 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17863 SelectionDAG &DAG) {
17864 MVT T = Op.getSimpleValueType();
17868 switch(T.SimpleTy) {
17869 default: llvm_unreachable("Invalid value type!");
17870 case MVT::i8: Reg = X86::AL; size = 1; break;
17871 case MVT::i16: Reg = X86::AX; size = 2; break;
17872 case MVT::i32: Reg = X86::EAX; size = 4; break;
17874 assert(Subtarget->is64Bit() && "Node not type legal!");
17875 Reg = X86::RAX; size = 8;
17878 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17879 Op.getOperand(2), SDValue());
17880 SDValue Ops[] = { cpIn.getValue(0),
17883 DAG.getTargetConstant(size, DL, MVT::i8),
17884 cpIn.getValue(1) };
17885 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17886 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17887 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17891 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17892 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17893 MVT::i32, cpOut.getValue(2));
17894 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17895 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17898 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17899 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17900 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17904 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17905 SelectionDAG &DAG) {
17906 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17907 MVT DstVT = Op.getSimpleValueType();
17909 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17910 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17911 if (DstVT != MVT::f64)
17912 // This conversion needs to be expanded.
17915 SDValue InVec = Op->getOperand(0);
17917 unsigned NumElts = SrcVT.getVectorNumElements();
17918 EVT SVT = SrcVT.getVectorElementType();
17920 // Widen the vector in input in the case of MVT::v2i32.
17921 // Example: from MVT::v2i32 to MVT::v4i32.
17922 SmallVector<SDValue, 16> Elts;
17923 for (unsigned i = 0, e = NumElts; i != e; ++i)
17924 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17925 DAG.getIntPtrConstant(i, dl)));
17927 // Explicitly mark the extra elements as Undef.
17928 Elts.append(NumElts, DAG.getUNDEF(SVT));
17930 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17931 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17932 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
17933 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17934 DAG.getIntPtrConstant(0, dl));
17937 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17938 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17939 assert((DstVT == MVT::i64 ||
17940 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17941 "Unexpected custom BITCAST");
17942 // i64 <=> MMX conversions are Legal.
17943 if (SrcVT==MVT::i64 && DstVT.isVector())
17945 if (DstVT==MVT::i64 && SrcVT.isVector())
17947 // MMX <=> MMX conversions are Legal.
17948 if (SrcVT.isVector() && DstVT.isVector())
17950 // All other conversions need to be expanded.
17954 /// Compute the horizontal sum of bytes in V for the elements of VT.
17956 /// Requires V to be a byte vector and VT to be an integer vector type with
17957 /// wider elements than V's type. The width of the elements of VT determines
17958 /// how many bytes of V are summed horizontally to produce each element of the
17960 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
17961 const X86Subtarget *Subtarget,
17962 SelectionDAG &DAG) {
17964 MVT ByteVecVT = V.getSimpleValueType();
17965 MVT EltVT = VT.getVectorElementType();
17966 int NumElts = VT.getVectorNumElements();
17967 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
17968 "Expected value to have byte element type.");
17969 assert(EltVT != MVT::i8 &&
17970 "Horizontal byte sum only makes sense for wider elements!");
17971 unsigned VecSize = VT.getSizeInBits();
17972 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
17974 // PSADBW instruction horizontally add all bytes and leave the result in i64
17975 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17976 if (EltVT == MVT::i64) {
17977 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17978 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
17979 return DAG.getBitcast(VT, V);
17982 if (EltVT == MVT::i32) {
17983 // We unpack the low half and high half into i32s interleaved with zeros so
17984 // that we can use PSADBW to horizontally sum them. The most useful part of
17985 // this is that it lines up the results of two PSADBW instructions to be
17986 // two v2i64 vectors which concatenated are the 4 population counts. We can
17987 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17988 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17989 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
17990 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
17992 // Do the horizontal sums into two v2i64s.
17993 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17994 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17995 DAG.getBitcast(ByteVecVT, Low), Zeros);
17996 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17997 DAG.getBitcast(ByteVecVT, High), Zeros);
17999 // Merge them together.
18000 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18001 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18002 DAG.getBitcast(ShortVecVT, Low),
18003 DAG.getBitcast(ShortVecVT, High));
18005 return DAG.getBitcast(VT, V);
18008 // The only element type left is i16.
18009 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18011 // To obtain pop count for each i16 element starting from the pop count for
18012 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18013 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18014 // directly supported.
18015 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18016 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18017 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18018 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18019 DAG.getBitcast(ByteVecVT, V));
18020 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18023 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18024 const X86Subtarget *Subtarget,
18025 SelectionDAG &DAG) {
18026 MVT VT = Op.getSimpleValueType();
18027 MVT EltVT = VT.getVectorElementType();
18028 unsigned VecSize = VT.getSizeInBits();
18030 // Implement a lookup table in register by using an algorithm based on:
18031 // http://wm.ite.pl/articles/sse-popcount.html
18033 // The general idea is that every lower byte nibble in the input vector is an
18034 // index into a in-register pre-computed pop count table. We then split up the
18035 // input vector in two new ones: (1) a vector with only the shifted-right
18036 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18037 // masked out higher ones) for each byte. PSHUB is used separately with both
18038 // to index the in-register table. Next, both are added and the result is a
18039 // i8 vector where each element contains the pop count for input byte.
18041 // To obtain the pop count for elements != i8, we follow up with the same
18042 // approach and use additional tricks as described below.
18044 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18045 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18046 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18047 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18049 int NumByteElts = VecSize / 8;
18050 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18051 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18052 SmallVector<SDValue, 16> LUTVec;
18053 for (int i = 0; i < NumByteElts; ++i)
18054 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18055 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18056 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18057 DAG.getConstant(0x0F, DL, MVT::i8));
18058 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18061 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18062 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18063 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18066 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18068 // The input vector is used as the shuffle mask that index elements into the
18069 // LUT. After counting low and high nibbles, add the vector to obtain the
18070 // final pop count per i8 element.
18071 SDValue HighPopCnt =
18072 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18073 SDValue LowPopCnt =
18074 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18075 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18077 if (EltVT == MVT::i8)
18080 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
18083 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
18084 const X86Subtarget *Subtarget,
18085 SelectionDAG &DAG) {
18086 MVT VT = Op.getSimpleValueType();
18087 assert(VT.is128BitVector() &&
18088 "Only 128-bit vector bitmath lowering supported.");
18090 int VecSize = VT.getSizeInBits();
18091 MVT EltVT = VT.getVectorElementType();
18092 int Len = EltVT.getSizeInBits();
18094 // This is the vectorized version of the "best" algorithm from
18095 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
18096 // with a minor tweak to use a series of adds + shifts instead of vector
18097 // multiplications. Implemented for all integer vector types. We only use
18098 // this when we don't have SSSE3 which allows a LUT-based lowering that is
18099 // much faster, even faster than using native popcnt instructions.
18101 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
18102 MVT VT = V.getSimpleValueType();
18103 SmallVector<SDValue, 32> Shifters(
18104 VT.getVectorNumElements(),
18105 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
18106 return DAG.getNode(OpCode, DL, VT, V,
18107 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
18109 auto GetMask = [&](SDValue V, APInt Mask) {
18110 MVT VT = V.getSimpleValueType();
18111 SmallVector<SDValue, 32> Masks(
18112 VT.getVectorNumElements(),
18113 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
18114 return DAG.getNode(ISD::AND, DL, VT, V,
18115 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
18118 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
18119 // x86, so set the SRL type to have elements at least i16 wide. This is
18120 // correct because all of our SRLs are followed immediately by a mask anyways
18121 // that handles any bits that sneak into the high bits of the byte elements.
18122 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
18126 // v = v - ((v >> 1) & 0x55555555...)
18128 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
18129 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
18130 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
18132 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
18133 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
18134 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
18135 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
18136 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
18138 // v = (v + (v >> 4)) & 0x0F0F0F0F...
18139 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
18140 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
18141 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
18143 // At this point, V contains the byte-wise population count, and we are
18144 // merely doing a horizontal sum if necessary to get the wider element
18146 if (EltVT == MVT::i8)
18149 return LowerHorizontalByteSum(
18150 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
18154 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18155 SelectionDAG &DAG) {
18156 MVT VT = Op.getSimpleValueType();
18157 // FIXME: Need to add AVX-512 support here!
18158 assert((VT.is256BitVector() || VT.is128BitVector()) &&
18159 "Unknown CTPOP type to handle");
18160 SDLoc DL(Op.getNode());
18161 SDValue Op0 = Op.getOperand(0);
18163 if (!Subtarget->hasSSSE3()) {
18164 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
18165 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
18166 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
18169 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
18170 unsigned NumElems = VT.getVectorNumElements();
18172 // Extract each 128-bit vector, compute pop count and concat the result.
18173 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
18174 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
18176 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
18177 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
18178 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
18181 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
18184 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18185 SelectionDAG &DAG) {
18186 assert(Op.getValueType().isVector() &&
18187 "We only do custom lowering for vector population count.");
18188 return LowerVectorCTPOP(Op, Subtarget, DAG);
18191 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18192 SDNode *Node = Op.getNode();
18194 EVT T = Node->getValueType(0);
18195 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18196 DAG.getConstant(0, dl, T), Node->getOperand(2));
18197 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18198 cast<AtomicSDNode>(Node)->getMemoryVT(),
18199 Node->getOperand(0),
18200 Node->getOperand(1), negOp,
18201 cast<AtomicSDNode>(Node)->getMemOperand(),
18202 cast<AtomicSDNode>(Node)->getOrdering(),
18203 cast<AtomicSDNode>(Node)->getSynchScope());
18206 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18207 SDNode *Node = Op.getNode();
18209 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18211 // Convert seq_cst store -> xchg
18212 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18213 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18214 // (The only way to get a 16-byte store is cmpxchg16b)
18215 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18216 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18217 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18218 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18219 cast<AtomicSDNode>(Node)->getMemoryVT(),
18220 Node->getOperand(0),
18221 Node->getOperand(1), Node->getOperand(2),
18222 cast<AtomicSDNode>(Node)->getMemOperand(),
18223 cast<AtomicSDNode>(Node)->getOrdering(),
18224 cast<AtomicSDNode>(Node)->getSynchScope());
18225 return Swap.getValue(1);
18227 // Other atomic stores have a simple pattern.
18231 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18232 EVT VT = Op.getNode()->getSimpleValueType(0);
18234 // Let legalize expand this if it isn't a legal type yet.
18235 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18238 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18241 bool ExtraOp = false;
18242 switch (Op.getOpcode()) {
18243 default: llvm_unreachable("Invalid code");
18244 case ISD::ADDC: Opc = X86ISD::ADD; break;
18245 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18246 case ISD::SUBC: Opc = X86ISD::SUB; break;
18247 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18251 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18253 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18254 Op.getOperand(1), Op.getOperand(2));
18257 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18258 SelectionDAG &DAG) {
18259 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18261 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18262 // which returns the values as { float, float } (in XMM0) or
18263 // { double, double } (which is returned in XMM0, XMM1).
18265 SDValue Arg = Op.getOperand(0);
18266 EVT ArgVT = Arg.getValueType();
18267 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18269 TargetLowering::ArgListTy Args;
18270 TargetLowering::ArgListEntry Entry;
18274 Entry.isSExt = false;
18275 Entry.isZExt = false;
18276 Args.push_back(Entry);
18278 bool isF64 = ArgVT == MVT::f64;
18279 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18280 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18281 // the results are returned via SRet in memory.
18282 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18283 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18285 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
18287 Type *RetTy = isF64
18288 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
18289 : (Type*)VectorType::get(ArgTy, 4);
18291 TargetLowering::CallLoweringInfo CLI(DAG);
18292 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18293 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18295 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18298 // Returned in xmm0 and xmm1.
18299 return CallResult.first;
18301 // Returned in bits 0:31 and 32:64 xmm0.
18302 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18303 CallResult.first, DAG.getIntPtrConstant(0, dl));
18304 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18305 CallResult.first, DAG.getIntPtrConstant(1, dl));
18306 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18307 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18310 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
18311 SelectionDAG &DAG) {
18312 assert(Subtarget->hasAVX512() &&
18313 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18315 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
18316 EVT VT = N->getValue().getValueType();
18317 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
18320 // X86 scatter kills mask register, so its type should be added to
18321 // the list of return values
18322 if (N->getNumValues() == 1) {
18323 SDValue Index = N->getIndex();
18324 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18325 !Index.getValueType().is512BitVector())
18326 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18328 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
18329 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18330 N->getOperand(3), Index };
18332 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
18333 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
18334 return SDValue(NewScatter.getNode(), 0);
18339 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
18340 SelectionDAG &DAG) {
18341 assert(Subtarget->hasAVX512() &&
18342 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18344 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
18345 EVT VT = Op.getValueType();
18346 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
18349 SDValue Index = N->getIndex();
18350 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18351 !Index.getValueType().is512BitVector()) {
18352 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18353 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18354 N->getOperand(3), Index };
18355 DAG.UpdateNodeOperands(N, Ops);
18360 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
18361 SelectionDAG &DAG) const {
18362 // TODO: Eventually, the lowering of these nodes should be informed by or
18363 // deferred to the GC strategy for the function in which they appear. For
18364 // now, however, they must be lowered to something. Since they are logically
18365 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18366 // require special handling for these nodes), lower them as literal NOOPs for
18368 SmallVector<SDValue, 2> Ops;
18370 Ops.push_back(Op.getOperand(0));
18371 if (Op->getGluedNode())
18372 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18375 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18376 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18381 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
18382 SelectionDAG &DAG) const {
18383 // TODO: Eventually, the lowering of these nodes should be informed by or
18384 // deferred to the GC strategy for the function in which they appear. For
18385 // now, however, they must be lowered to something. Since they are logically
18386 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18387 // require special handling for these nodes), lower them as literal NOOPs for
18389 SmallVector<SDValue, 2> Ops;
18391 Ops.push_back(Op.getOperand(0));
18392 if (Op->getGluedNode())
18393 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18396 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18397 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18402 /// LowerOperation - Provide custom lowering hooks for some operations.
18404 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18405 switch (Op.getOpcode()) {
18406 default: llvm_unreachable("Should not custom lower this!");
18407 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18408 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18409 return LowerCMP_SWAP(Op, Subtarget, DAG);
18410 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
18411 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18412 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18413 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18414 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
18415 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
18416 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18417 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18418 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18419 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18420 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18421 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18422 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18423 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18424 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18425 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18426 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18427 case ISD::SHL_PARTS:
18428 case ISD::SRA_PARTS:
18429 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18430 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18431 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18432 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18433 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18434 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18435 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18436 case ISD::SIGN_EXTEND_VECTOR_INREG:
18437 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
18438 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18439 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18440 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18441 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18443 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18444 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18445 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18446 case ISD::SETCC: return LowerSETCC(Op, DAG);
18447 case ISD::SELECT: return LowerSELECT(Op, DAG);
18448 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18449 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18450 case ISD::VASTART: return LowerVASTART(Op, DAG);
18451 case ISD::VAARG: return LowerVAARG(Op, DAG);
18452 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18453 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18454 case ISD::INTRINSIC_VOID:
18455 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18456 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18457 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18458 case ISD::FRAME_TO_ARGS_OFFSET:
18459 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18460 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18461 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18462 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18463 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18464 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18465 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18466 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18467 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18468 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18469 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18470 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18471 case ISD::UMUL_LOHI:
18472 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18475 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18481 case ISD::UMULO: return LowerXALUO(Op, DAG);
18482 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18483 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18487 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18488 case ISD::ADD: return LowerADD(Op, DAG);
18489 case ISD::SUB: return LowerSUB(Op, DAG);
18490 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18491 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
18492 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
18493 case ISD::GC_TRANSITION_START:
18494 return LowerGC_TRANSITION_START(Op, DAG);
18495 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
18499 /// ReplaceNodeResults - Replace a node with an illegal result type
18500 /// with a new node built out of custom code.
18501 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18502 SmallVectorImpl<SDValue>&Results,
18503 SelectionDAG &DAG) const {
18505 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18506 switch (N->getOpcode()) {
18508 llvm_unreachable("Do not know how to custom type legalize this operation!");
18509 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
18510 case X86ISD::FMINC:
18512 case X86ISD::FMAXC:
18513 case X86ISD::FMAX: {
18514 EVT VT = N->getValueType(0);
18515 if (VT != MVT::v2f32)
18516 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
18517 SDValue UNDEF = DAG.getUNDEF(VT);
18518 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18519 N->getOperand(0), UNDEF);
18520 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18521 N->getOperand(1), UNDEF);
18522 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
18525 case ISD::SIGN_EXTEND_INREG:
18530 // We don't want to expand or promote these.
18537 case ISD::UDIVREM: {
18538 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18539 Results.push_back(V);
18542 case ISD::FP_TO_SINT:
18543 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18544 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18545 if (N->getOperand(0).getValueType() == MVT::f16)
18548 case ISD::FP_TO_UINT: {
18549 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18551 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18554 std::pair<SDValue,SDValue> Vals =
18555 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18556 SDValue FIST = Vals.first, StackSlot = Vals.second;
18557 if (FIST.getNode()) {
18558 EVT VT = N->getValueType(0);
18559 // Return a load from the stack slot.
18560 if (StackSlot.getNode())
18561 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18562 MachinePointerInfo(),
18563 false, false, false, 0));
18565 Results.push_back(FIST);
18569 case ISD::UINT_TO_FP: {
18570 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18571 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18572 N->getValueType(0) != MVT::v2f32)
18574 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18576 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18578 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18579 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18580 DAG.getBitcast(MVT::v2i64, VBias));
18581 Or = DAG.getBitcast(MVT::v2f64, Or);
18582 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18583 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18586 case ISD::FP_ROUND: {
18587 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18589 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18590 Results.push_back(V);
18593 case ISD::FP_EXTEND: {
18594 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18595 // No other ValueType for FP_EXTEND should reach this point.
18596 assert(N->getValueType(0) == MVT::v2f32 &&
18597 "Do not know how to legalize this Node");
18600 case ISD::INTRINSIC_W_CHAIN: {
18601 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18603 default : llvm_unreachable("Do not know how to custom type "
18604 "legalize this intrinsic operation!");
18605 case Intrinsic::x86_rdtsc:
18606 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18608 case Intrinsic::x86_rdtscp:
18609 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18611 case Intrinsic::x86_rdpmc:
18612 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18615 case ISD::READCYCLECOUNTER: {
18616 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18619 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18620 EVT T = N->getValueType(0);
18621 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18622 bool Regs64bit = T == MVT::i128;
18623 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18624 SDValue cpInL, cpInH;
18625 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18626 DAG.getConstant(0, dl, HalfT));
18627 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18628 DAG.getConstant(1, dl, HalfT));
18629 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18630 Regs64bit ? X86::RAX : X86::EAX,
18632 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18633 Regs64bit ? X86::RDX : X86::EDX,
18634 cpInH, cpInL.getValue(1));
18635 SDValue swapInL, swapInH;
18636 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18637 DAG.getConstant(0, dl, HalfT));
18638 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18639 DAG.getConstant(1, dl, HalfT));
18640 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18641 Regs64bit ? X86::RBX : X86::EBX,
18642 swapInL, cpInH.getValue(1));
18643 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18644 Regs64bit ? X86::RCX : X86::ECX,
18645 swapInH, swapInL.getValue(1));
18646 SDValue Ops[] = { swapInH.getValue(0),
18648 swapInH.getValue(1) };
18649 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18650 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18651 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18652 X86ISD::LCMPXCHG8_DAG;
18653 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18654 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18655 Regs64bit ? X86::RAX : X86::EAX,
18656 HalfT, Result.getValue(1));
18657 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18658 Regs64bit ? X86::RDX : X86::EDX,
18659 HalfT, cpOutL.getValue(2));
18660 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18662 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18663 MVT::i32, cpOutH.getValue(2));
18665 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18666 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18667 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18669 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18670 Results.push_back(Success);
18671 Results.push_back(EFLAGS.getValue(1));
18674 case ISD::ATOMIC_SWAP:
18675 case ISD::ATOMIC_LOAD_ADD:
18676 case ISD::ATOMIC_LOAD_SUB:
18677 case ISD::ATOMIC_LOAD_AND:
18678 case ISD::ATOMIC_LOAD_OR:
18679 case ISD::ATOMIC_LOAD_XOR:
18680 case ISD::ATOMIC_LOAD_NAND:
18681 case ISD::ATOMIC_LOAD_MIN:
18682 case ISD::ATOMIC_LOAD_MAX:
18683 case ISD::ATOMIC_LOAD_UMIN:
18684 case ISD::ATOMIC_LOAD_UMAX:
18685 case ISD::ATOMIC_LOAD: {
18686 // Delegate to generic TypeLegalization. Situations we can really handle
18687 // should have already been dealt with by AtomicExpandPass.cpp.
18690 case ISD::BITCAST: {
18691 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18692 EVT DstVT = N->getValueType(0);
18693 EVT SrcVT = N->getOperand(0)->getValueType(0);
18695 if (SrcVT != MVT::f64 ||
18696 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18699 unsigned NumElts = DstVT.getVectorNumElements();
18700 EVT SVT = DstVT.getVectorElementType();
18701 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18702 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18703 MVT::v2f64, N->getOperand(0));
18704 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
18706 if (ExperimentalVectorWideningLegalization) {
18707 // If we are legalizing vectors by widening, we already have the desired
18708 // legal vector type, just return it.
18709 Results.push_back(ToVecInt);
18713 SmallVector<SDValue, 8> Elts;
18714 for (unsigned i = 0, e = NumElts; i != e; ++i)
18715 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18716 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18718 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18723 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18724 switch ((X86ISD::NodeType)Opcode) {
18725 case X86ISD::FIRST_NUMBER: break;
18726 case X86ISD::BSF: return "X86ISD::BSF";
18727 case X86ISD::BSR: return "X86ISD::BSR";
18728 case X86ISD::SHLD: return "X86ISD::SHLD";
18729 case X86ISD::SHRD: return "X86ISD::SHRD";
18730 case X86ISD::FAND: return "X86ISD::FAND";
18731 case X86ISD::FANDN: return "X86ISD::FANDN";
18732 case X86ISD::FOR: return "X86ISD::FOR";
18733 case X86ISD::FXOR: return "X86ISD::FXOR";
18734 case X86ISD::FILD: return "X86ISD::FILD";
18735 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18736 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18737 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18738 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18739 case X86ISD::FLD: return "X86ISD::FLD";
18740 case X86ISD::FST: return "X86ISD::FST";
18741 case X86ISD::CALL: return "X86ISD::CALL";
18742 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18743 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18744 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18745 case X86ISD::BT: return "X86ISD::BT";
18746 case X86ISD::CMP: return "X86ISD::CMP";
18747 case X86ISD::COMI: return "X86ISD::COMI";
18748 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18749 case X86ISD::CMPM: return "X86ISD::CMPM";
18750 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18751 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18752 case X86ISD::SETCC: return "X86ISD::SETCC";
18753 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18754 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18755 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18756 case X86ISD::CMOV: return "X86ISD::CMOV";
18757 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18758 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18759 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18760 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18761 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18762 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18763 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18764 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18765 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18766 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18767 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18768 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18769 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18770 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18771 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18772 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18773 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18774 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18775 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18776 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18777 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18778 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18779 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18780 case X86ISD::HADD: return "X86ISD::HADD";
18781 case X86ISD::HSUB: return "X86ISD::HSUB";
18782 case X86ISD::FHADD: return "X86ISD::FHADD";
18783 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18784 case X86ISD::ABS: return "X86ISD::ABS";
18785 case X86ISD::FMAX: return "X86ISD::FMAX";
18786 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18787 case X86ISD::FMIN: return "X86ISD::FMIN";
18788 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18789 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18790 case X86ISD::FMINC: return "X86ISD::FMINC";
18791 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18792 case X86ISD::FRCP: return "X86ISD::FRCP";
18793 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
18794 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
18795 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18796 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18797 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18798 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18799 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18800 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18801 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18802 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18803 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18804 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18805 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18806 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18807 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18808 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18809 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18810 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18811 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18812 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18813 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18814 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18815 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18816 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
18817 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18818 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18819 case X86ISD::VSHL: return "X86ISD::VSHL";
18820 case X86ISD::VSRL: return "X86ISD::VSRL";
18821 case X86ISD::VSRA: return "X86ISD::VSRA";
18822 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18823 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18824 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18825 case X86ISD::CMPP: return "X86ISD::CMPP";
18826 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18827 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18828 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18829 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18830 case X86ISD::ADD: return "X86ISD::ADD";
18831 case X86ISD::SUB: return "X86ISD::SUB";
18832 case X86ISD::ADC: return "X86ISD::ADC";
18833 case X86ISD::SBB: return "X86ISD::SBB";
18834 case X86ISD::SMUL: return "X86ISD::SMUL";
18835 case X86ISD::UMUL: return "X86ISD::UMUL";
18836 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18837 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18838 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18839 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18840 case X86ISD::INC: return "X86ISD::INC";
18841 case X86ISD::DEC: return "X86ISD::DEC";
18842 case X86ISD::OR: return "X86ISD::OR";
18843 case X86ISD::XOR: return "X86ISD::XOR";
18844 case X86ISD::AND: return "X86ISD::AND";
18845 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18846 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18847 case X86ISD::PTEST: return "X86ISD::PTEST";
18848 case X86ISD::TESTP: return "X86ISD::TESTP";
18849 case X86ISD::TESTM: return "X86ISD::TESTM";
18850 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18851 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18852 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18853 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18854 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18855 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18856 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18857 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18858 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18859 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18860 case X86ISD::SHUF128: return "X86ISD::SHUF128";
18861 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18862 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18863 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18864 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18865 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18866 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18867 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18868 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18869 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18870 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18871 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18872 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18873 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18874 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18875 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18876 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18877 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18878 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18879 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18880 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18881 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18882 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18883 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
18884 case X86ISD::VRANGE: return "X86ISD::VRANGE";
18885 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18886 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18887 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18888 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18889 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18890 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18891 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18892 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18893 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18894 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18895 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18896 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18897 case X86ISD::SAHF: return "X86ISD::SAHF";
18898 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18899 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18900 case X86ISD::FMADD: return "X86ISD::FMADD";
18901 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18902 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18903 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18904 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18905 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18906 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18907 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18908 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18909 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18910 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18911 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18912 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18913 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18914 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18915 case X86ISD::XTEST: return "X86ISD::XTEST";
18916 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18917 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18918 case X86ISD::SELECT: return "X86ISD::SELECT";
18919 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18920 case X86ISD::RCP28: return "X86ISD::RCP28";
18921 case X86ISD::EXP2: return "X86ISD::EXP2";
18922 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18923 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18924 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18925 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18926 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18927 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
18928 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
18929 case X86ISD::SCALEF: return "X86ISD::SCALEF";
18930 case X86ISD::ADDS: return "X86ISD::ADDS";
18931 case X86ISD::SUBS: return "X86ISD::SUBS";
18932 case X86ISD::AVG: return "X86ISD::AVG";
18933 case X86ISD::MULHRS: return "X86ISD::MULHRS";
18934 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
18935 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
18940 // isLegalAddressingMode - Return true if the addressing mode represented
18941 // by AM is legal for this target, for a load/store of the specified type.
18942 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18944 unsigned AS) const {
18945 // X86 supports extremely general addressing modes.
18946 CodeModel::Model M = getTargetMachine().getCodeModel();
18947 Reloc::Model R = getTargetMachine().getRelocationModel();
18949 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18950 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18955 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18957 // If a reference to this global requires an extra load, we can't fold it.
18958 if (isGlobalStubReference(GVFlags))
18961 // If BaseGV requires a register for the PIC base, we cannot also have a
18962 // BaseReg specified.
18963 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18966 // If lower 4G is not available, then we must use rip-relative addressing.
18967 if ((M != CodeModel::Small || R != Reloc::Static) &&
18968 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18972 switch (AM.Scale) {
18978 // These scales always work.
18983 // These scales are formed with basereg+scalereg. Only accept if there is
18988 default: // Other stuff never works.
18995 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18996 unsigned Bits = Ty->getScalarSizeInBits();
18998 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18999 // particularly cheaper than those without.
19003 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19004 // variable shifts just as cheap as scalar ones.
19005 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19008 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19009 // fully general vector.
19013 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19014 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19016 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19017 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19018 return NumBits1 > NumBits2;
19021 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19022 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19025 if (!isTypeLegal(EVT::getEVT(Ty1)))
19028 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19030 // Assuming the caller doesn't have a zeroext or signext return parameter,
19031 // truncation all the way down to i1 is valid.
19035 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19036 return isInt<32>(Imm);
19039 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19040 // Can also use sub to handle negated immediates.
19041 return isInt<32>(Imm);
19044 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19045 if (!VT1.isInteger() || !VT2.isInteger())
19047 unsigned NumBits1 = VT1.getSizeInBits();
19048 unsigned NumBits2 = VT2.getSizeInBits();
19049 return NumBits1 > NumBits2;
19052 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19053 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19054 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19057 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19058 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19059 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19062 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19063 EVT VT1 = Val.getValueType();
19064 if (isZExtFree(VT1, VT2))
19067 if (Val.getOpcode() != ISD::LOAD)
19070 if (!VT1.isSimple() || !VT1.isInteger() ||
19071 !VT2.isSimple() || !VT2.isInteger())
19074 switch (VT1.getSimpleVT().SimpleTy) {
19079 // X86 has 8, 16, and 32-bit zero-extending loads.
19086 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
19089 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19090 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
19093 VT = VT.getScalarType();
19095 if (!VT.isSimple())
19098 switch (VT.getSimpleVT().SimpleTy) {
19109 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19110 // i16 instructions are longer (0x66 prefix) and potentially slower.
19111 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19114 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19115 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19116 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19117 /// are assumed to be legal.
19119 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19121 if (!VT.isSimple())
19124 // Not for i1 vectors
19125 if (VT.getScalarType() == MVT::i1)
19128 // Very little shuffling can be done for 64-bit vectors right now.
19129 if (VT.getSizeInBits() == 64)
19132 // We only care that the types being shuffled are legal. The lowering can
19133 // handle any possible shuffle mask that results.
19134 return isTypeLegal(VT.getSimpleVT());
19138 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19140 // Just delegate to the generic legality, clear masks aren't special.
19141 return isShuffleMaskLegal(Mask, VT);
19144 //===----------------------------------------------------------------------===//
19145 // X86 Scheduler Hooks
19146 //===----------------------------------------------------------------------===//
19148 /// Utility function to emit xbegin specifying the start of an RTM region.
19149 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19150 const TargetInstrInfo *TII) {
19151 DebugLoc DL = MI->getDebugLoc();
19153 const BasicBlock *BB = MBB->getBasicBlock();
19154 MachineFunction::iterator I = MBB;
19157 // For the v = xbegin(), we generate
19168 MachineBasicBlock *thisMBB = MBB;
19169 MachineFunction *MF = MBB->getParent();
19170 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19171 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19172 MF->insert(I, mainMBB);
19173 MF->insert(I, sinkMBB);
19175 // Transfer the remainder of BB and its successor edges to sinkMBB.
19176 sinkMBB->splice(sinkMBB->begin(), MBB,
19177 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19178 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19182 // # fallthrough to mainMBB
19183 // # abortion to sinkMBB
19184 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19185 thisMBB->addSuccessor(mainMBB);
19186 thisMBB->addSuccessor(sinkMBB);
19190 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19191 mainMBB->addSuccessor(sinkMBB);
19194 // EAX is live into the sinkMBB
19195 sinkMBB->addLiveIn(X86::EAX);
19196 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19197 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19200 MI->eraseFromParent();
19204 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19205 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19206 // in the .td file.
19207 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19208 const TargetInstrInfo *TII) {
19210 switch (MI->getOpcode()) {
19211 default: llvm_unreachable("illegal opcode!");
19212 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19213 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19214 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19215 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19216 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19217 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19218 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19219 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19222 DebugLoc dl = MI->getDebugLoc();
19223 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19225 unsigned NumArgs = MI->getNumOperands();
19226 for (unsigned i = 1; i < NumArgs; ++i) {
19227 MachineOperand &Op = MI->getOperand(i);
19228 if (!(Op.isReg() && Op.isImplicit()))
19229 MIB.addOperand(Op);
19231 if (MI->hasOneMemOperand())
19232 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19234 BuildMI(*BB, MI, dl,
19235 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19236 .addReg(X86::XMM0);
19238 MI->eraseFromParent();
19242 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19243 // defs in an instruction pattern
19244 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19245 const TargetInstrInfo *TII) {
19247 switch (MI->getOpcode()) {
19248 default: llvm_unreachable("illegal opcode!");
19249 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19250 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19251 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19252 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19253 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19254 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19255 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19256 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19259 DebugLoc dl = MI->getDebugLoc();
19260 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19262 unsigned NumArgs = MI->getNumOperands(); // remove the results
19263 for (unsigned i = 1; i < NumArgs; ++i) {
19264 MachineOperand &Op = MI->getOperand(i);
19265 if (!(Op.isReg() && Op.isImplicit()))
19266 MIB.addOperand(Op);
19268 if (MI->hasOneMemOperand())
19269 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19271 BuildMI(*BB, MI, dl,
19272 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19275 MI->eraseFromParent();
19279 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19280 const X86Subtarget *Subtarget) {
19281 DebugLoc dl = MI->getDebugLoc();
19282 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19283 // Address into RAX/EAX, other two args into ECX, EDX.
19284 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19285 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19286 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19287 for (int i = 0; i < X86::AddrNumOperands; ++i)
19288 MIB.addOperand(MI->getOperand(i));
19290 unsigned ValOps = X86::AddrNumOperands;
19291 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19292 .addReg(MI->getOperand(ValOps).getReg());
19293 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19294 .addReg(MI->getOperand(ValOps+1).getReg());
19296 // The instruction doesn't actually take any operands though.
19297 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19299 MI->eraseFromParent(); // The pseudo is gone now.
19303 MachineBasicBlock *
19304 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
19305 MachineBasicBlock *MBB) const {
19306 // Emit va_arg instruction on X86-64.
19308 // Operands to this pseudo-instruction:
19309 // 0 ) Output : destination address (reg)
19310 // 1-5) Input : va_list address (addr, i64mem)
19311 // 6 ) ArgSize : Size (in bytes) of vararg type
19312 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19313 // 8 ) Align : Alignment of type
19314 // 9 ) EFLAGS (implicit-def)
19316 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19317 static_assert(X86::AddrNumOperands == 5,
19318 "VAARG_64 assumes 5 address operands");
19320 unsigned DestReg = MI->getOperand(0).getReg();
19321 MachineOperand &Base = MI->getOperand(1);
19322 MachineOperand &Scale = MI->getOperand(2);
19323 MachineOperand &Index = MI->getOperand(3);
19324 MachineOperand &Disp = MI->getOperand(4);
19325 MachineOperand &Segment = MI->getOperand(5);
19326 unsigned ArgSize = MI->getOperand(6).getImm();
19327 unsigned ArgMode = MI->getOperand(7).getImm();
19328 unsigned Align = MI->getOperand(8).getImm();
19330 // Memory Reference
19331 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19332 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19333 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19335 // Machine Information
19336 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19337 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19338 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19339 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19340 DebugLoc DL = MI->getDebugLoc();
19342 // struct va_list {
19345 // i64 overflow_area (address)
19346 // i64 reg_save_area (address)
19348 // sizeof(va_list) = 24
19349 // alignment(va_list) = 8
19351 unsigned TotalNumIntRegs = 6;
19352 unsigned TotalNumXMMRegs = 8;
19353 bool UseGPOffset = (ArgMode == 1);
19354 bool UseFPOffset = (ArgMode == 2);
19355 unsigned MaxOffset = TotalNumIntRegs * 8 +
19356 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19358 /* Align ArgSize to a multiple of 8 */
19359 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19360 bool NeedsAlign = (Align > 8);
19362 MachineBasicBlock *thisMBB = MBB;
19363 MachineBasicBlock *overflowMBB;
19364 MachineBasicBlock *offsetMBB;
19365 MachineBasicBlock *endMBB;
19367 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19368 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19369 unsigned OffsetReg = 0;
19371 if (!UseGPOffset && !UseFPOffset) {
19372 // If we only pull from the overflow region, we don't create a branch.
19373 // We don't need to alter control flow.
19374 OffsetDestReg = 0; // unused
19375 OverflowDestReg = DestReg;
19377 offsetMBB = nullptr;
19378 overflowMBB = thisMBB;
19381 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19382 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19383 // If not, pull from overflow_area. (branch to overflowMBB)
19388 // offsetMBB overflowMBB
19393 // Registers for the PHI in endMBB
19394 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19395 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19397 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19398 MachineFunction *MF = MBB->getParent();
19399 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19400 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19401 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19403 MachineFunction::iterator MBBIter = MBB;
19406 // Insert the new basic blocks
19407 MF->insert(MBBIter, offsetMBB);
19408 MF->insert(MBBIter, overflowMBB);
19409 MF->insert(MBBIter, endMBB);
19411 // Transfer the remainder of MBB and its successor edges to endMBB.
19412 endMBB->splice(endMBB->begin(), thisMBB,
19413 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19414 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19416 // Make offsetMBB and overflowMBB successors of thisMBB
19417 thisMBB->addSuccessor(offsetMBB);
19418 thisMBB->addSuccessor(overflowMBB);
19420 // endMBB is a successor of both offsetMBB and overflowMBB
19421 offsetMBB->addSuccessor(endMBB);
19422 overflowMBB->addSuccessor(endMBB);
19424 // Load the offset value into a register
19425 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19426 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19430 .addDisp(Disp, UseFPOffset ? 4 : 0)
19431 .addOperand(Segment)
19432 .setMemRefs(MMOBegin, MMOEnd);
19434 // Check if there is enough room left to pull this argument.
19435 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19437 .addImm(MaxOffset + 8 - ArgSizeA8);
19439 // Branch to "overflowMBB" if offset >= max
19440 // Fall through to "offsetMBB" otherwise
19441 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19442 .addMBB(overflowMBB);
19445 // In offsetMBB, emit code to use the reg_save_area.
19447 assert(OffsetReg != 0);
19449 // Read the reg_save_area address.
19450 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19451 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19456 .addOperand(Segment)
19457 .setMemRefs(MMOBegin, MMOEnd);
19459 // Zero-extend the offset
19460 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19461 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19464 .addImm(X86::sub_32bit);
19466 // Add the offset to the reg_save_area to get the final address.
19467 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19468 .addReg(OffsetReg64)
19469 .addReg(RegSaveReg);
19471 // Compute the offset for the next argument
19472 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19473 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19475 .addImm(UseFPOffset ? 16 : 8);
19477 // Store it back into the va_list.
19478 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19482 .addDisp(Disp, UseFPOffset ? 4 : 0)
19483 .addOperand(Segment)
19484 .addReg(NextOffsetReg)
19485 .setMemRefs(MMOBegin, MMOEnd);
19488 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
19493 // Emit code to use overflow area
19496 // Load the overflow_area address into a register.
19497 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19498 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19503 .addOperand(Segment)
19504 .setMemRefs(MMOBegin, MMOEnd);
19506 // If we need to align it, do so. Otherwise, just copy the address
19507 // to OverflowDestReg.
19509 // Align the overflow address
19510 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19511 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19513 // aligned_addr = (addr + (align-1)) & ~(align-1)
19514 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19515 .addReg(OverflowAddrReg)
19518 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19520 .addImm(~(uint64_t)(Align-1));
19522 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19523 .addReg(OverflowAddrReg);
19526 // Compute the next overflow address after this argument.
19527 // (the overflow address should be kept 8-byte aligned)
19528 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19529 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19530 .addReg(OverflowDestReg)
19531 .addImm(ArgSizeA8);
19533 // Store the new overflow address.
19534 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19539 .addOperand(Segment)
19540 .addReg(NextAddrReg)
19541 .setMemRefs(MMOBegin, MMOEnd);
19543 // If we branched, emit the PHI to the front of endMBB.
19545 BuildMI(*endMBB, endMBB->begin(), DL,
19546 TII->get(X86::PHI), DestReg)
19547 .addReg(OffsetDestReg).addMBB(offsetMBB)
19548 .addReg(OverflowDestReg).addMBB(overflowMBB);
19551 // Erase the pseudo instruction
19552 MI->eraseFromParent();
19557 MachineBasicBlock *
19558 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19560 MachineBasicBlock *MBB) const {
19561 // Emit code to save XMM registers to the stack. The ABI says that the
19562 // number of registers to save is given in %al, so it's theoretically
19563 // possible to do an indirect jump trick to avoid saving all of them,
19564 // however this code takes a simpler approach and just executes all
19565 // of the stores if %al is non-zero. It's less code, and it's probably
19566 // easier on the hardware branch predictor, and stores aren't all that
19567 // expensive anyway.
19569 // Create the new basic blocks. One block contains all the XMM stores,
19570 // and one block is the final destination regardless of whether any
19571 // stores were performed.
19572 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19573 MachineFunction *F = MBB->getParent();
19574 MachineFunction::iterator MBBIter = MBB;
19576 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19577 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19578 F->insert(MBBIter, XMMSaveMBB);
19579 F->insert(MBBIter, EndMBB);
19581 // Transfer the remainder of MBB and its successor edges to EndMBB.
19582 EndMBB->splice(EndMBB->begin(), MBB,
19583 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19584 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19586 // The original block will now fall through to the XMM save block.
19587 MBB->addSuccessor(XMMSaveMBB);
19588 // The XMMSaveMBB will fall through to the end block.
19589 XMMSaveMBB->addSuccessor(EndMBB);
19591 // Now add the instructions.
19592 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19593 DebugLoc DL = MI->getDebugLoc();
19595 unsigned CountReg = MI->getOperand(0).getReg();
19596 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19597 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19599 if (!Subtarget->isTargetWin64()) {
19600 // If %al is 0, branch around the XMM save block.
19601 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19602 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19603 MBB->addSuccessor(EndMBB);
19606 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19607 // that was just emitted, but clearly shouldn't be "saved".
19608 assert((MI->getNumOperands() <= 3 ||
19609 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19610 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19611 && "Expected last argument to be EFLAGS");
19612 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19613 // In the XMM save block, save all the XMM argument registers.
19614 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19615 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19616 MachineMemOperand *MMO =
19617 F->getMachineMemOperand(
19618 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19619 MachineMemOperand::MOStore,
19620 /*Size=*/16, /*Align=*/16);
19621 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19622 .addFrameIndex(RegSaveFrameIndex)
19623 .addImm(/*Scale=*/1)
19624 .addReg(/*IndexReg=*/0)
19625 .addImm(/*Disp=*/Offset)
19626 .addReg(/*Segment=*/0)
19627 .addReg(MI->getOperand(i).getReg())
19628 .addMemOperand(MMO);
19631 MI->eraseFromParent(); // The pseudo instruction is gone now.
19636 // The EFLAGS operand of SelectItr might be missing a kill marker
19637 // because there were multiple uses of EFLAGS, and ISel didn't know
19638 // which to mark. Figure out whether SelectItr should have had a
19639 // kill marker, and set it if it should. Returns the correct kill
19641 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19642 MachineBasicBlock* BB,
19643 const TargetRegisterInfo* TRI) {
19644 // Scan forward through BB for a use/def of EFLAGS.
19645 MachineBasicBlock::iterator miI(std::next(SelectItr));
19646 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19647 const MachineInstr& mi = *miI;
19648 if (mi.readsRegister(X86::EFLAGS))
19650 if (mi.definesRegister(X86::EFLAGS))
19651 break; // Should have kill-flag - update below.
19654 // If we hit the end of the block, check whether EFLAGS is live into a
19656 if (miI == BB->end()) {
19657 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19658 sEnd = BB->succ_end();
19659 sItr != sEnd; ++sItr) {
19660 MachineBasicBlock* succ = *sItr;
19661 if (succ->isLiveIn(X86::EFLAGS))
19666 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19667 // out. SelectMI should have a kill flag on EFLAGS.
19668 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19672 MachineBasicBlock *
19673 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19674 MachineBasicBlock *BB) const {
19675 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19676 DebugLoc DL = MI->getDebugLoc();
19678 // To "insert" a SELECT_CC instruction, we actually have to insert the
19679 // diamond control-flow pattern. The incoming instruction knows the
19680 // destination vreg to set, the condition code register to branch on, the
19681 // true/false values to select between, and a branch opcode to use.
19682 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19683 MachineFunction::iterator It = BB;
19689 // cmpTY ccX, r1, r2
19691 // fallthrough --> copy0MBB
19692 MachineBasicBlock *thisMBB = BB;
19693 MachineFunction *F = BB->getParent();
19695 // We also lower double CMOVs:
19696 // (CMOV (CMOV F, T, cc1), T, cc2)
19697 // to two successives branches. For that, we look for another CMOV as the
19698 // following instruction.
19700 // Without this, we would add a PHI between the two jumps, which ends up
19701 // creating a few copies all around. For instance, for
19703 // (sitofp (zext (fcmp une)))
19705 // we would generate:
19707 // ucomiss %xmm1, %xmm0
19708 // movss <1.0f>, %xmm0
19709 // movaps %xmm0, %xmm1
19711 // xorps %xmm1, %xmm1
19714 // movaps %xmm1, %xmm0
19718 // because this custom-inserter would have generated:
19730 // A: X = ...; Y = ...
19732 // C: Z = PHI [X, A], [Y, B]
19734 // E: PHI [X, C], [Z, D]
19736 // If we lower both CMOVs in a single step, we can instead generate:
19748 // A: X = ...; Y = ...
19750 // E: PHI [X, A], [X, C], [Y, D]
19752 // Which, in our sitofp/fcmp example, gives us something like:
19754 // ucomiss %xmm1, %xmm0
19755 // movss <1.0f>, %xmm0
19758 // xorps %xmm0, %xmm0
19762 MachineInstr *NextCMOV = nullptr;
19763 MachineBasicBlock::iterator NextMIIt =
19764 std::next(MachineBasicBlock::iterator(MI));
19765 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19766 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19767 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19768 NextCMOV = &*NextMIIt;
19770 MachineBasicBlock *jcc1MBB = nullptr;
19772 // If we have a double CMOV, we lower it to two successive branches to
19773 // the same block. EFLAGS is used by both, so mark it as live in the second.
19775 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19776 F->insert(It, jcc1MBB);
19777 jcc1MBB->addLiveIn(X86::EFLAGS);
19780 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19781 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19782 F->insert(It, copy0MBB);
19783 F->insert(It, sinkMBB);
19785 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19786 // live into the sink and copy blocks.
19787 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19789 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19790 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19791 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19792 copy0MBB->addLiveIn(X86::EFLAGS);
19793 sinkMBB->addLiveIn(X86::EFLAGS);
19796 // Transfer the remainder of BB and its successor edges to sinkMBB.
19797 sinkMBB->splice(sinkMBB->begin(), BB,
19798 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19799 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19801 // Add the true and fallthrough blocks as its successors.
19803 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19804 BB->addSuccessor(jcc1MBB);
19806 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19807 // jump to the sinkMBB.
19808 jcc1MBB->addSuccessor(copy0MBB);
19809 jcc1MBB->addSuccessor(sinkMBB);
19811 BB->addSuccessor(copy0MBB);
19814 // The true block target of the first (or only) branch is always sinkMBB.
19815 BB->addSuccessor(sinkMBB);
19817 // Create the conditional branch instruction.
19819 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19820 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19823 unsigned Opc2 = X86::GetCondBranchFromCond(
19824 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19825 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19829 // %FalseValue = ...
19830 // # fallthrough to sinkMBB
19831 copy0MBB->addSuccessor(sinkMBB);
19834 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19836 MachineInstrBuilder MIB =
19837 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19838 MI->getOperand(0).getReg())
19839 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19840 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19842 // If we have a double CMOV, the second Jcc provides the same incoming
19843 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19845 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19846 // Copy the PHI result to the register defined by the second CMOV.
19847 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19848 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19849 .addReg(MI->getOperand(0).getReg());
19850 NextCMOV->eraseFromParent();
19853 MI->eraseFromParent(); // The pseudo instruction is gone now.
19857 MachineBasicBlock *
19858 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19859 MachineBasicBlock *BB) const {
19860 MachineFunction *MF = BB->getParent();
19861 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19862 DebugLoc DL = MI->getDebugLoc();
19863 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19865 assert(MF->shouldSplitStack());
19867 const bool Is64Bit = Subtarget->is64Bit();
19868 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19870 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19871 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19874 // ... [Till the alloca]
19875 // If stacklet is not large enough, jump to mallocMBB
19878 // Allocate by subtracting from RSP
19879 // Jump to continueMBB
19882 // Allocate by call to runtime
19886 // [rest of original BB]
19889 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19890 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19891 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19893 MachineRegisterInfo &MRI = MF->getRegInfo();
19894 const TargetRegisterClass *AddrRegClass =
19895 getRegClassFor(getPointerTy(MF->getDataLayout()));
19897 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19898 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19899 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19900 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19901 sizeVReg = MI->getOperand(1).getReg(),
19902 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19904 MachineFunction::iterator MBBIter = BB;
19907 MF->insert(MBBIter, bumpMBB);
19908 MF->insert(MBBIter, mallocMBB);
19909 MF->insert(MBBIter, continueMBB);
19911 continueMBB->splice(continueMBB->begin(), BB,
19912 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19913 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19915 // Add code to the main basic block to check if the stack limit has been hit,
19916 // and if so, jump to mallocMBB otherwise to bumpMBB.
19917 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19918 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19919 .addReg(tmpSPVReg).addReg(sizeVReg);
19920 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19921 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19922 .addReg(SPLimitVReg);
19923 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19925 // bumpMBB simply decreases the stack pointer, since we know the current
19926 // stacklet has enough space.
19927 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19928 .addReg(SPLimitVReg);
19929 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19930 .addReg(SPLimitVReg);
19931 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19933 // Calls into a routine in libgcc to allocate more space from the heap.
19934 const uint32_t *RegMask =
19935 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19937 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19939 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19940 .addExternalSymbol("__morestack_allocate_stack_space")
19941 .addRegMask(RegMask)
19942 .addReg(X86::RDI, RegState::Implicit)
19943 .addReg(X86::RAX, RegState::ImplicitDefine);
19944 } else if (Is64Bit) {
19945 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19947 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19948 .addExternalSymbol("__morestack_allocate_stack_space")
19949 .addRegMask(RegMask)
19950 .addReg(X86::EDI, RegState::Implicit)
19951 .addReg(X86::EAX, RegState::ImplicitDefine);
19953 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19955 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19956 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19957 .addExternalSymbol("__morestack_allocate_stack_space")
19958 .addRegMask(RegMask)
19959 .addReg(X86::EAX, RegState::ImplicitDefine);
19963 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19966 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19967 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19968 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19970 // Set up the CFG correctly.
19971 BB->addSuccessor(bumpMBB);
19972 BB->addSuccessor(mallocMBB);
19973 mallocMBB->addSuccessor(continueMBB);
19974 bumpMBB->addSuccessor(continueMBB);
19976 // Take care of the PHI nodes.
19977 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19978 MI->getOperand(0).getReg())
19979 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19980 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19982 // Delete the original pseudo instruction.
19983 MI->eraseFromParent();
19986 return continueMBB;
19989 MachineBasicBlock *
19990 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19991 MachineBasicBlock *BB) const {
19992 DebugLoc DL = MI->getDebugLoc();
19994 assert(!Subtarget->isTargetMachO());
19996 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
19999 MI->eraseFromParent(); // The pseudo instruction is gone now.
20003 MachineBasicBlock *
20004 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20005 MachineBasicBlock *BB) const {
20006 // This is pretty easy. We're taking the value that we received from
20007 // our load from the relocation, sticking it in either RDI (x86-64)
20008 // or EAX and doing an indirect call. The return value will then
20009 // be in the normal return register.
20010 MachineFunction *F = BB->getParent();
20011 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20012 DebugLoc DL = MI->getDebugLoc();
20014 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20015 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20017 // Get a register mask for the lowered call.
20018 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20019 // proper register mask.
20020 const uint32_t *RegMask =
20021 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
20022 if (Subtarget->is64Bit()) {
20023 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20024 TII->get(X86::MOV64rm), X86::RDI)
20026 .addImm(0).addReg(0)
20027 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20028 MI->getOperand(3).getTargetFlags())
20030 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20031 addDirectMem(MIB, X86::RDI);
20032 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20033 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20034 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20035 TII->get(X86::MOV32rm), X86::EAX)
20037 .addImm(0).addReg(0)
20038 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20039 MI->getOperand(3).getTargetFlags())
20041 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20042 addDirectMem(MIB, X86::EAX);
20043 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20045 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20046 TII->get(X86::MOV32rm), X86::EAX)
20047 .addReg(TII->getGlobalBaseReg(F))
20048 .addImm(0).addReg(0)
20049 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20050 MI->getOperand(3).getTargetFlags())
20052 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20053 addDirectMem(MIB, X86::EAX);
20054 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20057 MI->eraseFromParent(); // The pseudo instruction is gone now.
20061 MachineBasicBlock *
20062 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20063 MachineBasicBlock *MBB) const {
20064 DebugLoc DL = MI->getDebugLoc();
20065 MachineFunction *MF = MBB->getParent();
20066 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20067 MachineRegisterInfo &MRI = MF->getRegInfo();
20069 const BasicBlock *BB = MBB->getBasicBlock();
20070 MachineFunction::iterator I = MBB;
20073 // Memory Reference
20074 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20075 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20078 unsigned MemOpndSlot = 0;
20080 unsigned CurOp = 0;
20082 DstReg = MI->getOperand(CurOp++).getReg();
20083 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20084 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20085 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20086 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20088 MemOpndSlot = CurOp;
20090 MVT PVT = getPointerTy(MF->getDataLayout());
20091 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20092 "Invalid Pointer Size!");
20094 // For v = setjmp(buf), we generate
20097 // buf[LabelOffset] = restoreMBB
20098 // SjLjSetup restoreMBB
20104 // v = phi(main, restore)
20107 // if base pointer being used, load it from frame
20110 MachineBasicBlock *thisMBB = MBB;
20111 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20112 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20113 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20114 MF->insert(I, mainMBB);
20115 MF->insert(I, sinkMBB);
20116 MF->push_back(restoreMBB);
20118 MachineInstrBuilder MIB;
20120 // Transfer the remainder of BB and its successor edges to sinkMBB.
20121 sinkMBB->splice(sinkMBB->begin(), MBB,
20122 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20123 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20126 unsigned PtrStoreOpc = 0;
20127 unsigned LabelReg = 0;
20128 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20129 Reloc::Model RM = MF->getTarget().getRelocationModel();
20130 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20131 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20133 // Prepare IP either in reg or imm.
20134 if (!UseImmLabel) {
20135 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20136 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20137 LabelReg = MRI.createVirtualRegister(PtrRC);
20138 if (Subtarget->is64Bit()) {
20139 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20143 .addMBB(restoreMBB)
20146 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20147 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20148 .addReg(XII->getGlobalBaseReg(MF))
20151 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20155 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20157 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20158 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20159 if (i == X86::AddrDisp)
20160 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20162 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20165 MIB.addReg(LabelReg);
20167 MIB.addMBB(restoreMBB);
20168 MIB.setMemRefs(MMOBegin, MMOEnd);
20170 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20171 .addMBB(restoreMBB);
20173 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20174 MIB.addRegMask(RegInfo->getNoPreservedMask());
20175 thisMBB->addSuccessor(mainMBB);
20176 thisMBB->addSuccessor(restoreMBB);
20180 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20181 mainMBB->addSuccessor(sinkMBB);
20184 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20185 TII->get(X86::PHI), DstReg)
20186 .addReg(mainDstReg).addMBB(mainMBB)
20187 .addReg(restoreDstReg).addMBB(restoreMBB);
20190 if (RegInfo->hasBasePointer(*MF)) {
20191 const bool Uses64BitFramePtr =
20192 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
20193 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
20194 X86FI->setRestoreBasePointer(MF);
20195 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
20196 unsigned BasePtr = RegInfo->getBaseRegister();
20197 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
20198 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
20199 FramePtr, true, X86FI->getRestoreBasePointerOffset())
20200 .setMIFlag(MachineInstr::FrameSetup);
20202 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20203 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
20204 restoreMBB->addSuccessor(sinkMBB);
20206 MI->eraseFromParent();
20210 MachineBasicBlock *
20211 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20212 MachineBasicBlock *MBB) const {
20213 DebugLoc DL = MI->getDebugLoc();
20214 MachineFunction *MF = MBB->getParent();
20215 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20216 MachineRegisterInfo &MRI = MF->getRegInfo();
20218 // Memory Reference
20219 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20220 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20222 MVT PVT = getPointerTy(MF->getDataLayout());
20223 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20224 "Invalid Pointer Size!");
20226 const TargetRegisterClass *RC =
20227 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20228 unsigned Tmp = MRI.createVirtualRegister(RC);
20229 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20230 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20231 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20232 unsigned SP = RegInfo->getStackRegister();
20234 MachineInstrBuilder MIB;
20236 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20237 const int64_t SPOffset = 2 * PVT.getStoreSize();
20239 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20240 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20243 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20244 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20245 MIB.addOperand(MI->getOperand(i));
20246 MIB.setMemRefs(MMOBegin, MMOEnd);
20248 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20249 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20250 if (i == X86::AddrDisp)
20251 MIB.addDisp(MI->getOperand(i), LabelOffset);
20253 MIB.addOperand(MI->getOperand(i));
20255 MIB.setMemRefs(MMOBegin, MMOEnd);
20257 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20258 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20259 if (i == X86::AddrDisp)
20260 MIB.addDisp(MI->getOperand(i), SPOffset);
20262 MIB.addOperand(MI->getOperand(i));
20264 MIB.setMemRefs(MMOBegin, MMOEnd);
20266 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20268 MI->eraseFromParent();
20272 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20273 // accumulator loops. Writing back to the accumulator allows the coalescer
20274 // to remove extra copies in the loop.
20275 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
20276 MachineBasicBlock *
20277 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20278 MachineBasicBlock *MBB) const {
20279 MachineOperand &AddendOp = MI->getOperand(3);
20281 // Bail out early if the addend isn't a register - we can't switch these.
20282 if (!AddendOp.isReg())
20285 MachineFunction &MF = *MBB->getParent();
20286 MachineRegisterInfo &MRI = MF.getRegInfo();
20288 // Check whether the addend is defined by a PHI:
20289 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20290 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20291 if (!AddendDef.isPHI())
20294 // Look for the following pattern:
20296 // %addend = phi [%entry, 0], [%loop, %result]
20298 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20302 // %addend = phi [%entry, 0], [%loop, %result]
20304 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20306 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20307 assert(AddendDef.getOperand(i).isReg());
20308 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20309 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20310 if (&PHISrcInst == MI) {
20311 // Found a matching instruction.
20312 unsigned NewFMAOpc = 0;
20313 switch (MI->getOpcode()) {
20314 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20315 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20316 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20317 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20318 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20319 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20320 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20321 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20322 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20323 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20324 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20325 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20326 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20327 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20328 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20329 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20330 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20331 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20332 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20333 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20335 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20336 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20337 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20338 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20339 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20340 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20341 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20342 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20343 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20344 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20345 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20346 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20347 default: llvm_unreachable("Unrecognized FMA variant.");
20350 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
20351 MachineInstrBuilder MIB =
20352 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20353 .addOperand(MI->getOperand(0))
20354 .addOperand(MI->getOperand(3))
20355 .addOperand(MI->getOperand(2))
20356 .addOperand(MI->getOperand(1));
20357 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20358 MI->eraseFromParent();
20365 MachineBasicBlock *
20366 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20367 MachineBasicBlock *BB) const {
20368 switch (MI->getOpcode()) {
20369 default: llvm_unreachable("Unexpected instr type to insert");
20370 case X86::TAILJMPd64:
20371 case X86::TAILJMPr64:
20372 case X86::TAILJMPm64:
20373 case X86::TAILJMPd64_REX:
20374 case X86::TAILJMPr64_REX:
20375 case X86::TAILJMPm64_REX:
20376 llvm_unreachable("TAILJMP64 would not be touched here.");
20377 case X86::TCRETURNdi64:
20378 case X86::TCRETURNri64:
20379 case X86::TCRETURNmi64:
20381 case X86::WIN_ALLOCA:
20382 return EmitLoweredWinAlloca(MI, BB);
20383 case X86::SEG_ALLOCA_32:
20384 case X86::SEG_ALLOCA_64:
20385 return EmitLoweredSegAlloca(MI, BB);
20386 case X86::TLSCall_32:
20387 case X86::TLSCall_64:
20388 return EmitLoweredTLSCall(MI, BB);
20389 case X86::CMOV_GR8:
20390 case X86::CMOV_FR32:
20391 case X86::CMOV_FR64:
20392 case X86::CMOV_V4F32:
20393 case X86::CMOV_V2F64:
20394 case X86::CMOV_V2I64:
20395 case X86::CMOV_V8F32:
20396 case X86::CMOV_V4F64:
20397 case X86::CMOV_V4I64:
20398 case X86::CMOV_V16F32:
20399 case X86::CMOV_V8F64:
20400 case X86::CMOV_V8I64:
20401 case X86::CMOV_GR16:
20402 case X86::CMOV_GR32:
20403 case X86::CMOV_RFP32:
20404 case X86::CMOV_RFP64:
20405 case X86::CMOV_RFP80:
20406 case X86::CMOV_V8I1:
20407 case X86::CMOV_V16I1:
20408 case X86::CMOV_V32I1:
20409 case X86::CMOV_V64I1:
20410 return EmitLoweredSelect(MI, BB);
20412 case X86::FP32_TO_INT16_IN_MEM:
20413 case X86::FP32_TO_INT32_IN_MEM:
20414 case X86::FP32_TO_INT64_IN_MEM:
20415 case X86::FP64_TO_INT16_IN_MEM:
20416 case X86::FP64_TO_INT32_IN_MEM:
20417 case X86::FP64_TO_INT64_IN_MEM:
20418 case X86::FP80_TO_INT16_IN_MEM:
20419 case X86::FP80_TO_INT32_IN_MEM:
20420 case X86::FP80_TO_INT64_IN_MEM: {
20421 MachineFunction *F = BB->getParent();
20422 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20423 DebugLoc DL = MI->getDebugLoc();
20425 // Change the floating point control register to use "round towards zero"
20426 // mode when truncating to an integer value.
20427 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20428 addFrameReference(BuildMI(*BB, MI, DL,
20429 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20431 // Load the old value of the high byte of the control word...
20433 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20434 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20437 // Set the high part to be round to zero...
20438 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20441 // Reload the modified control word now...
20442 addFrameReference(BuildMI(*BB, MI, DL,
20443 TII->get(X86::FLDCW16m)), CWFrameIdx);
20445 // Restore the memory image of control word to original value
20446 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20449 // Get the X86 opcode to use.
20451 switch (MI->getOpcode()) {
20452 default: llvm_unreachable("illegal opcode!");
20453 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20454 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20455 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20456 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20457 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20458 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20459 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20460 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20461 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20465 MachineOperand &Op = MI->getOperand(0);
20467 AM.BaseType = X86AddressMode::RegBase;
20468 AM.Base.Reg = Op.getReg();
20470 AM.BaseType = X86AddressMode::FrameIndexBase;
20471 AM.Base.FrameIndex = Op.getIndex();
20473 Op = MI->getOperand(1);
20475 AM.Scale = Op.getImm();
20476 Op = MI->getOperand(2);
20478 AM.IndexReg = Op.getImm();
20479 Op = MI->getOperand(3);
20480 if (Op.isGlobal()) {
20481 AM.GV = Op.getGlobal();
20483 AM.Disp = Op.getImm();
20485 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20486 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20488 // Reload the original control word now.
20489 addFrameReference(BuildMI(*BB, MI, DL,
20490 TII->get(X86::FLDCW16m)), CWFrameIdx);
20492 MI->eraseFromParent(); // The pseudo instruction is gone now.
20495 // String/text processing lowering.
20496 case X86::PCMPISTRM128REG:
20497 case X86::VPCMPISTRM128REG:
20498 case X86::PCMPISTRM128MEM:
20499 case X86::VPCMPISTRM128MEM:
20500 case X86::PCMPESTRM128REG:
20501 case X86::VPCMPESTRM128REG:
20502 case X86::PCMPESTRM128MEM:
20503 case X86::VPCMPESTRM128MEM:
20504 assert(Subtarget->hasSSE42() &&
20505 "Target must have SSE4.2 or AVX features enabled");
20506 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
20508 // String/text processing lowering.
20509 case X86::PCMPISTRIREG:
20510 case X86::VPCMPISTRIREG:
20511 case X86::PCMPISTRIMEM:
20512 case X86::VPCMPISTRIMEM:
20513 case X86::PCMPESTRIREG:
20514 case X86::VPCMPESTRIREG:
20515 case X86::PCMPESTRIMEM:
20516 case X86::VPCMPESTRIMEM:
20517 assert(Subtarget->hasSSE42() &&
20518 "Target must have SSE4.2 or AVX features enabled");
20519 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
20521 // Thread synchronization.
20523 return EmitMonitor(MI, BB, Subtarget);
20527 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
20529 case X86::VASTART_SAVE_XMM_REGS:
20530 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20532 case X86::VAARG_64:
20533 return EmitVAARG64WithCustomInserter(MI, BB);
20535 case X86::EH_SjLj_SetJmp32:
20536 case X86::EH_SjLj_SetJmp64:
20537 return emitEHSjLjSetJmp(MI, BB);
20539 case X86::EH_SjLj_LongJmp32:
20540 case X86::EH_SjLj_LongJmp64:
20541 return emitEHSjLjLongJmp(MI, BB);
20543 case TargetOpcode::STATEPOINT:
20544 // As an implementation detail, STATEPOINT shares the STACKMAP format at
20545 // this point in the process. We diverge later.
20546 return emitPatchPoint(MI, BB);
20548 case TargetOpcode::STACKMAP:
20549 case TargetOpcode::PATCHPOINT:
20550 return emitPatchPoint(MI, BB);
20552 case X86::VFMADDPDr213r:
20553 case X86::VFMADDPSr213r:
20554 case X86::VFMADDSDr213r:
20555 case X86::VFMADDSSr213r:
20556 case X86::VFMSUBPDr213r:
20557 case X86::VFMSUBPSr213r:
20558 case X86::VFMSUBSDr213r:
20559 case X86::VFMSUBSSr213r:
20560 case X86::VFNMADDPDr213r:
20561 case X86::VFNMADDPSr213r:
20562 case X86::VFNMADDSDr213r:
20563 case X86::VFNMADDSSr213r:
20564 case X86::VFNMSUBPDr213r:
20565 case X86::VFNMSUBPSr213r:
20566 case X86::VFNMSUBSDr213r:
20567 case X86::VFNMSUBSSr213r:
20568 case X86::VFMADDSUBPDr213r:
20569 case X86::VFMADDSUBPSr213r:
20570 case X86::VFMSUBADDPDr213r:
20571 case X86::VFMSUBADDPSr213r:
20572 case X86::VFMADDPDr213rY:
20573 case X86::VFMADDPSr213rY:
20574 case X86::VFMSUBPDr213rY:
20575 case X86::VFMSUBPSr213rY:
20576 case X86::VFNMADDPDr213rY:
20577 case X86::VFNMADDPSr213rY:
20578 case X86::VFNMSUBPDr213rY:
20579 case X86::VFNMSUBPSr213rY:
20580 case X86::VFMADDSUBPDr213rY:
20581 case X86::VFMADDSUBPSr213rY:
20582 case X86::VFMSUBADDPDr213rY:
20583 case X86::VFMSUBADDPSr213rY:
20584 return emitFMA3Instr(MI, BB);
20588 //===----------------------------------------------------------------------===//
20589 // X86 Optimization Hooks
20590 //===----------------------------------------------------------------------===//
20592 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20595 const SelectionDAG &DAG,
20596 unsigned Depth) const {
20597 unsigned BitWidth = KnownZero.getBitWidth();
20598 unsigned Opc = Op.getOpcode();
20599 assert((Opc >= ISD::BUILTIN_OP_END ||
20600 Opc == ISD::INTRINSIC_WO_CHAIN ||
20601 Opc == ISD::INTRINSIC_W_CHAIN ||
20602 Opc == ISD::INTRINSIC_VOID) &&
20603 "Should use MaskedValueIsZero if you don't know whether Op"
20604 " is a target node!");
20606 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20620 // These nodes' second result is a boolean.
20621 if (Op.getResNo() == 0)
20624 case X86ISD::SETCC:
20625 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20627 case ISD::INTRINSIC_WO_CHAIN: {
20628 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20629 unsigned NumLoBits = 0;
20632 case Intrinsic::x86_sse_movmsk_ps:
20633 case Intrinsic::x86_avx_movmsk_ps_256:
20634 case Intrinsic::x86_sse2_movmsk_pd:
20635 case Intrinsic::x86_avx_movmsk_pd_256:
20636 case Intrinsic::x86_mmx_pmovmskb:
20637 case Intrinsic::x86_sse2_pmovmskb_128:
20638 case Intrinsic::x86_avx2_pmovmskb: {
20639 // High bits of movmskp{s|d}, pmovmskb are known zero.
20641 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20642 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20643 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20644 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20645 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20646 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20647 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20648 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20650 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20659 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20661 const SelectionDAG &,
20662 unsigned Depth) const {
20663 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20664 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20665 return Op.getValueType().getScalarType().getSizeInBits();
20671 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20672 /// node is a GlobalAddress + offset.
20673 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20674 const GlobalValue* &GA,
20675 int64_t &Offset) const {
20676 if (N->getOpcode() == X86ISD::Wrapper) {
20677 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20678 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20679 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20683 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20686 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20687 /// same as extracting the high 128-bit part of 256-bit vector and then
20688 /// inserting the result into the low part of a new 256-bit vector
20689 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20690 EVT VT = SVOp->getValueType(0);
20691 unsigned NumElems = VT.getVectorNumElements();
20693 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20694 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20695 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20696 SVOp->getMaskElt(j) >= 0)
20702 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20703 /// same as extracting the low 128-bit part of 256-bit vector and then
20704 /// inserting the result into the high part of a new 256-bit vector
20705 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20706 EVT VT = SVOp->getValueType(0);
20707 unsigned NumElems = VT.getVectorNumElements();
20709 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20710 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20711 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20712 SVOp->getMaskElt(j) >= 0)
20718 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20719 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20720 TargetLowering::DAGCombinerInfo &DCI,
20721 const X86Subtarget* Subtarget) {
20723 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20724 SDValue V1 = SVOp->getOperand(0);
20725 SDValue V2 = SVOp->getOperand(1);
20726 EVT VT = SVOp->getValueType(0);
20727 unsigned NumElems = VT.getVectorNumElements();
20729 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20730 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20734 // V UNDEF BUILD_VECTOR UNDEF
20736 // CONCAT_VECTOR CONCAT_VECTOR
20739 // RESULT: V + zero extended
20741 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20742 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20743 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20746 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20749 // To match the shuffle mask, the first half of the mask should
20750 // be exactly the first vector, and all the rest a splat with the
20751 // first element of the second one.
20752 for (unsigned i = 0; i != NumElems/2; ++i)
20753 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20754 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20757 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20758 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20759 if (Ld->hasNUsesOfValue(1, 0)) {
20760 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20761 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20763 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20765 Ld->getPointerInfo(),
20766 Ld->getAlignment(),
20767 false/*isVolatile*/, true/*ReadMem*/,
20768 false/*WriteMem*/);
20770 // Make sure the newly-created LOAD is in the same position as Ld in
20771 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20772 // and update uses of Ld's output chain to use the TokenFactor.
20773 if (Ld->hasAnyUseOfValue(1)) {
20774 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20775 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20776 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20777 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20778 SDValue(ResNode.getNode(), 1));
20781 return DAG.getBitcast(VT, ResNode);
20785 // Emit a zeroed vector and insert the desired subvector on its
20787 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20788 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20789 return DCI.CombineTo(N, InsV);
20792 //===--------------------------------------------------------------------===//
20793 // Combine some shuffles into subvector extracts and inserts:
20796 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20797 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20798 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20799 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20800 return DCI.CombineTo(N, InsV);
20803 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20804 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20805 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20806 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20807 return DCI.CombineTo(N, InsV);
20813 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20816 /// This is the leaf of the recursive combinine below. When we have found some
20817 /// chain of single-use x86 shuffle instructions and accumulated the combined
20818 /// shuffle mask represented by them, this will try to pattern match that mask
20819 /// into either a single instruction if there is a special purpose instruction
20820 /// for this operation, or into a PSHUFB instruction which is a fully general
20821 /// instruction but should only be used to replace chains over a certain depth.
20822 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20823 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20824 TargetLowering::DAGCombinerInfo &DCI,
20825 const X86Subtarget *Subtarget) {
20826 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20828 // Find the operand that enters the chain. Note that multiple uses are OK
20829 // here, we're not going to remove the operand we find.
20830 SDValue Input = Op.getOperand(0);
20831 while (Input.getOpcode() == ISD::BITCAST)
20832 Input = Input.getOperand(0);
20834 MVT VT = Input.getSimpleValueType();
20835 MVT RootVT = Root.getSimpleValueType();
20838 // Just remove no-op shuffle masks.
20839 if (Mask.size() == 1) {
20840 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
20845 // Use the float domain if the operand type is a floating point type.
20846 bool FloatDomain = VT.isFloatingPoint();
20848 // For floating point shuffles, we don't have free copies in the shuffle
20849 // instructions or the ability to load as part of the instruction, so
20850 // canonicalize their shuffles to UNPCK or MOV variants.
20852 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20853 // vectors because it can have a load folded into it that UNPCK cannot. This
20854 // doesn't preclude something switching to the shorter encoding post-RA.
20856 // FIXME: Should teach these routines about AVX vector widths.
20857 if (FloatDomain && VT.getSizeInBits() == 128) {
20858 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20859 bool Lo = Mask.equals({0, 0});
20862 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20863 // is no slower than UNPCKLPD but has the option to fold the input operand
20864 // into even an unaligned memory load.
20865 if (Lo && Subtarget->hasSSE3()) {
20866 Shuffle = X86ISD::MOVDDUP;
20867 ShuffleVT = MVT::v2f64;
20869 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20870 // than the UNPCK variants.
20871 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20872 ShuffleVT = MVT::v4f32;
20874 if (Depth == 1 && Root->getOpcode() == Shuffle)
20875 return false; // Nothing to do!
20876 Op = DAG.getBitcast(ShuffleVT, Input);
20877 DCI.AddToWorklist(Op.getNode());
20878 if (Shuffle == X86ISD::MOVDDUP)
20879 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20881 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20882 DCI.AddToWorklist(Op.getNode());
20883 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20887 if (Subtarget->hasSSE3() &&
20888 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20889 bool Lo = Mask.equals({0, 0, 2, 2});
20890 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20891 MVT ShuffleVT = MVT::v4f32;
20892 if (Depth == 1 && Root->getOpcode() == Shuffle)
20893 return false; // Nothing to do!
20894 Op = DAG.getBitcast(ShuffleVT, Input);
20895 DCI.AddToWorklist(Op.getNode());
20896 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20897 DCI.AddToWorklist(Op.getNode());
20898 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20902 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20903 bool Lo = Mask.equals({0, 0, 1, 1});
20904 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20905 MVT ShuffleVT = MVT::v4f32;
20906 if (Depth == 1 && Root->getOpcode() == Shuffle)
20907 return false; // Nothing to do!
20908 Op = DAG.getBitcast(ShuffleVT, Input);
20909 DCI.AddToWorklist(Op.getNode());
20910 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20911 DCI.AddToWorklist(Op.getNode());
20912 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20918 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20919 // variants as none of these have single-instruction variants that are
20920 // superior to the UNPCK formulation.
20921 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20922 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20923 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20924 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20926 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20927 bool Lo = Mask[0] == 0;
20928 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20929 if (Depth == 1 && Root->getOpcode() == Shuffle)
20930 return false; // Nothing to do!
20932 switch (Mask.size()) {
20934 ShuffleVT = MVT::v8i16;
20937 ShuffleVT = MVT::v16i8;
20940 llvm_unreachable("Impossible mask size!");
20942 Op = DAG.getBitcast(ShuffleVT, Input);
20943 DCI.AddToWorklist(Op.getNode());
20944 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20945 DCI.AddToWorklist(Op.getNode());
20946 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20951 // Don't try to re-form single instruction chains under any circumstances now
20952 // that we've done encoding canonicalization for them.
20956 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20957 // can replace them with a single PSHUFB instruction profitably. Intel's
20958 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20959 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20960 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20961 SmallVector<SDValue, 16> PSHUFBMask;
20962 int NumBytes = VT.getSizeInBits() / 8;
20963 int Ratio = NumBytes / Mask.size();
20964 for (int i = 0; i < NumBytes; ++i) {
20965 if (Mask[i / Ratio] == SM_SentinelUndef) {
20966 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20969 int M = Mask[i / Ratio] != SM_SentinelZero
20970 ? Ratio * Mask[i / Ratio] + i % Ratio
20972 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20974 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20975 Op = DAG.getBitcast(ByteVT, Input);
20976 DCI.AddToWorklist(Op.getNode());
20977 SDValue PSHUFBMaskOp =
20978 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20979 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20980 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20981 DCI.AddToWorklist(Op.getNode());
20982 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20987 // Failed to find any combines.
20991 /// \brief Fully generic combining of x86 shuffle instructions.
20993 /// This should be the last combine run over the x86 shuffle instructions. Once
20994 /// they have been fully optimized, this will recursively consider all chains
20995 /// of single-use shuffle instructions, build a generic model of the cumulative
20996 /// shuffle operation, and check for simpler instructions which implement this
20997 /// operation. We use this primarily for two purposes:
20999 /// 1) Collapse generic shuffles to specialized single instructions when
21000 /// equivalent. In most cases, this is just an encoding size win, but
21001 /// sometimes we will collapse multiple generic shuffles into a single
21002 /// special-purpose shuffle.
21003 /// 2) Look for sequences of shuffle instructions with 3 or more total
21004 /// instructions, and replace them with the slightly more expensive SSSE3
21005 /// PSHUFB instruction if available. We do this as the last combining step
21006 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21007 /// a suitable short sequence of other instructions. The PHUFB will either
21008 /// use a register or have to read from memory and so is slightly (but only
21009 /// slightly) more expensive than the other shuffle instructions.
21011 /// Because this is inherently a quadratic operation (for each shuffle in
21012 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21013 /// This should never be an issue in practice as the shuffle lowering doesn't
21014 /// produce sequences of more than 8 instructions.
21016 /// FIXME: We will currently miss some cases where the redundant shuffling
21017 /// would simplify under the threshold for PSHUFB formation because of
21018 /// combine-ordering. To fix this, we should do the redundant instruction
21019 /// combining in this recursive walk.
21020 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21021 ArrayRef<int> RootMask,
21022 int Depth, bool HasPSHUFB,
21024 TargetLowering::DAGCombinerInfo &DCI,
21025 const X86Subtarget *Subtarget) {
21026 // Bound the depth of our recursive combine because this is ultimately
21027 // quadratic in nature.
21031 // Directly rip through bitcasts to find the underlying operand.
21032 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21033 Op = Op.getOperand(0);
21035 MVT VT = Op.getSimpleValueType();
21036 if (!VT.isVector())
21037 return false; // Bail if we hit a non-vector.
21039 assert(Root.getSimpleValueType().isVector() &&
21040 "Shuffles operate on vector types!");
21041 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21042 "Can only combine shuffles of the same vector register size.");
21044 if (!isTargetShuffle(Op.getOpcode()))
21046 SmallVector<int, 16> OpMask;
21048 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21049 // We only can combine unary shuffles which we can decode the mask for.
21050 if (!HaveMask || !IsUnary)
21053 assert(VT.getVectorNumElements() == OpMask.size() &&
21054 "Different mask size from vector size!");
21055 assert(((RootMask.size() > OpMask.size() &&
21056 RootMask.size() % OpMask.size() == 0) ||
21057 (OpMask.size() > RootMask.size() &&
21058 OpMask.size() % RootMask.size() == 0) ||
21059 OpMask.size() == RootMask.size()) &&
21060 "The smaller number of elements must divide the larger.");
21061 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21062 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21063 assert(((RootRatio == 1 && OpRatio == 1) ||
21064 (RootRatio == 1) != (OpRatio == 1)) &&
21065 "Must not have a ratio for both incoming and op masks!");
21067 SmallVector<int, 16> Mask;
21068 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21070 // Merge this shuffle operation's mask into our accumulated mask. Note that
21071 // this shuffle's mask will be the first applied to the input, followed by the
21072 // root mask to get us all the way to the root value arrangement. The reason
21073 // for this order is that we are recursing up the operation chain.
21074 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21075 int RootIdx = i / RootRatio;
21076 if (RootMask[RootIdx] < 0) {
21077 // This is a zero or undef lane, we're done.
21078 Mask.push_back(RootMask[RootIdx]);
21082 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21083 int OpIdx = RootMaskedIdx / OpRatio;
21084 if (OpMask[OpIdx] < 0) {
21085 // The incoming lanes are zero or undef, it doesn't matter which ones we
21087 Mask.push_back(OpMask[OpIdx]);
21091 // Ok, we have non-zero lanes, map them through.
21092 Mask.push_back(OpMask[OpIdx] * OpRatio +
21093 RootMaskedIdx % OpRatio);
21096 // See if we can recurse into the operand to combine more things.
21097 switch (Op.getOpcode()) {
21098 case X86ISD::PSHUFB:
21100 case X86ISD::PSHUFD:
21101 case X86ISD::PSHUFHW:
21102 case X86ISD::PSHUFLW:
21103 if (Op.getOperand(0).hasOneUse() &&
21104 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21105 HasPSHUFB, DAG, DCI, Subtarget))
21109 case X86ISD::UNPCKL:
21110 case X86ISD::UNPCKH:
21111 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21112 // We can't check for single use, we have to check that this shuffle is the only user.
21113 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21114 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21115 HasPSHUFB, DAG, DCI, Subtarget))
21120 // Minor canonicalization of the accumulated shuffle mask to make it easier
21121 // to match below. All this does is detect masks with squential pairs of
21122 // elements, and shrink them to the half-width mask. It does this in a loop
21123 // so it will reduce the size of the mask to the minimal width mask which
21124 // performs an equivalent shuffle.
21125 SmallVector<int, 16> WidenedMask;
21126 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21127 Mask = std::move(WidenedMask);
21128 WidenedMask.clear();
21131 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21135 /// \brief Get the PSHUF-style mask from PSHUF node.
21137 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21138 /// PSHUF-style masks that can be reused with such instructions.
21139 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21140 MVT VT = N.getSimpleValueType();
21141 SmallVector<int, 4> Mask;
21143 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
21147 // If we have more than 128-bits, only the low 128-bits of shuffle mask
21148 // matter. Check that the upper masks are repeats and remove them.
21149 if (VT.getSizeInBits() > 128) {
21150 int LaneElts = 128 / VT.getScalarSizeInBits();
21152 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
21153 for (int j = 0; j < LaneElts; ++j)
21154 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
21155 "Mask doesn't repeat in high 128-bit lanes!");
21157 Mask.resize(LaneElts);
21160 switch (N.getOpcode()) {
21161 case X86ISD::PSHUFD:
21163 case X86ISD::PSHUFLW:
21166 case X86ISD::PSHUFHW:
21167 Mask.erase(Mask.begin(), Mask.begin() + 4);
21168 for (int &M : Mask)
21172 llvm_unreachable("No valid shuffle instruction found!");
21176 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21178 /// We walk up the chain and look for a combinable shuffle, skipping over
21179 /// shuffles that we could hoist this shuffle's transformation past without
21180 /// altering anything.
21182 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21184 TargetLowering::DAGCombinerInfo &DCI) {
21185 assert(N.getOpcode() == X86ISD::PSHUFD &&
21186 "Called with something other than an x86 128-bit half shuffle!");
21189 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21190 // of the shuffles in the chain so that we can form a fresh chain to replace
21192 SmallVector<SDValue, 8> Chain;
21193 SDValue V = N.getOperand(0);
21194 for (; V.hasOneUse(); V = V.getOperand(0)) {
21195 switch (V.getOpcode()) {
21197 return SDValue(); // Nothing combined!
21200 // Skip bitcasts as we always know the type for the target specific
21204 case X86ISD::PSHUFD:
21205 // Found another dword shuffle.
21208 case X86ISD::PSHUFLW:
21209 // Check that the low words (being shuffled) are the identity in the
21210 // dword shuffle, and the high words are self-contained.
21211 if (Mask[0] != 0 || Mask[1] != 1 ||
21212 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21215 Chain.push_back(V);
21218 case X86ISD::PSHUFHW:
21219 // Check that the high words (being shuffled) are the identity in the
21220 // dword shuffle, and the low words are self-contained.
21221 if (Mask[2] != 2 || Mask[3] != 3 ||
21222 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21225 Chain.push_back(V);
21228 case X86ISD::UNPCKL:
21229 case X86ISD::UNPCKH:
21230 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21231 // shuffle into a preceding word shuffle.
21232 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
21233 V.getSimpleValueType().getScalarType() != MVT::i16)
21236 // Search for a half-shuffle which we can combine with.
21237 unsigned CombineOp =
21238 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21239 if (V.getOperand(0) != V.getOperand(1) ||
21240 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21242 Chain.push_back(V);
21243 V = V.getOperand(0);
21245 switch (V.getOpcode()) {
21247 return SDValue(); // Nothing to combine.
21249 case X86ISD::PSHUFLW:
21250 case X86ISD::PSHUFHW:
21251 if (V.getOpcode() == CombineOp)
21254 Chain.push_back(V);
21258 V = V.getOperand(0);
21262 } while (V.hasOneUse());
21265 // Break out of the loop if we break out of the switch.
21269 if (!V.hasOneUse())
21270 // We fell out of the loop without finding a viable combining instruction.
21273 // Merge this node's mask and our incoming mask.
21274 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21275 for (int &M : Mask)
21277 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21278 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21280 // Rebuild the chain around this new shuffle.
21281 while (!Chain.empty()) {
21282 SDValue W = Chain.pop_back_val();
21284 if (V.getValueType() != W.getOperand(0).getValueType())
21285 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
21287 switch (W.getOpcode()) {
21289 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21291 case X86ISD::UNPCKL:
21292 case X86ISD::UNPCKH:
21293 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21296 case X86ISD::PSHUFD:
21297 case X86ISD::PSHUFLW:
21298 case X86ISD::PSHUFHW:
21299 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21303 if (V.getValueType() != N.getValueType())
21304 V = DAG.getBitcast(N.getValueType(), V);
21306 // Return the new chain to replace N.
21310 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21312 /// We walk up the chain, skipping shuffles of the other half and looking
21313 /// through shuffles which switch halves trying to find a shuffle of the same
21314 /// pair of dwords.
21315 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21317 TargetLowering::DAGCombinerInfo &DCI) {
21319 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21320 "Called with something other than an x86 128-bit half shuffle!");
21322 unsigned CombineOpcode = N.getOpcode();
21324 // Walk up a single-use chain looking for a combinable shuffle.
21325 SDValue V = N.getOperand(0);
21326 for (; V.hasOneUse(); V = V.getOperand(0)) {
21327 switch (V.getOpcode()) {
21329 return false; // Nothing combined!
21332 // Skip bitcasts as we always know the type for the target specific
21336 case X86ISD::PSHUFLW:
21337 case X86ISD::PSHUFHW:
21338 if (V.getOpcode() == CombineOpcode)
21341 // Other-half shuffles are no-ops.
21344 // Break out of the loop if we break out of the switch.
21348 if (!V.hasOneUse())
21349 // We fell out of the loop without finding a viable combining instruction.
21352 // Combine away the bottom node as its shuffle will be accumulated into
21353 // a preceding shuffle.
21354 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21356 // Record the old value.
21359 // Merge this node's mask and our incoming mask (adjusted to account for all
21360 // the pshufd instructions encountered).
21361 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21362 for (int &M : Mask)
21364 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21365 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21367 // Check that the shuffles didn't cancel each other out. If not, we need to
21368 // combine to the new one.
21370 // Replace the combinable shuffle with the combined one, updating all users
21371 // so that we re-evaluate the chain here.
21372 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21377 /// \brief Try to combine x86 target specific shuffles.
21378 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21379 TargetLowering::DAGCombinerInfo &DCI,
21380 const X86Subtarget *Subtarget) {
21382 MVT VT = N.getSimpleValueType();
21383 SmallVector<int, 4> Mask;
21385 switch (N.getOpcode()) {
21386 case X86ISD::PSHUFD:
21387 case X86ISD::PSHUFLW:
21388 case X86ISD::PSHUFHW:
21389 Mask = getPSHUFShuffleMask(N);
21390 assert(Mask.size() == 4);
21396 // Nuke no-op shuffles that show up after combining.
21397 if (isNoopShuffleMask(Mask))
21398 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21400 // Look for simplifications involving one or two shuffle instructions.
21401 SDValue V = N.getOperand(0);
21402 switch (N.getOpcode()) {
21405 case X86ISD::PSHUFLW:
21406 case X86ISD::PSHUFHW:
21407 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
21409 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21410 return SDValue(); // We combined away this shuffle, so we're done.
21412 // See if this reduces to a PSHUFD which is no more expensive and can
21413 // combine with more operations. Note that it has to at least flip the
21414 // dwords as otherwise it would have been removed as a no-op.
21415 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
21416 int DMask[] = {0, 1, 2, 3};
21417 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21418 DMask[DOffset + 0] = DOffset + 1;
21419 DMask[DOffset + 1] = DOffset + 0;
21420 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
21421 V = DAG.getBitcast(DVT, V);
21422 DCI.AddToWorklist(V.getNode());
21423 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
21424 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
21425 DCI.AddToWorklist(V.getNode());
21426 return DAG.getBitcast(VT, V);
21429 // Look for shuffle patterns which can be implemented as a single unpack.
21430 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21431 // only works when we have a PSHUFD followed by two half-shuffles.
21432 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21433 (V.getOpcode() == X86ISD::PSHUFLW ||
21434 V.getOpcode() == X86ISD::PSHUFHW) &&
21435 V.getOpcode() != N.getOpcode() &&
21437 SDValue D = V.getOperand(0);
21438 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21439 D = D.getOperand(0);
21440 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21441 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21442 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21443 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21444 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21446 for (int i = 0; i < 4; ++i) {
21447 WordMask[i + NOffset] = Mask[i] + NOffset;
21448 WordMask[i + VOffset] = VMask[i] + VOffset;
21450 // Map the word mask through the DWord mask.
21452 for (int i = 0; i < 8; ++i)
21453 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21454 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21455 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
21456 // We can replace all three shuffles with an unpack.
21457 V = DAG.getBitcast(VT, D.getOperand(0));
21458 DCI.AddToWorklist(V.getNode());
21459 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21468 case X86ISD::PSHUFD:
21469 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21478 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21480 /// We combine this directly on the abstract vector shuffle nodes so it is
21481 /// easier to generically match. We also insert dummy vector shuffle nodes for
21482 /// the operands which explicitly discard the lanes which are unused by this
21483 /// operation to try to flow through the rest of the combiner the fact that
21484 /// they're unused.
21485 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21487 EVT VT = N->getValueType(0);
21489 // We only handle target-independent shuffles.
21490 // FIXME: It would be easy and harmless to use the target shuffle mask
21491 // extraction tool to support more.
21492 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21495 auto *SVN = cast<ShuffleVectorSDNode>(N);
21496 ArrayRef<int> Mask = SVN->getMask();
21497 SDValue V1 = N->getOperand(0);
21498 SDValue V2 = N->getOperand(1);
21500 // We require the first shuffle operand to be the SUB node, and the second to
21501 // be the ADD node.
21502 // FIXME: We should support the commuted patterns.
21503 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21506 // If there are other uses of these operations we can't fold them.
21507 if (!V1->hasOneUse() || !V2->hasOneUse())
21510 // Ensure that both operations have the same operands. Note that we can
21511 // commute the FADD operands.
21512 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21513 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21514 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21517 // We're looking for blends between FADD and FSUB nodes. We insist on these
21518 // nodes being lined up in a specific expected pattern.
21519 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
21520 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
21521 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
21524 // Only specific types are legal at this point, assert so we notice if and
21525 // when these change.
21526 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21527 VT == MVT::v4f64) &&
21528 "Unknown vector type encountered!");
21530 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21533 /// PerformShuffleCombine - Performs several different shuffle combines.
21534 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21535 TargetLowering::DAGCombinerInfo &DCI,
21536 const X86Subtarget *Subtarget) {
21538 SDValue N0 = N->getOperand(0);
21539 SDValue N1 = N->getOperand(1);
21540 EVT VT = N->getValueType(0);
21542 // Don't create instructions with illegal types after legalize types has run.
21543 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21544 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21547 // If we have legalized the vector types, look for blends of FADD and FSUB
21548 // nodes that we can fuse into an ADDSUB node.
21549 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21550 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21553 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21554 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21555 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21556 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21558 // During Type Legalization, when promoting illegal vector types,
21559 // the backend might introduce new shuffle dag nodes and bitcasts.
21561 // This code performs the following transformation:
21562 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21563 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21565 // We do this only if both the bitcast and the BINOP dag nodes have
21566 // one use. Also, perform this transformation only if the new binary
21567 // operation is legal. This is to avoid introducing dag nodes that
21568 // potentially need to be further expanded (or custom lowered) into a
21569 // less optimal sequence of dag nodes.
21570 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21571 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21572 N0.getOpcode() == ISD::BITCAST) {
21573 SDValue BC0 = N0.getOperand(0);
21574 EVT SVT = BC0.getValueType();
21575 unsigned Opcode = BC0.getOpcode();
21576 unsigned NumElts = VT.getVectorNumElements();
21578 if (BC0.hasOneUse() && SVT.isVector() &&
21579 SVT.getVectorNumElements() * 2 == NumElts &&
21580 TLI.isOperationLegal(Opcode, VT)) {
21581 bool CanFold = false;
21593 unsigned SVTNumElts = SVT.getVectorNumElements();
21594 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21595 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21596 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21597 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21598 CanFold = SVOp->getMaskElt(i) < 0;
21601 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
21602 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
21603 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21604 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21609 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21610 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21611 // consecutive, non-overlapping, and in the right order.
21612 SmallVector<SDValue, 16> Elts;
21613 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21614 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21616 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
21619 if (isTargetShuffle(N->getOpcode())) {
21621 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21622 if (Shuffle.getNode())
21625 // Try recursively combining arbitrary sequences of x86 shuffle
21626 // instructions into higher-order shuffles. We do this after combining
21627 // specific PSHUF instruction sequences into their minimal form so that we
21628 // can evaluate how many specialized shuffle instructions are involved in
21629 // a particular chain.
21630 SmallVector<int, 1> NonceMask; // Just a placeholder.
21631 NonceMask.push_back(0);
21632 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21633 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21635 return SDValue(); // This routine will use CombineTo to replace N.
21641 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21642 /// specific shuffle of a load can be folded into a single element load.
21643 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21644 /// shuffles have been custom lowered so we need to handle those here.
21645 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21646 TargetLowering::DAGCombinerInfo &DCI) {
21647 if (DCI.isBeforeLegalizeOps())
21650 SDValue InVec = N->getOperand(0);
21651 SDValue EltNo = N->getOperand(1);
21653 if (!isa<ConstantSDNode>(EltNo))
21656 EVT OriginalVT = InVec.getValueType();
21658 if (InVec.getOpcode() == ISD::BITCAST) {
21659 // Don't duplicate a load with other uses.
21660 if (!InVec.hasOneUse())
21662 EVT BCVT = InVec.getOperand(0).getValueType();
21663 if (!BCVT.isVector() ||
21664 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21666 InVec = InVec.getOperand(0);
21669 EVT CurrentVT = InVec.getValueType();
21671 if (!isTargetShuffle(InVec.getOpcode()))
21674 // Don't duplicate a load with other uses.
21675 if (!InVec.hasOneUse())
21678 SmallVector<int, 16> ShuffleMask;
21680 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21681 ShuffleMask, UnaryShuffle))
21684 // Select the input vector, guarding against out of range extract vector.
21685 unsigned NumElems = CurrentVT.getVectorNumElements();
21686 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21687 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21688 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21689 : InVec.getOperand(1);
21691 // If inputs to shuffle are the same for both ops, then allow 2 uses
21692 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21693 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21695 if (LdNode.getOpcode() == ISD::BITCAST) {
21696 // Don't duplicate a load with other uses.
21697 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21700 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21701 LdNode = LdNode.getOperand(0);
21704 if (!ISD::isNormalLoad(LdNode.getNode()))
21707 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21709 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21712 EVT EltVT = N->getValueType(0);
21713 // If there's a bitcast before the shuffle, check if the load type and
21714 // alignment is valid.
21715 unsigned Align = LN0->getAlignment();
21716 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21717 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21718 EltVT.getTypeForEVT(*DAG.getContext()));
21720 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21723 // All checks match so transform back to vector_shuffle so that DAG combiner
21724 // can finish the job
21727 // Create shuffle node taking into account the case that its a unary shuffle
21728 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21729 : InVec.getOperand(1);
21730 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21731 InVec.getOperand(0), Shuffle,
21733 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
21734 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21738 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21739 /// special and don't usually play with other vector types, it's better to
21740 /// handle them early to be sure we emit efficient code by avoiding
21741 /// store-load conversions.
21742 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21743 if (N->getValueType(0) != MVT::x86mmx ||
21744 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21745 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21748 SDValue V = N->getOperand(0);
21749 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21750 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21751 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21752 N->getValueType(0), V.getOperand(0));
21757 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21758 /// generation and convert it from being a bunch of shuffles and extracts
21759 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21760 /// storing the value and loading scalars back, while for x64 we should
21761 /// use 64-bit extracts and shifts.
21762 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21763 TargetLowering::DAGCombinerInfo &DCI) {
21764 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
21767 SDValue InputVector = N->getOperand(0);
21768 SDLoc dl(InputVector);
21769 // Detect mmx to i32 conversion through a v2i32 elt extract.
21770 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21771 N->getValueType(0) == MVT::i32 &&
21772 InputVector.getValueType() == MVT::v2i32) {
21774 // The bitcast source is a direct mmx result.
21775 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21776 if (MMXSrc.getValueType() == MVT::x86mmx)
21777 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21778 N->getValueType(0),
21779 InputVector.getNode()->getOperand(0));
21781 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21782 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21783 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21784 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21785 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21786 MMXSrcOp.getValueType() == MVT::v1i64 &&
21787 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21788 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21789 N->getValueType(0),
21790 MMXSrcOp.getOperand(0));
21793 EVT VT = N->getValueType(0);
21795 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21796 InputVector.getOpcode() == ISD::BITCAST &&
21797 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21798 uint64_t ExtractedElt =
21799 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21800 uint64_t InputValue =
21801 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21802 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21803 return DAG.getConstant(Res, dl, MVT::i1);
21805 // Only operate on vectors of 4 elements, where the alternative shuffling
21806 // gets to be more expensive.
21807 if (InputVector.getValueType() != MVT::v4i32)
21810 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21811 // single use which is a sign-extend or zero-extend, and all elements are
21813 SmallVector<SDNode *, 4> Uses;
21814 unsigned ExtractedElements = 0;
21815 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21816 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21817 if (UI.getUse().getResNo() != InputVector.getResNo())
21820 SDNode *Extract = *UI;
21821 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21824 if (Extract->getValueType(0) != MVT::i32)
21826 if (!Extract->hasOneUse())
21828 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21829 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21831 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21834 // Record which element was extracted.
21835 ExtractedElements |=
21836 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21838 Uses.push_back(Extract);
21841 // If not all the elements were used, this may not be worthwhile.
21842 if (ExtractedElements != 15)
21845 // Ok, we've now decided to do the transformation.
21846 // If 64-bit shifts are legal, use the extract-shift sequence,
21847 // otherwise bounce the vector off the cache.
21848 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21851 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21852 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
21853 auto &DL = DAG.getDataLayout();
21854 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
21855 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21856 DAG.getConstant(0, dl, VecIdxTy));
21857 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21858 DAG.getConstant(1, dl, VecIdxTy));
21860 SDValue ShAmt = DAG.getConstant(
21861 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
21862 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21863 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21864 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21865 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21866 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21867 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21869 // Store the value to a temporary stack slot.
21870 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21871 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21872 MachinePointerInfo(), false, false, 0);
21874 EVT ElementType = InputVector.getValueType().getVectorElementType();
21875 unsigned EltSize = ElementType.getSizeInBits() / 8;
21877 // Replace each use (extract) with a load of the appropriate element.
21878 for (unsigned i = 0; i < 4; ++i) {
21879 uint64_t Offset = EltSize * i;
21880 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
21881 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
21883 SDValue ScalarAddr =
21884 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
21886 // Load the scalar.
21887 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21888 ScalarAddr, MachinePointerInfo(),
21889 false, false, false, 0);
21894 // Replace the extracts
21895 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21896 UE = Uses.end(); UI != UE; ++UI) {
21897 SDNode *Extract = *UI;
21899 SDValue Idx = Extract->getOperand(1);
21900 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21901 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21904 // The replacement was made in place; don't return anything.
21908 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21909 static std::pair<unsigned, bool>
21910 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21911 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21912 if (!VT.isVector())
21913 return std::make_pair(0, false);
21915 bool NeedSplit = false;
21916 switch (VT.getSimpleVT().SimpleTy) {
21917 default: return std::make_pair(0, false);
21920 if (!Subtarget->hasVLX())
21921 return std::make_pair(0, false);
21925 if (!Subtarget->hasBWI())
21926 return std::make_pair(0, false);
21930 if (!Subtarget->hasAVX512())
21931 return std::make_pair(0, false);
21936 if (!Subtarget->hasAVX2())
21938 if (!Subtarget->hasAVX())
21939 return std::make_pair(0, false);
21944 if (!Subtarget->hasSSE2())
21945 return std::make_pair(0, false);
21948 // SSE2 has only a small subset of the operations.
21949 bool hasUnsigned = Subtarget->hasSSE41() ||
21950 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21951 bool hasSigned = Subtarget->hasSSE41() ||
21952 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21954 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21957 // Check for x CC y ? x : y.
21958 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21959 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21964 Opc = hasUnsigned ? ISD::UMIN : 0; break;
21967 Opc = hasUnsigned ? ISD::UMAX : 0; break;
21970 Opc = hasSigned ? ISD::SMIN : 0; break;
21973 Opc = hasSigned ? ISD::SMAX : 0; break;
21975 // Check for x CC y ? y : x -- a min/max with reversed arms.
21976 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21977 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21982 Opc = hasUnsigned ? ISD::UMAX : 0; break;
21985 Opc = hasUnsigned ? ISD::UMIN : 0; break;
21988 Opc = hasSigned ? ISD::SMAX : 0; break;
21991 Opc = hasSigned ? ISD::SMIN : 0; break;
21995 return std::make_pair(Opc, NeedSplit);
21999 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22000 const X86Subtarget *Subtarget) {
22002 SDValue Cond = N->getOperand(0);
22003 SDValue LHS = N->getOperand(1);
22004 SDValue RHS = N->getOperand(2);
22006 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22007 SDValue CondSrc = Cond->getOperand(0);
22008 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22009 Cond = CondSrc->getOperand(0);
22012 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22015 // A vselect where all conditions and data are constants can be optimized into
22016 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22017 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22018 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22021 unsigned MaskValue = 0;
22022 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22025 MVT VT = N->getSimpleValueType(0);
22026 unsigned NumElems = VT.getVectorNumElements();
22027 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22028 for (unsigned i = 0; i < NumElems; ++i) {
22029 // Be sure we emit undef where we can.
22030 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22031 ShuffleMask[i] = -1;
22033 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22036 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22037 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22039 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22042 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22044 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22045 TargetLowering::DAGCombinerInfo &DCI,
22046 const X86Subtarget *Subtarget) {
22048 SDValue Cond = N->getOperand(0);
22049 // Get the LHS/RHS of the select.
22050 SDValue LHS = N->getOperand(1);
22051 SDValue RHS = N->getOperand(2);
22052 EVT VT = LHS.getValueType();
22053 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22055 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22056 // instructions match the semantics of the common C idiom x<y?x:y but not
22057 // x<=y?x:y, because of how they handle negative zero (which can be
22058 // ignored in unsafe-math mode).
22059 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
22060 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22061 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
22062 (Subtarget->hasSSE2() ||
22063 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22064 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22066 unsigned Opcode = 0;
22067 // Check for x CC y ? x : y.
22068 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22069 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22073 // Converting this to a min would handle NaNs incorrectly, and swapping
22074 // the operands would cause it to handle comparisons between positive
22075 // and negative zero incorrectly.
22076 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22077 if (!DAG.getTarget().Options.UnsafeFPMath &&
22078 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22080 std::swap(LHS, RHS);
22082 Opcode = X86ISD::FMIN;
22085 // Converting this to a min would handle comparisons between positive
22086 // and negative zero incorrectly.
22087 if (!DAG.getTarget().Options.UnsafeFPMath &&
22088 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22090 Opcode = X86ISD::FMIN;
22093 // Converting this to a min would handle both negative zeros and NaNs
22094 // incorrectly, but we can swap the operands to fix both.
22095 std::swap(LHS, RHS);
22099 Opcode = X86ISD::FMIN;
22103 // Converting this to a max would handle comparisons between positive
22104 // and negative zero incorrectly.
22105 if (!DAG.getTarget().Options.UnsafeFPMath &&
22106 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22108 Opcode = X86ISD::FMAX;
22111 // Converting this to a max would handle NaNs incorrectly, and swapping
22112 // the operands would cause it to handle comparisons between positive
22113 // and negative zero incorrectly.
22114 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22115 if (!DAG.getTarget().Options.UnsafeFPMath &&
22116 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22118 std::swap(LHS, RHS);
22120 Opcode = X86ISD::FMAX;
22123 // Converting this to a max would handle both negative zeros and NaNs
22124 // incorrectly, but we can swap the operands to fix both.
22125 std::swap(LHS, RHS);
22129 Opcode = X86ISD::FMAX;
22132 // Check for x CC y ? y : x -- a min/max with reversed arms.
22133 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22134 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22138 // Converting this to a min would handle comparisons between positive
22139 // and negative zero incorrectly, and swapping the operands would
22140 // cause it to handle NaNs incorrectly.
22141 if (!DAG.getTarget().Options.UnsafeFPMath &&
22142 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22143 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22145 std::swap(LHS, RHS);
22147 Opcode = X86ISD::FMIN;
22150 // Converting this to a min would handle NaNs incorrectly.
22151 if (!DAG.getTarget().Options.UnsafeFPMath &&
22152 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22154 Opcode = X86ISD::FMIN;
22157 // Converting this to a min would handle both negative zeros and NaNs
22158 // incorrectly, but we can swap the operands to fix both.
22159 std::swap(LHS, RHS);
22163 Opcode = X86ISD::FMIN;
22167 // Converting this to a max would handle NaNs incorrectly.
22168 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22170 Opcode = X86ISD::FMAX;
22173 // Converting this to a max would handle comparisons between positive
22174 // and negative zero incorrectly, and swapping the operands would
22175 // cause it to handle NaNs incorrectly.
22176 if (!DAG.getTarget().Options.UnsafeFPMath &&
22177 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22178 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22180 std::swap(LHS, RHS);
22182 Opcode = X86ISD::FMAX;
22185 // Converting this to a max would handle both negative zeros and NaNs
22186 // incorrectly, but we can swap the operands to fix both.
22187 std::swap(LHS, RHS);
22191 Opcode = X86ISD::FMAX;
22197 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22200 EVT CondVT = Cond.getValueType();
22201 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22202 CondVT.getVectorElementType() == MVT::i1) {
22203 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22204 // lowering on KNL. In this case we convert it to
22205 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22206 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22207 // Since SKX these selects have a proper lowering.
22208 EVT OpVT = LHS.getValueType();
22209 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22210 (OpVT.getVectorElementType() == MVT::i8 ||
22211 OpVT.getVectorElementType() == MVT::i16) &&
22212 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22213 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22214 DCI.AddToWorklist(Cond.getNode());
22215 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22218 // If this is a select between two integer constants, try to do some
22220 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22221 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22222 // Don't do this for crazy integer types.
22223 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22224 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22225 // so that TrueC (the true value) is larger than FalseC.
22226 bool NeedsCondInvert = false;
22228 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22229 // Efficiently invertible.
22230 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22231 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22232 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22233 NeedsCondInvert = true;
22234 std::swap(TrueC, FalseC);
22237 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22238 if (FalseC->getAPIntValue() == 0 &&
22239 TrueC->getAPIntValue().isPowerOf2()) {
22240 if (NeedsCondInvert) // Invert the condition if needed.
22241 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22242 DAG.getConstant(1, DL, Cond.getValueType()));
22244 // Zero extend the condition if needed.
22245 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22247 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22248 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22249 DAG.getConstant(ShAmt, DL, MVT::i8));
22252 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22253 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22254 if (NeedsCondInvert) // Invert the condition if needed.
22255 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22256 DAG.getConstant(1, DL, Cond.getValueType()));
22258 // Zero extend the condition if needed.
22259 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22260 FalseC->getValueType(0), Cond);
22261 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22262 SDValue(FalseC, 0));
22265 // Optimize cases that will turn into an LEA instruction. This requires
22266 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22267 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22268 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22269 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22271 bool isFastMultiplier = false;
22273 switch ((unsigned char)Diff) {
22275 case 1: // result = add base, cond
22276 case 2: // result = lea base( , cond*2)
22277 case 3: // result = lea base(cond, cond*2)
22278 case 4: // result = lea base( , cond*4)
22279 case 5: // result = lea base(cond, cond*4)
22280 case 8: // result = lea base( , cond*8)
22281 case 9: // result = lea base(cond, cond*8)
22282 isFastMultiplier = true;
22287 if (isFastMultiplier) {
22288 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22289 if (NeedsCondInvert) // Invert the condition if needed.
22290 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22291 DAG.getConstant(1, DL, Cond.getValueType()));
22293 // Zero extend the condition if needed.
22294 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22296 // Scale the condition by the difference.
22298 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22299 DAG.getConstant(Diff, DL,
22300 Cond.getValueType()));
22302 // Add the base if non-zero.
22303 if (FalseC->getAPIntValue() != 0)
22304 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22305 SDValue(FalseC, 0));
22312 // Canonicalize max and min:
22313 // (x > y) ? x : y -> (x >= y) ? x : y
22314 // (x < y) ? x : y -> (x <= y) ? x : y
22315 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22316 // the need for an extra compare
22317 // against zero. e.g.
22318 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22320 // testl %edi, %edi
22322 // cmovgl %edi, %eax
22326 // cmovsl %eax, %edi
22327 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22328 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22329 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22330 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22335 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22336 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22337 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22338 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22343 // Early exit check
22344 if (!TLI.isTypeLegal(VT))
22347 // Match VSELECTs into subs with unsigned saturation.
22348 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22349 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22350 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22351 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22352 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22354 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22355 // left side invert the predicate to simplify logic below.
22357 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22359 CC = ISD::getSetCCInverse(CC, true);
22360 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22364 if (Other.getNode() && Other->getNumOperands() == 2 &&
22365 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22366 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22367 SDValue CondRHS = Cond->getOperand(1);
22369 // Look for a general sub with unsigned saturation first.
22370 // x >= y ? x-y : 0 --> subus x, y
22371 // x > y ? x-y : 0 --> subus x, y
22372 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22373 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22374 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22376 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22377 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22378 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22379 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22380 // If the RHS is a constant we have to reverse the const
22381 // canonicalization.
22382 // x > C-1 ? x+-C : 0 --> subus x, C
22383 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22384 CondRHSConst->getAPIntValue() ==
22385 (-OpRHSConst->getAPIntValue() - 1))
22386 return DAG.getNode(
22387 X86ISD::SUBUS, DL, VT, OpLHS,
22388 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
22390 // Another special case: If C was a sign bit, the sub has been
22391 // canonicalized into a xor.
22392 // FIXME: Would it be better to use computeKnownBits to determine
22393 // whether it's safe to decanonicalize the xor?
22394 // x s< 0 ? x^C : 0 --> subus x, C
22395 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22396 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22397 OpRHSConst->getAPIntValue().isSignBit())
22398 // Note that we have to rebuild the RHS constant here to ensure we
22399 // don't rely on particular values of undef lanes.
22400 return DAG.getNode(
22401 X86ISD::SUBUS, DL, VT, OpLHS,
22402 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
22407 // Try to match a min/max vector operation.
22408 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22409 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22410 unsigned Opc = ret.first;
22411 bool NeedSplit = ret.second;
22413 if (Opc && NeedSplit) {
22414 unsigned NumElems = VT.getVectorNumElements();
22415 // Extract the LHS vectors
22416 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22417 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22419 // Extract the RHS vectors
22420 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22421 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22423 // Create min/max for each subvector
22424 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22425 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22427 // Merge the result
22428 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22430 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22433 // Simplify vector selection if condition value type matches vselect
22435 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22436 assert(Cond.getValueType().isVector() &&
22437 "vector select expects a vector selector!");
22439 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22440 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22442 // Try invert the condition if true value is not all 1s and false value
22444 if (!TValIsAllOnes && !FValIsAllZeros &&
22445 // Check if the selector will be produced by CMPP*/PCMP*
22446 Cond.getOpcode() == ISD::SETCC &&
22447 // Check if SETCC has already been promoted
22448 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
22450 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22451 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22453 if (TValIsAllZeros || FValIsAllOnes) {
22454 SDValue CC = Cond.getOperand(2);
22455 ISD::CondCode NewCC =
22456 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22457 Cond.getOperand(0).getValueType().isInteger());
22458 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22459 std::swap(LHS, RHS);
22460 TValIsAllOnes = FValIsAllOnes;
22461 FValIsAllZeros = TValIsAllZeros;
22465 if (TValIsAllOnes || FValIsAllZeros) {
22468 if (TValIsAllOnes && FValIsAllZeros)
22470 else if (TValIsAllOnes)
22472 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
22473 else if (FValIsAllZeros)
22474 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22475 DAG.getBitcast(CondVT, LHS));
22477 return DAG.getBitcast(VT, Ret);
22481 // We should generate an X86ISD::BLENDI from a vselect if its argument
22482 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22483 // constants. This specific pattern gets generated when we split a
22484 // selector for a 512 bit vector in a machine without AVX512 (but with
22485 // 256-bit vectors), during legalization:
22487 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22489 // Iff we find this pattern and the build_vectors are built from
22490 // constants, we translate the vselect into a shuffle_vector that we
22491 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22492 if ((N->getOpcode() == ISD::VSELECT ||
22493 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22494 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
22495 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22496 if (Shuffle.getNode())
22500 // If this is a *dynamic* select (non-constant condition) and we can match
22501 // this node with one of the variable blend instructions, restructure the
22502 // condition so that the blends can use the high bit of each element and use
22503 // SimplifyDemandedBits to simplify the condition operand.
22504 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22505 !DCI.isBeforeLegalize() &&
22506 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22507 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22509 // Don't optimize vector selects that map to mask-registers.
22513 // We can only handle the cases where VSELECT is directly legal on the
22514 // subtarget. We custom lower VSELECT nodes with constant conditions and
22515 // this makes it hard to see whether a dynamic VSELECT will correctly
22516 // lower, so we both check the operation's status and explicitly handle the
22517 // cases where a *dynamic* blend will fail even though a constant-condition
22518 // blend could be custom lowered.
22519 // FIXME: We should find a better way to handle this class of problems.
22520 // Potentially, we should combine constant-condition vselect nodes
22521 // pre-legalization into shuffles and not mark as many types as custom
22523 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
22525 // FIXME: We don't support i16-element blends currently. We could and
22526 // should support them by making *all* the bits in the condition be set
22527 // rather than just the high bit and using an i8-element blend.
22528 if (VT.getScalarType() == MVT::i16)
22530 // Dynamic blending was only available from SSE4.1 onward.
22531 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
22533 // Byte blends are only available in AVX2
22534 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
22535 !Subtarget->hasAVX2())
22538 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22539 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22541 APInt KnownZero, KnownOne;
22542 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22543 DCI.isBeforeLegalizeOps());
22544 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22545 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22547 // If we changed the computation somewhere in the DAG, this change
22548 // will affect all users of Cond.
22549 // Make sure it is fine and update all the nodes so that we do not
22550 // use the generic VSELECT anymore. Otherwise, we may perform
22551 // wrong optimizations as we messed up with the actual expectation
22552 // for the vector boolean values.
22553 if (Cond != TLO.Old) {
22554 // Check all uses of that condition operand to check whether it will be
22555 // consumed by non-BLEND instructions, which may depend on all bits are
22557 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22559 if (I->getOpcode() != ISD::VSELECT)
22560 // TODO: Add other opcodes eventually lowered into BLEND.
22563 // Update all the users of the condition, before committing the change,
22564 // so that the VSELECT optimizations that expect the correct vector
22565 // boolean value will not be triggered.
22566 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22568 DAG.ReplaceAllUsesOfValueWith(
22570 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22571 Cond, I->getOperand(1), I->getOperand(2)));
22572 DCI.CommitTargetLoweringOpt(TLO);
22575 // At this point, only Cond is changed. Change the condition
22576 // just for N to keep the opportunity to optimize all other
22577 // users their own way.
22578 DAG.ReplaceAllUsesOfValueWith(
22580 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22581 TLO.New, N->getOperand(1), N->getOperand(2)));
22589 // Check whether a boolean test is testing a boolean value generated by
22590 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22593 // Simplify the following patterns:
22594 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22595 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22596 // to (Op EFLAGS Cond)
22598 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22599 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22600 // to (Op EFLAGS !Cond)
22602 // where Op could be BRCOND or CMOV.
22604 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22605 // Quit if not CMP and SUB with its value result used.
22606 if (Cmp.getOpcode() != X86ISD::CMP &&
22607 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22610 // Quit if not used as a boolean value.
22611 if (CC != X86::COND_E && CC != X86::COND_NE)
22614 // Check CMP operands. One of them should be 0 or 1 and the other should be
22615 // an SetCC or extended from it.
22616 SDValue Op1 = Cmp.getOperand(0);
22617 SDValue Op2 = Cmp.getOperand(1);
22620 const ConstantSDNode* C = nullptr;
22621 bool needOppositeCond = (CC == X86::COND_E);
22622 bool checkAgainstTrue = false; // Is it a comparison against 1?
22624 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22626 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22628 else // Quit if all operands are not constants.
22631 if (C->getZExtValue() == 1) {
22632 needOppositeCond = !needOppositeCond;
22633 checkAgainstTrue = true;
22634 } else if (C->getZExtValue() != 0)
22635 // Quit if the constant is neither 0 or 1.
22638 bool truncatedToBoolWithAnd = false;
22639 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22640 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22641 SetCC.getOpcode() == ISD::TRUNCATE ||
22642 SetCC.getOpcode() == ISD::AND) {
22643 if (SetCC.getOpcode() == ISD::AND) {
22645 ConstantSDNode *CS;
22646 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22647 CS->getZExtValue() == 1)
22649 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22650 CS->getZExtValue() == 1)
22654 SetCC = SetCC.getOperand(OpIdx);
22655 truncatedToBoolWithAnd = true;
22657 SetCC = SetCC.getOperand(0);
22660 switch (SetCC.getOpcode()) {
22661 case X86ISD::SETCC_CARRY:
22662 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22663 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22664 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22665 // truncated to i1 using 'and'.
22666 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22668 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22669 "Invalid use of SETCC_CARRY!");
22671 case X86ISD::SETCC:
22672 // Set the condition code or opposite one if necessary.
22673 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22674 if (needOppositeCond)
22675 CC = X86::GetOppositeBranchCondition(CC);
22676 return SetCC.getOperand(1);
22677 case X86ISD::CMOV: {
22678 // Check whether false/true value has canonical one, i.e. 0 or 1.
22679 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22680 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22681 // Quit if true value is not a constant.
22684 // Quit if false value is not a constant.
22686 SDValue Op = SetCC.getOperand(0);
22687 // Skip 'zext' or 'trunc' node.
22688 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22689 Op.getOpcode() == ISD::TRUNCATE)
22690 Op = Op.getOperand(0);
22691 // A special case for rdrand/rdseed, where 0 is set if false cond is
22693 if ((Op.getOpcode() != X86ISD::RDRAND &&
22694 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22697 // Quit if false value is not the constant 0 or 1.
22698 bool FValIsFalse = true;
22699 if (FVal && FVal->getZExtValue() != 0) {
22700 if (FVal->getZExtValue() != 1)
22702 // If FVal is 1, opposite cond is needed.
22703 needOppositeCond = !needOppositeCond;
22704 FValIsFalse = false;
22706 // Quit if TVal is not the constant opposite of FVal.
22707 if (FValIsFalse && TVal->getZExtValue() != 1)
22709 if (!FValIsFalse && TVal->getZExtValue() != 0)
22711 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22712 if (needOppositeCond)
22713 CC = X86::GetOppositeBranchCondition(CC);
22714 return SetCC.getOperand(3);
22721 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22723 /// (X86or (X86setcc) (X86setcc))
22724 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22725 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22726 X86::CondCode &CC1, SDValue &Flags,
22728 if (Cond->getOpcode() == X86ISD::CMP) {
22729 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22730 if (!CondOp1C || !CondOp1C->isNullValue())
22733 Cond = Cond->getOperand(0);
22738 SDValue SetCC0, SetCC1;
22739 switch (Cond->getOpcode()) {
22740 default: return false;
22747 SetCC0 = Cond->getOperand(0);
22748 SetCC1 = Cond->getOperand(1);
22752 // Make sure we have SETCC nodes, using the same flags value.
22753 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22754 SetCC1.getOpcode() != X86ISD::SETCC ||
22755 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22758 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22759 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22760 Flags = SetCC0->getOperand(1);
22764 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22765 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22766 TargetLowering::DAGCombinerInfo &DCI,
22767 const X86Subtarget *Subtarget) {
22770 // If the flag operand isn't dead, don't touch this CMOV.
22771 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22774 SDValue FalseOp = N->getOperand(0);
22775 SDValue TrueOp = N->getOperand(1);
22776 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22777 SDValue Cond = N->getOperand(3);
22779 if (CC == X86::COND_E || CC == X86::COND_NE) {
22780 switch (Cond.getOpcode()) {
22784 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22785 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22786 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22792 Flags = checkBoolTestSetCCCombine(Cond, CC);
22793 if (Flags.getNode() &&
22794 // Extra check as FCMOV only supports a subset of X86 cond.
22795 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22796 SDValue Ops[] = { FalseOp, TrueOp,
22797 DAG.getConstant(CC, DL, MVT::i8), Flags };
22798 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22801 // If this is a select between two integer constants, try to do some
22802 // optimizations. Note that the operands are ordered the opposite of SELECT
22804 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22805 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22806 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22807 // larger than FalseC (the false value).
22808 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22809 CC = X86::GetOppositeBranchCondition(CC);
22810 std::swap(TrueC, FalseC);
22811 std::swap(TrueOp, FalseOp);
22814 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22815 // This is efficient for any integer data type (including i8/i16) and
22817 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22818 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22819 DAG.getConstant(CC, DL, MVT::i8), Cond);
22821 // Zero extend the condition if needed.
22822 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22824 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22825 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22826 DAG.getConstant(ShAmt, DL, MVT::i8));
22827 if (N->getNumValues() == 2) // Dead flag value?
22828 return DCI.CombineTo(N, Cond, SDValue());
22832 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22833 // for any integer data type, including i8/i16.
22834 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22835 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22836 DAG.getConstant(CC, DL, MVT::i8), Cond);
22838 // Zero extend the condition if needed.
22839 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22840 FalseC->getValueType(0), Cond);
22841 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22842 SDValue(FalseC, 0));
22844 if (N->getNumValues() == 2) // Dead flag value?
22845 return DCI.CombineTo(N, Cond, SDValue());
22849 // Optimize cases that will turn into an LEA instruction. This requires
22850 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22851 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22852 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22853 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22855 bool isFastMultiplier = false;
22857 switch ((unsigned char)Diff) {
22859 case 1: // result = add base, cond
22860 case 2: // result = lea base( , cond*2)
22861 case 3: // result = lea base(cond, cond*2)
22862 case 4: // result = lea base( , cond*4)
22863 case 5: // result = lea base(cond, cond*4)
22864 case 8: // result = lea base( , cond*8)
22865 case 9: // result = lea base(cond, cond*8)
22866 isFastMultiplier = true;
22871 if (isFastMultiplier) {
22872 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22873 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22874 DAG.getConstant(CC, DL, MVT::i8), Cond);
22875 // Zero extend the condition if needed.
22876 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22878 // Scale the condition by the difference.
22880 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22881 DAG.getConstant(Diff, DL, Cond.getValueType()));
22883 // Add the base if non-zero.
22884 if (FalseC->getAPIntValue() != 0)
22885 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22886 SDValue(FalseC, 0));
22887 if (N->getNumValues() == 2) // Dead flag value?
22888 return DCI.CombineTo(N, Cond, SDValue());
22895 // Handle these cases:
22896 // (select (x != c), e, c) -> select (x != c), e, x),
22897 // (select (x == c), c, e) -> select (x == c), x, e)
22898 // where the c is an integer constant, and the "select" is the combination
22899 // of CMOV and CMP.
22901 // The rationale for this change is that the conditional-move from a constant
22902 // needs two instructions, however, conditional-move from a register needs
22903 // only one instruction.
22905 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22906 // some instruction-combining opportunities. This opt needs to be
22907 // postponed as late as possible.
22909 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22910 // the DCI.xxxx conditions are provided to postpone the optimization as
22911 // late as possible.
22913 ConstantSDNode *CmpAgainst = nullptr;
22914 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22915 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22916 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22918 if (CC == X86::COND_NE &&
22919 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22920 CC = X86::GetOppositeBranchCondition(CC);
22921 std::swap(TrueOp, FalseOp);
22924 if (CC == X86::COND_E &&
22925 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22926 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22927 DAG.getConstant(CC, DL, MVT::i8), Cond };
22928 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22933 // Fold and/or of setcc's to double CMOV:
22934 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22935 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22937 // This combine lets us generate:
22938 // cmovcc1 (jcc1 if we don't have CMOV)
22944 // cmovne (jne if we don't have CMOV)
22945 // When we can't use the CMOV instruction, it might increase branch
22947 // When we can use CMOV, or when there is no mispredict, this improves
22948 // throughput and reduces register pressure.
22950 if (CC == X86::COND_NE) {
22952 X86::CondCode CC0, CC1;
22954 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22956 std::swap(FalseOp, TrueOp);
22957 CC0 = X86::GetOppositeBranchCondition(CC0);
22958 CC1 = X86::GetOppositeBranchCondition(CC1);
22961 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22963 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22964 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22965 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22966 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22974 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22975 const X86Subtarget *Subtarget) {
22976 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22978 default: return SDValue();
22979 // SSE/AVX/AVX2 blend intrinsics.
22980 case Intrinsic::x86_avx2_pblendvb:
22981 // Don't try to simplify this intrinsic if we don't have AVX2.
22982 if (!Subtarget->hasAVX2())
22985 case Intrinsic::x86_avx_blendv_pd_256:
22986 case Intrinsic::x86_avx_blendv_ps_256:
22987 // Don't try to simplify this intrinsic if we don't have AVX.
22988 if (!Subtarget->hasAVX())
22991 case Intrinsic::x86_sse41_blendvps:
22992 case Intrinsic::x86_sse41_blendvpd:
22993 case Intrinsic::x86_sse41_pblendvb: {
22994 SDValue Op0 = N->getOperand(1);
22995 SDValue Op1 = N->getOperand(2);
22996 SDValue Mask = N->getOperand(3);
22998 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22999 if (!Subtarget->hasSSE41())
23002 // fold (blend A, A, Mask) -> A
23005 // fold (blend A, B, allZeros) -> A
23006 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23008 // fold (blend A, B, allOnes) -> B
23009 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23012 // Simplify the case where the mask is a constant i32 value.
23013 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23014 if (C->isNullValue())
23016 if (C->isAllOnesValue())
23023 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23024 case Intrinsic::x86_sse2_psrai_w:
23025 case Intrinsic::x86_sse2_psrai_d:
23026 case Intrinsic::x86_avx2_psrai_w:
23027 case Intrinsic::x86_avx2_psrai_d:
23028 case Intrinsic::x86_sse2_psra_w:
23029 case Intrinsic::x86_sse2_psra_d:
23030 case Intrinsic::x86_avx2_psra_w:
23031 case Intrinsic::x86_avx2_psra_d: {
23032 SDValue Op0 = N->getOperand(1);
23033 SDValue Op1 = N->getOperand(2);
23034 EVT VT = Op0.getValueType();
23035 assert(VT.isVector() && "Expected a vector type!");
23037 if (isa<BuildVectorSDNode>(Op1))
23038 Op1 = Op1.getOperand(0);
23040 if (!isa<ConstantSDNode>(Op1))
23043 EVT SVT = VT.getVectorElementType();
23044 unsigned SVTBits = SVT.getSizeInBits();
23046 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23047 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23048 uint64_t ShAmt = C.getZExtValue();
23050 // Don't try to convert this shift into a ISD::SRA if the shift
23051 // count is bigger than or equal to the element size.
23052 if (ShAmt >= SVTBits)
23055 // Trivial case: if the shift count is zero, then fold this
23056 // into the first operand.
23060 // Replace this packed shift intrinsic with a target independent
23063 SDValue Splat = DAG.getConstant(C, DL, VT);
23064 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
23069 /// PerformMulCombine - Optimize a single multiply with constant into two
23070 /// in order to implement it with two cheaper instructions, e.g.
23071 /// LEA + SHL, LEA + LEA.
23072 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23073 TargetLowering::DAGCombinerInfo &DCI) {
23074 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23077 EVT VT = N->getValueType(0);
23078 if (VT != MVT::i64 && VT != MVT::i32)
23081 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23084 uint64_t MulAmt = C->getZExtValue();
23085 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23088 uint64_t MulAmt1 = 0;
23089 uint64_t MulAmt2 = 0;
23090 if ((MulAmt % 9) == 0) {
23092 MulAmt2 = MulAmt / 9;
23093 } else if ((MulAmt % 5) == 0) {
23095 MulAmt2 = MulAmt / 5;
23096 } else if ((MulAmt % 3) == 0) {
23098 MulAmt2 = MulAmt / 3;
23101 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23104 if (isPowerOf2_64(MulAmt2) &&
23105 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23106 // If second multiplifer is pow2, issue it first. We want the multiply by
23107 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23109 std::swap(MulAmt1, MulAmt2);
23112 if (isPowerOf2_64(MulAmt1))
23113 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23114 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
23116 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23117 DAG.getConstant(MulAmt1, DL, VT));
23119 if (isPowerOf2_64(MulAmt2))
23120 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23121 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
23123 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23124 DAG.getConstant(MulAmt2, DL, VT));
23126 // Do not add new nodes to DAG combiner worklist.
23127 DCI.CombineTo(N, NewMul, false);
23132 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23133 SDValue N0 = N->getOperand(0);
23134 SDValue N1 = N->getOperand(1);
23135 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23136 EVT VT = N0.getValueType();
23138 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23139 // since the result of setcc_c is all zero's or all ones.
23140 if (VT.isInteger() && !VT.isVector() &&
23141 N1C && N0.getOpcode() == ISD::AND &&
23142 N0.getOperand(1).getOpcode() == ISD::Constant) {
23143 SDValue N00 = N0.getOperand(0);
23144 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23145 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23146 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23147 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23148 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23149 APInt ShAmt = N1C->getAPIntValue();
23150 Mask = Mask.shl(ShAmt);
23153 return DAG.getNode(ISD::AND, DL, VT,
23154 N00, DAG.getConstant(Mask, DL, VT));
23159 // Hardware support for vector shifts is sparse which makes us scalarize the
23160 // vector operations in many cases. Also, on sandybridge ADD is faster than
23162 // (shl V, 1) -> add V,V
23163 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23164 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23165 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23166 // We shift all of the values by one. In many cases we do not have
23167 // hardware support for this operation. This is better expressed as an ADD
23169 if (N1SplatC->getZExtValue() == 1)
23170 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23176 /// \brief Returns a vector of 0s if the node in input is a vector logical
23177 /// shift by a constant amount which is known to be bigger than or equal
23178 /// to the vector element size in bits.
23179 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23180 const X86Subtarget *Subtarget) {
23181 EVT VT = N->getValueType(0);
23183 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23184 (!Subtarget->hasInt256() ||
23185 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23188 SDValue Amt = N->getOperand(1);
23190 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23191 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23192 APInt ShiftAmt = AmtSplat->getAPIntValue();
23193 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23195 // SSE2/AVX2 logical shifts always return a vector of 0s
23196 // if the shift amount is bigger than or equal to
23197 // the element size. The constant shift amount will be
23198 // encoded as a 8-bit immediate.
23199 if (ShiftAmt.trunc(8).uge(MaxAmount))
23200 return getZeroVector(VT, Subtarget, DAG, DL);
23206 /// PerformShiftCombine - Combine shifts.
23207 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23208 TargetLowering::DAGCombinerInfo &DCI,
23209 const X86Subtarget *Subtarget) {
23210 if (N->getOpcode() == ISD::SHL)
23211 if (SDValue V = PerformSHLCombine(N, DAG))
23214 // Try to fold this logical shift into a zero vector.
23215 if (N->getOpcode() != ISD::SRA)
23216 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
23222 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23223 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23224 // and friends. Likewise for OR -> CMPNEQSS.
23225 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23226 TargetLowering::DAGCombinerInfo &DCI,
23227 const X86Subtarget *Subtarget) {
23230 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23231 // we're requiring SSE2 for both.
23232 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23233 SDValue N0 = N->getOperand(0);
23234 SDValue N1 = N->getOperand(1);
23235 SDValue CMP0 = N0->getOperand(1);
23236 SDValue CMP1 = N1->getOperand(1);
23239 // The SETCCs should both refer to the same CMP.
23240 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23243 SDValue CMP00 = CMP0->getOperand(0);
23244 SDValue CMP01 = CMP0->getOperand(1);
23245 EVT VT = CMP00.getValueType();
23247 if (VT == MVT::f32 || VT == MVT::f64) {
23248 bool ExpectingFlags = false;
23249 // Check for any users that want flags:
23250 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23251 !ExpectingFlags && UI != UE; ++UI)
23252 switch (UI->getOpcode()) {
23257 ExpectingFlags = true;
23259 case ISD::CopyToReg:
23260 case ISD::SIGN_EXTEND:
23261 case ISD::ZERO_EXTEND:
23262 case ISD::ANY_EXTEND:
23266 if (!ExpectingFlags) {
23267 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23268 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23270 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23271 X86::CondCode tmp = cc0;
23276 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23277 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23278 // FIXME: need symbolic constants for these magic numbers.
23279 // See X86ATTInstPrinter.cpp:printSSECC().
23280 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23281 if (Subtarget->hasAVX512()) {
23282 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23284 DAG.getConstant(x86cc, DL, MVT::i8));
23285 if (N->getValueType(0) != MVT::i1)
23286 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23290 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23291 CMP00.getValueType(), CMP00, CMP01,
23292 DAG.getConstant(x86cc, DL,
23295 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23296 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23298 if (is64BitFP && !Subtarget->is64Bit()) {
23299 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23300 // 64-bit integer, since that's not a legal type. Since
23301 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23302 // bits, but can do this little dance to extract the lowest 32 bits
23303 // and work with those going forward.
23304 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23306 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
23307 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23308 Vector32, DAG.getIntPtrConstant(0, DL));
23312 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
23313 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23314 DAG.getConstant(1, DL, IntVT));
23315 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
23317 return OneBitOfTruth;
23325 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23326 /// so it can be folded inside ANDNP.
23327 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23328 EVT VT = N->getValueType(0);
23330 // Match direct AllOnes for 128 and 256-bit vectors
23331 if (ISD::isBuildVectorAllOnes(N))
23334 // Look through a bit convert.
23335 if (N->getOpcode() == ISD::BITCAST)
23336 N = N->getOperand(0).getNode();
23338 // Sometimes the operand may come from a insert_subvector building a 256-bit
23340 if (VT.is256BitVector() &&
23341 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23342 SDValue V1 = N->getOperand(0);
23343 SDValue V2 = N->getOperand(1);
23345 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23346 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23347 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23348 ISD::isBuildVectorAllOnes(V2.getNode()))
23355 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23356 // register. In most cases we actually compare or select YMM-sized registers
23357 // and mixing the two types creates horrible code. This method optimizes
23358 // some of the transition sequences.
23359 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23360 TargetLowering::DAGCombinerInfo &DCI,
23361 const X86Subtarget *Subtarget) {
23362 EVT VT = N->getValueType(0);
23363 if (!VT.is256BitVector())
23366 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23367 N->getOpcode() == ISD::ZERO_EXTEND ||
23368 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23370 SDValue Narrow = N->getOperand(0);
23371 EVT NarrowVT = Narrow->getValueType(0);
23372 if (!NarrowVT.is128BitVector())
23375 if (Narrow->getOpcode() != ISD::XOR &&
23376 Narrow->getOpcode() != ISD::AND &&
23377 Narrow->getOpcode() != ISD::OR)
23380 SDValue N0 = Narrow->getOperand(0);
23381 SDValue N1 = Narrow->getOperand(1);
23384 // The Left side has to be a trunc.
23385 if (N0.getOpcode() != ISD::TRUNCATE)
23388 // The type of the truncated inputs.
23389 EVT WideVT = N0->getOperand(0)->getValueType(0);
23393 // The right side has to be a 'trunc' or a constant vector.
23394 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23395 ConstantSDNode *RHSConstSplat = nullptr;
23396 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23397 RHSConstSplat = RHSBV->getConstantSplatNode();
23398 if (!RHSTrunc && !RHSConstSplat)
23401 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23403 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23406 // Set N0 and N1 to hold the inputs to the new wide operation.
23407 N0 = N0->getOperand(0);
23408 if (RHSConstSplat) {
23409 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23410 SDValue(RHSConstSplat, 0));
23411 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23412 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23413 } else if (RHSTrunc) {
23414 N1 = N1->getOperand(0);
23417 // Generate the wide operation.
23418 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23419 unsigned Opcode = N->getOpcode();
23421 case ISD::ANY_EXTEND:
23423 case ISD::ZERO_EXTEND: {
23424 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23425 APInt Mask = APInt::getAllOnesValue(InBits);
23426 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23427 return DAG.getNode(ISD::AND, DL, VT,
23428 Op, DAG.getConstant(Mask, DL, VT));
23430 case ISD::SIGN_EXTEND:
23431 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23432 Op, DAG.getValueType(NarrowVT));
23434 llvm_unreachable("Unexpected opcode");
23438 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
23439 TargetLowering::DAGCombinerInfo &DCI,
23440 const X86Subtarget *Subtarget) {
23441 SDValue N0 = N->getOperand(0);
23442 SDValue N1 = N->getOperand(1);
23445 // A vector zext_in_reg may be represented as a shuffle,
23446 // feeding into a bitcast (this represents anyext) feeding into
23447 // an and with a mask.
23448 // We'd like to try to combine that into a shuffle with zero
23449 // plus a bitcast, removing the and.
23450 if (N0.getOpcode() != ISD::BITCAST ||
23451 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
23454 // The other side of the AND should be a splat of 2^C, where C
23455 // is the number of bits in the source type.
23456 if (N1.getOpcode() == ISD::BITCAST)
23457 N1 = N1.getOperand(0);
23458 if (N1.getOpcode() != ISD::BUILD_VECTOR)
23460 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
23462 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
23463 EVT SrcType = Shuffle->getValueType(0);
23465 // We expect a single-source shuffle
23466 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
23469 unsigned SrcSize = SrcType.getScalarSizeInBits();
23471 APInt SplatValue, SplatUndef;
23472 unsigned SplatBitSize;
23474 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
23475 SplatBitSize, HasAnyUndefs))
23478 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
23479 // Make sure the splat matches the mask we expect
23480 if (SplatBitSize > ResSize ||
23481 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
23484 // Make sure the input and output size make sense
23485 if (SrcSize >= ResSize || ResSize % SrcSize)
23488 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
23489 // The number of u's between each two values depends on the ratio between
23490 // the source and dest type.
23491 unsigned ZextRatio = ResSize / SrcSize;
23492 bool IsZext = true;
23493 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
23494 if (i % ZextRatio) {
23495 if (Shuffle->getMaskElt(i) > 0) {
23501 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
23502 // Expected element number
23512 // Ok, perform the transformation - replace the shuffle with
23513 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
23514 // (instead of undef) where the k elements come from the zero vector.
23515 SmallVector<int, 8> Mask;
23516 unsigned NumElems = SrcType.getVectorNumElements();
23517 for (unsigned i = 0; i < NumElems; ++i)
23519 Mask.push_back(NumElems);
23521 Mask.push_back(i / ZextRatio);
23523 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
23524 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
23525 return DAG.getBitcast(N0.getValueType(), NewShuffle);
23528 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23529 TargetLowering::DAGCombinerInfo &DCI,
23530 const X86Subtarget *Subtarget) {
23531 if (DCI.isBeforeLegalizeOps())
23534 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
23537 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23540 EVT VT = N->getValueType(0);
23541 SDValue N0 = N->getOperand(0);
23542 SDValue N1 = N->getOperand(1);
23545 // Create BEXTR instructions
23546 // BEXTR is ((X >> imm) & (2**size-1))
23547 if (VT == MVT::i32 || VT == MVT::i64) {
23548 // Check for BEXTR.
23549 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23550 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23551 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23552 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23553 if (MaskNode && ShiftNode) {
23554 uint64_t Mask = MaskNode->getZExtValue();
23555 uint64_t Shift = ShiftNode->getZExtValue();
23556 if (isMask_64(Mask)) {
23557 uint64_t MaskSize = countPopulation(Mask);
23558 if (Shift + MaskSize <= VT.getSizeInBits())
23559 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23560 DAG.getConstant(Shift | (MaskSize << 8), DL,
23569 // Want to form ANDNP nodes:
23570 // 1) In the hopes of then easily combining them with OR and AND nodes
23571 // to form PBLEND/PSIGN.
23572 // 2) To match ANDN packed intrinsics
23573 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23576 // Check LHS for vnot
23577 if (N0.getOpcode() == ISD::XOR &&
23578 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23579 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23580 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23582 // Check RHS for vnot
23583 if (N1.getOpcode() == ISD::XOR &&
23584 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23585 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23586 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23591 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23592 TargetLowering::DAGCombinerInfo &DCI,
23593 const X86Subtarget *Subtarget) {
23594 if (DCI.isBeforeLegalizeOps())
23597 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23600 SDValue N0 = N->getOperand(0);
23601 SDValue N1 = N->getOperand(1);
23602 EVT VT = N->getValueType(0);
23604 // look for psign/blend
23605 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23606 if (!Subtarget->hasSSSE3() ||
23607 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23610 // Canonicalize pandn to RHS
23611 if (N0.getOpcode() == X86ISD::ANDNP)
23613 // or (and (m, y), (pandn m, x))
23614 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23615 SDValue Mask = N1.getOperand(0);
23616 SDValue X = N1.getOperand(1);
23618 if (N0.getOperand(0) == Mask)
23619 Y = N0.getOperand(1);
23620 if (N0.getOperand(1) == Mask)
23621 Y = N0.getOperand(0);
23623 // Check to see if the mask appeared in both the AND and ANDNP and
23627 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23628 // Look through mask bitcast.
23629 if (Mask.getOpcode() == ISD::BITCAST)
23630 Mask = Mask.getOperand(0);
23631 if (X.getOpcode() == ISD::BITCAST)
23632 X = X.getOperand(0);
23633 if (Y.getOpcode() == ISD::BITCAST)
23634 Y = Y.getOperand(0);
23636 EVT MaskVT = Mask.getValueType();
23638 // Validate that the Mask operand is a vector sra node.
23639 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23640 // there is no psrai.b
23641 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23642 unsigned SraAmt = ~0;
23643 if (Mask.getOpcode() == ISD::SRA) {
23644 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23645 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23646 SraAmt = AmtConst->getZExtValue();
23647 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23648 SDValue SraC = Mask.getOperand(1);
23649 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23651 if ((SraAmt + 1) != EltBits)
23656 // Now we know we at least have a plendvb with the mask val. See if
23657 // we can form a psignb/w/d.
23658 // psign = x.type == y.type == mask.type && y = sub(0, x);
23659 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23660 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23661 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23662 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23663 "Unsupported VT for PSIGN");
23664 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23665 return DAG.getBitcast(VT, Mask);
23667 // PBLENDVB only available on SSE 4.1
23668 if (!Subtarget->hasSSE41())
23671 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23673 X = DAG.getBitcast(BlendVT, X);
23674 Y = DAG.getBitcast(BlendVT, Y);
23675 Mask = DAG.getBitcast(BlendVT, Mask);
23676 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23677 return DAG.getBitcast(VT, Mask);
23681 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23684 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23685 MachineFunction &MF = DAG.getMachineFunction();
23687 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23689 // SHLD/SHRD instructions have lower register pressure, but on some
23690 // platforms they have higher latency than the equivalent
23691 // series of shifts/or that would otherwise be generated.
23692 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23693 // have higher latencies and we are not optimizing for size.
23694 if (!OptForSize && Subtarget->isSHLDSlow())
23697 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23699 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23701 if (!N0.hasOneUse() || !N1.hasOneUse())
23704 SDValue ShAmt0 = N0.getOperand(1);
23705 if (ShAmt0.getValueType() != MVT::i8)
23707 SDValue ShAmt1 = N1.getOperand(1);
23708 if (ShAmt1.getValueType() != MVT::i8)
23710 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23711 ShAmt0 = ShAmt0.getOperand(0);
23712 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23713 ShAmt1 = ShAmt1.getOperand(0);
23716 unsigned Opc = X86ISD::SHLD;
23717 SDValue Op0 = N0.getOperand(0);
23718 SDValue Op1 = N1.getOperand(0);
23719 if (ShAmt0.getOpcode() == ISD::SUB) {
23720 Opc = X86ISD::SHRD;
23721 std::swap(Op0, Op1);
23722 std::swap(ShAmt0, ShAmt1);
23725 unsigned Bits = VT.getSizeInBits();
23726 if (ShAmt1.getOpcode() == ISD::SUB) {
23727 SDValue Sum = ShAmt1.getOperand(0);
23728 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23729 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23730 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23731 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23732 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23733 return DAG.getNode(Opc, DL, VT,
23735 DAG.getNode(ISD::TRUNCATE, DL,
23738 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23739 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23741 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23742 return DAG.getNode(Opc, DL, VT,
23743 N0.getOperand(0), N1.getOperand(0),
23744 DAG.getNode(ISD::TRUNCATE, DL,
23751 // Generate NEG and CMOV for integer abs.
23752 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23753 EVT VT = N->getValueType(0);
23755 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23756 // 8-bit integer abs to NEG and CMOV.
23757 if (VT.isInteger() && VT.getSizeInBits() == 8)
23760 SDValue N0 = N->getOperand(0);
23761 SDValue N1 = N->getOperand(1);
23764 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23765 // and change it to SUB and CMOV.
23766 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23767 N0.getOpcode() == ISD::ADD &&
23768 N0.getOperand(1) == N1 &&
23769 N1.getOpcode() == ISD::SRA &&
23770 N1.getOperand(0) == N0.getOperand(0))
23771 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23772 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23773 // Generate SUB & CMOV.
23774 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23775 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23777 SDValue Ops[] = { N0.getOperand(0), Neg,
23778 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23779 SDValue(Neg.getNode(), 1) };
23780 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23785 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23786 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23787 TargetLowering::DAGCombinerInfo &DCI,
23788 const X86Subtarget *Subtarget) {
23789 if (DCI.isBeforeLegalizeOps())
23792 if (Subtarget->hasCMov())
23793 if (SDValue RV = performIntegerAbsCombine(N, DAG))
23799 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23800 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23801 TargetLowering::DAGCombinerInfo &DCI,
23802 const X86Subtarget *Subtarget) {
23803 LoadSDNode *Ld = cast<LoadSDNode>(N);
23804 EVT RegVT = Ld->getValueType(0);
23805 EVT MemVT = Ld->getMemoryVT();
23807 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23809 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23810 // into two 16-byte operations.
23811 ISD::LoadExtType Ext = Ld->getExtensionType();
23812 unsigned Alignment = Ld->getAlignment();
23813 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23814 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23815 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23816 unsigned NumElems = RegVT.getVectorNumElements();
23820 SDValue Ptr = Ld->getBasePtr();
23821 SDValue Increment =
23822 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
23824 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23826 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23827 Ld->getPointerInfo(), Ld->isVolatile(),
23828 Ld->isNonTemporal(), Ld->isInvariant(),
23830 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23831 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23832 Ld->getPointerInfo(), Ld->isVolatile(),
23833 Ld->isNonTemporal(), Ld->isInvariant(),
23834 std::min(16U, Alignment));
23835 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23837 Load2.getValue(1));
23839 SDValue NewVec = DAG.getUNDEF(RegVT);
23840 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23841 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23842 return DCI.CombineTo(N, NewVec, TF, true);
23848 /// PerformMLOADCombine - Resolve extending loads
23849 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23850 TargetLowering::DAGCombinerInfo &DCI,
23851 const X86Subtarget *Subtarget) {
23852 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23853 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23856 EVT VT = Mld->getValueType(0);
23857 unsigned NumElems = VT.getVectorNumElements();
23858 EVT LdVT = Mld->getMemoryVT();
23861 assert(LdVT != VT && "Cannot extend to the same type");
23862 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23863 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23864 // From, To sizes and ElemCount must be pow of two
23865 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23866 "Unexpected size for extending masked load");
23868 unsigned SizeRatio = ToSz / FromSz;
23869 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23871 // Create a type on which we perform the shuffle
23872 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23873 LdVT.getScalarType(), NumElems*SizeRatio);
23874 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23876 // Convert Src0 value
23877 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
23878 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23879 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23880 for (unsigned i = 0; i != NumElems; ++i)
23881 ShuffleVec[i] = i * SizeRatio;
23883 // Can't shuffle using an illegal type.
23884 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23885 && "WideVecVT should be legal");
23886 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23887 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23889 // Prepare the new mask
23891 SDValue Mask = Mld->getMask();
23892 if (Mask.getValueType() == VT) {
23893 // Mask and original value have the same type
23894 NewMask = DAG.getBitcast(WideVecVT, Mask);
23895 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23896 for (unsigned i = 0; i != NumElems; ++i)
23897 ShuffleVec[i] = i * SizeRatio;
23898 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23899 ShuffleVec[i] = NumElems*SizeRatio;
23900 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23901 DAG.getConstant(0, dl, WideVecVT),
23905 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23906 unsigned WidenNumElts = NumElems*SizeRatio;
23907 unsigned MaskNumElts = VT.getVectorNumElements();
23908 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23911 unsigned NumConcat = WidenNumElts / MaskNumElts;
23912 SmallVector<SDValue, 16> Ops(NumConcat);
23913 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23915 for (unsigned i = 1; i != NumConcat; ++i)
23918 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23921 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23922 Mld->getBasePtr(), NewMask, WideSrc0,
23923 Mld->getMemoryVT(), Mld->getMemOperand(),
23925 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23926 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23929 /// PerformMSTORECombine - Resolve truncating stores
23930 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23931 const X86Subtarget *Subtarget) {
23932 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23933 if (!Mst->isTruncatingStore())
23936 EVT VT = Mst->getValue().getValueType();
23937 unsigned NumElems = VT.getVectorNumElements();
23938 EVT StVT = Mst->getMemoryVT();
23941 assert(StVT != VT && "Cannot truncate to the same type");
23942 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23943 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23945 // From, To sizes and ElemCount must be pow of two
23946 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23947 "Unexpected size for truncating masked store");
23948 // We are going to use the original vector elt for storing.
23949 // Accumulated smaller vector elements must be a multiple of the store size.
23950 assert (((NumElems * FromSz) % ToSz) == 0 &&
23951 "Unexpected ratio for truncating masked store");
23953 unsigned SizeRatio = FromSz / ToSz;
23954 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23956 // Create a type on which we perform the shuffle
23957 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23958 StVT.getScalarType(), NumElems*SizeRatio);
23960 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23962 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
23963 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23964 for (unsigned i = 0; i != NumElems; ++i)
23965 ShuffleVec[i] = i * SizeRatio;
23967 // Can't shuffle using an illegal type.
23968 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23969 && "WideVecVT should be legal");
23971 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23972 DAG.getUNDEF(WideVecVT),
23976 SDValue Mask = Mst->getMask();
23977 if (Mask.getValueType() == VT) {
23978 // Mask and original value have the same type
23979 NewMask = DAG.getBitcast(WideVecVT, Mask);
23980 for (unsigned i = 0; i != NumElems; ++i)
23981 ShuffleVec[i] = i * SizeRatio;
23982 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23983 ShuffleVec[i] = NumElems*SizeRatio;
23984 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23985 DAG.getConstant(0, dl, WideVecVT),
23989 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23990 unsigned WidenNumElts = NumElems*SizeRatio;
23991 unsigned MaskNumElts = VT.getVectorNumElements();
23992 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23995 unsigned NumConcat = WidenNumElts / MaskNumElts;
23996 SmallVector<SDValue, 16> Ops(NumConcat);
23997 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23999 for (unsigned i = 1; i != NumConcat; ++i)
24002 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24005 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
24006 NewMask, StVT, Mst->getMemOperand(), false);
24008 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24009 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24010 const X86Subtarget *Subtarget) {
24011 StoreSDNode *St = cast<StoreSDNode>(N);
24012 EVT VT = St->getValue().getValueType();
24013 EVT StVT = St->getMemoryVT();
24015 SDValue StoredVal = St->getOperand(1);
24016 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24018 // If we are saving a concatenation of two XMM registers and 32-byte stores
24019 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24020 unsigned Alignment = St->getAlignment();
24021 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24022 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24023 StVT == VT && !IsAligned) {
24024 unsigned NumElems = VT.getVectorNumElements();
24028 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24029 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24032 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24033 SDValue Ptr0 = St->getBasePtr();
24034 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24036 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24037 St->getPointerInfo(), St->isVolatile(),
24038 St->isNonTemporal(), Alignment);
24039 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24040 St->getPointerInfo(), St->isVolatile(),
24041 St->isNonTemporal(),
24042 std::min(16U, Alignment));
24043 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24046 // Optimize trunc store (of multiple scalars) to shuffle and store.
24047 // First, pack all of the elements in one place. Next, store to memory
24048 // in fewer chunks.
24049 if (St->isTruncatingStore() && VT.isVector()) {
24050 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24051 unsigned NumElems = VT.getVectorNumElements();
24052 assert(StVT != VT && "Cannot truncate to the same type");
24053 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24054 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24056 // From, To sizes and ElemCount must be pow of two
24057 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24058 // We are going to use the original vector elt for storing.
24059 // Accumulated smaller vector elements must be a multiple of the store size.
24060 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24062 unsigned SizeRatio = FromSz / ToSz;
24064 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24066 // Create a type on which we perform the shuffle
24067 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24068 StVT.getScalarType(), NumElems*SizeRatio);
24070 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24072 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
24073 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24074 for (unsigned i = 0; i != NumElems; ++i)
24075 ShuffleVec[i] = i * SizeRatio;
24077 // Can't shuffle using an illegal type.
24078 if (!TLI.isTypeLegal(WideVecVT))
24081 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24082 DAG.getUNDEF(WideVecVT),
24084 // At this point all of the data is stored at the bottom of the
24085 // register. We now need to save it to mem.
24087 // Find the largest store unit
24088 MVT StoreType = MVT::i8;
24089 for (MVT Tp : MVT::integer_valuetypes()) {
24090 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24094 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24095 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24096 (64 <= NumElems * ToSz))
24097 StoreType = MVT::f64;
24099 // Bitcast the original vector into a vector of store-size units
24100 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24101 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24102 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24103 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
24104 SmallVector<SDValue, 8> Chains;
24105 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
24106 TLI.getPointerTy(DAG.getDataLayout()));
24107 SDValue Ptr = St->getBasePtr();
24109 // Perform one or more big stores into memory.
24110 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24111 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24112 StoreType, ShuffWide,
24113 DAG.getIntPtrConstant(i, dl));
24114 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24115 St->getPointerInfo(), St->isVolatile(),
24116 St->isNonTemporal(), St->getAlignment());
24117 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24118 Chains.push_back(Ch);
24121 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24124 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24125 // the FP state in cases where an emms may be missing.
24126 // A preferable solution to the general problem is to figure out the right
24127 // places to insert EMMS. This qualifies as a quick hack.
24129 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24130 if (VT.getSizeInBits() != 64)
24133 const Function *F = DAG.getMachineFunction().getFunction();
24134 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
24136 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
24137 if ((VT.isVector() ||
24138 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24139 isa<LoadSDNode>(St->getValue()) &&
24140 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24141 St->getChain().hasOneUse() && !St->isVolatile()) {
24142 SDNode* LdVal = St->getValue().getNode();
24143 LoadSDNode *Ld = nullptr;
24144 int TokenFactorIndex = -1;
24145 SmallVector<SDValue, 8> Ops;
24146 SDNode* ChainVal = St->getChain().getNode();
24147 // Must be a store of a load. We currently handle two cases: the load
24148 // is a direct child, and it's under an intervening TokenFactor. It is
24149 // possible to dig deeper under nested TokenFactors.
24150 if (ChainVal == LdVal)
24151 Ld = cast<LoadSDNode>(St->getChain());
24152 else if (St->getValue().hasOneUse() &&
24153 ChainVal->getOpcode() == ISD::TokenFactor) {
24154 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24155 if (ChainVal->getOperand(i).getNode() == LdVal) {
24156 TokenFactorIndex = i;
24157 Ld = cast<LoadSDNode>(St->getValue());
24159 Ops.push_back(ChainVal->getOperand(i));
24163 if (!Ld || !ISD::isNormalLoad(Ld))
24166 // If this is not the MMX case, i.e. we are just turning i64 load/store
24167 // into f64 load/store, avoid the transformation if there are multiple
24168 // uses of the loaded value.
24169 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24174 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24175 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24177 if (Subtarget->is64Bit() || F64IsLegal) {
24178 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24179 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24180 Ld->getPointerInfo(), Ld->isVolatile(),
24181 Ld->isNonTemporal(), Ld->isInvariant(),
24182 Ld->getAlignment());
24183 SDValue NewChain = NewLd.getValue(1);
24184 if (TokenFactorIndex != -1) {
24185 Ops.push_back(NewChain);
24186 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24188 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24189 St->getPointerInfo(),
24190 St->isVolatile(), St->isNonTemporal(),
24191 St->getAlignment());
24194 // Otherwise, lower to two pairs of 32-bit loads / stores.
24195 SDValue LoAddr = Ld->getBasePtr();
24196 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24197 DAG.getConstant(4, LdDL, MVT::i32));
24199 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24200 Ld->getPointerInfo(),
24201 Ld->isVolatile(), Ld->isNonTemporal(),
24202 Ld->isInvariant(), Ld->getAlignment());
24203 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24204 Ld->getPointerInfo().getWithOffset(4),
24205 Ld->isVolatile(), Ld->isNonTemporal(),
24207 MinAlign(Ld->getAlignment(), 4));
24209 SDValue NewChain = LoLd.getValue(1);
24210 if (TokenFactorIndex != -1) {
24211 Ops.push_back(LoLd);
24212 Ops.push_back(HiLd);
24213 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24216 LoAddr = St->getBasePtr();
24217 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24218 DAG.getConstant(4, StDL, MVT::i32));
24220 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24221 St->getPointerInfo(),
24222 St->isVolatile(), St->isNonTemporal(),
24223 St->getAlignment());
24224 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24225 St->getPointerInfo().getWithOffset(4),
24227 St->isNonTemporal(),
24228 MinAlign(St->getAlignment(), 4));
24229 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24232 // This is similar to the above case, but here we handle a scalar 64-bit
24233 // integer store that is extracted from a vector on a 32-bit target.
24234 // If we have SSE2, then we can treat it like a floating-point double
24235 // to get past legalization. The execution dependencies fixup pass will
24236 // choose the optimal machine instruction for the store if this really is
24237 // an integer or v2f32 rather than an f64.
24238 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
24239 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
24240 SDValue OldExtract = St->getOperand(1);
24241 SDValue ExtOp0 = OldExtract.getOperand(0);
24242 unsigned VecSize = ExtOp0.getValueSizeInBits();
24243 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
24244 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
24245 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
24246 BitCast, OldExtract.getOperand(1));
24247 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
24248 St->getPointerInfo(), St->isVolatile(),
24249 St->isNonTemporal(), St->getAlignment());
24255 /// Return 'true' if this vector operation is "horizontal"
24256 /// and return the operands for the horizontal operation in LHS and RHS. A
24257 /// horizontal operation performs the binary operation on successive elements
24258 /// of its first operand, then on successive elements of its second operand,
24259 /// returning the resulting values in a vector. For example, if
24260 /// A = < float a0, float a1, float a2, float a3 >
24262 /// B = < float b0, float b1, float b2, float b3 >
24263 /// then the result of doing a horizontal operation on A and B is
24264 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24265 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24266 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24267 /// set to A, RHS to B, and the routine returns 'true'.
24268 /// Note that the binary operation should have the property that if one of the
24269 /// operands is UNDEF then the result is UNDEF.
24270 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24271 // Look for the following pattern: if
24272 // A = < float a0, float a1, float a2, float a3 >
24273 // B = < float b0, float b1, float b2, float b3 >
24275 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24276 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24277 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24278 // which is A horizontal-op B.
24280 // At least one of the operands should be a vector shuffle.
24281 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24282 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24285 MVT VT = LHS.getSimpleValueType();
24287 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24288 "Unsupported vector type for horizontal add/sub");
24290 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24291 // operate independently on 128-bit lanes.
24292 unsigned NumElts = VT.getVectorNumElements();
24293 unsigned NumLanes = VT.getSizeInBits()/128;
24294 unsigned NumLaneElts = NumElts / NumLanes;
24295 assert((NumLaneElts % 2 == 0) &&
24296 "Vector type should have an even number of elements in each lane");
24297 unsigned HalfLaneElts = NumLaneElts/2;
24299 // View LHS in the form
24300 // LHS = VECTOR_SHUFFLE A, B, LMask
24301 // If LHS is not a shuffle then pretend it is the shuffle
24302 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24303 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24306 SmallVector<int, 16> LMask(NumElts);
24307 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24308 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24309 A = LHS.getOperand(0);
24310 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24311 B = LHS.getOperand(1);
24312 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24313 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24315 if (LHS.getOpcode() != ISD::UNDEF)
24317 for (unsigned i = 0; i != NumElts; ++i)
24321 // Likewise, view RHS in the form
24322 // RHS = VECTOR_SHUFFLE C, D, RMask
24324 SmallVector<int, 16> RMask(NumElts);
24325 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24326 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24327 C = RHS.getOperand(0);
24328 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24329 D = RHS.getOperand(1);
24330 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24331 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24333 if (RHS.getOpcode() != ISD::UNDEF)
24335 for (unsigned i = 0; i != NumElts; ++i)
24339 // Check that the shuffles are both shuffling the same vectors.
24340 if (!(A == C && B == D) && !(A == D && B == C))
24343 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24344 if (!A.getNode() && !B.getNode())
24347 // If A and B occur in reverse order in RHS, then "swap" them (which means
24348 // rewriting the mask).
24350 ShuffleVectorSDNode::commuteMask(RMask);
24352 // At this point LHS and RHS are equivalent to
24353 // LHS = VECTOR_SHUFFLE A, B, LMask
24354 // RHS = VECTOR_SHUFFLE A, B, RMask
24355 // Check that the masks correspond to performing a horizontal operation.
24356 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24357 for (unsigned i = 0; i != NumLaneElts; ++i) {
24358 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24360 // Ignore any UNDEF components.
24361 if (LIdx < 0 || RIdx < 0 ||
24362 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24363 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24366 // Check that successive elements are being operated on. If not, this is
24367 // not a horizontal operation.
24368 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24369 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24370 if (!(LIdx == Index && RIdx == Index + 1) &&
24371 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24376 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24377 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24381 /// Do target-specific dag combines on floating point adds.
24382 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24383 const X86Subtarget *Subtarget) {
24384 EVT VT = N->getValueType(0);
24385 SDValue LHS = N->getOperand(0);
24386 SDValue RHS = N->getOperand(1);
24388 // Try to synthesize horizontal adds from adds of shuffles.
24389 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24390 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24391 isHorizontalBinOp(LHS, RHS, true))
24392 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24396 /// Do target-specific dag combines on floating point subs.
24397 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24398 const X86Subtarget *Subtarget) {
24399 EVT VT = N->getValueType(0);
24400 SDValue LHS = N->getOperand(0);
24401 SDValue RHS = N->getOperand(1);
24403 // Try to synthesize horizontal subs from subs of shuffles.
24404 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24405 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24406 isHorizontalBinOp(LHS, RHS, false))
24407 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24411 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24412 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24413 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24415 // F[X]OR(0.0, x) -> x
24416 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24417 if (C->getValueAPF().isPosZero())
24418 return N->getOperand(1);
24420 // F[X]OR(x, 0.0) -> x
24421 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24422 if (C->getValueAPF().isPosZero())
24423 return N->getOperand(0);
24427 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24428 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24429 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24431 // Only perform optimizations if UnsafeMath is used.
24432 if (!DAG.getTarget().Options.UnsafeFPMath)
24435 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24436 // into FMINC and FMAXC, which are Commutative operations.
24437 unsigned NewOp = 0;
24438 switch (N->getOpcode()) {
24439 default: llvm_unreachable("unknown opcode");
24440 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24441 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24444 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24445 N->getOperand(0), N->getOperand(1));
24448 /// Do target-specific dag combines on X86ISD::FAND nodes.
24449 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24450 // FAND(0.0, x) -> 0.0
24451 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24452 if (C->getValueAPF().isPosZero())
24453 return N->getOperand(0);
24455 // FAND(x, 0.0) -> 0.0
24456 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24457 if (C->getValueAPF().isPosZero())
24458 return N->getOperand(1);
24463 /// Do target-specific dag combines on X86ISD::FANDN nodes
24464 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24465 // FANDN(0.0, x) -> x
24466 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24467 if (C->getValueAPF().isPosZero())
24468 return N->getOperand(1);
24470 // FANDN(x, 0.0) -> 0.0
24471 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24472 if (C->getValueAPF().isPosZero())
24473 return N->getOperand(1);
24478 static SDValue PerformBTCombine(SDNode *N,
24480 TargetLowering::DAGCombinerInfo &DCI) {
24481 // BT ignores high bits in the bit index operand.
24482 SDValue Op1 = N->getOperand(1);
24483 if (Op1.hasOneUse()) {
24484 unsigned BitWidth = Op1.getValueSizeInBits();
24485 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24486 APInt KnownZero, KnownOne;
24487 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24488 !DCI.isBeforeLegalizeOps());
24489 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24490 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24491 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24492 DCI.CommitTargetLoweringOpt(TLO);
24497 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24498 SDValue Op = N->getOperand(0);
24499 if (Op.getOpcode() == ISD::BITCAST)
24500 Op = Op.getOperand(0);
24501 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24502 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24503 VT.getVectorElementType().getSizeInBits() ==
24504 OpVT.getVectorElementType().getSizeInBits()) {
24505 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24510 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24511 const X86Subtarget *Subtarget) {
24512 EVT VT = N->getValueType(0);
24513 if (!VT.isVector())
24516 SDValue N0 = N->getOperand(0);
24517 SDValue N1 = N->getOperand(1);
24518 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24521 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24522 // both SSE and AVX2 since there is no sign-extended shift right
24523 // operation on a vector with 64-bit elements.
24524 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24525 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24526 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24527 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24528 SDValue N00 = N0.getOperand(0);
24530 // EXTLOAD has a better solution on AVX2,
24531 // it may be replaced with X86ISD::VSEXT node.
24532 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24533 if (!ISD::isNormalLoad(N00.getNode()))
24536 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24537 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24539 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24545 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24546 TargetLowering::DAGCombinerInfo &DCI,
24547 const X86Subtarget *Subtarget) {
24548 SDValue N0 = N->getOperand(0);
24549 EVT VT = N->getValueType(0);
24550 EVT SVT = VT.getScalarType();
24551 EVT InVT = N0.getValueType();
24552 EVT InSVT = InVT.getScalarType();
24555 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24556 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24557 // This exposes the sext to the sdivrem lowering, so that it directly extends
24558 // from AH (which we otherwise need to do contortions to access).
24559 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24560 InVT == MVT::i8 && VT == MVT::i32) {
24561 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24562 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24563 N0.getOperand(0), N0.getOperand(1));
24564 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24565 return R.getValue(1);
24568 if (!DCI.isBeforeLegalizeOps()) {
24569 if (InVT == MVT::i1) {
24570 SDValue Zero = DAG.getConstant(0, DL, VT);
24572 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24573 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24578 if (VT.isVector() && Subtarget->hasSSE2()) {
24579 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
24580 EVT InVT = N.getValueType();
24581 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24582 Size / InVT.getScalarSizeInBits());
24583 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
24584 DAG.getUNDEF(InVT));
24586 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24589 // If target-size is less than 128-bits, extend to a type that would extend
24590 // to 128 bits, extend that and extract the original target vector.
24591 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
24592 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24593 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24594 unsigned Scale = 128 / VT.getSizeInBits();
24596 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
24597 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
24598 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
24599 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
24600 DAG.getIntPtrConstant(0, DL));
24603 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24604 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24605 if (VT.getSizeInBits() == 128 &&
24606 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24607 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24608 SDValue ExOp = ExtendVecSize(DL, N0, 128);
24609 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
24612 // On pre-AVX2 targets, split into 128-bit nodes of
24613 // ISD::SIGN_EXTEND_VECTOR_INREG.
24614 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
24615 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24616 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24617 unsigned NumVecs = VT.getSizeInBits() / 128;
24618 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24619 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24620 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24622 SmallVector<SDValue, 8> Opnds;
24623 for (unsigned i = 0, Offset = 0; i != NumVecs;
24624 ++i, Offset += NumSubElts) {
24625 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24626 DAG.getIntPtrConstant(Offset, DL));
24627 SrcVec = ExtendVecSize(DL, SrcVec, 128);
24628 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24629 Opnds.push_back(SrcVec);
24631 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24635 if (!Subtarget->hasFp256())
24638 if (VT.isVector() && VT.getSizeInBits() == 256)
24639 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24645 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24646 const X86Subtarget* Subtarget) {
24648 EVT VT = N->getValueType(0);
24650 // Let legalize expand this if it isn't a legal type yet.
24651 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24654 EVT ScalarVT = VT.getScalarType();
24655 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24656 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
24657 !Subtarget->hasAVX512()))
24660 SDValue A = N->getOperand(0);
24661 SDValue B = N->getOperand(1);
24662 SDValue C = N->getOperand(2);
24664 bool NegA = (A.getOpcode() == ISD::FNEG);
24665 bool NegB = (B.getOpcode() == ISD::FNEG);
24666 bool NegC = (C.getOpcode() == ISD::FNEG);
24668 // Negative multiplication when NegA xor NegB
24669 bool NegMul = (NegA != NegB);
24671 A = A.getOperand(0);
24673 B = B.getOperand(0);
24675 C = C.getOperand(0);
24679 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24681 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24683 return DAG.getNode(Opcode, dl, VT, A, B, C);
24686 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24687 TargetLowering::DAGCombinerInfo &DCI,
24688 const X86Subtarget *Subtarget) {
24689 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24690 // (and (i32 x86isd::setcc_carry), 1)
24691 // This eliminates the zext. This transformation is necessary because
24692 // ISD::SETCC is always legalized to i8.
24694 SDValue N0 = N->getOperand(0);
24695 EVT VT = N->getValueType(0);
24697 if (N0.getOpcode() == ISD::AND &&
24699 N0.getOperand(0).hasOneUse()) {
24700 SDValue N00 = N0.getOperand(0);
24701 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24702 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24703 if (!C || C->getZExtValue() != 1)
24705 return DAG.getNode(ISD::AND, dl, VT,
24706 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24707 N00.getOperand(0), N00.getOperand(1)),
24708 DAG.getConstant(1, dl, VT));
24712 if (N0.getOpcode() == ISD::TRUNCATE &&
24714 N0.getOperand(0).hasOneUse()) {
24715 SDValue N00 = N0.getOperand(0);
24716 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24717 return DAG.getNode(ISD::AND, dl, VT,
24718 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24719 N00.getOperand(0), N00.getOperand(1)),
24720 DAG.getConstant(1, dl, VT));
24724 if (VT.is256BitVector())
24725 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24728 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24729 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24730 // This exposes the zext to the udivrem lowering, so that it directly extends
24731 // from AH (which we otherwise need to do contortions to access).
24732 if (N0.getOpcode() == ISD::UDIVREM &&
24733 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24734 (VT == MVT::i32 || VT == MVT::i64)) {
24735 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24736 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24737 N0.getOperand(0), N0.getOperand(1));
24738 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24739 return R.getValue(1);
24745 // Optimize x == -y --> x+y == 0
24746 // x != -y --> x+y != 0
24747 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24748 const X86Subtarget* Subtarget) {
24749 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24750 SDValue LHS = N->getOperand(0);
24751 SDValue RHS = N->getOperand(1);
24752 EVT VT = N->getValueType(0);
24755 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24756 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24757 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24758 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24759 LHS.getOperand(1));
24760 return DAG.getSetCC(DL, N->getValueType(0), addV,
24761 DAG.getConstant(0, DL, addV.getValueType()), CC);
24763 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24764 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24765 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24766 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24767 RHS.getOperand(1));
24768 return DAG.getSetCC(DL, N->getValueType(0), addV,
24769 DAG.getConstant(0, DL, addV.getValueType()), CC);
24772 if (VT.getScalarType() == MVT::i1 &&
24773 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24775 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24776 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24777 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24779 if (!IsSEXT0 || !IsVZero1) {
24780 // Swap the operands and update the condition code.
24781 std::swap(LHS, RHS);
24782 CC = ISD::getSetCCSwappedOperands(CC);
24784 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24785 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24786 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24789 if (IsSEXT0 && IsVZero1) {
24790 assert(VT == LHS.getOperand(0).getValueType() &&
24791 "Uexpected operand type");
24792 if (CC == ISD::SETGT)
24793 return DAG.getConstant(0, DL, VT);
24794 if (CC == ISD::SETLE)
24795 return DAG.getConstant(1, DL, VT);
24796 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24797 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24799 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24800 "Unexpected condition code!");
24801 return LHS.getOperand(0);
24808 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24809 SelectionDAG &DAG) {
24811 MVT VT = Load->getSimpleValueType(0);
24812 MVT EVT = VT.getVectorElementType();
24813 SDValue Addr = Load->getOperand(1);
24814 SDValue NewAddr = DAG.getNode(
24815 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24816 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24817 Addr.getSimpleValueType()));
24820 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24821 DAG.getMachineFunction().getMachineMemOperand(
24822 Load->getMemOperand(), 0, EVT.getStoreSize()));
24826 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24827 const X86Subtarget *Subtarget) {
24829 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24830 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24831 "X86insertps is only defined for v4x32");
24833 SDValue Ld = N->getOperand(1);
24834 if (MayFoldLoad(Ld)) {
24835 // Extract the countS bits from the immediate so we can get the proper
24836 // address when narrowing the vector load to a specific element.
24837 // When the second source op is a memory address, insertps doesn't use
24838 // countS and just gets an f32 from that address.
24839 unsigned DestIndex =
24840 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24842 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24844 // Create this as a scalar to vector to match the instruction pattern.
24845 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24846 // countS bits are ignored when loading from memory on insertps, which
24847 // means we don't need to explicitly set them to 0.
24848 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24849 LoadScalarToVector, N->getOperand(2));
24854 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24855 SDValue V0 = N->getOperand(0);
24856 SDValue V1 = N->getOperand(1);
24858 EVT VT = N->getValueType(0);
24860 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24861 // operands and changing the mask to 1. This saves us a bunch of
24862 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24863 // x86InstrInfo knows how to commute this back after instruction selection
24864 // if it would help register allocation.
24866 // TODO: If optimizing for size or a processor that doesn't suffer from
24867 // partial register update stalls, this should be transformed into a MOVSD
24868 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24870 if (VT == MVT::v2f64)
24871 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24872 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24873 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24874 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24880 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24881 // as "sbb reg,reg", since it can be extended without zext and produces
24882 // an all-ones bit which is more useful than 0/1 in some cases.
24883 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24886 return DAG.getNode(ISD::AND, DL, VT,
24887 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24888 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24890 DAG.getConstant(1, DL, VT));
24891 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24892 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24893 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24894 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24898 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24899 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24900 TargetLowering::DAGCombinerInfo &DCI,
24901 const X86Subtarget *Subtarget) {
24903 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24904 SDValue EFLAGS = N->getOperand(1);
24906 if (CC == X86::COND_A) {
24907 // Try to convert COND_A into COND_B in an attempt to facilitate
24908 // materializing "setb reg".
24910 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24911 // cannot take an immediate as its first operand.
24913 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24914 EFLAGS.getValueType().isInteger() &&
24915 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24916 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24917 EFLAGS.getNode()->getVTList(),
24918 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24919 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24920 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24924 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24925 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24927 if (CC == X86::COND_B)
24928 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24930 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24931 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24932 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24938 // Optimize branch condition evaluation.
24940 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24941 TargetLowering::DAGCombinerInfo &DCI,
24942 const X86Subtarget *Subtarget) {
24944 SDValue Chain = N->getOperand(0);
24945 SDValue Dest = N->getOperand(1);
24946 SDValue EFLAGS = N->getOperand(3);
24947 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24949 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24950 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24951 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24958 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24959 SelectionDAG &DAG) {
24960 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24961 // optimize away operation when it's from a constant.
24963 // The general transformation is:
24964 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24965 // AND(VECTOR_CMP(x,y), constant2)
24966 // constant2 = UNARYOP(constant)
24968 // Early exit if this isn't a vector operation, the operand of the
24969 // unary operation isn't a bitwise AND, or if the sizes of the operations
24970 // aren't the same.
24971 EVT VT = N->getValueType(0);
24972 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24973 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24974 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24977 // Now check that the other operand of the AND is a constant. We could
24978 // make the transformation for non-constant splats as well, but it's unclear
24979 // that would be a benefit as it would not eliminate any operations, just
24980 // perform one more step in scalar code before moving to the vector unit.
24981 if (BuildVectorSDNode *BV =
24982 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24983 // Bail out if the vector isn't a constant.
24984 if (!BV->isConstant())
24987 // Everything checks out. Build up the new and improved node.
24989 EVT IntVT = BV->getValueType(0);
24990 // Create a new constant of the appropriate type for the transformed
24992 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24993 // The AND node needs bitcasts to/from an integer vector type around it.
24994 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
24995 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24996 N->getOperand(0)->getOperand(0), MaskConst);
24997 SDValue Res = DAG.getBitcast(VT, NewAnd);
25004 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25005 const X86Subtarget *Subtarget) {
25006 SDValue Op0 = N->getOperand(0);
25007 EVT VT = N->getValueType(0);
25008 EVT InVT = Op0.getValueType();
25009 EVT InSVT = InVT.getScalarType();
25010 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25012 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
25013 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
25014 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25016 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25017 InVT.getVectorNumElements());
25018 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
25020 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
25021 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
25023 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25029 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25030 const X86Subtarget *Subtarget) {
25031 // First try to optimize away the conversion entirely when it's
25032 // conditionally from a constant. Vectors only.
25033 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
25036 // Now move on to more general possibilities.
25037 SDValue Op0 = N->getOperand(0);
25038 EVT VT = N->getValueType(0);
25039 EVT InVT = Op0.getValueType();
25040 EVT InSVT = InVT.getScalarType();
25042 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
25043 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
25044 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25046 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25047 InVT.getVectorNumElements());
25048 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25049 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25052 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25053 // a 32-bit target where SSE doesn't support i64->FP operations.
25054 if (Op0.getOpcode() == ISD::LOAD) {
25055 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25056 EVT LdVT = Ld->getValueType(0);
25058 // This transformation is not supported if the result type is f16
25059 if (VT == MVT::f16)
25062 if (!Ld->isVolatile() && !VT.isVector() &&
25063 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25064 !Subtarget->is64Bit() && LdVT == MVT::i64) {
25065 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
25066 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
25067 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25074 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25075 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25076 X86TargetLowering::DAGCombinerInfo &DCI) {
25077 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25078 // the result is either zero or one (depending on the input carry bit).
25079 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25080 if (X86::isZeroNode(N->getOperand(0)) &&
25081 X86::isZeroNode(N->getOperand(1)) &&
25082 // We don't have a good way to replace an EFLAGS use, so only do this when
25084 SDValue(N, 1).use_empty()) {
25086 EVT VT = N->getValueType(0);
25087 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
25088 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25089 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25090 DAG.getConstant(X86::COND_B, DL,
25093 DAG.getConstant(1, DL, VT));
25094 return DCI.CombineTo(N, Res1, CarryOut);
25100 // fold (add Y, (sete X, 0)) -> adc 0, Y
25101 // (add Y, (setne X, 0)) -> sbb -1, Y
25102 // (sub (sete X, 0), Y) -> sbb 0, Y
25103 // (sub (setne X, 0), Y) -> adc -1, Y
25104 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25107 // Look through ZExts.
25108 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25109 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25112 SDValue SetCC = Ext.getOperand(0);
25113 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25116 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25117 if (CC != X86::COND_E && CC != X86::COND_NE)
25120 SDValue Cmp = SetCC.getOperand(1);
25121 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25122 !X86::isZeroNode(Cmp.getOperand(1)) ||
25123 !Cmp.getOperand(0).getValueType().isInteger())
25126 SDValue CmpOp0 = Cmp.getOperand(0);
25127 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25128 DAG.getConstant(1, DL, CmpOp0.getValueType()));
25130 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25131 if (CC == X86::COND_NE)
25132 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25133 DL, OtherVal.getValueType(), OtherVal,
25134 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
25136 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25137 DL, OtherVal.getValueType(), OtherVal,
25138 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
25141 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25142 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25143 const X86Subtarget *Subtarget) {
25144 EVT VT = N->getValueType(0);
25145 SDValue Op0 = N->getOperand(0);
25146 SDValue Op1 = N->getOperand(1);
25148 // Try to synthesize horizontal adds from adds of shuffles.
25149 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25150 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25151 isHorizontalBinOp(Op0, Op1, true))
25152 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25154 return OptimizeConditionalInDecrement(N, DAG);
25157 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25158 const X86Subtarget *Subtarget) {
25159 SDValue Op0 = N->getOperand(0);
25160 SDValue Op1 = N->getOperand(1);
25162 // X86 can't encode an immediate LHS of a sub. See if we can push the
25163 // negation into a preceding instruction.
25164 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25165 // If the RHS of the sub is a XOR with one use and a constant, invert the
25166 // immediate. Then add one to the LHS of the sub so we can turn
25167 // X-Y -> X+~Y+1, saving one register.
25168 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25169 isa<ConstantSDNode>(Op1.getOperand(1))) {
25170 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25171 EVT VT = Op0.getValueType();
25172 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25174 DAG.getConstant(~XorC, SDLoc(Op1), VT));
25175 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25176 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
25180 // Try to synthesize horizontal adds from adds of shuffles.
25181 EVT VT = N->getValueType(0);
25182 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25183 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25184 isHorizontalBinOp(Op0, Op1, true))
25185 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25187 return OptimizeConditionalInDecrement(N, DAG);
25190 /// performVZEXTCombine - Performs build vector combines
25191 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25192 TargetLowering::DAGCombinerInfo &DCI,
25193 const X86Subtarget *Subtarget) {
25195 MVT VT = N->getSimpleValueType(0);
25196 SDValue Op = N->getOperand(0);
25197 MVT OpVT = Op.getSimpleValueType();
25198 MVT OpEltVT = OpVT.getVectorElementType();
25199 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25201 // (vzext (bitcast (vzext (x)) -> (vzext x)
25203 while (V.getOpcode() == ISD::BITCAST)
25204 V = V.getOperand(0);
25206 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25207 MVT InnerVT = V.getSimpleValueType();
25208 MVT InnerEltVT = InnerVT.getVectorElementType();
25210 // If the element sizes match exactly, we can just do one larger vzext. This
25211 // is always an exact type match as vzext operates on integer types.
25212 if (OpEltVT == InnerEltVT) {
25213 assert(OpVT == InnerVT && "Types must match for vzext!");
25214 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25217 // The only other way we can combine them is if only a single element of the
25218 // inner vzext is used in the input to the outer vzext.
25219 if (InnerEltVT.getSizeInBits() < InputBits)
25222 // In this case, the inner vzext is completely dead because we're going to
25223 // only look at bits inside of the low element. Just do the outer vzext on
25224 // a bitcast of the input to the inner.
25225 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
25228 // Check if we can bypass extracting and re-inserting an element of an input
25229 // vector. Essentialy:
25230 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25231 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25232 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25233 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25234 SDValue ExtractedV = V.getOperand(0);
25235 SDValue OrigV = ExtractedV.getOperand(0);
25236 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25237 if (ExtractIdx->getZExtValue() == 0) {
25238 MVT OrigVT = OrigV.getSimpleValueType();
25239 // Extract a subvector if necessary...
25240 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25241 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25242 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25243 OrigVT.getVectorNumElements() / Ratio);
25244 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25245 DAG.getIntPtrConstant(0, DL));
25247 Op = DAG.getBitcast(OpVT, OrigV);
25248 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25255 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25256 DAGCombinerInfo &DCI) const {
25257 SelectionDAG &DAG = DCI.DAG;
25258 switch (N->getOpcode()) {
25260 case ISD::EXTRACT_VECTOR_ELT:
25261 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25264 case X86ISD::SHRUNKBLEND:
25265 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25266 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
25267 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25268 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25269 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25270 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25271 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25274 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25275 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25276 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25277 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25278 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25279 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
25280 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25281 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
25282 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
25283 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
25284 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25285 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25287 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25289 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25290 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25291 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25292 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25293 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25294 case ISD::ANY_EXTEND:
25295 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25296 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25297 case ISD::SIGN_EXTEND_INREG:
25298 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25299 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25300 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25301 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25302 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25303 case X86ISD::SHUFP: // Handle all target specific shuffles
25304 case X86ISD::PALIGNR:
25305 case X86ISD::UNPCKH:
25306 case X86ISD::UNPCKL:
25307 case X86ISD::MOVHLPS:
25308 case X86ISD::MOVLHPS:
25309 case X86ISD::PSHUFB:
25310 case X86ISD::PSHUFD:
25311 case X86ISD::PSHUFHW:
25312 case X86ISD::PSHUFLW:
25313 case X86ISD::MOVSS:
25314 case X86ISD::MOVSD:
25315 case X86ISD::VPERMILPI:
25316 case X86ISD::VPERM2X128:
25317 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25318 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25319 case ISD::INTRINSIC_WO_CHAIN:
25320 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25321 case X86ISD::INSERTPS: {
25322 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
25323 return PerformINSERTPSCombine(N, DAG, Subtarget);
25326 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
25332 /// isTypeDesirableForOp - Return true if the target has native support for
25333 /// the specified value type and it is 'desirable' to use the type for the
25334 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25335 /// instruction encodings are longer and some i16 instructions are slow.
25336 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25337 if (!isTypeLegal(VT))
25339 if (VT != MVT::i16)
25346 case ISD::SIGN_EXTEND:
25347 case ISD::ZERO_EXTEND:
25348 case ISD::ANY_EXTEND:
25361 /// IsDesirableToPromoteOp - This method query the target whether it is
25362 /// beneficial for dag combiner to promote the specified node. If true, it
25363 /// should return the desired promotion type by reference.
25364 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25365 EVT VT = Op.getValueType();
25366 if (VT != MVT::i16)
25369 bool Promote = false;
25370 bool Commute = false;
25371 switch (Op.getOpcode()) {
25374 LoadSDNode *LD = cast<LoadSDNode>(Op);
25375 // If the non-extending load has a single use and it's not live out, then it
25376 // might be folded.
25377 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25378 Op.hasOneUse()*/) {
25379 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25380 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25381 // The only case where we'd want to promote LOAD (rather then it being
25382 // promoted as an operand is when it's only use is liveout.
25383 if (UI->getOpcode() != ISD::CopyToReg)
25390 case ISD::SIGN_EXTEND:
25391 case ISD::ZERO_EXTEND:
25392 case ISD::ANY_EXTEND:
25397 SDValue N0 = Op.getOperand(0);
25398 // Look out for (store (shl (load), x)).
25399 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25412 SDValue N0 = Op.getOperand(0);
25413 SDValue N1 = Op.getOperand(1);
25414 if (!Commute && MayFoldLoad(N1))
25416 // Avoid disabling potential load folding opportunities.
25417 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25419 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25429 //===----------------------------------------------------------------------===//
25430 // X86 Inline Assembly Support
25431 //===----------------------------------------------------------------------===//
25433 // Helper to match a string separated by whitespace.
25434 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
25435 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
25437 for (StringRef Piece : Pieces) {
25438 if (!S.startswith(Piece)) // Check if the piece matches.
25441 S = S.substr(Piece.size());
25442 StringRef::size_type Pos = S.find_first_not_of(" \t");
25443 if (Pos == 0) // We matched a prefix.
25452 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25454 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25455 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25456 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25457 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25459 if (AsmPieces.size() == 3)
25461 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25468 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25469 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25471 std::string AsmStr = IA->getAsmString();
25473 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25474 if (!Ty || Ty->getBitWidth() % 16 != 0)
25477 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25478 SmallVector<StringRef, 4> AsmPieces;
25479 SplitString(AsmStr, AsmPieces, ";\n");
25481 switch (AsmPieces.size()) {
25482 default: return false;
25484 // FIXME: this should verify that we are targeting a 486 or better. If not,
25485 // we will turn this bswap into something that will be lowered to logical
25486 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25487 // lower so don't worry about this.
25489 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
25490 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
25491 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
25492 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
25493 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
25494 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
25495 // No need to check constraints, nothing other than the equivalent of
25496 // "=r,0" would be valid here.
25497 return IntrinsicLowering::LowerToByteSwap(CI);
25500 // rorw $$8, ${0:w} --> llvm.bswap.i16
25501 if (CI->getType()->isIntegerTy(16) &&
25502 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25503 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
25504 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
25506 StringRef ConstraintsStr = IA->getConstraintString();
25507 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25508 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25509 if (clobbersFlagRegisters(AsmPieces))
25510 return IntrinsicLowering::LowerToByteSwap(CI);
25514 if (CI->getType()->isIntegerTy(32) &&
25515 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25516 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
25517 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
25518 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
25520 StringRef ConstraintsStr = IA->getConstraintString();
25521 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25522 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25523 if (clobbersFlagRegisters(AsmPieces))
25524 return IntrinsicLowering::LowerToByteSwap(CI);
25527 if (CI->getType()->isIntegerTy(64)) {
25528 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25529 if (Constraints.size() >= 2 &&
25530 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25531 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25532 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25533 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
25534 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
25535 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
25536 return IntrinsicLowering::LowerToByteSwap(CI);
25544 /// getConstraintType - Given a constraint letter, return the type of
25545 /// constraint it is for this target.
25546 X86TargetLowering::ConstraintType
25547 X86TargetLowering::getConstraintType(StringRef Constraint) const {
25548 if (Constraint.size() == 1) {
25549 switch (Constraint[0]) {
25560 return C_RegisterClass;
25584 return TargetLowering::getConstraintType(Constraint);
25587 /// Examine constraint type and operand type and determine a weight value.
25588 /// This object must already have been set up with the operand type
25589 /// and the current alternative constraint selected.
25590 TargetLowering::ConstraintWeight
25591 X86TargetLowering::getSingleConstraintMatchWeight(
25592 AsmOperandInfo &info, const char *constraint) const {
25593 ConstraintWeight weight = CW_Invalid;
25594 Value *CallOperandVal = info.CallOperandVal;
25595 // If we don't have a value, we can't do a match,
25596 // but allow it at the lowest weight.
25597 if (!CallOperandVal)
25599 Type *type = CallOperandVal->getType();
25600 // Look at the constraint type.
25601 switch (*constraint) {
25603 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25614 if (CallOperandVal->getType()->isIntegerTy())
25615 weight = CW_SpecificReg;
25620 if (type->isFloatingPointTy())
25621 weight = CW_SpecificReg;
25624 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25625 weight = CW_SpecificReg;
25629 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25630 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25631 weight = CW_Register;
25634 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25635 if (C->getZExtValue() <= 31)
25636 weight = CW_Constant;
25640 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25641 if (C->getZExtValue() <= 63)
25642 weight = CW_Constant;
25646 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25647 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25648 weight = CW_Constant;
25652 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25653 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25654 weight = CW_Constant;
25658 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25659 if (C->getZExtValue() <= 3)
25660 weight = CW_Constant;
25664 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25665 if (C->getZExtValue() <= 0xff)
25666 weight = CW_Constant;
25671 if (isa<ConstantFP>(CallOperandVal)) {
25672 weight = CW_Constant;
25676 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25677 if ((C->getSExtValue() >= -0x80000000LL) &&
25678 (C->getSExtValue() <= 0x7fffffffLL))
25679 weight = CW_Constant;
25683 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25684 if (C->getZExtValue() <= 0xffffffff)
25685 weight = CW_Constant;
25692 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25693 /// with another that has more specific requirements based on the type of the
25694 /// corresponding operand.
25695 const char *X86TargetLowering::
25696 LowerXConstraint(EVT ConstraintVT) const {
25697 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25698 // 'f' like normal targets.
25699 if (ConstraintVT.isFloatingPoint()) {
25700 if (Subtarget->hasSSE2())
25702 if (Subtarget->hasSSE1())
25706 return TargetLowering::LowerXConstraint(ConstraintVT);
25709 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25710 /// vector. If it is invalid, don't add anything to Ops.
25711 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25712 std::string &Constraint,
25713 std::vector<SDValue>&Ops,
25714 SelectionDAG &DAG) const {
25717 // Only support length 1 constraints for now.
25718 if (Constraint.length() > 1) return;
25720 char ConstraintLetter = Constraint[0];
25721 switch (ConstraintLetter) {
25724 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25725 if (C->getZExtValue() <= 31) {
25726 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25727 Op.getValueType());
25733 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25734 if (C->getZExtValue() <= 63) {
25735 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25736 Op.getValueType());
25742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25743 if (isInt<8>(C->getSExtValue())) {
25744 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25745 Op.getValueType());
25751 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25752 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25753 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25754 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25755 Op.getValueType());
25761 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25762 if (C->getZExtValue() <= 3) {
25763 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25764 Op.getValueType());
25770 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25771 if (C->getZExtValue() <= 255) {
25772 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25773 Op.getValueType());
25779 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25780 if (C->getZExtValue() <= 127) {
25781 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25782 Op.getValueType());
25788 // 32-bit signed value
25789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25790 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25791 C->getSExtValue())) {
25792 // Widen to 64 bits here to get it sign extended.
25793 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25796 // FIXME gcc accepts some relocatable values here too, but only in certain
25797 // memory models; it's complicated.
25802 // 32-bit unsigned value
25803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25804 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25805 C->getZExtValue())) {
25806 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25807 Op.getValueType());
25811 // FIXME gcc accepts some relocatable values here too, but only in certain
25812 // memory models; it's complicated.
25816 // Literal immediates are always ok.
25817 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25818 // Widen to 64 bits here to get it sign extended.
25819 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25823 // In any sort of PIC mode addresses need to be computed at runtime by
25824 // adding in a register or some sort of table lookup. These can't
25825 // be used as immediates.
25826 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25829 // If we are in non-pic codegen mode, we allow the address of a global (with
25830 // an optional displacement) to be used with 'i'.
25831 GlobalAddressSDNode *GA = nullptr;
25832 int64_t Offset = 0;
25834 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25836 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25837 Offset += GA->getOffset();
25839 } else if (Op.getOpcode() == ISD::ADD) {
25840 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25841 Offset += C->getZExtValue();
25842 Op = Op.getOperand(0);
25845 } else if (Op.getOpcode() == ISD::SUB) {
25846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25847 Offset += -C->getZExtValue();
25848 Op = Op.getOperand(0);
25853 // Otherwise, this isn't something we can handle, reject it.
25857 const GlobalValue *GV = GA->getGlobal();
25858 // If we require an extra load to get this address, as in PIC mode, we
25859 // can't accept it.
25860 if (isGlobalStubReference(
25861 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25864 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25865 GA->getValueType(0), Offset);
25870 if (Result.getNode()) {
25871 Ops.push_back(Result);
25874 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25877 std::pair<unsigned, const TargetRegisterClass *>
25878 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25879 StringRef Constraint,
25881 // First, see if this is a constraint that directly corresponds to an LLVM
25883 if (Constraint.size() == 1) {
25884 // GCC Constraint Letters
25885 switch (Constraint[0]) {
25887 // TODO: Slight differences here in allocation order and leaving
25888 // RIP in the class. Do they matter any more here than they do
25889 // in the normal allocation?
25890 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25891 if (Subtarget->is64Bit()) {
25892 if (VT == MVT::i32 || VT == MVT::f32)
25893 return std::make_pair(0U, &X86::GR32RegClass);
25894 if (VT == MVT::i16)
25895 return std::make_pair(0U, &X86::GR16RegClass);
25896 if (VT == MVT::i8 || VT == MVT::i1)
25897 return std::make_pair(0U, &X86::GR8RegClass);
25898 if (VT == MVT::i64 || VT == MVT::f64)
25899 return std::make_pair(0U, &X86::GR64RegClass);
25902 // 32-bit fallthrough
25903 case 'Q': // Q_REGS
25904 if (VT == MVT::i32 || VT == MVT::f32)
25905 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25906 if (VT == MVT::i16)
25907 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25908 if (VT == MVT::i8 || VT == MVT::i1)
25909 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25910 if (VT == MVT::i64)
25911 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25913 case 'r': // GENERAL_REGS
25914 case 'l': // INDEX_REGS
25915 if (VT == MVT::i8 || VT == MVT::i1)
25916 return std::make_pair(0U, &X86::GR8RegClass);
25917 if (VT == MVT::i16)
25918 return std::make_pair(0U, &X86::GR16RegClass);
25919 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25920 return std::make_pair(0U, &X86::GR32RegClass);
25921 return std::make_pair(0U, &X86::GR64RegClass);
25922 case 'R': // LEGACY_REGS
25923 if (VT == MVT::i8 || VT == MVT::i1)
25924 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25925 if (VT == MVT::i16)
25926 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25927 if (VT == MVT::i32 || !Subtarget->is64Bit())
25928 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25929 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25930 case 'f': // FP Stack registers.
25931 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25932 // value to the correct fpstack register class.
25933 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25934 return std::make_pair(0U, &X86::RFP32RegClass);
25935 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25936 return std::make_pair(0U, &X86::RFP64RegClass);
25937 return std::make_pair(0U, &X86::RFP80RegClass);
25938 case 'y': // MMX_REGS if MMX allowed.
25939 if (!Subtarget->hasMMX()) break;
25940 return std::make_pair(0U, &X86::VR64RegClass);
25941 case 'Y': // SSE_REGS if SSE2 allowed
25942 if (!Subtarget->hasSSE2()) break;
25944 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25945 if (!Subtarget->hasSSE1()) break;
25947 switch (VT.SimpleTy) {
25949 // Scalar SSE types.
25952 return std::make_pair(0U, &X86::FR32RegClass);
25955 return std::make_pair(0U, &X86::FR64RegClass);
25963 return std::make_pair(0U, &X86::VR128RegClass);
25971 return std::make_pair(0U, &X86::VR256RegClass);
25976 return std::make_pair(0U, &X86::VR512RegClass);
25982 // Use the default implementation in TargetLowering to convert the register
25983 // constraint into a member of a register class.
25984 std::pair<unsigned, const TargetRegisterClass*> Res;
25985 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25987 // Not found as a standard register?
25989 // Map st(0) -> st(7) -> ST0
25990 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25991 tolower(Constraint[1]) == 's' &&
25992 tolower(Constraint[2]) == 't' &&
25993 Constraint[3] == '(' &&
25994 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25995 Constraint[5] == ')' &&
25996 Constraint[6] == '}') {
25998 Res.first = X86::FP0+Constraint[4]-'0';
25999 Res.second = &X86::RFP80RegClass;
26003 // GCC allows "st(0)" to be called just plain "st".
26004 if (StringRef("{st}").equals_lower(Constraint)) {
26005 Res.first = X86::FP0;
26006 Res.second = &X86::RFP80RegClass;
26011 if (StringRef("{flags}").equals_lower(Constraint)) {
26012 Res.first = X86::EFLAGS;
26013 Res.second = &X86::CCRRegClass;
26017 // 'A' means EAX + EDX.
26018 if (Constraint == "A") {
26019 Res.first = X86::EAX;
26020 Res.second = &X86::GR32_ADRegClass;
26026 // Otherwise, check to see if this is a register class of the wrong value
26027 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26028 // turn into {ax},{dx}.
26029 // MVT::Other is used to specify clobber names.
26030 if (Res.second->hasType(VT) || VT == MVT::Other)
26031 return Res; // Correct type already, nothing to do.
26033 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
26034 // return "eax". This should even work for things like getting 64bit integer
26035 // registers when given an f64 type.
26036 const TargetRegisterClass *Class = Res.second;
26037 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
26038 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
26039 unsigned Size = VT.getSizeInBits();
26040 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
26041 : Size == 16 ? MVT::i16
26042 : Size == 32 ? MVT::i32
26043 : Size == 64 ? MVT::i64
26045 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
26047 Res.first = DestReg;
26048 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
26049 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
26050 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
26051 : &X86::GR64RegClass;
26052 assert(Res.second->contains(Res.first) && "Register in register class");
26054 // No register found/type mismatch.
26056 Res.second = nullptr;
26058 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
26059 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
26060 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
26061 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
26062 Class == &X86::VR512RegClass) {
26063 // Handle references to XMM physical registers that got mapped into the
26064 // wrong class. This can happen with constraints like {xmm0} where the
26065 // target independent register mapper will just pick the first match it can
26066 // find, ignoring the required type.
26068 if (VT == MVT::f32 || VT == MVT::i32)
26069 Res.second = &X86::FR32RegClass;
26070 else if (VT == MVT::f64 || VT == MVT::i64)
26071 Res.second = &X86::FR64RegClass;
26072 else if (X86::VR128RegClass.hasType(VT))
26073 Res.second = &X86::VR128RegClass;
26074 else if (X86::VR256RegClass.hasType(VT))
26075 Res.second = &X86::VR256RegClass;
26076 else if (X86::VR512RegClass.hasType(VT))
26077 Res.second = &X86::VR512RegClass;
26079 // Type mismatch and not a clobber: Return an error;
26081 Res.second = nullptr;
26088 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26090 unsigned AS) const {
26091 // Scaling factors are not free at all.
26092 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26093 // will take 2 allocations in the out of order engine instead of 1
26094 // for plain addressing mode, i.e. inst (reg1).
26096 // vaddps (%rsi,%drx), %ymm0, %ymm1
26097 // Requires two allocations (one for the load, one for the computation)
26099 // vaddps (%rsi), %ymm0, %ymm1
26100 // Requires just 1 allocation, i.e., freeing allocations for other operations
26101 // and having less micro operations to execute.
26103 // For some X86 architectures, this is even worse because for instance for
26104 // stores, the complex addressing mode forces the instruction to use the
26105 // "load" ports instead of the dedicated "store" port.
26106 // E.g., on Haswell:
26107 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26108 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26109 if (isLegalAddressingMode(AM, Ty, AS))
26110 // Scale represents reg2 * scale, thus account for 1
26111 // as soon as we use a second register.
26112 return AM.Scale != 0;
26116 bool X86TargetLowering::isTargetFTOL() const {
26117 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();