1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MCTargetExpr.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
53 STATISTIC(NumTailCalls, "Number of tail calls");
56 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
58 // Disable16Bit - 16-bit operations typically have a larger encoding than
59 // corresponding 32-bit instructions, and 16-bit code is slow on some
60 // processors. This is an experimental flag to disable 16-bit operations
61 // (which forces them to be Legalized to 32-bit operations).
63 Disable16Bit("disable-16bit", cl::Hidden,
64 cl::desc("Disable use of 16-bit instructions"));
66 // Forward declarations.
67 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
70 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
71 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
72 default: llvm_unreachable("unknown subtarget type");
73 case X86Subtarget::isDarwin:
74 if (TM.getSubtarget<X86Subtarget>().is64Bit())
75 return new X8664_MachoTargetObjectFile();
76 return new TargetLoweringObjectFileMachO();
77 case X86Subtarget::isELF:
78 if (TM.getSubtarget<X86Subtarget>().is64Bit())
79 return new X8664_ELFTargetObjectFile(TM);
80 return new X8632_ELFTargetObjectFile(TM);
81 case X86Subtarget::isMingw:
82 case X86Subtarget::isCygwin:
83 case X86Subtarget::isWindows:
84 return new TargetLoweringObjectFileCOFF();
88 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
89 : TargetLowering(TM, createTLOF(TM)) {
90 Subtarget = &TM.getSubtarget<X86Subtarget>();
91 X86ScalarSSEf64 = Subtarget->hasSSE2();
92 X86ScalarSSEf32 = Subtarget->hasSSE1();
93 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
95 RegInfo = TM.getRegisterInfo();
98 // Set up the TargetLowering object.
100 // X86 is weird, it always uses i8 for shift amounts and setcc results.
101 setShiftAmountType(MVT::i8);
102 setBooleanContents(ZeroOrOneBooleanContent);
103 setSchedulingPreference(SchedulingForRegPressure);
104 setStackPointerRegisterToSaveRestore(X86StackPtr);
106 if (Subtarget->isTargetDarwin()) {
107 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
108 setUseUnderscoreSetJmp(false);
109 setUseUnderscoreLongJmp(false);
110 } else if (Subtarget->isTargetMingw()) {
111 // MS runtime is weird: it exports _setjmp, but longjmp!
112 setUseUnderscoreSetJmp(true);
113 setUseUnderscoreLongJmp(false);
115 setUseUnderscoreSetJmp(true);
116 setUseUnderscoreLongJmp(true);
119 // Set up the register classes.
120 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
122 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
123 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
124 if (Subtarget->is64Bit())
125 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
127 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
129 // We don't accept any truncstore of integer registers.
130 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
132 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
133 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
135 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
136 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
137 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
139 // SETOEQ and SETUNE require checking two conditions.
140 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
141 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
142 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
143 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
144 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
145 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
147 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
149 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
150 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
151 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
153 if (Subtarget->is64Bit()) {
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
155 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
156 } else if (!UseSoftFloat) {
157 if (X86ScalarSSEf64) {
158 // We have an impenetrably clever algorithm for ui64->double only.
159 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
161 // We have an algorithm for SSE2, and we turn this into a 64-bit
162 // FILD for other targets.
163 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
166 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
168 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
172 // SSE has no i16 to fp conversion, only i32
173 if (X86ScalarSSEf32) {
174 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
175 // f32 and f64 cases are Legal, f80 case is not
176 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
178 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
179 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
182 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
183 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
186 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
187 // are Legal, f80 is custom lowered.
188 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
189 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
191 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
193 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
194 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
201 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
202 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
205 // Handle FP_TO_UINT by promoting the destination to a larger signed
207 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
208 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
209 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
211 if (Subtarget->is64Bit()) {
212 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
213 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
214 } else if (!UseSoftFloat) {
215 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
216 // Expand FP_TO_UINT into a select.
217 // FIXME: We would like to use a Custom expander here eventually to do
218 // the optimal thing for SSE vs. the default expansion in the legalizer.
219 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
221 // With SSE3 we can use fisttpll to convert to a signed i64; without
222 // SSE, we're stuck with a fistpll.
223 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
226 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
227 if (!X86ScalarSSEf64) {
228 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
229 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
232 // Scalar integer divide and remainder are lowered to use operations that
233 // produce two results, to match the available instructions. This exposes
234 // the two-result form to trivial CSE, which is able to combine x/y and x%y
235 // into a single instruction.
237 // Scalar integer multiply-high is also lowered to use two-result
238 // operations, to match the available instructions. However, plain multiply
239 // (low) operations are left as Legal, as there are single-result
240 // instructions for this in x86. Using the two-result multiply instructions
241 // when both high and low results are needed must be arranged by dagcombine.
242 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
243 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
244 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
245 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
246 setOperationAction(ISD::SREM , MVT::i8 , Expand);
247 setOperationAction(ISD::UREM , MVT::i8 , Expand);
248 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
249 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
250 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
251 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
252 setOperationAction(ISD::SREM , MVT::i16 , Expand);
253 setOperationAction(ISD::UREM , MVT::i16 , Expand);
254 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
255 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
256 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
257 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
258 setOperationAction(ISD::SREM , MVT::i32 , Expand);
259 setOperationAction(ISD::UREM , MVT::i32 , Expand);
260 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
261 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
262 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
263 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
264 setOperationAction(ISD::SREM , MVT::i64 , Expand);
265 setOperationAction(ISD::UREM , MVT::i64 , Expand);
267 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
268 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
269 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
270 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
271 if (Subtarget->is64Bit())
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
276 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
277 setOperationAction(ISD::FREM , MVT::f32 , Expand);
278 setOperationAction(ISD::FREM , MVT::f64 , Expand);
279 setOperationAction(ISD::FREM , MVT::f80 , Expand);
280 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
282 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
283 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
284 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
285 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
287 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
288 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
290 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
291 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
293 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
294 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
295 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
296 if (Subtarget->is64Bit()) {
297 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
298 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
299 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
302 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
303 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
305 // These should be promoted to a larger select which is supported.
306 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
307 // X86 wants to expand cmov itself.
308 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
310 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
312 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
313 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
314 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
315 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
316 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
317 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
321 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
322 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
323 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
324 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
325 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
328 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
330 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
333 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
334 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
335 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
336 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
337 if (Subtarget->is64Bit())
338 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
339 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
340 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
341 if (Subtarget->is64Bit()) {
342 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
343 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
344 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
345 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
346 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
348 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
349 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
350 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
351 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
352 if (Subtarget->is64Bit()) {
353 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
354 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
355 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
358 if (Subtarget->hasSSE1())
359 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
361 if (!Subtarget->hasSSE2())
362 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
364 // Expand certain atomics
365 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
366 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
375 if (!Subtarget->is64Bit()) {
376 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
377 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
378 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
381 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
382 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
385 // FIXME - use subtarget debug flags
386 if (!Subtarget->isTargetDarwin() &&
387 !Subtarget->isTargetELF() &&
388 !Subtarget->isTargetCygMing()) {
389 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
392 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
393 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
395 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
396 if (Subtarget->is64Bit()) {
397 setExceptionPointerRegister(X86::RAX);
398 setExceptionSelectorRegister(X86::RDX);
400 setExceptionPointerRegister(X86::EAX);
401 setExceptionSelectorRegister(X86::EDX);
403 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
404 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
406 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
408 setOperationAction(ISD::TRAP, MVT::Other, Legal);
410 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
411 setOperationAction(ISD::VASTART , MVT::Other, Custom);
412 setOperationAction(ISD::VAEND , MVT::Other, Expand);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::VAARG , MVT::Other, Custom);
415 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
417 setOperationAction(ISD::VAARG , MVT::Other, Expand);
418 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
421 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
422 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
425 if (Subtarget->isTargetCygMing())
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
430 if (!UseSoftFloat && X86ScalarSSEf64) {
431 // f32 and f64 use SSE.
432 // Set up the FP register classes.
433 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
434 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
436 // Use ANDPD to simulate FABS.
437 setOperationAction(ISD::FABS , MVT::f64, Custom);
438 setOperationAction(ISD::FABS , MVT::f32, Custom);
440 // Use XORP to simulate FNEG.
441 setOperationAction(ISD::FNEG , MVT::f64, Custom);
442 setOperationAction(ISD::FNEG , MVT::f32, Custom);
444 // Use ANDPD and ORPD to simulate FCOPYSIGN.
445 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
446 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
448 // We don't support sin/cos/fmod
449 setOperationAction(ISD::FSIN , MVT::f64, Expand);
450 setOperationAction(ISD::FCOS , MVT::f64, Expand);
451 setOperationAction(ISD::FSIN , MVT::f32, Expand);
452 setOperationAction(ISD::FCOS , MVT::f32, Expand);
454 // Expand FP immediates into loads from the stack, except for the special
456 addLegalFPImmediate(APFloat(+0.0)); // xorpd
457 addLegalFPImmediate(APFloat(+0.0f)); // xorps
458 } else if (!UseSoftFloat && X86ScalarSSEf32) {
459 // Use SSE for f32, x87 for f64.
460 // Set up the FP register classes.
461 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
462 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
464 // Use ANDPS to simulate FABS.
465 setOperationAction(ISD::FABS , MVT::f32, Custom);
467 // Use XORP to simulate FNEG.
468 setOperationAction(ISD::FNEG , MVT::f32, Custom);
470 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
472 // Use ANDPS and ORPS to simulate FCOPYSIGN.
473 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
474 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
476 // We don't support sin/cos/fmod
477 setOperationAction(ISD::FSIN , MVT::f32, Expand);
478 setOperationAction(ISD::FCOS , MVT::f32, Expand);
480 // Special cases we handle for FP constants.
481 addLegalFPImmediate(APFloat(+0.0f)); // xorps
482 addLegalFPImmediate(APFloat(+0.0)); // FLD0
483 addLegalFPImmediate(APFloat(+1.0)); // FLD1
484 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
485 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
488 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
489 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
491 } else if (!UseSoftFloat) {
492 // f32 and f64 in x87.
493 // Set up the FP register classes.
494 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
495 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
497 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
498 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
499 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
500 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
503 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
504 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
506 addLegalFPImmediate(APFloat(+0.0)); // FLD0
507 addLegalFPImmediate(APFloat(+1.0)); // FLD1
508 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
509 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
510 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
511 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
512 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
513 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
516 // Long double always uses X87.
518 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
519 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
520 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
523 APFloat TmpFlt(+0.0);
524 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
526 addLegalFPImmediate(TmpFlt); // FLD0
528 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
529 APFloat TmpFlt2(+1.0);
530 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
532 addLegalFPImmediate(TmpFlt2); // FLD1
533 TmpFlt2.changeSign();
534 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
538 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
539 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
543 // Always use a library call for pow.
544 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
545 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
546 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
548 setOperationAction(ISD::FLOG, MVT::f80, Expand);
549 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
550 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
551 setOperationAction(ISD::FEXP, MVT::f80, Expand);
552 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
554 // First set operation action for all vector types to either promote
555 // (for widening) or expand (for scalarization). Then we will selectively
556 // turn on ones that can be effectively codegen'd.
557 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
558 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
559 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
574 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
575 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
608 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
609 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
610 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
611 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
612 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
613 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
614 setTruncStoreAction((MVT::SimpleValueType)VT,
615 (MVT::SimpleValueType)InnerVT, Expand);
616 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
617 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
618 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
621 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
622 // with -msoft-float, disable use of MMX as well.
623 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
624 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
625 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
626 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
627 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
628 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
630 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
631 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
632 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
633 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
635 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
636 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
637 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
638 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
640 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
641 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
643 setOperationAction(ISD::AND, MVT::v8i8, Promote);
644 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
645 setOperationAction(ISD::AND, MVT::v4i16, Promote);
646 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
647 setOperationAction(ISD::AND, MVT::v2i32, Promote);
648 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
649 setOperationAction(ISD::AND, MVT::v1i64, Legal);
651 setOperationAction(ISD::OR, MVT::v8i8, Promote);
652 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
653 setOperationAction(ISD::OR, MVT::v4i16, Promote);
654 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
655 setOperationAction(ISD::OR, MVT::v2i32, Promote);
656 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
657 setOperationAction(ISD::OR, MVT::v1i64, Legal);
659 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
660 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
661 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
662 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
663 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
664 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
665 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
667 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
668 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
669 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
670 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
671 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
672 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
673 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
674 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
675 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
677 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
678 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
679 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
680 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
681 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
686 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
688 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
689 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
691 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
693 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
695 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
696 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
697 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
698 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
699 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
700 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
701 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
704 if (!UseSoftFloat && Subtarget->hasSSE1()) {
705 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
707 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
708 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
709 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
710 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
711 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
712 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
713 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
714 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
715 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
716 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
717 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
718 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
721 if (!UseSoftFloat && Subtarget->hasSSE2()) {
722 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
724 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
725 // registers cannot be used even for integer operations.
726 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
727 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
728 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
729 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
731 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
732 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
733 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
734 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
735 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
736 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
737 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
738 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
739 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
740 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
741 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
742 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
743 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
744 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
745 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
746 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
748 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
749 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
750 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
751 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
754 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
757 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
759 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
760 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
763 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
765 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
766 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
767 EVT VT = (MVT::SimpleValueType)i;
768 // Do not attempt to custom lower non-power-of-2 vectors
769 if (!isPowerOf2_32(VT.getVectorNumElements()))
771 // Do not attempt to custom lower non-128-bit vectors
772 if (!VT.is128BitVector())
774 setOperationAction(ISD::BUILD_VECTOR,
775 VT.getSimpleVT().SimpleTy, Custom);
776 setOperationAction(ISD::VECTOR_SHUFFLE,
777 VT.getSimpleVT().SimpleTy, Custom);
778 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
779 VT.getSimpleVT().SimpleTy, Custom);
782 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
783 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
785 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
786 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
787 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
789 if (Subtarget->is64Bit()) {
790 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
791 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
794 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
795 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
796 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
799 // Do not attempt to promote non-128-bit vectors
800 if (!VT.is128BitVector()) {
803 setOperationAction(ISD::AND, SVT, Promote);
804 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
805 setOperationAction(ISD::OR, SVT, Promote);
806 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
807 setOperationAction(ISD::XOR, SVT, Promote);
808 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
809 setOperationAction(ISD::LOAD, SVT, Promote);
810 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
811 setOperationAction(ISD::SELECT, SVT, Promote);
812 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
815 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
817 // Custom lower v2i64 and v2f64 selects.
818 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
819 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
820 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
821 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
823 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
824 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
825 if (!DisableMMX && Subtarget->hasMMX()) {
826 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
827 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
831 if (Subtarget->hasSSE41()) {
832 // FIXME: Do we need to handle scalar-to-vector here?
833 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
835 // i8 and i16 vectors are custom , because the source register and source
836 // source memory operand types are not the same width. f32 vectors are
837 // custom since the immediate controlling the insert encodes additional
839 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
844 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
845 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
849 if (Subtarget->is64Bit()) {
850 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
855 if (Subtarget->hasSSE42()) {
856 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
859 if (!UseSoftFloat && Subtarget->hasAVX()) {
860 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
861 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
862 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
863 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
865 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
866 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
867 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
868 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
869 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
870 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
871 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
872 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
873 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
874 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
875 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
876 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
877 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
878 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
879 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
881 // Operations to consider commented out -v16i16 v32i8
882 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
883 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
884 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
885 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
886 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
887 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
888 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
889 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
890 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
891 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
892 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
893 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
894 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
895 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
897 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
898 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
899 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
900 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
902 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
903 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
904 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
905 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
906 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
908 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
909 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
910 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
911 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
913 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
916 // Not sure we want to do this since there are no 256-bit integer
919 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
920 // This includes 256-bit vectors
921 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
922 EVT VT = (MVT::SimpleValueType)i;
924 // Do not attempt to custom lower non-power-of-2 vectors
925 if (!isPowerOf2_32(VT.getVectorNumElements()))
928 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
929 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
930 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
933 if (Subtarget->is64Bit()) {
934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
935 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
940 // Not sure we want to do this since there are no 256-bit integer
943 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
944 // Including 256-bit vectors
945 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
946 EVT VT = (MVT::SimpleValueType)i;
948 if (!VT.is256BitVector()) {
951 setOperationAction(ISD::AND, VT, Promote);
952 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
953 setOperationAction(ISD::OR, VT, Promote);
954 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
955 setOperationAction(ISD::XOR, VT, Promote);
956 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
957 setOperationAction(ISD::LOAD, VT, Promote);
958 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
959 setOperationAction(ISD::SELECT, VT, Promote);
960 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
963 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
967 // We want to custom lower some of our intrinsics.
968 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
970 // Add/Sub/Mul with overflow operations are custom lowered.
971 setOperationAction(ISD::SADDO, MVT::i32, Custom);
972 setOperationAction(ISD::SADDO, MVT::i64, Custom);
973 setOperationAction(ISD::UADDO, MVT::i32, Custom);
974 setOperationAction(ISD::UADDO, MVT::i64, Custom);
975 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
976 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
977 setOperationAction(ISD::USUBO, MVT::i32, Custom);
978 setOperationAction(ISD::USUBO, MVT::i64, Custom);
979 setOperationAction(ISD::SMULO, MVT::i32, Custom);
980 setOperationAction(ISD::SMULO, MVT::i64, Custom);
982 if (!Subtarget->is64Bit()) {
983 // These libcalls are not available in 32-bit.
984 setLibcallName(RTLIB::SHL_I128, 0);
985 setLibcallName(RTLIB::SRL_I128, 0);
986 setLibcallName(RTLIB::SRA_I128, 0);
989 // We have target-specific dag combine patterns for the following nodes:
990 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
991 setTargetDAGCombine(ISD::BUILD_VECTOR);
992 setTargetDAGCombine(ISD::SELECT);
993 setTargetDAGCombine(ISD::SHL);
994 setTargetDAGCombine(ISD::SRA);
995 setTargetDAGCombine(ISD::SRL);
996 setTargetDAGCombine(ISD::OR);
997 setTargetDAGCombine(ISD::STORE);
998 setTargetDAGCombine(ISD::MEMBARRIER);
999 setTargetDAGCombine(ISD::ZERO_EXTEND);
1000 if (Subtarget->is64Bit())
1001 setTargetDAGCombine(ISD::MUL);
1003 computeRegisterProperties();
1005 // FIXME: These should be based on subtarget info. Plus, the values should
1006 // be smaller when we are in optimizing for size mode.
1007 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1008 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1009 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1010 setPrefLoopAlignment(16);
1011 benefitFromCodePlacementOpt = true;
1015 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1020 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1021 /// the desired ByVal argument alignment.
1022 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1025 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1026 if (VTy->getBitWidth() == 128)
1028 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1029 unsigned EltAlign = 0;
1030 getMaxByValAlign(ATy->getElementType(), EltAlign);
1031 if (EltAlign > MaxAlign)
1032 MaxAlign = EltAlign;
1033 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1034 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1035 unsigned EltAlign = 0;
1036 getMaxByValAlign(STy->getElementType(i), EltAlign);
1037 if (EltAlign > MaxAlign)
1038 MaxAlign = EltAlign;
1046 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1047 /// function arguments in the caller parameter area. For X86, aggregates
1048 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1049 /// are at 4-byte boundaries.
1050 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1051 if (Subtarget->is64Bit()) {
1052 // Max of 8 and alignment of type.
1053 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1060 if (Subtarget->hasSSE1())
1061 getMaxByValAlign(Ty, Align);
1065 /// getOptimalMemOpType - Returns the target specific optimal type for load
1066 /// and store operations as a result of memset, memcpy, and memmove
1067 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1070 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1071 bool isSrcConst, bool isSrcStr,
1072 SelectionDAG &DAG) const {
1073 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1074 // linux. This is because the stack realignment code can't handle certain
1075 // cases like PR2962. This should be removed when PR2962 is fixed.
1076 const Function *F = DAG.getMachineFunction().getFunction();
1077 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1078 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1079 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1081 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1084 if (Subtarget->is64Bit() && Size >= 8)
1089 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1090 /// current function. The returned value is a member of the
1091 /// MachineJumpTableInfo::JTEntryKind enum.
1092 unsigned X86TargetLowering::getJumpTableEncoding() const {
1093 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1095 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1096 Subtarget->isPICStyleGOT())
1097 return MachineJumpTableInfo::EK_Custom32;
1099 // Otherwise, use the normal jump table encoding heuristics.
1100 return TargetLowering::getJumpTableEncoding();
1103 /// getPICBaseSymbol - Return the X86-32 PIC base.
1105 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1106 MCContext &Ctx) const {
1107 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1108 return Ctx.GetOrCreateTemporarySymbol(Twine(MAI.getPrivateGlobalPrefix())+
1109 Twine(MF->getFunctionNumber())+"$pb");
1114 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1115 const MachineBasicBlock *MBB,
1116 unsigned uid,MCContext &Ctx) const{
1117 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1118 Subtarget->isPICStyleGOT());
1119 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1121 return X86MCTargetExpr::Create(MBB->getSymbol(Ctx),
1122 X86MCTargetExpr::GOTOFF, Ctx);
1125 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1127 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1128 SelectionDAG &DAG) const {
1129 if (!Subtarget->is64Bit())
1130 // This doesn't have DebugLoc associated with it, but is not really the
1131 // same as a Register.
1132 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1137 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1138 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1140 const MCExpr *X86TargetLowering::
1141 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1142 MCContext &Ctx) const {
1143 // X86-64 uses RIP relative addressing based on the jump table label.
1144 if (Subtarget->isPICStyleRIPRel())
1145 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1147 // Otherwise, the reference is relative to the PIC base.
1148 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1151 /// getFunctionAlignment - Return the Log2 alignment of this function.
1152 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1153 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1156 //===----------------------------------------------------------------------===//
1157 // Return Value Calling Convention Implementation
1158 //===----------------------------------------------------------------------===//
1160 #include "X86GenCallingConv.inc"
1163 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1164 const SmallVectorImpl<EVT> &OutTys,
1165 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1166 SelectionDAG &DAG) {
1167 SmallVector<CCValAssign, 16> RVLocs;
1168 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1169 RVLocs, *DAG.getContext());
1170 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1174 X86TargetLowering::LowerReturn(SDValue Chain,
1175 CallingConv::ID CallConv, bool isVarArg,
1176 const SmallVectorImpl<ISD::OutputArg> &Outs,
1177 DebugLoc dl, SelectionDAG &DAG) {
1179 SmallVector<CCValAssign, 16> RVLocs;
1180 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1181 RVLocs, *DAG.getContext());
1182 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1184 // Add the regs to the liveout set for the function.
1185 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1186 for (unsigned i = 0; i != RVLocs.size(); ++i)
1187 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1188 MRI.addLiveOut(RVLocs[i].getLocReg());
1192 SmallVector<SDValue, 6> RetOps;
1193 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1194 // Operand #1 = Bytes To Pop
1195 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1197 // Copy the result values into the output registers.
1198 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1199 CCValAssign &VA = RVLocs[i];
1200 assert(VA.isRegLoc() && "Can only return in registers!");
1201 SDValue ValToCopy = Outs[i].Val;
1203 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1204 // the RET instruction and handled by the FP Stackifier.
1205 if (VA.getLocReg() == X86::ST0 ||
1206 VA.getLocReg() == X86::ST1) {
1207 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1208 // change the value to the FP stack register class.
1209 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1210 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1211 RetOps.push_back(ValToCopy);
1212 // Don't emit a copytoreg.
1216 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1217 // which is returned in RAX / RDX.
1218 if (Subtarget->is64Bit()) {
1219 EVT ValVT = ValToCopy.getValueType();
1220 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1221 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1222 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1223 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1227 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1228 Flag = Chain.getValue(1);
1231 // The x86-64 ABI for returning structs by value requires that we copy
1232 // the sret argument into %rax for the return. We saved the argument into
1233 // a virtual register in the entry block, so now we copy the value out
1235 if (Subtarget->is64Bit() &&
1236 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1237 MachineFunction &MF = DAG.getMachineFunction();
1238 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1239 unsigned Reg = FuncInfo->getSRetReturnReg();
1241 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64));
1242 FuncInfo->setSRetReturnReg(Reg);
1244 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1246 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1247 Flag = Chain.getValue(1);
1249 // RAX now acts like a return value.
1250 MRI.addLiveOut(X86::RAX);
1253 RetOps[0] = Chain; // Update chain.
1255 // Add the flag if we have it.
1257 RetOps.push_back(Flag);
1259 return DAG.getNode(X86ISD::RET_FLAG, dl,
1260 MVT::Other, &RetOps[0], RetOps.size());
1263 /// LowerCallResult - Lower the result values of a call into the
1264 /// appropriate copies out of appropriate physical registers.
1267 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1268 CallingConv::ID CallConv, bool isVarArg,
1269 const SmallVectorImpl<ISD::InputArg> &Ins,
1270 DebugLoc dl, SelectionDAG &DAG,
1271 SmallVectorImpl<SDValue> &InVals) {
1273 // Assign locations to each value returned by this call.
1274 SmallVector<CCValAssign, 16> RVLocs;
1275 bool Is64Bit = Subtarget->is64Bit();
1276 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1277 RVLocs, *DAG.getContext());
1278 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1280 // Copy all of the result registers out of their specified physreg.
1281 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1282 CCValAssign &VA = RVLocs[i];
1283 EVT CopyVT = VA.getValVT();
1285 // If this is x86-64, and we disabled SSE, we can't return FP values
1286 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1287 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1288 llvm_report_error("SSE register return with SSE disabled");
1291 // If this is a call to a function that returns an fp value on the floating
1292 // point stack, but where we prefer to use the value in xmm registers, copy
1293 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1294 if ((VA.getLocReg() == X86::ST0 ||
1295 VA.getLocReg() == X86::ST1) &&
1296 isScalarFPTypeInSSEReg(VA.getValVT())) {
1301 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1302 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1303 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1304 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1305 MVT::v2i64, InFlag).getValue(1);
1306 Val = Chain.getValue(0);
1307 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1308 Val, DAG.getConstant(0, MVT::i64));
1310 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1311 MVT::i64, InFlag).getValue(1);
1312 Val = Chain.getValue(0);
1314 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1316 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1317 CopyVT, InFlag).getValue(1);
1318 Val = Chain.getValue(0);
1320 InFlag = Chain.getValue(2);
1322 if (CopyVT != VA.getValVT()) {
1323 // Round the F80 the right size, which also moves to the appropriate xmm
1325 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1326 // This truncation won't change the value.
1327 DAG.getIntPtrConstant(1));
1330 InVals.push_back(Val);
1337 //===----------------------------------------------------------------------===//
1338 // C & StdCall & Fast Calling Convention implementation
1339 //===----------------------------------------------------------------------===//
1340 // StdCall calling convention seems to be standard for many Windows' API
1341 // routines and around. It differs from C calling convention just a little:
1342 // callee should clean up the stack, not caller. Symbols should be also
1343 // decorated in some fancy way :) It doesn't support any vector arguments.
1344 // For info on fast calling convention see Fast Calling Convention (tail call)
1345 // implementation LowerX86_32FastCCCallTo.
1347 /// CallIsStructReturn - Determines whether a call uses struct return
1349 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1353 return Outs[0].Flags.isSRet();
1356 /// ArgsAreStructReturn - Determines whether a function uses struct
1357 /// return semantics.
1359 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1363 return Ins[0].Flags.isSRet();
1366 /// IsCalleePop - Determines whether the callee is required to pop its
1367 /// own arguments. Callee pop is necessary to support tail calls.
1368 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1372 switch (CallingConv) {
1375 case CallingConv::X86_StdCall:
1376 return !Subtarget->is64Bit();
1377 case CallingConv::X86_FastCall:
1378 return !Subtarget->is64Bit();
1379 case CallingConv::Fast:
1380 return GuaranteedTailCallOpt;
1381 case CallingConv::GHC:
1382 return GuaranteedTailCallOpt;
1386 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1387 /// given CallingConvention value.
1388 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1389 if (Subtarget->is64Bit()) {
1390 if (CC == CallingConv::GHC)
1391 return CC_X86_64_GHC;
1392 else if (Subtarget->isTargetWin64())
1393 return CC_X86_Win64_C;
1398 if (CC == CallingConv::X86_FastCall)
1399 return CC_X86_32_FastCall;
1400 else if (CC == CallingConv::Fast)
1401 return CC_X86_32_FastCC;
1402 else if (CC == CallingConv::GHC)
1403 return CC_X86_32_GHC;
1408 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1409 /// by "Src" to address "Dst" with size and alignment information specified by
1410 /// the specific parameter attribute. The copy will be passed as a byval
1411 /// function parameter.
1413 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1414 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1416 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1417 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1418 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1421 /// IsTailCallConvention - Return true if the calling convention is one that
1422 /// supports tail call optimization.
1423 static bool IsTailCallConvention(CallingConv::ID CC) {
1424 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1427 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1428 /// a tailcall target by changing its ABI.
1429 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1430 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1434 X86TargetLowering::LowerMemArgument(SDValue Chain,
1435 CallingConv::ID CallConv,
1436 const SmallVectorImpl<ISD::InputArg> &Ins,
1437 DebugLoc dl, SelectionDAG &DAG,
1438 const CCValAssign &VA,
1439 MachineFrameInfo *MFI,
1441 // Create the nodes corresponding to a load from this parameter slot.
1442 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1443 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1444 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1447 // If value is passed by pointer we have address passed instead of the value
1449 if (VA.getLocInfo() == CCValAssign::Indirect)
1450 ValVT = VA.getLocVT();
1452 ValVT = VA.getValVT();
1454 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1455 // changed with more analysis.
1456 // In case of tail call optimization mark all arguments mutable. Since they
1457 // could be overwritten by lowering of arguments in case of a tail call.
1458 if (Flags.isByVal()) {
1459 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1460 VA.getLocMemOffset(), isImmutable, false);
1461 return DAG.getFrameIndex(FI, getPointerTy());
1463 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1464 VA.getLocMemOffset(), isImmutable, false);
1465 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1466 return DAG.getLoad(ValVT, dl, Chain, FIN,
1467 PseudoSourceValue::getFixedStack(FI), 0,
1473 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1474 CallingConv::ID CallConv,
1476 const SmallVectorImpl<ISD::InputArg> &Ins,
1479 SmallVectorImpl<SDValue> &InVals) {
1481 MachineFunction &MF = DAG.getMachineFunction();
1482 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1484 const Function* Fn = MF.getFunction();
1485 if (Fn->hasExternalLinkage() &&
1486 Subtarget->isTargetCygMing() &&
1487 Fn->getName() == "main")
1488 FuncInfo->setForceFramePointer(true);
1490 MachineFrameInfo *MFI = MF.getFrameInfo();
1491 bool Is64Bit = Subtarget->is64Bit();
1492 bool IsWin64 = Subtarget->isTargetWin64();
1494 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1495 "Var args not supported with calling convention fastcc or ghc");
1497 // Assign locations to all of the incoming arguments.
1498 SmallVector<CCValAssign, 16> ArgLocs;
1499 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1500 ArgLocs, *DAG.getContext());
1501 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1503 unsigned LastVal = ~0U;
1505 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1506 CCValAssign &VA = ArgLocs[i];
1507 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1509 assert(VA.getValNo() != LastVal &&
1510 "Don't support value assigned to multiple locs yet");
1511 LastVal = VA.getValNo();
1513 if (VA.isRegLoc()) {
1514 EVT RegVT = VA.getLocVT();
1515 TargetRegisterClass *RC = NULL;
1516 if (RegVT == MVT::i32)
1517 RC = X86::GR32RegisterClass;
1518 else if (Is64Bit && RegVT == MVT::i64)
1519 RC = X86::GR64RegisterClass;
1520 else if (RegVT == MVT::f32)
1521 RC = X86::FR32RegisterClass;
1522 else if (RegVT == MVT::f64)
1523 RC = X86::FR64RegisterClass;
1524 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1525 RC = X86::VR128RegisterClass;
1526 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1527 RC = X86::VR64RegisterClass;
1529 llvm_unreachable("Unknown argument type!");
1531 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1532 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1534 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1535 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1537 if (VA.getLocInfo() == CCValAssign::SExt)
1538 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1539 DAG.getValueType(VA.getValVT()));
1540 else if (VA.getLocInfo() == CCValAssign::ZExt)
1541 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1542 DAG.getValueType(VA.getValVT()));
1543 else if (VA.getLocInfo() == CCValAssign::BCvt)
1544 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1546 if (VA.isExtInLoc()) {
1547 // Handle MMX values passed in XMM regs.
1548 if (RegVT.isVector()) {
1549 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1550 ArgValue, DAG.getConstant(0, MVT::i64));
1551 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1553 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1556 assert(VA.isMemLoc());
1557 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1560 // If value is passed via pointer - do a load.
1561 if (VA.getLocInfo() == CCValAssign::Indirect)
1562 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1565 InVals.push_back(ArgValue);
1568 // The x86-64 ABI for returning structs by value requires that we copy
1569 // the sret argument into %rax for the return. Save the argument into
1570 // a virtual register so that we can access it from the return points.
1571 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1572 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1573 unsigned Reg = FuncInfo->getSRetReturnReg();
1575 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1576 FuncInfo->setSRetReturnReg(Reg);
1578 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1579 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1582 unsigned StackSize = CCInfo.getNextStackOffset();
1583 // Align stack specially for tail calls.
1584 if (FuncIsMadeTailCallSafe(CallConv))
1585 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1587 // If the function takes variable number of arguments, make a frame index for
1588 // the start of the first vararg value... for expansion of llvm.va_start.
1590 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1591 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1594 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1596 // FIXME: We should really autogenerate these arrays
1597 static const unsigned GPR64ArgRegsWin64[] = {
1598 X86::RCX, X86::RDX, X86::R8, X86::R9
1600 static const unsigned XMMArgRegsWin64[] = {
1601 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1603 static const unsigned GPR64ArgRegs64Bit[] = {
1604 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1606 static const unsigned XMMArgRegs64Bit[] = {
1607 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1608 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1610 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1613 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1614 GPR64ArgRegs = GPR64ArgRegsWin64;
1615 XMMArgRegs = XMMArgRegsWin64;
1617 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1618 GPR64ArgRegs = GPR64ArgRegs64Bit;
1619 XMMArgRegs = XMMArgRegs64Bit;
1621 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1623 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1626 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1627 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1628 "SSE register cannot be used when SSE is disabled!");
1629 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1630 "SSE register cannot be used when SSE is disabled!");
1631 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1632 // Kernel mode asks for SSE to be disabled, so don't push them
1634 TotalNumXMMRegs = 0;
1636 // For X86-64, if there are vararg parameters that are passed via
1637 // registers, then we must store them to their spots on the stack so they
1638 // may be loaded by deferencing the result of va_next.
1639 VarArgsGPOffset = NumIntRegs * 8;
1640 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1641 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1642 TotalNumXMMRegs * 16, 16,
1645 // Store the integer parameter registers.
1646 SmallVector<SDValue, 8> MemOps;
1647 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1648 unsigned Offset = VarArgsGPOffset;
1649 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1650 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1651 DAG.getIntPtrConstant(Offset));
1652 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1653 X86::GR64RegisterClass);
1654 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1656 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1657 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1658 Offset, false, false, 0);
1659 MemOps.push_back(Store);
1663 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1664 // Now store the XMM (fp + vector) parameter registers.
1665 SmallVector<SDValue, 11> SaveXMMOps;
1666 SaveXMMOps.push_back(Chain);
1668 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1669 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1670 SaveXMMOps.push_back(ALVal);
1672 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1673 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1675 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1676 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1677 X86::VR128RegisterClass);
1678 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1679 SaveXMMOps.push_back(Val);
1681 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1683 &SaveXMMOps[0], SaveXMMOps.size()));
1686 if (!MemOps.empty())
1687 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1688 &MemOps[0], MemOps.size());
1692 // Some CCs need callee pop.
1693 if (IsCalleePop(isVarArg, CallConv)) {
1694 BytesToPopOnReturn = StackSize; // Callee pops everything.
1696 BytesToPopOnReturn = 0; // Callee pops nothing.
1697 // If this is an sret function, the return should pop the hidden pointer.
1698 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1699 BytesToPopOnReturn = 4;
1703 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1704 if (CallConv == CallingConv::X86_FastCall)
1705 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1708 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1714 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1715 SDValue StackPtr, SDValue Arg,
1716 DebugLoc dl, SelectionDAG &DAG,
1717 const CCValAssign &VA,
1718 ISD::ArgFlagsTy Flags) {
1719 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1720 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1721 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1722 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1723 if (Flags.isByVal()) {
1724 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1726 return DAG.getStore(Chain, dl, Arg, PtrOff,
1727 PseudoSourceValue::getStack(), LocMemOffset,
1731 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1732 /// optimization is performed and it is required.
1734 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1735 SDValue &OutRetAddr, SDValue Chain,
1736 bool IsTailCall, bool Is64Bit,
1737 int FPDiff, DebugLoc dl) {
1738 // Adjust the Return address stack slot.
1739 EVT VT = getPointerTy();
1740 OutRetAddr = getReturnAddressFrameIndex(DAG);
1742 // Load the "old" Return address.
1743 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1744 return SDValue(OutRetAddr.getNode(), 1);
1747 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1748 /// optimization is performed and it is required (FPDiff!=0).
1750 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1751 SDValue Chain, SDValue RetAddrFrIdx,
1752 bool Is64Bit, int FPDiff, DebugLoc dl) {
1753 // Store the return address to the appropriate stack slot.
1754 if (!FPDiff) return Chain;
1755 // Calculate the new stack slot for the return address.
1756 int SlotSize = Is64Bit ? 8 : 4;
1757 int NewReturnAddrFI =
1758 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false, false);
1759 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1760 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1761 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1762 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1768 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1769 CallingConv::ID CallConv, bool isVarArg,
1771 const SmallVectorImpl<ISD::OutputArg> &Outs,
1772 const SmallVectorImpl<ISD::InputArg> &Ins,
1773 DebugLoc dl, SelectionDAG &DAG,
1774 SmallVectorImpl<SDValue> &InVals) {
1775 MachineFunction &MF = DAG.getMachineFunction();
1776 bool Is64Bit = Subtarget->is64Bit();
1777 bool IsStructRet = CallIsStructReturn(Outs);
1778 bool IsSibcall = false;
1781 // Check if it's really possible to do a tail call.
1782 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
1785 // Sibcalls are automatically detected tailcalls which do not require
1787 if (!GuaranteedTailCallOpt && isTailCall)
1794 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1795 "Var args not supported with calling convention fastcc or ghc");
1797 // Analyze operands of the call, assigning locations to each operand.
1798 SmallVector<CCValAssign, 16> ArgLocs;
1799 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1800 ArgLocs, *DAG.getContext());
1801 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1803 // Get a count of how many bytes are to be pushed on the stack.
1804 unsigned NumBytes = CCInfo.getNextStackOffset();
1806 // This is a sibcall. The memory operands are available in caller's
1807 // own caller's stack.
1809 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1810 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1813 if (isTailCall && !IsSibcall) {
1814 // Lower arguments at fp - stackoffset + fpdiff.
1815 unsigned NumBytesCallerPushed =
1816 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1817 FPDiff = NumBytesCallerPushed - NumBytes;
1819 // Set the delta of movement of the returnaddr stackslot.
1820 // But only set if delta is greater than previous delta.
1821 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1822 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1826 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1828 SDValue RetAddrFrIdx;
1829 // Load return adress for tail calls.
1830 if (isTailCall && FPDiff)
1831 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1832 Is64Bit, FPDiff, dl);
1834 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1835 SmallVector<SDValue, 8> MemOpChains;
1838 // Walk the register/memloc assignments, inserting copies/loads. In the case
1839 // of tail call optimization arguments are handle later.
1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1841 CCValAssign &VA = ArgLocs[i];
1842 EVT RegVT = VA.getLocVT();
1843 SDValue Arg = Outs[i].Val;
1844 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1845 bool isByVal = Flags.isByVal();
1847 // Promote the value if needed.
1848 switch (VA.getLocInfo()) {
1849 default: llvm_unreachable("Unknown loc info!");
1850 case CCValAssign::Full: break;
1851 case CCValAssign::SExt:
1852 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1854 case CCValAssign::ZExt:
1855 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1857 case CCValAssign::AExt:
1858 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1859 // Special case: passing MMX values in XMM registers.
1860 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1861 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1862 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1864 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1866 case CCValAssign::BCvt:
1867 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1869 case CCValAssign::Indirect: {
1870 // Store the argument.
1871 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1872 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1873 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1874 PseudoSourceValue::getFixedStack(FI), 0,
1881 if (VA.isRegLoc()) {
1882 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1883 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1884 assert(VA.isMemLoc());
1885 if (StackPtr.getNode() == 0)
1886 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1887 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1888 dl, DAG, VA, Flags));
1892 if (!MemOpChains.empty())
1893 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1894 &MemOpChains[0], MemOpChains.size());
1896 // Build a sequence of copy-to-reg nodes chained together with token chain
1897 // and flag operands which copy the outgoing args into registers.
1899 // Tail call byval lowering might overwrite argument registers so in case of
1900 // tail call optimization the copies to registers are lowered later.
1902 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1903 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1904 RegsToPass[i].second, InFlag);
1905 InFlag = Chain.getValue(1);
1908 if (Subtarget->isPICStyleGOT()) {
1909 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1912 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1913 DAG.getNode(X86ISD::GlobalBaseReg,
1914 DebugLoc::getUnknownLoc(),
1917 InFlag = Chain.getValue(1);
1919 // If we are tail calling and generating PIC/GOT style code load the
1920 // address of the callee into ECX. The value in ecx is used as target of
1921 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1922 // for tail calls on PIC/GOT architectures. Normally we would just put the
1923 // address of GOT into ebx and then call target@PLT. But for tail calls
1924 // ebx would be restored (since ebx is callee saved) before jumping to the
1927 // Note: The actual moving to ECX is done further down.
1928 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1929 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1930 !G->getGlobal()->hasProtectedVisibility())
1931 Callee = LowerGlobalAddress(Callee, DAG);
1932 else if (isa<ExternalSymbolSDNode>(Callee))
1933 Callee = LowerExternalSymbol(Callee, DAG);
1937 if (Is64Bit && isVarArg) {
1938 // From AMD64 ABI document:
1939 // For calls that may call functions that use varargs or stdargs
1940 // (prototype-less calls or calls to functions containing ellipsis (...) in
1941 // the declaration) %al is used as hidden argument to specify the number
1942 // of SSE registers used. The contents of %al do not need to match exactly
1943 // the number of registers, but must be an ubound on the number of SSE
1944 // registers used and is in the range 0 - 8 inclusive.
1946 // FIXME: Verify this on Win64
1947 // Count the number of XMM registers allocated.
1948 static const unsigned XMMArgRegs[] = {
1949 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1950 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1952 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1953 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1954 && "SSE registers cannot be used when SSE is disabled");
1956 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1957 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1958 InFlag = Chain.getValue(1);
1962 // For tail calls lower the arguments to the 'real' stack slot.
1964 // Force all the incoming stack arguments to be loaded from the stack
1965 // before any new outgoing arguments are stored to the stack, because the
1966 // outgoing stack slots may alias the incoming argument stack slots, and
1967 // the alias isn't otherwise explicit. This is slightly more conservative
1968 // than necessary, because it means that each store effectively depends
1969 // on every argument instead of just those arguments it would clobber.
1970 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1972 SmallVector<SDValue, 8> MemOpChains2;
1975 // Do not flag preceeding copytoreg stuff together with the following stuff.
1977 if (GuaranteedTailCallOpt) {
1978 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1979 CCValAssign &VA = ArgLocs[i];
1982 assert(VA.isMemLoc());
1983 SDValue Arg = Outs[i].Val;
1984 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1985 // Create frame index.
1986 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1987 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1988 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1989 FIN = DAG.getFrameIndex(FI, getPointerTy());
1991 if (Flags.isByVal()) {
1992 // Copy relative to framepointer.
1993 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1994 if (StackPtr.getNode() == 0)
1995 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1997 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1999 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2003 // Store relative to framepointer.
2004 MemOpChains2.push_back(
2005 DAG.getStore(ArgChain, dl, Arg, FIN,
2006 PseudoSourceValue::getFixedStack(FI), 0,
2012 if (!MemOpChains2.empty())
2013 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2014 &MemOpChains2[0], MemOpChains2.size());
2016 // Copy arguments to their registers.
2017 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2018 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2019 RegsToPass[i].second, InFlag);
2020 InFlag = Chain.getValue(1);
2024 // Store the return address to the appropriate stack slot.
2025 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2029 bool WasGlobalOrExternal = false;
2030 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2031 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2032 // In the 64-bit large code model, we have to make all calls
2033 // through a register, since the call instruction's 32-bit
2034 // pc-relative offset may not be large enough to hold the whole
2036 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2037 WasGlobalOrExternal = true;
2038 // If the callee is a GlobalAddress node (quite common, every direct call
2039 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2042 // We should use extra load for direct calls to dllimported functions in
2044 GlobalValue *GV = G->getGlobal();
2045 if (!GV->hasDLLImportLinkage()) {
2046 unsigned char OpFlags = 0;
2048 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2049 // external symbols most go through the PLT in PIC mode. If the symbol
2050 // has hidden or protected visibility, or if it is static or local, then
2051 // we don't need to use the PLT - we can directly call it.
2052 if (Subtarget->isTargetELF() &&
2053 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2054 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2055 OpFlags = X86II::MO_PLT;
2056 } else if (Subtarget->isPICStyleStubAny() &&
2057 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2058 Subtarget->getDarwinVers() < 9) {
2059 // PC-relative references to external symbols should go through $stub,
2060 // unless we're building with the leopard linker or later, which
2061 // automatically synthesizes these stubs.
2062 OpFlags = X86II::MO_DARWIN_STUB;
2065 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
2066 G->getOffset(), OpFlags);
2068 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2069 WasGlobalOrExternal = true;
2070 unsigned char OpFlags = 0;
2072 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2073 // symbols should go through the PLT.
2074 if (Subtarget->isTargetELF() &&
2075 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2076 OpFlags = X86II::MO_PLT;
2077 } else if (Subtarget->isPICStyleStubAny() &&
2078 Subtarget->getDarwinVers() < 9) {
2079 // PC-relative references to external symbols should go through $stub,
2080 // unless we're building with the leopard linker or later, which
2081 // automatically synthesizes these stubs.
2082 OpFlags = X86II::MO_DARWIN_STUB;
2085 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2089 if (isTailCall && !WasGlobalOrExternal) {
2090 // Force the address into a (call preserved) caller-saved register since
2091 // tailcall must happen after callee-saved registers are poped.
2092 // FIXME: Give it a special register class that contains caller-saved
2093 // register instead?
2094 unsigned TCReg = Is64Bit ? X86::R11 : X86::EAX;
2095 Chain = DAG.getCopyToReg(Chain, dl,
2096 DAG.getRegister(TCReg, getPointerTy()),
2098 Callee = DAG.getRegister(TCReg, getPointerTy());
2101 // Returns a chain & a flag for retval copy to use.
2102 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2103 SmallVector<SDValue, 8> Ops;
2105 if (!IsSibcall && isTailCall) {
2106 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2107 DAG.getIntPtrConstant(0, true), InFlag);
2108 InFlag = Chain.getValue(1);
2111 Ops.push_back(Chain);
2112 Ops.push_back(Callee);
2115 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2117 // Add argument registers to the end of the list so that they are known live
2119 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2120 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2121 RegsToPass[i].second.getValueType()));
2123 // Add an implicit use GOT pointer in EBX.
2124 if (!isTailCall && Subtarget->isPICStyleGOT())
2125 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2127 // Add an implicit use of AL for x86 vararg functions.
2128 if (Is64Bit && isVarArg)
2129 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2131 if (InFlag.getNode())
2132 Ops.push_back(InFlag);
2135 // If this is the first return lowered for this function, add the regs
2136 // to the liveout set for the function.
2137 if (MF.getRegInfo().liveout_empty()) {
2138 SmallVector<CCValAssign, 16> RVLocs;
2139 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2141 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2142 for (unsigned i = 0; i != RVLocs.size(); ++i)
2143 if (RVLocs[i].isRegLoc())
2144 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2147 assert(((Callee.getOpcode() == ISD::Register &&
2148 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2149 cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) ||
2150 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2151 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2152 "Expecting a global address, external symbol, or scratch register");
2154 return DAG.getNode(X86ISD::TC_RETURN, dl,
2155 NodeTys, &Ops[0], Ops.size());
2158 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2159 InFlag = Chain.getValue(1);
2161 // Create the CALLSEQ_END node.
2162 unsigned NumBytesForCalleeToPush;
2163 if (IsCalleePop(isVarArg, CallConv))
2164 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2165 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2166 // If this is a call to a struct-return function, the callee
2167 // pops the hidden struct pointer, so we have to push it back.
2168 // This is common for Darwin/X86, Linux & Mingw32 targets.
2169 NumBytesForCalleeToPush = 4;
2171 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2173 // Returns a flag for retval copy to use.
2175 Chain = DAG.getCALLSEQ_END(Chain,
2176 DAG.getIntPtrConstant(NumBytes, true),
2177 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2180 InFlag = Chain.getValue(1);
2183 // Handle result values, copying them out of physregs into vregs that we
2185 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2186 Ins, dl, DAG, InVals);
2190 //===----------------------------------------------------------------------===//
2191 // Fast Calling Convention (tail call) implementation
2192 //===----------------------------------------------------------------------===//
2194 // Like std call, callee cleans arguments, convention except that ECX is
2195 // reserved for storing the tail called function address. Only 2 registers are
2196 // free for argument passing (inreg). Tail call optimization is performed
2198 // * tailcallopt is enabled
2199 // * caller/callee are fastcc
2200 // On X86_64 architecture with GOT-style position independent code only local
2201 // (within module) calls are supported at the moment.
2202 // To keep the stack aligned according to platform abi the function
2203 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2204 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2205 // If a tail called function callee has more arguments than the caller the
2206 // caller needs to make sure that there is room to move the RETADDR to. This is
2207 // achieved by reserving an area the size of the argument delta right after the
2208 // original REtADDR, but before the saved framepointer or the spilled registers
2209 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2221 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2222 /// for a 16 byte align requirement.
2223 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2224 SelectionDAG& DAG) {
2225 MachineFunction &MF = DAG.getMachineFunction();
2226 const TargetMachine &TM = MF.getTarget();
2227 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2228 unsigned StackAlignment = TFI.getStackAlignment();
2229 uint64_t AlignMask = StackAlignment - 1;
2230 int64_t Offset = StackSize;
2231 uint64_t SlotSize = TD->getPointerSize();
2232 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2233 // Number smaller than 12 so just add the difference.
2234 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2236 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2237 Offset = ((~AlignMask) & Offset) + StackAlignment +
2238 (StackAlignment-SlotSize);
2243 /// MatchingStackOffset - Return true if the given stack call argument is
2244 /// already available in the same position (relatively) of the caller's
2245 /// incoming argument stack.
2247 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2248 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2249 const X86InstrInfo *TII) {
2250 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2252 if (Arg.getOpcode() == ISD::CopyFromReg) {
2253 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2254 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2256 MachineInstr *Def = MRI->getVRegDef(VR);
2259 if (!Flags.isByVal()) {
2260 if (!TII->isLoadFromStackSlot(Def, FI))
2263 unsigned Opcode = Def->getOpcode();
2264 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2265 Def->getOperand(1).isFI()) {
2266 FI = Def->getOperand(1).getIndex();
2267 Bytes = Flags.getByValSize();
2271 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2272 if (Flags.isByVal())
2273 // ByVal argument is passed in as a pointer but it's now being
2274 // dereferenced. e.g.
2275 // define @foo(%struct.X* %A) {
2276 // tail call @bar(%struct.X* byval %A)
2279 SDValue Ptr = Ld->getBasePtr();
2280 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2283 FI = FINode->getIndex();
2287 assert(FI != INT_MAX);
2288 if (!MFI->isFixedObjectIndex(FI))
2290 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2293 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2294 /// for tail call optimization. Targets which want to do tail call
2295 /// optimization should implement this function.
2297 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2298 CallingConv::ID CalleeCC,
2300 const SmallVectorImpl<ISD::OutputArg> &Outs,
2301 const SmallVectorImpl<ISD::InputArg> &Ins,
2302 SelectionDAG& DAG) const {
2303 if (!IsTailCallConvention(CalleeCC) &&
2304 CalleeCC != CallingConv::C)
2307 // If -tailcallopt is specified, make fastcc functions tail-callable.
2308 const Function *CallerF = DAG.getMachineFunction().getFunction();
2309 if (GuaranteedTailCallOpt) {
2310 if (IsTailCallConvention(CalleeCC) &&
2311 CallerF->getCallingConv() == CalleeCC)
2316 // Look for obvious safe cases to perform tail call optimization that does not
2317 // requite ABI changes. This is what gcc calls sibcall.
2319 // Do not tail call optimize vararg calls for now.
2323 // If the callee takes no arguments then go on to check the results of the
2325 if (!Outs.empty()) {
2326 // Check if stack adjustment is needed. For now, do not do this if any
2327 // argument is passed on the stack.
2328 SmallVector<CCValAssign, 16> ArgLocs;
2329 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2330 ArgLocs, *DAG.getContext());
2331 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2332 if (CCInfo.getNextStackOffset()) {
2333 MachineFunction &MF = DAG.getMachineFunction();
2334 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2336 if (Subtarget->isTargetWin64())
2337 // Win64 ABI has additional complications.
2340 // Check if the arguments are already laid out in the right way as
2341 // the caller's fixed stack objects.
2342 MachineFrameInfo *MFI = MF.getFrameInfo();
2343 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2344 const X86InstrInfo *TII =
2345 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2346 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2347 CCValAssign &VA = ArgLocs[i];
2348 EVT RegVT = VA.getLocVT();
2349 SDValue Arg = Outs[i].Val;
2350 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2351 if (VA.getLocInfo() == CCValAssign::Indirect)
2353 if (!VA.isRegLoc()) {
2354 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2366 X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo,
2368 DenseMap<const Value *, unsigned> &vm,
2369 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2370 DenseMap<const AllocaInst *, int> &am
2372 , SmallSet<Instruction*, 8> &cil
2375 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2383 //===----------------------------------------------------------------------===//
2384 // Other Lowering Hooks
2385 //===----------------------------------------------------------------------===//
2388 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 int ReturnAddrIndex = FuncInfo->getRAIndex();
2393 if (ReturnAddrIndex == 0) {
2394 // Set up a frame object for the return address.
2395 uint64_t SlotSize = TD->getPointerSize();
2396 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2398 FuncInfo->setRAIndex(ReturnAddrIndex);
2401 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2405 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2406 bool hasSymbolicDisplacement) {
2407 // Offset should fit into 32 bit immediate field.
2408 if (!isInt32(Offset))
2411 // If we don't have a symbolic displacement - we don't have any extra
2413 if (!hasSymbolicDisplacement)
2416 // FIXME: Some tweaks might be needed for medium code model.
2417 if (M != CodeModel::Small && M != CodeModel::Kernel)
2420 // For small code model we assume that latest object is 16MB before end of 31
2421 // bits boundary. We may also accept pretty large negative constants knowing
2422 // that all objects are in the positive half of address space.
2423 if (M == CodeModel::Small && Offset < 16*1024*1024)
2426 // For kernel code model we know that all object resist in the negative half
2427 // of 32bits address space. We may not accept negative offsets, since they may
2428 // be just off and we may accept pretty large positive ones.
2429 if (M == CodeModel::Kernel && Offset > 0)
2435 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2436 /// specific condition code, returning the condition code and the LHS/RHS of the
2437 /// comparison to make.
2438 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2439 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2441 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2442 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2443 // X > -1 -> X == 0, jump !sign.
2444 RHS = DAG.getConstant(0, RHS.getValueType());
2445 return X86::COND_NS;
2446 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2447 // X < 0 -> X == 0, jump on sign.
2449 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2451 RHS = DAG.getConstant(0, RHS.getValueType());
2452 return X86::COND_LE;
2456 switch (SetCCOpcode) {
2457 default: llvm_unreachable("Invalid integer condition!");
2458 case ISD::SETEQ: return X86::COND_E;
2459 case ISD::SETGT: return X86::COND_G;
2460 case ISD::SETGE: return X86::COND_GE;
2461 case ISD::SETLT: return X86::COND_L;
2462 case ISD::SETLE: return X86::COND_LE;
2463 case ISD::SETNE: return X86::COND_NE;
2464 case ISD::SETULT: return X86::COND_B;
2465 case ISD::SETUGT: return X86::COND_A;
2466 case ISD::SETULE: return X86::COND_BE;
2467 case ISD::SETUGE: return X86::COND_AE;
2471 // First determine if it is required or is profitable to flip the operands.
2473 // If LHS is a foldable load, but RHS is not, flip the condition.
2474 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2475 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2476 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2477 std::swap(LHS, RHS);
2480 switch (SetCCOpcode) {
2486 std::swap(LHS, RHS);
2490 // On a floating point condition, the flags are set as follows:
2492 // 0 | 0 | 0 | X > Y
2493 // 0 | 0 | 1 | X < Y
2494 // 1 | 0 | 0 | X == Y
2495 // 1 | 1 | 1 | unordered
2496 switch (SetCCOpcode) {
2497 default: llvm_unreachable("Condcode should be pre-legalized away");
2499 case ISD::SETEQ: return X86::COND_E;
2500 case ISD::SETOLT: // flipped
2502 case ISD::SETGT: return X86::COND_A;
2503 case ISD::SETOLE: // flipped
2505 case ISD::SETGE: return X86::COND_AE;
2506 case ISD::SETUGT: // flipped
2508 case ISD::SETLT: return X86::COND_B;
2509 case ISD::SETUGE: // flipped
2511 case ISD::SETLE: return X86::COND_BE;
2513 case ISD::SETNE: return X86::COND_NE;
2514 case ISD::SETUO: return X86::COND_P;
2515 case ISD::SETO: return X86::COND_NP;
2517 case ISD::SETUNE: return X86::COND_INVALID;
2521 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2522 /// code. Current x86 isa includes the following FP cmov instructions:
2523 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2524 static bool hasFPCMov(unsigned X86CC) {
2540 /// isFPImmLegal - Returns true if the target can instruction select the
2541 /// specified FP immediate natively. If false, the legalizer will
2542 /// materialize the FP immediate as a load from a constant pool.
2543 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2544 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2545 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2551 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2552 /// the specified range (L, H].
2553 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2554 return (Val < 0) || (Val >= Low && Val < Hi);
2557 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2558 /// specified value.
2559 static bool isUndefOrEqual(int Val, int CmpVal) {
2560 if (Val < 0 || Val == CmpVal)
2565 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2566 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2567 /// the second operand.
2568 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2569 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2570 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2571 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2572 return (Mask[0] < 2 && Mask[1] < 2);
2576 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2577 SmallVector<int, 8> M;
2579 return ::isPSHUFDMask(M, N->getValueType(0));
2582 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2583 /// is suitable for input to PSHUFHW.
2584 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2585 if (VT != MVT::v8i16)
2588 // Lower quadword copied in order or undef.
2589 for (int i = 0; i != 4; ++i)
2590 if (Mask[i] >= 0 && Mask[i] != i)
2593 // Upper quadword shuffled.
2594 for (int i = 4; i != 8; ++i)
2595 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2601 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2602 SmallVector<int, 8> M;
2604 return ::isPSHUFHWMask(M, N->getValueType(0));
2607 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2608 /// is suitable for input to PSHUFLW.
2609 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2610 if (VT != MVT::v8i16)
2613 // Upper quadword copied in order.
2614 for (int i = 4; i != 8; ++i)
2615 if (Mask[i] >= 0 && Mask[i] != i)
2618 // Lower quadword shuffled.
2619 for (int i = 0; i != 4; ++i)
2626 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2627 SmallVector<int, 8> M;
2629 return ::isPSHUFLWMask(M, N->getValueType(0));
2632 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2633 /// is suitable for input to PALIGNR.
2634 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2636 int i, e = VT.getVectorNumElements();
2638 // Do not handle v2i64 / v2f64 shuffles with palignr.
2639 if (e < 4 || !hasSSSE3)
2642 for (i = 0; i != e; ++i)
2646 // All undef, not a palignr.
2650 // Determine if it's ok to perform a palignr with only the LHS, since we
2651 // don't have access to the actual shuffle elements to see if RHS is undef.
2652 bool Unary = Mask[i] < (int)e;
2653 bool NeedsUnary = false;
2655 int s = Mask[i] - i;
2657 // Check the rest of the elements to see if they are consecutive.
2658 for (++i; i != e; ++i) {
2663 Unary = Unary && (m < (int)e);
2664 NeedsUnary = NeedsUnary || (m < s);
2666 if (NeedsUnary && !Unary)
2668 if (Unary && m != ((s+i) & (e-1)))
2670 if (!Unary && m != (s+i))
2676 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2677 SmallVector<int, 8> M;
2679 return ::isPALIGNRMask(M, N->getValueType(0), true);
2682 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2683 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2684 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2685 int NumElems = VT.getVectorNumElements();
2686 if (NumElems != 2 && NumElems != 4)
2689 int Half = NumElems / 2;
2690 for (int i = 0; i < Half; ++i)
2691 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2693 for (int i = Half; i < NumElems; ++i)
2694 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2700 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2701 SmallVector<int, 8> M;
2703 return ::isSHUFPMask(M, N->getValueType(0));
2706 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2707 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2708 /// half elements to come from vector 1 (which would equal the dest.) and
2709 /// the upper half to come from vector 2.
2710 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2711 int NumElems = VT.getVectorNumElements();
2713 if (NumElems != 2 && NumElems != 4)
2716 int Half = NumElems / 2;
2717 for (int i = 0; i < Half; ++i)
2718 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2720 for (int i = Half; i < NumElems; ++i)
2721 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2726 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2727 SmallVector<int, 8> M;
2729 return isCommutedSHUFPMask(M, N->getValueType(0));
2732 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2733 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2734 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2735 if (N->getValueType(0).getVectorNumElements() != 4)
2738 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2739 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2740 isUndefOrEqual(N->getMaskElt(1), 7) &&
2741 isUndefOrEqual(N->getMaskElt(2), 2) &&
2742 isUndefOrEqual(N->getMaskElt(3), 3);
2745 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2746 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2748 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2749 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2754 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2755 isUndefOrEqual(N->getMaskElt(1), 3) &&
2756 isUndefOrEqual(N->getMaskElt(2), 2) &&
2757 isUndefOrEqual(N->getMaskElt(3), 3);
2760 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2761 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2762 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2763 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2765 if (NumElems != 2 && NumElems != 4)
2768 for (unsigned i = 0; i < NumElems/2; ++i)
2769 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2772 for (unsigned i = NumElems/2; i < NumElems; ++i)
2773 if (!isUndefOrEqual(N->getMaskElt(i), i))
2779 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2780 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2781 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2782 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2784 if (NumElems != 2 && NumElems != 4)
2787 for (unsigned i = 0; i < NumElems/2; ++i)
2788 if (!isUndefOrEqual(N->getMaskElt(i), i))
2791 for (unsigned i = 0; i < NumElems/2; ++i)
2792 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2798 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2799 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2800 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2801 bool V2IsSplat = false) {
2802 int NumElts = VT.getVectorNumElements();
2803 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2806 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2808 int BitI1 = Mask[i+1];
2809 if (!isUndefOrEqual(BitI, j))
2812 if (!isUndefOrEqual(BitI1, NumElts))
2815 if (!isUndefOrEqual(BitI1, j + NumElts))
2822 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2823 SmallVector<int, 8> M;
2825 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2828 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2829 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2830 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2831 bool V2IsSplat = false) {
2832 int NumElts = VT.getVectorNumElements();
2833 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2836 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2838 int BitI1 = Mask[i+1];
2839 if (!isUndefOrEqual(BitI, j + NumElts/2))
2842 if (isUndefOrEqual(BitI1, NumElts))
2845 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2852 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2853 SmallVector<int, 8> M;
2855 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2858 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2859 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2861 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2862 int NumElems = VT.getVectorNumElements();
2863 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2866 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2868 int BitI1 = Mask[i+1];
2869 if (!isUndefOrEqual(BitI, j))
2871 if (!isUndefOrEqual(BitI1, j))
2877 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2878 SmallVector<int, 8> M;
2880 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2883 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2884 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2886 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2887 int NumElems = VT.getVectorNumElements();
2888 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2891 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2893 int BitI1 = Mask[i+1];
2894 if (!isUndefOrEqual(BitI, j))
2896 if (!isUndefOrEqual(BitI1, j))
2902 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2903 SmallVector<int, 8> M;
2905 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2908 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2909 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2910 /// MOVSD, and MOVD, i.e. setting the lowest element.
2911 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2912 if (VT.getVectorElementType().getSizeInBits() < 32)
2915 int NumElts = VT.getVectorNumElements();
2917 if (!isUndefOrEqual(Mask[0], NumElts))
2920 for (int i = 1; i < NumElts; ++i)
2921 if (!isUndefOrEqual(Mask[i], i))
2927 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2928 SmallVector<int, 8> M;
2930 return ::isMOVLMask(M, N->getValueType(0));
2933 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2934 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2935 /// element of vector 2 and the other elements to come from vector 1 in order.
2936 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2937 bool V2IsSplat = false, bool V2IsUndef = false) {
2938 int NumOps = VT.getVectorNumElements();
2939 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2942 if (!isUndefOrEqual(Mask[0], 0))
2945 for (int i = 1; i < NumOps; ++i)
2946 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2947 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2948 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2954 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2955 bool V2IsUndef = false) {
2956 SmallVector<int, 8> M;
2958 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2961 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2962 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2963 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2964 if (N->getValueType(0).getVectorNumElements() != 4)
2967 // Expect 1, 1, 3, 3
2968 for (unsigned i = 0; i < 2; ++i) {
2969 int Elt = N->getMaskElt(i);
2970 if (Elt >= 0 && Elt != 1)
2975 for (unsigned i = 2; i < 4; ++i) {
2976 int Elt = N->getMaskElt(i);
2977 if (Elt >= 0 && Elt != 3)
2982 // Don't use movshdup if it can be done with a shufps.
2983 // FIXME: verify that matching u, u, 3, 3 is what we want.
2987 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2988 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2989 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2990 if (N->getValueType(0).getVectorNumElements() != 4)
2993 // Expect 0, 0, 2, 2
2994 for (unsigned i = 0; i < 2; ++i)
2995 if (N->getMaskElt(i) > 0)
2999 for (unsigned i = 2; i < 4; ++i) {
3000 int Elt = N->getMaskElt(i);
3001 if (Elt >= 0 && Elt != 2)
3006 // Don't use movsldup if it can be done with a shufps.
3010 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3011 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3012 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3013 int e = N->getValueType(0).getVectorNumElements() / 2;
3015 for (int i = 0; i < e; ++i)
3016 if (!isUndefOrEqual(N->getMaskElt(i), i))
3018 for (int i = 0; i < e; ++i)
3019 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3024 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3025 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3026 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3027 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3028 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3030 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3032 for (int i = 0; i < NumOperands; ++i) {
3033 int Val = SVOp->getMaskElt(NumOperands-i-1);
3034 if (Val < 0) Val = 0;
3035 if (Val >= NumOperands) Val -= NumOperands;
3037 if (i != NumOperands - 1)
3043 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3044 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3045 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3048 // 8 nodes, but we only care about the last 4.
3049 for (unsigned i = 7; i >= 4; --i) {
3050 int Val = SVOp->getMaskElt(i);
3059 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3060 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3061 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3064 // 8 nodes, but we only care about the first 4.
3065 for (int i = 3; i >= 0; --i) {
3066 int Val = SVOp->getMaskElt(i);
3075 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3076 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3077 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3079 EVT VVT = N->getValueType(0);
3080 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3084 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3085 Val = SVOp->getMaskElt(i);
3089 return (Val - i) * EltSize;
3092 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3094 bool X86::isZeroNode(SDValue Elt) {
3095 return ((isa<ConstantSDNode>(Elt) &&
3096 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
3097 (isa<ConstantFPSDNode>(Elt) &&
3098 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3101 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3102 /// their permute mask.
3103 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3104 SelectionDAG &DAG) {
3105 EVT VT = SVOp->getValueType(0);
3106 unsigned NumElems = VT.getVectorNumElements();
3107 SmallVector<int, 8> MaskVec;
3109 for (unsigned i = 0; i != NumElems; ++i) {
3110 int idx = SVOp->getMaskElt(i);
3112 MaskVec.push_back(idx);
3113 else if (idx < (int)NumElems)
3114 MaskVec.push_back(idx + NumElems);
3116 MaskVec.push_back(idx - NumElems);
3118 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3119 SVOp->getOperand(0), &MaskVec[0]);
3122 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3123 /// the two vector operands have swapped position.
3124 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3125 unsigned NumElems = VT.getVectorNumElements();
3126 for (unsigned i = 0; i != NumElems; ++i) {
3130 else if (idx < (int)NumElems)
3131 Mask[i] = idx + NumElems;
3133 Mask[i] = idx - NumElems;
3137 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3138 /// match movhlps. The lower half elements should come from upper half of
3139 /// V1 (and in order), and the upper half elements should come from the upper
3140 /// half of V2 (and in order).
3141 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3142 if (Op->getValueType(0).getVectorNumElements() != 4)
3144 for (unsigned i = 0, e = 2; i != e; ++i)
3145 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3147 for (unsigned i = 2; i != 4; ++i)
3148 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3153 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3154 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3156 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3157 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3159 N = N->getOperand(0).getNode();
3160 if (!ISD::isNON_EXTLoad(N))
3163 *LD = cast<LoadSDNode>(N);
3167 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3168 /// match movlp{s|d}. The lower half elements should come from lower half of
3169 /// V1 (and in order), and the upper half elements should come from the upper
3170 /// half of V2 (and in order). And since V1 will become the source of the
3171 /// MOVLP, it must be either a vector load or a scalar load to vector.
3172 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3173 ShuffleVectorSDNode *Op) {
3174 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3176 // Is V2 is a vector load, don't do this transformation. We will try to use
3177 // load folding shufps op.
3178 if (ISD::isNON_EXTLoad(V2))
3181 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3183 if (NumElems != 2 && NumElems != 4)
3185 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3186 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3188 for (unsigned i = NumElems/2; i != NumElems; ++i)
3189 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3194 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3196 static bool isSplatVector(SDNode *N) {
3197 if (N->getOpcode() != ISD::BUILD_VECTOR)
3200 SDValue SplatValue = N->getOperand(0);
3201 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3202 if (N->getOperand(i) != SplatValue)
3207 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3208 /// to an zero vector.
3209 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3210 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3211 SDValue V1 = N->getOperand(0);
3212 SDValue V2 = N->getOperand(1);
3213 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3214 for (unsigned i = 0; i != NumElems; ++i) {
3215 int Idx = N->getMaskElt(i);
3216 if (Idx >= (int)NumElems) {
3217 unsigned Opc = V2.getOpcode();
3218 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3220 if (Opc != ISD::BUILD_VECTOR ||
3221 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3223 } else if (Idx >= 0) {
3224 unsigned Opc = V1.getOpcode();
3225 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3227 if (Opc != ISD::BUILD_VECTOR ||
3228 !X86::isZeroNode(V1.getOperand(Idx)))
3235 /// getZeroVector - Returns a vector of specified type with all zero elements.
3237 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3239 assert(VT.isVector() && "Expected a vector type");
3241 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3242 // type. This ensures they get CSE'd.
3244 if (VT.getSizeInBits() == 64) { // MMX
3245 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3246 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3247 } else if (HasSSE2) { // SSE2
3248 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3249 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3251 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3254 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3257 /// getOnesVector - Returns a vector of specified type with all bits set.
3259 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3260 assert(VT.isVector() && "Expected a vector type");
3262 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3263 // type. This ensures they get CSE'd.
3264 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3266 if (VT.getSizeInBits() == 64) // MMX
3267 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3269 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3270 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3274 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3275 /// that point to V2 points to its first element.
3276 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3277 EVT VT = SVOp->getValueType(0);
3278 unsigned NumElems = VT.getVectorNumElements();
3280 bool Changed = false;
3281 SmallVector<int, 8> MaskVec;
3282 SVOp->getMask(MaskVec);
3284 for (unsigned i = 0; i != NumElems; ++i) {
3285 if (MaskVec[i] > (int)NumElems) {
3286 MaskVec[i] = NumElems;
3291 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3292 SVOp->getOperand(1), &MaskVec[0]);
3293 return SDValue(SVOp, 0);
3296 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3297 /// operation of specified width.
3298 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3300 unsigned NumElems = VT.getVectorNumElements();
3301 SmallVector<int, 8> Mask;
3302 Mask.push_back(NumElems);
3303 for (unsigned i = 1; i != NumElems; ++i)
3305 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3308 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3309 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3311 unsigned NumElems = VT.getVectorNumElements();
3312 SmallVector<int, 8> Mask;
3313 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3315 Mask.push_back(i + NumElems);
3317 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3320 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3321 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3323 unsigned NumElems = VT.getVectorNumElements();
3324 unsigned Half = NumElems/2;
3325 SmallVector<int, 8> Mask;
3326 for (unsigned i = 0; i != Half; ++i) {
3327 Mask.push_back(i + Half);
3328 Mask.push_back(i + NumElems + Half);
3330 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3333 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3334 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3336 if (SV->getValueType(0).getVectorNumElements() <= 4)
3337 return SDValue(SV, 0);
3339 EVT PVT = MVT::v4f32;
3340 EVT VT = SV->getValueType(0);
3341 DebugLoc dl = SV->getDebugLoc();
3342 SDValue V1 = SV->getOperand(0);
3343 int NumElems = VT.getVectorNumElements();
3344 int EltNo = SV->getSplatIndex();
3346 // unpack elements to the correct location
3347 while (NumElems > 4) {
3348 if (EltNo < NumElems/2) {
3349 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3351 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3352 EltNo -= NumElems/2;
3357 // Perform the splat.
3358 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3359 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3360 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3361 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3364 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3365 /// vector of zero or undef vector. This produces a shuffle where the low
3366 /// element of V2 is swizzled into the zero/undef vector, landing at element
3367 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3368 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3369 bool isZero, bool HasSSE2,
3370 SelectionDAG &DAG) {
3371 EVT VT = V2.getValueType();
3373 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3374 unsigned NumElems = VT.getVectorNumElements();
3375 SmallVector<int, 16> MaskVec;
3376 for (unsigned i = 0; i != NumElems; ++i)
3377 // If this is the insertion idx, put the low elt of V2 here.
3378 MaskVec.push_back(i == Idx ? NumElems : i);
3379 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3382 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3383 /// a shuffle that is zero.
3385 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3386 bool Low, SelectionDAG &DAG) {
3387 unsigned NumZeros = 0;
3388 for (int i = 0; i < NumElems; ++i) {
3389 unsigned Index = Low ? i : NumElems-i-1;
3390 int Idx = SVOp->getMaskElt(Index);
3395 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3396 if (Elt.getNode() && X86::isZeroNode(Elt))
3404 /// isVectorShift - Returns true if the shuffle can be implemented as a
3405 /// logical left or right shift of a vector.
3406 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3407 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3408 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3409 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3412 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3415 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3419 bool SeenV1 = false;
3420 bool SeenV2 = false;
3421 for (int i = NumZeros; i < NumElems; ++i) {
3422 int Val = isLeft ? (i - NumZeros) : i;
3423 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3435 if (SeenV1 && SeenV2)
3438 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3444 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3446 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3447 unsigned NumNonZero, unsigned NumZero,
3448 SelectionDAG &DAG, TargetLowering &TLI) {
3452 DebugLoc dl = Op.getDebugLoc();
3455 for (unsigned i = 0; i < 16; ++i) {
3456 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3457 if (ThisIsNonZero && First) {
3459 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3461 V = DAG.getUNDEF(MVT::v8i16);
3466 SDValue ThisElt(0, 0), LastElt(0, 0);
3467 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3468 if (LastIsNonZero) {
3469 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3470 MVT::i16, Op.getOperand(i-1));
3472 if (ThisIsNonZero) {
3473 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3474 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3475 ThisElt, DAG.getConstant(8, MVT::i8));
3477 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3481 if (ThisElt.getNode())
3482 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3483 DAG.getIntPtrConstant(i/2));
3487 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3490 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3492 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3493 unsigned NumNonZero, unsigned NumZero,
3494 SelectionDAG &DAG, TargetLowering &TLI) {
3498 DebugLoc dl = Op.getDebugLoc();
3501 for (unsigned i = 0; i < 8; ++i) {
3502 bool isNonZero = (NonZeros & (1 << i)) != 0;
3506 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3508 V = DAG.getUNDEF(MVT::v8i16);
3511 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3512 MVT::v8i16, V, Op.getOperand(i),
3513 DAG.getIntPtrConstant(i));
3520 /// getVShift - Return a vector logical shift node.
3522 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3523 unsigned NumBits, SelectionDAG &DAG,
3524 const TargetLowering &TLI, DebugLoc dl) {
3525 bool isMMX = VT.getSizeInBits() == 64;
3526 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3527 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3528 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3529 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3530 DAG.getNode(Opc, dl, ShVT, SrcOp,
3531 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3535 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3536 SelectionDAG &DAG) {
3538 // Check if the scalar load can be widened into a vector load. And if
3539 // the address is "base + cst" see if the cst can be "absorbed" into
3540 // the shuffle mask.
3541 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3542 SDValue Ptr = LD->getBasePtr();
3543 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3545 EVT PVT = LD->getValueType(0);
3546 if (PVT != MVT::i32 && PVT != MVT::f32)
3551 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3552 FI = FINode->getIndex();
3554 } else if (Ptr.getOpcode() == ISD::ADD &&
3555 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3556 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3557 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3558 Offset = Ptr.getConstantOperandVal(1);
3559 Ptr = Ptr.getOperand(0);
3564 SDValue Chain = LD->getChain();
3565 // Make sure the stack object alignment is at least 16.
3566 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3567 if (DAG.InferPtrAlignment(Ptr) < 16) {
3568 if (MFI->isFixedObjectIndex(FI)) {
3569 // Can't change the alignment. FIXME: It's possible to compute
3570 // the exact stack offset and reference FI + adjust offset instead.
3571 // If someone *really* cares about this. That's the way to implement it.
3574 MFI->setObjectAlignment(FI, 16);
3578 // (Offset % 16) must be multiple of 4. Then address is then
3579 // Ptr + (Offset & ~15).
3582 if ((Offset % 16) & 3)
3584 int64_t StartOffset = Offset & ~15;
3586 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3587 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3589 int EltNo = (Offset - StartOffset) >> 2;
3590 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3591 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3592 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3594 // Canonicalize it to a v4i32 shuffle.
3595 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3596 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3597 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3598 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3605 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3606 DebugLoc dl = Op.getDebugLoc();
3607 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3608 if (ISD::isBuildVectorAllZeros(Op.getNode())
3609 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3610 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3611 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3612 // eliminated on x86-32 hosts.
3613 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3616 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3617 return getOnesVector(Op.getValueType(), DAG, dl);
3618 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3621 EVT VT = Op.getValueType();
3622 EVT ExtVT = VT.getVectorElementType();
3623 unsigned EVTBits = ExtVT.getSizeInBits();
3625 unsigned NumElems = Op.getNumOperands();
3626 unsigned NumZero = 0;
3627 unsigned NumNonZero = 0;
3628 unsigned NonZeros = 0;
3629 bool IsAllConstants = true;
3630 SmallSet<SDValue, 8> Values;
3631 for (unsigned i = 0; i < NumElems; ++i) {
3632 SDValue Elt = Op.getOperand(i);
3633 if (Elt.getOpcode() == ISD::UNDEF)
3636 if (Elt.getOpcode() != ISD::Constant &&
3637 Elt.getOpcode() != ISD::ConstantFP)
3638 IsAllConstants = false;
3639 if (X86::isZeroNode(Elt))
3642 NonZeros |= (1 << i);
3647 if (NumNonZero == 0) {
3648 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3649 return DAG.getUNDEF(VT);
3652 // Special case for single non-zero, non-undef, element.
3653 if (NumNonZero == 1) {
3654 unsigned Idx = CountTrailingZeros_32(NonZeros);
3655 SDValue Item = Op.getOperand(Idx);
3657 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3658 // the value are obviously zero, truncate the value to i32 and do the
3659 // insertion that way. Only do this if the value is non-constant or if the
3660 // value is a constant being inserted into element 0. It is cheaper to do
3661 // a constant pool load than it is to do a movd + shuffle.
3662 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3663 (!IsAllConstants || Idx == 0)) {
3664 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3665 // Handle MMX and SSE both.
3666 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3667 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3669 // Truncate the value (which may itself be a constant) to i32, and
3670 // convert it to a vector with movd (S2V+shuffle to zero extend).
3671 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3672 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3673 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3674 Subtarget->hasSSE2(), DAG);
3676 // Now we have our 32-bit value zero extended in the low element of
3677 // a vector. If Idx != 0, swizzle it into place.
3679 SmallVector<int, 4> Mask;
3680 Mask.push_back(Idx);
3681 for (unsigned i = 1; i != VecElts; ++i)
3683 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3684 DAG.getUNDEF(Item.getValueType()),
3687 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3691 // If we have a constant or non-constant insertion into the low element of
3692 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3693 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3694 // depending on what the source datatype is.
3697 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3698 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3699 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3700 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3701 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3702 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3704 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3705 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3706 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3707 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3708 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3709 Subtarget->hasSSE2(), DAG);
3710 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3714 // Is it a vector logical left shift?
3715 if (NumElems == 2 && Idx == 1 &&
3716 X86::isZeroNode(Op.getOperand(0)) &&
3717 !X86::isZeroNode(Op.getOperand(1))) {
3718 unsigned NumBits = VT.getSizeInBits();
3719 return getVShift(true, VT,
3720 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3721 VT, Op.getOperand(1)),
3722 NumBits/2, DAG, *this, dl);
3725 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3728 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3729 // is a non-constant being inserted into an element other than the low one,
3730 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3731 // movd/movss) to move this into the low element, then shuffle it into
3733 if (EVTBits == 32) {
3734 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3736 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3737 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3738 Subtarget->hasSSE2(), DAG);
3739 SmallVector<int, 8> MaskVec;
3740 for (unsigned i = 0; i < NumElems; i++)
3741 MaskVec.push_back(i == Idx ? 0 : 1);
3742 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3746 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3747 if (Values.size() == 1) {
3748 if (EVTBits == 32) {
3749 // Instead of a shuffle like this:
3750 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3751 // Check if it's possible to issue this instead.
3752 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3753 unsigned Idx = CountTrailingZeros_32(NonZeros);
3754 SDValue Item = Op.getOperand(Idx);
3755 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3756 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3761 // A vector full of immediates; various special cases are already
3762 // handled, so this is best done with a single constant-pool load.
3766 // Let legalizer expand 2-wide build_vectors.
3767 if (EVTBits == 64) {
3768 if (NumNonZero == 1) {
3769 // One half is zero or undef.
3770 unsigned Idx = CountTrailingZeros_32(NonZeros);
3771 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3772 Op.getOperand(Idx));
3773 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3774 Subtarget->hasSSE2(), DAG);
3779 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3780 if (EVTBits == 8 && NumElems == 16) {
3781 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3783 if (V.getNode()) return V;
3786 if (EVTBits == 16 && NumElems == 8) {
3787 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3789 if (V.getNode()) return V;
3792 // If element VT is == 32 bits, turn it into a number of shuffles.
3793 SmallVector<SDValue, 8> V;
3795 if (NumElems == 4 && NumZero > 0) {
3796 for (unsigned i = 0; i < 4; ++i) {
3797 bool isZero = !(NonZeros & (1 << i));
3799 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3801 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3804 for (unsigned i = 0; i < 2; ++i) {
3805 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3808 V[i] = V[i*2]; // Must be a zero vector.
3811 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3814 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3817 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3822 SmallVector<int, 8> MaskVec;
3823 bool Reverse = (NonZeros & 0x3) == 2;
3824 for (unsigned i = 0; i < 2; ++i)
3825 MaskVec.push_back(Reverse ? 1-i : i);
3826 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3827 for (unsigned i = 0; i < 2; ++i)
3828 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3829 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3832 if (Values.size() > 2) {
3833 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3834 // values to be inserted is equal to the number of elements, in which case
3835 // use the unpack code below in the hopes of matching the consecutive elts
3836 // load merge pattern for shuffles.
3837 // FIXME: We could probably just check that here directly.
3838 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3839 getSubtarget()->hasSSE41()) {
3840 V[0] = DAG.getUNDEF(VT);
3841 for (unsigned i = 0; i < NumElems; ++i)
3842 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3843 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3844 Op.getOperand(i), DAG.getIntPtrConstant(i));
3847 // Expand into a number of unpckl*.
3849 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3850 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3851 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3852 for (unsigned i = 0; i < NumElems; ++i)
3853 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3855 while (NumElems != 0) {
3856 for (unsigned i = 0; i < NumElems; ++i)
3857 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3867 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3868 // We support concatenate two MMX registers and place them in a MMX
3869 // register. This is better than doing a stack convert.
3870 DebugLoc dl = Op.getDebugLoc();
3871 EVT ResVT = Op.getValueType();
3872 assert(Op.getNumOperands() == 2);
3873 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
3874 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
3876 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
3877 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3878 InVec = Op.getOperand(1);
3879 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3880 unsigned NumElts = ResVT.getVectorNumElements();
3881 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3882 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
3883 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
3885 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
3886 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3887 Mask[0] = 0; Mask[1] = 2;
3888 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
3890 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3893 // v8i16 shuffles - Prefer shuffles in the following order:
3894 // 1. [all] pshuflw, pshufhw, optional move
3895 // 2. [ssse3] 1 x pshufb
3896 // 3. [ssse3] 2 x pshufb + 1 x por
3897 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3899 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3900 SelectionDAG &DAG, X86TargetLowering &TLI) {
3901 SDValue V1 = SVOp->getOperand(0);
3902 SDValue V2 = SVOp->getOperand(1);
3903 DebugLoc dl = SVOp->getDebugLoc();
3904 SmallVector<int, 8> MaskVals;
3906 // Determine if more than 1 of the words in each of the low and high quadwords
3907 // of the result come from the same quadword of one of the two inputs. Undef
3908 // mask values count as coming from any quadword, for better codegen.
3909 SmallVector<unsigned, 4> LoQuad(4);
3910 SmallVector<unsigned, 4> HiQuad(4);
3911 BitVector InputQuads(4);
3912 for (unsigned i = 0; i < 8; ++i) {
3913 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3914 int EltIdx = SVOp->getMaskElt(i);
3915 MaskVals.push_back(EltIdx);
3924 InputQuads.set(EltIdx / 4);
3927 int BestLoQuad = -1;
3928 unsigned MaxQuad = 1;
3929 for (unsigned i = 0; i < 4; ++i) {
3930 if (LoQuad[i] > MaxQuad) {
3932 MaxQuad = LoQuad[i];
3936 int BestHiQuad = -1;
3938 for (unsigned i = 0; i < 4; ++i) {
3939 if (HiQuad[i] > MaxQuad) {
3941 MaxQuad = HiQuad[i];
3945 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3946 // of the two input vectors, shuffle them into one input vector so only a
3947 // single pshufb instruction is necessary. If There are more than 2 input
3948 // quads, disable the next transformation since it does not help SSSE3.
3949 bool V1Used = InputQuads[0] || InputQuads[1];
3950 bool V2Used = InputQuads[2] || InputQuads[3];
3951 if (TLI.getSubtarget()->hasSSSE3()) {
3952 if (InputQuads.count() == 2 && V1Used && V2Used) {
3953 BestLoQuad = InputQuads.find_first();
3954 BestHiQuad = InputQuads.find_next(BestLoQuad);
3956 if (InputQuads.count() > 2) {
3962 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3963 // the shuffle mask. If a quad is scored as -1, that means that it contains
3964 // words from all 4 input quadwords.
3966 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3967 SmallVector<int, 8> MaskV;
3968 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3969 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3970 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3971 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3972 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3973 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3975 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3976 // source words for the shuffle, to aid later transformations.
3977 bool AllWordsInNewV = true;
3978 bool InOrder[2] = { true, true };
3979 for (unsigned i = 0; i != 8; ++i) {
3980 int idx = MaskVals[i];
3982 InOrder[i/4] = false;
3983 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3985 AllWordsInNewV = false;
3989 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3990 if (AllWordsInNewV) {
3991 for (int i = 0; i != 8; ++i) {
3992 int idx = MaskVals[i];
3995 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3996 if ((idx != i) && idx < 4)
3998 if ((idx != i) && idx > 3)
4007 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4008 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4009 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4010 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4011 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4015 // If we have SSSE3, and all words of the result are from 1 input vector,
4016 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4017 // is present, fall back to case 4.
4018 if (TLI.getSubtarget()->hasSSSE3()) {
4019 SmallVector<SDValue,16> pshufbMask;
4021 // If we have elements from both input vectors, set the high bit of the
4022 // shuffle mask element to zero out elements that come from V2 in the V1
4023 // mask, and elements that come from V1 in the V2 mask, so that the two
4024 // results can be OR'd together.
4025 bool TwoInputs = V1Used && V2Used;
4026 for (unsigned i = 0; i != 8; ++i) {
4027 int EltIdx = MaskVals[i] * 2;
4028 if (TwoInputs && (EltIdx >= 16)) {
4029 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4030 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4033 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4034 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4036 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4037 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4038 DAG.getNode(ISD::BUILD_VECTOR, dl,
4039 MVT::v16i8, &pshufbMask[0], 16));
4041 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4043 // Calculate the shuffle mask for the second input, shuffle it, and
4044 // OR it with the first shuffled input.
4046 for (unsigned i = 0; i != 8; ++i) {
4047 int EltIdx = MaskVals[i] * 2;
4049 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4050 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4053 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4054 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4056 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4057 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4058 DAG.getNode(ISD::BUILD_VECTOR, dl,
4059 MVT::v16i8, &pshufbMask[0], 16));
4060 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4061 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4064 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4065 // and update MaskVals with new element order.
4066 BitVector InOrder(8);
4067 if (BestLoQuad >= 0) {
4068 SmallVector<int, 8> MaskV;
4069 for (int i = 0; i != 4; ++i) {
4070 int idx = MaskVals[i];
4072 MaskV.push_back(-1);
4074 } else if ((idx / 4) == BestLoQuad) {
4075 MaskV.push_back(idx & 3);
4078 MaskV.push_back(-1);
4081 for (unsigned i = 4; i != 8; ++i)
4083 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4087 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4088 // and update MaskVals with the new element order.
4089 if (BestHiQuad >= 0) {
4090 SmallVector<int, 8> MaskV;
4091 for (unsigned i = 0; i != 4; ++i)
4093 for (unsigned i = 4; i != 8; ++i) {
4094 int idx = MaskVals[i];
4096 MaskV.push_back(-1);
4098 } else if ((idx / 4) == BestHiQuad) {
4099 MaskV.push_back((idx & 3) + 4);
4102 MaskV.push_back(-1);
4105 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4109 // In case BestHi & BestLo were both -1, which means each quadword has a word
4110 // from each of the four input quadwords, calculate the InOrder bitvector now
4111 // before falling through to the insert/extract cleanup.
4112 if (BestLoQuad == -1 && BestHiQuad == -1) {
4114 for (int i = 0; i != 8; ++i)
4115 if (MaskVals[i] < 0 || MaskVals[i] == i)
4119 // The other elements are put in the right place using pextrw and pinsrw.
4120 for (unsigned i = 0; i != 8; ++i) {
4123 int EltIdx = MaskVals[i];
4126 SDValue ExtOp = (EltIdx < 8)
4127 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4128 DAG.getIntPtrConstant(EltIdx))
4129 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4130 DAG.getIntPtrConstant(EltIdx - 8));
4131 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4132 DAG.getIntPtrConstant(i));
4137 // v16i8 shuffles - Prefer shuffles in the following order:
4138 // 1. [ssse3] 1 x pshufb
4139 // 2. [ssse3] 2 x pshufb + 1 x por
4140 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4142 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4143 SelectionDAG &DAG, X86TargetLowering &TLI) {
4144 SDValue V1 = SVOp->getOperand(0);
4145 SDValue V2 = SVOp->getOperand(1);
4146 DebugLoc dl = SVOp->getDebugLoc();
4147 SmallVector<int, 16> MaskVals;
4148 SVOp->getMask(MaskVals);
4150 // If we have SSSE3, case 1 is generated when all result bytes come from
4151 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4152 // present, fall back to case 3.
4153 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4156 for (unsigned i = 0; i < 16; ++i) {
4157 int EltIdx = MaskVals[i];
4166 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4167 if (TLI.getSubtarget()->hasSSSE3()) {
4168 SmallVector<SDValue,16> pshufbMask;
4170 // If all result elements are from one input vector, then only translate
4171 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4173 // Otherwise, we have elements from both input vectors, and must zero out
4174 // elements that come from V2 in the first mask, and V1 in the second mask
4175 // so that we can OR them together.
4176 bool TwoInputs = !(V1Only || V2Only);
4177 for (unsigned i = 0; i != 16; ++i) {
4178 int EltIdx = MaskVals[i];
4179 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4180 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4183 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4185 // If all the elements are from V2, assign it to V1 and return after
4186 // building the first pshufb.
4189 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4190 DAG.getNode(ISD::BUILD_VECTOR, dl,
4191 MVT::v16i8, &pshufbMask[0], 16));
4195 // Calculate the shuffle mask for the second input, shuffle it, and
4196 // OR it with the first shuffled input.
4198 for (unsigned i = 0; i != 16; ++i) {
4199 int EltIdx = MaskVals[i];
4201 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4204 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4206 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4207 DAG.getNode(ISD::BUILD_VECTOR, dl,
4208 MVT::v16i8, &pshufbMask[0], 16));
4209 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4212 // No SSSE3 - Calculate in place words and then fix all out of place words
4213 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4214 // the 16 different words that comprise the two doublequadword input vectors.
4215 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4216 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4217 SDValue NewV = V2Only ? V2 : V1;
4218 for (int i = 0; i != 8; ++i) {
4219 int Elt0 = MaskVals[i*2];
4220 int Elt1 = MaskVals[i*2+1];
4222 // This word of the result is all undef, skip it.
4223 if (Elt0 < 0 && Elt1 < 0)
4226 // This word of the result is already in the correct place, skip it.
4227 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4229 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4232 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4233 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4236 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4237 // using a single extract together, load it and store it.
4238 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4239 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4240 DAG.getIntPtrConstant(Elt1 / 2));
4241 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4242 DAG.getIntPtrConstant(i));
4246 // If Elt1 is defined, extract it from the appropriate source. If the
4247 // source byte is not also odd, shift the extracted word left 8 bits
4248 // otherwise clear the bottom 8 bits if we need to do an or.
4250 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4251 DAG.getIntPtrConstant(Elt1 / 2));
4252 if ((Elt1 & 1) == 0)
4253 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4254 DAG.getConstant(8, TLI.getShiftAmountTy()));
4256 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4257 DAG.getConstant(0xFF00, MVT::i16));
4259 // If Elt0 is defined, extract it from the appropriate source. If the
4260 // source byte is not also even, shift the extracted word right 8 bits. If
4261 // Elt1 was also defined, OR the extracted values together before
4262 // inserting them in the result.
4264 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4265 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4266 if ((Elt0 & 1) != 0)
4267 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4268 DAG.getConstant(8, TLI.getShiftAmountTy()));
4270 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4271 DAG.getConstant(0x00FF, MVT::i16));
4272 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4275 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4276 DAG.getIntPtrConstant(i));
4278 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4281 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4282 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4283 /// done when every pair / quad of shuffle mask elements point to elements in
4284 /// the right sequence. e.g.
4285 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4287 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4289 TargetLowering &TLI, DebugLoc dl) {
4290 EVT VT = SVOp->getValueType(0);
4291 SDValue V1 = SVOp->getOperand(0);
4292 SDValue V2 = SVOp->getOperand(1);
4293 unsigned NumElems = VT.getVectorNumElements();
4294 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4295 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4296 EVT MaskEltVT = MaskVT.getVectorElementType();
4298 switch (VT.getSimpleVT().SimpleTy) {
4299 default: assert(false && "Unexpected!");
4300 case MVT::v4f32: NewVT = MVT::v2f64; break;
4301 case MVT::v4i32: NewVT = MVT::v2i64; break;
4302 case MVT::v8i16: NewVT = MVT::v4i32; break;
4303 case MVT::v16i8: NewVT = MVT::v4i32; break;
4306 if (NewWidth == 2) {
4312 int Scale = NumElems / NewWidth;
4313 SmallVector<int, 8> MaskVec;
4314 for (unsigned i = 0; i < NumElems; i += Scale) {
4316 for (int j = 0; j < Scale; ++j) {
4317 int EltIdx = SVOp->getMaskElt(i+j);
4321 StartIdx = EltIdx - (EltIdx % Scale);
4322 if (EltIdx != StartIdx + j)
4326 MaskVec.push_back(-1);
4328 MaskVec.push_back(StartIdx / Scale);
4331 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4332 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4333 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4336 /// getVZextMovL - Return a zero-extending vector move low node.
4338 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4339 SDValue SrcOp, SelectionDAG &DAG,
4340 const X86Subtarget *Subtarget, DebugLoc dl) {
4341 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4342 LoadSDNode *LD = NULL;
4343 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4344 LD = dyn_cast<LoadSDNode>(SrcOp);
4346 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4348 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4349 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4350 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4351 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4352 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4354 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4355 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4356 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4357 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4365 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4366 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4367 DAG.getNode(ISD::BIT_CONVERT, dl,
4371 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4374 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4375 SDValue V1 = SVOp->getOperand(0);
4376 SDValue V2 = SVOp->getOperand(1);
4377 DebugLoc dl = SVOp->getDebugLoc();
4378 EVT VT = SVOp->getValueType(0);
4380 SmallVector<std::pair<int, int>, 8> Locs;
4382 SmallVector<int, 8> Mask1(4U, -1);
4383 SmallVector<int, 8> PermMask;
4384 SVOp->getMask(PermMask);
4388 for (unsigned i = 0; i != 4; ++i) {
4389 int Idx = PermMask[i];
4391 Locs[i] = std::make_pair(-1, -1);
4393 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4395 Locs[i] = std::make_pair(0, NumLo);
4399 Locs[i] = std::make_pair(1, NumHi);
4401 Mask1[2+NumHi] = Idx;
4407 if (NumLo <= 2 && NumHi <= 2) {
4408 // If no more than two elements come from either vector. This can be
4409 // implemented with two shuffles. First shuffle gather the elements.
4410 // The second shuffle, which takes the first shuffle as both of its
4411 // vector operands, put the elements into the right order.
4412 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4414 SmallVector<int, 8> Mask2(4U, -1);
4416 for (unsigned i = 0; i != 4; ++i) {
4417 if (Locs[i].first == -1)
4420 unsigned Idx = (i < 2) ? 0 : 4;
4421 Idx += Locs[i].first * 2 + Locs[i].second;
4426 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4427 } else if (NumLo == 3 || NumHi == 3) {
4428 // Otherwise, we must have three elements from one vector, call it X, and
4429 // one element from the other, call it Y. First, use a shufps to build an
4430 // intermediate vector with the one element from Y and the element from X
4431 // that will be in the same half in the final destination (the indexes don't
4432 // matter). Then, use a shufps to build the final vector, taking the half
4433 // containing the element from Y from the intermediate, and the other half
4436 // Normalize it so the 3 elements come from V1.
4437 CommuteVectorShuffleMask(PermMask, VT);
4441 // Find the element from V2.
4443 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4444 int Val = PermMask[HiIndex];
4451 Mask1[0] = PermMask[HiIndex];
4453 Mask1[2] = PermMask[HiIndex^1];
4455 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4458 Mask1[0] = PermMask[0];
4459 Mask1[1] = PermMask[1];
4460 Mask1[2] = HiIndex & 1 ? 6 : 4;
4461 Mask1[3] = HiIndex & 1 ? 4 : 6;
4462 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4464 Mask1[0] = HiIndex & 1 ? 2 : 0;
4465 Mask1[1] = HiIndex & 1 ? 0 : 2;
4466 Mask1[2] = PermMask[2];
4467 Mask1[3] = PermMask[3];
4472 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4476 // Break it into (shuffle shuffle_hi, shuffle_lo).
4478 SmallVector<int,8> LoMask(4U, -1);
4479 SmallVector<int,8> HiMask(4U, -1);
4481 SmallVector<int,8> *MaskPtr = &LoMask;
4482 unsigned MaskIdx = 0;
4485 for (unsigned i = 0; i != 4; ++i) {
4492 int Idx = PermMask[i];
4494 Locs[i] = std::make_pair(-1, -1);
4495 } else if (Idx < 4) {
4496 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4497 (*MaskPtr)[LoIdx] = Idx;
4500 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4501 (*MaskPtr)[HiIdx] = Idx;
4506 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4507 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4508 SmallVector<int, 8> MaskOps;
4509 for (unsigned i = 0; i != 4; ++i) {
4510 if (Locs[i].first == -1) {
4511 MaskOps.push_back(-1);
4513 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4514 MaskOps.push_back(Idx);
4517 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4521 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4522 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4523 SDValue V1 = Op.getOperand(0);
4524 SDValue V2 = Op.getOperand(1);
4525 EVT VT = Op.getValueType();
4526 DebugLoc dl = Op.getDebugLoc();
4527 unsigned NumElems = VT.getVectorNumElements();
4528 bool isMMX = VT.getSizeInBits() == 64;
4529 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4530 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4531 bool V1IsSplat = false;
4532 bool V2IsSplat = false;
4534 if (isZeroShuffle(SVOp))
4535 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4537 // Promote splats to v4f32.
4538 if (SVOp->isSplat()) {
4539 if (isMMX || NumElems < 4)
4541 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4544 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4546 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4547 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4548 if (NewOp.getNode())
4549 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4550 LowerVECTOR_SHUFFLE(NewOp, DAG));
4551 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4552 // FIXME: Figure out a cleaner way to do this.
4553 // Try to make use of movq to zero out the top part.
4554 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4555 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4556 if (NewOp.getNode()) {
4557 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4558 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4559 DAG, Subtarget, dl);
4561 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4562 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4563 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4564 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4565 DAG, Subtarget, dl);
4569 if (X86::isPSHUFDMask(SVOp))
4572 // Check if this can be converted into a logical shift.
4573 bool isLeft = false;
4576 bool isShift = getSubtarget()->hasSSE2() &&
4577 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4578 if (isShift && ShVal.hasOneUse()) {
4579 // If the shifted value has multiple uses, it may be cheaper to use
4580 // v_set0 + movlhps or movhlps, etc.
4581 EVT EltVT = VT.getVectorElementType();
4582 ShAmt *= EltVT.getSizeInBits();
4583 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4586 if (X86::isMOVLMask(SVOp)) {
4589 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4590 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4595 // FIXME: fold these into legal mask.
4596 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4597 X86::isMOVSLDUPMask(SVOp) ||
4598 X86::isMOVHLPSMask(SVOp) ||
4599 X86::isMOVLHPSMask(SVOp) ||
4600 X86::isMOVLPMask(SVOp)))
4603 if (ShouldXformToMOVHLPS(SVOp) ||
4604 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4605 return CommuteVectorShuffle(SVOp, DAG);
4608 // No better options. Use a vshl / vsrl.
4609 EVT EltVT = VT.getVectorElementType();
4610 ShAmt *= EltVT.getSizeInBits();
4611 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4614 bool Commuted = false;
4615 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4616 // 1,1,1,1 -> v8i16 though.
4617 V1IsSplat = isSplatVector(V1.getNode());
4618 V2IsSplat = isSplatVector(V2.getNode());
4620 // Canonicalize the splat or undef, if present, to be on the RHS.
4621 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4622 Op = CommuteVectorShuffle(SVOp, DAG);
4623 SVOp = cast<ShuffleVectorSDNode>(Op);
4624 V1 = SVOp->getOperand(0);
4625 V2 = SVOp->getOperand(1);
4626 std::swap(V1IsSplat, V2IsSplat);
4627 std::swap(V1IsUndef, V2IsUndef);
4631 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4632 // Shuffling low element of v1 into undef, just return v1.
4635 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4636 // the instruction selector will not match, so get a canonical MOVL with
4637 // swapped operands to undo the commute.
4638 return getMOVL(DAG, dl, VT, V2, V1);
4641 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4642 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4643 X86::isUNPCKLMask(SVOp) ||
4644 X86::isUNPCKHMask(SVOp))
4648 // Normalize mask so all entries that point to V2 points to its first
4649 // element then try to match unpck{h|l} again. If match, return a
4650 // new vector_shuffle with the corrected mask.
4651 SDValue NewMask = NormalizeMask(SVOp, DAG);
4652 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4653 if (NSVOp != SVOp) {
4654 if (X86::isUNPCKLMask(NSVOp, true)) {
4656 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4663 // Commute is back and try unpck* again.
4664 // FIXME: this seems wrong.
4665 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4666 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4667 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4668 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4669 X86::isUNPCKLMask(NewSVOp) ||
4670 X86::isUNPCKHMask(NewSVOp))
4674 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4676 // Normalize the node to match x86 shuffle ops if needed
4677 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4678 return CommuteVectorShuffle(SVOp, DAG);
4680 // Check for legal shuffle and return?
4681 SmallVector<int, 16> PermMask;
4682 SVOp->getMask(PermMask);
4683 if (isShuffleMaskLegal(PermMask, VT))
4686 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4687 if (VT == MVT::v8i16) {
4688 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4689 if (NewOp.getNode())
4693 if (VT == MVT::v16i8) {
4694 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4695 if (NewOp.getNode())
4699 // Handle all 4 wide cases with a number of shuffles except for MMX.
4700 if (NumElems == 4 && !isMMX)
4701 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4707 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4708 SelectionDAG &DAG) {
4709 EVT VT = Op.getValueType();
4710 DebugLoc dl = Op.getDebugLoc();
4711 if (VT.getSizeInBits() == 8) {
4712 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4713 Op.getOperand(0), Op.getOperand(1));
4714 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4715 DAG.getValueType(VT));
4716 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4717 } else if (VT.getSizeInBits() == 16) {
4718 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4719 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4721 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4722 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4723 DAG.getNode(ISD::BIT_CONVERT, dl,
4727 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4728 Op.getOperand(0), Op.getOperand(1));
4729 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4730 DAG.getValueType(VT));
4731 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4732 } else if (VT == MVT::f32) {
4733 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4734 // the result back to FR32 register. It's only worth matching if the
4735 // result has a single use which is a store or a bitcast to i32. And in
4736 // the case of a store, it's not worth it if the index is a constant 0,
4737 // because a MOVSSmr can be used instead, which is smaller and faster.
4738 if (!Op.hasOneUse())
4740 SDNode *User = *Op.getNode()->use_begin();
4741 if ((User->getOpcode() != ISD::STORE ||
4742 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4743 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4744 (User->getOpcode() != ISD::BIT_CONVERT ||
4745 User->getValueType(0) != MVT::i32))
4747 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4748 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4751 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4752 } else if (VT == MVT::i32) {
4753 // ExtractPS works with constant index.
4754 if (isa<ConstantSDNode>(Op.getOperand(1)))
4762 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4763 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4766 if (Subtarget->hasSSE41()) {
4767 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4772 EVT VT = Op.getValueType();
4773 DebugLoc dl = Op.getDebugLoc();
4774 // TODO: handle v16i8.
4775 if (VT.getSizeInBits() == 16) {
4776 SDValue Vec = Op.getOperand(0);
4777 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4779 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4780 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4781 DAG.getNode(ISD::BIT_CONVERT, dl,
4784 // Transform it so it match pextrw which produces a 32-bit result.
4785 EVT EltVT = MVT::i32;
4786 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4787 Op.getOperand(0), Op.getOperand(1));
4788 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4789 DAG.getValueType(VT));
4790 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4791 } else if (VT.getSizeInBits() == 32) {
4792 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4796 // SHUFPS the element to the lowest double word, then movss.
4797 int Mask[4] = { Idx, -1, -1, -1 };
4798 EVT VVT = Op.getOperand(0).getValueType();
4799 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4800 DAG.getUNDEF(VVT), Mask);
4801 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4802 DAG.getIntPtrConstant(0));
4803 } else if (VT.getSizeInBits() == 64) {
4804 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4805 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4806 // to match extract_elt for f64.
4807 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4811 // UNPCKHPD the element to the lowest double word, then movsd.
4812 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4813 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4814 int Mask[2] = { 1, -1 };
4815 EVT VVT = Op.getOperand(0).getValueType();
4816 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4817 DAG.getUNDEF(VVT), Mask);
4818 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4819 DAG.getIntPtrConstant(0));
4826 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4827 EVT VT = Op.getValueType();
4828 EVT EltVT = VT.getVectorElementType();
4829 DebugLoc dl = Op.getDebugLoc();
4831 SDValue N0 = Op.getOperand(0);
4832 SDValue N1 = Op.getOperand(1);
4833 SDValue N2 = Op.getOperand(2);
4835 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4836 isa<ConstantSDNode>(N2)) {
4838 if (VT == MVT::v8i16)
4839 Opc = X86ISD::PINSRW;
4840 else if (VT == MVT::v4i16)
4841 Opc = X86ISD::MMX_PINSRW;
4842 else if (VT == MVT::v16i8)
4843 Opc = X86ISD::PINSRB;
4845 Opc = X86ISD::PINSRB;
4847 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4849 if (N1.getValueType() != MVT::i32)
4850 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4851 if (N2.getValueType() != MVT::i32)
4852 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4853 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4854 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4855 // Bits [7:6] of the constant are the source select. This will always be
4856 // zero here. The DAG Combiner may combine an extract_elt index into these
4857 // bits. For example (insert (extract, 3), 2) could be matched by putting
4858 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4859 // Bits [5:4] of the constant are the destination select. This is the
4860 // value of the incoming immediate.
4861 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4862 // combine either bitwise AND or insert of float 0.0 to set these bits.
4863 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4864 // Create this as a scalar to vector..
4865 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4866 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4867 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4868 // PINSR* works with constant index.
4875 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4876 EVT VT = Op.getValueType();
4877 EVT EltVT = VT.getVectorElementType();
4879 if (Subtarget->hasSSE41())
4880 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4882 if (EltVT == MVT::i8)
4885 DebugLoc dl = Op.getDebugLoc();
4886 SDValue N0 = Op.getOperand(0);
4887 SDValue N1 = Op.getOperand(1);
4888 SDValue N2 = Op.getOperand(2);
4890 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4891 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4892 // as its second argument.
4893 if (N1.getValueType() != MVT::i32)
4894 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4895 if (N2.getValueType() != MVT::i32)
4896 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4897 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
4898 dl, VT, N0, N1, N2);
4904 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4905 DebugLoc dl = Op.getDebugLoc();
4906 if (Op.getValueType() == MVT::v2f32)
4907 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4908 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4909 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4910 Op.getOperand(0))));
4912 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4913 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4915 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4916 EVT VT = MVT::v2i32;
4917 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4924 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4925 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4928 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4929 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4930 // one of the above mentioned nodes. It has to be wrapped because otherwise
4931 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4932 // be used to form addressing mode. These wrapped nodes will be selected
4935 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4936 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4938 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4940 unsigned char OpFlag = 0;
4941 unsigned WrapperKind = X86ISD::Wrapper;
4942 CodeModel::Model M = getTargetMachine().getCodeModel();
4944 if (Subtarget->isPICStyleRIPRel() &&
4945 (M == CodeModel::Small || M == CodeModel::Kernel))
4946 WrapperKind = X86ISD::WrapperRIP;
4947 else if (Subtarget->isPICStyleGOT())
4948 OpFlag = X86II::MO_GOTOFF;
4949 else if (Subtarget->isPICStyleStubPIC())
4950 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4952 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4954 CP->getOffset(), OpFlag);
4955 DebugLoc DL = CP->getDebugLoc();
4956 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4957 // With PIC, the address is actually $g + Offset.
4959 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4960 DAG.getNode(X86ISD::GlobalBaseReg,
4961 DebugLoc::getUnknownLoc(), getPointerTy()),
4968 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4969 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4971 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4973 unsigned char OpFlag = 0;
4974 unsigned WrapperKind = X86ISD::Wrapper;
4975 CodeModel::Model M = getTargetMachine().getCodeModel();
4977 if (Subtarget->isPICStyleRIPRel() &&
4978 (M == CodeModel::Small || M == CodeModel::Kernel))
4979 WrapperKind = X86ISD::WrapperRIP;
4980 else if (Subtarget->isPICStyleGOT())
4981 OpFlag = X86II::MO_GOTOFF;
4982 else if (Subtarget->isPICStyleStubPIC())
4983 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4985 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4987 DebugLoc DL = JT->getDebugLoc();
4988 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4990 // With PIC, the address is actually $g + Offset.
4992 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4993 DAG.getNode(X86ISD::GlobalBaseReg,
4994 DebugLoc::getUnknownLoc(), getPointerTy()),
5002 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
5003 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5005 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5007 unsigned char OpFlag = 0;
5008 unsigned WrapperKind = X86ISD::Wrapper;
5009 CodeModel::Model M = getTargetMachine().getCodeModel();
5011 if (Subtarget->isPICStyleRIPRel() &&
5012 (M == CodeModel::Small || M == CodeModel::Kernel))
5013 WrapperKind = X86ISD::WrapperRIP;
5014 else if (Subtarget->isPICStyleGOT())
5015 OpFlag = X86II::MO_GOTOFF;
5016 else if (Subtarget->isPICStyleStubPIC())
5017 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5019 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5021 DebugLoc DL = Op.getDebugLoc();
5022 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5025 // With PIC, the address is actually $g + Offset.
5026 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5027 !Subtarget->is64Bit()) {
5028 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5029 DAG.getNode(X86ISD::GlobalBaseReg,
5030 DebugLoc::getUnknownLoc(),
5039 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
5040 // Create the TargetBlockAddressAddress node.
5041 unsigned char OpFlags =
5042 Subtarget->ClassifyBlockAddressReference();
5043 CodeModel::Model M = getTargetMachine().getCodeModel();
5044 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5045 DebugLoc dl = Op.getDebugLoc();
5046 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5047 /*isTarget=*/true, OpFlags);
5049 if (Subtarget->isPICStyleRIPRel() &&
5050 (M == CodeModel::Small || M == CodeModel::Kernel))
5051 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5053 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5055 // With PIC, the address is actually $g + Offset.
5056 if (isGlobalRelativeToPICBase(OpFlags)) {
5057 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5058 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5066 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5068 SelectionDAG &DAG) const {
5069 // Create the TargetGlobalAddress node, folding in the constant
5070 // offset if it is legal.
5071 unsigned char OpFlags =
5072 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5073 CodeModel::Model M = getTargetMachine().getCodeModel();
5075 if (OpFlags == X86II::MO_NO_FLAG &&
5076 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5077 // A direct static reference to a global.
5078 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
5081 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
5084 if (Subtarget->isPICStyleRIPRel() &&
5085 (M == CodeModel::Small || M == CodeModel::Kernel))
5086 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5088 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5090 // With PIC, the address is actually $g + Offset.
5091 if (isGlobalRelativeToPICBase(OpFlags)) {
5092 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5093 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5097 // For globals that require a load from a stub to get the address, emit the
5099 if (isGlobalStubReference(OpFlags))
5100 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5101 PseudoSourceValue::getGOT(), 0, false, false, 0);
5103 // If there was a non-zero offset that we didn't fold, create an explicit
5106 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5107 DAG.getConstant(Offset, getPointerTy()));
5113 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
5114 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5115 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5116 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5120 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5121 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5122 unsigned char OperandFlags) {
5123 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5124 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5125 DebugLoc dl = GA->getDebugLoc();
5126 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
5127 GA->getValueType(0),
5131 SDValue Ops[] = { Chain, TGA, *InFlag };
5132 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5134 SDValue Ops[] = { Chain, TGA };
5135 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5138 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5139 MFI->setHasCalls(true);
5141 SDValue Flag = Chain.getValue(1);
5142 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5145 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5147 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5150 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5151 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5152 DAG.getNode(X86ISD::GlobalBaseReg,
5153 DebugLoc::getUnknownLoc(),
5155 InFlag = Chain.getValue(1);
5157 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5160 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5162 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5164 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5165 X86::RAX, X86II::MO_TLSGD);
5168 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5169 // "local exec" model.
5170 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5171 const EVT PtrVT, TLSModel::Model model,
5173 DebugLoc dl = GA->getDebugLoc();
5174 // Get the Thread Pointer
5175 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5176 DebugLoc::getUnknownLoc(), PtrVT,
5177 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5180 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5181 NULL, 0, false, false, 0);
5183 unsigned char OperandFlags = 0;
5184 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5186 unsigned WrapperKind = X86ISD::Wrapper;
5187 if (model == TLSModel::LocalExec) {
5188 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5189 } else if (is64Bit) {
5190 assert(model == TLSModel::InitialExec);
5191 OperandFlags = X86II::MO_GOTTPOFF;
5192 WrapperKind = X86ISD::WrapperRIP;
5194 assert(model == TLSModel::InitialExec);
5195 OperandFlags = X86II::MO_INDNTPOFF;
5198 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5200 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5201 GA->getOffset(), OperandFlags);
5202 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5204 if (model == TLSModel::InitialExec)
5205 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5206 PseudoSourceValue::getGOT(), 0, false, false, 0);
5208 // The address of the thread local variable is the add of the thread
5209 // pointer with the offset of the variable.
5210 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5214 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5215 // TODO: implement the "local dynamic" model
5216 // TODO: implement the "initial exec"model for pic executables
5217 assert(Subtarget->isTargetELF() &&
5218 "TLS not implemented for non-ELF targets");
5219 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5220 const GlobalValue *GV = GA->getGlobal();
5222 // If GV is an alias then use the aliasee for determining
5223 // thread-localness.
5224 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5225 GV = GA->resolveAliasedGlobal(false);
5227 TLSModel::Model model = getTLSModel(GV,
5228 getTargetMachine().getRelocationModel());
5231 case TLSModel::GeneralDynamic:
5232 case TLSModel::LocalDynamic: // not implemented
5233 if (Subtarget->is64Bit())
5234 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5235 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5237 case TLSModel::InitialExec:
5238 case TLSModel::LocalExec:
5239 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5240 Subtarget->is64Bit());
5243 llvm_unreachable("Unreachable");
5248 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5249 /// take a 2 x i32 value to shift plus a shift amount.
5250 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5251 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5252 EVT VT = Op.getValueType();
5253 unsigned VTBits = VT.getSizeInBits();
5254 DebugLoc dl = Op.getDebugLoc();
5255 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5256 SDValue ShOpLo = Op.getOperand(0);
5257 SDValue ShOpHi = Op.getOperand(1);
5258 SDValue ShAmt = Op.getOperand(2);
5259 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5260 DAG.getConstant(VTBits - 1, MVT::i8))
5261 : DAG.getConstant(0, VT);
5264 if (Op.getOpcode() == ISD::SHL_PARTS) {
5265 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5266 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5268 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5269 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5272 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5273 DAG.getConstant(VTBits, MVT::i8));
5274 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5275 AndNode, DAG.getConstant(0, MVT::i8));
5278 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5279 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5280 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5282 if (Op.getOpcode() == ISD::SHL_PARTS) {
5283 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5284 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5286 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5287 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5290 SDValue Ops[2] = { Lo, Hi };
5291 return DAG.getMergeValues(Ops, 2, dl);
5294 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5295 EVT SrcVT = Op.getOperand(0).getValueType();
5297 if (SrcVT.isVector()) {
5298 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5304 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5305 "Unknown SINT_TO_FP to lower!");
5307 // These are really Legal; return the operand so the caller accepts it as
5309 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5311 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5312 Subtarget->is64Bit()) {
5316 DebugLoc dl = Op.getDebugLoc();
5317 unsigned Size = SrcVT.getSizeInBits()/8;
5318 MachineFunction &MF = DAG.getMachineFunction();
5319 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5320 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5321 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5323 PseudoSourceValue::getFixedStack(SSFI), 0,
5325 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5328 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5330 SelectionDAG &DAG) {
5332 DebugLoc dl = Op.getDebugLoc();
5334 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5336 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5338 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5339 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5340 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5341 Tys, Ops, array_lengthof(Ops));
5344 Chain = Result.getValue(1);
5345 SDValue InFlag = Result.getValue(2);
5347 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5348 // shouldn't be necessary except that RFP cannot be live across
5349 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5350 MachineFunction &MF = DAG.getMachineFunction();
5351 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5352 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5353 Tys = DAG.getVTList(MVT::Other);
5355 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5357 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5358 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5359 PseudoSourceValue::getFixedStack(SSFI), 0,
5366 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5367 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5368 // This algorithm is not obvious. Here it is in C code, more or less:
5370 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5371 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5372 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5374 // Copy ints to xmm registers.
5375 __m128i xh = _mm_cvtsi32_si128( hi );
5376 __m128i xl = _mm_cvtsi32_si128( lo );
5378 // Combine into low half of a single xmm register.
5379 __m128i x = _mm_unpacklo_epi32( xh, xl );
5383 // Merge in appropriate exponents to give the integer bits the right
5385 x = _mm_unpacklo_epi32( x, exp );
5387 // Subtract away the biases to deal with the IEEE-754 double precision
5389 d = _mm_sub_pd( (__m128d) x, bias );
5391 // All conversions up to here are exact. The correctly rounded result is
5392 // calculated using the current rounding mode using the following
5394 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5395 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5396 // store doesn't really need to be here (except
5397 // maybe to zero the other double)
5402 DebugLoc dl = Op.getDebugLoc();
5403 LLVMContext *Context = DAG.getContext();
5405 // Build some magic constants.
5406 std::vector<Constant*> CV0;
5407 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5408 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5409 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5410 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5411 Constant *C0 = ConstantVector::get(CV0);
5412 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5414 std::vector<Constant*> CV1;
5416 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5418 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5419 Constant *C1 = ConstantVector::get(CV1);
5420 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5422 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5423 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5425 DAG.getIntPtrConstant(1)));
5426 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5427 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5429 DAG.getIntPtrConstant(0)));
5430 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5431 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5432 PseudoSourceValue::getConstantPool(), 0,
5434 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5435 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5436 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5437 PseudoSourceValue::getConstantPool(), 0,
5439 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5441 // Add the halves; easiest way is to swap them into another reg first.
5442 int ShufMask[2] = { 1, -1 };
5443 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5444 DAG.getUNDEF(MVT::v2f64), ShufMask);
5445 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5446 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5447 DAG.getIntPtrConstant(0));
5450 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5451 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5452 DebugLoc dl = Op.getDebugLoc();
5453 // FP constant to bias correct the final result.
5454 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5457 // Load the 32-bit value into an XMM register.
5458 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5459 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5461 DAG.getIntPtrConstant(0)));
5463 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5464 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5465 DAG.getIntPtrConstant(0));
5467 // Or the load with the bias.
5468 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5469 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5470 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5472 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5473 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5474 MVT::v2f64, Bias)));
5475 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5476 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5477 DAG.getIntPtrConstant(0));
5479 // Subtract the bias.
5480 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5482 // Handle final rounding.
5483 EVT DestVT = Op.getValueType();
5485 if (DestVT.bitsLT(MVT::f64)) {
5486 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5487 DAG.getIntPtrConstant(0));
5488 } else if (DestVT.bitsGT(MVT::f64)) {
5489 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5492 // Handle final rounding.
5496 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5497 SDValue N0 = Op.getOperand(0);
5498 DebugLoc dl = Op.getDebugLoc();
5500 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5501 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5502 // the optimization here.
5503 if (DAG.SignBitIsZero(N0))
5504 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5506 EVT SrcVT = N0.getValueType();
5507 if (SrcVT == MVT::i64) {
5508 // We only handle SSE2 f64 target here; caller can expand the rest.
5509 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5512 return LowerUINT_TO_FP_i64(Op, DAG);
5513 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5514 return LowerUINT_TO_FP_i32(Op, DAG);
5517 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5519 // Make a 64-bit buffer, and use it to build an FILD.
5520 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5521 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5522 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5523 getPointerTy(), StackSlot, WordOff);
5524 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5525 StackSlot, NULL, 0, false, false, 0);
5526 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5527 OffsetSlot, NULL, 0, false, false, 0);
5528 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5531 std::pair<SDValue,SDValue> X86TargetLowering::
5532 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5533 DebugLoc dl = Op.getDebugLoc();
5535 EVT DstTy = Op.getValueType();
5538 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5542 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5543 DstTy.getSimpleVT() >= MVT::i16 &&
5544 "Unknown FP_TO_SINT to lower!");
5546 // These are really Legal.
5547 if (DstTy == MVT::i32 &&
5548 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5549 return std::make_pair(SDValue(), SDValue());
5550 if (Subtarget->is64Bit() &&
5551 DstTy == MVT::i64 &&
5552 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5553 return std::make_pair(SDValue(), SDValue());
5555 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5557 MachineFunction &MF = DAG.getMachineFunction();
5558 unsigned MemSize = DstTy.getSizeInBits()/8;
5559 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5560 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5563 switch (DstTy.getSimpleVT().SimpleTy) {
5564 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5565 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5566 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5567 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5570 SDValue Chain = DAG.getEntryNode();
5571 SDValue Value = Op.getOperand(0);
5572 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5573 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5574 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5575 PseudoSourceValue::getFixedStack(SSFI), 0,
5577 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5579 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5581 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5582 Chain = Value.getValue(1);
5583 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5584 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5587 // Build the FP_TO_INT*_IN_MEM
5588 SDValue Ops[] = { Chain, Value, StackSlot };
5589 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5591 return std::make_pair(FIST, StackSlot);
5594 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5595 if (Op.getValueType().isVector()) {
5596 if (Op.getValueType() == MVT::v2i32 &&
5597 Op.getOperand(0).getValueType() == MVT::v2f64) {
5603 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5604 SDValue FIST = Vals.first, StackSlot = Vals.second;
5605 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5606 if (FIST.getNode() == 0) return Op;
5609 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5610 FIST, StackSlot, NULL, 0, false, false, 0);
5613 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5614 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5615 SDValue FIST = Vals.first, StackSlot = Vals.second;
5616 assert(FIST.getNode() && "Unexpected failure");
5619 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5620 FIST, StackSlot, NULL, 0, false, false, 0);
5623 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5624 LLVMContext *Context = DAG.getContext();
5625 DebugLoc dl = Op.getDebugLoc();
5626 EVT VT = Op.getValueType();
5629 EltVT = VT.getVectorElementType();
5630 std::vector<Constant*> CV;
5631 if (EltVT == MVT::f64) {
5632 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5636 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5642 Constant *C = ConstantVector::get(CV);
5643 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5644 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5645 PseudoSourceValue::getConstantPool(), 0,
5647 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5650 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5651 LLVMContext *Context = DAG.getContext();
5652 DebugLoc dl = Op.getDebugLoc();
5653 EVT VT = Op.getValueType();
5656 EltVT = VT.getVectorElementType();
5657 std::vector<Constant*> CV;
5658 if (EltVT == MVT::f64) {
5659 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5663 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5669 Constant *C = ConstantVector::get(CV);
5670 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5671 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5672 PseudoSourceValue::getConstantPool(), 0,
5674 if (VT.isVector()) {
5675 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5676 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5677 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5679 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5681 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5685 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5686 LLVMContext *Context = DAG.getContext();
5687 SDValue Op0 = Op.getOperand(0);
5688 SDValue Op1 = Op.getOperand(1);
5689 DebugLoc dl = Op.getDebugLoc();
5690 EVT VT = Op.getValueType();
5691 EVT SrcVT = Op1.getValueType();
5693 // If second operand is smaller, extend it first.
5694 if (SrcVT.bitsLT(VT)) {
5695 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5698 // And if it is bigger, shrink it first.
5699 if (SrcVT.bitsGT(VT)) {
5700 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5704 // At this point the operands and the result should have the same
5705 // type, and that won't be f80 since that is not custom lowered.
5707 // First get the sign bit of second operand.
5708 std::vector<Constant*> CV;
5709 if (SrcVT == MVT::f64) {
5710 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5711 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5713 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5714 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5715 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5716 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5718 Constant *C = ConstantVector::get(CV);
5719 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5720 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5721 PseudoSourceValue::getConstantPool(), 0,
5723 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5725 // Shift sign bit right or left if the two operands have different types.
5726 if (SrcVT.bitsGT(VT)) {
5727 // Op0 is MVT::f32, Op1 is MVT::f64.
5728 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5729 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5730 DAG.getConstant(32, MVT::i32));
5731 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5732 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5733 DAG.getIntPtrConstant(0));
5736 // Clear first operand sign bit.
5738 if (VT == MVT::f64) {
5739 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5740 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5742 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5743 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5744 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5745 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5747 C = ConstantVector::get(CV);
5748 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5749 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5750 PseudoSourceValue::getConstantPool(), 0,
5752 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5754 // Or the value with the sign bit.
5755 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5758 /// Emit nodes that will be selected as "test Op0,Op0", or something
5760 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5761 SelectionDAG &DAG) {
5762 DebugLoc dl = Op.getDebugLoc();
5764 // CF and OF aren't always set the way we want. Determine which
5765 // of these we need.
5766 bool NeedCF = false;
5767 bool NeedOF = false;
5769 case X86::COND_A: case X86::COND_AE:
5770 case X86::COND_B: case X86::COND_BE:
5773 case X86::COND_G: case X86::COND_GE:
5774 case X86::COND_L: case X86::COND_LE:
5775 case X86::COND_O: case X86::COND_NO:
5781 // See if we can use the EFLAGS value from the operand instead of
5782 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5783 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5784 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5785 unsigned Opcode = 0;
5786 unsigned NumOperands = 0;
5787 switch (Op.getNode()->getOpcode()) {
5789 // Due to an isel shortcoming, be conservative if this add is likely to
5790 // be selected as part of a load-modify-store instruction. When the root
5791 // node in a match is a store, isel doesn't know how to remap non-chain
5792 // non-flag uses of other nodes in the match, such as the ADD in this
5793 // case. This leads to the ADD being left around and reselected, with
5794 // the result being two adds in the output.
5795 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5796 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5797 if (UI->getOpcode() == ISD::STORE)
5799 if (ConstantSDNode *C =
5800 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5801 // An add of one will be selected as an INC.
5802 if (C->getAPIntValue() == 1) {
5803 Opcode = X86ISD::INC;
5807 // An add of negative one (subtract of one) will be selected as a DEC.
5808 if (C->getAPIntValue().isAllOnesValue()) {
5809 Opcode = X86ISD::DEC;
5814 // Otherwise use a regular EFLAGS-setting add.
5815 Opcode = X86ISD::ADD;
5819 // If the primary and result isn't used, don't bother using X86ISD::AND,
5820 // because a TEST instruction will be better.
5821 bool NonFlagUse = false;
5822 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5823 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
5825 unsigned UOpNo = UI.getOperandNo();
5826 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
5827 // Look pass truncate.
5828 UOpNo = User->use_begin().getOperandNo();
5829 User = *User->use_begin();
5831 if (User->getOpcode() != ISD::BRCOND &&
5832 User->getOpcode() != ISD::SETCC &&
5833 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
5845 // Due to the ISEL shortcoming noted above, be conservative if this op is
5846 // likely to be selected as part of a load-modify-store instruction.
5847 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5848 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5849 if (UI->getOpcode() == ISD::STORE)
5851 // Otherwise use a regular EFLAGS-setting instruction.
5852 switch (Op.getNode()->getOpcode()) {
5853 case ISD::SUB: Opcode = X86ISD::SUB; break;
5854 case ISD::OR: Opcode = X86ISD::OR; break;
5855 case ISD::XOR: Opcode = X86ISD::XOR; break;
5856 case ISD::AND: Opcode = X86ISD::AND; break;
5857 default: llvm_unreachable("unexpected operator!");
5868 return SDValue(Op.getNode(), 1);
5874 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5875 SmallVector<SDValue, 4> Ops;
5876 for (unsigned i = 0; i != NumOperands; ++i)
5877 Ops.push_back(Op.getOperand(i));
5878 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5879 DAG.ReplaceAllUsesWith(Op, New);
5880 return SDValue(New.getNode(), 1);
5884 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5885 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5886 DAG.getConstant(0, Op.getValueType()));
5889 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5891 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5892 SelectionDAG &DAG) {
5893 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5894 if (C->getAPIntValue() == 0)
5895 return EmitTest(Op0, X86CC, DAG);
5897 DebugLoc dl = Op0.getDebugLoc();
5898 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5901 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
5902 /// if it's possible.
5903 static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
5904 DebugLoc dl, SelectionDAG &DAG) {
5905 SDValue Op0 = And.getOperand(0);
5906 SDValue Op1 = And.getOperand(1);
5907 if (Op0.getOpcode() == ISD::TRUNCATE)
5908 Op0 = Op0.getOperand(0);
5909 if (Op1.getOpcode() == ISD::TRUNCATE)
5910 Op1 = Op1.getOperand(0);
5913 if (Op1.getOpcode() == ISD::SHL) {
5914 if (ConstantSDNode *And10C = dyn_cast<ConstantSDNode>(Op1.getOperand(0)))
5915 if (And10C->getZExtValue() == 1) {
5917 RHS = Op1.getOperand(1);
5919 } else if (Op0.getOpcode() == ISD::SHL) {
5920 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
5921 if (And00C->getZExtValue() == 1) {
5923 RHS = Op0.getOperand(1);
5925 } else if (Op1.getOpcode() == ISD::Constant) {
5926 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
5927 SDValue AndLHS = Op0;
5928 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5929 LHS = AndLHS.getOperand(0);
5930 RHS = AndLHS.getOperand(1);
5934 if (LHS.getNode()) {
5935 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5936 // instruction. Since the shift amount is in-range-or-undefined, we know
5937 // that doing a bittest on the i16 value is ok. We extend to i32 because
5938 // the encoding for the i16 version is larger than the i32 version.
5939 if (LHS.getValueType() == MVT::i8)
5940 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5942 // If the operand types disagree, extend the shift amount to match. Since
5943 // BT ignores high bits (like shifts) we can use anyextend.
5944 if (LHS.getValueType() != RHS.getValueType())
5945 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5947 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5948 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5949 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5950 DAG.getConstant(Cond, MVT::i8), BT);
5956 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5957 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5958 SDValue Op0 = Op.getOperand(0);
5959 SDValue Op1 = Op.getOperand(1);
5960 DebugLoc dl = Op.getDebugLoc();
5961 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5963 // Optimize to BT if possible.
5964 // Lower (X & (1 << N)) == 0 to BT(X, N).
5965 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5966 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5967 if (Op0.getOpcode() == ISD::AND &&
5969 Op1.getOpcode() == ISD::Constant &&
5970 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5971 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5972 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
5973 if (NewSetCC.getNode())
5977 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
5978 if (Op0.getOpcode() == X86ISD::SETCC &&
5979 Op1.getOpcode() == ISD::Constant &&
5980 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
5981 cast<ConstantSDNode>(Op1)->isNullValue()) &&
5982 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5983 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
5984 bool Invert = (CC == ISD::SETNE) ^
5985 cast<ConstantSDNode>(Op1)->isNullValue();
5987 CCode = X86::GetOppositeBranchCondition(CCode);
5988 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5989 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
5992 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5993 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5994 if (X86CC == X86::COND_INVALID)
5997 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5999 // Use sbb x, x to materialize carry bit into a GPR.
6000 if (X86CC == X86::COND_B)
6001 return DAG.getNode(ISD::AND, dl, MVT::i8,
6002 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6003 DAG.getConstant(X86CC, MVT::i8), Cond),
6004 DAG.getConstant(1, MVT::i8));
6006 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6007 DAG.getConstant(X86CC, MVT::i8), Cond);
6010 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
6012 SDValue Op0 = Op.getOperand(0);
6013 SDValue Op1 = Op.getOperand(1);
6014 SDValue CC = Op.getOperand(2);
6015 EVT VT = Op.getValueType();
6016 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6017 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6018 DebugLoc dl = Op.getDebugLoc();
6022 EVT VT0 = Op0.getValueType();
6023 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6024 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6027 switch (SetCCOpcode) {
6030 case ISD::SETEQ: SSECC = 0; break;
6032 case ISD::SETGT: Swap = true; // Fallthrough
6034 case ISD::SETOLT: SSECC = 1; break;
6036 case ISD::SETGE: Swap = true; // Fallthrough
6038 case ISD::SETOLE: SSECC = 2; break;
6039 case ISD::SETUO: SSECC = 3; break;
6041 case ISD::SETNE: SSECC = 4; break;
6042 case ISD::SETULE: Swap = true;
6043 case ISD::SETUGE: SSECC = 5; break;
6044 case ISD::SETULT: Swap = true;
6045 case ISD::SETUGT: SSECC = 6; break;
6046 case ISD::SETO: SSECC = 7; break;
6049 std::swap(Op0, Op1);
6051 // In the two special cases we can't handle, emit two comparisons.
6053 if (SetCCOpcode == ISD::SETUEQ) {
6055 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6056 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6057 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6059 else if (SetCCOpcode == ISD::SETONE) {
6061 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6062 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6063 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6065 llvm_unreachable("Illegal FP comparison");
6067 // Handle all other FP comparisons here.
6068 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6071 // We are handling one of the integer comparisons here. Since SSE only has
6072 // GT and EQ comparisons for integer, swapping operands and multiple
6073 // operations may be required for some comparisons.
6074 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6075 bool Swap = false, Invert = false, FlipSigns = false;
6077 switch (VT.getSimpleVT().SimpleTy) {
6080 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6082 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6084 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6085 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6088 switch (SetCCOpcode) {
6090 case ISD::SETNE: Invert = true;
6091 case ISD::SETEQ: Opc = EQOpc; break;
6092 case ISD::SETLT: Swap = true;
6093 case ISD::SETGT: Opc = GTOpc; break;
6094 case ISD::SETGE: Swap = true;
6095 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6096 case ISD::SETULT: Swap = true;
6097 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6098 case ISD::SETUGE: Swap = true;
6099 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6102 std::swap(Op0, Op1);
6104 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6105 // bits of the inputs before performing those operations.
6107 EVT EltVT = VT.getVectorElementType();
6108 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6110 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6111 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6113 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6114 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6117 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6119 // If the logical-not of the result is required, perform that now.
6121 Result = DAG.getNOT(dl, Result, VT);
6126 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6127 static bool isX86LogicalCmp(SDValue Op) {
6128 unsigned Opc = Op.getNode()->getOpcode();
6129 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6131 if (Op.getResNo() == 1 &&
6132 (Opc == X86ISD::ADD ||
6133 Opc == X86ISD::SUB ||
6134 Opc == X86ISD::SMUL ||
6135 Opc == X86ISD::UMUL ||
6136 Opc == X86ISD::INC ||
6137 Opc == X86ISD::DEC ||
6138 Opc == X86ISD::OR ||
6139 Opc == X86ISD::XOR ||
6140 Opc == X86ISD::AND))
6146 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
6147 bool addTest = true;
6148 SDValue Cond = Op.getOperand(0);
6149 DebugLoc dl = Op.getDebugLoc();
6152 if (Cond.getOpcode() == ISD::SETCC) {
6153 SDValue NewCond = LowerSETCC(Cond, DAG);
6154 if (NewCond.getNode())
6158 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6159 SDValue Op1 = Op.getOperand(1);
6160 SDValue Op2 = Op.getOperand(2);
6161 if (Cond.getOpcode() == X86ISD::SETCC &&
6162 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6163 SDValue Cmp = Cond.getOperand(1);
6164 if (Cmp.getOpcode() == X86ISD::CMP) {
6165 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6166 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6167 ConstantSDNode *RHSC =
6168 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6169 if (N1C && N1C->isAllOnesValue() &&
6170 N2C && N2C->isNullValue() &&
6171 RHSC && RHSC->isNullValue()) {
6172 SDValue CmpOp0 = Cmp.getOperand(0);
6173 Cmp = DAG.getNode(X86ISD::CMP, dl, CmpOp0.getValueType(),
6174 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6175 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6176 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6181 // Look pass (and (setcc_carry (cmp ...)), 1).
6182 if (Cond.getOpcode() == ISD::AND &&
6183 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6184 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6185 if (C && C->getAPIntValue() == 1)
6186 Cond = Cond.getOperand(0);
6189 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6190 // setting operand in place of the X86ISD::SETCC.
6191 if (Cond.getOpcode() == X86ISD::SETCC ||
6192 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6193 CC = Cond.getOperand(0);
6195 SDValue Cmp = Cond.getOperand(1);
6196 unsigned Opc = Cmp.getOpcode();
6197 EVT VT = Op.getValueType();
6199 bool IllegalFPCMov = false;
6200 if (VT.isFloatingPoint() && !VT.isVector() &&
6201 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6202 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6204 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6205 Opc == X86ISD::BT) { // FIXME
6212 // Look pass the truncate.
6213 if (Cond.getOpcode() == ISD::TRUNCATE)
6214 Cond = Cond.getOperand(0);
6216 // We know the result of AND is compared against zero. Try to match
6218 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6219 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6220 if (NewSetCC.getNode()) {
6221 CC = NewSetCC.getOperand(0);
6222 Cond = NewSetCC.getOperand(1);
6229 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6230 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6233 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6234 // condition is true.
6235 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6236 SDValue Ops[] = { Op2, Op1, CC, Cond };
6237 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6240 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6241 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6242 // from the AND / OR.
6243 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6244 Opc = Op.getOpcode();
6245 if (Opc != ISD::OR && Opc != ISD::AND)
6247 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6248 Op.getOperand(0).hasOneUse() &&
6249 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6250 Op.getOperand(1).hasOneUse());
6253 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6254 // 1 and that the SETCC node has a single use.
6255 static bool isXor1OfSetCC(SDValue Op) {
6256 if (Op.getOpcode() != ISD::XOR)
6258 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6259 if (N1C && N1C->getAPIntValue() == 1) {
6260 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6261 Op.getOperand(0).hasOneUse();
6266 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
6267 bool addTest = true;
6268 SDValue Chain = Op.getOperand(0);
6269 SDValue Cond = Op.getOperand(1);
6270 SDValue Dest = Op.getOperand(2);
6271 DebugLoc dl = Op.getDebugLoc();
6274 if (Cond.getOpcode() == ISD::SETCC) {
6275 SDValue NewCond = LowerSETCC(Cond, DAG);
6276 if (NewCond.getNode())
6280 // FIXME: LowerXALUO doesn't handle these!!
6281 else if (Cond.getOpcode() == X86ISD::ADD ||
6282 Cond.getOpcode() == X86ISD::SUB ||
6283 Cond.getOpcode() == X86ISD::SMUL ||
6284 Cond.getOpcode() == X86ISD::UMUL)
6285 Cond = LowerXALUO(Cond, DAG);
6288 // Look pass (and (setcc_carry (cmp ...)), 1).
6289 if (Cond.getOpcode() == ISD::AND &&
6290 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6291 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6292 if (C && C->getAPIntValue() == 1)
6293 Cond = Cond.getOperand(0);
6296 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6297 // setting operand in place of the X86ISD::SETCC.
6298 if (Cond.getOpcode() == X86ISD::SETCC ||
6299 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6300 CC = Cond.getOperand(0);
6302 SDValue Cmp = Cond.getOperand(1);
6303 unsigned Opc = Cmp.getOpcode();
6304 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6305 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6309 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6313 // These can only come from an arithmetic instruction with overflow,
6314 // e.g. SADDO, UADDO.
6315 Cond = Cond.getNode()->getOperand(1);
6322 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6323 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6324 if (CondOpc == ISD::OR) {
6325 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6326 // two branches instead of an explicit OR instruction with a
6328 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6329 isX86LogicalCmp(Cmp)) {
6330 CC = Cond.getOperand(0).getOperand(0);
6331 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6332 Chain, Dest, CC, Cmp);
6333 CC = Cond.getOperand(1).getOperand(0);
6337 } else { // ISD::AND
6338 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6339 // two branches instead of an explicit AND instruction with a
6340 // separate test. However, we only do this if this block doesn't
6341 // have a fall-through edge, because this requires an explicit
6342 // jmp when the condition is false.
6343 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6344 isX86LogicalCmp(Cmp) &&
6345 Op.getNode()->hasOneUse()) {
6346 X86::CondCode CCode =
6347 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6348 CCode = X86::GetOppositeBranchCondition(CCode);
6349 CC = DAG.getConstant(CCode, MVT::i8);
6350 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6351 // Look for an unconditional branch following this conditional branch.
6352 // We need this because we need to reverse the successors in order
6353 // to implement FCMP_OEQ.
6354 if (User.getOpcode() == ISD::BR) {
6355 SDValue FalseBB = User.getOperand(1);
6357 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6358 assert(NewBR == User);
6361 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6362 Chain, Dest, CC, Cmp);
6363 X86::CondCode CCode =
6364 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6365 CCode = X86::GetOppositeBranchCondition(CCode);
6366 CC = DAG.getConstant(CCode, MVT::i8);
6372 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6373 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6374 // It should be transformed during dag combiner except when the condition
6375 // is set by a arithmetics with overflow node.
6376 X86::CondCode CCode =
6377 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6378 CCode = X86::GetOppositeBranchCondition(CCode);
6379 CC = DAG.getConstant(CCode, MVT::i8);
6380 Cond = Cond.getOperand(0).getOperand(1);
6386 // Look pass the truncate.
6387 if (Cond.getOpcode() == ISD::TRUNCATE)
6388 Cond = Cond.getOperand(0);
6390 // We know the result of AND is compared against zero. Try to match
6392 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6393 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6394 if (NewSetCC.getNode()) {
6395 CC = NewSetCC.getOperand(0);
6396 Cond = NewSetCC.getOperand(1);
6403 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6404 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6406 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6407 Chain, Dest, CC, Cond);
6411 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6412 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6413 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6414 // that the guard pages used by the OS virtual memory manager are allocated in
6415 // correct sequence.
6417 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6418 SelectionDAG &DAG) {
6419 assert(Subtarget->isTargetCygMing() &&
6420 "This should be used only on Cygwin/Mingw targets");
6421 DebugLoc dl = Op.getDebugLoc();
6424 SDValue Chain = Op.getOperand(0);
6425 SDValue Size = Op.getOperand(1);
6426 // FIXME: Ensure alignment here
6430 EVT IntPtr = getPointerTy();
6431 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6433 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6434 Flag = Chain.getValue(1);
6436 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6438 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6439 Flag = Chain.getValue(1);
6441 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6443 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6444 return DAG.getMergeValues(Ops1, 2, dl);
6448 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6450 SDValue Dst, SDValue Src,
6451 SDValue Size, unsigned Align,
6453 uint64_t DstSVOff) {
6454 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6456 // If not DWORD aligned or size is more than the threshold, call the library.
6457 // The libc version is likely to be faster for these cases. It can use the
6458 // address value and run time information about the CPU.
6459 if ((Align & 3) != 0 ||
6461 ConstantSize->getZExtValue() >
6462 getSubtarget()->getMaxInlineSizeThreshold()) {
6463 SDValue InFlag(0, 0);
6465 // Check to see if there is a specialized entry-point for memory zeroing.
6466 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6468 if (const char *bzeroEntry = V &&
6469 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6470 EVT IntPtr = getPointerTy();
6471 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6472 TargetLowering::ArgListTy Args;
6473 TargetLowering::ArgListEntry Entry;
6475 Entry.Ty = IntPtrTy;
6476 Args.push_back(Entry);
6478 Args.push_back(Entry);
6479 std::pair<SDValue,SDValue> CallResult =
6480 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6481 false, false, false, false,
6482 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6483 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
6484 return CallResult.second;
6487 // Otherwise have the target-independent code call memset.
6491 uint64_t SizeVal = ConstantSize->getZExtValue();
6492 SDValue InFlag(0, 0);
6495 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6496 unsigned BytesLeft = 0;
6497 bool TwoRepStos = false;
6500 uint64_t Val = ValC->getZExtValue() & 255;
6502 // If the value is a constant, then we can potentially use larger sets.
6503 switch (Align & 3) {
6504 case 2: // WORD aligned
6507 Val = (Val << 8) | Val;
6509 case 0: // DWORD aligned
6512 Val = (Val << 8) | Val;
6513 Val = (Val << 16) | Val;
6514 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6517 Val = (Val << 32) | Val;
6520 default: // Byte aligned
6523 Count = DAG.getIntPtrConstant(SizeVal);
6527 if (AVT.bitsGT(MVT::i8)) {
6528 unsigned UBytes = AVT.getSizeInBits() / 8;
6529 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6530 BytesLeft = SizeVal % UBytes;
6533 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6535 InFlag = Chain.getValue(1);
6538 Count = DAG.getIntPtrConstant(SizeVal);
6539 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6540 InFlag = Chain.getValue(1);
6543 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6546 InFlag = Chain.getValue(1);
6547 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6550 InFlag = Chain.getValue(1);
6552 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6553 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6554 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6557 InFlag = Chain.getValue(1);
6559 EVT CVT = Count.getValueType();
6560 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6561 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6562 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6565 InFlag = Chain.getValue(1);
6566 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6567 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
6568 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6569 } else if (BytesLeft) {
6570 // Handle the last 1 - 7 bytes.
6571 unsigned Offset = SizeVal - BytesLeft;
6572 EVT AddrVT = Dst.getValueType();
6573 EVT SizeVT = Size.getValueType();
6575 Chain = DAG.getMemset(Chain, dl,
6576 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6577 DAG.getConstant(Offset, AddrVT)),
6579 DAG.getConstant(BytesLeft, SizeVT),
6580 Align, DstSV, DstSVOff + Offset);
6583 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6588 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6589 SDValue Chain, SDValue Dst, SDValue Src,
6590 SDValue Size, unsigned Align,
6592 const Value *DstSV, uint64_t DstSVOff,
6593 const Value *SrcSV, uint64_t SrcSVOff) {
6594 // This requires the copy size to be a constant, preferrably
6595 // within a subtarget-specific limit.
6596 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6599 uint64_t SizeVal = ConstantSize->getZExtValue();
6600 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6603 /// If not DWORD aligned, call the library.
6604 if ((Align & 3) != 0)
6609 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6612 unsigned UBytes = AVT.getSizeInBits() / 8;
6613 unsigned CountVal = SizeVal / UBytes;
6614 SDValue Count = DAG.getIntPtrConstant(CountVal);
6615 unsigned BytesLeft = SizeVal % UBytes;
6617 SDValue InFlag(0, 0);
6618 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6621 InFlag = Chain.getValue(1);
6622 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6625 InFlag = Chain.getValue(1);
6626 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6629 InFlag = Chain.getValue(1);
6631 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6632 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6633 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
6634 array_lengthof(Ops));
6636 SmallVector<SDValue, 4> Results;
6637 Results.push_back(RepMovs);
6639 // Handle the last 1 - 7 bytes.
6640 unsigned Offset = SizeVal - BytesLeft;
6641 EVT DstVT = Dst.getValueType();
6642 EVT SrcVT = Src.getValueType();
6643 EVT SizeVT = Size.getValueType();
6644 Results.push_back(DAG.getMemcpy(Chain, dl,
6645 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6646 DAG.getConstant(Offset, DstVT)),
6647 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6648 DAG.getConstant(Offset, SrcVT)),
6649 DAG.getConstant(BytesLeft, SizeVT),
6650 Align, AlwaysInline,
6651 DstSV, DstSVOff + Offset,
6652 SrcSV, SrcSVOff + Offset));
6655 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6656 &Results[0], Results.size());
6659 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6660 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6661 DebugLoc dl = Op.getDebugLoc();
6663 if (!Subtarget->is64Bit()) {
6664 // vastart just stores the address of the VarArgsFrameIndex slot into the
6665 // memory location argument.
6666 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6667 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6672 // gp_offset (0 - 6 * 8)
6673 // fp_offset (48 - 48 + 8 * 16)
6674 // overflow_arg_area (point to parameters coming in memory).
6676 SmallVector<SDValue, 8> MemOps;
6677 SDValue FIN = Op.getOperand(1);
6679 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6680 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6681 FIN, SV, 0, false, false, 0);
6682 MemOps.push_back(Store);
6685 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6686 FIN, DAG.getIntPtrConstant(4));
6687 Store = DAG.getStore(Op.getOperand(0), dl,
6688 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6689 FIN, SV, 0, false, false, 0);
6690 MemOps.push_back(Store);
6692 // Store ptr to overflow_arg_area
6693 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6694 FIN, DAG.getIntPtrConstant(4));
6695 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6696 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0,
6698 MemOps.push_back(Store);
6700 // Store ptr to reg_save_area.
6701 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6702 FIN, DAG.getIntPtrConstant(8));
6703 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6704 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0,
6706 MemOps.push_back(Store);
6707 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6708 &MemOps[0], MemOps.size());
6711 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6712 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6713 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6714 SDValue Chain = Op.getOperand(0);
6715 SDValue SrcPtr = Op.getOperand(1);
6716 SDValue SrcSV = Op.getOperand(2);
6718 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6722 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6723 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6724 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6725 SDValue Chain = Op.getOperand(0);
6726 SDValue DstPtr = Op.getOperand(1);
6727 SDValue SrcPtr = Op.getOperand(2);
6728 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6729 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6730 DebugLoc dl = Op.getDebugLoc();
6732 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6733 DAG.getIntPtrConstant(24), 8, false,
6734 DstSV, 0, SrcSV, 0);
6738 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6739 DebugLoc dl = Op.getDebugLoc();
6740 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6742 default: return SDValue(); // Don't custom lower most intrinsics.
6743 // Comparison intrinsics.
6744 case Intrinsic::x86_sse_comieq_ss:
6745 case Intrinsic::x86_sse_comilt_ss:
6746 case Intrinsic::x86_sse_comile_ss:
6747 case Intrinsic::x86_sse_comigt_ss:
6748 case Intrinsic::x86_sse_comige_ss:
6749 case Intrinsic::x86_sse_comineq_ss:
6750 case Intrinsic::x86_sse_ucomieq_ss:
6751 case Intrinsic::x86_sse_ucomilt_ss:
6752 case Intrinsic::x86_sse_ucomile_ss:
6753 case Intrinsic::x86_sse_ucomigt_ss:
6754 case Intrinsic::x86_sse_ucomige_ss:
6755 case Intrinsic::x86_sse_ucomineq_ss:
6756 case Intrinsic::x86_sse2_comieq_sd:
6757 case Intrinsic::x86_sse2_comilt_sd:
6758 case Intrinsic::x86_sse2_comile_sd:
6759 case Intrinsic::x86_sse2_comigt_sd:
6760 case Intrinsic::x86_sse2_comige_sd:
6761 case Intrinsic::x86_sse2_comineq_sd:
6762 case Intrinsic::x86_sse2_ucomieq_sd:
6763 case Intrinsic::x86_sse2_ucomilt_sd:
6764 case Intrinsic::x86_sse2_ucomile_sd:
6765 case Intrinsic::x86_sse2_ucomigt_sd:
6766 case Intrinsic::x86_sse2_ucomige_sd:
6767 case Intrinsic::x86_sse2_ucomineq_sd: {
6769 ISD::CondCode CC = ISD::SETCC_INVALID;
6772 case Intrinsic::x86_sse_comieq_ss:
6773 case Intrinsic::x86_sse2_comieq_sd:
6777 case Intrinsic::x86_sse_comilt_ss:
6778 case Intrinsic::x86_sse2_comilt_sd:
6782 case Intrinsic::x86_sse_comile_ss:
6783 case Intrinsic::x86_sse2_comile_sd:
6787 case Intrinsic::x86_sse_comigt_ss:
6788 case Intrinsic::x86_sse2_comigt_sd:
6792 case Intrinsic::x86_sse_comige_ss:
6793 case Intrinsic::x86_sse2_comige_sd:
6797 case Intrinsic::x86_sse_comineq_ss:
6798 case Intrinsic::x86_sse2_comineq_sd:
6802 case Intrinsic::x86_sse_ucomieq_ss:
6803 case Intrinsic::x86_sse2_ucomieq_sd:
6804 Opc = X86ISD::UCOMI;
6807 case Intrinsic::x86_sse_ucomilt_ss:
6808 case Intrinsic::x86_sse2_ucomilt_sd:
6809 Opc = X86ISD::UCOMI;
6812 case Intrinsic::x86_sse_ucomile_ss:
6813 case Intrinsic::x86_sse2_ucomile_sd:
6814 Opc = X86ISD::UCOMI;
6817 case Intrinsic::x86_sse_ucomigt_ss:
6818 case Intrinsic::x86_sse2_ucomigt_sd:
6819 Opc = X86ISD::UCOMI;
6822 case Intrinsic::x86_sse_ucomige_ss:
6823 case Intrinsic::x86_sse2_ucomige_sd:
6824 Opc = X86ISD::UCOMI;
6827 case Intrinsic::x86_sse_ucomineq_ss:
6828 case Intrinsic::x86_sse2_ucomineq_sd:
6829 Opc = X86ISD::UCOMI;
6834 SDValue LHS = Op.getOperand(1);
6835 SDValue RHS = Op.getOperand(2);
6836 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6837 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6838 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6839 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6840 DAG.getConstant(X86CC, MVT::i8), Cond);
6841 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6843 // ptest intrinsics. The intrinsic these come from are designed to return
6844 // an integer value, not just an instruction so lower it to the ptest
6845 // pattern and a setcc for the result.
6846 case Intrinsic::x86_sse41_ptestz:
6847 case Intrinsic::x86_sse41_ptestc:
6848 case Intrinsic::x86_sse41_ptestnzc:{
6851 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6852 case Intrinsic::x86_sse41_ptestz:
6854 X86CC = X86::COND_E;
6856 case Intrinsic::x86_sse41_ptestc:
6858 X86CC = X86::COND_B;
6860 case Intrinsic::x86_sse41_ptestnzc:
6862 X86CC = X86::COND_A;
6866 SDValue LHS = Op.getOperand(1);
6867 SDValue RHS = Op.getOperand(2);
6868 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6869 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6870 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6871 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6874 // Fix vector shift instructions where the last operand is a non-immediate
6876 case Intrinsic::x86_sse2_pslli_w:
6877 case Intrinsic::x86_sse2_pslli_d:
6878 case Intrinsic::x86_sse2_pslli_q:
6879 case Intrinsic::x86_sse2_psrli_w:
6880 case Intrinsic::x86_sse2_psrli_d:
6881 case Intrinsic::x86_sse2_psrli_q:
6882 case Intrinsic::x86_sse2_psrai_w:
6883 case Intrinsic::x86_sse2_psrai_d:
6884 case Intrinsic::x86_mmx_pslli_w:
6885 case Intrinsic::x86_mmx_pslli_d:
6886 case Intrinsic::x86_mmx_pslli_q:
6887 case Intrinsic::x86_mmx_psrli_w:
6888 case Intrinsic::x86_mmx_psrli_d:
6889 case Intrinsic::x86_mmx_psrli_q:
6890 case Intrinsic::x86_mmx_psrai_w:
6891 case Intrinsic::x86_mmx_psrai_d: {
6892 SDValue ShAmt = Op.getOperand(2);
6893 if (isa<ConstantSDNode>(ShAmt))
6896 unsigned NewIntNo = 0;
6897 EVT ShAmtVT = MVT::v4i32;
6899 case Intrinsic::x86_sse2_pslli_w:
6900 NewIntNo = Intrinsic::x86_sse2_psll_w;
6902 case Intrinsic::x86_sse2_pslli_d:
6903 NewIntNo = Intrinsic::x86_sse2_psll_d;
6905 case Intrinsic::x86_sse2_pslli_q:
6906 NewIntNo = Intrinsic::x86_sse2_psll_q;
6908 case Intrinsic::x86_sse2_psrli_w:
6909 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6911 case Intrinsic::x86_sse2_psrli_d:
6912 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6914 case Intrinsic::x86_sse2_psrli_q:
6915 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6917 case Intrinsic::x86_sse2_psrai_w:
6918 NewIntNo = Intrinsic::x86_sse2_psra_w;
6920 case Intrinsic::x86_sse2_psrai_d:
6921 NewIntNo = Intrinsic::x86_sse2_psra_d;
6924 ShAmtVT = MVT::v2i32;
6926 case Intrinsic::x86_mmx_pslli_w:
6927 NewIntNo = Intrinsic::x86_mmx_psll_w;
6929 case Intrinsic::x86_mmx_pslli_d:
6930 NewIntNo = Intrinsic::x86_mmx_psll_d;
6932 case Intrinsic::x86_mmx_pslli_q:
6933 NewIntNo = Intrinsic::x86_mmx_psll_q;
6935 case Intrinsic::x86_mmx_psrli_w:
6936 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6938 case Intrinsic::x86_mmx_psrli_d:
6939 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6941 case Intrinsic::x86_mmx_psrli_q:
6942 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6944 case Intrinsic::x86_mmx_psrai_w:
6945 NewIntNo = Intrinsic::x86_mmx_psra_w;
6947 case Intrinsic::x86_mmx_psrai_d:
6948 NewIntNo = Intrinsic::x86_mmx_psra_d;
6950 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6956 // The vector shift intrinsics with scalars uses 32b shift amounts but
6957 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6961 ShOps[1] = DAG.getConstant(0, MVT::i32);
6962 if (ShAmtVT == MVT::v4i32) {
6963 ShOps[2] = DAG.getUNDEF(MVT::i32);
6964 ShOps[3] = DAG.getUNDEF(MVT::i32);
6965 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6967 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6970 EVT VT = Op.getValueType();
6971 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6972 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6973 DAG.getConstant(NewIntNo, MVT::i32),
6974 Op.getOperand(1), ShAmt);
6979 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6980 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6981 DebugLoc dl = Op.getDebugLoc();
6984 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6986 DAG.getConstant(TD->getPointerSize(),
6987 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6988 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6989 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6991 NULL, 0, false, false, 0);
6994 // Just load the return address.
6995 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6996 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6997 RetAddrFI, NULL, 0, false, false, 0);
7000 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
7001 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7002 MFI->setFrameAddressIsTaken(true);
7003 EVT VT = Op.getValueType();
7004 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7005 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7006 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7007 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7009 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7014 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7015 SelectionDAG &DAG) {
7016 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7019 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
7021 MachineFunction &MF = DAG.getMachineFunction();
7022 SDValue Chain = Op.getOperand(0);
7023 SDValue Offset = Op.getOperand(1);
7024 SDValue Handler = Op.getOperand(2);
7025 DebugLoc dl = Op.getDebugLoc();
7027 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7029 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7031 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7032 DAG.getIntPtrConstant(-TD->getPointerSize()));
7033 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7034 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7035 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7036 MF.getRegInfo().addLiveOut(StoreAddrReg);
7038 return DAG.getNode(X86ISD::EH_RETURN, dl,
7040 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7043 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7044 SelectionDAG &DAG) {
7045 SDValue Root = Op.getOperand(0);
7046 SDValue Trmp = Op.getOperand(1); // trampoline
7047 SDValue FPtr = Op.getOperand(2); // nested function
7048 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7049 DebugLoc dl = Op.getDebugLoc();
7051 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7053 if (Subtarget->is64Bit()) {
7054 SDValue OutChains[6];
7056 // Large code-model.
7057 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7058 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7060 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7061 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7063 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7065 // Load the pointer to the nested function into R11.
7066 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7067 SDValue Addr = Trmp;
7068 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7069 Addr, TrmpAddr, 0, false, false, 0);
7071 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7072 DAG.getConstant(2, MVT::i64));
7073 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7076 // Load the 'nest' parameter value into R10.
7077 // R10 is specified in X86CallingConv.td
7078 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7079 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7080 DAG.getConstant(10, MVT::i64));
7081 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7082 Addr, TrmpAddr, 10, false, false, 0);
7084 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7085 DAG.getConstant(12, MVT::i64));
7086 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7089 // Jump to the nested function.
7090 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7091 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7092 DAG.getConstant(20, MVT::i64));
7093 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7094 Addr, TrmpAddr, 20, false, false, 0);
7096 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7097 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7098 DAG.getConstant(22, MVT::i64));
7099 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7100 TrmpAddr, 22, false, false, 0);
7103 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7104 return DAG.getMergeValues(Ops, 2, dl);
7106 const Function *Func =
7107 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7108 CallingConv::ID CC = Func->getCallingConv();
7113 llvm_unreachable("Unsupported calling convention");
7114 case CallingConv::C:
7115 case CallingConv::X86_StdCall: {
7116 // Pass 'nest' parameter in ECX.
7117 // Must be kept in sync with X86CallingConv.td
7120 // Check that ECX wasn't needed by an 'inreg' parameter.
7121 const FunctionType *FTy = Func->getFunctionType();
7122 const AttrListPtr &Attrs = Func->getAttributes();
7124 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7125 unsigned InRegCount = 0;
7128 for (FunctionType::param_iterator I = FTy->param_begin(),
7129 E = FTy->param_end(); I != E; ++I, ++Idx)
7130 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7131 // FIXME: should only count parameters that are lowered to integers.
7132 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7134 if (InRegCount > 2) {
7135 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
7140 case CallingConv::X86_FastCall:
7141 case CallingConv::Fast:
7142 // Pass 'nest' parameter in EAX.
7143 // Must be kept in sync with X86CallingConv.td
7148 SDValue OutChains[4];
7151 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7152 DAG.getConstant(10, MVT::i32));
7153 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7155 // This is storing the opcode for MOV32ri.
7156 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7157 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7158 OutChains[0] = DAG.getStore(Root, dl,
7159 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7160 Trmp, TrmpAddr, 0, false, false, 0);
7162 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7163 DAG.getConstant(1, MVT::i32));
7164 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7167 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7168 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7169 DAG.getConstant(5, MVT::i32));
7170 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7171 TrmpAddr, 5, false, false, 1);
7173 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7174 DAG.getConstant(6, MVT::i32));
7175 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7179 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7180 return DAG.getMergeValues(Ops, 2, dl);
7184 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
7186 The rounding mode is in bits 11:10 of FPSR, and has the following
7193 FLT_ROUNDS, on the other hand, expects the following:
7200 To perform the conversion, we do:
7201 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7204 MachineFunction &MF = DAG.getMachineFunction();
7205 const TargetMachine &TM = MF.getTarget();
7206 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7207 unsigned StackAlignment = TFI.getStackAlignment();
7208 EVT VT = Op.getValueType();
7209 DebugLoc dl = Op.getDebugLoc();
7211 // Save FP Control Word to stack slot
7212 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7213 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7215 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7216 DAG.getEntryNode(), StackSlot);
7218 // Load FP Control Word from stack slot
7219 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7222 // Transform as necessary
7224 DAG.getNode(ISD::SRL, dl, MVT::i16,
7225 DAG.getNode(ISD::AND, dl, MVT::i16,
7226 CWD, DAG.getConstant(0x800, MVT::i16)),
7227 DAG.getConstant(11, MVT::i8));
7229 DAG.getNode(ISD::SRL, dl, MVT::i16,
7230 DAG.getNode(ISD::AND, dl, MVT::i16,
7231 CWD, DAG.getConstant(0x400, MVT::i16)),
7232 DAG.getConstant(9, MVT::i8));
7235 DAG.getNode(ISD::AND, dl, MVT::i16,
7236 DAG.getNode(ISD::ADD, dl, MVT::i16,
7237 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7238 DAG.getConstant(1, MVT::i16)),
7239 DAG.getConstant(3, MVT::i16));
7242 return DAG.getNode((VT.getSizeInBits() < 16 ?
7243 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7246 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
7247 EVT VT = Op.getValueType();
7249 unsigned NumBits = VT.getSizeInBits();
7250 DebugLoc dl = Op.getDebugLoc();
7252 Op = Op.getOperand(0);
7253 if (VT == MVT::i8) {
7254 // Zero extend to i32 since there is not an i8 bsr.
7256 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7259 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7260 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7261 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7263 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7266 DAG.getConstant(NumBits+NumBits-1, OpVT),
7267 DAG.getConstant(X86::COND_E, MVT::i8),
7270 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7272 // Finally xor with NumBits-1.
7273 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7276 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7280 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
7281 EVT VT = Op.getValueType();
7283 unsigned NumBits = VT.getSizeInBits();
7284 DebugLoc dl = Op.getDebugLoc();
7286 Op = Op.getOperand(0);
7287 if (VT == MVT::i8) {
7289 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7292 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7293 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7294 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7296 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7299 DAG.getConstant(NumBits, OpVT),
7300 DAG.getConstant(X86::COND_E, MVT::i8),
7303 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7306 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7310 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7311 EVT VT = Op.getValueType();
7312 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7313 DebugLoc dl = Op.getDebugLoc();
7315 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7316 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7317 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7318 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7319 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7321 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7322 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7323 // return AloBlo + AloBhi + AhiBlo;
7325 SDValue A = Op.getOperand(0);
7326 SDValue B = Op.getOperand(1);
7328 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7329 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7330 A, DAG.getConstant(32, MVT::i32));
7331 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7332 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7333 B, DAG.getConstant(32, MVT::i32));
7334 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7335 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7337 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7338 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7340 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7341 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7343 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7344 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7345 AloBhi, DAG.getConstant(32, MVT::i32));
7346 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7347 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7348 AhiBlo, DAG.getConstant(32, MVT::i32));
7349 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7350 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7355 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7356 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7357 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7358 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7359 // has only one use.
7360 SDNode *N = Op.getNode();
7361 SDValue LHS = N->getOperand(0);
7362 SDValue RHS = N->getOperand(1);
7363 unsigned BaseOp = 0;
7365 DebugLoc dl = Op.getDebugLoc();
7367 switch (Op.getOpcode()) {
7368 default: llvm_unreachable("Unknown ovf instruction!");
7370 // A subtract of one will be selected as a INC. Note that INC doesn't
7371 // set CF, so we can't do this for UADDO.
7372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7373 if (C->getAPIntValue() == 1) {
7374 BaseOp = X86ISD::INC;
7378 BaseOp = X86ISD::ADD;
7382 BaseOp = X86ISD::ADD;
7386 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7387 // set CF, so we can't do this for USUBO.
7388 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7389 if (C->getAPIntValue() == 1) {
7390 BaseOp = X86ISD::DEC;
7394 BaseOp = X86ISD::SUB;
7398 BaseOp = X86ISD::SUB;
7402 BaseOp = X86ISD::SMUL;
7406 BaseOp = X86ISD::UMUL;
7411 // Also sets EFLAGS.
7412 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7413 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7416 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7417 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7419 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7423 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7424 EVT T = Op.getValueType();
7425 DebugLoc dl = Op.getDebugLoc();
7428 switch(T.getSimpleVT().SimpleTy) {
7430 assert(false && "Invalid value type!");
7431 case MVT::i8: Reg = X86::AL; size = 1; break;
7432 case MVT::i16: Reg = X86::AX; size = 2; break;
7433 case MVT::i32: Reg = X86::EAX; size = 4; break;
7435 assert(Subtarget->is64Bit() && "Node not type legal!");
7436 Reg = X86::RAX; size = 8;
7439 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7440 Op.getOperand(2), SDValue());
7441 SDValue Ops[] = { cpIn.getValue(0),
7444 DAG.getTargetConstant(size, MVT::i8),
7446 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7447 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7449 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7453 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7454 SelectionDAG &DAG) {
7455 assert(Subtarget->is64Bit() && "Result not type legalized?");
7456 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7457 SDValue TheChain = Op.getOperand(0);
7458 DebugLoc dl = Op.getDebugLoc();
7459 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7460 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7461 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7463 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7464 DAG.getConstant(32, MVT::i8));
7466 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7469 return DAG.getMergeValues(Ops, 2, dl);
7472 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7473 SDNode *Node = Op.getNode();
7474 DebugLoc dl = Node->getDebugLoc();
7475 EVT T = Node->getValueType(0);
7476 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7477 DAG.getConstant(0, T), Node->getOperand(2));
7478 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7479 cast<AtomicSDNode>(Node)->getMemoryVT(),
7480 Node->getOperand(0),
7481 Node->getOperand(1), negOp,
7482 cast<AtomicSDNode>(Node)->getSrcValue(),
7483 cast<AtomicSDNode>(Node)->getAlignment());
7486 /// LowerOperation - Provide custom lowering hooks for some operations.
7488 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7489 switch (Op.getOpcode()) {
7490 default: llvm_unreachable("Should not custom lower this!");
7491 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7492 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7493 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7494 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7495 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7496 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7497 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7498 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7499 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7500 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7501 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7502 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7503 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7504 case ISD::SHL_PARTS:
7505 case ISD::SRA_PARTS:
7506 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7507 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7508 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7509 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7510 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7511 case ISD::FABS: return LowerFABS(Op, DAG);
7512 case ISD::FNEG: return LowerFNEG(Op, DAG);
7513 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7514 case ISD::SETCC: return LowerSETCC(Op, DAG);
7515 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7516 case ISD::SELECT: return LowerSELECT(Op, DAG);
7517 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7518 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7519 case ISD::VASTART: return LowerVASTART(Op, DAG);
7520 case ISD::VAARG: return LowerVAARG(Op, DAG);
7521 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7522 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7523 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7524 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7525 case ISD::FRAME_TO_ARGS_OFFSET:
7526 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7527 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7528 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7529 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7530 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7531 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7532 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7533 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7539 case ISD::UMULO: return LowerXALUO(Op, DAG);
7540 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7544 void X86TargetLowering::
7545 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7546 SelectionDAG &DAG, unsigned NewOp) {
7547 EVT T = Node->getValueType(0);
7548 DebugLoc dl = Node->getDebugLoc();
7549 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7551 SDValue Chain = Node->getOperand(0);
7552 SDValue In1 = Node->getOperand(1);
7553 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7554 Node->getOperand(2), DAG.getIntPtrConstant(0));
7555 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7556 Node->getOperand(2), DAG.getIntPtrConstant(1));
7557 SDValue Ops[] = { Chain, In1, In2L, In2H };
7558 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7560 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7561 cast<MemSDNode>(Node)->getMemOperand());
7562 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7563 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7564 Results.push_back(Result.getValue(2));
7567 /// ReplaceNodeResults - Replace a node with an illegal result type
7568 /// with a new node built out of custom code.
7569 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7570 SmallVectorImpl<SDValue>&Results,
7571 SelectionDAG &DAG) {
7572 DebugLoc dl = N->getDebugLoc();
7573 switch (N->getOpcode()) {
7575 assert(false && "Do not know how to custom type legalize this operation!");
7577 case ISD::FP_TO_SINT: {
7578 std::pair<SDValue,SDValue> Vals =
7579 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7580 SDValue FIST = Vals.first, StackSlot = Vals.second;
7581 if (FIST.getNode() != 0) {
7582 EVT VT = N->getValueType(0);
7583 // Return a load from the stack slot.
7584 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7589 case ISD::READCYCLECOUNTER: {
7590 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7591 SDValue TheChain = N->getOperand(0);
7592 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7593 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7595 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7597 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7598 SDValue Ops[] = { eax, edx };
7599 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7600 Results.push_back(edx.getValue(1));
7603 case ISD::ATOMIC_CMP_SWAP: {
7604 EVT T = N->getValueType(0);
7605 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7606 SDValue cpInL, cpInH;
7607 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7608 DAG.getConstant(0, MVT::i32));
7609 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7610 DAG.getConstant(1, MVT::i32));
7611 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7612 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7614 SDValue swapInL, swapInH;
7615 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7616 DAG.getConstant(0, MVT::i32));
7617 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7618 DAG.getConstant(1, MVT::i32));
7619 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7621 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7622 swapInL.getValue(1));
7623 SDValue Ops[] = { swapInH.getValue(0),
7625 swapInH.getValue(1) };
7626 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7627 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7628 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7629 MVT::i32, Result.getValue(1));
7630 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7631 MVT::i32, cpOutL.getValue(2));
7632 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7633 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7634 Results.push_back(cpOutH.getValue(1));
7637 case ISD::ATOMIC_LOAD_ADD:
7638 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7640 case ISD::ATOMIC_LOAD_AND:
7641 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7643 case ISD::ATOMIC_LOAD_NAND:
7644 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7646 case ISD::ATOMIC_LOAD_OR:
7647 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7649 case ISD::ATOMIC_LOAD_SUB:
7650 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7652 case ISD::ATOMIC_LOAD_XOR:
7653 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7655 case ISD::ATOMIC_SWAP:
7656 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7661 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7663 default: return NULL;
7664 case X86ISD::BSF: return "X86ISD::BSF";
7665 case X86ISD::BSR: return "X86ISD::BSR";
7666 case X86ISD::SHLD: return "X86ISD::SHLD";
7667 case X86ISD::SHRD: return "X86ISD::SHRD";
7668 case X86ISD::FAND: return "X86ISD::FAND";
7669 case X86ISD::FOR: return "X86ISD::FOR";
7670 case X86ISD::FXOR: return "X86ISD::FXOR";
7671 case X86ISD::FSRL: return "X86ISD::FSRL";
7672 case X86ISD::FILD: return "X86ISD::FILD";
7673 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7674 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7675 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7676 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7677 case X86ISD::FLD: return "X86ISD::FLD";
7678 case X86ISD::FST: return "X86ISD::FST";
7679 case X86ISD::CALL: return "X86ISD::CALL";
7680 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7681 case X86ISD::BT: return "X86ISD::BT";
7682 case X86ISD::CMP: return "X86ISD::CMP";
7683 case X86ISD::COMI: return "X86ISD::COMI";
7684 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7685 case X86ISD::SETCC: return "X86ISD::SETCC";
7686 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7687 case X86ISD::CMOV: return "X86ISD::CMOV";
7688 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7689 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7690 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7691 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7692 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7693 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7694 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7695 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7696 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7697 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7698 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7699 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7700 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7701 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7702 case X86ISD::FMAX: return "X86ISD::FMAX";
7703 case X86ISD::FMIN: return "X86ISD::FMIN";
7704 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7705 case X86ISD::FRCP: return "X86ISD::FRCP";
7706 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7707 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7708 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7709 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7710 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7711 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7712 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7713 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7714 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7715 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7716 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7717 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7718 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7719 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7720 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7721 case X86ISD::VSHL: return "X86ISD::VSHL";
7722 case X86ISD::VSRL: return "X86ISD::VSRL";
7723 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7724 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7725 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7726 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7727 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7728 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7729 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7730 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7731 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7732 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7733 case X86ISD::ADD: return "X86ISD::ADD";
7734 case X86ISD::SUB: return "X86ISD::SUB";
7735 case X86ISD::SMUL: return "X86ISD::SMUL";
7736 case X86ISD::UMUL: return "X86ISD::UMUL";
7737 case X86ISD::INC: return "X86ISD::INC";
7738 case X86ISD::DEC: return "X86ISD::DEC";
7739 case X86ISD::OR: return "X86ISD::OR";
7740 case X86ISD::XOR: return "X86ISD::XOR";
7741 case X86ISD::AND: return "X86ISD::AND";
7742 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7743 case X86ISD::PTEST: return "X86ISD::PTEST";
7744 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7745 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7749 // isLegalAddressingMode - Return true if the addressing mode represented
7750 // by AM is legal for this target, for a load/store of the specified type.
7751 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7752 const Type *Ty) const {
7753 // X86 supports extremely general addressing modes.
7754 CodeModel::Model M = getTargetMachine().getCodeModel();
7756 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7757 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7762 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7764 // If a reference to this global requires an extra load, we can't fold it.
7765 if (isGlobalStubReference(GVFlags))
7768 // If BaseGV requires a register for the PIC base, we cannot also have a
7769 // BaseReg specified.
7770 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7773 // If lower 4G is not available, then we must use rip-relative addressing.
7774 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7784 // These scales always work.
7789 // These scales are formed with basereg+scalereg. Only accept if there is
7794 default: // Other stuff never works.
7802 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7803 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7805 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7806 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7807 if (NumBits1 <= NumBits2)
7812 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7813 if (!VT1.isInteger() || !VT2.isInteger())
7815 unsigned NumBits1 = VT1.getSizeInBits();
7816 unsigned NumBits2 = VT2.getSizeInBits();
7817 if (NumBits1 <= NumBits2)
7822 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7823 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7824 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
7827 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7828 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7829 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7832 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7833 // i16 instructions are longer (0x66 prefix) and potentially slower.
7834 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7837 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7838 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7839 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7840 /// are assumed to be legal.
7842 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7844 // Only do shuffles on 128-bit vector types for now.
7845 if (VT.getSizeInBits() == 64)
7848 // FIXME: pshufb, blends, shifts.
7849 return (VT.getVectorNumElements() == 2 ||
7850 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7851 isMOVLMask(M, VT) ||
7852 isSHUFPMask(M, VT) ||
7853 isPSHUFDMask(M, VT) ||
7854 isPSHUFHWMask(M, VT) ||
7855 isPSHUFLWMask(M, VT) ||
7856 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7857 isUNPCKLMask(M, VT) ||
7858 isUNPCKHMask(M, VT) ||
7859 isUNPCKL_v_undef_Mask(M, VT) ||
7860 isUNPCKH_v_undef_Mask(M, VT));
7864 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7866 unsigned NumElts = VT.getVectorNumElements();
7867 // FIXME: This collection of masks seems suspect.
7870 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7871 return (isMOVLMask(Mask, VT) ||
7872 isCommutedMOVLMask(Mask, VT, true) ||
7873 isSHUFPMask(Mask, VT) ||
7874 isCommutedSHUFPMask(Mask, VT));
7879 //===----------------------------------------------------------------------===//
7880 // X86 Scheduler Hooks
7881 //===----------------------------------------------------------------------===//
7883 // private utility function
7885 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7886 MachineBasicBlock *MBB,
7894 TargetRegisterClass *RC,
7895 bool invSrc) const {
7896 // For the atomic bitwise operator, we generate
7899 // ld t1 = [bitinstr.addr]
7900 // op t2 = t1, [bitinstr.val]
7902 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7904 // fallthrough -->nextMBB
7905 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7906 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7907 MachineFunction::iterator MBBIter = MBB;
7910 /// First build the CFG
7911 MachineFunction *F = MBB->getParent();
7912 MachineBasicBlock *thisMBB = MBB;
7913 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7914 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7915 F->insert(MBBIter, newMBB);
7916 F->insert(MBBIter, nextMBB);
7918 // Move all successors to thisMBB to nextMBB
7919 nextMBB->transferSuccessors(thisMBB);
7921 // Update thisMBB to fall through to newMBB
7922 thisMBB->addSuccessor(newMBB);
7924 // newMBB jumps to itself and fall through to nextMBB
7925 newMBB->addSuccessor(nextMBB);
7926 newMBB->addSuccessor(newMBB);
7928 // Insert instructions into newMBB based on incoming instruction
7929 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7930 "unexpected number of operands");
7931 DebugLoc dl = bInstr->getDebugLoc();
7932 MachineOperand& destOper = bInstr->getOperand(0);
7933 MachineOperand* argOpers[2 + X86AddrNumOperands];
7934 int numArgs = bInstr->getNumOperands() - 1;
7935 for (int i=0; i < numArgs; ++i)
7936 argOpers[i] = &bInstr->getOperand(i+1);
7938 // x86 address has 4 operands: base, index, scale, and displacement
7939 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7940 int valArgIndx = lastAddrIndx + 1;
7942 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7943 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7944 for (int i=0; i <= lastAddrIndx; ++i)
7945 (*MIB).addOperand(*argOpers[i]);
7947 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7949 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7954 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7955 assert((argOpers[valArgIndx]->isReg() ||
7956 argOpers[valArgIndx]->isImm()) &&
7958 if (argOpers[valArgIndx]->isReg())
7959 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7961 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7963 (*MIB).addOperand(*argOpers[valArgIndx]);
7965 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7968 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7969 for (int i=0; i <= lastAddrIndx; ++i)
7970 (*MIB).addOperand(*argOpers[i]);
7972 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7973 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7974 bInstr->memoperands_end());
7976 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7980 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
7982 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7986 // private utility function: 64 bit atomics on 32 bit host.
7988 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7989 MachineBasicBlock *MBB,
7994 bool invSrc) const {
7995 // For the atomic bitwise operator, we generate
7996 // thisMBB (instructions are in pairs, except cmpxchg8b)
7997 // ld t1,t2 = [bitinstr.addr]
7999 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8000 // op t5, t6 <- out1, out2, [bitinstr.val]
8001 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8002 // mov ECX, EBX <- t5, t6
8003 // mov EAX, EDX <- t1, t2
8004 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8005 // mov t3, t4 <- EAX, EDX
8007 // result in out1, out2
8008 // fallthrough -->nextMBB
8010 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8011 const unsigned LoadOpc = X86::MOV32rm;
8012 const unsigned copyOpc = X86::MOV32rr;
8013 const unsigned NotOpc = X86::NOT32r;
8014 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8015 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8016 MachineFunction::iterator MBBIter = MBB;
8019 /// First build the CFG
8020 MachineFunction *F = MBB->getParent();
8021 MachineBasicBlock *thisMBB = MBB;
8022 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8023 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8024 F->insert(MBBIter, newMBB);
8025 F->insert(MBBIter, nextMBB);
8027 // Move all successors to thisMBB to nextMBB
8028 nextMBB->transferSuccessors(thisMBB);
8030 // Update thisMBB to fall through to newMBB
8031 thisMBB->addSuccessor(newMBB);
8033 // newMBB jumps to itself and fall through to nextMBB
8034 newMBB->addSuccessor(nextMBB);
8035 newMBB->addSuccessor(newMBB);
8037 DebugLoc dl = bInstr->getDebugLoc();
8038 // Insert instructions into newMBB based on incoming instruction
8039 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8040 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
8041 "unexpected number of operands");
8042 MachineOperand& dest1Oper = bInstr->getOperand(0);
8043 MachineOperand& dest2Oper = bInstr->getOperand(1);
8044 MachineOperand* argOpers[2 + X86AddrNumOperands];
8045 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
8046 argOpers[i] = &bInstr->getOperand(i+2);
8048 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8049 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8051 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8052 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8053 for (int i=0; i <= lastAddrIndx; ++i)
8054 (*MIB).addOperand(*argOpers[i]);
8055 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8056 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8057 // add 4 to displacement.
8058 for (int i=0; i <= lastAddrIndx-2; ++i)
8059 (*MIB).addOperand(*argOpers[i]);
8060 MachineOperand newOp3 = *(argOpers[3]);
8062 newOp3.setImm(newOp3.getImm()+4);
8064 newOp3.setOffset(newOp3.getOffset()+4);
8065 (*MIB).addOperand(newOp3);
8066 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8068 // t3/4 are defined later, at the bottom of the loop
8069 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8070 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8071 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8072 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8073 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8074 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8076 // The subsequent operations should be using the destination registers of
8077 //the PHI instructions.
8079 t1 = F->getRegInfo().createVirtualRegister(RC);
8080 t2 = F->getRegInfo().createVirtualRegister(RC);
8081 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8082 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8084 t1 = dest1Oper.getReg();
8085 t2 = dest2Oper.getReg();
8088 int valArgIndx = lastAddrIndx + 1;
8089 assert((argOpers[valArgIndx]->isReg() ||
8090 argOpers[valArgIndx]->isImm()) &&
8092 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8093 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8094 if (argOpers[valArgIndx]->isReg())
8095 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8097 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8098 if (regOpcL != X86::MOV32rr)
8100 (*MIB).addOperand(*argOpers[valArgIndx]);
8101 assert(argOpers[valArgIndx + 1]->isReg() ==
8102 argOpers[valArgIndx]->isReg());
8103 assert(argOpers[valArgIndx + 1]->isImm() ==
8104 argOpers[valArgIndx]->isImm());
8105 if (argOpers[valArgIndx + 1]->isReg())
8106 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8108 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8109 if (regOpcH != X86::MOV32rr)
8111 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8113 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8115 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8118 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8120 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8123 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8124 for (int i=0; i <= lastAddrIndx; ++i)
8125 (*MIB).addOperand(*argOpers[i]);
8127 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8128 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8129 bInstr->memoperands_end());
8131 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8132 MIB.addReg(X86::EAX);
8133 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8134 MIB.addReg(X86::EDX);
8137 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8139 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8143 // private utility function
8145 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8146 MachineBasicBlock *MBB,
8147 unsigned cmovOpc) const {
8148 // For the atomic min/max operator, we generate
8151 // ld t1 = [min/max.addr]
8152 // mov t2 = [min/max.val]
8154 // cmov[cond] t2 = t1
8156 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8158 // fallthrough -->nextMBB
8160 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8161 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8162 MachineFunction::iterator MBBIter = MBB;
8165 /// First build the CFG
8166 MachineFunction *F = MBB->getParent();
8167 MachineBasicBlock *thisMBB = MBB;
8168 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8169 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8170 F->insert(MBBIter, newMBB);
8171 F->insert(MBBIter, nextMBB);
8173 // Move all successors of thisMBB to nextMBB
8174 nextMBB->transferSuccessors(thisMBB);
8176 // Update thisMBB to fall through to newMBB
8177 thisMBB->addSuccessor(newMBB);
8179 // newMBB jumps to newMBB and fall through to nextMBB
8180 newMBB->addSuccessor(nextMBB);
8181 newMBB->addSuccessor(newMBB);
8183 DebugLoc dl = mInstr->getDebugLoc();
8184 // Insert instructions into newMBB based on incoming instruction
8185 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8186 "unexpected number of operands");
8187 MachineOperand& destOper = mInstr->getOperand(0);
8188 MachineOperand* argOpers[2 + X86AddrNumOperands];
8189 int numArgs = mInstr->getNumOperands() - 1;
8190 for (int i=0; i < numArgs; ++i)
8191 argOpers[i] = &mInstr->getOperand(i+1);
8193 // x86 address has 4 operands: base, index, scale, and displacement
8194 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8195 int valArgIndx = lastAddrIndx + 1;
8197 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8198 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8199 for (int i=0; i <= lastAddrIndx; ++i)
8200 (*MIB).addOperand(*argOpers[i]);
8202 // We only support register and immediate values
8203 assert((argOpers[valArgIndx]->isReg() ||
8204 argOpers[valArgIndx]->isImm()) &&
8207 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8208 if (argOpers[valArgIndx]->isReg())
8209 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8211 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8212 (*MIB).addOperand(*argOpers[valArgIndx]);
8214 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8217 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8222 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8223 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8227 // Cmp and exchange if none has modified the memory location
8228 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8229 for (int i=0; i <= lastAddrIndx; ++i)
8230 (*MIB).addOperand(*argOpers[i]);
8232 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8233 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8234 mInstr->memoperands_end());
8236 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8237 MIB.addReg(X86::EAX);
8240 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8242 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
8246 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8247 // all of this code can be replaced with that in the .td file.
8249 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8250 unsigned numArgs, bool memArg) const {
8252 MachineFunction *F = BB->getParent();
8253 DebugLoc dl = MI->getDebugLoc();
8254 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8258 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8260 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8262 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8264 for (unsigned i = 0; i < numArgs; ++i) {
8265 MachineOperand &Op = MI->getOperand(i+1);
8267 if (!(Op.isReg() && Op.isImplicit()))
8271 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8274 F->DeleteMachineInstr(MI);
8280 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8282 MachineBasicBlock *MBB) const {
8283 // Emit code to save XMM registers to the stack. The ABI says that the
8284 // number of registers to save is given in %al, so it's theoretically
8285 // possible to do an indirect jump trick to avoid saving all of them,
8286 // however this code takes a simpler approach and just executes all
8287 // of the stores if %al is non-zero. It's less code, and it's probably
8288 // easier on the hardware branch predictor, and stores aren't all that
8289 // expensive anyway.
8291 // Create the new basic blocks. One block contains all the XMM stores,
8292 // and one block is the final destination regardless of whether any
8293 // stores were performed.
8294 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8295 MachineFunction *F = MBB->getParent();
8296 MachineFunction::iterator MBBIter = MBB;
8298 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8299 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8300 F->insert(MBBIter, XMMSaveMBB);
8301 F->insert(MBBIter, EndMBB);
8304 // Move any original successors of MBB to the end block.
8305 EndMBB->transferSuccessors(MBB);
8306 // The original block will now fall through to the XMM save block.
8307 MBB->addSuccessor(XMMSaveMBB);
8308 // The XMMSaveMBB will fall through to the end block.
8309 XMMSaveMBB->addSuccessor(EndMBB);
8311 // Now add the instructions.
8312 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8313 DebugLoc DL = MI->getDebugLoc();
8315 unsigned CountReg = MI->getOperand(0).getReg();
8316 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8317 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8319 if (!Subtarget->isTargetWin64()) {
8320 // If %al is 0, branch around the XMM save block.
8321 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8322 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8323 MBB->addSuccessor(EndMBB);
8326 // In the XMM save block, save all the XMM argument registers.
8327 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8328 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8329 MachineMemOperand *MMO =
8330 F->getMachineMemOperand(
8331 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8332 MachineMemOperand::MOStore, Offset,
8333 /*Size=*/16, /*Align=*/16);
8334 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8335 .addFrameIndex(RegSaveFrameIndex)
8336 .addImm(/*Scale=*/1)
8337 .addReg(/*IndexReg=*/0)
8338 .addImm(/*Disp=*/Offset)
8339 .addReg(/*Segment=*/0)
8340 .addReg(MI->getOperand(i).getReg())
8341 .addMemOperand(MMO);
8344 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8350 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8351 MachineBasicBlock *BB,
8352 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8353 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8354 DebugLoc DL = MI->getDebugLoc();
8356 // To "insert" a SELECT_CC instruction, we actually have to insert the
8357 // diamond control-flow pattern. The incoming instruction knows the
8358 // destination vreg to set, the condition code register to branch on, the
8359 // true/false values to select between, and a branch opcode to use.
8360 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8361 MachineFunction::iterator It = BB;
8367 // cmpTY ccX, r1, r2
8369 // fallthrough --> copy0MBB
8370 MachineBasicBlock *thisMBB = BB;
8371 MachineFunction *F = BB->getParent();
8372 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8373 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8375 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8376 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8377 F->insert(It, copy0MBB);
8378 F->insert(It, sinkMBB);
8379 // Update machine-CFG edges by first adding all successors of the current
8380 // block to the new block which will contain the Phi node for the select.
8381 // Also inform sdisel of the edge changes.
8382 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8383 E = BB->succ_end(); I != E; ++I) {
8384 EM->insert(std::make_pair(*I, sinkMBB));
8385 sinkMBB->addSuccessor(*I);
8387 // Next, remove all successors of the current block, and add the true
8388 // and fallthrough blocks as its successors.
8389 while (!BB->succ_empty())
8390 BB->removeSuccessor(BB->succ_begin());
8391 // Add the true and fallthrough blocks as its successors.
8392 BB->addSuccessor(copy0MBB);
8393 BB->addSuccessor(sinkMBB);
8396 // %FalseValue = ...
8397 // # fallthrough to sinkMBB
8400 // Update machine-CFG edges
8401 BB->addSuccessor(sinkMBB);
8404 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8407 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8408 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8409 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8411 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8416 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8417 MachineBasicBlock *BB,
8418 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8419 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8420 DebugLoc DL = MI->getDebugLoc();
8421 MachineFunction *F = BB->getParent();
8423 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8424 // non-trivial part is impdef of ESP.
8425 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8428 BuildMI(BB, DL, TII->get(X86::CALLpcrel32))
8429 .addExternalSymbol("_alloca")
8430 .addReg(X86::EAX, RegState::Implicit)
8431 .addReg(X86::ESP, RegState::Implicit)
8432 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8433 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8435 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8440 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8441 MachineBasicBlock *BB,
8442 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8443 switch (MI->getOpcode()) {
8444 default: assert(false && "Unexpected instr type to insert");
8445 case X86::MINGW_ALLOCA:
8446 return EmitLoweredMingwAlloca(MI, BB, EM);
8448 case X86::CMOV_V1I64:
8449 case X86::CMOV_FR32:
8450 case X86::CMOV_FR64:
8451 case X86::CMOV_V4F32:
8452 case X86::CMOV_V2F64:
8453 case X86::CMOV_V2I64:
8454 return EmitLoweredSelect(MI, BB, EM);
8456 case X86::FP32_TO_INT16_IN_MEM:
8457 case X86::FP32_TO_INT32_IN_MEM:
8458 case X86::FP32_TO_INT64_IN_MEM:
8459 case X86::FP64_TO_INT16_IN_MEM:
8460 case X86::FP64_TO_INT32_IN_MEM:
8461 case X86::FP64_TO_INT64_IN_MEM:
8462 case X86::FP80_TO_INT16_IN_MEM:
8463 case X86::FP80_TO_INT32_IN_MEM:
8464 case X86::FP80_TO_INT64_IN_MEM: {
8465 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8466 DebugLoc DL = MI->getDebugLoc();
8468 // Change the floating point control register to use "round towards zero"
8469 // mode when truncating to an integer value.
8470 MachineFunction *F = BB->getParent();
8471 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8472 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8474 // Load the old value of the high byte of the control word...
8476 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8477 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8480 // Set the high part to be round to zero...
8481 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8484 // Reload the modified control word now...
8485 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8487 // Restore the memory image of control word to original value
8488 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8491 // Get the X86 opcode to use.
8493 switch (MI->getOpcode()) {
8494 default: llvm_unreachable("illegal opcode!");
8495 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8496 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8497 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8498 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8499 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8500 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8501 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8502 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8503 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8507 MachineOperand &Op = MI->getOperand(0);
8509 AM.BaseType = X86AddressMode::RegBase;
8510 AM.Base.Reg = Op.getReg();
8512 AM.BaseType = X86AddressMode::FrameIndexBase;
8513 AM.Base.FrameIndex = Op.getIndex();
8515 Op = MI->getOperand(1);
8517 AM.Scale = Op.getImm();
8518 Op = MI->getOperand(2);
8520 AM.IndexReg = Op.getImm();
8521 Op = MI->getOperand(3);
8522 if (Op.isGlobal()) {
8523 AM.GV = Op.getGlobal();
8525 AM.Disp = Op.getImm();
8527 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8528 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8530 // Reload the original control word now.
8531 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8533 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8536 // DBG_VALUE. Only the frame index case is done here.
8537 case X86::DBG_VALUE: {
8538 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8539 DebugLoc DL = MI->getDebugLoc();
8541 MachineFunction *F = BB->getParent();
8542 AM.BaseType = X86AddressMode::FrameIndexBase;
8543 AM.Base.FrameIndex = MI->getOperand(0).getImm();
8544 addFullAddress(BuildMI(BB, DL, TII->get(X86::DBG_VALUE)), AM).
8545 addImm(MI->getOperand(1).getImm()).
8546 addMetadata(MI->getOperand(2).getMetadata());
8547 F->DeleteMachineInstr(MI); // Remove pseudo.
8551 // String/text processing lowering.
8552 case X86::PCMPISTRM128REG:
8553 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8554 case X86::PCMPISTRM128MEM:
8555 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8556 case X86::PCMPESTRM128REG:
8557 return EmitPCMP(MI, BB, 5, false /* in mem */);
8558 case X86::PCMPESTRM128MEM:
8559 return EmitPCMP(MI, BB, 5, true /* in mem */);
8562 case X86::ATOMAND32:
8563 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8564 X86::AND32ri, X86::MOV32rm,
8565 X86::LCMPXCHG32, X86::MOV32rr,
8566 X86::NOT32r, X86::EAX,
8567 X86::GR32RegisterClass);
8569 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8570 X86::OR32ri, X86::MOV32rm,
8571 X86::LCMPXCHG32, X86::MOV32rr,
8572 X86::NOT32r, X86::EAX,
8573 X86::GR32RegisterClass);
8574 case X86::ATOMXOR32:
8575 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8576 X86::XOR32ri, X86::MOV32rm,
8577 X86::LCMPXCHG32, X86::MOV32rr,
8578 X86::NOT32r, X86::EAX,
8579 X86::GR32RegisterClass);
8580 case X86::ATOMNAND32:
8581 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8582 X86::AND32ri, X86::MOV32rm,
8583 X86::LCMPXCHG32, X86::MOV32rr,
8584 X86::NOT32r, X86::EAX,
8585 X86::GR32RegisterClass, true);
8586 case X86::ATOMMIN32:
8587 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8588 case X86::ATOMMAX32:
8589 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8590 case X86::ATOMUMIN32:
8591 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8592 case X86::ATOMUMAX32:
8593 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8595 case X86::ATOMAND16:
8596 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8597 X86::AND16ri, X86::MOV16rm,
8598 X86::LCMPXCHG16, X86::MOV16rr,
8599 X86::NOT16r, X86::AX,
8600 X86::GR16RegisterClass);
8602 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8603 X86::OR16ri, X86::MOV16rm,
8604 X86::LCMPXCHG16, X86::MOV16rr,
8605 X86::NOT16r, X86::AX,
8606 X86::GR16RegisterClass);
8607 case X86::ATOMXOR16:
8608 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8609 X86::XOR16ri, X86::MOV16rm,
8610 X86::LCMPXCHG16, X86::MOV16rr,
8611 X86::NOT16r, X86::AX,
8612 X86::GR16RegisterClass);
8613 case X86::ATOMNAND16:
8614 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8615 X86::AND16ri, X86::MOV16rm,
8616 X86::LCMPXCHG16, X86::MOV16rr,
8617 X86::NOT16r, X86::AX,
8618 X86::GR16RegisterClass, true);
8619 case X86::ATOMMIN16:
8620 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8621 case X86::ATOMMAX16:
8622 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8623 case X86::ATOMUMIN16:
8624 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8625 case X86::ATOMUMAX16:
8626 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8630 X86::AND8ri, X86::MOV8rm,
8631 X86::LCMPXCHG8, X86::MOV8rr,
8632 X86::NOT8r, X86::AL,
8633 X86::GR8RegisterClass);
8635 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8636 X86::OR8ri, X86::MOV8rm,
8637 X86::LCMPXCHG8, X86::MOV8rr,
8638 X86::NOT8r, X86::AL,
8639 X86::GR8RegisterClass);
8641 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8642 X86::XOR8ri, X86::MOV8rm,
8643 X86::LCMPXCHG8, X86::MOV8rr,
8644 X86::NOT8r, X86::AL,
8645 X86::GR8RegisterClass);
8646 case X86::ATOMNAND8:
8647 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8648 X86::AND8ri, X86::MOV8rm,
8649 X86::LCMPXCHG8, X86::MOV8rr,
8650 X86::NOT8r, X86::AL,
8651 X86::GR8RegisterClass, true);
8652 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8653 // This group is for 64-bit host.
8654 case X86::ATOMAND64:
8655 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8656 X86::AND64ri32, X86::MOV64rm,
8657 X86::LCMPXCHG64, X86::MOV64rr,
8658 X86::NOT64r, X86::RAX,
8659 X86::GR64RegisterClass);
8661 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8662 X86::OR64ri32, X86::MOV64rm,
8663 X86::LCMPXCHG64, X86::MOV64rr,
8664 X86::NOT64r, X86::RAX,
8665 X86::GR64RegisterClass);
8666 case X86::ATOMXOR64:
8667 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8668 X86::XOR64ri32, X86::MOV64rm,
8669 X86::LCMPXCHG64, X86::MOV64rr,
8670 X86::NOT64r, X86::RAX,
8671 X86::GR64RegisterClass);
8672 case X86::ATOMNAND64:
8673 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8674 X86::AND64ri32, X86::MOV64rm,
8675 X86::LCMPXCHG64, X86::MOV64rr,
8676 X86::NOT64r, X86::RAX,
8677 X86::GR64RegisterClass, true);
8678 case X86::ATOMMIN64:
8679 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8680 case X86::ATOMMAX64:
8681 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8682 case X86::ATOMUMIN64:
8683 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8684 case X86::ATOMUMAX64:
8685 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8687 // This group does 64-bit operations on a 32-bit host.
8688 case X86::ATOMAND6432:
8689 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8690 X86::AND32rr, X86::AND32rr,
8691 X86::AND32ri, X86::AND32ri,
8693 case X86::ATOMOR6432:
8694 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8695 X86::OR32rr, X86::OR32rr,
8696 X86::OR32ri, X86::OR32ri,
8698 case X86::ATOMXOR6432:
8699 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8700 X86::XOR32rr, X86::XOR32rr,
8701 X86::XOR32ri, X86::XOR32ri,
8703 case X86::ATOMNAND6432:
8704 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8705 X86::AND32rr, X86::AND32rr,
8706 X86::AND32ri, X86::AND32ri,
8708 case X86::ATOMADD6432:
8709 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8710 X86::ADD32rr, X86::ADC32rr,
8711 X86::ADD32ri, X86::ADC32ri,
8713 case X86::ATOMSUB6432:
8714 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8715 X86::SUB32rr, X86::SBB32rr,
8716 X86::SUB32ri, X86::SBB32ri,
8718 case X86::ATOMSWAP6432:
8719 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8720 X86::MOV32rr, X86::MOV32rr,
8721 X86::MOV32ri, X86::MOV32ri,
8723 case X86::VASTART_SAVE_XMM_REGS:
8724 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8728 //===----------------------------------------------------------------------===//
8729 // X86 Optimization Hooks
8730 //===----------------------------------------------------------------------===//
8732 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8736 const SelectionDAG &DAG,
8737 unsigned Depth) const {
8738 unsigned Opc = Op.getOpcode();
8739 assert((Opc >= ISD::BUILTIN_OP_END ||
8740 Opc == ISD::INTRINSIC_WO_CHAIN ||
8741 Opc == ISD::INTRINSIC_W_CHAIN ||
8742 Opc == ISD::INTRINSIC_VOID) &&
8743 "Should use MaskedValueIsZero if you don't know whether Op"
8744 " is a target node!");
8746 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8758 // These nodes' second result is a boolean.
8759 if (Op.getResNo() == 0)
8763 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8764 Mask.getBitWidth() - 1);
8769 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8770 /// node is a GlobalAddress + offset.
8771 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8772 GlobalValue* &GA, int64_t &Offset) const{
8773 if (N->getOpcode() == X86ISD::Wrapper) {
8774 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8775 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8776 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8780 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8783 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8784 EVT EltVT, LoadSDNode *&LDBase,
8785 unsigned &LastLoadedElt,
8786 SelectionDAG &DAG, MachineFrameInfo *MFI,
8787 const TargetLowering &TLI) {
8789 LastLoadedElt = -1U;
8790 for (unsigned i = 0; i < NumElems; ++i) {
8791 if (N->getMaskElt(i) < 0) {
8797 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8798 if (!Elt.getNode() ||
8799 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8802 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8804 LDBase = cast<LoadSDNode>(Elt.getNode());
8808 if (Elt.getOpcode() == ISD::UNDEF)
8811 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8812 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8819 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8820 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8821 /// if the load addresses are consecutive, non-overlapping, and in the right
8822 /// order. In the case of v2i64, it will see if it can rewrite the
8823 /// shuffle to be an appropriate build vector so it can take advantage of
8824 // performBuildVectorCombine.
8825 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8826 const TargetLowering &TLI) {
8827 DebugLoc dl = N->getDebugLoc();
8828 EVT VT = N->getValueType(0);
8829 EVT EltVT = VT.getVectorElementType();
8830 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8831 unsigned NumElems = VT.getVectorNumElements();
8833 if (VT.getSizeInBits() != 128)
8836 // Try to combine a vector_shuffle into a 128-bit load.
8837 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8838 LoadSDNode *LD = NULL;
8839 unsigned LastLoadedElt;
8840 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8844 if (LastLoadedElt == NumElems - 1) {
8845 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8846 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8847 LD->getSrcValue(), LD->getSrcValueOffset(),
8848 LD->isVolatile(), LD->isNonTemporal(), 0);
8849 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8850 LD->getSrcValue(), LD->getSrcValueOffset(),
8851 LD->isVolatile(), LD->isNonTemporal(),
8852 LD->getAlignment());
8853 } else if (NumElems == 4 && LastLoadedElt == 1) {
8854 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8855 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8856 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8857 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8862 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8863 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8864 const X86Subtarget *Subtarget) {
8865 DebugLoc DL = N->getDebugLoc();
8866 SDValue Cond = N->getOperand(0);
8867 // Get the LHS/RHS of the select.
8868 SDValue LHS = N->getOperand(1);
8869 SDValue RHS = N->getOperand(2);
8871 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8872 // instructions match the semantics of the common C idiom x<y?x:y but not
8873 // x<=y?x:y, because of how they handle negative zero (which can be
8874 // ignored in unsafe-math mode).
8875 if (Subtarget->hasSSE2() &&
8876 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8877 Cond.getOpcode() == ISD::SETCC) {
8878 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8880 unsigned Opcode = 0;
8881 // Check for x CC y ? x : y.
8882 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
8883 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
8887 // Converting this to a min would handle NaNs incorrectly, and swapping
8888 // the operands would cause it to handle comparisons between positive
8889 // and negative zero incorrectly.
8890 if (!FiniteOnlyFPMath() &&
8891 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
8892 if (!UnsafeFPMath &&
8893 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8895 std::swap(LHS, RHS);
8897 Opcode = X86ISD::FMIN;
8900 // Converting this to a min would handle comparisons between positive
8901 // and negative zero incorrectly.
8902 if (!UnsafeFPMath &&
8903 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
8905 Opcode = X86ISD::FMIN;
8908 // Converting this to a min would handle both negative zeros and NaNs
8909 // incorrectly, but we can swap the operands to fix both.
8910 std::swap(LHS, RHS);
8914 Opcode = X86ISD::FMIN;
8918 // Converting this to a max would handle comparisons between positive
8919 // and negative zero incorrectly.
8920 if (!UnsafeFPMath &&
8921 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
8923 Opcode = X86ISD::FMAX;
8926 // Converting this to a max would handle NaNs incorrectly, and swapping
8927 // the operands would cause it to handle comparisons between positive
8928 // and negative zero incorrectly.
8929 if (!FiniteOnlyFPMath() &&
8930 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
8931 if (!UnsafeFPMath &&
8932 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8934 std::swap(LHS, RHS);
8936 Opcode = X86ISD::FMAX;
8939 // Converting this to a max would handle both negative zeros and NaNs
8940 // incorrectly, but we can swap the operands to fix both.
8941 std::swap(LHS, RHS);
8945 Opcode = X86ISD::FMAX;
8948 // Check for x CC y ? y : x -- a min/max with reversed arms.
8949 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
8950 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
8954 // Converting this to a min would handle comparisons between positive
8955 // and negative zero incorrectly, and swapping the operands would
8956 // cause it to handle NaNs incorrectly.
8957 if (!UnsafeFPMath &&
8958 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
8959 if (!FiniteOnlyFPMath() &&
8960 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
8962 std::swap(LHS, RHS);
8964 Opcode = X86ISD::FMIN;
8967 // Converting this to a min would handle NaNs incorrectly.
8968 if (!UnsafeFPMath &&
8969 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
8971 Opcode = X86ISD::FMIN;
8974 // Converting this to a min would handle both negative zeros and NaNs
8975 // incorrectly, but we can swap the operands to fix both.
8976 std::swap(LHS, RHS);
8980 Opcode = X86ISD::FMIN;
8984 // Converting this to a max would handle NaNs incorrectly.
8985 if (!FiniteOnlyFPMath() &&
8986 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
8988 Opcode = X86ISD::FMAX;
8991 // Converting this to a max would handle comparisons between positive
8992 // and negative zero incorrectly, and swapping the operands would
8993 // cause it to handle NaNs incorrectly.
8994 if (!UnsafeFPMath &&
8995 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
8996 if (!FiniteOnlyFPMath() &&
8997 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
8999 std::swap(LHS, RHS);
9001 Opcode = X86ISD::FMAX;
9004 // Converting this to a max would handle both negative zeros and NaNs
9005 // incorrectly, but we can swap the operands to fix both.
9006 std::swap(LHS, RHS);
9010 Opcode = X86ISD::FMAX;
9016 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9019 // If this is a select between two integer constants, try to do some
9021 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9022 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9023 // Don't do this for crazy integer types.
9024 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9025 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9026 // so that TrueC (the true value) is larger than FalseC.
9027 bool NeedsCondInvert = false;
9029 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9030 // Efficiently invertible.
9031 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9032 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9033 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9034 NeedsCondInvert = true;
9035 std::swap(TrueC, FalseC);
9038 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9039 if (FalseC->getAPIntValue() == 0 &&
9040 TrueC->getAPIntValue().isPowerOf2()) {
9041 if (NeedsCondInvert) // Invert the condition if needed.
9042 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9043 DAG.getConstant(1, Cond.getValueType()));
9045 // Zero extend the condition if needed.
9046 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9048 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9049 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9050 DAG.getConstant(ShAmt, MVT::i8));
9053 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9054 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9055 if (NeedsCondInvert) // Invert the condition if needed.
9056 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9057 DAG.getConstant(1, Cond.getValueType()));
9059 // Zero extend the condition if needed.
9060 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9061 FalseC->getValueType(0), Cond);
9062 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9063 SDValue(FalseC, 0));
9066 // Optimize cases that will turn into an LEA instruction. This requires
9067 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9068 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9069 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9070 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9072 bool isFastMultiplier = false;
9074 switch ((unsigned char)Diff) {
9076 case 1: // result = add base, cond
9077 case 2: // result = lea base( , cond*2)
9078 case 3: // result = lea base(cond, cond*2)
9079 case 4: // result = lea base( , cond*4)
9080 case 5: // result = lea base(cond, cond*4)
9081 case 8: // result = lea base( , cond*8)
9082 case 9: // result = lea base(cond, cond*8)
9083 isFastMultiplier = true;
9088 if (isFastMultiplier) {
9089 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9090 if (NeedsCondInvert) // Invert the condition if needed.
9091 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9092 DAG.getConstant(1, Cond.getValueType()));
9094 // Zero extend the condition if needed.
9095 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9097 // Scale the condition by the difference.
9099 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9100 DAG.getConstant(Diff, Cond.getValueType()));
9102 // Add the base if non-zero.
9103 if (FalseC->getAPIntValue() != 0)
9104 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9105 SDValue(FalseC, 0));
9115 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9116 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9117 TargetLowering::DAGCombinerInfo &DCI) {
9118 DebugLoc DL = N->getDebugLoc();
9120 // If the flag operand isn't dead, don't touch this CMOV.
9121 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9124 // If this is a select between two integer constants, try to do some
9125 // optimizations. Note that the operands are ordered the opposite of SELECT
9127 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9128 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9129 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9130 // larger than FalseC (the false value).
9131 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9133 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9134 CC = X86::GetOppositeBranchCondition(CC);
9135 std::swap(TrueC, FalseC);
9138 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9139 // This is efficient for any integer data type (including i8/i16) and
9141 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9142 SDValue Cond = N->getOperand(3);
9143 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9144 DAG.getConstant(CC, MVT::i8), Cond);
9146 // Zero extend the condition if needed.
9147 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9149 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9150 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9151 DAG.getConstant(ShAmt, MVT::i8));
9152 if (N->getNumValues() == 2) // Dead flag value?
9153 return DCI.CombineTo(N, Cond, SDValue());
9157 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9158 // for any integer data type, including i8/i16.
9159 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9160 SDValue Cond = N->getOperand(3);
9161 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9162 DAG.getConstant(CC, MVT::i8), Cond);
9164 // Zero extend the condition if needed.
9165 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9166 FalseC->getValueType(0), Cond);
9167 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9168 SDValue(FalseC, 0));
9170 if (N->getNumValues() == 2) // Dead flag value?
9171 return DCI.CombineTo(N, Cond, SDValue());
9175 // Optimize cases that will turn into an LEA instruction. This requires
9176 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9177 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9178 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9179 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9181 bool isFastMultiplier = false;
9183 switch ((unsigned char)Diff) {
9185 case 1: // result = add base, cond
9186 case 2: // result = lea base( , cond*2)
9187 case 3: // result = lea base(cond, cond*2)
9188 case 4: // result = lea base( , cond*4)
9189 case 5: // result = lea base(cond, cond*4)
9190 case 8: // result = lea base( , cond*8)
9191 case 9: // result = lea base(cond, cond*8)
9192 isFastMultiplier = true;
9197 if (isFastMultiplier) {
9198 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9199 SDValue Cond = N->getOperand(3);
9200 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9201 DAG.getConstant(CC, MVT::i8), Cond);
9202 // Zero extend the condition if needed.
9203 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9205 // Scale the condition by the difference.
9207 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9208 DAG.getConstant(Diff, Cond.getValueType()));
9210 // Add the base if non-zero.
9211 if (FalseC->getAPIntValue() != 0)
9212 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9213 SDValue(FalseC, 0));
9214 if (N->getNumValues() == 2) // Dead flag value?
9215 return DCI.CombineTo(N, Cond, SDValue());
9225 /// PerformMulCombine - Optimize a single multiply with constant into two
9226 /// in order to implement it with two cheaper instructions, e.g.
9227 /// LEA + SHL, LEA + LEA.
9228 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9229 TargetLowering::DAGCombinerInfo &DCI) {
9230 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9233 EVT VT = N->getValueType(0);
9237 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9240 uint64_t MulAmt = C->getZExtValue();
9241 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9244 uint64_t MulAmt1 = 0;
9245 uint64_t MulAmt2 = 0;
9246 if ((MulAmt % 9) == 0) {
9248 MulAmt2 = MulAmt / 9;
9249 } else if ((MulAmt % 5) == 0) {
9251 MulAmt2 = MulAmt / 5;
9252 } else if ((MulAmt % 3) == 0) {
9254 MulAmt2 = MulAmt / 3;
9257 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9258 DebugLoc DL = N->getDebugLoc();
9260 if (isPowerOf2_64(MulAmt2) &&
9261 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9262 // If second multiplifer is pow2, issue it first. We want the multiply by
9263 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9265 std::swap(MulAmt1, MulAmt2);
9268 if (isPowerOf2_64(MulAmt1))
9269 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9270 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9272 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9273 DAG.getConstant(MulAmt1, VT));
9275 if (isPowerOf2_64(MulAmt2))
9276 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9277 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9279 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9280 DAG.getConstant(MulAmt2, VT));
9282 // Do not add new nodes to DAG combiner worklist.
9283 DCI.CombineTo(N, NewMul, false);
9288 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9289 SDValue N0 = N->getOperand(0);
9290 SDValue N1 = N->getOperand(1);
9291 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9292 EVT VT = N0.getValueType();
9294 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9295 // since the result of setcc_c is all zero's or all ones.
9296 if (N1C && N0.getOpcode() == ISD::AND &&
9297 N0.getOperand(1).getOpcode() == ISD::Constant) {
9298 SDValue N00 = N0.getOperand(0);
9299 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9300 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9301 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9302 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9303 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9304 APInt ShAmt = N1C->getAPIntValue();
9305 Mask = Mask.shl(ShAmt);
9307 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9308 N00, DAG.getConstant(Mask, VT));
9315 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9317 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9318 const X86Subtarget *Subtarget) {
9319 EVT VT = N->getValueType(0);
9320 if (!VT.isVector() && VT.isInteger() &&
9321 N->getOpcode() == ISD::SHL)
9322 return PerformSHLCombine(N, DAG);
9324 // On X86 with SSE2 support, we can transform this to a vector shift if
9325 // all elements are shifted by the same amount. We can't do this in legalize
9326 // because the a constant vector is typically transformed to a constant pool
9327 // so we have no knowledge of the shift amount.
9328 if (!Subtarget->hasSSE2())
9331 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9334 SDValue ShAmtOp = N->getOperand(1);
9335 EVT EltVT = VT.getVectorElementType();
9336 DebugLoc DL = N->getDebugLoc();
9337 SDValue BaseShAmt = SDValue();
9338 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9339 unsigned NumElts = VT.getVectorNumElements();
9341 for (; i != NumElts; ++i) {
9342 SDValue Arg = ShAmtOp.getOperand(i);
9343 if (Arg.getOpcode() == ISD::UNDEF) continue;
9347 for (; i != NumElts; ++i) {
9348 SDValue Arg = ShAmtOp.getOperand(i);
9349 if (Arg.getOpcode() == ISD::UNDEF) continue;
9350 if (Arg != BaseShAmt) {
9354 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9355 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9356 SDValue InVec = ShAmtOp.getOperand(0);
9357 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9358 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9360 for (; i != NumElts; ++i) {
9361 SDValue Arg = InVec.getOperand(i);
9362 if (Arg.getOpcode() == ISD::UNDEF) continue;
9366 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9368 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9369 if (C->getZExtValue() == SplatIdx)
9370 BaseShAmt = InVec.getOperand(1);
9373 if (BaseShAmt.getNode() == 0)
9374 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9375 DAG.getIntPtrConstant(0));
9379 // The shift amount is an i32.
9380 if (EltVT.bitsGT(MVT::i32))
9381 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9382 else if (EltVT.bitsLT(MVT::i32))
9383 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9385 // The shift amount is identical so we can do a vector shift.
9386 SDValue ValOp = N->getOperand(0);
9387 switch (N->getOpcode()) {
9389 llvm_unreachable("Unknown shift opcode!");
9392 if (VT == MVT::v2i64)
9393 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9394 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9396 if (VT == MVT::v4i32)
9397 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9398 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9400 if (VT == MVT::v8i16)
9401 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9402 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9406 if (VT == MVT::v4i32)
9407 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9408 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9410 if (VT == MVT::v8i16)
9411 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9412 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9416 if (VT == MVT::v2i64)
9417 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9418 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9420 if (VT == MVT::v4i32)
9421 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9422 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9424 if (VT == MVT::v8i16)
9425 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9426 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9433 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9434 const X86Subtarget *Subtarget) {
9435 EVT VT = N->getValueType(0);
9436 if (VT != MVT::i64 || !Subtarget->is64Bit())
9439 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9440 SDValue N0 = N->getOperand(0);
9441 SDValue N1 = N->getOperand(1);
9442 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9444 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9447 SDValue ShAmt0 = N0.getOperand(1);
9448 if (ShAmt0.getValueType() != MVT::i8)
9450 SDValue ShAmt1 = N1.getOperand(1);
9451 if (ShAmt1.getValueType() != MVT::i8)
9453 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9454 ShAmt0 = ShAmt0.getOperand(0);
9455 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9456 ShAmt1 = ShAmt1.getOperand(0);
9458 DebugLoc DL = N->getDebugLoc();
9459 unsigned Opc = X86ISD::SHLD;
9460 SDValue Op0 = N0.getOperand(0);
9461 SDValue Op1 = N1.getOperand(0);
9462 if (ShAmt0.getOpcode() == ISD::SUB) {
9464 std::swap(Op0, Op1);
9465 std::swap(ShAmt0, ShAmt1);
9468 if (ShAmt1.getOpcode() == ISD::SUB) {
9469 SDValue Sum = ShAmt1.getOperand(0);
9470 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9471 if (SumC->getSExtValue() == 64 &&
9472 ShAmt1.getOperand(1) == ShAmt0)
9473 return DAG.getNode(Opc, DL, VT,
9475 DAG.getNode(ISD::TRUNCATE, DL,
9478 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9479 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9481 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
9482 return DAG.getNode(Opc, DL, VT,
9483 N0.getOperand(0), N1.getOperand(0),
9484 DAG.getNode(ISD::TRUNCATE, DL,
9491 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9492 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9493 const X86Subtarget *Subtarget) {
9494 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9495 // the FP state in cases where an emms may be missing.
9496 // A preferable solution to the general problem is to figure out the right
9497 // places to insert EMMS. This qualifies as a quick hack.
9499 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9500 StoreSDNode *St = cast<StoreSDNode>(N);
9501 EVT VT = St->getValue().getValueType();
9502 if (VT.getSizeInBits() != 64)
9505 const Function *F = DAG.getMachineFunction().getFunction();
9506 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9507 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9508 && Subtarget->hasSSE2();
9509 if ((VT.isVector() ||
9510 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9511 isa<LoadSDNode>(St->getValue()) &&
9512 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9513 St->getChain().hasOneUse() && !St->isVolatile()) {
9514 SDNode* LdVal = St->getValue().getNode();
9516 int TokenFactorIndex = -1;
9517 SmallVector<SDValue, 8> Ops;
9518 SDNode* ChainVal = St->getChain().getNode();
9519 // Must be a store of a load. We currently handle two cases: the load
9520 // is a direct child, and it's under an intervening TokenFactor. It is
9521 // possible to dig deeper under nested TokenFactors.
9522 if (ChainVal == LdVal)
9523 Ld = cast<LoadSDNode>(St->getChain());
9524 else if (St->getValue().hasOneUse() &&
9525 ChainVal->getOpcode() == ISD::TokenFactor) {
9526 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9527 if (ChainVal->getOperand(i).getNode() == LdVal) {
9528 TokenFactorIndex = i;
9529 Ld = cast<LoadSDNode>(St->getValue());
9531 Ops.push_back(ChainVal->getOperand(i));
9535 if (!Ld || !ISD::isNormalLoad(Ld))
9538 // If this is not the MMX case, i.e. we are just turning i64 load/store
9539 // into f64 load/store, avoid the transformation if there are multiple
9540 // uses of the loaded value.
9541 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9544 DebugLoc LdDL = Ld->getDebugLoc();
9545 DebugLoc StDL = N->getDebugLoc();
9546 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9547 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9549 if (Subtarget->is64Bit() || F64IsLegal) {
9550 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9551 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9552 Ld->getBasePtr(), Ld->getSrcValue(),
9553 Ld->getSrcValueOffset(), Ld->isVolatile(),
9554 Ld->isNonTemporal(), Ld->getAlignment());
9555 SDValue NewChain = NewLd.getValue(1);
9556 if (TokenFactorIndex != -1) {
9557 Ops.push_back(NewChain);
9558 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9561 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9562 St->getSrcValue(), St->getSrcValueOffset(),
9563 St->isVolatile(), St->isNonTemporal(),
9564 St->getAlignment());
9567 // Otherwise, lower to two pairs of 32-bit loads / stores.
9568 SDValue LoAddr = Ld->getBasePtr();
9569 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9570 DAG.getConstant(4, MVT::i32));
9572 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9573 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9574 Ld->isVolatile(), Ld->isNonTemporal(),
9575 Ld->getAlignment());
9576 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9577 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9578 Ld->isVolatile(), Ld->isNonTemporal(),
9579 MinAlign(Ld->getAlignment(), 4));
9581 SDValue NewChain = LoLd.getValue(1);
9582 if (TokenFactorIndex != -1) {
9583 Ops.push_back(LoLd);
9584 Ops.push_back(HiLd);
9585 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9589 LoAddr = St->getBasePtr();
9590 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9591 DAG.getConstant(4, MVT::i32));
9593 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9594 St->getSrcValue(), St->getSrcValueOffset(),
9595 St->isVolatile(), St->isNonTemporal(),
9596 St->getAlignment());
9597 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9599 St->getSrcValueOffset() + 4,
9601 St->isNonTemporal(),
9602 MinAlign(St->getAlignment(), 4));
9603 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9608 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9609 /// X86ISD::FXOR nodes.
9610 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9611 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9612 // F[X]OR(0.0, x) -> x
9613 // F[X]OR(x, 0.0) -> x
9614 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9615 if (C->getValueAPF().isPosZero())
9616 return N->getOperand(1);
9617 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9618 if (C->getValueAPF().isPosZero())
9619 return N->getOperand(0);
9623 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9624 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9625 // FAND(0.0, x) -> 0.0
9626 // FAND(x, 0.0) -> 0.0
9627 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9628 if (C->getValueAPF().isPosZero())
9629 return N->getOperand(0);
9630 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9631 if (C->getValueAPF().isPosZero())
9632 return N->getOperand(1);
9636 static SDValue PerformBTCombine(SDNode *N,
9638 TargetLowering::DAGCombinerInfo &DCI) {
9639 // BT ignores high bits in the bit index operand.
9640 SDValue Op1 = N->getOperand(1);
9641 if (Op1.hasOneUse()) {
9642 unsigned BitWidth = Op1.getValueSizeInBits();
9643 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9644 APInt KnownZero, KnownOne;
9645 TargetLowering::TargetLoweringOpt TLO(DAG);
9646 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9647 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9648 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9649 DCI.CommitTargetLoweringOpt(TLO);
9654 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9655 SDValue Op = N->getOperand(0);
9656 if (Op.getOpcode() == ISD::BIT_CONVERT)
9657 Op = Op.getOperand(0);
9658 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9659 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9660 VT.getVectorElementType().getSizeInBits() ==
9661 OpVT.getVectorElementType().getSizeInBits()) {
9662 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9667 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9668 // Locked instructions, in turn, have implicit fence semantics (all memory
9669 // operations are flushed before issuing the locked instruction, and the
9670 // are not buffered), so we can fold away the common pattern of
9671 // fence-atomic-fence.
9672 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9673 SDValue atomic = N->getOperand(0);
9674 switch (atomic.getOpcode()) {
9675 case ISD::ATOMIC_CMP_SWAP:
9676 case ISD::ATOMIC_SWAP:
9677 case ISD::ATOMIC_LOAD_ADD:
9678 case ISD::ATOMIC_LOAD_SUB:
9679 case ISD::ATOMIC_LOAD_AND:
9680 case ISD::ATOMIC_LOAD_OR:
9681 case ISD::ATOMIC_LOAD_XOR:
9682 case ISD::ATOMIC_LOAD_NAND:
9683 case ISD::ATOMIC_LOAD_MIN:
9684 case ISD::ATOMIC_LOAD_MAX:
9685 case ISD::ATOMIC_LOAD_UMIN:
9686 case ISD::ATOMIC_LOAD_UMAX:
9692 SDValue fence = atomic.getOperand(0);
9693 if (fence.getOpcode() != ISD::MEMBARRIER)
9696 switch (atomic.getOpcode()) {
9697 case ISD::ATOMIC_CMP_SWAP:
9698 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9699 atomic.getOperand(1), atomic.getOperand(2),
9700 atomic.getOperand(3));
9701 case ISD::ATOMIC_SWAP:
9702 case ISD::ATOMIC_LOAD_ADD:
9703 case ISD::ATOMIC_LOAD_SUB:
9704 case ISD::ATOMIC_LOAD_AND:
9705 case ISD::ATOMIC_LOAD_OR:
9706 case ISD::ATOMIC_LOAD_XOR:
9707 case ISD::ATOMIC_LOAD_NAND:
9708 case ISD::ATOMIC_LOAD_MIN:
9709 case ISD::ATOMIC_LOAD_MAX:
9710 case ISD::ATOMIC_LOAD_UMIN:
9711 case ISD::ATOMIC_LOAD_UMAX:
9712 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9713 atomic.getOperand(1), atomic.getOperand(2));
9719 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9720 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9721 // (and (i32 x86isd::setcc_carry), 1)
9722 // This eliminates the zext. This transformation is necessary because
9723 // ISD::SETCC is always legalized to i8.
9724 DebugLoc dl = N->getDebugLoc();
9725 SDValue N0 = N->getOperand(0);
9726 EVT VT = N->getValueType(0);
9727 if (N0.getOpcode() == ISD::AND &&
9729 N0.getOperand(0).hasOneUse()) {
9730 SDValue N00 = N0.getOperand(0);
9731 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9733 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9734 if (!C || C->getZExtValue() != 1)
9736 return DAG.getNode(ISD::AND, dl, VT,
9737 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9738 N00.getOperand(0), N00.getOperand(1)),
9739 DAG.getConstant(1, VT));
9745 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9746 DAGCombinerInfo &DCI) const {
9747 SelectionDAG &DAG = DCI.DAG;
9748 switch (N->getOpcode()) {
9750 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9751 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9752 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9753 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9756 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9757 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget);
9758 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9760 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9761 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9762 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9763 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9764 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9765 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9771 //===----------------------------------------------------------------------===//
9772 // X86 Inline Assembly Support
9773 //===----------------------------------------------------------------------===//
9775 static bool LowerToBSwap(CallInst *CI) {
9776 // FIXME: this should verify that we are targetting a 486 or better. If not,
9777 // we will turn this bswap into something that will be lowered to logical ops
9778 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9779 // so don't worry about this.
9781 // Verify this is a simple bswap.
9782 if (CI->getNumOperands() != 2 ||
9783 CI->getType() != CI->getOperand(1)->getType() ||
9784 !CI->getType()->isIntegerTy())
9787 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9788 if (!Ty || Ty->getBitWidth() % 16 != 0)
9791 // Okay, we can do this xform, do so now.
9792 const Type *Tys[] = { Ty };
9793 Module *M = CI->getParent()->getParent()->getParent();
9794 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9796 Value *Op = CI->getOperand(1);
9797 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9799 CI->replaceAllUsesWith(Op);
9800 CI->eraseFromParent();
9804 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9805 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9806 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9808 std::string AsmStr = IA->getAsmString();
9810 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9811 SmallVector<StringRef, 4> AsmPieces;
9812 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9814 switch (AsmPieces.size()) {
9815 default: return false;
9817 AsmStr = AsmPieces[0];
9819 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9822 if (AsmPieces.size() == 2 &&
9823 (AsmPieces[0] == "bswap" ||
9824 AsmPieces[0] == "bswapq" ||
9825 AsmPieces[0] == "bswapl") &&
9826 (AsmPieces[1] == "$0" ||
9827 AsmPieces[1] == "${0:q}")) {
9828 // No need to check constraints, nothing other than the equivalent of
9829 // "=r,0" would be valid here.
9830 return LowerToBSwap(CI);
9832 // rorw $$8, ${0:w} --> llvm.bswap.i16
9833 if (CI->getType()->isIntegerTy(16) &&
9834 AsmPieces.size() == 3 &&
9835 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
9836 AsmPieces[1] == "$$8," &&
9837 AsmPieces[2] == "${0:w}" &&
9838 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
9840 SplitString(IA->getConstraintString().substr(5), AsmPieces, ",");
9841 std::sort(AsmPieces.begin(), AsmPieces.end());
9842 if (AsmPieces.size() == 4 &&
9843 AsmPieces[0] == "~{cc}" &&
9844 AsmPieces[1] == "~{dirflag}" &&
9845 AsmPieces[2] == "~{flags}" &&
9846 AsmPieces[3] == "~{fpsr}") {
9847 return LowerToBSwap(CI);
9852 if (CI->getType()->isIntegerTy(64) &&
9853 Constraints.size() >= 2 &&
9854 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9855 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9856 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9857 SmallVector<StringRef, 4> Words;
9858 SplitString(AsmPieces[0], Words, " \t");
9859 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9861 SplitString(AsmPieces[1], Words, " \t");
9862 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9864 SplitString(AsmPieces[2], Words, " \t,");
9865 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9866 Words[2] == "%edx") {
9867 return LowerToBSwap(CI);
9879 /// getConstraintType - Given a constraint letter, return the type of
9880 /// constraint it is for this target.
9881 X86TargetLowering::ConstraintType
9882 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9883 if (Constraint.size() == 1) {
9884 switch (Constraint[0]) {
9896 return C_RegisterClass;
9904 return TargetLowering::getConstraintType(Constraint);
9907 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9908 /// with another that has more specific requirements based on the type of the
9909 /// corresponding operand.
9910 const char *X86TargetLowering::
9911 LowerXConstraint(EVT ConstraintVT) const {
9912 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9913 // 'f' like normal targets.
9914 if (ConstraintVT.isFloatingPoint()) {
9915 if (Subtarget->hasSSE2())
9917 if (Subtarget->hasSSE1())
9921 return TargetLowering::LowerXConstraint(ConstraintVT);
9924 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9925 /// vector. If it is invalid, don't add anything to Ops.
9926 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9929 std::vector<SDValue>&Ops,
9930 SelectionDAG &DAG) const {
9931 SDValue Result(0, 0);
9933 switch (Constraint) {
9936 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9937 if (C->getZExtValue() <= 31) {
9938 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9944 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9945 if (C->getZExtValue() <= 63) {
9946 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9952 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9953 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9954 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9960 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9961 if (C->getZExtValue() <= 255) {
9962 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9968 // 32-bit signed value
9969 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9970 const ConstantInt *CI = C->getConstantIntValue();
9971 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9972 C->getSExtValue())) {
9973 // Widen to 64 bits here to get it sign extended.
9974 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9977 // FIXME gcc accepts some relocatable values here too, but only in certain
9978 // memory models; it's complicated.
9983 // 32-bit unsigned value
9984 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9985 const ConstantInt *CI = C->getConstantIntValue();
9986 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9987 C->getZExtValue())) {
9988 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9992 // FIXME gcc accepts some relocatable values here too, but only in certain
9993 // memory models; it's complicated.
9997 // Literal immediates are always ok.
9998 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9999 // Widen to 64 bits here to get it sign extended.
10000 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10004 // If we are in non-pic codegen mode, we allow the address of a global (with
10005 // an optional displacement) to be used with 'i'.
10006 GlobalAddressSDNode *GA = 0;
10007 int64_t Offset = 0;
10009 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10011 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10012 Offset += GA->getOffset();
10014 } else if (Op.getOpcode() == ISD::ADD) {
10015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10016 Offset += C->getZExtValue();
10017 Op = Op.getOperand(0);
10020 } else if (Op.getOpcode() == ISD::SUB) {
10021 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10022 Offset += -C->getZExtValue();
10023 Op = Op.getOperand(0);
10028 // Otherwise, this isn't something we can handle, reject it.
10032 GlobalValue *GV = GA->getGlobal();
10033 // If we require an extra load to get this address, as in PIC mode, we
10034 // can't accept it.
10035 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10036 getTargetMachine())))
10040 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
10042 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
10048 if (Result.getNode()) {
10049 Ops.push_back(Result);
10052 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
10056 std::vector<unsigned> X86TargetLowering::
10057 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10059 if (Constraint.size() == 1) {
10060 // FIXME: not handling fp-stack yet!
10061 switch (Constraint[0]) { // GCC X86 Constraint Letters
10062 default: break; // Unknown constraint letter
10063 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10064 if (Subtarget->is64Bit()) {
10065 if (VT == MVT::i32)
10066 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10067 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10068 X86::R10D,X86::R11D,X86::R12D,
10069 X86::R13D,X86::R14D,X86::R15D,
10070 X86::EBP, X86::ESP, 0);
10071 else if (VT == MVT::i16)
10072 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10073 X86::SI, X86::DI, X86::R8W,X86::R9W,
10074 X86::R10W,X86::R11W,X86::R12W,
10075 X86::R13W,X86::R14W,X86::R15W,
10076 X86::BP, X86::SP, 0);
10077 else if (VT == MVT::i8)
10078 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10079 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10080 X86::R10B,X86::R11B,X86::R12B,
10081 X86::R13B,X86::R14B,X86::R15B,
10082 X86::BPL, X86::SPL, 0);
10084 else if (VT == MVT::i64)
10085 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10086 X86::RSI, X86::RDI, X86::R8, X86::R9,
10087 X86::R10, X86::R11, X86::R12,
10088 X86::R13, X86::R14, X86::R15,
10089 X86::RBP, X86::RSP, 0);
10093 // 32-bit fallthrough
10094 case 'Q': // Q_REGS
10095 if (VT == MVT::i32)
10096 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10097 else if (VT == MVT::i16)
10098 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10099 else if (VT == MVT::i8)
10100 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10101 else if (VT == MVT::i64)
10102 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10107 return std::vector<unsigned>();
10110 std::pair<unsigned, const TargetRegisterClass*>
10111 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10113 // First, see if this is a constraint that directly corresponds to an LLVM
10115 if (Constraint.size() == 1) {
10116 // GCC Constraint Letters
10117 switch (Constraint[0]) {
10119 case 'r': // GENERAL_REGS
10120 case 'l': // INDEX_REGS
10122 return std::make_pair(0U, X86::GR8RegisterClass);
10123 if (VT == MVT::i16)
10124 return std::make_pair(0U, X86::GR16RegisterClass);
10125 if (VT == MVT::i32 || !Subtarget->is64Bit())
10126 return std::make_pair(0U, X86::GR32RegisterClass);
10127 return std::make_pair(0U, X86::GR64RegisterClass);
10128 case 'R': // LEGACY_REGS
10130 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10131 if (VT == MVT::i16)
10132 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10133 if (VT == MVT::i32 || !Subtarget->is64Bit())
10134 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10135 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10136 case 'f': // FP Stack registers.
10137 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10138 // value to the correct fpstack register class.
10139 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10140 return std::make_pair(0U, X86::RFP32RegisterClass);
10141 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10142 return std::make_pair(0U, X86::RFP64RegisterClass);
10143 return std::make_pair(0U, X86::RFP80RegisterClass);
10144 case 'y': // MMX_REGS if MMX allowed.
10145 if (!Subtarget->hasMMX()) break;
10146 return std::make_pair(0U, X86::VR64RegisterClass);
10147 case 'Y': // SSE_REGS if SSE2 allowed
10148 if (!Subtarget->hasSSE2()) break;
10150 case 'x': // SSE_REGS if SSE1 allowed
10151 if (!Subtarget->hasSSE1()) break;
10153 switch (VT.getSimpleVT().SimpleTy) {
10155 // Scalar SSE types.
10158 return std::make_pair(0U, X86::FR32RegisterClass);
10161 return std::make_pair(0U, X86::FR64RegisterClass);
10169 return std::make_pair(0U, X86::VR128RegisterClass);
10175 // Use the default implementation in TargetLowering to convert the register
10176 // constraint into a member of a register class.
10177 std::pair<unsigned, const TargetRegisterClass*> Res;
10178 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10180 // Not found as a standard register?
10181 if (Res.second == 0) {
10182 // Map st(0) -> st(7) -> ST0
10183 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10184 tolower(Constraint[1]) == 's' &&
10185 tolower(Constraint[2]) == 't' &&
10186 Constraint[3] == '(' &&
10187 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10188 Constraint[5] == ')' &&
10189 Constraint[6] == '}') {
10191 Res.first = X86::ST0+Constraint[4]-'0';
10192 Res.second = X86::RFP80RegisterClass;
10196 // GCC allows "st(0)" to be called just plain "st".
10197 if (StringRef("{st}").equals_lower(Constraint)) {
10198 Res.first = X86::ST0;
10199 Res.second = X86::RFP80RegisterClass;
10204 if (StringRef("{flags}").equals_lower(Constraint)) {
10205 Res.first = X86::EFLAGS;
10206 Res.second = X86::CCRRegisterClass;
10210 // 'A' means EAX + EDX.
10211 if (Constraint == "A") {
10212 Res.first = X86::EAX;
10213 Res.second = X86::GR32_ADRegisterClass;
10219 // Otherwise, check to see if this is a register class of the wrong value
10220 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10221 // turn into {ax},{dx}.
10222 if (Res.second->hasType(VT))
10223 return Res; // Correct type already, nothing to do.
10225 // All of the single-register GCC register classes map their values onto
10226 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10227 // really want an 8-bit or 32-bit register, map to the appropriate register
10228 // class and return the appropriate register.
10229 if (Res.second == X86::GR16RegisterClass) {
10230 if (VT == MVT::i8) {
10231 unsigned DestReg = 0;
10232 switch (Res.first) {
10234 case X86::AX: DestReg = X86::AL; break;
10235 case X86::DX: DestReg = X86::DL; break;
10236 case X86::CX: DestReg = X86::CL; break;
10237 case X86::BX: DestReg = X86::BL; break;
10240 Res.first = DestReg;
10241 Res.second = X86::GR8RegisterClass;
10243 } else if (VT == MVT::i32) {
10244 unsigned DestReg = 0;
10245 switch (Res.first) {
10247 case X86::AX: DestReg = X86::EAX; break;
10248 case X86::DX: DestReg = X86::EDX; break;
10249 case X86::CX: DestReg = X86::ECX; break;
10250 case X86::BX: DestReg = X86::EBX; break;
10251 case X86::SI: DestReg = X86::ESI; break;
10252 case X86::DI: DestReg = X86::EDI; break;
10253 case X86::BP: DestReg = X86::EBP; break;
10254 case X86::SP: DestReg = X86::ESP; break;
10257 Res.first = DestReg;
10258 Res.second = X86::GR32RegisterClass;
10260 } else if (VT == MVT::i64) {
10261 unsigned DestReg = 0;
10262 switch (Res.first) {
10264 case X86::AX: DestReg = X86::RAX; break;
10265 case X86::DX: DestReg = X86::RDX; break;
10266 case X86::CX: DestReg = X86::RCX; break;
10267 case X86::BX: DestReg = X86::RBX; break;
10268 case X86::SI: DestReg = X86::RSI; break;
10269 case X86::DI: DestReg = X86::RDI; break;
10270 case X86::BP: DestReg = X86::RBP; break;
10271 case X86::SP: DestReg = X86::RSP; break;
10274 Res.first = DestReg;
10275 Res.second = X86::GR64RegisterClass;
10278 } else if (Res.second == X86::FR32RegisterClass ||
10279 Res.second == X86::FR64RegisterClass ||
10280 Res.second == X86::VR128RegisterClass) {
10281 // Handle references to XMM physical registers that got mapped into the
10282 // wrong class. This can happen with constraints like {xmm0} where the
10283 // target independent register mapper will just pick the first match it can
10284 // find, ignoring the required type.
10285 if (VT == MVT::f32)
10286 Res.second = X86::FR32RegisterClass;
10287 else if (VT == MVT::f64)
10288 Res.second = X86::FR64RegisterClass;
10289 else if (X86::VR128RegisterClass->hasType(VT))
10290 Res.second = X86::VR128RegisterClass;
10296 //===----------------------------------------------------------------------===//
10297 // X86 Widen vector type
10298 //===----------------------------------------------------------------------===//
10300 /// getWidenVectorType: given a vector type, returns the type to widen
10301 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
10302 /// If there is no vector type that we want to widen to, returns MVT::Other
10303 /// When and where to widen is target dependent based on the cost of
10304 /// scalarizing vs using the wider vector type.
10306 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
10307 assert(VT.isVector());
10308 if (isTypeLegal(VT))
10311 // TODO: In computeRegisterProperty, we can compute the list of legal vector
10312 // type based on element type. This would speed up our search (though
10313 // it may not be worth it since the size of the list is relatively
10315 EVT EltVT = VT.getVectorElementType();
10316 unsigned NElts = VT.getVectorNumElements();
10318 // On X86, it make sense to widen any vector wider than 1
10322 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
10323 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
10324 EVT SVT = (MVT::SimpleValueType)nVT;
10326 if (isTypeLegal(SVT) &&
10327 SVT.getVectorElementType() == EltVT &&
10328 SVT.getVectorNumElements() > NElts)