1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec,
69 EVT VT = Vec.getValueType();
70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
71 EVT ElVT = VT.getVectorElementType();
72 int Factor = VT.getSizeInBits()/128;
73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
74 VT.getVectorNumElements()/Factor);
76 // Extract from UNDEF is UNDEF.
77 if (Vec.getOpcode() == ISD::UNDEF)
78 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
80 if (isa<ConstantSDNode>(Idx)) {
81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
84 // we can match to VEXTRACTF128.
85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
87 // This is the index of the first element of the 128-bit chunk
89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
102 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
103 /// sets things up to match to an AVX VINSERTF128 instruction or a
104 /// simple superregister reference. Idx is an index in the 128 bits
105 /// we want. It need not be aligned to a 128-bit bounday. That makes
106 /// lowering INSERT_VECTOR_ELT operations easier.
107 static SDValue Insert128BitVector(SDValue Result,
112 if (isa<ConstantSDNode>(Idx)) {
113 EVT VT = Vec.getValueType();
114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
116 EVT ElVT = VT.getVectorElementType();
117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
118 EVT ResultVT = Result.getValueType();
120 // Insert the relevant 128 bits.
121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
123 // This is the index of the first element of the 128-bit chunk
125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X8664_MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetELF())
148 return new TargetLoweringObjectFileELF();
149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
150 return new TargetLoweringObjectFileCOFF();
151 llvm_unreachable("unknown subtarget type");
154 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
155 : TargetLowering(TM, createTLOF(TM)) {
156 Subtarget = &TM.getSubtarget<X86Subtarget>();
157 X86ScalarSSEf64 = Subtarget->hasSSE2();
158 X86ScalarSSEf32 = Subtarget->hasSSE1();
159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
161 RegInfo = TM.getRegisterInfo();
162 TD = getTargetData();
164 // Set up the TargetLowering object.
165 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
167 // X86 is weird, it always uses i8 for shift amounts and setcc results.
168 setBooleanContents(ZeroOrOneBooleanContent);
169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
172 // For 64-bit since we have so many registers use the ILP scheduler, for
173 // 32-bit code use the register pressure specific scheduling.
174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
175 if (Subtarget->is64Bit())
176 setSchedulingPreference(Sched::ILP);
177 else if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::Hybrid);
180 setSchedulingPreference(Sched::RegPressure);
181 setStackPointerRegisterToSaveRestore(X86StackPtr);
183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
184 // Setup Windows compiler runtime calls.
185 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
187 setLibcallName(RTLIB::SREM_I64, "_allrem");
188 setLibcallName(RTLIB::UREM_I64, "_aullrem");
189 setLibcallName(RTLIB::MUL_I64, "_allmul");
190 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
191 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
192 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
196 // The _ftol2 runtime function has an unusual calling conv, which
197 // is modeled by a special pseudo-instruction.
198 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
199 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
200 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
201 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
204 if (Subtarget->isTargetDarwin()) {
205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
206 setUseUnderscoreSetJmp(false);
207 setUseUnderscoreLongJmp(false);
208 } else if (Subtarget->isTargetMingw()) {
209 // MS runtime is weird: it exports _setjmp, but longjmp!
210 setUseUnderscoreSetJmp(true);
211 setUseUnderscoreLongJmp(false);
213 setUseUnderscoreSetJmp(true);
214 setUseUnderscoreLongJmp(true);
217 // Set up the register classes.
218 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
219 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
220 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
221 if (Subtarget->is64Bit())
222 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
226 // We don't accept any truncstore of integer registers.
227 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
228 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
230 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
234 // SETOEQ and SETUNE require checking two conditions.
235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
248 if (Subtarget->is64Bit()) {
249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 } else if (!TM.Options.UseSoftFloat) {
252 // We have an algorithm for SSE2->double, and we turn this into a
253 // 64-bit FILD followed by conditional FADD for other targets.
254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
255 // We have an algorithm for SSE2, and we turn this into a 64-bit
256 // FILD for other targets.
257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
265 if (!TM.Options.UseSoftFloat) {
266 // SSE has no i16 to fp conversion, only i32
267 if (X86ScalarSSEf32) {
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
269 // f32 and f64 cases are Legal, f80 case is not
270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
281 // are Legal, f80 is custom lowered.
282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
290 if (X86ScalarSSEf32) {
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
292 // f32 and f64 cases are Legal, f80 case is not
293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
299 // Handle FP_TO_UINT by promoting the destination to a larger signed
301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
305 if (Subtarget->is64Bit()) {
306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
308 } else if (!TM.Options.UseSoftFloat) {
309 // Since AVX is a superset of SSE3, only check for SSE here.
310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
311 // Expand FP_TO_UINT into a select.
312 // FIXME: We would like to use a Custom expander here eventually to do
313 // the optimal thing for SSE vs. the default expansion in the legalizer.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
316 // With SSE3 we can use fisttpll to convert to a signed i64; without
317 // SSE, we're stuck with a fistpll.
318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
321 if (isTargetFTOL()) {
322 // Use the _ftol2 runtime function, which has a pseudo-instruction
323 // to handle its weird calling convention.
324 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
327 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
328 if (!X86ScalarSSEf64) {
329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
331 if (Subtarget->is64Bit()) {
332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
333 // Without SSE, i64->f64 goes through memory.
334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
338 // Scalar integer divide and remainder are lowered to use operations that
339 // produce two results, to match the available instructions. This exposes
340 // the two-result form to trivial CSE, which is able to combine x/y and x%y
341 // into a single instruction.
343 // Scalar integer multiply-high is also lowered to use two-result
344 // operations, to match the available instructions. However, plain multiply
345 // (low) operations are left as Legal, as there are single-result
346 // instructions for this in x86. Using the two-result multiply instructions
347 // when both high and low results are needed must be arranged by dagcombine.
348 for (unsigned i = 0, e = 4; i != e; ++i) {
350 setOperationAction(ISD::MULHS, VT, Expand);
351 setOperationAction(ISD::MULHU, VT, Expand);
352 setOperationAction(ISD::SDIV, VT, Expand);
353 setOperationAction(ISD::UDIV, VT, Expand);
354 setOperationAction(ISD::SREM, VT, Expand);
355 setOperationAction(ISD::UREM, VT, Expand);
357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
358 setOperationAction(ISD::ADDC, VT, Custom);
359 setOperationAction(ISD::ADDE, VT, Custom);
360 setOperationAction(ISD::SUBC, VT, Custom);
361 setOperationAction(ISD::SUBE, VT, Custom);
364 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
365 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
366 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
368 if (Subtarget->is64Bit())
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f64 , Expand);
376 setOperationAction(ISD::FREM , MVT::f80 , Expand);
377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
379 // Promote the i8 variants and force them on up to i32 which has a shorter
381 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
382 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
385 if (Subtarget->hasBMI()) {
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
388 if (Subtarget->is64Bit())
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
391 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
392 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
397 if (Subtarget->hasLZCNT()) {
398 // When promoting the i8 variants, force them to i32 for a shorter
400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
401 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
406 if (Subtarget->is64Bit())
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
409 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
410 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
421 if (Subtarget->hasPOPCNT()) {
422 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
424 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
425 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
427 if (Subtarget->is64Bit())
428 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
431 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
432 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
434 // These should be promoted to a larger select which is supported.
435 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
436 // X86 wants to expand cmov itself.
437 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
438 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
440 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
443 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
446 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
449 if (Subtarget->is64Bit()) {
450 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
453 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
456 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
457 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
458 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
460 if (Subtarget->is64Bit())
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
462 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
463 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
464 if (Subtarget->is64Bit()) {
465 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
466 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
467 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
468 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
469 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
471 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
472 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
475 if (Subtarget->is64Bit()) {
476 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
477 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
481 if (Subtarget->hasSSE1())
482 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
484 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
485 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
487 // On X86 and X86-64, atomic operations are lowered to locked instructions.
488 // Locked instructions, in turn, have implicit fence semantics (all memory
489 // operations are flushed before issuing the locked instruction, and they
490 // are not buffered), so we can fold away the common pattern of
491 // fence-atomic-fence.
492 setShouldFoldAtomicFences(true);
494 // Expand certain atomics
495 for (unsigned i = 0, e = 4; i != e; ++i) {
497 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
498 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
502 if (!Subtarget->is64Bit()) {
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
513 if (Subtarget->hasCmpxchg16b()) {
514 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
517 // FIXME - use subtarget debug flags
518 if (!Subtarget->isTargetDarwin() &&
519 !Subtarget->isTargetELF() &&
520 !Subtarget->isTargetCygMing()) {
521 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
525 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
528 if (Subtarget->is64Bit()) {
529 setExceptionPointerRegister(X86::RAX);
530 setExceptionSelectorRegister(X86::RDX);
532 setExceptionPointerRegister(X86::EAX);
533 setExceptionSelectorRegister(X86::EDX);
535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
538 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
539 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::TRAP, MVT::Other, Legal);
543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
544 setOperationAction(ISD::VASTART , MVT::Other, Custom);
545 setOperationAction(ISD::VAEND , MVT::Other, Expand);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::VAARG , MVT::Other, Custom);
548 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
550 setOperationAction(ISD::VAARG , MVT::Other, Expand);
551 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
554 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
555 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
557 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
559 MVT::i64 : MVT::i32, Custom);
560 else if (TM.Options.EnableSegmentedStacks)
561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
562 MVT::i64 : MVT::i32, Custom);
564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
565 MVT::i64 : MVT::i32, Expand);
567 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
568 // f32 and f64 use SSE.
569 // Set up the FP register classes.
570 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
571 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
573 // Use ANDPD to simulate FABS.
574 setOperationAction(ISD::FABS , MVT::f64, Custom);
575 setOperationAction(ISD::FABS , MVT::f32, Custom);
577 // Use XORP to simulate FNEG.
578 setOperationAction(ISD::FNEG , MVT::f64, Custom);
579 setOperationAction(ISD::FNEG , MVT::f32, Custom);
581 // Use ANDPD and ORPD to simulate FCOPYSIGN.
582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
585 // Lower this to FGETSIGNx86 plus an AND.
586 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
587 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
589 // We don't support sin/cos/fmod
590 setOperationAction(ISD::FSIN , MVT::f64, Expand);
591 setOperationAction(ISD::FCOS , MVT::f64, Expand);
592 setOperationAction(ISD::FSIN , MVT::f32, Expand);
593 setOperationAction(ISD::FCOS , MVT::f32, Expand);
595 // Expand FP immediates into loads from the stack, except for the special
597 addLegalFPImmediate(APFloat(+0.0)); // xorpd
598 addLegalFPImmediate(APFloat(+0.0f)); // xorps
599 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
600 // Use SSE for f32, x87 for f64.
601 // Set up the FP register classes.
602 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
603 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
605 // Use ANDPS to simulate FABS.
606 setOperationAction(ISD::FABS , MVT::f32, Custom);
608 // Use XORP to simulate FNEG.
609 setOperationAction(ISD::FNEG , MVT::f32, Custom);
611 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
613 // Use ANDPS and ORPS to simulate FCOPYSIGN.
614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
617 // We don't support sin/cos/fmod
618 setOperationAction(ISD::FSIN , MVT::f32, Expand);
619 setOperationAction(ISD::FCOS , MVT::f32, Expand);
621 // Special cases we handle for FP constants.
622 addLegalFPImmediate(APFloat(+0.0f)); // xorps
623 addLegalFPImmediate(APFloat(+0.0)); // FLD0
624 addLegalFPImmediate(APFloat(+1.0)); // FLD1
625 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
626 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
628 if (!TM.Options.UnsafeFPMath) {
629 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
630 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
632 } else if (!TM.Options.UseSoftFloat) {
633 // f32 and f64 in x87.
634 // Set up the FP register classes.
635 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
636 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
638 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
639 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
640 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
643 if (!TM.Options.UnsafeFPMath) {
644 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
645 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
647 addLegalFPImmediate(APFloat(+0.0)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
651 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
652 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
653 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
654 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
657 // We don't support FMA.
658 setOperationAction(ISD::FMA, MVT::f64, Expand);
659 setOperationAction(ISD::FMA, MVT::f32, Expand);
661 // Long double always uses X87.
662 if (!TM.Options.UseSoftFloat) {
663 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
664 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
665 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
667 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
668 addLegalFPImmediate(TmpFlt); // FLD0
670 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
673 APFloat TmpFlt2(+1.0);
674 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
676 addLegalFPImmediate(TmpFlt2); // FLD1
677 TmpFlt2.changeSign();
678 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
681 if (!TM.Options.UnsafeFPMath) {
682 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
683 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
686 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
687 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
688 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
689 setOperationAction(ISD::FRINT, MVT::f80, Expand);
690 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
691 setOperationAction(ISD::FMA, MVT::f80, Expand);
694 // Always use a library call for pow.
695 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
696 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
699 setOperationAction(ISD::FLOG, MVT::f80, Expand);
700 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
702 setOperationAction(ISD::FEXP, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
705 // First set operation action for all vector types to either promote
706 // (for widening) or expand (for scalarization). Then we will selectively
707 // turn on ones that can be effectively codegen'd.
708 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
709 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
710 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
725 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
762 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
767 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
768 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
769 setTruncStoreAction((MVT::SimpleValueType)VT,
770 (MVT::SimpleValueType)InnerVT, Expand);
771 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
777 // with -msoft-float, disable use of MMX as well.
778 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
779 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
780 // No operations on x86mmx supported, everything uses intrinsics.
783 // MMX-sized vectors (other than x86mmx) are expected to be expanded
784 // into smaller operations.
785 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
786 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
787 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
788 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
789 setOperationAction(ISD::AND, MVT::v8i8, Expand);
790 setOperationAction(ISD::AND, MVT::v4i16, Expand);
791 setOperationAction(ISD::AND, MVT::v2i32, Expand);
792 setOperationAction(ISD::AND, MVT::v1i64, Expand);
793 setOperationAction(ISD::OR, MVT::v8i8, Expand);
794 setOperationAction(ISD::OR, MVT::v4i16, Expand);
795 setOperationAction(ISD::OR, MVT::v2i32, Expand);
796 setOperationAction(ISD::OR, MVT::v1i64, Expand);
797 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
806 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
807 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
808 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
809 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
810 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
815 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
816 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
818 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
819 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
820 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
821 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
823 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
824 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
825 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
826 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
828 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
832 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
833 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
835 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
836 // registers cannot be used even for integer operations.
837 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
838 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
839 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
840 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
842 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
843 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
844 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
845 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
846 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
847 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
848 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
849 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
850 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
851 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
852 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
853 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
854 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
855 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
856 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
857 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
859 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
861 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
862 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
877 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
878 EVT VT = (MVT::SimpleValueType)i;
879 // Do not attempt to custom lower non-power-of-2 vectors
880 if (!isPowerOf2_32(VT.getVectorNumElements()))
882 // Do not attempt to custom lower non-128-bit vectors
883 if (!VT.is128BitVector())
885 setOperationAction(ISD::BUILD_VECTOR,
886 VT.getSimpleVT().SimpleTy, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE,
888 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
890 VT.getSimpleVT().SimpleTy, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
900 if (Subtarget->is64Bit()) {
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
907 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
910 // Do not attempt to promote non-128-bit vectors
911 if (!VT.is128BitVector())
914 setOperationAction(ISD::AND, SVT, Promote);
915 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
916 setOperationAction(ISD::OR, SVT, Promote);
917 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
918 setOperationAction(ISD::XOR, SVT, Promote);
919 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
920 setOperationAction(ISD::LOAD, SVT, Promote);
921 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
922 setOperationAction(ISD::SELECT, SVT, Promote);
923 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
926 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
938 if (Subtarget->hasSSE41()) {
939 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
940 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
941 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
942 setOperationAction(ISD::FRINT, MVT::f32, Legal);
943 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
944 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
945 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
946 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
947 setOperationAction(ISD::FRINT, MVT::f64, Legal);
948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
950 // FIXME: Do we need to handle scalar-to-vector here?
951 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
959 // i8 and i16 vectors are custom , because the source register and source
960 // source memory operand types are not the same width. f32 vectors are
961 // custom since the immediate controlling the insert encodes additional
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
973 // FIXME: these should be Legal but thats only for the case where
974 // the index is constant. For now custom expand to deal with that.
975 if (Subtarget->is64Bit()) {
976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
981 if (Subtarget->hasSSE2()) {
982 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
983 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
985 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
986 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
988 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
989 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
991 if (Subtarget->hasAVX2()) {
992 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
993 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
995 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
996 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
998 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1000 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1001 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1003 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1004 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1006 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1010 if (Subtarget->hasSSE42())
1011 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1013 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1014 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1015 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1016 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1017 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1018 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1019 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1021 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1025 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1032 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1039 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1040 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1041 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1064 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1068 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1073 if (Subtarget->hasAVX2()) {
1074 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1075 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1076 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1077 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1079 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1080 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1081 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1082 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1084 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1085 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1086 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1087 // Don't lower v32i8 because there is no 128-bit byte mul
1089 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1091 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1092 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1094 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1095 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1099 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1100 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1101 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1104 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1105 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1106 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1109 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1110 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1111 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1112 // Don't lower v32i8 because there is no 128-bit byte mul
1114 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1115 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1117 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1120 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1123 // Custom lower several nodes for 256-bit types.
1124 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1125 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1126 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1129 // Extract subvector is special because the value type
1130 // (result) is 128-bit but the source is 256-bit wide.
1131 if (VT.is128BitVector())
1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1134 // Do not attempt to custom lower other non-256-bit vectors
1135 if (!VT.is256BitVector())
1138 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1140 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1143 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1146 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1147 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1148 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1151 // Do not attempt to promote non-256-bit vectors
1152 if (!VT.is256BitVector())
1155 setOperationAction(ISD::AND, SVT, Promote);
1156 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1157 setOperationAction(ISD::OR, SVT, Promote);
1158 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1159 setOperationAction(ISD::XOR, SVT, Promote);
1160 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1161 setOperationAction(ISD::LOAD, SVT, Promote);
1162 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1163 setOperationAction(ISD::SELECT, SVT, Promote);
1164 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1169 // of this type with custom code.
1170 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1171 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1176 // We want to custom lower some of our intrinsics.
1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1180 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1181 // handle type legalization for these operations here.
1183 // FIXME: We really should do custom legalization for addition and
1184 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1185 // than generic legalization for 64-bit multiplication-with-overflow, though.
1186 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1187 // Add/Sub/Mul with overflow operations are custom lowered.
1189 setOperationAction(ISD::SADDO, VT, Custom);
1190 setOperationAction(ISD::UADDO, VT, Custom);
1191 setOperationAction(ISD::SSUBO, VT, Custom);
1192 setOperationAction(ISD::USUBO, VT, Custom);
1193 setOperationAction(ISD::SMULO, VT, Custom);
1194 setOperationAction(ISD::UMULO, VT, Custom);
1197 // There are no 8-bit 3-address imul/mul instructions
1198 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1199 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1201 if (!Subtarget->is64Bit()) {
1202 // These libcalls are not available in 32-bit.
1203 setLibcallName(RTLIB::SHL_I128, 0);
1204 setLibcallName(RTLIB::SRL_I128, 0);
1205 setLibcallName(RTLIB::SRA_I128, 0);
1208 // We have target-specific dag combine patterns for the following nodes:
1209 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1210 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1211 setTargetDAGCombine(ISD::VSELECT);
1212 setTargetDAGCombine(ISD::SELECT);
1213 setTargetDAGCombine(ISD::SHL);
1214 setTargetDAGCombine(ISD::SRA);
1215 setTargetDAGCombine(ISD::SRL);
1216 setTargetDAGCombine(ISD::OR);
1217 setTargetDAGCombine(ISD::AND);
1218 setTargetDAGCombine(ISD::ADD);
1219 setTargetDAGCombine(ISD::FADD);
1220 setTargetDAGCombine(ISD::FSUB);
1221 setTargetDAGCombine(ISD::SUB);
1222 setTargetDAGCombine(ISD::LOAD);
1223 setTargetDAGCombine(ISD::STORE);
1224 setTargetDAGCombine(ISD::ZERO_EXTEND);
1225 setTargetDAGCombine(ISD::SIGN_EXTEND);
1226 setTargetDAGCombine(ISD::TRUNCATE);
1227 setTargetDAGCombine(ISD::SINT_TO_FP);
1228 if (Subtarget->is64Bit())
1229 setTargetDAGCombine(ISD::MUL);
1230 if (Subtarget->hasBMI())
1231 setTargetDAGCombine(ISD::XOR);
1233 computeRegisterProperties();
1235 // On Darwin, -Os means optimize for size without hurting performance,
1236 // do not reduce the limit.
1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1243 setPrefLoopAlignment(4); // 2^4 bytes.
1244 benefitFromCodePlacementOpt = true;
1246 setPrefFunctionAlignment(4); // 2^4 bytes.
1250 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1251 if (!VT.isVector()) return MVT::i8;
1252 return VT.changeVectorElementTypeToInteger();
1256 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1257 /// the desired ByVal argument alignment.
1258 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262 if (VTy->getBitWidth() == 128)
1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1265 unsigned EltAlign = 0;
1266 getMaxByValAlign(ATy->getElementType(), EltAlign);
1267 if (EltAlign > MaxAlign)
1268 MaxAlign = EltAlign;
1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1271 unsigned EltAlign = 0;
1272 getMaxByValAlign(STy->getElementType(i), EltAlign);
1273 if (EltAlign > MaxAlign)
1274 MaxAlign = EltAlign;
1282 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1283 /// function arguments in the caller parameter area. For X86, aggregates
1284 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1285 /// are at 4-byte boundaries.
1286 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1287 if (Subtarget->is64Bit()) {
1288 // Max of 8 and alignment of type.
1289 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1296 if (Subtarget->hasSSE1())
1297 getMaxByValAlign(Ty, Align);
1301 /// getOptimalMemOpType - Returns the target specific optimal type for load
1302 /// and store operations as a result of memset, memcpy, and memmove
1303 /// lowering. If DstAlign is zero that means it's safe to destination
1304 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1305 /// means there isn't a need to check it against alignment requirement,
1306 /// probably because the source does not need to be loaded. If
1307 /// 'IsZeroVal' is true, that means it's safe to return a
1308 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1309 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1310 /// constant so it does not need to be loaded.
1311 /// It returns EVT::Other if the type should be determined using generic
1312 /// target-independent logic.
1314 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1315 unsigned DstAlign, unsigned SrcAlign,
1318 MachineFunction &MF) const {
1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1320 // linux. This is because the stack realignment code can't handle certain
1321 // cases like PR2962. This should be removed when PR2962 is fixed.
1322 const Function *F = MF.getFunction();
1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1326 (Subtarget->isUnalignedMemAccessFast() ||
1327 ((DstAlign == 0 || DstAlign >= 16) &&
1328 (SrcAlign == 0 || SrcAlign >= 16))) &&
1329 Subtarget->getStackAlignment() >= 16) {
1330 if (Subtarget->getStackAlignment() >= 32) {
1331 if (Subtarget->hasAVX2())
1333 if (Subtarget->hasAVX())
1336 if (Subtarget->hasSSE2())
1338 if (Subtarget->hasSSE1())
1340 } else if (!MemcpyStrSrc && Size >= 8 &&
1341 !Subtarget->is64Bit() &&
1342 Subtarget->getStackAlignment() >= 8 &&
1343 Subtarget->hasSSE2()) {
1344 // Do not use f64 to lower memcpy if source is string constant. It's
1345 // better to use i32 to avoid the loads.
1349 if (Subtarget->is64Bit() && Size >= 8)
1354 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1355 /// current function. The returned value is a member of the
1356 /// MachineJumpTableInfo::JTEntryKind enum.
1357 unsigned X86TargetLowering::getJumpTableEncoding() const {
1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1361 Subtarget->isPICStyleGOT())
1362 return MachineJumpTableInfo::EK_Custom32;
1364 // Otherwise, use the normal jump table encoding heuristics.
1365 return TargetLowering::getJumpTableEncoding();
1369 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1370 const MachineBasicBlock *MBB,
1371 unsigned uid,MCContext &Ctx) const{
1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1373 Subtarget->isPICStyleGOT());
1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1376 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1377 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1380 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1382 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1383 SelectionDAG &DAG) const {
1384 if (!Subtarget->is64Bit())
1385 // This doesn't have DebugLoc associated with it, but is not really the
1386 // same as a Register.
1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1391 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1392 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1394 const MCExpr *X86TargetLowering::
1395 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1396 MCContext &Ctx) const {
1397 // X86-64 uses RIP relative addressing based on the jump table label.
1398 if (Subtarget->isPICStyleRIPRel())
1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1401 // Otherwise, the reference is relative to the PIC base.
1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1405 // FIXME: Why this routine is here? Move to RegInfo!
1406 std::pair<const TargetRegisterClass*, uint8_t>
1407 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1408 const TargetRegisterClass *RRC = 0;
1410 switch (VT.getSimpleVT().SimpleTy) {
1412 return TargetLowering::findRepresentativeClass(VT);
1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1414 RRC = (Subtarget->is64Bit()
1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1418 RRC = X86::VR64RegisterClass;
1420 case MVT::f32: case MVT::f64:
1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1422 case MVT::v4f32: case MVT::v2f64:
1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1425 RRC = X86::VR128RegisterClass;
1428 return std::make_pair(RRC, Cost);
1431 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1432 unsigned &Offset) const {
1433 if (!Subtarget->isTargetLinux())
1436 if (Subtarget->is64Bit()) {
1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1452 //===----------------------------------------------------------------------===//
1453 // Return Value Calling Convention Implementation
1454 //===----------------------------------------------------------------------===//
1456 #include "X86GenCallingConv.inc"
1459 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1460 MachineFunction &MF, bool isVarArg,
1461 const SmallVectorImpl<ISD::OutputArg> &Outs,
1462 LLVMContext &Context) const {
1463 SmallVector<CCValAssign, 16> RVLocs;
1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1466 return CCInfo.CheckReturn(Outs, RetCC_X86);
1470 X86TargetLowering::LowerReturn(SDValue Chain,
1471 CallingConv::ID CallConv, bool isVarArg,
1472 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<SDValue> &OutVals,
1474 DebugLoc dl, SelectionDAG &DAG) const {
1475 MachineFunction &MF = DAG.getMachineFunction();
1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1478 SmallVector<CCValAssign, 16> RVLocs;
1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1480 RVLocs, *DAG.getContext());
1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1483 // Add the regs to the liveout set for the function.
1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1485 for (unsigned i = 0; i != RVLocs.size(); ++i)
1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1487 MRI.addLiveOut(RVLocs[i].getLocReg());
1491 SmallVector<SDValue, 6> RetOps;
1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1493 // Operand #1 = Bytes To Pop
1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1497 // Copy the result values into the output registers.
1498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1499 CCValAssign &VA = RVLocs[i];
1500 assert(VA.isRegLoc() && "Can only return in registers!");
1501 SDValue ValToCopy = OutVals[i];
1502 EVT ValVT = ValToCopy.getValueType();
1504 // If this is x86-64, and we disabled SSE, we can't return FP values,
1505 // or SSE or MMX vectors.
1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1509 report_fatal_error("SSE register return with SSE disabled");
1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1512 // llvm-gcc has never done it right and no one has noticed, so this
1513 // should be OK for now.
1514 if (ValVT == MVT::f64 &&
1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1516 report_fatal_error("SSE2 register return with SSE2 disabled");
1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1519 // the RET instruction and handled by the FP Stackifier.
1520 if (VA.getLocReg() == X86::ST0 ||
1521 VA.getLocReg() == X86::ST1) {
1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1523 // change the value to the FP stack register class.
1524 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1526 RetOps.push_back(ValToCopy);
1527 // Don't emit a copytoreg.
1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1532 // which is returned in RAX / RDX.
1533 if (Subtarget->is64Bit()) {
1534 if (ValVT == MVT::x86mmx) {
1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1539 // If we don't have SSE2 available, convert to v4f32 so the generated
1540 // register is legal.
1541 if (!Subtarget->hasSSE2())
1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1548 Flag = Chain.getValue(1);
1551 // The x86-64 ABI for returning structs by value requires that we copy
1552 // the sret argument into %rax for the return. We saved the argument into
1553 // a virtual register in the entry block, so now we copy the value out
1555 if (Subtarget->is64Bit() &&
1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1559 unsigned Reg = FuncInfo->getSRetReturnReg();
1561 "SRetReturnReg should have been set in LowerFormalArguments().");
1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1565 Flag = Chain.getValue(1);
1567 // RAX now acts like a return value.
1568 MRI.addLiveOut(X86::RAX);
1571 RetOps[0] = Chain; // Update chain.
1573 // Add the flag if we have it.
1575 RetOps.push_back(Flag);
1577 return DAG.getNode(X86ISD::RET_FLAG, dl,
1578 MVT::Other, &RetOps[0], RetOps.size());
1581 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1582 if (N->getNumValues() != 1)
1584 if (!N->hasNUsesOfValue(1, 0))
1587 SDValue TCChain = Chain;
1588 SDNode *Copy = *N->use_begin();
1589 if (Copy->getOpcode() == ISD::CopyToReg) {
1590 // If the copy has a glue operand, we conservatively assume it isn't safe to
1591 // perform a tail call.
1592 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1594 TCChain = Copy->getOperand(0);
1595 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1598 bool HasRet = false;
1599 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1601 if (UI->getOpcode() != X86ISD::RET_FLAG)
1614 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1615 ISD::NodeType ExtendKind) const {
1617 // TODO: Is this also valid on 32-bit?
1618 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1619 ReturnMVT = MVT::i8;
1621 ReturnMVT = MVT::i32;
1623 EVT MinVT = getRegisterType(Context, ReturnMVT);
1624 return VT.bitsLT(MinVT) ? MinVT : VT;
1627 /// LowerCallResult - Lower the result values of a call into the
1628 /// appropriate copies out of appropriate physical registers.
1631 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1632 CallingConv::ID CallConv, bool isVarArg,
1633 const SmallVectorImpl<ISD::InputArg> &Ins,
1634 DebugLoc dl, SelectionDAG &DAG,
1635 SmallVectorImpl<SDValue> &InVals) const {
1637 // Assign locations to each value returned by this call.
1638 SmallVector<CCValAssign, 16> RVLocs;
1639 bool Is64Bit = Subtarget->is64Bit();
1640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1641 getTargetMachine(), RVLocs, *DAG.getContext());
1642 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1644 // Copy all of the result registers out of their specified physreg.
1645 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1646 CCValAssign &VA = RVLocs[i];
1647 EVT CopyVT = VA.getValVT();
1649 // If this is x86-64, and we disabled SSE, we can't return FP values
1650 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1651 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1652 report_fatal_error("SSE register return with SSE disabled");
1657 // If this is a call to a function that returns an fp value on the floating
1658 // point stack, we must guarantee the the value is popped from the stack, so
1659 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1660 // if the return value is not used. We use the FpPOP_RETVAL instruction
1662 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1663 // If we prefer to use the value in xmm registers, copy it out as f80 and
1664 // use a truncate to move it from fp stack reg to xmm reg.
1665 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1666 SDValue Ops[] = { Chain, InFlag };
1667 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1668 MVT::Other, MVT::Glue, Ops, 2), 1);
1669 Val = Chain.getValue(0);
1671 // Round the f80 to the right size, which also moves it to the appropriate
1673 if (CopyVT != VA.getValVT())
1674 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1675 // This truncation won't change the value.
1676 DAG.getIntPtrConstant(1));
1678 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1679 CopyVT, InFlag).getValue(1);
1680 Val = Chain.getValue(0);
1682 InFlag = Chain.getValue(2);
1683 InVals.push_back(Val);
1690 //===----------------------------------------------------------------------===//
1691 // C & StdCall & Fast Calling Convention implementation
1692 //===----------------------------------------------------------------------===//
1693 // StdCall calling convention seems to be standard for many Windows' API
1694 // routines and around. It differs from C calling convention just a little:
1695 // callee should clean up the stack, not caller. Symbols should be also
1696 // decorated in some fancy way :) It doesn't support any vector arguments.
1697 // For info on fast calling convention see Fast Calling Convention (tail call)
1698 // implementation LowerX86_32FastCCCallTo.
1700 /// CallIsStructReturn - Determines whether a call uses struct return
1702 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1706 return Outs[0].Flags.isSRet();
1709 /// ArgsAreStructReturn - Determines whether a function uses struct
1710 /// return semantics.
1712 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1716 return Ins[0].Flags.isSRet();
1719 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1720 /// by "Src" to address "Dst" with size and alignment information specified by
1721 /// the specific parameter attribute. The copy will be passed as a byval
1722 /// function parameter.
1724 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1725 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1727 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1729 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1730 /*isVolatile*/false, /*AlwaysInline=*/true,
1731 MachinePointerInfo(), MachinePointerInfo());
1734 /// IsTailCallConvention - Return true if the calling convention is one that
1735 /// supports tail call optimization.
1736 static bool IsTailCallConvention(CallingConv::ID CC) {
1737 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1740 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1741 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1745 CallingConv::ID CalleeCC = CS.getCallingConv();
1746 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1752 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1753 /// a tailcall target by changing its ABI.
1754 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1755 bool GuaranteedTailCallOpt) {
1756 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1760 X86TargetLowering::LowerMemArgument(SDValue Chain,
1761 CallingConv::ID CallConv,
1762 const SmallVectorImpl<ISD::InputArg> &Ins,
1763 DebugLoc dl, SelectionDAG &DAG,
1764 const CCValAssign &VA,
1765 MachineFrameInfo *MFI,
1767 // Create the nodes corresponding to a load from this parameter slot.
1768 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1769 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1770 getTargetMachine().Options.GuaranteedTailCallOpt);
1771 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1774 // If value is passed by pointer we have address passed instead of the value
1776 if (VA.getLocInfo() == CCValAssign::Indirect)
1777 ValVT = VA.getLocVT();
1779 ValVT = VA.getValVT();
1781 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1782 // changed with more analysis.
1783 // In case of tail call optimization mark all arguments mutable. Since they
1784 // could be overwritten by lowering of arguments in case of a tail call.
1785 if (Flags.isByVal()) {
1786 unsigned Bytes = Flags.getByValSize();
1787 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1788 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1789 return DAG.getFrameIndex(FI, getPointerTy());
1791 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1792 VA.getLocMemOffset(), isImmutable);
1793 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1794 return DAG.getLoad(ValVT, dl, Chain, FIN,
1795 MachinePointerInfo::getFixedStack(FI),
1796 false, false, false, 0);
1801 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1802 CallingConv::ID CallConv,
1804 const SmallVectorImpl<ISD::InputArg> &Ins,
1807 SmallVectorImpl<SDValue> &InVals)
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1812 const Function* Fn = MF.getFunction();
1813 if (Fn->hasExternalLinkage() &&
1814 Subtarget->isTargetCygMing() &&
1815 Fn->getName() == "main")
1816 FuncInfo->setForceFramePointer(true);
1818 MachineFrameInfo *MFI = MF.getFrameInfo();
1819 bool Is64Bit = Subtarget->is64Bit();
1820 bool IsWindows = Subtarget->isTargetWindows();
1821 bool IsWin64 = Subtarget->isTargetWin64();
1823 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1824 "Var args not supported with calling convention fastcc or ghc");
1826 // Assign locations to all of the incoming arguments.
1827 SmallVector<CCValAssign, 16> ArgLocs;
1828 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1829 ArgLocs, *DAG.getContext());
1831 // Allocate shadow area for Win64
1833 CCInfo.AllocateStack(32, 8);
1836 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1838 unsigned LastVal = ~0U;
1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1841 CCValAssign &VA = ArgLocs[i];
1842 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1844 assert(VA.getValNo() != LastVal &&
1845 "Don't support value assigned to multiple locs yet");
1847 LastVal = VA.getValNo();
1849 if (VA.isRegLoc()) {
1850 EVT RegVT = VA.getLocVT();
1851 const TargetRegisterClass *RC;
1852 if (RegVT == MVT::i32)
1853 RC = X86::GR32RegisterClass;
1854 else if (Is64Bit && RegVT == MVT::i64)
1855 RC = X86::GR64RegisterClass;
1856 else if (RegVT == MVT::f32)
1857 RC = X86::FR32RegisterClass;
1858 else if (RegVT == MVT::f64)
1859 RC = X86::FR64RegisterClass;
1860 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1861 RC = X86::VR256RegisterClass;
1862 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1863 RC = X86::VR128RegisterClass;
1864 else if (RegVT == MVT::x86mmx)
1865 RC = X86::VR64RegisterClass;
1867 llvm_unreachable("Unknown argument type!");
1869 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1870 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1872 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1873 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1875 if (VA.getLocInfo() == CCValAssign::SExt)
1876 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1877 DAG.getValueType(VA.getValVT()));
1878 else if (VA.getLocInfo() == CCValAssign::ZExt)
1879 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1880 DAG.getValueType(VA.getValVT()));
1881 else if (VA.getLocInfo() == CCValAssign::BCvt)
1882 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1884 if (VA.isExtInLoc()) {
1885 // Handle MMX values passed in XMM regs.
1886 if (RegVT.isVector()) {
1887 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1890 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1893 assert(VA.isMemLoc());
1894 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1897 // If value is passed via pointer - do a load.
1898 if (VA.getLocInfo() == CCValAssign::Indirect)
1899 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1900 MachinePointerInfo(), false, false, false, 0);
1902 InVals.push_back(ArgValue);
1905 // The x86-64 ABI for returning structs by value requires that we copy
1906 // the sret argument into %rax for the return. Save the argument into
1907 // a virtual register so that we can access it from the return points.
1908 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1909 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1910 unsigned Reg = FuncInfo->getSRetReturnReg();
1912 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1913 FuncInfo->setSRetReturnReg(Reg);
1915 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1919 unsigned StackSize = CCInfo.getNextStackOffset();
1920 // Align stack specially for tail calls.
1921 if (FuncIsMadeTailCallSafe(CallConv,
1922 MF.getTarget().Options.GuaranteedTailCallOpt))
1923 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1925 // If the function takes variable number of arguments, make a frame index for
1926 // the start of the first vararg value... for expansion of llvm.va_start.
1928 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1929 CallConv != CallingConv::X86_ThisCall)) {
1930 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1933 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1935 // FIXME: We should really autogenerate these arrays
1936 static const uint16_t GPR64ArgRegsWin64[] = {
1937 X86::RCX, X86::RDX, X86::R8, X86::R9
1939 static const uint16_t GPR64ArgRegs64Bit[] = {
1940 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1942 static const uint16_t XMMArgRegs64Bit[] = {
1943 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1944 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1946 const uint16_t *GPR64ArgRegs;
1947 unsigned NumXMMRegs = 0;
1950 // The XMM registers which might contain var arg parameters are shadowed
1951 // in their paired GPR. So we only need to save the GPR to their home
1953 TotalNumIntRegs = 4;
1954 GPR64ArgRegs = GPR64ArgRegsWin64;
1956 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1957 GPR64ArgRegs = GPR64ArgRegs64Bit;
1959 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1962 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1965 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1966 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1967 "SSE register cannot be used when SSE is disabled!");
1968 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1969 NoImplicitFloatOps) &&
1970 "SSE register cannot be used when SSE is disabled!");
1971 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1972 !Subtarget->hasSSE1())
1973 // Kernel mode asks for SSE to be disabled, so don't push them
1975 TotalNumXMMRegs = 0;
1978 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1979 // Get to the caller-allocated home save location. Add 8 to account
1980 // for the return address.
1981 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1982 FuncInfo->setRegSaveFrameIndex(
1983 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1984 // Fixup to set vararg frame on shadow area (4 x i64).
1986 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1988 // For X86-64, if there are vararg parameters that are passed via
1989 // registers, then we must store them to their spots on the stack so
1990 // they may be loaded by deferencing the result of va_next.
1991 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1992 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1993 FuncInfo->setRegSaveFrameIndex(
1994 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1998 // Store the integer parameter registers.
1999 SmallVector<SDValue, 8> MemOps;
2000 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2002 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2003 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2004 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2005 DAG.getIntPtrConstant(Offset));
2006 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2007 X86::GR64RegisterClass);
2008 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2010 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2011 MachinePointerInfo::getFixedStack(
2012 FuncInfo->getRegSaveFrameIndex(), Offset),
2014 MemOps.push_back(Store);
2018 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2019 // Now store the XMM (fp + vector) parameter registers.
2020 SmallVector<SDValue, 11> SaveXMMOps;
2021 SaveXMMOps.push_back(Chain);
2023 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2024 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2025 SaveXMMOps.push_back(ALVal);
2027 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2028 FuncInfo->getRegSaveFrameIndex()));
2029 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2030 FuncInfo->getVarArgsFPOffset()));
2032 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2033 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2034 X86::VR128RegisterClass);
2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2036 SaveXMMOps.push_back(Val);
2038 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2040 &SaveXMMOps[0], SaveXMMOps.size()));
2043 if (!MemOps.empty())
2044 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2045 &MemOps[0], MemOps.size());
2049 // Some CCs need callee pop.
2050 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2051 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2052 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2054 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2055 // If this is an sret function, the return should pop the hidden pointer.
2056 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2057 ArgsAreStructReturn(Ins))
2058 FuncInfo->setBytesToPopOnReturn(4);
2062 // RegSaveFrameIndex is X86-64 only.
2063 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2064 if (CallConv == CallingConv::X86_FastCall ||
2065 CallConv == CallingConv::X86_ThisCall)
2066 // fastcc functions can't have varargs.
2067 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2070 FuncInfo->setArgumentStackSize(StackSize);
2076 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2077 SDValue StackPtr, SDValue Arg,
2078 DebugLoc dl, SelectionDAG &DAG,
2079 const CCValAssign &VA,
2080 ISD::ArgFlagsTy Flags) const {
2081 unsigned LocMemOffset = VA.getLocMemOffset();
2082 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2083 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2084 if (Flags.isByVal())
2085 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2087 return DAG.getStore(Chain, dl, Arg, PtrOff,
2088 MachinePointerInfo::getStack(LocMemOffset),
2092 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2093 /// optimization is performed and it is required.
2095 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2096 SDValue &OutRetAddr, SDValue Chain,
2097 bool IsTailCall, bool Is64Bit,
2098 int FPDiff, DebugLoc dl) const {
2099 // Adjust the Return address stack slot.
2100 EVT VT = getPointerTy();
2101 OutRetAddr = getReturnAddressFrameIndex(DAG);
2103 // Load the "old" Return address.
2104 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2105 false, false, false, 0);
2106 return SDValue(OutRetAddr.getNode(), 1);
2109 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2110 /// optimization is performed and it is required (FPDiff!=0).
2112 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2113 SDValue Chain, SDValue RetAddrFrIdx,
2114 bool Is64Bit, int FPDiff, DebugLoc dl) {
2115 // Store the return address to the appropriate stack slot.
2116 if (!FPDiff) return Chain;
2117 // Calculate the new stack slot for the return address.
2118 int SlotSize = Is64Bit ? 8 : 4;
2119 int NewReturnAddrFI =
2120 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2121 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2122 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2123 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2124 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2130 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2131 CallingConv::ID CallConv, bool isVarArg,
2132 bool doesNotRet, bool &isTailCall,
2133 const SmallVectorImpl<ISD::OutputArg> &Outs,
2134 const SmallVectorImpl<SDValue> &OutVals,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2136 DebugLoc dl, SelectionDAG &DAG,
2137 SmallVectorImpl<SDValue> &InVals) const {
2138 MachineFunction &MF = DAG.getMachineFunction();
2139 bool Is64Bit = Subtarget->is64Bit();
2140 bool IsWin64 = Subtarget->isTargetWin64();
2141 bool IsWindows = Subtarget->isTargetWindows();
2142 bool IsStructRet = CallIsStructReturn(Outs);
2143 bool IsSibcall = false;
2145 if (MF.getTarget().Options.DisableTailCalls)
2149 // Check if it's really possible to do a tail call.
2150 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2151 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2152 Outs, OutVals, Ins, DAG);
2154 // Sibcalls are automatically detected tailcalls which do not require
2156 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2163 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2164 "Var args not supported with calling convention fastcc or ghc");
2166 // Analyze operands of the call, assigning locations to each operand.
2167 SmallVector<CCValAssign, 16> ArgLocs;
2168 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2169 ArgLocs, *DAG.getContext());
2171 // Allocate shadow area for Win64
2173 CCInfo.AllocateStack(32, 8);
2176 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2178 // Get a count of how many bytes are to be pushed on the stack.
2179 unsigned NumBytes = CCInfo.getNextStackOffset();
2181 // This is a sibcall. The memory operands are available in caller's
2182 // own caller's stack.
2184 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2185 IsTailCallConvention(CallConv))
2186 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2189 if (isTailCall && !IsSibcall) {
2190 // Lower arguments at fp - stackoffset + fpdiff.
2191 unsigned NumBytesCallerPushed =
2192 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2193 FPDiff = NumBytesCallerPushed - NumBytes;
2195 // Set the delta of movement of the returnaddr stackslot.
2196 // But only set if delta is greater than previous delta.
2197 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2198 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2202 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2204 SDValue RetAddrFrIdx;
2205 // Load return address for tail calls.
2206 if (isTailCall && FPDiff)
2207 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2208 Is64Bit, FPDiff, dl);
2210 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2211 SmallVector<SDValue, 8> MemOpChains;
2214 // Walk the register/memloc assignments, inserting copies/loads. In the case
2215 // of tail call optimization arguments are handle later.
2216 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2217 CCValAssign &VA = ArgLocs[i];
2218 EVT RegVT = VA.getLocVT();
2219 SDValue Arg = OutVals[i];
2220 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2221 bool isByVal = Flags.isByVal();
2223 // Promote the value if needed.
2224 switch (VA.getLocInfo()) {
2225 default: llvm_unreachable("Unknown loc info!");
2226 case CCValAssign::Full: break;
2227 case CCValAssign::SExt:
2228 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2230 case CCValAssign::ZExt:
2231 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2233 case CCValAssign::AExt:
2234 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2235 // Special case: passing MMX values in XMM registers.
2236 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2237 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2238 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2240 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2242 case CCValAssign::BCvt:
2243 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2245 case CCValAssign::Indirect: {
2246 // Store the argument.
2247 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2248 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2249 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2250 MachinePointerInfo::getFixedStack(FI),
2257 if (VA.isRegLoc()) {
2258 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2259 if (isVarArg && IsWin64) {
2260 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2261 // shadow reg if callee is a varargs function.
2262 unsigned ShadowReg = 0;
2263 switch (VA.getLocReg()) {
2264 case X86::XMM0: ShadowReg = X86::RCX; break;
2265 case X86::XMM1: ShadowReg = X86::RDX; break;
2266 case X86::XMM2: ShadowReg = X86::R8; break;
2267 case X86::XMM3: ShadowReg = X86::R9; break;
2270 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2272 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2273 assert(VA.isMemLoc());
2274 if (StackPtr.getNode() == 0)
2275 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2276 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2277 dl, DAG, VA, Flags));
2281 if (!MemOpChains.empty())
2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2283 &MemOpChains[0], MemOpChains.size());
2285 // Build a sequence of copy-to-reg nodes chained together with token chain
2286 // and flag operands which copy the outgoing args into registers.
2288 // Tail call byval lowering might overwrite argument registers so in case of
2289 // tail call optimization the copies to registers are lowered later.
2291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2293 RegsToPass[i].second, InFlag);
2294 InFlag = Chain.getValue(1);
2297 if (Subtarget->isPICStyleGOT()) {
2298 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2301 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2302 DAG.getNode(X86ISD::GlobalBaseReg,
2303 DebugLoc(), getPointerTy()),
2305 InFlag = Chain.getValue(1);
2307 // If we are tail calling and generating PIC/GOT style code load the
2308 // address of the callee into ECX. The value in ecx is used as target of
2309 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2310 // for tail calls on PIC/GOT architectures. Normally we would just put the
2311 // address of GOT into ebx and then call target@PLT. But for tail calls
2312 // ebx would be restored (since ebx is callee saved) before jumping to the
2315 // Note: The actual moving to ECX is done further down.
2316 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2317 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2318 !G->getGlobal()->hasProtectedVisibility())
2319 Callee = LowerGlobalAddress(Callee, DAG);
2320 else if (isa<ExternalSymbolSDNode>(Callee))
2321 Callee = LowerExternalSymbol(Callee, DAG);
2325 if (Is64Bit && isVarArg && !IsWin64) {
2326 // From AMD64 ABI document:
2327 // For calls that may call functions that use varargs or stdargs
2328 // (prototype-less calls or calls to functions containing ellipsis (...) in
2329 // the declaration) %al is used as hidden argument to specify the number
2330 // of SSE registers used. The contents of %al do not need to match exactly
2331 // the number of registers, but must be an ubound on the number of SSE
2332 // registers used and is in the range 0 - 8 inclusive.
2334 // Count the number of XMM registers allocated.
2335 static const uint16_t XMMArgRegs[] = {
2336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2337 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2339 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2340 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2341 && "SSE registers cannot be used when SSE is disabled");
2343 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2344 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2345 InFlag = Chain.getValue(1);
2349 // For tail calls lower the arguments to the 'real' stack slot.
2351 // Force all the incoming stack arguments to be loaded from the stack
2352 // before any new outgoing arguments are stored to the stack, because the
2353 // outgoing stack slots may alias the incoming argument stack slots, and
2354 // the alias isn't otherwise explicit. This is slightly more conservative
2355 // than necessary, because it means that each store effectively depends
2356 // on every argument instead of just those arguments it would clobber.
2357 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2359 SmallVector<SDValue, 8> MemOpChains2;
2362 // Do not flag preceding copytoreg stuff together with the following stuff.
2364 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2366 CCValAssign &VA = ArgLocs[i];
2369 assert(VA.isMemLoc());
2370 SDValue Arg = OutVals[i];
2371 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2372 // Create frame index.
2373 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2374 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2375 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2376 FIN = DAG.getFrameIndex(FI, getPointerTy());
2378 if (Flags.isByVal()) {
2379 // Copy relative to framepointer.
2380 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2381 if (StackPtr.getNode() == 0)
2382 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2384 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2386 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2390 // Store relative to framepointer.
2391 MemOpChains2.push_back(
2392 DAG.getStore(ArgChain, dl, Arg, FIN,
2393 MachinePointerInfo::getFixedStack(FI),
2399 if (!MemOpChains2.empty())
2400 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2401 &MemOpChains2[0], MemOpChains2.size());
2403 // Copy arguments to their registers.
2404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2405 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2406 RegsToPass[i].second, InFlag);
2407 InFlag = Chain.getValue(1);
2411 // Store the return address to the appropriate stack slot.
2412 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2416 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2417 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2418 // In the 64-bit large code model, we have to make all calls
2419 // through a register, since the call instruction's 32-bit
2420 // pc-relative offset may not be large enough to hold the whole
2422 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2423 // If the callee is a GlobalAddress node (quite common, every direct call
2424 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2427 // We should use extra load for direct calls to dllimported functions in
2429 const GlobalValue *GV = G->getGlobal();
2430 if (!GV->hasDLLImportLinkage()) {
2431 unsigned char OpFlags = 0;
2432 bool ExtraLoad = false;
2433 unsigned WrapperKind = ISD::DELETED_NODE;
2435 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2436 // external symbols most go through the PLT in PIC mode. If the symbol
2437 // has hidden or protected visibility, or if it is static or local, then
2438 // we don't need to use the PLT - we can directly call it.
2439 if (Subtarget->isTargetELF() &&
2440 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2441 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2442 OpFlags = X86II::MO_PLT;
2443 } else if (Subtarget->isPICStyleStubAny() &&
2444 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2445 (!Subtarget->getTargetTriple().isMacOSX() ||
2446 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2447 // PC-relative references to external symbols should go through $stub,
2448 // unless we're building with the leopard linker or later, which
2449 // automatically synthesizes these stubs.
2450 OpFlags = X86II::MO_DARWIN_STUB;
2451 } else if (Subtarget->isPICStyleRIPRel() &&
2452 isa<Function>(GV) &&
2453 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2454 // If the function is marked as non-lazy, generate an indirect call
2455 // which loads from the GOT directly. This avoids runtime overhead
2456 // at the cost of eager binding (and one extra byte of encoding).
2457 OpFlags = X86II::MO_GOTPCREL;
2458 WrapperKind = X86ISD::WrapperRIP;
2462 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2463 G->getOffset(), OpFlags);
2465 // Add a wrapper if needed.
2466 if (WrapperKind != ISD::DELETED_NODE)
2467 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2468 // Add extra indirection if needed.
2470 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2471 MachinePointerInfo::getGOT(),
2472 false, false, false, 0);
2474 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2475 unsigned char OpFlags = 0;
2477 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2478 // external symbols should go through the PLT.
2479 if (Subtarget->isTargetELF() &&
2480 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2481 OpFlags = X86II::MO_PLT;
2482 } else if (Subtarget->isPICStyleStubAny() &&
2483 (!Subtarget->getTargetTriple().isMacOSX() ||
2484 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2485 // PC-relative references to external symbols should go through $stub,
2486 // unless we're building with the leopard linker or later, which
2487 // automatically synthesizes these stubs.
2488 OpFlags = X86II::MO_DARWIN_STUB;
2491 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2495 // Returns a chain & a flag for retval copy to use.
2496 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2497 SmallVector<SDValue, 8> Ops;
2499 if (!IsSibcall && isTailCall) {
2500 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2501 DAG.getIntPtrConstant(0, true), InFlag);
2502 InFlag = Chain.getValue(1);
2505 Ops.push_back(Chain);
2506 Ops.push_back(Callee);
2509 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2511 // Add argument registers to the end of the list so that they are known live
2513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2514 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2515 RegsToPass[i].second.getValueType()));
2517 // Add an implicit use GOT pointer in EBX.
2518 if (!isTailCall && Subtarget->isPICStyleGOT())
2519 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2521 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2522 if (Is64Bit && isVarArg && !IsWin64)
2523 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2525 // Add a register mask operand representing the call-preserved registers.
2526 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2527 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2528 assert(Mask && "Missing call preserved mask for calling convention");
2529 Ops.push_back(DAG.getRegisterMask(Mask));
2531 if (InFlag.getNode())
2532 Ops.push_back(InFlag);
2536 //// If this is the first return lowered for this function, add the regs
2537 //// to the liveout set for the function.
2538 // This isn't right, although it's probably harmless on x86; liveouts
2539 // should be computed from returns not tail calls. Consider a void
2540 // function making a tail call to a function returning int.
2541 return DAG.getNode(X86ISD::TC_RETURN, dl,
2542 NodeTys, &Ops[0], Ops.size());
2545 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2546 InFlag = Chain.getValue(1);
2548 // Create the CALLSEQ_END node.
2549 unsigned NumBytesForCalleeToPush;
2550 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2551 getTargetMachine().Options.GuaranteedTailCallOpt))
2552 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2553 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2555 // If this is a call to a struct-return function, the callee
2556 // pops the hidden struct pointer, so we have to push it back.
2557 // This is common for Darwin/X86, Linux & Mingw32 targets.
2558 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2559 NumBytesForCalleeToPush = 4;
2561 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2563 // Returns a flag for retval copy to use.
2565 Chain = DAG.getCALLSEQ_END(Chain,
2566 DAG.getIntPtrConstant(NumBytes, true),
2567 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2570 InFlag = Chain.getValue(1);
2573 // Handle result values, copying them out of physregs into vregs that we
2575 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2576 Ins, dl, DAG, InVals);
2580 //===----------------------------------------------------------------------===//
2581 // Fast Calling Convention (tail call) implementation
2582 //===----------------------------------------------------------------------===//
2584 // Like std call, callee cleans arguments, convention except that ECX is
2585 // reserved for storing the tail called function address. Only 2 registers are
2586 // free for argument passing (inreg). Tail call optimization is performed
2588 // * tailcallopt is enabled
2589 // * caller/callee are fastcc
2590 // On X86_64 architecture with GOT-style position independent code only local
2591 // (within module) calls are supported at the moment.
2592 // To keep the stack aligned according to platform abi the function
2593 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2594 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2595 // If a tail called function callee has more arguments than the caller the
2596 // caller needs to make sure that there is room to move the RETADDR to. This is
2597 // achieved by reserving an area the size of the argument delta right after the
2598 // original REtADDR, but before the saved framepointer or the spilled registers
2599 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2611 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2612 /// for a 16 byte align requirement.
2614 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2615 SelectionDAG& DAG) const {
2616 MachineFunction &MF = DAG.getMachineFunction();
2617 const TargetMachine &TM = MF.getTarget();
2618 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2619 unsigned StackAlignment = TFI.getStackAlignment();
2620 uint64_t AlignMask = StackAlignment - 1;
2621 int64_t Offset = StackSize;
2622 uint64_t SlotSize = TD->getPointerSize();
2623 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2624 // Number smaller than 12 so just add the difference.
2625 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2627 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2628 Offset = ((~AlignMask) & Offset) + StackAlignment +
2629 (StackAlignment-SlotSize);
2634 /// MatchingStackOffset - Return true if the given stack call argument is
2635 /// already available in the same position (relatively) of the caller's
2636 /// incoming argument stack.
2638 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2639 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2640 const X86InstrInfo *TII) {
2641 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2643 if (Arg.getOpcode() == ISD::CopyFromReg) {
2644 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2645 if (!TargetRegisterInfo::isVirtualRegister(VR))
2647 MachineInstr *Def = MRI->getVRegDef(VR);
2650 if (!Flags.isByVal()) {
2651 if (!TII->isLoadFromStackSlot(Def, FI))
2654 unsigned Opcode = Def->getOpcode();
2655 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2656 Def->getOperand(1).isFI()) {
2657 FI = Def->getOperand(1).getIndex();
2658 Bytes = Flags.getByValSize();
2662 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2663 if (Flags.isByVal())
2664 // ByVal argument is passed in as a pointer but it's now being
2665 // dereferenced. e.g.
2666 // define @foo(%struct.X* %A) {
2667 // tail call @bar(%struct.X* byval %A)
2670 SDValue Ptr = Ld->getBasePtr();
2671 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2674 FI = FINode->getIndex();
2675 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2676 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2677 FI = FINode->getIndex();
2678 Bytes = Flags.getByValSize();
2682 assert(FI != INT_MAX);
2683 if (!MFI->isFixedObjectIndex(FI))
2685 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2688 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2689 /// for tail call optimization. Targets which want to do tail call
2690 /// optimization should implement this function.
2692 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2693 CallingConv::ID CalleeCC,
2695 bool isCalleeStructRet,
2696 bool isCallerStructRet,
2697 const SmallVectorImpl<ISD::OutputArg> &Outs,
2698 const SmallVectorImpl<SDValue> &OutVals,
2699 const SmallVectorImpl<ISD::InputArg> &Ins,
2700 SelectionDAG& DAG) const {
2701 if (!IsTailCallConvention(CalleeCC) &&
2702 CalleeCC != CallingConv::C)
2705 // If -tailcallopt is specified, make fastcc functions tail-callable.
2706 const MachineFunction &MF = DAG.getMachineFunction();
2707 const Function *CallerF = DAG.getMachineFunction().getFunction();
2708 CallingConv::ID CallerCC = CallerF->getCallingConv();
2709 bool CCMatch = CallerCC == CalleeCC;
2711 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2712 if (IsTailCallConvention(CalleeCC) && CCMatch)
2717 // Look for obvious safe cases to perform tail call optimization that do not
2718 // require ABI changes. This is what gcc calls sibcall.
2720 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2721 // emit a special epilogue.
2722 if (RegInfo->needsStackRealignment(MF))
2725 // Also avoid sibcall optimization if either caller or callee uses struct
2726 // return semantics.
2727 if (isCalleeStructRet || isCallerStructRet)
2730 // An stdcall caller is expected to clean up its arguments; the callee
2731 // isn't going to do that.
2732 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2735 // Do not sibcall optimize vararg calls unless all arguments are passed via
2737 if (isVarArg && !Outs.empty()) {
2739 // Optimizing for varargs on Win64 is unlikely to be safe without
2740 // additional testing.
2741 if (Subtarget->isTargetWin64())
2744 SmallVector<CCValAssign, 16> ArgLocs;
2745 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2746 getTargetMachine(), ArgLocs, *DAG.getContext());
2748 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2750 if (!ArgLocs[i].isRegLoc())
2754 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2755 // stack. Therefore, if it's not used by the call it is not safe to optimize
2756 // this into a sibcall.
2757 bool Unused = false;
2758 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2765 SmallVector<CCValAssign, 16> RVLocs;
2766 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2767 getTargetMachine(), RVLocs, *DAG.getContext());
2768 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2769 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2770 CCValAssign &VA = RVLocs[i];
2771 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2776 // If the calling conventions do not match, then we'd better make sure the
2777 // results are returned in the same way as what the caller expects.
2779 SmallVector<CCValAssign, 16> RVLocs1;
2780 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2781 getTargetMachine(), RVLocs1, *DAG.getContext());
2782 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2784 SmallVector<CCValAssign, 16> RVLocs2;
2785 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2786 getTargetMachine(), RVLocs2, *DAG.getContext());
2787 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2789 if (RVLocs1.size() != RVLocs2.size())
2791 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2792 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2794 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2796 if (RVLocs1[i].isRegLoc()) {
2797 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2800 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2806 // If the callee takes no arguments then go on to check the results of the
2808 if (!Outs.empty()) {
2809 // Check if stack adjustment is needed. For now, do not do this if any
2810 // argument is passed on the stack.
2811 SmallVector<CCValAssign, 16> ArgLocs;
2812 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2813 getTargetMachine(), ArgLocs, *DAG.getContext());
2815 // Allocate shadow area for Win64
2816 if (Subtarget->isTargetWin64()) {
2817 CCInfo.AllocateStack(32, 8);
2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2821 if (CCInfo.getNextStackOffset()) {
2822 MachineFunction &MF = DAG.getMachineFunction();
2823 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2826 // Check if the arguments are already laid out in the right way as
2827 // the caller's fixed stack objects.
2828 MachineFrameInfo *MFI = MF.getFrameInfo();
2829 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2830 const X86InstrInfo *TII =
2831 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2832 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2833 CCValAssign &VA = ArgLocs[i];
2834 SDValue Arg = OutVals[i];
2835 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2836 if (VA.getLocInfo() == CCValAssign::Indirect)
2838 if (!VA.isRegLoc()) {
2839 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2846 // If the tailcall address may be in a register, then make sure it's
2847 // possible to register allocate for it. In 32-bit, the call address can
2848 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2849 // callee-saved registers are restored. These happen to be the same
2850 // registers used to pass 'inreg' arguments so watch out for those.
2851 if (!Subtarget->is64Bit() &&
2852 !isa<GlobalAddressSDNode>(Callee) &&
2853 !isa<ExternalSymbolSDNode>(Callee)) {
2854 unsigned NumInRegs = 0;
2855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2856 CCValAssign &VA = ArgLocs[i];
2859 unsigned Reg = VA.getLocReg();
2862 case X86::EAX: case X86::EDX: case X86::ECX:
2863 if (++NumInRegs == 3)
2875 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2876 return X86::createFastISel(funcInfo);
2880 //===----------------------------------------------------------------------===//
2881 // Other Lowering Hooks
2882 //===----------------------------------------------------------------------===//
2884 static bool MayFoldLoad(SDValue Op) {
2885 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2888 static bool MayFoldIntoStore(SDValue Op) {
2889 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2892 static bool isTargetShuffle(unsigned Opcode) {
2894 default: return false;
2895 case X86ISD::PSHUFD:
2896 case X86ISD::PSHUFHW:
2897 case X86ISD::PSHUFLW:
2899 case X86ISD::PALIGN:
2900 case X86ISD::MOVLHPS:
2901 case X86ISD::MOVLHPD:
2902 case X86ISD::MOVHLPS:
2903 case X86ISD::MOVLPS:
2904 case X86ISD::MOVLPD:
2905 case X86ISD::MOVSHDUP:
2906 case X86ISD::MOVSLDUP:
2907 case X86ISD::MOVDDUP:
2910 case X86ISD::UNPCKL:
2911 case X86ISD::UNPCKH:
2912 case X86ISD::VPERMILP:
2913 case X86ISD::VPERM2X128:
2918 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2919 SDValue V1, SelectionDAG &DAG) {
2921 default: llvm_unreachable("Unknown x86 shuffle node");
2922 case X86ISD::MOVSHDUP:
2923 case X86ISD::MOVSLDUP:
2924 case X86ISD::MOVDDUP:
2925 return DAG.getNode(Opc, dl, VT, V1);
2929 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2930 SDValue V1, unsigned TargetMask,
2931 SelectionDAG &DAG) {
2933 default: llvm_unreachable("Unknown x86 shuffle node");
2934 case X86ISD::PSHUFD:
2935 case X86ISD::PSHUFHW:
2936 case X86ISD::PSHUFLW:
2937 case X86ISD::VPERMILP:
2938 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2942 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2943 SDValue V1, SDValue V2, unsigned TargetMask,
2944 SelectionDAG &DAG) {
2946 default: llvm_unreachable("Unknown x86 shuffle node");
2947 case X86ISD::PALIGN:
2949 case X86ISD::VPERM2X128:
2950 return DAG.getNode(Opc, dl, VT, V1, V2,
2951 DAG.getConstant(TargetMask, MVT::i8));
2955 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2956 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2958 default: llvm_unreachable("Unknown x86 shuffle node");
2959 case X86ISD::MOVLHPS:
2960 case X86ISD::MOVLHPD:
2961 case X86ISD::MOVHLPS:
2962 case X86ISD::MOVLPS:
2963 case X86ISD::MOVLPD:
2966 case X86ISD::UNPCKL:
2967 case X86ISD::UNPCKH:
2968 return DAG.getNode(Opc, dl, VT, V1, V2);
2972 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2973 MachineFunction &MF = DAG.getMachineFunction();
2974 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2975 int ReturnAddrIndex = FuncInfo->getRAIndex();
2977 if (ReturnAddrIndex == 0) {
2978 // Set up a frame object for the return address.
2979 uint64_t SlotSize = TD->getPointerSize();
2980 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2982 FuncInfo->setRAIndex(ReturnAddrIndex);
2985 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2989 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2990 bool hasSymbolicDisplacement) {
2991 // Offset should fit into 32 bit immediate field.
2992 if (!isInt<32>(Offset))
2995 // If we don't have a symbolic displacement - we don't have any extra
2997 if (!hasSymbolicDisplacement)
3000 // FIXME: Some tweaks might be needed for medium code model.
3001 if (M != CodeModel::Small && M != CodeModel::Kernel)
3004 // For small code model we assume that latest object is 16MB before end of 31
3005 // bits boundary. We may also accept pretty large negative constants knowing
3006 // that all objects are in the positive half of address space.
3007 if (M == CodeModel::Small && Offset < 16*1024*1024)
3010 // For kernel code model we know that all object resist in the negative half
3011 // of 32bits address space. We may not accept negative offsets, since they may
3012 // be just off and we may accept pretty large positive ones.
3013 if (M == CodeModel::Kernel && Offset > 0)
3019 /// isCalleePop - Determines whether the callee is required to pop its
3020 /// own arguments. Callee pop is necessary to support tail calls.
3021 bool X86::isCalleePop(CallingConv::ID CallingConv,
3022 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3026 switch (CallingConv) {
3029 case CallingConv::X86_StdCall:
3031 case CallingConv::X86_FastCall:
3033 case CallingConv::X86_ThisCall:
3035 case CallingConv::Fast:
3037 case CallingConv::GHC:
3042 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3043 /// specific condition code, returning the condition code and the LHS/RHS of the
3044 /// comparison to make.
3045 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3046 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3048 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3049 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3050 // X > -1 -> X == 0, jump !sign.
3051 RHS = DAG.getConstant(0, RHS.getValueType());
3052 return X86::COND_NS;
3053 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3054 // X < 0 -> X == 0, jump on sign.
3056 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3058 RHS = DAG.getConstant(0, RHS.getValueType());
3059 return X86::COND_LE;
3063 switch (SetCCOpcode) {
3064 default: llvm_unreachable("Invalid integer condition!");
3065 case ISD::SETEQ: return X86::COND_E;
3066 case ISD::SETGT: return X86::COND_G;
3067 case ISD::SETGE: return X86::COND_GE;
3068 case ISD::SETLT: return X86::COND_L;
3069 case ISD::SETLE: return X86::COND_LE;
3070 case ISD::SETNE: return X86::COND_NE;
3071 case ISD::SETULT: return X86::COND_B;
3072 case ISD::SETUGT: return X86::COND_A;
3073 case ISD::SETULE: return X86::COND_BE;
3074 case ISD::SETUGE: return X86::COND_AE;
3078 // First determine if it is required or is profitable to flip the operands.
3080 // If LHS is a foldable load, but RHS is not, flip the condition.
3081 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3082 !ISD::isNON_EXTLoad(RHS.getNode())) {
3083 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3084 std::swap(LHS, RHS);
3087 switch (SetCCOpcode) {
3093 std::swap(LHS, RHS);
3097 // On a floating point condition, the flags are set as follows:
3099 // 0 | 0 | 0 | X > Y
3100 // 0 | 0 | 1 | X < Y
3101 // 1 | 0 | 0 | X == Y
3102 // 1 | 1 | 1 | unordered
3103 switch (SetCCOpcode) {
3104 default: llvm_unreachable("Condcode should be pre-legalized away");
3106 case ISD::SETEQ: return X86::COND_E;
3107 case ISD::SETOLT: // flipped
3109 case ISD::SETGT: return X86::COND_A;
3110 case ISD::SETOLE: // flipped
3112 case ISD::SETGE: return X86::COND_AE;
3113 case ISD::SETUGT: // flipped
3115 case ISD::SETLT: return X86::COND_B;
3116 case ISD::SETUGE: // flipped
3118 case ISD::SETLE: return X86::COND_BE;
3120 case ISD::SETNE: return X86::COND_NE;
3121 case ISD::SETUO: return X86::COND_P;
3122 case ISD::SETO: return X86::COND_NP;
3124 case ISD::SETUNE: return X86::COND_INVALID;
3128 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3129 /// code. Current x86 isa includes the following FP cmov instructions:
3130 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3131 static bool hasFPCMov(unsigned X86CC) {
3147 /// isFPImmLegal - Returns true if the target can instruction select the
3148 /// specified FP immediate natively. If false, the legalizer will
3149 /// materialize the FP immediate as a load from a constant pool.
3150 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3151 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3152 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3158 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3159 /// the specified range (L, H].
3160 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3161 return (Val < 0) || (Val >= Low && Val < Hi);
3164 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3165 /// specified value.
3166 static bool isUndefOrEqual(int Val, int CmpVal) {
3167 if (Val < 0 || Val == CmpVal)
3172 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3173 /// from position Pos and ending in Pos+Size, falls within the specified
3174 /// sequential range (L, L+Pos]. or is undef.
3175 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3176 int Pos, int Size, int Low) {
3177 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3178 if (!isUndefOrEqual(Mask[i], Low))
3183 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3184 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3185 /// the second operand.
3186 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3187 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3188 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3189 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3190 return (Mask[0] < 2 && Mask[1] < 2);
3194 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3195 /// is suitable for input to PSHUFHW.
3196 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3197 if (VT != MVT::v8i16)
3200 // Lower quadword copied in order or undef.
3201 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3204 // Upper quadword shuffled.
3205 for (unsigned i = 4; i != 8; ++i)
3206 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3212 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3213 /// is suitable for input to PSHUFLW.
3214 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3215 if (VT != MVT::v8i16)
3218 // Upper quadword copied in order.
3219 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3222 // Lower quadword shuffled.
3223 for (unsigned i = 0; i != 4; ++i)
3230 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3231 /// is suitable for input to PALIGNR.
3232 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3233 const X86Subtarget *Subtarget) {
3234 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3235 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3238 unsigned NumElts = VT.getVectorNumElements();
3239 unsigned NumLanes = VT.getSizeInBits()/128;
3240 unsigned NumLaneElts = NumElts/NumLanes;
3242 // Do not handle 64-bit element shuffles with palignr.
3243 if (NumLaneElts == 2)
3246 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3248 for (i = 0; i != NumLaneElts; ++i) {
3253 // Lane is all undef, go to next lane
3254 if (i == NumLaneElts)
3257 int Start = Mask[i+l];
3259 // Make sure its in this lane in one of the sources
3260 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3261 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3264 // If not lane 0, then we must match lane 0
3265 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3268 // Correct second source to be contiguous with first source
3269 if (Start >= (int)NumElts)
3270 Start -= NumElts - NumLaneElts;
3272 // Make sure we're shifting in the right direction.
3273 if (Start <= (int)(i+l))
3278 // Check the rest of the elements to see if they are consecutive.
3279 for (++i; i != NumLaneElts; ++i) {
3280 int Idx = Mask[i+l];
3282 // Make sure its in this lane
3283 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3284 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3287 // If not lane 0, then we must match lane 0
3288 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3291 if (Idx >= (int)NumElts)
3292 Idx -= NumElts - NumLaneElts;
3294 if (!isUndefOrEqual(Idx, Start+i))
3303 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3304 /// the two vector operands have swapped position.
3305 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3306 unsigned NumElems) {
3307 for (unsigned i = 0; i != NumElems; ++i) {
3311 else if (idx < (int)NumElems)
3312 Mask[i] = idx + NumElems;
3314 Mask[i] = idx - NumElems;
3318 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3319 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3320 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3321 /// reverse of what x86 shuffles want.
3322 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3323 bool Commuted = false) {
3324 if (!HasAVX && VT.getSizeInBits() == 256)
3327 unsigned NumElems = VT.getVectorNumElements();
3328 unsigned NumLanes = VT.getSizeInBits()/128;
3329 unsigned NumLaneElems = NumElems/NumLanes;
3331 if (NumLaneElems != 2 && NumLaneElems != 4)
3334 // VSHUFPSY divides the resulting vector into 4 chunks.
3335 // The sources are also splitted into 4 chunks, and each destination
3336 // chunk must come from a different source chunk.
3338 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3339 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3341 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3342 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3344 // VSHUFPDY divides the resulting vector into 4 chunks.
3345 // The sources are also splitted into 4 chunks, and each destination
3346 // chunk must come from a different source chunk.
3348 // SRC1 => X3 X2 X1 X0
3349 // SRC2 => Y3 Y2 Y1 Y0
3351 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3353 unsigned HalfLaneElems = NumLaneElems/2;
3354 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3355 for (unsigned i = 0; i != NumLaneElems; ++i) {
3356 int Idx = Mask[i+l];
3357 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3358 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3360 // For VSHUFPSY, the mask of the second half must be the same as the
3361 // first but with the appropriate offsets. This works in the same way as
3362 // VPERMILPS works with masks.
3363 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3365 if (!isUndefOrEqual(Idx, Mask[i]+l))
3373 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3374 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3375 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3376 unsigned NumElems = VT.getVectorNumElements();
3378 if (VT.getSizeInBits() != 128)
3384 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3385 return isUndefOrEqual(Mask[0], 6) &&
3386 isUndefOrEqual(Mask[1], 7) &&
3387 isUndefOrEqual(Mask[2], 2) &&
3388 isUndefOrEqual(Mask[3], 3);
3391 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3392 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3394 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3395 unsigned NumElems = VT.getVectorNumElements();
3397 if (VT.getSizeInBits() != 128)
3403 return isUndefOrEqual(Mask[0], 2) &&
3404 isUndefOrEqual(Mask[1], 3) &&
3405 isUndefOrEqual(Mask[2], 2) &&
3406 isUndefOrEqual(Mask[3], 3);
3409 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3410 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3411 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3412 if (VT.getSizeInBits() != 128)
3415 unsigned NumElems = VT.getVectorNumElements();
3417 if (NumElems != 2 && NumElems != 4)
3420 for (unsigned i = 0; i != NumElems/2; ++i)
3421 if (!isUndefOrEqual(Mask[i], i + NumElems))
3424 for (unsigned i = NumElems/2; i != NumElems; ++i)
3425 if (!isUndefOrEqual(Mask[i], i))
3431 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3432 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3433 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3434 unsigned NumElems = VT.getVectorNumElements();
3436 if ((NumElems != 2 && NumElems != 4)
3437 || VT.getSizeInBits() > 128)
3440 for (unsigned i = 0; i != NumElems/2; ++i)
3441 if (!isUndefOrEqual(Mask[i], i))
3444 for (unsigned i = 0; i != NumElems/2; ++i)
3445 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3451 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3452 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3453 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3454 bool HasAVX2, bool V2IsSplat = false) {
3455 unsigned NumElts = VT.getVectorNumElements();
3457 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3458 "Unsupported vector type for unpckh");
3460 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3461 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3464 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3465 // independently on 128-bit lanes.
3466 unsigned NumLanes = VT.getSizeInBits()/128;
3467 unsigned NumLaneElts = NumElts/NumLanes;
3469 for (unsigned l = 0; l != NumLanes; ++l) {
3470 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3471 i != (l+1)*NumLaneElts;
3474 int BitI1 = Mask[i+1];
3475 if (!isUndefOrEqual(BitI, j))
3478 if (!isUndefOrEqual(BitI1, NumElts))
3481 if (!isUndefOrEqual(BitI1, j + NumElts))
3490 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3491 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3492 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3493 bool HasAVX2, bool V2IsSplat = false) {
3494 unsigned NumElts = VT.getVectorNumElements();
3496 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3497 "Unsupported vector type for unpckh");
3499 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3500 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3503 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3504 // independently on 128-bit lanes.
3505 unsigned NumLanes = VT.getSizeInBits()/128;
3506 unsigned NumLaneElts = NumElts/NumLanes;
3508 for (unsigned l = 0; l != NumLanes; ++l) {
3509 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3510 i != (l+1)*NumLaneElts; i += 2, ++j) {
3512 int BitI1 = Mask[i+1];
3513 if (!isUndefOrEqual(BitI, j))
3516 if (isUndefOrEqual(BitI1, NumElts))
3519 if (!isUndefOrEqual(BitI1, j+NumElts))
3527 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3528 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3530 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3532 unsigned NumElts = VT.getVectorNumElements();
3534 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3535 "Unsupported vector type for unpckh");
3537 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3538 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3541 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3542 // FIXME: Need a better way to get rid of this, there's no latency difference
3543 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3544 // the former later. We should also remove the "_undef" special mask.
3545 if (NumElts == 4 && VT.getSizeInBits() == 256)
3548 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3549 // independently on 128-bit lanes.
3550 unsigned NumLanes = VT.getSizeInBits()/128;
3551 unsigned NumLaneElts = NumElts/NumLanes;
3553 for (unsigned l = 0; l != NumLanes; ++l) {
3554 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3555 i != (l+1)*NumLaneElts;
3558 int BitI1 = Mask[i+1];
3560 if (!isUndefOrEqual(BitI, j))
3562 if (!isUndefOrEqual(BitI1, j))
3570 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3571 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3573 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3574 unsigned NumElts = VT.getVectorNumElements();
3576 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3577 "Unsupported vector type for unpckh");
3579 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3580 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3583 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3584 // independently on 128-bit lanes.
3585 unsigned NumLanes = VT.getSizeInBits()/128;
3586 unsigned NumLaneElts = NumElts/NumLanes;
3588 for (unsigned l = 0; l != NumLanes; ++l) {
3589 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3590 i != (l+1)*NumLaneElts; i += 2, ++j) {
3592 int BitI1 = Mask[i+1];
3593 if (!isUndefOrEqual(BitI, j))
3595 if (!isUndefOrEqual(BitI1, j))
3602 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3603 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3604 /// MOVSD, and MOVD, i.e. setting the lowest element.
3605 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3606 if (VT.getVectorElementType().getSizeInBits() < 32)
3608 if (VT.getSizeInBits() == 256)
3611 unsigned NumElts = VT.getVectorNumElements();
3613 if (!isUndefOrEqual(Mask[0], NumElts))
3616 for (unsigned i = 1; i != NumElts; ++i)
3617 if (!isUndefOrEqual(Mask[i], i))
3623 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3624 /// as permutations between 128-bit chunks or halves. As an example: this
3626 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3627 /// The first half comes from the second half of V1 and the second half from the
3628 /// the second half of V2.
3629 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3630 if (!HasAVX || VT.getSizeInBits() != 256)
3633 // The shuffle result is divided into half A and half B. In total the two
3634 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3635 // B must come from C, D, E or F.
3636 unsigned HalfSize = VT.getVectorNumElements()/2;
3637 bool MatchA = false, MatchB = false;
3639 // Check if A comes from one of C, D, E, F.
3640 for (unsigned Half = 0; Half != 4; ++Half) {
3641 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3647 // Check if B comes from one of C, D, E, F.
3648 for (unsigned Half = 0; Half != 4; ++Half) {
3649 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3655 return MatchA && MatchB;
3658 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3659 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3660 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3661 EVT VT = SVOp->getValueType(0);
3663 unsigned HalfSize = VT.getVectorNumElements()/2;
3665 unsigned FstHalf = 0, SndHalf = 0;
3666 for (unsigned i = 0; i < HalfSize; ++i) {
3667 if (SVOp->getMaskElt(i) > 0) {
3668 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3672 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3673 if (SVOp->getMaskElt(i) > 0) {
3674 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3679 return (FstHalf | (SndHalf << 4));
3682 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3683 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3684 /// Note that VPERMIL mask matching is different depending whether theunderlying
3685 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3686 /// to the same elements of the low, but to the higher half of the source.
3687 /// In VPERMILPD the two lanes could be shuffled independently of each other
3688 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3689 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3693 unsigned NumElts = VT.getVectorNumElements();
3694 // Only match 256-bit with 32/64-bit types
3695 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3698 unsigned NumLanes = VT.getSizeInBits()/128;
3699 unsigned LaneSize = NumElts/NumLanes;
3700 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3701 for (unsigned i = 0; i != LaneSize; ++i) {
3702 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3704 if (NumElts != 8 || l == 0)
3706 // VPERMILPS handling
3709 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3717 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3718 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3719 /// element of vector 2 and the other elements to come from vector 1 in order.
3720 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3721 bool V2IsSplat = false, bool V2IsUndef = false) {
3722 unsigned NumOps = VT.getVectorNumElements();
3723 if (VT.getSizeInBits() == 256)
3725 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3728 if (!isUndefOrEqual(Mask[0], 0))
3731 for (unsigned i = 1; i != NumOps; ++i)
3732 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3733 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3734 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3740 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3741 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3742 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3743 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3744 const X86Subtarget *Subtarget) {
3745 if (!Subtarget->hasSSE3())
3748 unsigned NumElems = VT.getVectorNumElements();
3750 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3751 (VT.getSizeInBits() == 256 && NumElems != 8))
3754 // "i+1" is the value the indexed mask element must have
3755 for (unsigned i = 0; i != NumElems; i += 2)
3756 if (!isUndefOrEqual(Mask[i], i+1) ||
3757 !isUndefOrEqual(Mask[i+1], i+1))
3763 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3764 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3765 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3766 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3767 const X86Subtarget *Subtarget) {
3768 if (!Subtarget->hasSSE3())
3771 unsigned NumElems = VT.getVectorNumElements();
3773 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3774 (VT.getSizeInBits() == 256 && NumElems != 8))
3777 // "i" is the value the indexed mask element must have
3778 for (unsigned i = 0; i != NumElems; i += 2)
3779 if (!isUndefOrEqual(Mask[i], i) ||
3780 !isUndefOrEqual(Mask[i+1], i))
3786 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3787 /// specifies a shuffle of elements that is suitable for input to 256-bit
3788 /// version of MOVDDUP.
3789 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3790 unsigned NumElts = VT.getVectorNumElements();
3792 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3795 for (unsigned i = 0; i != NumElts/2; ++i)
3796 if (!isUndefOrEqual(Mask[i], 0))
3798 for (unsigned i = NumElts/2; i != NumElts; ++i)
3799 if (!isUndefOrEqual(Mask[i], NumElts/2))
3804 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3805 /// specifies a shuffle of elements that is suitable for input to 128-bit
3806 /// version of MOVDDUP.
3807 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3808 if (VT.getSizeInBits() != 128)
3811 unsigned e = VT.getVectorNumElements() / 2;
3812 for (unsigned i = 0; i != e; ++i)
3813 if (!isUndefOrEqual(Mask[i], i))
3815 for (unsigned i = 0; i != e; ++i)
3816 if (!isUndefOrEqual(Mask[e+i], i))
3821 /// isVEXTRACTF128Index - Return true if the specified
3822 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3823 /// suitable for input to VEXTRACTF128.
3824 bool X86::isVEXTRACTF128Index(SDNode *N) {
3825 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3828 // The index should be aligned on a 128-bit boundary.
3830 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3832 unsigned VL = N->getValueType(0).getVectorNumElements();
3833 unsigned VBits = N->getValueType(0).getSizeInBits();
3834 unsigned ElSize = VBits / VL;
3835 bool Result = (Index * ElSize) % 128 == 0;
3840 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3841 /// operand specifies a subvector insert that is suitable for input to
3843 bool X86::isVINSERTF128Index(SDNode *N) {
3844 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3847 // The index should be aligned on a 128-bit boundary.
3849 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3851 unsigned VL = N->getValueType(0).getVectorNumElements();
3852 unsigned VBits = N->getValueType(0).getSizeInBits();
3853 unsigned ElSize = VBits / VL;
3854 bool Result = (Index * ElSize) % 128 == 0;
3859 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3860 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3861 /// Handles 128-bit and 256-bit.
3862 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3863 EVT VT = N->getValueType(0);
3865 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3866 "Unsupported vector type for PSHUF/SHUFP");
3868 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3869 // independently on 128-bit lanes.
3870 unsigned NumElts = VT.getVectorNumElements();
3871 unsigned NumLanes = VT.getSizeInBits()/128;
3872 unsigned NumLaneElts = NumElts/NumLanes;
3874 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3875 "Only supports 2 or 4 elements per lane");
3877 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3879 for (unsigned i = 0; i != NumElts; ++i) {
3880 int Elt = N->getMaskElt(i);
3881 if (Elt < 0) continue;
3883 unsigned ShAmt = i << Shift;
3884 if (ShAmt >= 8) ShAmt -= 8;
3885 Mask |= Elt << ShAmt;
3891 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3892 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3893 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3895 // 8 nodes, but we only care about the last 4.
3896 for (unsigned i = 7; i >= 4; --i) {
3897 int Val = N->getMaskElt(i);
3906 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3907 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3908 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3910 // 8 nodes, but we only care about the first 4.
3911 for (int i = 3; i >= 0; --i) {
3912 int Val = N->getMaskElt(i);
3921 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3922 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3923 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3924 EVT VT = SVOp->getValueType(0);
3925 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3927 unsigned NumElts = VT.getVectorNumElements();
3928 unsigned NumLanes = VT.getSizeInBits()/128;
3929 unsigned NumLaneElts = NumElts/NumLanes;
3933 for (i = 0; i != NumElts; ++i) {
3934 Val = SVOp->getMaskElt(i);
3938 if (Val >= (int)NumElts)
3939 Val -= NumElts - NumLaneElts;
3941 assert(Val - i > 0 && "PALIGNR imm should be positive");
3942 return (Val - i) * EltSize;
3945 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3946 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3948 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3949 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3950 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3953 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3955 EVT VecVT = N->getOperand(0).getValueType();
3956 EVT ElVT = VecVT.getVectorElementType();
3958 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3959 return Index / NumElemsPerChunk;
3962 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3963 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3965 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3966 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3967 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3970 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3972 EVT VecVT = N->getValueType(0);
3973 EVT ElVT = VecVT.getVectorElementType();
3975 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3976 return Index / NumElemsPerChunk;
3979 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3981 bool X86::isZeroNode(SDValue Elt) {
3982 return ((isa<ConstantSDNode>(Elt) &&
3983 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3984 (isa<ConstantFPSDNode>(Elt) &&
3985 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3988 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3989 /// their permute mask.
3990 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3991 SelectionDAG &DAG) {
3992 EVT VT = SVOp->getValueType(0);
3993 unsigned NumElems = VT.getVectorNumElements();
3994 SmallVector<int, 8> MaskVec;
3996 for (unsigned i = 0; i != NumElems; ++i) {
3997 int idx = SVOp->getMaskElt(i);
3999 MaskVec.push_back(idx);
4000 else if (idx < (int)NumElems)
4001 MaskVec.push_back(idx + NumElems);
4003 MaskVec.push_back(idx - NumElems);
4005 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4006 SVOp->getOperand(0), &MaskVec[0]);
4009 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4010 /// match movhlps. The lower half elements should come from upper half of
4011 /// V1 (and in order), and the upper half elements should come from the upper
4012 /// half of V2 (and in order).
4013 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4014 if (VT.getSizeInBits() != 128)
4016 if (VT.getVectorNumElements() != 4)
4018 for (unsigned i = 0, e = 2; i != e; ++i)
4019 if (!isUndefOrEqual(Mask[i], i+2))
4021 for (unsigned i = 2; i != 4; ++i)
4022 if (!isUndefOrEqual(Mask[i], i+4))
4027 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4028 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4030 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4031 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4033 N = N->getOperand(0).getNode();
4034 if (!ISD::isNON_EXTLoad(N))
4037 *LD = cast<LoadSDNode>(N);
4041 // Test whether the given value is a vector value which will be legalized
4043 static bool WillBeConstantPoolLoad(SDNode *N) {
4044 if (N->getOpcode() != ISD::BUILD_VECTOR)
4047 // Check for any non-constant elements.
4048 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4049 switch (N->getOperand(i).getNode()->getOpcode()) {
4051 case ISD::ConstantFP:
4058 // Vectors of all-zeros and all-ones are materialized with special
4059 // instructions rather than being loaded.
4060 return !ISD::isBuildVectorAllZeros(N) &&
4061 !ISD::isBuildVectorAllOnes(N);
4064 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4065 /// match movlp{s|d}. The lower half elements should come from lower half of
4066 /// V1 (and in order), and the upper half elements should come from the upper
4067 /// half of V2 (and in order). And since V1 will become the source of the
4068 /// MOVLP, it must be either a vector load or a scalar load to vector.
4069 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4070 ArrayRef<int> Mask, EVT VT) {
4071 if (VT.getSizeInBits() != 128)
4074 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4076 // Is V2 is a vector load, don't do this transformation. We will try to use
4077 // load folding shufps op.
4078 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4081 unsigned NumElems = VT.getVectorNumElements();
4083 if (NumElems != 2 && NumElems != 4)
4085 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4086 if (!isUndefOrEqual(Mask[i], i))
4088 for (unsigned i = NumElems/2; i != NumElems; ++i)
4089 if (!isUndefOrEqual(Mask[i], i+NumElems))
4094 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4096 static bool isSplatVector(SDNode *N) {
4097 if (N->getOpcode() != ISD::BUILD_VECTOR)
4100 SDValue SplatValue = N->getOperand(0);
4101 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4102 if (N->getOperand(i) != SplatValue)
4107 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4108 /// to an zero vector.
4109 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4110 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4111 SDValue V1 = N->getOperand(0);
4112 SDValue V2 = N->getOperand(1);
4113 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4114 for (unsigned i = 0; i != NumElems; ++i) {
4115 int Idx = N->getMaskElt(i);
4116 if (Idx >= (int)NumElems) {
4117 unsigned Opc = V2.getOpcode();
4118 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4120 if (Opc != ISD::BUILD_VECTOR ||
4121 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4123 } else if (Idx >= 0) {
4124 unsigned Opc = V1.getOpcode();
4125 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4127 if (Opc != ISD::BUILD_VECTOR ||
4128 !X86::isZeroNode(V1.getOperand(Idx)))
4135 /// getZeroVector - Returns a vector of specified type with all zero elements.
4137 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4138 SelectionDAG &DAG, DebugLoc dl) {
4139 assert(VT.isVector() && "Expected a vector type");
4141 // Always build SSE zero vectors as <4 x i32> bitcasted
4142 // to their dest type. This ensures they get CSE'd.
4144 if (VT.getSizeInBits() == 128) { // SSE
4145 if (Subtarget->hasSSE2()) { // SSE2
4146 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4147 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4149 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4150 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4152 } else if (VT.getSizeInBits() == 256) { // AVX
4153 if (Subtarget->hasAVX2()) { // AVX2
4154 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4155 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4156 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4158 // 256-bit logic and arithmetic instructions in AVX are all
4159 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4160 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4161 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4162 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4165 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4168 /// getOnesVector - Returns a vector of specified type with all bits set.
4169 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4170 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4171 /// Then bitcast to their original type, ensuring they get CSE'd.
4172 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4174 assert(VT.isVector() && "Expected a vector type");
4175 assert((VT.is128BitVector() || VT.is256BitVector())
4176 && "Expected a 128-bit or 256-bit vector type");
4178 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4180 if (VT.getSizeInBits() == 256) {
4181 if (HasAVX2) { // AVX2
4182 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4183 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4185 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4186 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4187 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4188 Vec = Insert128BitVector(InsV, Vec,
4189 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4192 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4195 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4198 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4199 /// that point to V2 points to its first element.
4200 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4201 for (unsigned i = 0; i != NumElems; ++i) {
4202 if (Mask[i] > (int)NumElems) {
4208 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4209 /// operation of specified width.
4210 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4212 unsigned NumElems = VT.getVectorNumElements();
4213 SmallVector<int, 8> Mask;
4214 Mask.push_back(NumElems);
4215 for (unsigned i = 1; i != NumElems; ++i)
4217 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4220 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4221 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4223 unsigned NumElems = VT.getVectorNumElements();
4224 SmallVector<int, 8> Mask;
4225 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4227 Mask.push_back(i + NumElems);
4229 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4232 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4233 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4235 unsigned NumElems = VT.getVectorNumElements();
4236 unsigned Half = NumElems/2;
4237 SmallVector<int, 8> Mask;
4238 for (unsigned i = 0; i != Half; ++i) {
4239 Mask.push_back(i + Half);
4240 Mask.push_back(i + NumElems + Half);
4242 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4245 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4246 // a generic shuffle instruction because the target has no such instructions.
4247 // Generate shuffles which repeat i16 and i8 several times until they can be
4248 // represented by v4f32 and then be manipulated by target suported shuffles.
4249 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4250 EVT VT = V.getValueType();
4251 int NumElems = VT.getVectorNumElements();
4252 DebugLoc dl = V.getDebugLoc();
4254 while (NumElems > 4) {
4255 if (EltNo < NumElems/2) {
4256 V = getUnpackl(DAG, dl, VT, V, V);
4258 V = getUnpackh(DAG, dl, VT, V, V);
4259 EltNo -= NumElems/2;
4266 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4267 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4268 EVT VT = V.getValueType();
4269 DebugLoc dl = V.getDebugLoc();
4270 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4271 && "Vector size not supported");
4273 if (VT.getSizeInBits() == 128) {
4274 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4275 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4276 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4279 // To use VPERMILPS to splat scalars, the second half of indicies must
4280 // refer to the higher part, which is a duplication of the lower one,
4281 // because VPERMILPS can only handle in-lane permutations.
4282 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4283 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4285 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4286 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4290 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4293 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4294 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4295 EVT SrcVT = SV->getValueType(0);
4296 SDValue V1 = SV->getOperand(0);
4297 DebugLoc dl = SV->getDebugLoc();
4299 int EltNo = SV->getSplatIndex();
4300 int NumElems = SrcVT.getVectorNumElements();
4301 unsigned Size = SrcVT.getSizeInBits();
4303 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4304 "Unknown how to promote splat for type");
4306 // Extract the 128-bit part containing the splat element and update
4307 // the splat element index when it refers to the higher register.
4309 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4310 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4312 EltNo -= NumElems/2;
4315 // All i16 and i8 vector types can't be used directly by a generic shuffle
4316 // instruction because the target has no such instruction. Generate shuffles
4317 // which repeat i16 and i8 several times until they fit in i32, and then can
4318 // be manipulated by target suported shuffles.
4319 EVT EltVT = SrcVT.getVectorElementType();
4320 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4321 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4323 // Recreate the 256-bit vector and place the same 128-bit vector
4324 // into the low and high part. This is necessary because we want
4325 // to use VPERM* to shuffle the vectors
4327 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4328 DAG.getConstant(0, MVT::i32), DAG, dl);
4329 V1 = Insert128BitVector(InsV, V1,
4330 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4333 return getLegalSplat(DAG, V1, EltNo);
4336 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4337 /// vector of zero or undef vector. This produces a shuffle where the low
4338 /// element of V2 is swizzled into the zero/undef vector, landing at element
4339 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4340 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4342 const X86Subtarget *Subtarget,
4343 SelectionDAG &DAG) {
4344 EVT VT = V2.getValueType();
4346 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4347 unsigned NumElems = VT.getVectorNumElements();
4348 SmallVector<int, 16> MaskVec;
4349 for (unsigned i = 0; i != NumElems; ++i)
4350 // If this is the insertion idx, put the low elt of V2 here.
4351 MaskVec.push_back(i == Idx ? NumElems : i);
4352 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4355 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4356 /// target specific opcode. Returns true if the Mask could be calculated.
4357 /// Sets IsUnary to true if only uses one source.
4358 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4359 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4360 unsigned NumElems = VT.getVectorNumElements();
4364 switch(N->getOpcode()) {
4366 ImmN = N->getOperand(N->getNumOperands()-1);
4367 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4369 case X86ISD::UNPCKH:
4370 DecodeUNPCKHMask(VT, Mask);
4372 case X86ISD::UNPCKL:
4373 DecodeUNPCKLMask(VT, Mask);
4375 case X86ISD::MOVHLPS:
4376 DecodeMOVHLPSMask(NumElems, Mask);
4378 case X86ISD::MOVLHPS:
4379 DecodeMOVLHPSMask(NumElems, Mask);
4381 case X86ISD::PSHUFD:
4382 case X86ISD::VPERMILP:
4383 ImmN = N->getOperand(N->getNumOperands()-1);
4384 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4387 case X86ISD::PSHUFHW:
4388 ImmN = N->getOperand(N->getNumOperands()-1);
4389 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4392 case X86ISD::PSHUFLW:
4393 ImmN = N->getOperand(N->getNumOperands()-1);
4394 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4398 case X86ISD::MOVSD: {
4399 // The index 0 always comes from the first element of the second source,
4400 // this is why MOVSS and MOVSD are used in the first place. The other
4401 // elements come from the other positions of the first source vector
4402 Mask.push_back(NumElems);
4403 for (unsigned i = 1; i != NumElems; ++i) {
4408 case X86ISD::VPERM2X128:
4409 ImmN = N->getOperand(N->getNumOperands()-1);
4410 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4412 case X86ISD::MOVDDUP:
4413 case X86ISD::MOVLHPD:
4414 case X86ISD::MOVLPD:
4415 case X86ISD::MOVLPS:
4416 case X86ISD::MOVSHDUP:
4417 case X86ISD::MOVSLDUP:
4418 case X86ISD::PALIGN:
4419 // Not yet implemented
4421 default: llvm_unreachable("unknown target shuffle node");
4427 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4428 /// element of the result of the vector shuffle.
4429 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4432 return SDValue(); // Limit search depth.
4434 SDValue V = SDValue(N, 0);
4435 EVT VT = V.getValueType();
4436 unsigned Opcode = V.getOpcode();
4438 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4439 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4440 int Elt = SV->getMaskElt(Index);
4443 return DAG.getUNDEF(VT.getVectorElementType());
4445 unsigned NumElems = VT.getVectorNumElements();
4446 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4447 : SV->getOperand(1);
4448 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4451 // Recurse into target specific vector shuffles to find scalars.
4452 if (isTargetShuffle(Opcode)) {
4453 unsigned NumElems = VT.getVectorNumElements();
4454 SmallVector<int, 16> ShuffleMask;
4458 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4461 int Elt = ShuffleMask[Index];
4463 return DAG.getUNDEF(VT.getVectorElementType());
4465 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4467 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4471 // Actual nodes that may contain scalar elements
4472 if (Opcode == ISD::BITCAST) {
4473 V = V.getOperand(0);
4474 EVT SrcVT = V.getValueType();
4475 unsigned NumElems = VT.getVectorNumElements();
4477 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4481 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4482 return (Index == 0) ? V.getOperand(0)
4483 : DAG.getUNDEF(VT.getVectorElementType());
4485 if (V.getOpcode() == ISD::BUILD_VECTOR)
4486 return V.getOperand(Index);
4491 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4492 /// shuffle operation which come from a consecutively from a zero. The
4493 /// search can start in two different directions, from left or right.
4495 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4496 bool ZerosFromLeft, SelectionDAG &DAG) {
4498 for (i = 0; i != NumElems; ++i) {
4499 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4500 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4501 if (!(Elt.getNode() &&
4502 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4509 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4510 /// correspond consecutively to elements from one of the vector operands,
4511 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4513 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4514 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4515 unsigned NumElems, unsigned &OpNum) {
4516 bool SeenV1 = false;
4517 bool SeenV2 = false;
4519 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4520 int Idx = SVOp->getMaskElt(i);
4521 // Ignore undef indicies
4525 if (Idx < (int)NumElems)
4530 // Only accept consecutive elements from the same vector
4531 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4535 OpNum = SeenV1 ? 0 : 1;
4539 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4540 /// logical left shift of a vector.
4541 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4542 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4543 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4544 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4545 false /* check zeros from right */, DAG);
4551 // Considering the elements in the mask that are not consecutive zeros,
4552 // check if they consecutively come from only one of the source vectors.
4554 // V1 = {X, A, B, C} 0
4556 // vector_shuffle V1, V2 <1, 2, 3, X>
4558 if (!isShuffleMaskConsecutive(SVOp,
4559 0, // Mask Start Index
4560 NumElems-NumZeros, // Mask End Index(exclusive)
4561 NumZeros, // Where to start looking in the src vector
4562 NumElems, // Number of elements in vector
4563 OpSrc)) // Which source operand ?
4568 ShVal = SVOp->getOperand(OpSrc);
4572 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4573 /// logical left shift of a vector.
4574 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4575 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4576 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4577 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4578 true /* check zeros from left */, DAG);
4584 // Considering the elements in the mask that are not consecutive zeros,
4585 // check if they consecutively come from only one of the source vectors.
4587 // 0 { A, B, X, X } = V2
4589 // vector_shuffle V1, V2 <X, X, 4, 5>
4591 if (!isShuffleMaskConsecutive(SVOp,
4592 NumZeros, // Mask Start Index
4593 NumElems, // Mask End Index(exclusive)
4594 0, // Where to start looking in the src vector
4595 NumElems, // Number of elements in vector
4596 OpSrc)) // Which source operand ?
4601 ShVal = SVOp->getOperand(OpSrc);
4605 /// isVectorShift - Returns true if the shuffle can be implemented as a
4606 /// logical left or right shift of a vector.
4607 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4609 // Although the logic below support any bitwidth size, there are no
4610 // shift instructions which handle more than 128-bit vectors.
4611 if (SVOp->getValueType(0).getSizeInBits() > 128)
4614 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4615 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4621 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4623 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4624 unsigned NumNonZero, unsigned NumZero,
4626 const X86Subtarget* Subtarget,
4627 const TargetLowering &TLI) {
4631 DebugLoc dl = Op.getDebugLoc();
4634 for (unsigned i = 0; i < 16; ++i) {
4635 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4636 if (ThisIsNonZero && First) {
4638 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4640 V = DAG.getUNDEF(MVT::v8i16);
4645 SDValue ThisElt(0, 0), LastElt(0, 0);
4646 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4647 if (LastIsNonZero) {
4648 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4649 MVT::i16, Op.getOperand(i-1));
4651 if (ThisIsNonZero) {
4652 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4653 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4654 ThisElt, DAG.getConstant(8, MVT::i8));
4656 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4660 if (ThisElt.getNode())
4661 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4662 DAG.getIntPtrConstant(i/2));
4666 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4669 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4671 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4672 unsigned NumNonZero, unsigned NumZero,
4674 const X86Subtarget* Subtarget,
4675 const TargetLowering &TLI) {
4679 DebugLoc dl = Op.getDebugLoc();
4682 for (unsigned i = 0; i < 8; ++i) {
4683 bool isNonZero = (NonZeros & (1 << i)) != 0;
4687 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4689 V = DAG.getUNDEF(MVT::v8i16);
4692 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4693 MVT::v8i16, V, Op.getOperand(i),
4694 DAG.getIntPtrConstant(i));
4701 /// getVShift - Return a vector logical shift node.
4703 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4704 unsigned NumBits, SelectionDAG &DAG,
4705 const TargetLowering &TLI, DebugLoc dl) {
4706 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4707 EVT ShVT = MVT::v2i64;
4708 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4709 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4710 return DAG.getNode(ISD::BITCAST, dl, VT,
4711 DAG.getNode(Opc, dl, ShVT, SrcOp,
4712 DAG.getConstant(NumBits,
4713 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4717 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4718 SelectionDAG &DAG) const {
4720 // Check if the scalar load can be widened into a vector load. And if
4721 // the address is "base + cst" see if the cst can be "absorbed" into
4722 // the shuffle mask.
4723 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4724 SDValue Ptr = LD->getBasePtr();
4725 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4727 EVT PVT = LD->getValueType(0);
4728 if (PVT != MVT::i32 && PVT != MVT::f32)
4733 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4734 FI = FINode->getIndex();
4736 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4737 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4738 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4739 Offset = Ptr.getConstantOperandVal(1);
4740 Ptr = Ptr.getOperand(0);
4745 // FIXME: 256-bit vector instructions don't require a strict alignment,
4746 // improve this code to support it better.
4747 unsigned RequiredAlign = VT.getSizeInBits()/8;
4748 SDValue Chain = LD->getChain();
4749 // Make sure the stack object alignment is at least 16 or 32.
4750 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4751 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4752 if (MFI->isFixedObjectIndex(FI)) {
4753 // Can't change the alignment. FIXME: It's possible to compute
4754 // the exact stack offset and reference FI + adjust offset instead.
4755 // If someone *really* cares about this. That's the way to implement it.
4758 MFI->setObjectAlignment(FI, RequiredAlign);
4762 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4763 // Ptr + (Offset & ~15).
4766 if ((Offset % RequiredAlign) & 3)
4768 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4770 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4771 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4773 int EltNo = (Offset - StartOffset) >> 2;
4774 int NumElems = VT.getVectorNumElements();
4776 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4777 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4778 LD->getPointerInfo().getWithOffset(StartOffset),
4779 false, false, false, 0);
4781 SmallVector<int, 8> Mask;
4782 for (int i = 0; i < NumElems; ++i)
4783 Mask.push_back(EltNo);
4785 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4791 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4792 /// vector of type 'VT', see if the elements can be replaced by a single large
4793 /// load which has the same value as a build_vector whose operands are 'elts'.
4795 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4797 /// FIXME: we'd also like to handle the case where the last elements are zero
4798 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4799 /// There's even a handy isZeroNode for that purpose.
4800 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4801 DebugLoc &DL, SelectionDAG &DAG) {
4802 EVT EltVT = VT.getVectorElementType();
4803 unsigned NumElems = Elts.size();
4805 LoadSDNode *LDBase = NULL;
4806 unsigned LastLoadedElt = -1U;
4808 // For each element in the initializer, see if we've found a load or an undef.
4809 // If we don't find an initial load element, or later load elements are
4810 // non-consecutive, bail out.
4811 for (unsigned i = 0; i < NumElems; ++i) {
4812 SDValue Elt = Elts[i];
4814 if (!Elt.getNode() ||
4815 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4818 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4820 LDBase = cast<LoadSDNode>(Elt.getNode());
4824 if (Elt.getOpcode() == ISD::UNDEF)
4827 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4828 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4833 // If we have found an entire vector of loads and undefs, then return a large
4834 // load of the entire vector width starting at the base pointer. If we found
4835 // consecutive loads for the low half, generate a vzext_load node.
4836 if (LastLoadedElt == NumElems - 1) {
4837 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4838 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4839 LDBase->getPointerInfo(),
4840 LDBase->isVolatile(), LDBase->isNonTemporal(),
4841 LDBase->isInvariant(), 0);
4842 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4843 LDBase->getPointerInfo(),
4844 LDBase->isVolatile(), LDBase->isNonTemporal(),
4845 LDBase->isInvariant(), LDBase->getAlignment());
4846 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4847 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4848 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4849 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4851 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4852 LDBase->getPointerInfo(),
4853 LDBase->getAlignment(),
4854 false/*isVolatile*/, true/*ReadMem*/,
4856 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4861 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4862 /// to generate a splat value for the following cases:
4863 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4864 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4865 /// a scalar load, or a constant.
4866 /// The VBROADCAST node is returned when a pattern is found,
4867 /// or SDValue() otherwise.
4869 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4870 if (!Subtarget->hasAVX())
4873 EVT VT = Op.getValueType();
4874 DebugLoc dl = Op.getDebugLoc();
4879 switch (Op.getOpcode()) {
4881 // Unknown pattern found.
4884 case ISD::BUILD_VECTOR: {
4885 // The BUILD_VECTOR node must be a splat.
4886 if (!isSplatVector(Op.getNode()))
4889 Ld = Op.getOperand(0);
4890 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4891 Ld.getOpcode() == ISD::ConstantFP);
4893 // The suspected load node has several users. Make sure that all
4894 // of its users are from the BUILD_VECTOR node.
4895 // Constants may have multiple users.
4896 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4901 case ISD::VECTOR_SHUFFLE: {
4902 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4904 // Shuffles must have a splat mask where the first element is
4906 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4909 SDValue Sc = Op.getOperand(0);
4910 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4913 Ld = Sc.getOperand(0);
4914 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4915 Ld.getOpcode() == ISD::ConstantFP);
4917 // The scalar_to_vector node and the suspected
4918 // load node must have exactly one user.
4919 // Constants may have multiple users.
4920 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
4926 bool Is256 = VT.getSizeInBits() == 256;
4927 bool Is128 = VT.getSizeInBits() == 128;
4929 // Handle the broadcasting a single constant scalar from the constant pool
4930 // into a vector. On Sandybridge it is still better to load a constant vector
4931 // from the constant pool and not to broadcast it from a scalar.
4932 if (ConstSplatVal && Subtarget->hasAVX2()) {
4933 EVT CVT = Ld.getValueType();
4934 assert(!CVT.isVector() && "Must not broadcast a vector type");
4935 unsigned ScalarSize = CVT.getSizeInBits();
4937 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) ||
4938 (Is128 && (ScalarSize == 32))) {
4940 const Constant *C = 0;
4941 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4942 C = CI->getConstantIntValue();
4943 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4944 C = CF->getConstantFPValue();
4946 assert(C && "Invalid constant type");
4948 SDValue CP = DAG.getConstantPool(C, getPointerTy());
4949 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4950 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4951 MachinePointerInfo::getConstantPool(),
4952 false, false, false, Alignment);
4954 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4958 // The scalar source must be a normal load.
4959 if (!ISD::isNormalLoad(Ld.getNode()))
4962 // Reject loads that have uses of the chain result
4963 if (Ld->hasAnyUseOfValue(1))
4966 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4968 // VBroadcast to YMM
4969 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4970 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4972 // VBroadcast to XMM
4973 if (Is128 && (ScalarSize == 32))
4974 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4976 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4977 // double since there is vbroadcastsd xmm
4978 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
4979 // VBroadcast to YMM
4980 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
4981 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4983 // VBroadcast to XMM
4984 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
4985 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4988 // Unsupported broadcast.
4993 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4994 DebugLoc dl = Op.getDebugLoc();
4996 EVT VT = Op.getValueType();
4997 EVT ExtVT = VT.getVectorElementType();
4998 unsigned NumElems = Op.getNumOperands();
5000 // Vectors containing all zeros can be matched by pxor and xorps later
5001 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5002 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5003 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5004 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5007 return getZeroVector(VT, Subtarget, DAG, dl);
5010 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5011 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5012 // vpcmpeqd on 256-bit vectors.
5013 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5014 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5017 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5020 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5021 if (Broadcast.getNode())
5024 unsigned EVTBits = ExtVT.getSizeInBits();
5026 unsigned NumZero = 0;
5027 unsigned NumNonZero = 0;
5028 unsigned NonZeros = 0;
5029 bool IsAllConstants = true;
5030 SmallSet<SDValue, 8> Values;
5031 for (unsigned i = 0; i < NumElems; ++i) {
5032 SDValue Elt = Op.getOperand(i);
5033 if (Elt.getOpcode() == ISD::UNDEF)
5036 if (Elt.getOpcode() != ISD::Constant &&
5037 Elt.getOpcode() != ISD::ConstantFP)
5038 IsAllConstants = false;
5039 if (X86::isZeroNode(Elt))
5042 NonZeros |= (1 << i);
5047 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5048 if (NumNonZero == 0)
5049 return DAG.getUNDEF(VT);
5051 // Special case for single non-zero, non-undef, element.
5052 if (NumNonZero == 1) {
5053 unsigned Idx = CountTrailingZeros_32(NonZeros);
5054 SDValue Item = Op.getOperand(Idx);
5056 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5057 // the value are obviously zero, truncate the value to i32 and do the
5058 // insertion that way. Only do this if the value is non-constant or if the
5059 // value is a constant being inserted into element 0. It is cheaper to do
5060 // a constant pool load than it is to do a movd + shuffle.
5061 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5062 (!IsAllConstants || Idx == 0)) {
5063 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5065 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5066 EVT VecVT = MVT::v4i32;
5067 unsigned VecElts = 4;
5069 // Truncate the value (which may itself be a constant) to i32, and
5070 // convert it to a vector with movd (S2V+shuffle to zero extend).
5071 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5072 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5073 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5075 // Now we have our 32-bit value zero extended in the low element of
5076 // a vector. If Idx != 0, swizzle it into place.
5078 SmallVector<int, 4> Mask;
5079 Mask.push_back(Idx);
5080 for (unsigned i = 1; i != VecElts; ++i)
5082 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5083 DAG.getUNDEF(Item.getValueType()),
5086 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5090 // If we have a constant or non-constant insertion into the low element of
5091 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5092 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5093 // depending on what the source datatype is.
5096 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5098 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5099 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5100 if (VT.getSizeInBits() == 256) {
5101 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5102 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5103 Item, DAG.getIntPtrConstant(0));
5105 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5106 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5107 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5108 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5111 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5112 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5113 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5114 if (VT.getSizeInBits() == 256) {
5115 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5116 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5119 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5120 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5122 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5126 // Is it a vector logical left shift?
5127 if (NumElems == 2 && Idx == 1 &&
5128 X86::isZeroNode(Op.getOperand(0)) &&
5129 !X86::isZeroNode(Op.getOperand(1))) {
5130 unsigned NumBits = VT.getSizeInBits();
5131 return getVShift(true, VT,
5132 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5133 VT, Op.getOperand(1)),
5134 NumBits/2, DAG, *this, dl);
5137 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5140 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5141 // is a non-constant being inserted into an element other than the low one,
5142 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5143 // movd/movss) to move this into the low element, then shuffle it into
5145 if (EVTBits == 32) {
5146 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5148 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5149 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5150 SmallVector<int, 8> MaskVec;
5151 for (unsigned i = 0; i < NumElems; i++)
5152 MaskVec.push_back(i == Idx ? 0 : 1);
5153 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5157 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5158 if (Values.size() == 1) {
5159 if (EVTBits == 32) {
5160 // Instead of a shuffle like this:
5161 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5162 // Check if it's possible to issue this instead.
5163 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5164 unsigned Idx = CountTrailingZeros_32(NonZeros);
5165 SDValue Item = Op.getOperand(Idx);
5166 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5167 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5172 // A vector full of immediates; various special cases are already
5173 // handled, so this is best done with a single constant-pool load.
5177 // For AVX-length vectors, build the individual 128-bit pieces and use
5178 // shuffles to put them in place.
5179 if (VT.getSizeInBits() == 256) {
5180 SmallVector<SDValue, 32> V;
5181 for (unsigned i = 0; i != NumElems; ++i)
5182 V.push_back(Op.getOperand(i));
5184 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5186 // Build both the lower and upper subvector.
5187 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5188 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5191 // Recreate the wider vector with the lower and upper part.
5192 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5193 DAG.getConstant(0, MVT::i32), DAG, dl);
5194 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5198 // Let legalizer expand 2-wide build_vectors.
5199 if (EVTBits == 64) {
5200 if (NumNonZero == 1) {
5201 // One half is zero or undef.
5202 unsigned Idx = CountTrailingZeros_32(NonZeros);
5203 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5204 Op.getOperand(Idx));
5205 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5210 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5211 if (EVTBits == 8 && NumElems == 16) {
5212 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5214 if (V.getNode()) return V;
5217 if (EVTBits == 16 && NumElems == 8) {
5218 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5220 if (V.getNode()) return V;
5223 // If element VT is == 32 bits, turn it into a number of shuffles.
5224 SmallVector<SDValue, 8> V(NumElems);
5225 if (NumElems == 4 && NumZero > 0) {
5226 for (unsigned i = 0; i < 4; ++i) {
5227 bool isZero = !(NonZeros & (1 << i));
5229 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5231 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5234 for (unsigned i = 0; i < 2; ++i) {
5235 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5238 V[i] = V[i*2]; // Must be a zero vector.
5241 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5244 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5247 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5252 bool Reverse1 = (NonZeros & 0x3) == 2;
5253 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5257 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5258 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5260 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5263 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5264 // Check for a build vector of consecutive loads.
5265 for (unsigned i = 0; i < NumElems; ++i)
5266 V[i] = Op.getOperand(i);
5268 // Check for elements which are consecutive loads.
5269 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5273 // For SSE 4.1, use insertps to put the high elements into the low element.
5274 if (getSubtarget()->hasSSE41()) {
5276 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5277 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5279 Result = DAG.getUNDEF(VT);
5281 for (unsigned i = 1; i < NumElems; ++i) {
5282 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5283 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5284 Op.getOperand(i), DAG.getIntPtrConstant(i));
5289 // Otherwise, expand into a number of unpckl*, start by extending each of
5290 // our (non-undef) elements to the full vector width with the element in the
5291 // bottom slot of the vector (which generates no code for SSE).
5292 for (unsigned i = 0; i < NumElems; ++i) {
5293 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5294 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5296 V[i] = DAG.getUNDEF(VT);
5299 // Next, we iteratively mix elements, e.g. for v4f32:
5300 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5301 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5302 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5303 unsigned EltStride = NumElems >> 1;
5304 while (EltStride != 0) {
5305 for (unsigned i = 0; i < EltStride; ++i) {
5306 // If V[i+EltStride] is undef and this is the first round of mixing,
5307 // then it is safe to just drop this shuffle: V[i] is already in the
5308 // right place, the one element (since it's the first round) being
5309 // inserted as undef can be dropped. This isn't safe for successive
5310 // rounds because they will permute elements within both vectors.
5311 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5312 EltStride == NumElems/2)
5315 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5324 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5325 // them in a MMX register. This is better than doing a stack convert.
5326 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5327 DebugLoc dl = Op.getDebugLoc();
5328 EVT ResVT = Op.getValueType();
5330 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5331 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5333 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5334 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5335 InVec = Op.getOperand(1);
5336 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5337 unsigned NumElts = ResVT.getVectorNumElements();
5338 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5339 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5340 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5342 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5343 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5344 Mask[0] = 0; Mask[1] = 2;
5345 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5347 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5350 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5351 // to create 256-bit vectors from two other 128-bit ones.
5352 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5353 DebugLoc dl = Op.getDebugLoc();
5354 EVT ResVT = Op.getValueType();
5356 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5358 SDValue V1 = Op.getOperand(0);
5359 SDValue V2 = Op.getOperand(1);
5360 unsigned NumElems = ResVT.getVectorNumElements();
5362 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5363 DAG.getConstant(0, MVT::i32), DAG, dl);
5364 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5369 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5370 EVT ResVT = Op.getValueType();
5372 assert(Op.getNumOperands() == 2);
5373 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5374 "Unsupported CONCAT_VECTORS for value type");
5376 // We support concatenate two MMX registers and place them in a MMX register.
5377 // This is better than doing a stack convert.
5378 if (ResVT.is128BitVector())
5379 return LowerMMXCONCAT_VECTORS(Op, DAG);
5381 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5382 // from two other 128-bit ones.
5383 return LowerAVXCONCAT_VECTORS(Op, DAG);
5386 // Try to lower a shuffle node into a simple blend instruction.
5387 static SDValue LowerVECTOR_SHUFFLEtoBlend(SDValue Op,
5388 const X86Subtarget *Subtarget,
5389 SelectionDAG &DAG, EVT PtrTy) {
5390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5391 SDValue V1 = SVOp->getOperand(0);
5392 SDValue V2 = SVOp->getOperand(1);
5393 DebugLoc dl = SVOp->getDebugLoc();
5394 EVT VT = Op.getValueType();
5395 EVT InVT = V1.getValueType();
5396 EVT EltVT = VT.getVectorElementType();
5397 int MaskSize = VT.getVectorNumElements();
5398 int InSize = InVT.getVectorNumElements();
5400 if (!Subtarget->hasSSE41())
5403 if (MaskSize != InSize)
5409 switch (VT.getSimpleVT().SimpleTy) {
5410 default: return SDValue();
5412 ISDNo = X86ISD::BLENDPW;
5417 ISDNo = X86ISD::BLENDPS;
5422 ISDNo = X86ISD::BLENDPD;
5427 if (!Subtarget->hasAVX())
5429 ISDNo = X86ISD::BLENDPS;
5434 if (!Subtarget->hasAVX())
5436 ISDNo = X86ISD::BLENDPD;
5440 if (!Subtarget->hasAVX2())
5442 ISDNo = X86ISD::BLENDPW;
5446 assert(ISDNo && "Invalid Op Number");
5448 unsigned MaskVals = 0;
5450 for (int i = 0; i < MaskSize; ++i) {
5451 int EltIdx = SVOp->getMaskElt(i);
5452 if (EltIdx == i || EltIdx == -1)
5454 else if (EltIdx == (i + MaskSize))
5455 continue; // Bit is set to zero;
5456 else return SDValue();
5459 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5460 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5461 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5462 DAG.getConstant(MaskVals, MVT::i32));
5463 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5466 // v8i16 shuffles - Prefer shuffles in the following order:
5467 // 1. [all] pshuflw, pshufhw, optional move
5468 // 2. [ssse3] 1 x pshufb
5469 // 3. [ssse3] 2 x pshufb + 1 x por
5470 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5472 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5473 SelectionDAG &DAG) const {
5474 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5475 SDValue V1 = SVOp->getOperand(0);
5476 SDValue V2 = SVOp->getOperand(1);
5477 DebugLoc dl = SVOp->getDebugLoc();
5478 SmallVector<int, 8> MaskVals;
5480 // Determine if more than 1 of the words in each of the low and high quadwords
5481 // of the result come from the same quadword of one of the two inputs. Undef
5482 // mask values count as coming from any quadword, for better codegen.
5483 unsigned LoQuad[] = { 0, 0, 0, 0 };
5484 unsigned HiQuad[] = { 0, 0, 0, 0 };
5485 std::bitset<4> InputQuads;
5486 for (unsigned i = 0; i < 8; ++i) {
5487 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5488 int EltIdx = SVOp->getMaskElt(i);
5489 MaskVals.push_back(EltIdx);
5498 InputQuads.set(EltIdx / 4);
5501 int BestLoQuad = -1;
5502 unsigned MaxQuad = 1;
5503 for (unsigned i = 0; i < 4; ++i) {
5504 if (LoQuad[i] > MaxQuad) {
5506 MaxQuad = LoQuad[i];
5510 int BestHiQuad = -1;
5512 for (unsigned i = 0; i < 4; ++i) {
5513 if (HiQuad[i] > MaxQuad) {
5515 MaxQuad = HiQuad[i];
5519 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5520 // of the two input vectors, shuffle them into one input vector so only a
5521 // single pshufb instruction is necessary. If There are more than 2 input
5522 // quads, disable the next transformation since it does not help SSSE3.
5523 bool V1Used = InputQuads[0] || InputQuads[1];
5524 bool V2Used = InputQuads[2] || InputQuads[3];
5525 if (Subtarget->hasSSSE3()) {
5526 if (InputQuads.count() == 2 && V1Used && V2Used) {
5527 BestLoQuad = InputQuads[0] ? 0 : 1;
5528 BestHiQuad = InputQuads[2] ? 2 : 3;
5530 if (InputQuads.count() > 2) {
5536 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5537 // the shuffle mask. If a quad is scored as -1, that means that it contains
5538 // words from all 4 input quadwords.
5540 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5542 BestLoQuad < 0 ? 0 : BestLoQuad,
5543 BestHiQuad < 0 ? 1 : BestHiQuad
5545 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5546 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5547 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5548 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5550 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5551 // source words for the shuffle, to aid later transformations.
5552 bool AllWordsInNewV = true;
5553 bool InOrder[2] = { true, true };
5554 for (unsigned i = 0; i != 8; ++i) {
5555 int idx = MaskVals[i];
5557 InOrder[i/4] = false;
5558 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5560 AllWordsInNewV = false;
5564 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5565 if (AllWordsInNewV) {
5566 for (int i = 0; i != 8; ++i) {
5567 int idx = MaskVals[i];
5570 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5571 if ((idx != i) && idx < 4)
5573 if ((idx != i) && idx > 3)
5582 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5583 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5584 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5585 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5586 unsigned TargetMask = 0;
5587 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5588 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5589 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5590 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5591 getShufflePSHUFLWImmediate(SVOp);
5592 V1 = NewV.getOperand(0);
5593 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5597 // If we have SSSE3, and all words of the result are from 1 input vector,
5598 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5599 // is present, fall back to case 4.
5600 if (Subtarget->hasSSSE3()) {
5601 SmallVector<SDValue,16> pshufbMask;
5603 // If we have elements from both input vectors, set the high bit of the
5604 // shuffle mask element to zero out elements that come from V2 in the V1
5605 // mask, and elements that come from V1 in the V2 mask, so that the two
5606 // results can be OR'd together.
5607 bool TwoInputs = V1Used && V2Used;
5608 for (unsigned i = 0; i != 8; ++i) {
5609 int EltIdx = MaskVals[i] * 2;
5610 if (TwoInputs && (EltIdx >= 16)) {
5611 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5612 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5615 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5616 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5618 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5619 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5620 DAG.getNode(ISD::BUILD_VECTOR, dl,
5621 MVT::v16i8, &pshufbMask[0], 16));
5623 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5625 // Calculate the shuffle mask for the second input, shuffle it, and
5626 // OR it with the first shuffled input.
5628 for (unsigned i = 0; i != 8; ++i) {
5629 int EltIdx = MaskVals[i] * 2;
5631 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5632 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5635 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5636 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5638 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5639 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5640 DAG.getNode(ISD::BUILD_VECTOR, dl,
5641 MVT::v16i8, &pshufbMask[0], 16));
5642 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5643 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5646 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5647 // and update MaskVals with new element order.
5648 std::bitset<8> InOrder;
5649 if (BestLoQuad >= 0) {
5650 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5651 for (int i = 0; i != 4; ++i) {
5652 int idx = MaskVals[i];
5655 } else if ((idx / 4) == BestLoQuad) {
5660 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5663 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5664 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5665 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5667 getShufflePSHUFLWImmediate(SVOp), DAG);
5671 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5672 // and update MaskVals with the new element order.
5673 if (BestHiQuad >= 0) {
5674 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5675 for (unsigned i = 4; i != 8; ++i) {
5676 int idx = MaskVals[i];
5679 } else if ((idx / 4) == BestHiQuad) {
5680 MaskV[i] = (idx & 3) + 4;
5684 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5687 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5688 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5689 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5691 getShufflePSHUFHWImmediate(SVOp), DAG);
5695 // In case BestHi & BestLo were both -1, which means each quadword has a word
5696 // from each of the four input quadwords, calculate the InOrder bitvector now
5697 // before falling through to the insert/extract cleanup.
5698 if (BestLoQuad == -1 && BestHiQuad == -1) {
5700 for (int i = 0; i != 8; ++i)
5701 if (MaskVals[i] < 0 || MaskVals[i] == i)
5705 // The other elements are put in the right place using pextrw and pinsrw.
5706 for (unsigned i = 0; i != 8; ++i) {
5709 int EltIdx = MaskVals[i];
5712 SDValue ExtOp = (EltIdx < 8)
5713 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5714 DAG.getIntPtrConstant(EltIdx))
5715 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5716 DAG.getIntPtrConstant(EltIdx - 8));
5717 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5718 DAG.getIntPtrConstant(i));
5723 // v16i8 shuffles - Prefer shuffles in the following order:
5724 // 1. [ssse3] 1 x pshufb
5725 // 2. [ssse3] 2 x pshufb + 1 x por
5726 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5728 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5730 const X86TargetLowering &TLI) {
5731 SDValue V1 = SVOp->getOperand(0);
5732 SDValue V2 = SVOp->getOperand(1);
5733 DebugLoc dl = SVOp->getDebugLoc();
5734 ArrayRef<int> MaskVals = SVOp->getMask();
5736 // If we have SSSE3, case 1 is generated when all result bytes come from
5737 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5738 // present, fall back to case 3.
5739 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5742 for (unsigned i = 0; i < 16; ++i) {
5743 int EltIdx = MaskVals[i];
5752 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5753 if (TLI.getSubtarget()->hasSSSE3()) {
5754 SmallVector<SDValue,16> pshufbMask;
5756 // If all result elements are from one input vector, then only translate
5757 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5759 // Otherwise, we have elements from both input vectors, and must zero out
5760 // elements that come from V2 in the first mask, and V1 in the second mask
5761 // so that we can OR them together.
5762 bool TwoInputs = !(V1Only || V2Only);
5763 for (unsigned i = 0; i != 16; ++i) {
5764 int EltIdx = MaskVals[i];
5765 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5766 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5769 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5771 // If all the elements are from V2, assign it to V1 and return after
5772 // building the first pshufb.
5775 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5776 DAG.getNode(ISD::BUILD_VECTOR, dl,
5777 MVT::v16i8, &pshufbMask[0], 16));
5781 // Calculate the shuffle mask for the second input, shuffle it, and
5782 // OR it with the first shuffled input.
5784 for (unsigned i = 0; i != 16; ++i) {
5785 int EltIdx = MaskVals[i];
5787 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5790 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5792 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5793 DAG.getNode(ISD::BUILD_VECTOR, dl,
5794 MVT::v16i8, &pshufbMask[0], 16));
5795 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5798 // No SSSE3 - Calculate in place words and then fix all out of place words
5799 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5800 // the 16 different words that comprise the two doublequadword input vectors.
5801 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5802 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5803 SDValue NewV = V2Only ? V2 : V1;
5804 for (int i = 0; i != 8; ++i) {
5805 int Elt0 = MaskVals[i*2];
5806 int Elt1 = MaskVals[i*2+1];
5808 // This word of the result is all undef, skip it.
5809 if (Elt0 < 0 && Elt1 < 0)
5812 // This word of the result is already in the correct place, skip it.
5813 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5815 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5818 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5819 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5822 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5823 // using a single extract together, load it and store it.
5824 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5825 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5826 DAG.getIntPtrConstant(Elt1 / 2));
5827 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5828 DAG.getIntPtrConstant(i));
5832 // If Elt1 is defined, extract it from the appropriate source. If the
5833 // source byte is not also odd, shift the extracted word left 8 bits
5834 // otherwise clear the bottom 8 bits if we need to do an or.
5836 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5837 DAG.getIntPtrConstant(Elt1 / 2));
5838 if ((Elt1 & 1) == 0)
5839 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5841 TLI.getShiftAmountTy(InsElt.getValueType())));
5843 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5844 DAG.getConstant(0xFF00, MVT::i16));
5846 // If Elt0 is defined, extract it from the appropriate source. If the
5847 // source byte is not also even, shift the extracted word right 8 bits. If
5848 // Elt1 was also defined, OR the extracted values together before
5849 // inserting them in the result.
5851 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5852 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5853 if ((Elt0 & 1) != 0)
5854 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5856 TLI.getShiftAmountTy(InsElt0.getValueType())));
5858 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5859 DAG.getConstant(0x00FF, MVT::i16));
5860 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5863 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5864 DAG.getIntPtrConstant(i));
5866 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5869 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5870 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5871 /// done when every pair / quad of shuffle mask elements point to elements in
5872 /// the right sequence. e.g.
5873 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5875 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5876 SelectionDAG &DAG, DebugLoc dl) {
5877 EVT VT = SVOp->getValueType(0);
5878 SDValue V1 = SVOp->getOperand(0);
5879 SDValue V2 = SVOp->getOperand(1);
5880 unsigned NumElems = VT.getVectorNumElements();
5881 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5883 switch (VT.getSimpleVT().SimpleTy) {
5884 default: llvm_unreachable("Unexpected!");
5885 case MVT::v4f32: NewVT = MVT::v2f64; break;
5886 case MVT::v4i32: NewVT = MVT::v2i64; break;
5887 case MVT::v8i16: NewVT = MVT::v4i32; break;
5888 case MVT::v16i8: NewVT = MVT::v4i32; break;
5891 int Scale = NumElems / NewWidth;
5892 SmallVector<int, 8> MaskVec;
5893 for (unsigned i = 0; i < NumElems; i += Scale) {
5895 for (int j = 0; j < Scale; ++j) {
5896 int EltIdx = SVOp->getMaskElt(i+j);
5900 StartIdx = EltIdx - (EltIdx % Scale);
5901 if (EltIdx != StartIdx + j)
5905 MaskVec.push_back(-1);
5907 MaskVec.push_back(StartIdx / Scale);
5910 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5911 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5912 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5915 /// getVZextMovL - Return a zero-extending vector move low node.
5917 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5918 SDValue SrcOp, SelectionDAG &DAG,
5919 const X86Subtarget *Subtarget, DebugLoc dl) {
5920 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5921 LoadSDNode *LD = NULL;
5922 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5923 LD = dyn_cast<LoadSDNode>(SrcOp);
5925 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5927 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5928 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5929 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5930 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5931 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5933 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5934 return DAG.getNode(ISD::BITCAST, dl, VT,
5935 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5936 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5944 return DAG.getNode(ISD::BITCAST, dl, VT,
5945 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5946 DAG.getNode(ISD::BITCAST, dl,
5950 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5951 /// which could not be matched by any known target speficic shuffle
5953 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5954 EVT VT = SVOp->getValueType(0);
5956 unsigned NumElems = VT.getVectorNumElements();
5957 unsigned NumLaneElems = NumElems / 2;
5959 DebugLoc dl = SVOp->getDebugLoc();
5960 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5961 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5964 SmallVector<int, 16> Mask;
5965 for (unsigned l = 0; l < 2; ++l) {
5966 // Build a shuffle mask for the output, discovering on the fly which
5967 // input vectors to use as shuffle operands (recorded in InputUsed).
5968 // If building a suitable shuffle vector proves too hard, then bail
5969 // out with useBuildVector set.
5970 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5971 unsigned LaneStart = l * NumLaneElems;
5972 for (unsigned i = 0; i != NumLaneElems; ++i) {
5973 // The mask element. This indexes into the input.
5974 int Idx = SVOp->getMaskElt(i+LaneStart);
5976 // the mask element does not index into any input vector.
5981 // The input vector this mask element indexes into.
5982 int Input = Idx / NumLaneElems;
5984 // Turn the index into an offset from the start of the input vector.
5985 Idx -= Input * NumLaneElems;
5987 // Find or create a shuffle vector operand to hold this input.
5989 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
5990 if (InputUsed[OpNo] == Input)
5991 // This input vector is already an operand.
5993 if (InputUsed[OpNo] < 0) {
5994 // Create a new operand for this input vector.
5995 InputUsed[OpNo] = Input;
6000 if (OpNo >= array_lengthof(InputUsed)) {
6001 // More than two input vectors used! Give up.
6005 // Add the mask index for the new shuffle vector.
6006 Mask.push_back(Idx + OpNo * NumLaneElems);
6009 if (InputUsed[0] < 0) {
6010 // No input vectors were used! The result is undefined.
6011 Shufs[l] = DAG.getUNDEF(NVT);
6013 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6014 DAG.getConstant((InputUsed[0] % 2) * NumLaneElems, MVT::i32),
6016 // If only one input was used, use an undefined vector for the other.
6017 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6018 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6019 DAG.getConstant((InputUsed[1] % 2) * NumLaneElems, MVT::i32),
6021 // At least one input vector was used. Create a new shuffle vector.
6022 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6028 // Concatenate the result back
6029 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shufs[0],
6030 DAG.getConstant(0, MVT::i32), DAG, dl);
6031 return Insert128BitVector(V, Shufs[1],DAG.getConstant(NumLaneElems, MVT::i32),
6035 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6036 /// 4 elements, and match them with several different shuffle types.
6038 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6039 SDValue V1 = SVOp->getOperand(0);
6040 SDValue V2 = SVOp->getOperand(1);
6041 DebugLoc dl = SVOp->getDebugLoc();
6042 EVT VT = SVOp->getValueType(0);
6044 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6046 std::pair<int, int> Locs[4];
6047 int Mask1[] = { -1, -1, -1, -1 };
6048 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6052 for (unsigned i = 0; i != 4; ++i) {
6053 int Idx = PermMask[i];
6055 Locs[i] = std::make_pair(-1, -1);
6057 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6059 Locs[i] = std::make_pair(0, NumLo);
6063 Locs[i] = std::make_pair(1, NumHi);
6065 Mask1[2+NumHi] = Idx;
6071 if (NumLo <= 2 && NumHi <= 2) {
6072 // If no more than two elements come from either vector. This can be
6073 // implemented with two shuffles. First shuffle gather the elements.
6074 // The second shuffle, which takes the first shuffle as both of its
6075 // vector operands, put the elements into the right order.
6076 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6078 int Mask2[] = { -1, -1, -1, -1 };
6080 for (unsigned i = 0; i != 4; ++i)
6081 if (Locs[i].first != -1) {
6082 unsigned Idx = (i < 2) ? 0 : 4;
6083 Idx += Locs[i].first * 2 + Locs[i].second;
6087 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6088 } else if (NumLo == 3 || NumHi == 3) {
6089 // Otherwise, we must have three elements from one vector, call it X, and
6090 // one element from the other, call it Y. First, use a shufps to build an
6091 // intermediate vector with the one element from Y and the element from X
6092 // that will be in the same half in the final destination (the indexes don't
6093 // matter). Then, use a shufps to build the final vector, taking the half
6094 // containing the element from Y from the intermediate, and the other half
6097 // Normalize it so the 3 elements come from V1.
6098 CommuteVectorShuffleMask(PermMask, 4);
6102 // Find the element from V2.
6104 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6105 int Val = PermMask[HiIndex];
6112 Mask1[0] = PermMask[HiIndex];
6114 Mask1[2] = PermMask[HiIndex^1];
6116 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6119 Mask1[0] = PermMask[0];
6120 Mask1[1] = PermMask[1];
6121 Mask1[2] = HiIndex & 1 ? 6 : 4;
6122 Mask1[3] = HiIndex & 1 ? 4 : 6;
6123 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6125 Mask1[0] = HiIndex & 1 ? 2 : 0;
6126 Mask1[1] = HiIndex & 1 ? 0 : 2;
6127 Mask1[2] = PermMask[2];
6128 Mask1[3] = PermMask[3];
6133 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6137 // Break it into (shuffle shuffle_hi, shuffle_lo).
6138 int LoMask[] = { -1, -1, -1, -1 };
6139 int HiMask[] = { -1, -1, -1, -1 };
6141 int *MaskPtr = LoMask;
6142 unsigned MaskIdx = 0;
6145 for (unsigned i = 0; i != 4; ++i) {
6152 int Idx = PermMask[i];
6154 Locs[i] = std::make_pair(-1, -1);
6155 } else if (Idx < 4) {
6156 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6157 MaskPtr[LoIdx] = Idx;
6160 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6161 MaskPtr[HiIdx] = Idx;
6166 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6167 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6168 int MaskOps[] = { -1, -1, -1, -1 };
6169 for (unsigned i = 0; i != 4; ++i)
6170 if (Locs[i].first != -1)
6171 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6172 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6175 static bool MayFoldVectorLoad(SDValue V) {
6176 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6177 V = V.getOperand(0);
6178 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6179 V = V.getOperand(0);
6180 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6181 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6182 // BUILD_VECTOR (load), undef
6183 V = V.getOperand(0);
6189 // FIXME: the version above should always be used. Since there's
6190 // a bug where several vector shuffles can't be folded because the
6191 // DAG is not updated during lowering and a node claims to have two
6192 // uses while it only has one, use this version, and let isel match
6193 // another instruction if the load really happens to have more than
6194 // one use. Remove this version after this bug get fixed.
6195 // rdar://8434668, PR8156
6196 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6197 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6198 V = V.getOperand(0);
6199 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6200 V = V.getOperand(0);
6201 if (ISD::isNormalLoad(V.getNode()))
6207 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6208 EVT VT = Op.getValueType();
6210 // Canonizalize to v2f64.
6211 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6212 return DAG.getNode(ISD::BITCAST, dl, VT,
6213 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6218 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6220 SDValue V1 = Op.getOperand(0);
6221 SDValue V2 = Op.getOperand(1);
6222 EVT VT = Op.getValueType();
6224 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6226 if (HasSSE2 && VT == MVT::v2f64)
6227 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6229 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6230 return DAG.getNode(ISD::BITCAST, dl, VT,
6231 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6232 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6233 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6237 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6238 SDValue V1 = Op.getOperand(0);
6239 SDValue V2 = Op.getOperand(1);
6240 EVT VT = Op.getValueType();
6242 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6243 "unsupported shuffle type");
6245 if (V2.getOpcode() == ISD::UNDEF)
6249 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6253 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6254 SDValue V1 = Op.getOperand(0);
6255 SDValue V2 = Op.getOperand(1);
6256 EVT VT = Op.getValueType();
6257 unsigned NumElems = VT.getVectorNumElements();
6259 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6260 // operand of these instructions is only memory, so check if there's a
6261 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6263 bool CanFoldLoad = false;
6265 // Trivial case, when V2 comes from a load.
6266 if (MayFoldVectorLoad(V2))
6269 // When V1 is a load, it can be folded later into a store in isel, example:
6270 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6272 // (MOVLPSmr addr:$src1, VR128:$src2)
6273 // So, recognize this potential and also use MOVLPS or MOVLPD
6274 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6277 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6279 if (HasSSE2 && NumElems == 2)
6280 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6283 // If we don't care about the second element, procede to use movss.
6284 if (SVOp->getMaskElt(1) != -1)
6285 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6288 // movl and movlp will both match v2i64, but v2i64 is never matched by
6289 // movl earlier because we make it strict to avoid messing with the movlp load
6290 // folding logic (see the code above getMOVLP call). Match it here then,
6291 // this is horrible, but will stay like this until we move all shuffle
6292 // matching to x86 specific nodes. Note that for the 1st condition all
6293 // types are matched with movsd.
6295 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6296 // as to remove this logic from here, as much as possible
6297 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6298 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6299 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6302 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6304 // Invert the operand order and use SHUFPS to match it.
6305 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6306 getShuffleSHUFImmediate(SVOp), DAG);
6310 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6312 EVT VT = Op.getValueType();
6313 DebugLoc dl = Op.getDebugLoc();
6314 SDValue V1 = Op.getOperand(0);
6315 SDValue V2 = Op.getOperand(1);
6317 if (isZeroShuffle(SVOp))
6318 return getZeroVector(VT, Subtarget, DAG, dl);
6320 // Handle splat operations
6321 if (SVOp->isSplat()) {
6322 unsigned NumElem = VT.getVectorNumElements();
6323 int Size = VT.getSizeInBits();
6325 // Use vbroadcast whenever the splat comes from a foldable load
6326 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6327 if (Broadcast.getNode())
6330 // Handle splats by matching through known shuffle masks
6331 if ((Size == 128 && NumElem <= 4) ||
6332 (Size == 256 && NumElem < 8))
6335 // All remaning splats are promoted to target supported vector shuffles.
6336 return PromoteSplat(SVOp, DAG);
6339 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6341 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6342 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6343 if (NewOp.getNode())
6344 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6345 } else if ((VT == MVT::v4i32 ||
6346 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6347 // FIXME: Figure out a cleaner way to do this.
6348 // Try to make use of movq to zero out the top part.
6349 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6350 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6351 if (NewOp.getNode()) {
6352 EVT NewVT = NewOp.getValueType();
6353 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6354 NewVT, true, false))
6355 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6356 DAG, Subtarget, dl);
6358 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6359 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6360 if (NewOp.getNode()) {
6361 EVT NewVT = NewOp.getValueType();
6362 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6363 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6364 DAG, Subtarget, dl);
6372 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6373 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6374 SDValue V1 = Op.getOperand(0);
6375 SDValue V2 = Op.getOperand(1);
6376 EVT VT = Op.getValueType();
6377 DebugLoc dl = Op.getDebugLoc();
6378 unsigned NumElems = VT.getVectorNumElements();
6379 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6380 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6381 bool V1IsSplat = false;
6382 bool V2IsSplat = false;
6383 bool HasSSE2 = Subtarget->hasSSE2();
6384 bool HasAVX = Subtarget->hasAVX();
6385 bool HasAVX2 = Subtarget->hasAVX2();
6386 MachineFunction &MF = DAG.getMachineFunction();
6387 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6389 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6391 if (V1IsUndef && V2IsUndef)
6392 return DAG.getUNDEF(VT);
6394 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6396 // Vector shuffle lowering takes 3 steps:
6398 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6399 // narrowing and commutation of operands should be handled.
6400 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6402 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6403 // so the shuffle can be broken into other shuffles and the legalizer can
6404 // try the lowering again.
6406 // The general idea is that no vector_shuffle operation should be left to
6407 // be matched during isel, all of them must be converted to a target specific
6410 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6411 // narrowing and commutation of operands should be handled. The actual code
6412 // doesn't include all of those, work in progress...
6413 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6414 if (NewOp.getNode())
6417 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6419 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6420 // unpckh_undef). Only use pshufd if speed is more important than size.
6421 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6422 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6423 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6424 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6426 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6427 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6428 return getMOVDDup(Op, dl, V1, DAG);
6430 if (isMOVHLPS_v_undef_Mask(M, VT))
6431 return getMOVHighToLow(Op, dl, DAG);
6433 // Use to match splats
6434 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6435 (VT == MVT::v2f64 || VT == MVT::v2i64))
6436 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6438 if (isPSHUFDMask(M, VT)) {
6439 // The actual implementation will match the mask in the if above and then
6440 // during isel it can match several different instructions, not only pshufd
6441 // as its name says, sad but true, emulate the behavior for now...
6442 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6443 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6445 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6447 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6448 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6450 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6451 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6453 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6457 // Check if this can be converted into a logical shift.
6458 bool isLeft = false;
6461 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6462 if (isShift && ShVal.hasOneUse()) {
6463 // If the shifted value has multiple uses, it may be cheaper to use
6464 // v_set0 + movlhps or movhlps, etc.
6465 EVT EltVT = VT.getVectorElementType();
6466 ShAmt *= EltVT.getSizeInBits();
6467 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6470 if (isMOVLMask(M, VT)) {
6471 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6472 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6473 if (!isMOVLPMask(M, VT)) {
6474 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6475 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6477 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6478 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6482 // FIXME: fold these into legal mask.
6483 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6484 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6486 if (isMOVHLPSMask(M, VT))
6487 return getMOVHighToLow(Op, dl, DAG);
6489 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6490 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6492 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6493 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6495 if (isMOVLPMask(M, VT))
6496 return getMOVLP(Op, dl, DAG, HasSSE2);
6498 if (ShouldXformToMOVHLPS(M, VT) ||
6499 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6500 return CommuteVectorShuffle(SVOp, DAG);
6503 // No better options. Use a vshldq / vsrldq.
6504 EVT EltVT = VT.getVectorElementType();
6505 ShAmt *= EltVT.getSizeInBits();
6506 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6509 bool Commuted = false;
6510 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6511 // 1,1,1,1 -> v8i16 though.
6512 V1IsSplat = isSplatVector(V1.getNode());
6513 V2IsSplat = isSplatVector(V2.getNode());
6515 // Canonicalize the splat or undef, if present, to be on the RHS.
6516 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6517 CommuteVectorShuffleMask(M, NumElems);
6519 std::swap(V1IsSplat, V2IsSplat);
6523 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6524 // Shuffling low element of v1 into undef, just return v1.
6527 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6528 // the instruction selector will not match, so get a canonical MOVL with
6529 // swapped operands to undo the commute.
6530 return getMOVL(DAG, dl, VT, V2, V1);
6533 if (isUNPCKLMask(M, VT, HasAVX2))
6534 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6536 if (isUNPCKHMask(M, VT, HasAVX2))
6537 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6540 // Normalize mask so all entries that point to V2 points to its first
6541 // element then try to match unpck{h|l} again. If match, return a
6542 // new vector_shuffle with the corrected mask.p
6543 SmallVector<int, 8> NewMask(M.begin(), M.end());
6544 NormalizeMask(NewMask, NumElems);
6545 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) {
6546 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6547 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) {
6548 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6553 // Commute is back and try unpck* again.
6554 // FIXME: this seems wrong.
6555 CommuteVectorShuffleMask(M, NumElems);
6557 std::swap(V1IsSplat, V2IsSplat);
6560 if (isUNPCKLMask(M, VT, HasAVX2))
6561 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6563 if (isUNPCKHMask(M, VT, HasAVX2))
6564 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6567 // Normalize the node to match x86 shuffle ops if needed
6568 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6569 return CommuteVectorShuffle(SVOp, DAG);
6571 // The checks below are all present in isShuffleMaskLegal, but they are
6572 // inlined here right now to enable us to directly emit target specific
6573 // nodes, and remove one by one until they don't return Op anymore.
6575 if (isPALIGNRMask(M, VT, Subtarget))
6576 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6577 getShufflePALIGNRImmediate(SVOp),
6580 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6581 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6582 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6583 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6586 if (isPSHUFHWMask(M, VT))
6587 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6588 getShufflePSHUFHWImmediate(SVOp),
6591 if (isPSHUFLWMask(M, VT))
6592 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6593 getShufflePSHUFLWImmediate(SVOp),
6596 if (isSHUFPMask(M, VT, HasAVX))
6597 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6598 getShuffleSHUFImmediate(SVOp), DAG);
6600 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6601 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6602 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6603 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6605 //===--------------------------------------------------------------------===//
6606 // Generate target specific nodes for 128 or 256-bit shuffles only
6607 // supported in the AVX instruction set.
6610 // Handle VMOVDDUPY permutations
6611 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6612 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6614 // Handle VPERMILPS/D* permutations
6615 if (isVPERMILPMask(M, VT, HasAVX)) {
6616 if (HasAVX2 && VT == MVT::v8i32)
6617 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6618 getShuffleSHUFImmediate(SVOp), DAG);
6619 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6620 getShuffleSHUFImmediate(SVOp), DAG);
6623 // Handle VPERM2F128/VPERM2I128 permutations
6624 if (isVPERM2X128Mask(M, VT, HasAVX))
6625 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6626 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6628 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG, getPointerTy());
6629 if (BlendOp.getNode())
6632 //===--------------------------------------------------------------------===//
6633 // Since no target specific shuffle was selected for this generic one,
6634 // lower it into other known shuffles. FIXME: this isn't true yet, but
6635 // this is the plan.
6638 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6639 if (VT == MVT::v8i16) {
6640 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6641 if (NewOp.getNode())
6645 if (VT == MVT::v16i8) {
6646 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6647 if (NewOp.getNode())
6651 // Handle all 128-bit wide vectors with 4 elements, and match them with
6652 // several different shuffle types.
6653 if (NumElems == 4 && VT.getSizeInBits() == 128)
6654 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6656 // Handle general 256-bit shuffles
6657 if (VT.is256BitVector())
6658 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6664 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6665 SelectionDAG &DAG) const {
6666 EVT VT = Op.getValueType();
6667 DebugLoc dl = Op.getDebugLoc();
6669 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6672 if (VT.getSizeInBits() == 8) {
6673 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6674 Op.getOperand(0), Op.getOperand(1));
6675 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6676 DAG.getValueType(VT));
6677 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6678 } else if (VT.getSizeInBits() == 16) {
6679 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6680 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6682 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6683 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6684 DAG.getNode(ISD::BITCAST, dl,
6688 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6689 Op.getOperand(0), Op.getOperand(1));
6690 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6691 DAG.getValueType(VT));
6692 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6693 } else if (VT == MVT::f32) {
6694 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6695 // the result back to FR32 register. It's only worth matching if the
6696 // result has a single use which is a store or a bitcast to i32. And in
6697 // the case of a store, it's not worth it if the index is a constant 0,
6698 // because a MOVSSmr can be used instead, which is smaller and faster.
6699 if (!Op.hasOneUse())
6701 SDNode *User = *Op.getNode()->use_begin();
6702 if ((User->getOpcode() != ISD::STORE ||
6703 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6704 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6705 (User->getOpcode() != ISD::BITCAST ||
6706 User->getValueType(0) != MVT::i32))
6708 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6709 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6712 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6713 } else if (VT == MVT::i32 || VT == MVT::i64) {
6714 // ExtractPS/pextrq works with constant index.
6715 if (isa<ConstantSDNode>(Op.getOperand(1)))
6723 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6724 SelectionDAG &DAG) const {
6725 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6728 SDValue Vec = Op.getOperand(0);
6729 EVT VecVT = Vec.getValueType();
6731 // If this is a 256-bit vector result, first extract the 128-bit vector and
6732 // then extract the element from the 128-bit vector.
6733 if (VecVT.getSizeInBits() == 256) {
6734 DebugLoc dl = Op.getNode()->getDebugLoc();
6735 unsigned NumElems = VecVT.getVectorNumElements();
6736 SDValue Idx = Op.getOperand(1);
6737 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6739 // Get the 128-bit vector.
6740 bool Upper = IdxVal >= NumElems/2;
6741 Vec = Extract128BitVector(Vec,
6742 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6744 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6745 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6748 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6750 if (Subtarget->hasSSE41()) {
6751 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6756 EVT VT = Op.getValueType();
6757 DebugLoc dl = Op.getDebugLoc();
6758 // TODO: handle v16i8.
6759 if (VT.getSizeInBits() == 16) {
6760 SDValue Vec = Op.getOperand(0);
6761 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6763 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6764 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6765 DAG.getNode(ISD::BITCAST, dl,
6768 // Transform it so it match pextrw which produces a 32-bit result.
6769 EVT EltVT = MVT::i32;
6770 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6771 Op.getOperand(0), Op.getOperand(1));
6772 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6773 DAG.getValueType(VT));
6774 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6775 } else if (VT.getSizeInBits() == 32) {
6776 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6780 // SHUFPS the element to the lowest double word, then movss.
6781 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6782 EVT VVT = Op.getOperand(0).getValueType();
6783 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6784 DAG.getUNDEF(VVT), Mask);
6785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6786 DAG.getIntPtrConstant(0));
6787 } else if (VT.getSizeInBits() == 64) {
6788 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6789 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6790 // to match extract_elt for f64.
6791 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6795 // UNPCKHPD the element to the lowest double word, then movsd.
6796 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6797 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6798 int Mask[2] = { 1, -1 };
6799 EVT VVT = Op.getOperand(0).getValueType();
6800 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6801 DAG.getUNDEF(VVT), Mask);
6802 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6803 DAG.getIntPtrConstant(0));
6810 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6811 SelectionDAG &DAG) const {
6812 EVT VT = Op.getValueType();
6813 EVT EltVT = VT.getVectorElementType();
6814 DebugLoc dl = Op.getDebugLoc();
6816 SDValue N0 = Op.getOperand(0);
6817 SDValue N1 = Op.getOperand(1);
6818 SDValue N2 = Op.getOperand(2);
6820 if (VT.getSizeInBits() == 256)
6823 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6824 isa<ConstantSDNode>(N2)) {
6826 if (VT == MVT::v8i16)
6827 Opc = X86ISD::PINSRW;
6828 else if (VT == MVT::v16i8)
6829 Opc = X86ISD::PINSRB;
6831 Opc = X86ISD::PINSRB;
6833 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6835 if (N1.getValueType() != MVT::i32)
6836 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6837 if (N2.getValueType() != MVT::i32)
6838 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6839 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6840 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6841 // Bits [7:6] of the constant are the source select. This will always be
6842 // zero here. The DAG Combiner may combine an extract_elt index into these
6843 // bits. For example (insert (extract, 3), 2) could be matched by putting
6844 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6845 // Bits [5:4] of the constant are the destination select. This is the
6846 // value of the incoming immediate.
6847 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6848 // combine either bitwise AND or insert of float 0.0 to set these bits.
6849 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6850 // Create this as a scalar to vector..
6851 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6852 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6853 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6854 isa<ConstantSDNode>(N2)) {
6855 // PINSR* works with constant index.
6862 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6863 EVT VT = Op.getValueType();
6864 EVT EltVT = VT.getVectorElementType();
6866 DebugLoc dl = Op.getDebugLoc();
6867 SDValue N0 = Op.getOperand(0);
6868 SDValue N1 = Op.getOperand(1);
6869 SDValue N2 = Op.getOperand(2);
6871 // If this is a 256-bit vector result, first extract the 128-bit vector,
6872 // insert the element into the extracted half and then place it back.
6873 if (VT.getSizeInBits() == 256) {
6874 if (!isa<ConstantSDNode>(N2))
6877 // Get the desired 128-bit vector half.
6878 unsigned NumElems = VT.getVectorNumElements();
6879 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6880 bool Upper = IdxVal >= NumElems/2;
6881 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6882 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6884 // Insert the element into the desired half.
6885 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6886 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6888 // Insert the changed part back to the 256-bit vector
6889 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6892 if (Subtarget->hasSSE41())
6893 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6895 if (EltVT == MVT::i8)
6898 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6899 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6900 // as its second argument.
6901 if (N1.getValueType() != MVT::i32)
6902 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6903 if (N2.getValueType() != MVT::i32)
6904 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6905 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6911 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6912 LLVMContext *Context = DAG.getContext();
6913 DebugLoc dl = Op.getDebugLoc();
6914 EVT OpVT = Op.getValueType();
6916 // If this is a 256-bit vector result, first insert into a 128-bit
6917 // vector and then insert into the 256-bit vector.
6918 if (OpVT.getSizeInBits() > 128) {
6919 // Insert into a 128-bit vector.
6920 EVT VT128 = EVT::getVectorVT(*Context,
6921 OpVT.getVectorElementType(),
6922 OpVT.getVectorNumElements() / 2);
6924 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6926 // Insert the 128-bit vector.
6927 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6928 DAG.getConstant(0, MVT::i32),
6932 if (Op.getValueType() == MVT::v1i64 &&
6933 Op.getOperand(0).getValueType() == MVT::i64)
6934 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6936 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6937 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6938 "Expected an SSE type!");
6939 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6940 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6943 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6944 // a simple subregister reference or explicit instructions to grab
6945 // upper bits of a vector.
6947 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6948 if (Subtarget->hasAVX()) {
6949 DebugLoc dl = Op.getNode()->getDebugLoc();
6950 SDValue Vec = Op.getNode()->getOperand(0);
6951 SDValue Idx = Op.getNode()->getOperand(1);
6953 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6954 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6955 return Extract128BitVector(Vec, Idx, DAG, dl);
6961 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6962 // simple superregister reference or explicit instructions to insert
6963 // the upper bits of a vector.
6965 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6966 if (Subtarget->hasAVX()) {
6967 DebugLoc dl = Op.getNode()->getDebugLoc();
6968 SDValue Vec = Op.getNode()->getOperand(0);
6969 SDValue SubVec = Op.getNode()->getOperand(1);
6970 SDValue Idx = Op.getNode()->getOperand(2);
6972 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6973 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6974 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6980 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6981 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6982 // one of the above mentioned nodes. It has to be wrapped because otherwise
6983 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6984 // be used to form addressing mode. These wrapped nodes will be selected
6987 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6988 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6990 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6992 unsigned char OpFlag = 0;
6993 unsigned WrapperKind = X86ISD::Wrapper;
6994 CodeModel::Model M = getTargetMachine().getCodeModel();
6996 if (Subtarget->isPICStyleRIPRel() &&
6997 (M == CodeModel::Small || M == CodeModel::Kernel))
6998 WrapperKind = X86ISD::WrapperRIP;
6999 else if (Subtarget->isPICStyleGOT())
7000 OpFlag = X86II::MO_GOTOFF;
7001 else if (Subtarget->isPICStyleStubPIC())
7002 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7004 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7006 CP->getOffset(), OpFlag);
7007 DebugLoc DL = CP->getDebugLoc();
7008 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7009 // With PIC, the address is actually $g + Offset.
7011 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7012 DAG.getNode(X86ISD::GlobalBaseReg,
7013 DebugLoc(), getPointerTy()),
7020 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7021 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7023 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7025 unsigned char OpFlag = 0;
7026 unsigned WrapperKind = X86ISD::Wrapper;
7027 CodeModel::Model M = getTargetMachine().getCodeModel();
7029 if (Subtarget->isPICStyleRIPRel() &&
7030 (M == CodeModel::Small || M == CodeModel::Kernel))
7031 WrapperKind = X86ISD::WrapperRIP;
7032 else if (Subtarget->isPICStyleGOT())
7033 OpFlag = X86II::MO_GOTOFF;
7034 else if (Subtarget->isPICStyleStubPIC())
7035 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7037 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7039 DebugLoc DL = JT->getDebugLoc();
7040 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7042 // With PIC, the address is actually $g + Offset.
7044 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7045 DAG.getNode(X86ISD::GlobalBaseReg,
7046 DebugLoc(), getPointerTy()),
7053 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7054 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7056 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7058 unsigned char OpFlag = 0;
7059 unsigned WrapperKind = X86ISD::Wrapper;
7060 CodeModel::Model M = getTargetMachine().getCodeModel();
7062 if (Subtarget->isPICStyleRIPRel() &&
7063 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7064 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7065 OpFlag = X86II::MO_GOTPCREL;
7066 WrapperKind = X86ISD::WrapperRIP;
7067 } else if (Subtarget->isPICStyleGOT()) {
7068 OpFlag = X86II::MO_GOT;
7069 } else if (Subtarget->isPICStyleStubPIC()) {
7070 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7071 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7072 OpFlag = X86II::MO_DARWIN_NONLAZY;
7075 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7077 DebugLoc DL = Op.getDebugLoc();
7078 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7081 // With PIC, the address is actually $g + Offset.
7082 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7083 !Subtarget->is64Bit()) {
7084 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7085 DAG.getNode(X86ISD::GlobalBaseReg,
7086 DebugLoc(), getPointerTy()),
7090 // For symbols that require a load from a stub to get the address, emit the
7092 if (isGlobalStubReference(OpFlag))
7093 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7094 MachinePointerInfo::getGOT(), false, false, false, 0);
7100 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7101 // Create the TargetBlockAddressAddress node.
7102 unsigned char OpFlags =
7103 Subtarget->ClassifyBlockAddressReference();
7104 CodeModel::Model M = getTargetMachine().getCodeModel();
7105 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7106 DebugLoc dl = Op.getDebugLoc();
7107 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7108 /*isTarget=*/true, OpFlags);
7110 if (Subtarget->isPICStyleRIPRel() &&
7111 (M == CodeModel::Small || M == CodeModel::Kernel))
7112 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7114 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7116 // With PIC, the address is actually $g + Offset.
7117 if (isGlobalRelativeToPICBase(OpFlags)) {
7118 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7119 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7127 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7129 SelectionDAG &DAG) const {
7130 // Create the TargetGlobalAddress node, folding in the constant
7131 // offset if it is legal.
7132 unsigned char OpFlags =
7133 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7134 CodeModel::Model M = getTargetMachine().getCodeModel();
7136 if (OpFlags == X86II::MO_NO_FLAG &&
7137 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7138 // A direct static reference to a global.
7139 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7142 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7145 if (Subtarget->isPICStyleRIPRel() &&
7146 (M == CodeModel::Small || M == CodeModel::Kernel))
7147 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7149 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7151 // With PIC, the address is actually $g + Offset.
7152 if (isGlobalRelativeToPICBase(OpFlags)) {
7153 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7154 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7158 // For globals that require a load from a stub to get the address, emit the
7160 if (isGlobalStubReference(OpFlags))
7161 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7162 MachinePointerInfo::getGOT(), false, false, false, 0);
7164 // If there was a non-zero offset that we didn't fold, create an explicit
7167 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7168 DAG.getConstant(Offset, getPointerTy()));
7174 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7175 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7176 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7177 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7181 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7182 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7183 unsigned char OperandFlags) {
7184 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7185 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7186 DebugLoc dl = GA->getDebugLoc();
7187 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7188 GA->getValueType(0),
7192 SDValue Ops[] = { Chain, TGA, *InFlag };
7193 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7195 SDValue Ops[] = { Chain, TGA };
7196 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7199 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7200 MFI->setAdjustsStack(true);
7202 SDValue Flag = Chain.getValue(1);
7203 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7206 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7208 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7211 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7212 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7213 DAG.getNode(X86ISD::GlobalBaseReg,
7214 DebugLoc(), PtrVT), InFlag);
7215 InFlag = Chain.getValue(1);
7217 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7220 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7222 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7224 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7225 X86::RAX, X86II::MO_TLSGD);
7228 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7229 // "local exec" model.
7230 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7231 const EVT PtrVT, TLSModel::Model model,
7233 DebugLoc dl = GA->getDebugLoc();
7235 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7236 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7237 is64Bit ? 257 : 256));
7239 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7240 DAG.getIntPtrConstant(0),
7241 MachinePointerInfo(Ptr),
7242 false, false, false, 0);
7244 unsigned char OperandFlags = 0;
7245 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7247 unsigned WrapperKind = X86ISD::Wrapper;
7248 if (model == TLSModel::LocalExec) {
7249 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7250 } else if (is64Bit) {
7251 assert(model == TLSModel::InitialExec);
7252 OperandFlags = X86II::MO_GOTTPOFF;
7253 WrapperKind = X86ISD::WrapperRIP;
7255 assert(model == TLSModel::InitialExec);
7256 OperandFlags = X86II::MO_INDNTPOFF;
7259 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7261 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7262 GA->getValueType(0),
7263 GA->getOffset(), OperandFlags);
7264 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7266 if (model == TLSModel::InitialExec)
7267 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7268 MachinePointerInfo::getGOT(), false, false, false, 0);
7270 // The address of the thread local variable is the add of the thread
7271 // pointer with the offset of the variable.
7272 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7276 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7278 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7279 const GlobalValue *GV = GA->getGlobal();
7281 if (Subtarget->isTargetELF()) {
7282 // TODO: implement the "local dynamic" model
7283 // TODO: implement the "initial exec"model for pic executables
7285 // If GV is an alias then use the aliasee for determining
7286 // thread-localness.
7287 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7288 GV = GA->resolveAliasedGlobal(false);
7290 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7293 case TLSModel::GeneralDynamic:
7294 case TLSModel::LocalDynamic: // not implemented
7295 if (Subtarget->is64Bit())
7296 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7297 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7299 case TLSModel::InitialExec:
7300 case TLSModel::LocalExec:
7301 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7302 Subtarget->is64Bit());
7304 } else if (Subtarget->isTargetDarwin()) {
7305 // Darwin only has one model of TLS. Lower to that.
7306 unsigned char OpFlag = 0;
7307 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7308 X86ISD::WrapperRIP : X86ISD::Wrapper;
7310 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7312 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7313 !Subtarget->is64Bit();
7315 OpFlag = X86II::MO_TLVP_PIC_BASE;
7317 OpFlag = X86II::MO_TLVP;
7318 DebugLoc DL = Op.getDebugLoc();
7319 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7320 GA->getValueType(0),
7321 GA->getOffset(), OpFlag);
7322 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7324 // With PIC32, the address is actually $g + Offset.
7326 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7327 DAG.getNode(X86ISD::GlobalBaseReg,
7328 DebugLoc(), getPointerTy()),
7331 // Lowering the machine isd will make sure everything is in the right
7333 SDValue Chain = DAG.getEntryNode();
7334 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7335 SDValue Args[] = { Chain, Offset };
7336 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7338 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7339 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7340 MFI->setAdjustsStack(true);
7342 // And our return value (tls address) is in the standard call return value
7344 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7345 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7347 } else if (Subtarget->isTargetWindows()) {
7348 // Just use the implicit TLS architecture
7349 // Need to generate someting similar to:
7350 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7352 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7353 // mov rcx, qword [rdx+rcx*8]
7354 // mov eax, .tls$:tlsvar
7355 // [rax+rcx] contains the address
7356 // Windows 64bit: gs:0x58
7357 // Windows 32bit: fs:__tls_array
7359 // If GV is an alias then use the aliasee for determining
7360 // thread-localness.
7361 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7362 GV = GA->resolveAliasedGlobal(false);
7363 DebugLoc dl = GA->getDebugLoc();
7364 SDValue Chain = DAG.getEntryNode();
7366 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7367 // %gs:0x58 (64-bit).
7368 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7369 ? Type::getInt8PtrTy(*DAG.getContext(),
7371 : Type::getInt32PtrTy(*DAG.getContext(),
7374 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7375 Subtarget->is64Bit()
7376 ? DAG.getIntPtrConstant(0x58)
7377 : DAG.getExternalSymbol("_tls_array",
7379 MachinePointerInfo(Ptr),
7380 false, false, false, 0);
7382 // Load the _tls_index variable
7383 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7384 if (Subtarget->is64Bit())
7385 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7386 IDX, MachinePointerInfo(), MVT::i32,
7389 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7390 false, false, false, 0);
7392 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7394 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7396 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7397 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7398 false, false, false, 0);
7400 // Get the offset of start of .tls section
7401 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7402 GA->getValueType(0),
7403 GA->getOffset(), X86II::MO_SECREL);
7404 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7406 // The address of the thread local variable is the add of the thread
7407 // pointer with the offset of the variable.
7408 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7411 llvm_unreachable("TLS not implemented for this target.");
7415 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7416 /// and take a 2 x i32 value to shift plus a shift amount.
7417 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7418 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7419 EVT VT = Op.getValueType();
7420 unsigned VTBits = VT.getSizeInBits();
7421 DebugLoc dl = Op.getDebugLoc();
7422 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7423 SDValue ShOpLo = Op.getOperand(0);
7424 SDValue ShOpHi = Op.getOperand(1);
7425 SDValue ShAmt = Op.getOperand(2);
7426 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7427 DAG.getConstant(VTBits - 1, MVT::i8))
7428 : DAG.getConstant(0, VT);
7431 if (Op.getOpcode() == ISD::SHL_PARTS) {
7432 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7433 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7435 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7436 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7439 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7440 DAG.getConstant(VTBits, MVT::i8));
7441 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7442 AndNode, DAG.getConstant(0, MVT::i8));
7445 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7446 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7447 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7449 if (Op.getOpcode() == ISD::SHL_PARTS) {
7450 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7451 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7453 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7454 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7457 SDValue Ops[2] = { Lo, Hi };
7458 return DAG.getMergeValues(Ops, 2, dl);
7461 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7462 SelectionDAG &DAG) const {
7463 EVT SrcVT = Op.getOperand(0).getValueType();
7465 if (SrcVT.isVector())
7468 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7469 "Unknown SINT_TO_FP to lower!");
7471 // These are really Legal; return the operand so the caller accepts it as
7473 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7475 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7476 Subtarget->is64Bit()) {
7480 DebugLoc dl = Op.getDebugLoc();
7481 unsigned Size = SrcVT.getSizeInBits()/8;
7482 MachineFunction &MF = DAG.getMachineFunction();
7483 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7484 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7485 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7487 MachinePointerInfo::getFixedStack(SSFI),
7489 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7492 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7494 SelectionDAG &DAG) const {
7496 DebugLoc DL = Op.getDebugLoc();
7498 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7500 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7502 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7504 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7506 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7507 MachineMemOperand *MMO;
7509 int SSFI = FI->getIndex();
7511 DAG.getMachineFunction()
7512 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7513 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7515 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7516 StackSlot = StackSlot.getOperand(1);
7518 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7519 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7521 Tys, Ops, array_lengthof(Ops),
7525 Chain = Result.getValue(1);
7526 SDValue InFlag = Result.getValue(2);
7528 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7529 // shouldn't be necessary except that RFP cannot be live across
7530 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7531 MachineFunction &MF = DAG.getMachineFunction();
7532 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7533 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7534 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7535 Tys = DAG.getVTList(MVT::Other);
7537 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7539 MachineMemOperand *MMO =
7540 DAG.getMachineFunction()
7541 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7542 MachineMemOperand::MOStore, SSFISize, SSFISize);
7544 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7545 Ops, array_lengthof(Ops),
7546 Op.getValueType(), MMO);
7547 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7548 MachinePointerInfo::getFixedStack(SSFI),
7549 false, false, false, 0);
7555 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7556 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7557 SelectionDAG &DAG) const {
7558 // This algorithm is not obvious. Here it is what we're trying to output:
7561 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7562 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7566 pshufd $0x4e, %xmm0, %xmm1
7571 DebugLoc dl = Op.getDebugLoc();
7572 LLVMContext *Context = DAG.getContext();
7574 // Build some magic constants.
7575 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7576 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7577 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7579 SmallVector<Constant*,2> CV1;
7581 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7583 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7584 Constant *C1 = ConstantVector::get(CV1);
7585 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7587 // Load the 64-bit value into an XMM register.
7588 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7590 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7591 MachinePointerInfo::getConstantPool(),
7592 false, false, false, 16);
7593 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7594 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7597 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7598 MachinePointerInfo::getConstantPool(),
7599 false, false, false, 16);
7600 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7601 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7604 if (Subtarget->hasSSE3()) {
7605 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7606 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7608 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7609 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7611 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7612 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7616 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7617 DAG.getIntPtrConstant(0));
7620 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7621 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7622 SelectionDAG &DAG) const {
7623 DebugLoc dl = Op.getDebugLoc();
7624 // FP constant to bias correct the final result.
7625 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7628 // Load the 32-bit value into an XMM register.
7629 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7632 // Zero out the upper parts of the register.
7633 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7635 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7636 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7637 DAG.getIntPtrConstant(0));
7639 // Or the load with the bias.
7640 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7641 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7642 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7644 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7645 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7646 MVT::v2f64, Bias)));
7647 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7648 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7649 DAG.getIntPtrConstant(0));
7651 // Subtract the bias.
7652 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7654 // Handle final rounding.
7655 EVT DestVT = Op.getValueType();
7657 if (DestVT.bitsLT(MVT::f64)) {
7658 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7659 DAG.getIntPtrConstant(0));
7660 } else if (DestVT.bitsGT(MVT::f64)) {
7661 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7664 // Handle final rounding.
7668 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7669 SelectionDAG &DAG) const {
7670 SDValue N0 = Op.getOperand(0);
7671 DebugLoc dl = Op.getDebugLoc();
7673 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7674 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7675 // the optimization here.
7676 if (DAG.SignBitIsZero(N0))
7677 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7679 EVT SrcVT = N0.getValueType();
7680 EVT DstVT = Op.getValueType();
7681 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7682 return LowerUINT_TO_FP_i64(Op, DAG);
7683 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7684 return LowerUINT_TO_FP_i32(Op, DAG);
7685 else if (Subtarget->is64Bit() &&
7686 SrcVT == MVT::i64 && DstVT == MVT::f32)
7689 // Make a 64-bit buffer, and use it to build an FILD.
7690 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7691 if (SrcVT == MVT::i32) {
7692 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7693 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7694 getPointerTy(), StackSlot, WordOff);
7695 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7696 StackSlot, MachinePointerInfo(),
7698 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7699 OffsetSlot, MachinePointerInfo(),
7701 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7705 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7706 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7707 StackSlot, MachinePointerInfo(),
7709 // For i64 source, we need to add the appropriate power of 2 if the input
7710 // was negative. This is the same as the optimization in
7711 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7712 // we must be careful to do the computation in x87 extended precision, not
7713 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7714 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7715 MachineMemOperand *MMO =
7716 DAG.getMachineFunction()
7717 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7718 MachineMemOperand::MOLoad, 8, 8);
7720 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7721 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7722 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7725 APInt FF(32, 0x5F800000ULL);
7727 // Check whether the sign bit is set.
7728 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7729 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7732 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7733 SDValue FudgePtr = DAG.getConstantPool(
7734 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7737 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7738 SDValue Zero = DAG.getIntPtrConstant(0);
7739 SDValue Four = DAG.getIntPtrConstant(4);
7740 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7742 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7744 // Load the value out, extending it from f32 to f80.
7745 // FIXME: Avoid the extend by constructing the right constant pool?
7746 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7747 FudgePtr, MachinePointerInfo::getConstantPool(),
7748 MVT::f32, false, false, 4);
7749 // Extend everything to 80 bits to force it to be done on x87.
7750 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7751 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7754 std::pair<SDValue,SDValue> X86TargetLowering::
7755 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7756 DebugLoc DL = Op.getDebugLoc();
7758 EVT DstTy = Op.getValueType();
7760 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7761 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7765 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7766 DstTy.getSimpleVT() >= MVT::i16 &&
7767 "Unknown FP_TO_INT to lower!");
7769 // These are really Legal.
7770 if (DstTy == MVT::i32 &&
7771 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7772 return std::make_pair(SDValue(), SDValue());
7773 if (Subtarget->is64Bit() &&
7774 DstTy == MVT::i64 &&
7775 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7776 return std::make_pair(SDValue(), SDValue());
7778 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7779 // stack slot, or into the FTOL runtime function.
7780 MachineFunction &MF = DAG.getMachineFunction();
7781 unsigned MemSize = DstTy.getSizeInBits()/8;
7782 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7783 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7786 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7787 Opc = X86ISD::WIN_FTOL;
7789 switch (DstTy.getSimpleVT().SimpleTy) {
7790 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7791 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7792 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7793 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7796 SDValue Chain = DAG.getEntryNode();
7797 SDValue Value = Op.getOperand(0);
7798 EVT TheVT = Op.getOperand(0).getValueType();
7799 // FIXME This causes a redundant load/store if the SSE-class value is already
7800 // in memory, such as if it is on the callstack.
7801 if (isScalarFPTypeInSSEReg(TheVT)) {
7802 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7803 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7804 MachinePointerInfo::getFixedStack(SSFI),
7806 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7808 Chain, StackSlot, DAG.getValueType(TheVT)
7811 MachineMemOperand *MMO =
7812 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7813 MachineMemOperand::MOLoad, MemSize, MemSize);
7814 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7816 Chain = Value.getValue(1);
7817 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7818 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7821 MachineMemOperand *MMO =
7822 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7823 MachineMemOperand::MOStore, MemSize, MemSize);
7825 if (Opc != X86ISD::WIN_FTOL) {
7826 // Build the FP_TO_INT*_IN_MEM
7827 SDValue Ops[] = { Chain, Value, StackSlot };
7828 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7829 Ops, 3, DstTy, MMO);
7830 return std::make_pair(FIST, StackSlot);
7832 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7833 DAG.getVTList(MVT::Other, MVT::Glue),
7835 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7836 MVT::i32, ftol.getValue(1));
7837 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7838 MVT::i32, eax.getValue(2));
7839 SDValue Ops[] = { eax, edx };
7840 SDValue pair = IsReplace
7841 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7842 : DAG.getMergeValues(Ops, 2, DL);
7843 return std::make_pair(pair, SDValue());
7847 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7848 SelectionDAG &DAG) const {
7849 if (Op.getValueType().isVector())
7852 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7853 /*IsSigned=*/ true, /*IsReplace=*/ false);
7854 SDValue FIST = Vals.first, StackSlot = Vals.second;
7855 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7856 if (FIST.getNode() == 0) return Op;
7858 if (StackSlot.getNode())
7860 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7861 FIST, StackSlot, MachinePointerInfo(),
7862 false, false, false, 0);
7864 // The node is the result.
7868 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7869 SelectionDAG &DAG) const {
7870 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7871 /*IsSigned=*/ false, /*IsReplace=*/ false);
7872 SDValue FIST = Vals.first, StackSlot = Vals.second;
7873 assert(FIST.getNode() && "Unexpected failure");
7875 if (StackSlot.getNode())
7877 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7878 FIST, StackSlot, MachinePointerInfo(),
7879 false, false, false, 0);
7881 // The node is the result.
7885 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7886 SelectionDAG &DAG) const {
7887 LLVMContext *Context = DAG.getContext();
7888 DebugLoc dl = Op.getDebugLoc();
7889 EVT VT = Op.getValueType();
7892 EltVT = VT.getVectorElementType();
7894 if (EltVT == MVT::f64) {
7895 C = ConstantVector::getSplat(2,
7896 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7898 C = ConstantVector::getSplat(4,
7899 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7901 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7902 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7903 MachinePointerInfo::getConstantPool(),
7904 false, false, false, 16);
7905 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7908 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7909 LLVMContext *Context = DAG.getContext();
7910 DebugLoc dl = Op.getDebugLoc();
7911 EVT VT = Op.getValueType();
7913 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7914 if (VT.isVector()) {
7915 EltVT = VT.getVectorElementType();
7916 NumElts = VT.getVectorNumElements();
7919 if (EltVT == MVT::f64)
7920 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7922 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7923 C = ConstantVector::getSplat(NumElts, C);
7924 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7925 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7926 MachinePointerInfo::getConstantPool(),
7927 false, false, false, 16);
7928 if (VT.isVector()) {
7929 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7930 return DAG.getNode(ISD::BITCAST, dl, VT,
7931 DAG.getNode(ISD::XOR, dl, XORVT,
7932 DAG.getNode(ISD::BITCAST, dl, XORVT,
7934 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7936 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7940 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7941 LLVMContext *Context = DAG.getContext();
7942 SDValue Op0 = Op.getOperand(0);
7943 SDValue Op1 = Op.getOperand(1);
7944 DebugLoc dl = Op.getDebugLoc();
7945 EVT VT = Op.getValueType();
7946 EVT SrcVT = Op1.getValueType();
7948 // If second operand is smaller, extend it first.
7949 if (SrcVT.bitsLT(VT)) {
7950 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7953 // And if it is bigger, shrink it first.
7954 if (SrcVT.bitsGT(VT)) {
7955 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7959 // At this point the operands and the result should have the same
7960 // type, and that won't be f80 since that is not custom lowered.
7962 // First get the sign bit of second operand.
7963 SmallVector<Constant*,4> CV;
7964 if (SrcVT == MVT::f64) {
7965 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7966 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7968 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7969 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7970 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7971 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7973 Constant *C = ConstantVector::get(CV);
7974 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7975 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7976 MachinePointerInfo::getConstantPool(),
7977 false, false, false, 16);
7978 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7980 // Shift sign bit right or left if the two operands have different types.
7981 if (SrcVT.bitsGT(VT)) {
7982 // Op0 is MVT::f32, Op1 is MVT::f64.
7983 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7984 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7985 DAG.getConstant(32, MVT::i32));
7986 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7987 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7988 DAG.getIntPtrConstant(0));
7991 // Clear first operand sign bit.
7993 if (VT == MVT::f64) {
7994 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7995 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7997 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7998 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7999 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8000 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8002 C = ConstantVector::get(CV);
8003 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8004 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8005 MachinePointerInfo::getConstantPool(),
8006 false, false, false, 16);
8007 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8009 // Or the value with the sign bit.
8010 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8013 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8014 SDValue N0 = Op.getOperand(0);
8015 DebugLoc dl = Op.getDebugLoc();
8016 EVT VT = Op.getValueType();
8018 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8019 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8020 DAG.getConstant(1, VT));
8021 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8024 /// Emit nodes that will be selected as "test Op0,Op0", or something
8026 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8027 SelectionDAG &DAG) const {
8028 DebugLoc dl = Op.getDebugLoc();
8030 // CF and OF aren't always set the way we want. Determine which
8031 // of these we need.
8032 bool NeedCF = false;
8033 bool NeedOF = false;
8036 case X86::COND_A: case X86::COND_AE:
8037 case X86::COND_B: case X86::COND_BE:
8040 case X86::COND_G: case X86::COND_GE:
8041 case X86::COND_L: case X86::COND_LE:
8042 case X86::COND_O: case X86::COND_NO:
8047 // See if we can use the EFLAGS value from the operand instead of
8048 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8049 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8050 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8051 // Emit a CMP with 0, which is the TEST pattern.
8052 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8053 DAG.getConstant(0, Op.getValueType()));
8055 unsigned Opcode = 0;
8056 unsigned NumOperands = 0;
8057 switch (Op.getNode()->getOpcode()) {
8059 // Due to an isel shortcoming, be conservative if this add is likely to be
8060 // selected as part of a load-modify-store instruction. When the root node
8061 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8062 // uses of other nodes in the match, such as the ADD in this case. This
8063 // leads to the ADD being left around and reselected, with the result being
8064 // two adds in the output. Alas, even if none our users are stores, that
8065 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8066 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8067 // climbing the DAG back to the root, and it doesn't seem to be worth the
8069 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8070 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8071 if (UI->getOpcode() != ISD::CopyToReg &&
8072 UI->getOpcode() != ISD::SETCC &&
8073 UI->getOpcode() != ISD::STORE)
8076 if (ConstantSDNode *C =
8077 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8078 // An add of one will be selected as an INC.
8079 if (C->getAPIntValue() == 1) {
8080 Opcode = X86ISD::INC;
8085 // An add of negative one (subtract of one) will be selected as a DEC.
8086 if (C->getAPIntValue().isAllOnesValue()) {
8087 Opcode = X86ISD::DEC;
8093 // Otherwise use a regular EFLAGS-setting add.
8094 Opcode = X86ISD::ADD;
8098 // If the primary and result isn't used, don't bother using X86ISD::AND,
8099 // because a TEST instruction will be better.
8100 bool NonFlagUse = false;
8101 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8102 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8104 unsigned UOpNo = UI.getOperandNo();
8105 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8106 // Look pass truncate.
8107 UOpNo = User->use_begin().getOperandNo();
8108 User = *User->use_begin();
8111 if (User->getOpcode() != ISD::BRCOND &&
8112 User->getOpcode() != ISD::SETCC &&
8113 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8126 // Due to the ISEL shortcoming noted above, be conservative if this op is
8127 // likely to be selected as part of a load-modify-store instruction.
8128 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8129 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8130 if (UI->getOpcode() == ISD::STORE)
8133 // Otherwise use a regular EFLAGS-setting instruction.
8134 switch (Op.getNode()->getOpcode()) {
8135 default: llvm_unreachable("unexpected operator!");
8136 case ISD::SUB: Opcode = X86ISD::SUB; break;
8137 case ISD::OR: Opcode = X86ISD::OR; break;
8138 case ISD::XOR: Opcode = X86ISD::XOR; break;
8139 case ISD::AND: Opcode = X86ISD::AND; break;
8151 return SDValue(Op.getNode(), 1);
8158 // Emit a CMP with 0, which is the TEST pattern.
8159 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8160 DAG.getConstant(0, Op.getValueType()));
8162 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8163 SmallVector<SDValue, 4> Ops;
8164 for (unsigned i = 0; i != NumOperands; ++i)
8165 Ops.push_back(Op.getOperand(i));
8167 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8168 DAG.ReplaceAllUsesWith(Op, New);
8169 return SDValue(New.getNode(), 1);
8172 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8174 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8175 SelectionDAG &DAG) const {
8176 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8177 if (C->getAPIntValue() == 0)
8178 return EmitTest(Op0, X86CC, DAG);
8180 DebugLoc dl = Op0.getDebugLoc();
8181 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8184 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8185 /// if it's possible.
8186 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8187 DebugLoc dl, SelectionDAG &DAG) const {
8188 SDValue Op0 = And.getOperand(0);
8189 SDValue Op1 = And.getOperand(1);
8190 if (Op0.getOpcode() == ISD::TRUNCATE)
8191 Op0 = Op0.getOperand(0);
8192 if (Op1.getOpcode() == ISD::TRUNCATE)
8193 Op1 = Op1.getOperand(0);
8196 if (Op1.getOpcode() == ISD::SHL)
8197 std::swap(Op0, Op1);
8198 if (Op0.getOpcode() == ISD::SHL) {
8199 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8200 if (And00C->getZExtValue() == 1) {
8201 // If we looked past a truncate, check that it's only truncating away
8203 unsigned BitWidth = Op0.getValueSizeInBits();
8204 unsigned AndBitWidth = And.getValueSizeInBits();
8205 if (BitWidth > AndBitWidth) {
8207 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8208 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8212 RHS = Op0.getOperand(1);
8214 } else if (Op1.getOpcode() == ISD::Constant) {
8215 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8216 uint64_t AndRHSVal = AndRHS->getZExtValue();
8217 SDValue AndLHS = Op0;
8219 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8220 LHS = AndLHS.getOperand(0);
8221 RHS = AndLHS.getOperand(1);
8224 // Use BT if the immediate can't be encoded in a TEST instruction.
8225 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8227 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8231 if (LHS.getNode()) {
8232 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8233 // instruction. Since the shift amount is in-range-or-undefined, we know
8234 // that doing a bittest on the i32 value is ok. We extend to i32 because
8235 // the encoding for the i16 version is larger than the i32 version.
8236 // Also promote i16 to i32 for performance / code size reason.
8237 if (LHS.getValueType() == MVT::i8 ||
8238 LHS.getValueType() == MVT::i16)
8239 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8241 // If the operand types disagree, extend the shift amount to match. Since
8242 // BT ignores high bits (like shifts) we can use anyextend.
8243 if (LHS.getValueType() != RHS.getValueType())
8244 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8246 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8247 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8248 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8249 DAG.getConstant(Cond, MVT::i8), BT);
8255 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8257 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8259 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8260 SDValue Op0 = Op.getOperand(0);
8261 SDValue Op1 = Op.getOperand(1);
8262 DebugLoc dl = Op.getDebugLoc();
8263 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8265 // Optimize to BT if possible.
8266 // Lower (X & (1 << N)) == 0 to BT(X, N).
8267 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8268 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8269 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8270 Op1.getOpcode() == ISD::Constant &&
8271 cast<ConstantSDNode>(Op1)->isNullValue() &&
8272 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8273 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8274 if (NewSetCC.getNode())
8278 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8280 if (Op1.getOpcode() == ISD::Constant &&
8281 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8282 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8283 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8285 // If the input is a setcc, then reuse the input setcc or use a new one with
8286 // the inverted condition.
8287 if (Op0.getOpcode() == X86ISD::SETCC) {
8288 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8289 bool Invert = (CC == ISD::SETNE) ^
8290 cast<ConstantSDNode>(Op1)->isNullValue();
8291 if (!Invert) return Op0;
8293 CCode = X86::GetOppositeBranchCondition(CCode);
8294 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8295 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8299 bool isFP = Op1.getValueType().isFloatingPoint();
8300 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8301 if (X86CC == X86::COND_INVALID)
8304 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8305 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8306 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8309 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8310 // ones, and then concatenate the result back.
8311 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8312 EVT VT = Op.getValueType();
8314 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8315 "Unsupported value type for operation");
8317 int NumElems = VT.getVectorNumElements();
8318 DebugLoc dl = Op.getDebugLoc();
8319 SDValue CC = Op.getOperand(2);
8320 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8321 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8323 // Extract the LHS vectors
8324 SDValue LHS = Op.getOperand(0);
8325 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8326 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8328 // Extract the RHS vectors
8329 SDValue RHS = Op.getOperand(1);
8330 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8331 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8333 // Issue the operation on the smaller types and concatenate the result back
8334 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8335 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8336 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8337 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8338 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8342 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8344 SDValue Op0 = Op.getOperand(0);
8345 SDValue Op1 = Op.getOperand(1);
8346 SDValue CC = Op.getOperand(2);
8347 EVT VT = Op.getValueType();
8348 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8349 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8350 DebugLoc dl = Op.getDebugLoc();
8354 EVT EltVT = Op0.getValueType().getVectorElementType();
8355 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8359 // SSE Condition code mapping:
8368 switch (SetCCOpcode) {
8371 case ISD::SETEQ: SSECC = 0; break;
8373 case ISD::SETGT: Swap = true; // Fallthrough
8375 case ISD::SETOLT: SSECC = 1; break;
8377 case ISD::SETGE: Swap = true; // Fallthrough
8379 case ISD::SETOLE: SSECC = 2; break;
8380 case ISD::SETUO: SSECC = 3; break;
8382 case ISD::SETNE: SSECC = 4; break;
8383 case ISD::SETULE: Swap = true;
8384 case ISD::SETUGE: SSECC = 5; break;
8385 case ISD::SETULT: Swap = true;
8386 case ISD::SETUGT: SSECC = 6; break;
8387 case ISD::SETO: SSECC = 7; break;
8390 std::swap(Op0, Op1);
8392 // In the two special cases we can't handle, emit two comparisons.
8394 if (SetCCOpcode == ISD::SETUEQ) {
8396 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8397 DAG.getConstant(3, MVT::i8));
8398 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8399 DAG.getConstant(0, MVT::i8));
8400 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8401 } else if (SetCCOpcode == ISD::SETONE) {
8403 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8404 DAG.getConstant(7, MVT::i8));
8405 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8406 DAG.getConstant(4, MVT::i8));
8407 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8409 llvm_unreachable("Illegal FP comparison");
8411 // Handle all other FP comparisons here.
8412 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8413 DAG.getConstant(SSECC, MVT::i8));
8416 // Break 256-bit integer vector compare into smaller ones.
8417 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8418 return Lower256IntVSETCC(Op, DAG);
8420 // We are handling one of the integer comparisons here. Since SSE only has
8421 // GT and EQ comparisons for integer, swapping operands and multiple
8422 // operations may be required for some comparisons.
8424 bool Swap = false, Invert = false, FlipSigns = false;
8426 switch (SetCCOpcode) {
8428 case ISD::SETNE: Invert = true;
8429 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8430 case ISD::SETLT: Swap = true;
8431 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8432 case ISD::SETGE: Swap = true;
8433 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8434 case ISD::SETULT: Swap = true;
8435 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8436 case ISD::SETUGE: Swap = true;
8437 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8440 std::swap(Op0, Op1);
8442 // Check that the operation in question is available (most are plain SSE2,
8443 // but PCMPGTQ and PCMPEQQ have different requirements).
8444 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8446 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8449 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8450 // bits of the inputs before performing those operations.
8452 EVT EltVT = VT.getVectorElementType();
8453 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8455 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8456 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8458 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8459 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8462 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8464 // If the logical-not of the result is required, perform that now.
8466 Result = DAG.getNOT(dl, Result, VT);
8471 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8472 static bool isX86LogicalCmp(SDValue Op) {
8473 unsigned Opc = Op.getNode()->getOpcode();
8474 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8476 if (Op.getResNo() == 1 &&
8477 (Opc == X86ISD::ADD ||
8478 Opc == X86ISD::SUB ||
8479 Opc == X86ISD::ADC ||
8480 Opc == X86ISD::SBB ||
8481 Opc == X86ISD::SMUL ||
8482 Opc == X86ISD::UMUL ||
8483 Opc == X86ISD::INC ||
8484 Opc == X86ISD::DEC ||
8485 Opc == X86ISD::OR ||
8486 Opc == X86ISD::XOR ||
8487 Opc == X86ISD::AND))
8490 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8496 static bool isZero(SDValue V) {
8497 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8498 return C && C->isNullValue();
8501 static bool isAllOnes(SDValue V) {
8502 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8503 return C && C->isAllOnesValue();
8506 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8507 bool addTest = true;
8508 SDValue Cond = Op.getOperand(0);
8509 SDValue Op1 = Op.getOperand(1);
8510 SDValue Op2 = Op.getOperand(2);
8511 DebugLoc DL = Op.getDebugLoc();
8514 if (Cond.getOpcode() == ISD::SETCC) {
8515 SDValue NewCond = LowerSETCC(Cond, DAG);
8516 if (NewCond.getNode())
8520 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8521 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8522 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8523 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8524 if (Cond.getOpcode() == X86ISD::SETCC &&
8525 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8526 isZero(Cond.getOperand(1).getOperand(1))) {
8527 SDValue Cmp = Cond.getOperand(1);
8529 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8531 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8532 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8533 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8535 SDValue CmpOp0 = Cmp.getOperand(0);
8536 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8537 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8539 SDValue Res = // Res = 0 or -1.
8540 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8541 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8543 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8544 Res = DAG.getNOT(DL, Res, Res.getValueType());
8546 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8547 if (N2C == 0 || !N2C->isNullValue())
8548 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8553 // Look past (and (setcc_carry (cmp ...)), 1).
8554 if (Cond.getOpcode() == ISD::AND &&
8555 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8556 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8557 if (C && C->getAPIntValue() == 1)
8558 Cond = Cond.getOperand(0);
8561 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8562 // setting operand in place of the X86ISD::SETCC.
8563 unsigned CondOpcode = Cond.getOpcode();
8564 if (CondOpcode == X86ISD::SETCC ||
8565 CondOpcode == X86ISD::SETCC_CARRY) {
8566 CC = Cond.getOperand(0);
8568 SDValue Cmp = Cond.getOperand(1);
8569 unsigned Opc = Cmp.getOpcode();
8570 EVT VT = Op.getValueType();
8572 bool IllegalFPCMov = false;
8573 if (VT.isFloatingPoint() && !VT.isVector() &&
8574 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8575 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8577 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8578 Opc == X86ISD::BT) { // FIXME
8582 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8583 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8584 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8585 Cond.getOperand(0).getValueType() != MVT::i8)) {
8586 SDValue LHS = Cond.getOperand(0);
8587 SDValue RHS = Cond.getOperand(1);
8591 switch (CondOpcode) {
8592 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8593 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8594 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8595 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8596 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8597 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8598 default: llvm_unreachable("unexpected overflowing operator");
8600 if (CondOpcode == ISD::UMULO)
8601 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8604 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8606 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8608 if (CondOpcode == ISD::UMULO)
8609 Cond = X86Op.getValue(2);
8611 Cond = X86Op.getValue(1);
8613 CC = DAG.getConstant(X86Cond, MVT::i8);
8618 // Look pass the truncate.
8619 if (Cond.getOpcode() == ISD::TRUNCATE)
8620 Cond = Cond.getOperand(0);
8622 // We know the result of AND is compared against zero. Try to match
8624 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8625 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8626 if (NewSetCC.getNode()) {
8627 CC = NewSetCC.getOperand(0);
8628 Cond = NewSetCC.getOperand(1);
8635 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8636 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8639 // a < b ? -1 : 0 -> RES = ~setcc_carry
8640 // a < b ? 0 : -1 -> RES = setcc_carry
8641 // a >= b ? -1 : 0 -> RES = setcc_carry
8642 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8643 if (Cond.getOpcode() == X86ISD::CMP) {
8644 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8646 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8647 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8648 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8649 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8650 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8651 return DAG.getNOT(DL, Res, Res.getValueType());
8656 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8657 // condition is true.
8658 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8659 SDValue Ops[] = { Op2, Op1, CC, Cond };
8660 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8663 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8664 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8665 // from the AND / OR.
8666 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8667 Opc = Op.getOpcode();
8668 if (Opc != ISD::OR && Opc != ISD::AND)
8670 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8671 Op.getOperand(0).hasOneUse() &&
8672 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8673 Op.getOperand(1).hasOneUse());
8676 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8677 // 1 and that the SETCC node has a single use.
8678 static bool isXor1OfSetCC(SDValue Op) {
8679 if (Op.getOpcode() != ISD::XOR)
8681 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8682 if (N1C && N1C->getAPIntValue() == 1) {
8683 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8684 Op.getOperand(0).hasOneUse();
8689 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8690 bool addTest = true;
8691 SDValue Chain = Op.getOperand(0);
8692 SDValue Cond = Op.getOperand(1);
8693 SDValue Dest = Op.getOperand(2);
8694 DebugLoc dl = Op.getDebugLoc();
8696 bool Inverted = false;
8698 if (Cond.getOpcode() == ISD::SETCC) {
8699 // Check for setcc([su]{add,sub,mul}o == 0).
8700 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8701 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8702 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8703 Cond.getOperand(0).getResNo() == 1 &&
8704 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8705 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8706 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8707 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8708 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8709 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8711 Cond = Cond.getOperand(0);
8713 SDValue NewCond = LowerSETCC(Cond, DAG);
8714 if (NewCond.getNode())
8719 // FIXME: LowerXALUO doesn't handle these!!
8720 else if (Cond.getOpcode() == X86ISD::ADD ||
8721 Cond.getOpcode() == X86ISD::SUB ||
8722 Cond.getOpcode() == X86ISD::SMUL ||
8723 Cond.getOpcode() == X86ISD::UMUL)
8724 Cond = LowerXALUO(Cond, DAG);
8727 // Look pass (and (setcc_carry (cmp ...)), 1).
8728 if (Cond.getOpcode() == ISD::AND &&
8729 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8730 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8731 if (C && C->getAPIntValue() == 1)
8732 Cond = Cond.getOperand(0);
8735 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8736 // setting operand in place of the X86ISD::SETCC.
8737 unsigned CondOpcode = Cond.getOpcode();
8738 if (CondOpcode == X86ISD::SETCC ||
8739 CondOpcode == X86ISD::SETCC_CARRY) {
8740 CC = Cond.getOperand(0);
8742 SDValue Cmp = Cond.getOperand(1);
8743 unsigned Opc = Cmp.getOpcode();
8744 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8745 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8749 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8753 // These can only come from an arithmetic instruction with overflow,
8754 // e.g. SADDO, UADDO.
8755 Cond = Cond.getNode()->getOperand(1);
8761 CondOpcode = Cond.getOpcode();
8762 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8763 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8764 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8765 Cond.getOperand(0).getValueType() != MVT::i8)) {
8766 SDValue LHS = Cond.getOperand(0);
8767 SDValue RHS = Cond.getOperand(1);
8771 switch (CondOpcode) {
8772 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8773 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8774 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8775 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8776 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8777 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8778 default: llvm_unreachable("unexpected overflowing operator");
8781 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8782 if (CondOpcode == ISD::UMULO)
8783 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8786 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8788 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8790 if (CondOpcode == ISD::UMULO)
8791 Cond = X86Op.getValue(2);
8793 Cond = X86Op.getValue(1);
8795 CC = DAG.getConstant(X86Cond, MVT::i8);
8799 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8800 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8801 if (CondOpc == ISD::OR) {
8802 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8803 // two branches instead of an explicit OR instruction with a
8805 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8806 isX86LogicalCmp(Cmp)) {
8807 CC = Cond.getOperand(0).getOperand(0);
8808 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8809 Chain, Dest, CC, Cmp);
8810 CC = Cond.getOperand(1).getOperand(0);
8814 } else { // ISD::AND
8815 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8816 // two branches instead of an explicit AND instruction with a
8817 // separate test. However, we only do this if this block doesn't
8818 // have a fall-through edge, because this requires an explicit
8819 // jmp when the condition is false.
8820 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8821 isX86LogicalCmp(Cmp) &&
8822 Op.getNode()->hasOneUse()) {
8823 X86::CondCode CCode =
8824 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8825 CCode = X86::GetOppositeBranchCondition(CCode);
8826 CC = DAG.getConstant(CCode, MVT::i8);
8827 SDNode *User = *Op.getNode()->use_begin();
8828 // Look for an unconditional branch following this conditional branch.
8829 // We need this because we need to reverse the successors in order
8830 // to implement FCMP_OEQ.
8831 if (User->getOpcode() == ISD::BR) {
8832 SDValue FalseBB = User->getOperand(1);
8834 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8835 assert(NewBR == User);
8839 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8840 Chain, Dest, CC, Cmp);
8841 X86::CondCode CCode =
8842 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8843 CCode = X86::GetOppositeBranchCondition(CCode);
8844 CC = DAG.getConstant(CCode, MVT::i8);
8850 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8851 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8852 // It should be transformed during dag combiner except when the condition
8853 // is set by a arithmetics with overflow node.
8854 X86::CondCode CCode =
8855 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8856 CCode = X86::GetOppositeBranchCondition(CCode);
8857 CC = DAG.getConstant(CCode, MVT::i8);
8858 Cond = Cond.getOperand(0).getOperand(1);
8860 } else if (Cond.getOpcode() == ISD::SETCC &&
8861 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8862 // For FCMP_OEQ, we can emit
8863 // two branches instead of an explicit AND instruction with a
8864 // separate test. However, we only do this if this block doesn't
8865 // have a fall-through edge, because this requires an explicit
8866 // jmp when the condition is false.
8867 if (Op.getNode()->hasOneUse()) {
8868 SDNode *User = *Op.getNode()->use_begin();
8869 // Look for an unconditional branch following this conditional branch.
8870 // We need this because we need to reverse the successors in order
8871 // to implement FCMP_OEQ.
8872 if (User->getOpcode() == ISD::BR) {
8873 SDValue FalseBB = User->getOperand(1);
8875 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8876 assert(NewBR == User);
8880 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8881 Cond.getOperand(0), Cond.getOperand(1));
8882 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8883 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8884 Chain, Dest, CC, Cmp);
8885 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8890 } else if (Cond.getOpcode() == ISD::SETCC &&
8891 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8892 // For FCMP_UNE, we can emit
8893 // two branches instead of an explicit AND instruction with a
8894 // separate test. However, we only do this if this block doesn't
8895 // have a fall-through edge, because this requires an explicit
8896 // jmp when the condition is false.
8897 if (Op.getNode()->hasOneUse()) {
8898 SDNode *User = *Op.getNode()->use_begin();
8899 // Look for an unconditional branch following this conditional branch.
8900 // We need this because we need to reverse the successors in order
8901 // to implement FCMP_UNE.
8902 if (User->getOpcode() == ISD::BR) {
8903 SDValue FalseBB = User->getOperand(1);
8905 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8906 assert(NewBR == User);
8909 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8910 Cond.getOperand(0), Cond.getOperand(1));
8911 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8912 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8913 Chain, Dest, CC, Cmp);
8914 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8924 // Look pass the truncate.
8925 if (Cond.getOpcode() == ISD::TRUNCATE)
8926 Cond = Cond.getOperand(0);
8928 // We know the result of AND is compared against zero. Try to match
8930 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8931 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8932 if (NewSetCC.getNode()) {
8933 CC = NewSetCC.getOperand(0);
8934 Cond = NewSetCC.getOperand(1);
8941 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8942 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8944 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8945 Chain, Dest, CC, Cond);
8949 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8950 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8951 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8952 // that the guard pages used by the OS virtual memory manager are allocated in
8953 // correct sequence.
8955 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8956 SelectionDAG &DAG) const {
8957 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8958 getTargetMachine().Options.EnableSegmentedStacks) &&
8959 "This should be used only on Windows targets or when segmented stacks "
8961 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8962 DebugLoc dl = Op.getDebugLoc();
8965 SDValue Chain = Op.getOperand(0);
8966 SDValue Size = Op.getOperand(1);
8967 // FIXME: Ensure alignment here
8969 bool Is64Bit = Subtarget->is64Bit();
8970 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8972 if (getTargetMachine().Options.EnableSegmentedStacks) {
8973 MachineFunction &MF = DAG.getMachineFunction();
8974 MachineRegisterInfo &MRI = MF.getRegInfo();
8977 // The 64 bit implementation of segmented stacks needs to clobber both r10
8978 // r11. This makes it impossible to use it along with nested parameters.
8979 const Function *F = MF.getFunction();
8981 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8983 if (I->hasNestAttr())
8984 report_fatal_error("Cannot use segmented stacks with functions that "
8985 "have nested arguments.");
8988 const TargetRegisterClass *AddrRegClass =
8989 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8990 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8991 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8992 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8993 DAG.getRegister(Vreg, SPTy));
8994 SDValue Ops1[2] = { Value, Chain };
8995 return DAG.getMergeValues(Ops1, 2, dl);
8998 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9000 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9001 Flag = Chain.getValue(1);
9002 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9004 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9005 Flag = Chain.getValue(1);
9007 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9009 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9010 return DAG.getMergeValues(Ops1, 2, dl);
9014 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9015 MachineFunction &MF = DAG.getMachineFunction();
9016 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9018 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9019 DebugLoc DL = Op.getDebugLoc();
9021 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9022 // vastart just stores the address of the VarArgsFrameIndex slot into the
9023 // memory location argument.
9024 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9026 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9027 MachinePointerInfo(SV), false, false, 0);
9031 // gp_offset (0 - 6 * 8)
9032 // fp_offset (48 - 48 + 8 * 16)
9033 // overflow_arg_area (point to parameters coming in memory).
9035 SmallVector<SDValue, 8> MemOps;
9036 SDValue FIN = Op.getOperand(1);
9038 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9039 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9041 FIN, MachinePointerInfo(SV), false, false, 0);
9042 MemOps.push_back(Store);
9045 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9046 FIN, DAG.getIntPtrConstant(4));
9047 Store = DAG.getStore(Op.getOperand(0), DL,
9048 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9050 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9051 MemOps.push_back(Store);
9053 // Store ptr to overflow_arg_area
9054 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9055 FIN, DAG.getIntPtrConstant(4));
9056 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9058 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9059 MachinePointerInfo(SV, 8),
9061 MemOps.push_back(Store);
9063 // Store ptr to reg_save_area.
9064 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9065 FIN, DAG.getIntPtrConstant(8));
9066 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9068 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9069 MachinePointerInfo(SV, 16), false, false, 0);
9070 MemOps.push_back(Store);
9071 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9072 &MemOps[0], MemOps.size());
9075 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9076 assert(Subtarget->is64Bit() &&
9077 "LowerVAARG only handles 64-bit va_arg!");
9078 assert((Subtarget->isTargetLinux() ||
9079 Subtarget->isTargetDarwin()) &&
9080 "Unhandled target in LowerVAARG");
9081 assert(Op.getNode()->getNumOperands() == 4);
9082 SDValue Chain = Op.getOperand(0);
9083 SDValue SrcPtr = Op.getOperand(1);
9084 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9085 unsigned Align = Op.getConstantOperandVal(3);
9086 DebugLoc dl = Op.getDebugLoc();
9088 EVT ArgVT = Op.getNode()->getValueType(0);
9089 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9090 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9093 // Decide which area this value should be read from.
9094 // TODO: Implement the AMD64 ABI in its entirety. This simple
9095 // selection mechanism works only for the basic types.
9096 if (ArgVT == MVT::f80) {
9097 llvm_unreachable("va_arg for f80 not yet implemented");
9098 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9099 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9100 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9101 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9103 llvm_unreachable("Unhandled argument type in LowerVAARG");
9107 // Sanity Check: Make sure using fp_offset makes sense.
9108 assert(!getTargetMachine().Options.UseSoftFloat &&
9109 !(DAG.getMachineFunction()
9110 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9111 Subtarget->hasSSE1());
9114 // Insert VAARG_64 node into the DAG
9115 // VAARG_64 returns two values: Variable Argument Address, Chain
9116 SmallVector<SDValue, 11> InstOps;
9117 InstOps.push_back(Chain);
9118 InstOps.push_back(SrcPtr);
9119 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9120 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9121 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9122 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9123 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9124 VTs, &InstOps[0], InstOps.size(),
9126 MachinePointerInfo(SV),
9131 Chain = VAARG.getValue(1);
9133 // Load the next argument and return it
9134 return DAG.getLoad(ArgVT, dl,
9137 MachinePointerInfo(),
9138 false, false, false, 0);
9141 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9142 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9143 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9144 SDValue Chain = Op.getOperand(0);
9145 SDValue DstPtr = Op.getOperand(1);
9146 SDValue SrcPtr = Op.getOperand(2);
9147 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9148 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9149 DebugLoc DL = Op.getDebugLoc();
9151 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9152 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9154 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9157 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9158 // may or may not be a constant. Takes immediate version of shift as input.
9159 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9160 SDValue SrcOp, SDValue ShAmt,
9161 SelectionDAG &DAG) {
9162 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9164 if (isa<ConstantSDNode>(ShAmt)) {
9166 default: llvm_unreachable("Unknown target vector shift node");
9170 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9174 // Change opcode to non-immediate version
9176 default: llvm_unreachable("Unknown target vector shift node");
9177 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9178 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9179 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9182 // Need to build a vector containing shift amount
9183 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9186 ShOps[1] = DAG.getConstant(0, MVT::i32);
9187 ShOps[2] = DAG.getUNDEF(MVT::i32);
9188 ShOps[3] = DAG.getUNDEF(MVT::i32);
9189 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9190 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9191 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9195 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9196 DebugLoc dl = Op.getDebugLoc();
9197 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9199 default: return SDValue(); // Don't custom lower most intrinsics.
9200 // Comparison intrinsics.
9201 case Intrinsic::x86_sse_comieq_ss:
9202 case Intrinsic::x86_sse_comilt_ss:
9203 case Intrinsic::x86_sse_comile_ss:
9204 case Intrinsic::x86_sse_comigt_ss:
9205 case Intrinsic::x86_sse_comige_ss:
9206 case Intrinsic::x86_sse_comineq_ss:
9207 case Intrinsic::x86_sse_ucomieq_ss:
9208 case Intrinsic::x86_sse_ucomilt_ss:
9209 case Intrinsic::x86_sse_ucomile_ss:
9210 case Intrinsic::x86_sse_ucomigt_ss:
9211 case Intrinsic::x86_sse_ucomige_ss:
9212 case Intrinsic::x86_sse_ucomineq_ss:
9213 case Intrinsic::x86_sse2_comieq_sd:
9214 case Intrinsic::x86_sse2_comilt_sd:
9215 case Intrinsic::x86_sse2_comile_sd:
9216 case Intrinsic::x86_sse2_comigt_sd:
9217 case Intrinsic::x86_sse2_comige_sd:
9218 case Intrinsic::x86_sse2_comineq_sd:
9219 case Intrinsic::x86_sse2_ucomieq_sd:
9220 case Intrinsic::x86_sse2_ucomilt_sd:
9221 case Intrinsic::x86_sse2_ucomile_sd:
9222 case Intrinsic::x86_sse2_ucomigt_sd:
9223 case Intrinsic::x86_sse2_ucomige_sd:
9224 case Intrinsic::x86_sse2_ucomineq_sd: {
9226 ISD::CondCode CC = ISD::SETCC_INVALID;
9228 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9229 case Intrinsic::x86_sse_comieq_ss:
9230 case Intrinsic::x86_sse2_comieq_sd:
9234 case Intrinsic::x86_sse_comilt_ss:
9235 case Intrinsic::x86_sse2_comilt_sd:
9239 case Intrinsic::x86_sse_comile_ss:
9240 case Intrinsic::x86_sse2_comile_sd:
9244 case Intrinsic::x86_sse_comigt_ss:
9245 case Intrinsic::x86_sse2_comigt_sd:
9249 case Intrinsic::x86_sse_comige_ss:
9250 case Intrinsic::x86_sse2_comige_sd:
9254 case Intrinsic::x86_sse_comineq_ss:
9255 case Intrinsic::x86_sse2_comineq_sd:
9259 case Intrinsic::x86_sse_ucomieq_ss:
9260 case Intrinsic::x86_sse2_ucomieq_sd:
9261 Opc = X86ISD::UCOMI;
9264 case Intrinsic::x86_sse_ucomilt_ss:
9265 case Intrinsic::x86_sse2_ucomilt_sd:
9266 Opc = X86ISD::UCOMI;
9269 case Intrinsic::x86_sse_ucomile_ss:
9270 case Intrinsic::x86_sse2_ucomile_sd:
9271 Opc = X86ISD::UCOMI;
9274 case Intrinsic::x86_sse_ucomigt_ss:
9275 case Intrinsic::x86_sse2_ucomigt_sd:
9276 Opc = X86ISD::UCOMI;
9279 case Intrinsic::x86_sse_ucomige_ss:
9280 case Intrinsic::x86_sse2_ucomige_sd:
9281 Opc = X86ISD::UCOMI;
9284 case Intrinsic::x86_sse_ucomineq_ss:
9285 case Intrinsic::x86_sse2_ucomineq_sd:
9286 Opc = X86ISD::UCOMI;
9291 SDValue LHS = Op.getOperand(1);
9292 SDValue RHS = Op.getOperand(2);
9293 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9294 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9295 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9296 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9297 DAG.getConstant(X86CC, MVT::i8), Cond);
9298 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9300 // XOP comparison intrinsics
9301 case Intrinsic::x86_xop_vpcomltb:
9302 case Intrinsic::x86_xop_vpcomltw:
9303 case Intrinsic::x86_xop_vpcomltd:
9304 case Intrinsic::x86_xop_vpcomltq:
9305 case Intrinsic::x86_xop_vpcomltub:
9306 case Intrinsic::x86_xop_vpcomltuw:
9307 case Intrinsic::x86_xop_vpcomltud:
9308 case Intrinsic::x86_xop_vpcomltuq:
9309 case Intrinsic::x86_xop_vpcomleb:
9310 case Intrinsic::x86_xop_vpcomlew:
9311 case Intrinsic::x86_xop_vpcomled:
9312 case Intrinsic::x86_xop_vpcomleq:
9313 case Intrinsic::x86_xop_vpcomleub:
9314 case Intrinsic::x86_xop_vpcomleuw:
9315 case Intrinsic::x86_xop_vpcomleud:
9316 case Intrinsic::x86_xop_vpcomleuq:
9317 case Intrinsic::x86_xop_vpcomgtb:
9318 case Intrinsic::x86_xop_vpcomgtw:
9319 case Intrinsic::x86_xop_vpcomgtd:
9320 case Intrinsic::x86_xop_vpcomgtq:
9321 case Intrinsic::x86_xop_vpcomgtub:
9322 case Intrinsic::x86_xop_vpcomgtuw:
9323 case Intrinsic::x86_xop_vpcomgtud:
9324 case Intrinsic::x86_xop_vpcomgtuq:
9325 case Intrinsic::x86_xop_vpcomgeb:
9326 case Intrinsic::x86_xop_vpcomgew:
9327 case Intrinsic::x86_xop_vpcomged:
9328 case Intrinsic::x86_xop_vpcomgeq:
9329 case Intrinsic::x86_xop_vpcomgeub:
9330 case Intrinsic::x86_xop_vpcomgeuw:
9331 case Intrinsic::x86_xop_vpcomgeud:
9332 case Intrinsic::x86_xop_vpcomgeuq:
9333 case Intrinsic::x86_xop_vpcomeqb:
9334 case Intrinsic::x86_xop_vpcomeqw:
9335 case Intrinsic::x86_xop_vpcomeqd:
9336 case Intrinsic::x86_xop_vpcomeqq:
9337 case Intrinsic::x86_xop_vpcomequb:
9338 case Intrinsic::x86_xop_vpcomequw:
9339 case Intrinsic::x86_xop_vpcomequd:
9340 case Intrinsic::x86_xop_vpcomequq:
9341 case Intrinsic::x86_xop_vpcomneb:
9342 case Intrinsic::x86_xop_vpcomnew:
9343 case Intrinsic::x86_xop_vpcomned:
9344 case Intrinsic::x86_xop_vpcomneq:
9345 case Intrinsic::x86_xop_vpcomneub:
9346 case Intrinsic::x86_xop_vpcomneuw:
9347 case Intrinsic::x86_xop_vpcomneud:
9348 case Intrinsic::x86_xop_vpcomneuq:
9349 case Intrinsic::x86_xop_vpcomfalseb:
9350 case Intrinsic::x86_xop_vpcomfalsew:
9351 case Intrinsic::x86_xop_vpcomfalsed:
9352 case Intrinsic::x86_xop_vpcomfalseq:
9353 case Intrinsic::x86_xop_vpcomfalseub:
9354 case Intrinsic::x86_xop_vpcomfalseuw:
9355 case Intrinsic::x86_xop_vpcomfalseud:
9356 case Intrinsic::x86_xop_vpcomfalseuq:
9357 case Intrinsic::x86_xop_vpcomtrueb:
9358 case Intrinsic::x86_xop_vpcomtruew:
9359 case Intrinsic::x86_xop_vpcomtrued:
9360 case Intrinsic::x86_xop_vpcomtrueq:
9361 case Intrinsic::x86_xop_vpcomtrueub:
9362 case Intrinsic::x86_xop_vpcomtrueuw:
9363 case Intrinsic::x86_xop_vpcomtrueud:
9364 case Intrinsic::x86_xop_vpcomtrueuq: {
9369 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9370 case Intrinsic::x86_xop_vpcomltb:
9371 case Intrinsic::x86_xop_vpcomltw:
9372 case Intrinsic::x86_xop_vpcomltd:
9373 case Intrinsic::x86_xop_vpcomltq:
9375 Opc = X86ISD::VPCOM;
9377 case Intrinsic::x86_xop_vpcomltub:
9378 case Intrinsic::x86_xop_vpcomltuw:
9379 case Intrinsic::x86_xop_vpcomltud:
9380 case Intrinsic::x86_xop_vpcomltuq:
9382 Opc = X86ISD::VPCOMU;
9384 case Intrinsic::x86_xop_vpcomleb:
9385 case Intrinsic::x86_xop_vpcomlew:
9386 case Intrinsic::x86_xop_vpcomled:
9387 case Intrinsic::x86_xop_vpcomleq:
9389 Opc = X86ISD::VPCOM;
9391 case Intrinsic::x86_xop_vpcomleub:
9392 case Intrinsic::x86_xop_vpcomleuw:
9393 case Intrinsic::x86_xop_vpcomleud:
9394 case Intrinsic::x86_xop_vpcomleuq:
9396 Opc = X86ISD::VPCOMU;
9398 case Intrinsic::x86_xop_vpcomgtb:
9399 case Intrinsic::x86_xop_vpcomgtw:
9400 case Intrinsic::x86_xop_vpcomgtd:
9401 case Intrinsic::x86_xop_vpcomgtq:
9403 Opc = X86ISD::VPCOM;
9405 case Intrinsic::x86_xop_vpcomgtub:
9406 case Intrinsic::x86_xop_vpcomgtuw:
9407 case Intrinsic::x86_xop_vpcomgtud:
9408 case Intrinsic::x86_xop_vpcomgtuq:
9410 Opc = X86ISD::VPCOMU;
9412 case Intrinsic::x86_xop_vpcomgeb:
9413 case Intrinsic::x86_xop_vpcomgew:
9414 case Intrinsic::x86_xop_vpcomged:
9415 case Intrinsic::x86_xop_vpcomgeq:
9417 Opc = X86ISD::VPCOM;
9419 case Intrinsic::x86_xop_vpcomgeub:
9420 case Intrinsic::x86_xop_vpcomgeuw:
9421 case Intrinsic::x86_xop_vpcomgeud:
9422 case Intrinsic::x86_xop_vpcomgeuq:
9424 Opc = X86ISD::VPCOMU;
9426 case Intrinsic::x86_xop_vpcomeqb:
9427 case Intrinsic::x86_xop_vpcomeqw:
9428 case Intrinsic::x86_xop_vpcomeqd:
9429 case Intrinsic::x86_xop_vpcomeqq:
9431 Opc = X86ISD::VPCOM;
9433 case Intrinsic::x86_xop_vpcomequb:
9434 case Intrinsic::x86_xop_vpcomequw:
9435 case Intrinsic::x86_xop_vpcomequd:
9436 case Intrinsic::x86_xop_vpcomequq:
9438 Opc = X86ISD::VPCOMU;
9440 case Intrinsic::x86_xop_vpcomneb:
9441 case Intrinsic::x86_xop_vpcomnew:
9442 case Intrinsic::x86_xop_vpcomned:
9443 case Intrinsic::x86_xop_vpcomneq:
9445 Opc = X86ISD::VPCOM;
9447 case Intrinsic::x86_xop_vpcomneub:
9448 case Intrinsic::x86_xop_vpcomneuw:
9449 case Intrinsic::x86_xop_vpcomneud:
9450 case Intrinsic::x86_xop_vpcomneuq:
9452 Opc = X86ISD::VPCOMU;
9454 case Intrinsic::x86_xop_vpcomfalseb:
9455 case Intrinsic::x86_xop_vpcomfalsew:
9456 case Intrinsic::x86_xop_vpcomfalsed:
9457 case Intrinsic::x86_xop_vpcomfalseq:
9459 Opc = X86ISD::VPCOM;
9461 case Intrinsic::x86_xop_vpcomfalseub:
9462 case Intrinsic::x86_xop_vpcomfalseuw:
9463 case Intrinsic::x86_xop_vpcomfalseud:
9464 case Intrinsic::x86_xop_vpcomfalseuq:
9466 Opc = X86ISD::VPCOMU;
9468 case Intrinsic::x86_xop_vpcomtrueb:
9469 case Intrinsic::x86_xop_vpcomtruew:
9470 case Intrinsic::x86_xop_vpcomtrued:
9471 case Intrinsic::x86_xop_vpcomtrueq:
9473 Opc = X86ISD::VPCOM;
9475 case Intrinsic::x86_xop_vpcomtrueub:
9476 case Intrinsic::x86_xop_vpcomtrueuw:
9477 case Intrinsic::x86_xop_vpcomtrueud:
9478 case Intrinsic::x86_xop_vpcomtrueuq:
9480 Opc = X86ISD::VPCOMU;
9484 SDValue LHS = Op.getOperand(1);
9485 SDValue RHS = Op.getOperand(2);
9486 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9487 DAG.getConstant(CC, MVT::i8));
9490 // Arithmetic intrinsics.
9491 case Intrinsic::x86_sse2_pmulu_dq:
9492 case Intrinsic::x86_avx2_pmulu_dq:
9493 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9494 Op.getOperand(1), Op.getOperand(2));
9495 case Intrinsic::x86_sse3_hadd_ps:
9496 case Intrinsic::x86_sse3_hadd_pd:
9497 case Intrinsic::x86_avx_hadd_ps_256:
9498 case Intrinsic::x86_avx_hadd_pd_256:
9499 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9500 Op.getOperand(1), Op.getOperand(2));
9501 case Intrinsic::x86_sse3_hsub_ps:
9502 case Intrinsic::x86_sse3_hsub_pd:
9503 case Intrinsic::x86_avx_hsub_ps_256:
9504 case Intrinsic::x86_avx_hsub_pd_256:
9505 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9506 Op.getOperand(1), Op.getOperand(2));
9507 case Intrinsic::x86_ssse3_phadd_w_128:
9508 case Intrinsic::x86_ssse3_phadd_d_128:
9509 case Intrinsic::x86_avx2_phadd_w:
9510 case Intrinsic::x86_avx2_phadd_d:
9511 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9512 Op.getOperand(1), Op.getOperand(2));
9513 case Intrinsic::x86_ssse3_phsub_w_128:
9514 case Intrinsic::x86_ssse3_phsub_d_128:
9515 case Intrinsic::x86_avx2_phsub_w:
9516 case Intrinsic::x86_avx2_phsub_d:
9517 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9518 Op.getOperand(1), Op.getOperand(2));
9519 case Intrinsic::x86_avx2_psllv_d:
9520 case Intrinsic::x86_avx2_psllv_q:
9521 case Intrinsic::x86_avx2_psllv_d_256:
9522 case Intrinsic::x86_avx2_psllv_q_256:
9523 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9524 Op.getOperand(1), Op.getOperand(2));
9525 case Intrinsic::x86_avx2_psrlv_d:
9526 case Intrinsic::x86_avx2_psrlv_q:
9527 case Intrinsic::x86_avx2_psrlv_d_256:
9528 case Intrinsic::x86_avx2_psrlv_q_256:
9529 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9530 Op.getOperand(1), Op.getOperand(2));
9531 case Intrinsic::x86_avx2_psrav_d:
9532 case Intrinsic::x86_avx2_psrav_d_256:
9533 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9534 Op.getOperand(1), Op.getOperand(2));
9535 case Intrinsic::x86_ssse3_pshuf_b_128:
9536 case Intrinsic::x86_avx2_pshuf_b:
9537 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9538 Op.getOperand(1), Op.getOperand(2));
9539 case Intrinsic::x86_ssse3_psign_b_128:
9540 case Intrinsic::x86_ssse3_psign_w_128:
9541 case Intrinsic::x86_ssse3_psign_d_128:
9542 case Intrinsic::x86_avx2_psign_b:
9543 case Intrinsic::x86_avx2_psign_w:
9544 case Intrinsic::x86_avx2_psign_d:
9545 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9546 Op.getOperand(1), Op.getOperand(2));
9547 case Intrinsic::x86_sse41_insertps:
9548 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9549 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9550 case Intrinsic::x86_avx_vperm2f128_ps_256:
9551 case Intrinsic::x86_avx_vperm2f128_pd_256:
9552 case Intrinsic::x86_avx_vperm2f128_si_256:
9553 case Intrinsic::x86_avx2_vperm2i128:
9554 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9555 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9556 case Intrinsic::x86_avx_vpermil_ps:
9557 case Intrinsic::x86_avx_vpermil_pd:
9558 case Intrinsic::x86_avx_vpermil_ps_256:
9559 case Intrinsic::x86_avx_vpermil_pd_256:
9560 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(),
9561 Op.getOperand(1), Op.getOperand(2));
9563 // ptest and testp intrinsics. The intrinsic these come from are designed to
9564 // return an integer value, not just an instruction so lower it to the ptest
9565 // or testp pattern and a setcc for the result.
9566 case Intrinsic::x86_sse41_ptestz:
9567 case Intrinsic::x86_sse41_ptestc:
9568 case Intrinsic::x86_sse41_ptestnzc:
9569 case Intrinsic::x86_avx_ptestz_256:
9570 case Intrinsic::x86_avx_ptestc_256:
9571 case Intrinsic::x86_avx_ptestnzc_256:
9572 case Intrinsic::x86_avx_vtestz_ps:
9573 case Intrinsic::x86_avx_vtestc_ps:
9574 case Intrinsic::x86_avx_vtestnzc_ps:
9575 case Intrinsic::x86_avx_vtestz_pd:
9576 case Intrinsic::x86_avx_vtestc_pd:
9577 case Intrinsic::x86_avx_vtestnzc_pd:
9578 case Intrinsic::x86_avx_vtestz_ps_256:
9579 case Intrinsic::x86_avx_vtestc_ps_256:
9580 case Intrinsic::x86_avx_vtestnzc_ps_256:
9581 case Intrinsic::x86_avx_vtestz_pd_256:
9582 case Intrinsic::x86_avx_vtestc_pd_256:
9583 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9584 bool IsTestPacked = false;
9587 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9588 case Intrinsic::x86_avx_vtestz_ps:
9589 case Intrinsic::x86_avx_vtestz_pd:
9590 case Intrinsic::x86_avx_vtestz_ps_256:
9591 case Intrinsic::x86_avx_vtestz_pd_256:
9592 IsTestPacked = true; // Fallthrough
9593 case Intrinsic::x86_sse41_ptestz:
9594 case Intrinsic::x86_avx_ptestz_256:
9596 X86CC = X86::COND_E;
9598 case Intrinsic::x86_avx_vtestc_ps:
9599 case Intrinsic::x86_avx_vtestc_pd:
9600 case Intrinsic::x86_avx_vtestc_ps_256:
9601 case Intrinsic::x86_avx_vtestc_pd_256:
9602 IsTestPacked = true; // Fallthrough
9603 case Intrinsic::x86_sse41_ptestc:
9604 case Intrinsic::x86_avx_ptestc_256:
9606 X86CC = X86::COND_B;
9608 case Intrinsic::x86_avx_vtestnzc_ps:
9609 case Intrinsic::x86_avx_vtestnzc_pd:
9610 case Intrinsic::x86_avx_vtestnzc_ps_256:
9611 case Intrinsic::x86_avx_vtestnzc_pd_256:
9612 IsTestPacked = true; // Fallthrough
9613 case Intrinsic::x86_sse41_ptestnzc:
9614 case Intrinsic::x86_avx_ptestnzc_256:
9616 X86CC = X86::COND_A;
9620 SDValue LHS = Op.getOperand(1);
9621 SDValue RHS = Op.getOperand(2);
9622 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9623 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9624 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9625 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9626 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9629 // SSE/AVX shift intrinsics
9630 case Intrinsic::x86_sse2_psll_w:
9631 case Intrinsic::x86_sse2_psll_d:
9632 case Intrinsic::x86_sse2_psll_q:
9633 case Intrinsic::x86_avx2_psll_w:
9634 case Intrinsic::x86_avx2_psll_d:
9635 case Intrinsic::x86_avx2_psll_q:
9636 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9637 Op.getOperand(1), Op.getOperand(2));
9638 case Intrinsic::x86_sse2_psrl_w:
9639 case Intrinsic::x86_sse2_psrl_d:
9640 case Intrinsic::x86_sse2_psrl_q:
9641 case Intrinsic::x86_avx2_psrl_w:
9642 case Intrinsic::x86_avx2_psrl_d:
9643 case Intrinsic::x86_avx2_psrl_q:
9644 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9645 Op.getOperand(1), Op.getOperand(2));
9646 case Intrinsic::x86_sse2_psra_w:
9647 case Intrinsic::x86_sse2_psra_d:
9648 case Intrinsic::x86_avx2_psra_w:
9649 case Intrinsic::x86_avx2_psra_d:
9650 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9651 Op.getOperand(1), Op.getOperand(2));
9652 case Intrinsic::x86_sse2_pslli_w:
9653 case Intrinsic::x86_sse2_pslli_d:
9654 case Intrinsic::x86_sse2_pslli_q:
9655 case Intrinsic::x86_avx2_pslli_w:
9656 case Intrinsic::x86_avx2_pslli_d:
9657 case Intrinsic::x86_avx2_pslli_q:
9658 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9659 Op.getOperand(1), Op.getOperand(2), DAG);
9660 case Intrinsic::x86_sse2_psrli_w:
9661 case Intrinsic::x86_sse2_psrli_d:
9662 case Intrinsic::x86_sse2_psrli_q:
9663 case Intrinsic::x86_avx2_psrli_w:
9664 case Intrinsic::x86_avx2_psrli_d:
9665 case Intrinsic::x86_avx2_psrli_q:
9666 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9667 Op.getOperand(1), Op.getOperand(2), DAG);
9668 case Intrinsic::x86_sse2_psrai_w:
9669 case Intrinsic::x86_sse2_psrai_d:
9670 case Intrinsic::x86_avx2_psrai_w:
9671 case Intrinsic::x86_avx2_psrai_d:
9672 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9673 Op.getOperand(1), Op.getOperand(2), DAG);
9674 // Fix vector shift instructions where the last operand is a non-immediate
9676 case Intrinsic::x86_mmx_pslli_w:
9677 case Intrinsic::x86_mmx_pslli_d:
9678 case Intrinsic::x86_mmx_pslli_q:
9679 case Intrinsic::x86_mmx_psrli_w:
9680 case Intrinsic::x86_mmx_psrli_d:
9681 case Intrinsic::x86_mmx_psrli_q:
9682 case Intrinsic::x86_mmx_psrai_w:
9683 case Intrinsic::x86_mmx_psrai_d: {
9684 SDValue ShAmt = Op.getOperand(2);
9685 if (isa<ConstantSDNode>(ShAmt))
9688 unsigned NewIntNo = 0;
9690 case Intrinsic::x86_mmx_pslli_w:
9691 NewIntNo = Intrinsic::x86_mmx_psll_w;
9693 case Intrinsic::x86_mmx_pslli_d:
9694 NewIntNo = Intrinsic::x86_mmx_psll_d;
9696 case Intrinsic::x86_mmx_pslli_q:
9697 NewIntNo = Intrinsic::x86_mmx_psll_q;
9699 case Intrinsic::x86_mmx_psrli_w:
9700 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9702 case Intrinsic::x86_mmx_psrli_d:
9703 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9705 case Intrinsic::x86_mmx_psrli_q:
9706 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9708 case Intrinsic::x86_mmx_psrai_w:
9709 NewIntNo = Intrinsic::x86_mmx_psra_w;
9711 case Intrinsic::x86_mmx_psrai_d:
9712 NewIntNo = Intrinsic::x86_mmx_psra_d;
9714 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9717 // The vector shift intrinsics with scalars uses 32b shift amounts but
9718 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9720 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9721 DAG.getConstant(0, MVT::i32));
9722 // FIXME this must be lowered to get rid of the invalid type.
9724 EVT VT = Op.getValueType();
9725 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9726 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9727 DAG.getConstant(NewIntNo, MVT::i32),
9728 Op.getOperand(1), ShAmt);
9733 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9734 SelectionDAG &DAG) const {
9735 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9736 MFI->setReturnAddressIsTaken(true);
9738 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9739 DebugLoc dl = Op.getDebugLoc();
9742 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9744 DAG.getConstant(TD->getPointerSize(),
9745 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9746 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9747 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9749 MachinePointerInfo(), false, false, false, 0);
9752 // Just load the return address.
9753 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9754 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9755 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9758 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9759 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9760 MFI->setFrameAddressIsTaken(true);
9762 EVT VT = Op.getValueType();
9763 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9764 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9765 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9766 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9768 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9769 MachinePointerInfo(),
9770 false, false, false, 0);
9774 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9775 SelectionDAG &DAG) const {
9776 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9779 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9780 MachineFunction &MF = DAG.getMachineFunction();
9781 SDValue Chain = Op.getOperand(0);
9782 SDValue Offset = Op.getOperand(1);
9783 SDValue Handler = Op.getOperand(2);
9784 DebugLoc dl = Op.getDebugLoc();
9786 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9787 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9789 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9791 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9792 DAG.getIntPtrConstant(TD->getPointerSize()));
9793 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9794 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9796 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9797 MF.getRegInfo().addLiveOut(StoreAddrReg);
9799 return DAG.getNode(X86ISD::EH_RETURN, dl,
9801 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9804 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9805 SelectionDAG &DAG) const {
9806 return Op.getOperand(0);
9809 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9810 SelectionDAG &DAG) const {
9811 SDValue Root = Op.getOperand(0);
9812 SDValue Trmp = Op.getOperand(1); // trampoline
9813 SDValue FPtr = Op.getOperand(2); // nested function
9814 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9815 DebugLoc dl = Op.getDebugLoc();
9817 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9819 if (Subtarget->is64Bit()) {
9820 SDValue OutChains[6];
9822 // Large code-model.
9823 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9824 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9826 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9827 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9829 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9831 // Load the pointer to the nested function into R11.
9832 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9833 SDValue Addr = Trmp;
9834 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9835 Addr, MachinePointerInfo(TrmpAddr),
9838 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9839 DAG.getConstant(2, MVT::i64));
9840 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9841 MachinePointerInfo(TrmpAddr, 2),
9844 // Load the 'nest' parameter value into R10.
9845 // R10 is specified in X86CallingConv.td
9846 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9847 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9848 DAG.getConstant(10, MVT::i64));
9849 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9850 Addr, MachinePointerInfo(TrmpAddr, 10),
9853 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9854 DAG.getConstant(12, MVT::i64));
9855 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9856 MachinePointerInfo(TrmpAddr, 12),
9859 // Jump to the nested function.
9860 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9861 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9862 DAG.getConstant(20, MVT::i64));
9863 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9864 Addr, MachinePointerInfo(TrmpAddr, 20),
9867 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9868 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9869 DAG.getConstant(22, MVT::i64));
9870 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9871 MachinePointerInfo(TrmpAddr, 22),
9874 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9876 const Function *Func =
9877 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9878 CallingConv::ID CC = Func->getCallingConv();
9883 llvm_unreachable("Unsupported calling convention");
9884 case CallingConv::C:
9885 case CallingConv::X86_StdCall: {
9886 // Pass 'nest' parameter in ECX.
9887 // Must be kept in sync with X86CallingConv.td
9890 // Check that ECX wasn't needed by an 'inreg' parameter.
9891 FunctionType *FTy = Func->getFunctionType();
9892 const AttrListPtr &Attrs = Func->getAttributes();
9894 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9895 unsigned InRegCount = 0;
9898 for (FunctionType::param_iterator I = FTy->param_begin(),
9899 E = FTy->param_end(); I != E; ++I, ++Idx)
9900 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9901 // FIXME: should only count parameters that are lowered to integers.
9902 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9904 if (InRegCount > 2) {
9905 report_fatal_error("Nest register in use - reduce number of inreg"
9911 case CallingConv::X86_FastCall:
9912 case CallingConv::X86_ThisCall:
9913 case CallingConv::Fast:
9914 // Pass 'nest' parameter in EAX.
9915 // Must be kept in sync with X86CallingConv.td
9920 SDValue OutChains[4];
9923 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9924 DAG.getConstant(10, MVT::i32));
9925 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9927 // This is storing the opcode for MOV32ri.
9928 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9929 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9930 OutChains[0] = DAG.getStore(Root, dl,
9931 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9932 Trmp, MachinePointerInfo(TrmpAddr),
9935 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9936 DAG.getConstant(1, MVT::i32));
9937 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9938 MachinePointerInfo(TrmpAddr, 1),
9941 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9942 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9943 DAG.getConstant(5, MVT::i32));
9944 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9945 MachinePointerInfo(TrmpAddr, 5),
9948 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9949 DAG.getConstant(6, MVT::i32));
9950 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9951 MachinePointerInfo(TrmpAddr, 6),
9954 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9958 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9959 SelectionDAG &DAG) const {
9961 The rounding mode is in bits 11:10 of FPSR, and has the following
9968 FLT_ROUNDS, on the other hand, expects the following:
9975 To perform the conversion, we do:
9976 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9979 MachineFunction &MF = DAG.getMachineFunction();
9980 const TargetMachine &TM = MF.getTarget();
9981 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9982 unsigned StackAlignment = TFI.getStackAlignment();
9983 EVT VT = Op.getValueType();
9984 DebugLoc DL = Op.getDebugLoc();
9986 // Save FP Control Word to stack slot
9987 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9988 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9991 MachineMemOperand *MMO =
9992 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9993 MachineMemOperand::MOStore, 2, 2);
9995 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9996 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9997 DAG.getVTList(MVT::Other),
9998 Ops, 2, MVT::i16, MMO);
10000 // Load FP Control Word from stack slot
10001 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10002 MachinePointerInfo(), false, false, false, 0);
10004 // Transform as necessary
10006 DAG.getNode(ISD::SRL, DL, MVT::i16,
10007 DAG.getNode(ISD::AND, DL, MVT::i16,
10008 CWD, DAG.getConstant(0x800, MVT::i16)),
10009 DAG.getConstant(11, MVT::i8));
10011 DAG.getNode(ISD::SRL, DL, MVT::i16,
10012 DAG.getNode(ISD::AND, DL, MVT::i16,
10013 CWD, DAG.getConstant(0x400, MVT::i16)),
10014 DAG.getConstant(9, MVT::i8));
10017 DAG.getNode(ISD::AND, DL, MVT::i16,
10018 DAG.getNode(ISD::ADD, DL, MVT::i16,
10019 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10020 DAG.getConstant(1, MVT::i16)),
10021 DAG.getConstant(3, MVT::i16));
10024 return DAG.getNode((VT.getSizeInBits() < 16 ?
10025 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10028 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10029 EVT VT = Op.getValueType();
10031 unsigned NumBits = VT.getSizeInBits();
10032 DebugLoc dl = Op.getDebugLoc();
10034 Op = Op.getOperand(0);
10035 if (VT == MVT::i8) {
10036 // Zero extend to i32 since there is not an i8 bsr.
10038 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10041 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10042 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10043 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10045 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10048 DAG.getConstant(NumBits+NumBits-1, OpVT),
10049 DAG.getConstant(X86::COND_E, MVT::i8),
10052 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10054 // Finally xor with NumBits-1.
10055 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10058 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10062 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10063 SelectionDAG &DAG) const {
10064 EVT VT = Op.getValueType();
10066 unsigned NumBits = VT.getSizeInBits();
10067 DebugLoc dl = Op.getDebugLoc();
10069 Op = Op.getOperand(0);
10070 if (VT == MVT::i8) {
10071 // Zero extend to i32 since there is not an i8 bsr.
10073 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10076 // Issue a bsr (scan bits in reverse).
10077 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10078 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10080 // And xor with NumBits-1.
10081 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10084 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10088 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10089 EVT VT = Op.getValueType();
10090 unsigned NumBits = VT.getSizeInBits();
10091 DebugLoc dl = Op.getDebugLoc();
10092 Op = Op.getOperand(0);
10094 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10095 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10096 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10098 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10101 DAG.getConstant(NumBits, VT),
10102 DAG.getConstant(X86::COND_E, MVT::i8),
10105 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10108 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10109 // ones, and then concatenate the result back.
10110 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10111 EVT VT = Op.getValueType();
10113 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10114 "Unsupported value type for operation");
10116 int NumElems = VT.getVectorNumElements();
10117 DebugLoc dl = Op.getDebugLoc();
10118 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10119 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10121 // Extract the LHS vectors
10122 SDValue LHS = Op.getOperand(0);
10123 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10124 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10126 // Extract the RHS vectors
10127 SDValue RHS = Op.getOperand(1);
10128 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10129 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10131 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10132 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10134 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10135 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10136 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10139 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10140 assert(Op.getValueType().getSizeInBits() == 256 &&
10141 Op.getValueType().isInteger() &&
10142 "Only handle AVX 256-bit vector integer operation");
10143 return Lower256IntArith(Op, DAG);
10146 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10147 assert(Op.getValueType().getSizeInBits() == 256 &&
10148 Op.getValueType().isInteger() &&
10149 "Only handle AVX 256-bit vector integer operation");
10150 return Lower256IntArith(Op, DAG);
10153 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10154 EVT VT = Op.getValueType();
10156 // Decompose 256-bit ops into smaller 128-bit ops.
10157 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10158 return Lower256IntArith(Op, DAG);
10160 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10161 "Only know how to lower V2I64/V4I64 multiply");
10163 DebugLoc dl = Op.getDebugLoc();
10165 // Ahi = psrlqi(a, 32);
10166 // Bhi = psrlqi(b, 32);
10168 // AloBlo = pmuludq(a, b);
10169 // AloBhi = pmuludq(a, Bhi);
10170 // AhiBlo = pmuludq(Ahi, b);
10172 // AloBhi = psllqi(AloBhi, 32);
10173 // AhiBlo = psllqi(AhiBlo, 32);
10174 // return AloBlo + AloBhi + AhiBlo;
10176 SDValue A = Op.getOperand(0);
10177 SDValue B = Op.getOperand(1);
10179 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10181 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10182 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10184 // Bit cast to 32-bit vectors for MULUDQ
10185 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10186 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10187 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10188 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10189 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10191 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10192 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10193 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10195 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10196 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10198 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10199 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10202 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10204 EVT VT = Op.getValueType();
10205 DebugLoc dl = Op.getDebugLoc();
10206 SDValue R = Op.getOperand(0);
10207 SDValue Amt = Op.getOperand(1);
10208 LLVMContext *Context = DAG.getContext();
10210 if (!Subtarget->hasSSE2())
10213 // Optimize shl/srl/sra with constant shift amount.
10214 if (isSplatVector(Amt.getNode())) {
10215 SDValue SclrAmt = Amt->getOperand(0);
10216 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10217 uint64_t ShiftAmt = C->getZExtValue();
10219 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10220 (Subtarget->hasAVX2() &&
10221 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10222 if (Op.getOpcode() == ISD::SHL)
10223 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10224 DAG.getConstant(ShiftAmt, MVT::i32));
10225 if (Op.getOpcode() == ISD::SRL)
10226 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10227 DAG.getConstant(ShiftAmt, MVT::i32));
10228 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10229 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10230 DAG.getConstant(ShiftAmt, MVT::i32));
10233 if (VT == MVT::v16i8) {
10234 if (Op.getOpcode() == ISD::SHL) {
10235 // Make a large shift.
10236 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10237 DAG.getConstant(ShiftAmt, MVT::i32));
10238 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10239 // Zero out the rightmost bits.
10240 SmallVector<SDValue, 16> V(16,
10241 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10243 return DAG.getNode(ISD::AND, dl, VT, SHL,
10244 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10246 if (Op.getOpcode() == ISD::SRL) {
10247 // Make a large shift.
10248 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10249 DAG.getConstant(ShiftAmt, MVT::i32));
10250 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10251 // Zero out the leftmost bits.
10252 SmallVector<SDValue, 16> V(16,
10253 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10255 return DAG.getNode(ISD::AND, dl, VT, SRL,
10256 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10258 if (Op.getOpcode() == ISD::SRA) {
10259 if (ShiftAmt == 7) {
10260 // R s>> 7 === R s< 0
10261 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10262 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10265 // R s>> a === ((R u>> a) ^ m) - m
10266 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10267 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10269 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10270 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10271 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10276 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10277 if (Op.getOpcode() == ISD::SHL) {
10278 // Make a large shift.
10279 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10280 DAG.getConstant(ShiftAmt, MVT::i32));
10281 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10282 // Zero out the rightmost bits.
10283 SmallVector<SDValue, 32> V(32,
10284 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10286 return DAG.getNode(ISD::AND, dl, VT, SHL,
10287 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10289 if (Op.getOpcode() == ISD::SRL) {
10290 // Make a large shift.
10291 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10292 DAG.getConstant(ShiftAmt, MVT::i32));
10293 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10294 // Zero out the leftmost bits.
10295 SmallVector<SDValue, 32> V(32,
10296 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10298 return DAG.getNode(ISD::AND, dl, VT, SRL,
10299 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10301 if (Op.getOpcode() == ISD::SRA) {
10302 if (ShiftAmt == 7) {
10303 // R s>> 7 === R s< 0
10304 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10305 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10308 // R s>> a === ((R u>> a) ^ m) - m
10309 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10310 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10312 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10313 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10314 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10321 // Lower SHL with variable shift amount.
10322 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10323 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10324 DAG.getConstant(23, MVT::i32));
10326 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10327 Constant *C = ConstantDataVector::get(*Context, CV);
10328 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10329 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10330 MachinePointerInfo::getConstantPool(),
10331 false, false, false, 16);
10333 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10334 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10335 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10336 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10338 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10339 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10342 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10343 DAG.getConstant(5, MVT::i32));
10344 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10346 // Turn 'a' into a mask suitable for VSELECT
10347 SDValue VSelM = DAG.getConstant(0x80, VT);
10348 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10349 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10351 SDValue CM1 = DAG.getConstant(0x0f, VT);
10352 SDValue CM2 = DAG.getConstant(0x3f, VT);
10354 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10355 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10356 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10357 DAG.getConstant(4, MVT::i32), DAG);
10358 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10359 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10362 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10363 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10364 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10366 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10367 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10368 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10369 DAG.getConstant(2, MVT::i32), DAG);
10370 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10371 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10374 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10375 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10376 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10378 // return VSELECT(r, r+r, a);
10379 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10380 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10384 // Decompose 256-bit shifts into smaller 128-bit shifts.
10385 if (VT.getSizeInBits() == 256) {
10386 unsigned NumElems = VT.getVectorNumElements();
10387 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10388 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10390 // Extract the two vectors
10391 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10392 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10395 // Recreate the shift amount vectors
10396 SDValue Amt1, Amt2;
10397 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10398 // Constant shift amount
10399 SmallVector<SDValue, 4> Amt1Csts;
10400 SmallVector<SDValue, 4> Amt2Csts;
10401 for (unsigned i = 0; i != NumElems/2; ++i)
10402 Amt1Csts.push_back(Amt->getOperand(i));
10403 for (unsigned i = NumElems/2; i != NumElems; ++i)
10404 Amt2Csts.push_back(Amt->getOperand(i));
10406 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10407 &Amt1Csts[0], NumElems/2);
10408 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10409 &Amt2Csts[0], NumElems/2);
10411 // Variable shift amount
10412 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10413 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10417 // Issue new vector shifts for the smaller types
10418 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10419 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10421 // Concatenate the result back
10422 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10428 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10429 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10430 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10431 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10432 // has only one use.
10433 SDNode *N = Op.getNode();
10434 SDValue LHS = N->getOperand(0);
10435 SDValue RHS = N->getOperand(1);
10436 unsigned BaseOp = 0;
10438 DebugLoc DL = Op.getDebugLoc();
10439 switch (Op.getOpcode()) {
10440 default: llvm_unreachable("Unknown ovf instruction!");
10442 // A subtract of one will be selected as a INC. Note that INC doesn't
10443 // set CF, so we can't do this for UADDO.
10444 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10446 BaseOp = X86ISD::INC;
10447 Cond = X86::COND_O;
10450 BaseOp = X86ISD::ADD;
10451 Cond = X86::COND_O;
10454 BaseOp = X86ISD::ADD;
10455 Cond = X86::COND_B;
10458 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10459 // set CF, so we can't do this for USUBO.
10460 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10462 BaseOp = X86ISD::DEC;
10463 Cond = X86::COND_O;
10466 BaseOp = X86ISD::SUB;
10467 Cond = X86::COND_O;
10470 BaseOp = X86ISD::SUB;
10471 Cond = X86::COND_B;
10474 BaseOp = X86ISD::SMUL;
10475 Cond = X86::COND_O;
10477 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10478 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10480 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10483 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10484 DAG.getConstant(X86::COND_O, MVT::i32),
10485 SDValue(Sum.getNode(), 2));
10487 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10491 // Also sets EFLAGS.
10492 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10493 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10496 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10497 DAG.getConstant(Cond, MVT::i32),
10498 SDValue(Sum.getNode(), 1));
10500 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10503 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10504 SelectionDAG &DAG) const {
10505 DebugLoc dl = Op.getDebugLoc();
10506 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10507 EVT VT = Op.getValueType();
10509 if (!Subtarget->hasSSE2() || !VT.isVector())
10512 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10513 ExtraVT.getScalarType().getSizeInBits();
10514 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10516 switch (VT.getSimpleVT().SimpleTy) {
10517 default: return SDValue();
10520 if (!Subtarget->hasAVX())
10522 if (!Subtarget->hasAVX2()) {
10523 // needs to be split
10524 int NumElems = VT.getVectorNumElements();
10525 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10526 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10528 // Extract the LHS vectors
10529 SDValue LHS = Op.getOperand(0);
10530 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10531 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10533 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10534 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10536 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10537 int ExtraNumElems = ExtraVT.getVectorNumElements();
10538 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10540 SDValue Extra = DAG.getValueType(ExtraVT);
10542 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10543 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10545 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10550 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10551 Op.getOperand(0), ShAmt, DAG);
10552 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10558 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10559 DebugLoc dl = Op.getDebugLoc();
10561 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10562 // There isn't any reason to disable it if the target processor supports it.
10563 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10564 SDValue Chain = Op.getOperand(0);
10565 SDValue Zero = DAG.getConstant(0, MVT::i32);
10567 DAG.getRegister(X86::ESP, MVT::i32), // Base
10568 DAG.getTargetConstant(1, MVT::i8), // Scale
10569 DAG.getRegister(0, MVT::i32), // Index
10570 DAG.getTargetConstant(0, MVT::i32), // Disp
10571 DAG.getRegister(0, MVT::i32), // Segment.
10576 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10577 array_lengthof(Ops));
10578 return SDValue(Res, 0);
10581 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10583 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10585 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10586 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10587 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10588 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10590 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10591 if (!Op1 && !Op2 && !Op3 && Op4)
10592 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10594 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10595 if (Op1 && !Op2 && !Op3 && !Op4)
10596 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10598 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10600 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10603 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10604 SelectionDAG &DAG) const {
10605 DebugLoc dl = Op.getDebugLoc();
10606 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10607 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10608 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10609 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10611 // The only fence that needs an instruction is a sequentially-consistent
10612 // cross-thread fence.
10613 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10614 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10615 // no-sse2). There isn't any reason to disable it if the target processor
10617 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10618 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10620 SDValue Chain = Op.getOperand(0);
10621 SDValue Zero = DAG.getConstant(0, MVT::i32);
10623 DAG.getRegister(X86::ESP, MVT::i32), // Base
10624 DAG.getTargetConstant(1, MVT::i8), // Scale
10625 DAG.getRegister(0, MVT::i32), // Index
10626 DAG.getTargetConstant(0, MVT::i32), // Disp
10627 DAG.getRegister(0, MVT::i32), // Segment.
10632 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10633 array_lengthof(Ops));
10634 return SDValue(Res, 0);
10637 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10638 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10642 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10643 EVT T = Op.getValueType();
10644 DebugLoc DL = Op.getDebugLoc();
10647 switch(T.getSimpleVT().SimpleTy) {
10648 default: llvm_unreachable("Invalid value type!");
10649 case MVT::i8: Reg = X86::AL; size = 1; break;
10650 case MVT::i16: Reg = X86::AX; size = 2; break;
10651 case MVT::i32: Reg = X86::EAX; size = 4; break;
10653 assert(Subtarget->is64Bit() && "Node not type legal!");
10654 Reg = X86::RAX; size = 8;
10657 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10658 Op.getOperand(2), SDValue());
10659 SDValue Ops[] = { cpIn.getValue(0),
10662 DAG.getTargetConstant(size, MVT::i8),
10663 cpIn.getValue(1) };
10664 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10665 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10666 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10669 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10673 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10674 SelectionDAG &DAG) const {
10675 assert(Subtarget->is64Bit() && "Result not type legalized?");
10676 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10677 SDValue TheChain = Op.getOperand(0);
10678 DebugLoc dl = Op.getDebugLoc();
10679 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10680 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10681 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10683 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10684 DAG.getConstant(32, MVT::i8));
10686 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10689 return DAG.getMergeValues(Ops, 2, dl);
10692 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10693 SelectionDAG &DAG) const {
10694 EVT SrcVT = Op.getOperand(0).getValueType();
10695 EVT DstVT = Op.getValueType();
10696 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10697 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10698 assert((DstVT == MVT::i64 ||
10699 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10700 "Unexpected custom BITCAST");
10701 // i64 <=> MMX conversions are Legal.
10702 if (SrcVT==MVT::i64 && DstVT.isVector())
10704 if (DstVT==MVT::i64 && SrcVT.isVector())
10706 // MMX <=> MMX conversions are Legal.
10707 if (SrcVT.isVector() && DstVT.isVector())
10709 // All other conversions need to be expanded.
10713 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10714 SDNode *Node = Op.getNode();
10715 DebugLoc dl = Node->getDebugLoc();
10716 EVT T = Node->getValueType(0);
10717 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10718 DAG.getConstant(0, T), Node->getOperand(2));
10719 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10720 cast<AtomicSDNode>(Node)->getMemoryVT(),
10721 Node->getOperand(0),
10722 Node->getOperand(1), negOp,
10723 cast<AtomicSDNode>(Node)->getSrcValue(),
10724 cast<AtomicSDNode>(Node)->getAlignment(),
10725 cast<AtomicSDNode>(Node)->getOrdering(),
10726 cast<AtomicSDNode>(Node)->getSynchScope());
10729 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10730 SDNode *Node = Op.getNode();
10731 DebugLoc dl = Node->getDebugLoc();
10732 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10734 // Convert seq_cst store -> xchg
10735 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10736 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10737 // (The only way to get a 16-byte store is cmpxchg16b)
10738 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10739 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10740 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10741 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10742 cast<AtomicSDNode>(Node)->getMemoryVT(),
10743 Node->getOperand(0),
10744 Node->getOperand(1), Node->getOperand(2),
10745 cast<AtomicSDNode>(Node)->getMemOperand(),
10746 cast<AtomicSDNode>(Node)->getOrdering(),
10747 cast<AtomicSDNode>(Node)->getSynchScope());
10748 return Swap.getValue(1);
10750 // Other atomic stores have a simple pattern.
10754 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10755 EVT VT = Op.getNode()->getValueType(0);
10757 // Let legalize expand this if it isn't a legal type yet.
10758 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10761 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10764 bool ExtraOp = false;
10765 switch (Op.getOpcode()) {
10766 default: llvm_unreachable("Invalid code");
10767 case ISD::ADDC: Opc = X86ISD::ADD; break;
10768 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10769 case ISD::SUBC: Opc = X86ISD::SUB; break;
10770 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10774 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10776 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10777 Op.getOperand(1), Op.getOperand(2));
10780 /// LowerOperation - Provide custom lowering hooks for some operations.
10782 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10783 switch (Op.getOpcode()) {
10784 default: llvm_unreachable("Should not custom lower this!");
10785 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10786 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10787 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10788 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10789 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10790 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10791 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10792 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10793 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10794 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10795 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10796 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10797 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10798 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10799 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10800 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10801 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10802 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10803 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10804 case ISD::SHL_PARTS:
10805 case ISD::SRA_PARTS:
10806 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10807 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10808 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10809 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10810 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10811 case ISD::FABS: return LowerFABS(Op, DAG);
10812 case ISD::FNEG: return LowerFNEG(Op, DAG);
10813 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10814 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10815 case ISD::SETCC: return LowerSETCC(Op, DAG);
10816 case ISD::SELECT: return LowerSELECT(Op, DAG);
10817 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10818 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10819 case ISD::VASTART: return LowerVASTART(Op, DAG);
10820 case ISD::VAARG: return LowerVAARG(Op, DAG);
10821 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10822 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10823 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10824 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10825 case ISD::FRAME_TO_ARGS_OFFSET:
10826 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10827 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10828 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10829 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10830 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10831 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10832 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10833 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10834 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10835 case ISD::MUL: return LowerMUL(Op, DAG);
10838 case ISD::SHL: return LowerShift(Op, DAG);
10844 case ISD::UMULO: return LowerXALUO(Op, DAG);
10845 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10846 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10850 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10851 case ISD::ADD: return LowerADD(Op, DAG);
10852 case ISD::SUB: return LowerSUB(Op, DAG);
10856 static void ReplaceATOMIC_LOAD(SDNode *Node,
10857 SmallVectorImpl<SDValue> &Results,
10858 SelectionDAG &DAG) {
10859 DebugLoc dl = Node->getDebugLoc();
10860 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10862 // Convert wide load -> cmpxchg8b/cmpxchg16b
10863 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10864 // (The only way to get a 16-byte load is cmpxchg16b)
10865 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10866 SDValue Zero = DAG.getConstant(0, VT);
10867 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10868 Node->getOperand(0),
10869 Node->getOperand(1), Zero, Zero,
10870 cast<AtomicSDNode>(Node)->getMemOperand(),
10871 cast<AtomicSDNode>(Node)->getOrdering(),
10872 cast<AtomicSDNode>(Node)->getSynchScope());
10873 Results.push_back(Swap.getValue(0));
10874 Results.push_back(Swap.getValue(1));
10877 void X86TargetLowering::
10878 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10879 SelectionDAG &DAG, unsigned NewOp) const {
10880 DebugLoc dl = Node->getDebugLoc();
10881 assert (Node->getValueType(0) == MVT::i64 &&
10882 "Only know how to expand i64 atomics");
10884 SDValue Chain = Node->getOperand(0);
10885 SDValue In1 = Node->getOperand(1);
10886 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10887 Node->getOperand(2), DAG.getIntPtrConstant(0));
10888 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10889 Node->getOperand(2), DAG.getIntPtrConstant(1));
10890 SDValue Ops[] = { Chain, In1, In2L, In2H };
10891 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10893 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10894 cast<MemSDNode>(Node)->getMemOperand());
10895 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10896 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10897 Results.push_back(Result.getValue(2));
10900 /// ReplaceNodeResults - Replace a node with an illegal result type
10901 /// with a new node built out of custom code.
10902 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10903 SmallVectorImpl<SDValue>&Results,
10904 SelectionDAG &DAG) const {
10905 DebugLoc dl = N->getDebugLoc();
10906 switch (N->getOpcode()) {
10908 llvm_unreachable("Do not know how to custom type legalize this operation!");
10909 case ISD::SIGN_EXTEND_INREG:
10914 // We don't want to expand or promote these.
10916 case ISD::FP_TO_SINT:
10917 case ISD::FP_TO_UINT: {
10918 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10920 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10923 std::pair<SDValue,SDValue> Vals =
10924 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10925 SDValue FIST = Vals.first, StackSlot = Vals.second;
10926 if (FIST.getNode() != 0) {
10927 EVT VT = N->getValueType(0);
10928 // Return a load from the stack slot.
10929 if (StackSlot.getNode() != 0)
10930 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10931 MachinePointerInfo(),
10932 false, false, false, 0));
10934 Results.push_back(FIST);
10938 case ISD::READCYCLECOUNTER: {
10939 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10940 SDValue TheChain = N->getOperand(0);
10941 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10942 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10944 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10946 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10947 SDValue Ops[] = { eax, edx };
10948 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10949 Results.push_back(edx.getValue(1));
10952 case ISD::ATOMIC_CMP_SWAP: {
10953 EVT T = N->getValueType(0);
10954 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10955 bool Regs64bit = T == MVT::i128;
10956 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10957 SDValue cpInL, cpInH;
10958 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10959 DAG.getConstant(0, HalfT));
10960 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10961 DAG.getConstant(1, HalfT));
10962 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10963 Regs64bit ? X86::RAX : X86::EAX,
10965 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10966 Regs64bit ? X86::RDX : X86::EDX,
10967 cpInH, cpInL.getValue(1));
10968 SDValue swapInL, swapInH;
10969 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10970 DAG.getConstant(0, HalfT));
10971 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10972 DAG.getConstant(1, HalfT));
10973 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10974 Regs64bit ? X86::RBX : X86::EBX,
10975 swapInL, cpInH.getValue(1));
10976 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10977 Regs64bit ? X86::RCX : X86::ECX,
10978 swapInH, swapInL.getValue(1));
10979 SDValue Ops[] = { swapInH.getValue(0),
10981 swapInH.getValue(1) };
10982 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10983 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10984 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10985 X86ISD::LCMPXCHG8_DAG;
10986 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10988 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10989 Regs64bit ? X86::RAX : X86::EAX,
10990 HalfT, Result.getValue(1));
10991 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10992 Regs64bit ? X86::RDX : X86::EDX,
10993 HalfT, cpOutL.getValue(2));
10994 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10995 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10996 Results.push_back(cpOutH.getValue(1));
10999 case ISD::ATOMIC_LOAD_ADD:
11000 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11002 case ISD::ATOMIC_LOAD_AND:
11003 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11005 case ISD::ATOMIC_LOAD_NAND:
11006 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11008 case ISD::ATOMIC_LOAD_OR:
11009 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11011 case ISD::ATOMIC_LOAD_SUB:
11012 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11014 case ISD::ATOMIC_LOAD_XOR:
11015 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11017 case ISD::ATOMIC_SWAP:
11018 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11020 case ISD::ATOMIC_LOAD:
11021 ReplaceATOMIC_LOAD(N, Results, DAG);
11025 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11027 default: return NULL;
11028 case X86ISD::BSF: return "X86ISD::BSF";
11029 case X86ISD::BSR: return "X86ISD::BSR";
11030 case X86ISD::SHLD: return "X86ISD::SHLD";
11031 case X86ISD::SHRD: return "X86ISD::SHRD";
11032 case X86ISD::FAND: return "X86ISD::FAND";
11033 case X86ISD::FOR: return "X86ISD::FOR";
11034 case X86ISD::FXOR: return "X86ISD::FXOR";
11035 case X86ISD::FSRL: return "X86ISD::FSRL";
11036 case X86ISD::FILD: return "X86ISD::FILD";
11037 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11038 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11039 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11040 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11041 case X86ISD::FLD: return "X86ISD::FLD";
11042 case X86ISD::FST: return "X86ISD::FST";
11043 case X86ISD::CALL: return "X86ISD::CALL";
11044 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11045 case X86ISD::BT: return "X86ISD::BT";
11046 case X86ISD::CMP: return "X86ISD::CMP";
11047 case X86ISD::COMI: return "X86ISD::COMI";
11048 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11049 case X86ISD::SETCC: return "X86ISD::SETCC";
11050 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11051 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11052 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11053 case X86ISD::CMOV: return "X86ISD::CMOV";
11054 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11055 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11056 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11057 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11058 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11059 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11060 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11061 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11062 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11063 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11064 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11065 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11066 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11067 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11068 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11069 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11070 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11071 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11072 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11073 case X86ISD::HADD: return "X86ISD::HADD";
11074 case X86ISD::HSUB: return "X86ISD::HSUB";
11075 case X86ISD::FHADD: return "X86ISD::FHADD";
11076 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11077 case X86ISD::FMAX: return "X86ISD::FMAX";
11078 case X86ISD::FMIN: return "X86ISD::FMIN";
11079 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11080 case X86ISD::FRCP: return "X86ISD::FRCP";
11081 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11082 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11083 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11084 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11085 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11086 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11087 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11088 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11089 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11090 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11091 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11092 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11093 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11094 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11095 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11096 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11097 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11098 case X86ISD::VSHL: return "X86ISD::VSHL";
11099 case X86ISD::VSRL: return "X86ISD::VSRL";
11100 case X86ISD::VSRA: return "X86ISD::VSRA";
11101 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11102 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11103 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11104 case X86ISD::CMPP: return "X86ISD::CMPP";
11105 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11106 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11107 case X86ISD::ADD: return "X86ISD::ADD";
11108 case X86ISD::SUB: return "X86ISD::SUB";
11109 case X86ISD::ADC: return "X86ISD::ADC";
11110 case X86ISD::SBB: return "X86ISD::SBB";
11111 case X86ISD::SMUL: return "X86ISD::SMUL";
11112 case X86ISD::UMUL: return "X86ISD::UMUL";
11113 case X86ISD::INC: return "X86ISD::INC";
11114 case X86ISD::DEC: return "X86ISD::DEC";
11115 case X86ISD::OR: return "X86ISD::OR";
11116 case X86ISD::XOR: return "X86ISD::XOR";
11117 case X86ISD::AND: return "X86ISD::AND";
11118 case X86ISD::ANDN: return "X86ISD::ANDN";
11119 case X86ISD::BLSI: return "X86ISD::BLSI";
11120 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11121 case X86ISD::BLSR: return "X86ISD::BLSR";
11122 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11123 case X86ISD::PTEST: return "X86ISD::PTEST";
11124 case X86ISD::TESTP: return "X86ISD::TESTP";
11125 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11126 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11127 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11128 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11129 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11130 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11131 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11132 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11133 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11134 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11135 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11136 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11137 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11138 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11139 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11140 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11141 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11142 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11143 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11144 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11145 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11146 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11147 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11148 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11149 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11150 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11151 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11155 // isLegalAddressingMode - Return true if the addressing mode represented
11156 // by AM is legal for this target, for a load/store of the specified type.
11157 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11159 // X86 supports extremely general addressing modes.
11160 CodeModel::Model M = getTargetMachine().getCodeModel();
11161 Reloc::Model R = getTargetMachine().getRelocationModel();
11163 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11164 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11169 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11171 // If a reference to this global requires an extra load, we can't fold it.
11172 if (isGlobalStubReference(GVFlags))
11175 // If BaseGV requires a register for the PIC base, we cannot also have a
11176 // BaseReg specified.
11177 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11180 // If lower 4G is not available, then we must use rip-relative addressing.
11181 if ((M != CodeModel::Small || R != Reloc::Static) &&
11182 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11186 switch (AM.Scale) {
11192 // These scales always work.
11197 // These scales are formed with basereg+scalereg. Only accept if there is
11202 default: // Other stuff never works.
11210 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11211 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11213 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11214 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11215 if (NumBits1 <= NumBits2)
11220 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11221 if (!VT1.isInteger() || !VT2.isInteger())
11223 unsigned NumBits1 = VT1.getSizeInBits();
11224 unsigned NumBits2 = VT2.getSizeInBits();
11225 if (NumBits1 <= NumBits2)
11230 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11231 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11232 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11235 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11236 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11237 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11240 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11241 // i16 instructions are longer (0x66 prefix) and potentially slower.
11242 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11245 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11246 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11247 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11248 /// are assumed to be legal.
11250 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11252 // Very little shuffling can be done for 64-bit vectors right now.
11253 if (VT.getSizeInBits() == 64)
11256 // FIXME: pshufb, blends, shifts.
11257 return (VT.getVectorNumElements() == 2 ||
11258 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11259 isMOVLMask(M, VT) ||
11260 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11261 isPSHUFDMask(M, VT) ||
11262 isPSHUFHWMask(M, VT) ||
11263 isPSHUFLWMask(M, VT) ||
11264 isPALIGNRMask(M, VT, Subtarget) ||
11265 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11266 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11267 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11268 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11272 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11274 unsigned NumElts = VT.getVectorNumElements();
11275 // FIXME: This collection of masks seems suspect.
11278 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11279 return (isMOVLMask(Mask, VT) ||
11280 isCommutedMOVLMask(Mask, VT, true) ||
11281 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11282 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11287 //===----------------------------------------------------------------------===//
11288 // X86 Scheduler Hooks
11289 //===----------------------------------------------------------------------===//
11291 // private utility function
11292 MachineBasicBlock *
11293 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11294 MachineBasicBlock *MBB,
11301 const TargetRegisterClass *RC,
11302 bool invSrc) const {
11303 // For the atomic bitwise operator, we generate
11306 // ld t1 = [bitinstr.addr]
11307 // op t2 = t1, [bitinstr.val]
11309 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11311 // fallthrough -->nextMBB
11312 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11313 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11314 MachineFunction::iterator MBBIter = MBB;
11317 /// First build the CFG
11318 MachineFunction *F = MBB->getParent();
11319 MachineBasicBlock *thisMBB = MBB;
11320 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11321 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11322 F->insert(MBBIter, newMBB);
11323 F->insert(MBBIter, nextMBB);
11325 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11326 nextMBB->splice(nextMBB->begin(), thisMBB,
11327 llvm::next(MachineBasicBlock::iterator(bInstr)),
11329 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11331 // Update thisMBB to fall through to newMBB
11332 thisMBB->addSuccessor(newMBB);
11334 // newMBB jumps to itself and fall through to nextMBB
11335 newMBB->addSuccessor(nextMBB);
11336 newMBB->addSuccessor(newMBB);
11338 // Insert instructions into newMBB based on incoming instruction
11339 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11340 "unexpected number of operands");
11341 DebugLoc dl = bInstr->getDebugLoc();
11342 MachineOperand& destOper = bInstr->getOperand(0);
11343 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11344 int numArgs = bInstr->getNumOperands() - 1;
11345 for (int i=0; i < numArgs; ++i)
11346 argOpers[i] = &bInstr->getOperand(i+1);
11348 // x86 address has 4 operands: base, index, scale, and displacement
11349 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11350 int valArgIndx = lastAddrIndx + 1;
11352 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11353 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11354 for (int i=0; i <= lastAddrIndx; ++i)
11355 (*MIB).addOperand(*argOpers[i]);
11357 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11359 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11364 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11365 assert((argOpers[valArgIndx]->isReg() ||
11366 argOpers[valArgIndx]->isImm()) &&
11367 "invalid operand");
11368 if (argOpers[valArgIndx]->isReg())
11369 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11371 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11373 (*MIB).addOperand(*argOpers[valArgIndx]);
11375 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11378 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11379 for (int i=0; i <= lastAddrIndx; ++i)
11380 (*MIB).addOperand(*argOpers[i]);
11382 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11383 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11384 bInstr->memoperands_end());
11386 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11387 MIB.addReg(EAXreg);
11390 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11392 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11396 // private utility function: 64 bit atomics on 32 bit host.
11397 MachineBasicBlock *
11398 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11399 MachineBasicBlock *MBB,
11404 bool invSrc) const {
11405 // For the atomic bitwise operator, we generate
11406 // thisMBB (instructions are in pairs, except cmpxchg8b)
11407 // ld t1,t2 = [bitinstr.addr]
11409 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11410 // op t5, t6 <- out1, out2, [bitinstr.val]
11411 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11412 // mov ECX, EBX <- t5, t6
11413 // mov EAX, EDX <- t1, t2
11414 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11415 // mov t3, t4 <- EAX, EDX
11417 // result in out1, out2
11418 // fallthrough -->nextMBB
11420 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11421 const unsigned LoadOpc = X86::MOV32rm;
11422 const unsigned NotOpc = X86::NOT32r;
11423 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11424 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11425 MachineFunction::iterator MBBIter = MBB;
11428 /// First build the CFG
11429 MachineFunction *F = MBB->getParent();
11430 MachineBasicBlock *thisMBB = MBB;
11431 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11432 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11433 F->insert(MBBIter, newMBB);
11434 F->insert(MBBIter, nextMBB);
11436 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11437 nextMBB->splice(nextMBB->begin(), thisMBB,
11438 llvm::next(MachineBasicBlock::iterator(bInstr)),
11440 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11442 // Update thisMBB to fall through to newMBB
11443 thisMBB->addSuccessor(newMBB);
11445 // newMBB jumps to itself and fall through to nextMBB
11446 newMBB->addSuccessor(nextMBB);
11447 newMBB->addSuccessor(newMBB);
11449 DebugLoc dl = bInstr->getDebugLoc();
11450 // Insert instructions into newMBB based on incoming instruction
11451 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11452 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11453 "unexpected number of operands");
11454 MachineOperand& dest1Oper = bInstr->getOperand(0);
11455 MachineOperand& dest2Oper = bInstr->getOperand(1);
11456 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11457 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11458 argOpers[i] = &bInstr->getOperand(i+2);
11460 // We use some of the operands multiple times, so conservatively just
11461 // clear any kill flags that might be present.
11462 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11463 argOpers[i]->setIsKill(false);
11466 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11467 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11469 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11470 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11471 for (int i=0; i <= lastAddrIndx; ++i)
11472 (*MIB).addOperand(*argOpers[i]);
11473 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11474 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11475 // add 4 to displacement.
11476 for (int i=0; i <= lastAddrIndx-2; ++i)
11477 (*MIB).addOperand(*argOpers[i]);
11478 MachineOperand newOp3 = *(argOpers[3]);
11479 if (newOp3.isImm())
11480 newOp3.setImm(newOp3.getImm()+4);
11482 newOp3.setOffset(newOp3.getOffset()+4);
11483 (*MIB).addOperand(newOp3);
11484 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11486 // t3/4 are defined later, at the bottom of the loop
11487 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11488 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11489 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11490 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11491 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11492 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11494 // The subsequent operations should be using the destination registers of
11495 //the PHI instructions.
11497 t1 = F->getRegInfo().createVirtualRegister(RC);
11498 t2 = F->getRegInfo().createVirtualRegister(RC);
11499 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11500 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11502 t1 = dest1Oper.getReg();
11503 t2 = dest2Oper.getReg();
11506 int valArgIndx = lastAddrIndx + 1;
11507 assert((argOpers[valArgIndx]->isReg() ||
11508 argOpers[valArgIndx]->isImm()) &&
11509 "invalid operand");
11510 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11511 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11512 if (argOpers[valArgIndx]->isReg())
11513 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11515 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11516 if (regOpcL != X86::MOV32rr)
11518 (*MIB).addOperand(*argOpers[valArgIndx]);
11519 assert(argOpers[valArgIndx + 1]->isReg() ==
11520 argOpers[valArgIndx]->isReg());
11521 assert(argOpers[valArgIndx + 1]->isImm() ==
11522 argOpers[valArgIndx]->isImm());
11523 if (argOpers[valArgIndx + 1]->isReg())
11524 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11526 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11527 if (regOpcH != X86::MOV32rr)
11529 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11531 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11533 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11536 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11538 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11541 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11542 for (int i=0; i <= lastAddrIndx; ++i)
11543 (*MIB).addOperand(*argOpers[i]);
11545 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11546 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11547 bInstr->memoperands_end());
11549 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11550 MIB.addReg(X86::EAX);
11551 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11552 MIB.addReg(X86::EDX);
11555 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11557 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11561 // private utility function
11562 MachineBasicBlock *
11563 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11564 MachineBasicBlock *MBB,
11565 unsigned cmovOpc) const {
11566 // For the atomic min/max operator, we generate
11569 // ld t1 = [min/max.addr]
11570 // mov t2 = [min/max.val]
11572 // cmov[cond] t2 = t1
11574 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11576 // fallthrough -->nextMBB
11578 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11579 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11580 MachineFunction::iterator MBBIter = MBB;
11583 /// First build the CFG
11584 MachineFunction *F = MBB->getParent();
11585 MachineBasicBlock *thisMBB = MBB;
11586 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11587 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11588 F->insert(MBBIter, newMBB);
11589 F->insert(MBBIter, nextMBB);
11591 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11592 nextMBB->splice(nextMBB->begin(), thisMBB,
11593 llvm::next(MachineBasicBlock::iterator(mInstr)),
11595 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11597 // Update thisMBB to fall through to newMBB
11598 thisMBB->addSuccessor(newMBB);
11600 // newMBB jumps to newMBB and fall through to nextMBB
11601 newMBB->addSuccessor(nextMBB);
11602 newMBB->addSuccessor(newMBB);
11604 DebugLoc dl = mInstr->getDebugLoc();
11605 // Insert instructions into newMBB based on incoming instruction
11606 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11607 "unexpected number of operands");
11608 MachineOperand& destOper = mInstr->getOperand(0);
11609 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11610 int numArgs = mInstr->getNumOperands() - 1;
11611 for (int i=0; i < numArgs; ++i)
11612 argOpers[i] = &mInstr->getOperand(i+1);
11614 // x86 address has 4 operands: base, index, scale, and displacement
11615 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11616 int valArgIndx = lastAddrIndx + 1;
11618 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11619 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11620 for (int i=0; i <= lastAddrIndx; ++i)
11621 (*MIB).addOperand(*argOpers[i]);
11623 // We only support register and immediate values
11624 assert((argOpers[valArgIndx]->isReg() ||
11625 argOpers[valArgIndx]->isImm()) &&
11626 "invalid operand");
11628 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11629 if (argOpers[valArgIndx]->isReg())
11630 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11632 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11633 (*MIB).addOperand(*argOpers[valArgIndx]);
11635 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11638 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11643 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11644 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11648 // Cmp and exchange if none has modified the memory location
11649 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11650 for (int i=0; i <= lastAddrIndx; ++i)
11651 (*MIB).addOperand(*argOpers[i]);
11653 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11654 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11655 mInstr->memoperands_end());
11657 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11658 MIB.addReg(X86::EAX);
11661 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11663 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11667 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11668 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11669 // in the .td file.
11670 MachineBasicBlock *
11671 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11672 unsigned numArgs, bool memArg) const {
11673 assert(Subtarget->hasSSE42() &&
11674 "Target must have SSE4.2 or AVX features enabled");
11676 DebugLoc dl = MI->getDebugLoc();
11677 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11679 if (!Subtarget->hasAVX()) {
11681 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11683 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11686 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11688 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11691 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11692 for (unsigned i = 0; i < numArgs; ++i) {
11693 MachineOperand &Op = MI->getOperand(i+1);
11694 if (!(Op.isReg() && Op.isImplicit()))
11695 MIB.addOperand(Op);
11697 BuildMI(*BB, MI, dl,
11698 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11699 MI->getOperand(0).getReg())
11700 .addReg(X86::XMM0);
11702 MI->eraseFromParent();
11706 MachineBasicBlock *
11707 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11708 DebugLoc dl = MI->getDebugLoc();
11709 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11711 // Address into RAX/EAX, other two args into ECX, EDX.
11712 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11713 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11714 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11715 for (int i = 0; i < X86::AddrNumOperands; ++i)
11716 MIB.addOperand(MI->getOperand(i));
11718 unsigned ValOps = X86::AddrNumOperands;
11719 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11720 .addReg(MI->getOperand(ValOps).getReg());
11721 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11722 .addReg(MI->getOperand(ValOps+1).getReg());
11724 // The instruction doesn't actually take any operands though.
11725 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11727 MI->eraseFromParent(); // The pseudo is gone now.
11731 MachineBasicBlock *
11732 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11733 DebugLoc dl = MI->getDebugLoc();
11734 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11736 // First arg in ECX, the second in EAX.
11737 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11738 .addReg(MI->getOperand(0).getReg());
11739 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11740 .addReg(MI->getOperand(1).getReg());
11742 // The instruction doesn't actually take any operands though.
11743 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11745 MI->eraseFromParent(); // The pseudo is gone now.
11749 MachineBasicBlock *
11750 X86TargetLowering::EmitVAARG64WithCustomInserter(
11752 MachineBasicBlock *MBB) const {
11753 // Emit va_arg instruction on X86-64.
11755 // Operands to this pseudo-instruction:
11756 // 0 ) Output : destination address (reg)
11757 // 1-5) Input : va_list address (addr, i64mem)
11758 // 6 ) ArgSize : Size (in bytes) of vararg type
11759 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11760 // 8 ) Align : Alignment of type
11761 // 9 ) EFLAGS (implicit-def)
11763 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11764 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11766 unsigned DestReg = MI->getOperand(0).getReg();
11767 MachineOperand &Base = MI->getOperand(1);
11768 MachineOperand &Scale = MI->getOperand(2);
11769 MachineOperand &Index = MI->getOperand(3);
11770 MachineOperand &Disp = MI->getOperand(4);
11771 MachineOperand &Segment = MI->getOperand(5);
11772 unsigned ArgSize = MI->getOperand(6).getImm();
11773 unsigned ArgMode = MI->getOperand(7).getImm();
11774 unsigned Align = MI->getOperand(8).getImm();
11776 // Memory Reference
11777 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11778 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11779 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11781 // Machine Information
11782 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11783 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11784 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11785 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11786 DebugLoc DL = MI->getDebugLoc();
11788 // struct va_list {
11791 // i64 overflow_area (address)
11792 // i64 reg_save_area (address)
11794 // sizeof(va_list) = 24
11795 // alignment(va_list) = 8
11797 unsigned TotalNumIntRegs = 6;
11798 unsigned TotalNumXMMRegs = 8;
11799 bool UseGPOffset = (ArgMode == 1);
11800 bool UseFPOffset = (ArgMode == 2);
11801 unsigned MaxOffset = TotalNumIntRegs * 8 +
11802 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11804 /* Align ArgSize to a multiple of 8 */
11805 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11806 bool NeedsAlign = (Align > 8);
11808 MachineBasicBlock *thisMBB = MBB;
11809 MachineBasicBlock *overflowMBB;
11810 MachineBasicBlock *offsetMBB;
11811 MachineBasicBlock *endMBB;
11813 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11814 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11815 unsigned OffsetReg = 0;
11817 if (!UseGPOffset && !UseFPOffset) {
11818 // If we only pull from the overflow region, we don't create a branch.
11819 // We don't need to alter control flow.
11820 OffsetDestReg = 0; // unused
11821 OverflowDestReg = DestReg;
11824 overflowMBB = thisMBB;
11827 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11828 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11829 // If not, pull from overflow_area. (branch to overflowMBB)
11834 // offsetMBB overflowMBB
11839 // Registers for the PHI in endMBB
11840 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11841 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11843 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11844 MachineFunction *MF = MBB->getParent();
11845 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11846 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11847 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11849 MachineFunction::iterator MBBIter = MBB;
11852 // Insert the new basic blocks
11853 MF->insert(MBBIter, offsetMBB);
11854 MF->insert(MBBIter, overflowMBB);
11855 MF->insert(MBBIter, endMBB);
11857 // Transfer the remainder of MBB and its successor edges to endMBB.
11858 endMBB->splice(endMBB->begin(), thisMBB,
11859 llvm::next(MachineBasicBlock::iterator(MI)),
11861 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11863 // Make offsetMBB and overflowMBB successors of thisMBB
11864 thisMBB->addSuccessor(offsetMBB);
11865 thisMBB->addSuccessor(overflowMBB);
11867 // endMBB is a successor of both offsetMBB and overflowMBB
11868 offsetMBB->addSuccessor(endMBB);
11869 overflowMBB->addSuccessor(endMBB);
11871 // Load the offset value into a register
11872 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11873 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11877 .addDisp(Disp, UseFPOffset ? 4 : 0)
11878 .addOperand(Segment)
11879 .setMemRefs(MMOBegin, MMOEnd);
11881 // Check if there is enough room left to pull this argument.
11882 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11884 .addImm(MaxOffset + 8 - ArgSizeA8);
11886 // Branch to "overflowMBB" if offset >= max
11887 // Fall through to "offsetMBB" otherwise
11888 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11889 .addMBB(overflowMBB);
11892 // In offsetMBB, emit code to use the reg_save_area.
11894 assert(OffsetReg != 0);
11896 // Read the reg_save_area address.
11897 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11898 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11903 .addOperand(Segment)
11904 .setMemRefs(MMOBegin, MMOEnd);
11906 // Zero-extend the offset
11907 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11908 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11911 .addImm(X86::sub_32bit);
11913 // Add the offset to the reg_save_area to get the final address.
11914 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11915 .addReg(OffsetReg64)
11916 .addReg(RegSaveReg);
11918 // Compute the offset for the next argument
11919 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11920 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11922 .addImm(UseFPOffset ? 16 : 8);
11924 // Store it back into the va_list.
11925 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11929 .addDisp(Disp, UseFPOffset ? 4 : 0)
11930 .addOperand(Segment)
11931 .addReg(NextOffsetReg)
11932 .setMemRefs(MMOBegin, MMOEnd);
11935 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11940 // Emit code to use overflow area
11943 // Load the overflow_area address into a register.
11944 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11945 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11950 .addOperand(Segment)
11951 .setMemRefs(MMOBegin, MMOEnd);
11953 // If we need to align it, do so. Otherwise, just copy the address
11954 // to OverflowDestReg.
11956 // Align the overflow address
11957 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11958 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11960 // aligned_addr = (addr + (align-1)) & ~(align-1)
11961 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11962 .addReg(OverflowAddrReg)
11965 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11967 .addImm(~(uint64_t)(Align-1));
11969 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11970 .addReg(OverflowAddrReg);
11973 // Compute the next overflow address after this argument.
11974 // (the overflow address should be kept 8-byte aligned)
11975 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11976 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11977 .addReg(OverflowDestReg)
11978 .addImm(ArgSizeA8);
11980 // Store the new overflow address.
11981 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11986 .addOperand(Segment)
11987 .addReg(NextAddrReg)
11988 .setMemRefs(MMOBegin, MMOEnd);
11990 // If we branched, emit the PHI to the front of endMBB.
11992 BuildMI(*endMBB, endMBB->begin(), DL,
11993 TII->get(X86::PHI), DestReg)
11994 .addReg(OffsetDestReg).addMBB(offsetMBB)
11995 .addReg(OverflowDestReg).addMBB(overflowMBB);
11998 // Erase the pseudo instruction
11999 MI->eraseFromParent();
12004 MachineBasicBlock *
12005 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12007 MachineBasicBlock *MBB) const {
12008 // Emit code to save XMM registers to the stack. The ABI says that the
12009 // number of registers to save is given in %al, so it's theoretically
12010 // possible to do an indirect jump trick to avoid saving all of them,
12011 // however this code takes a simpler approach and just executes all
12012 // of the stores if %al is non-zero. It's less code, and it's probably
12013 // easier on the hardware branch predictor, and stores aren't all that
12014 // expensive anyway.
12016 // Create the new basic blocks. One block contains all the XMM stores,
12017 // and one block is the final destination regardless of whether any
12018 // stores were performed.
12019 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12020 MachineFunction *F = MBB->getParent();
12021 MachineFunction::iterator MBBIter = MBB;
12023 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12024 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12025 F->insert(MBBIter, XMMSaveMBB);
12026 F->insert(MBBIter, EndMBB);
12028 // Transfer the remainder of MBB and its successor edges to EndMBB.
12029 EndMBB->splice(EndMBB->begin(), MBB,
12030 llvm::next(MachineBasicBlock::iterator(MI)),
12032 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12034 // The original block will now fall through to the XMM save block.
12035 MBB->addSuccessor(XMMSaveMBB);
12036 // The XMMSaveMBB will fall through to the end block.
12037 XMMSaveMBB->addSuccessor(EndMBB);
12039 // Now add the instructions.
12040 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12041 DebugLoc DL = MI->getDebugLoc();
12043 unsigned CountReg = MI->getOperand(0).getReg();
12044 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12045 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12047 if (!Subtarget->isTargetWin64()) {
12048 // If %al is 0, branch around the XMM save block.
12049 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12050 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12051 MBB->addSuccessor(EndMBB);
12054 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12055 // In the XMM save block, save all the XMM argument registers.
12056 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12057 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12058 MachineMemOperand *MMO =
12059 F->getMachineMemOperand(
12060 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12061 MachineMemOperand::MOStore,
12062 /*Size=*/16, /*Align=*/16);
12063 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12064 .addFrameIndex(RegSaveFrameIndex)
12065 .addImm(/*Scale=*/1)
12066 .addReg(/*IndexReg=*/0)
12067 .addImm(/*Disp=*/Offset)
12068 .addReg(/*Segment=*/0)
12069 .addReg(MI->getOperand(i).getReg())
12070 .addMemOperand(MMO);
12073 MI->eraseFromParent(); // The pseudo instruction is gone now.
12078 // The EFLAGS operand of SelectItr might be missing a kill marker
12079 // because there were multiple uses of EFLAGS, and ISel didn't know
12080 // which to mark. Figure out whether SelectItr should have had a
12081 // kill marker, and set it if it should. Returns the correct kill
12083 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12084 MachineBasicBlock* BB,
12085 const TargetRegisterInfo* TRI) {
12086 // Scan forward through BB for a use/def of EFLAGS.
12087 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12088 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12089 const MachineInstr& mi = *miI;
12090 if (mi.readsRegister(X86::EFLAGS))
12092 if (mi.definesRegister(X86::EFLAGS))
12093 break; // Should have kill-flag - update below.
12096 // If we hit the end of the block, check whether EFLAGS is live into a
12098 if (miI == BB->end()) {
12099 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12100 sEnd = BB->succ_end();
12101 sItr != sEnd; ++sItr) {
12102 MachineBasicBlock* succ = *sItr;
12103 if (succ->isLiveIn(X86::EFLAGS))
12108 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12109 // out. SelectMI should have a kill flag on EFLAGS.
12110 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12114 MachineBasicBlock *
12115 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12116 MachineBasicBlock *BB) const {
12117 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12118 DebugLoc DL = MI->getDebugLoc();
12120 // To "insert" a SELECT_CC instruction, we actually have to insert the
12121 // diamond control-flow pattern. The incoming instruction knows the
12122 // destination vreg to set, the condition code register to branch on, the
12123 // true/false values to select between, and a branch opcode to use.
12124 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12125 MachineFunction::iterator It = BB;
12131 // cmpTY ccX, r1, r2
12133 // fallthrough --> copy0MBB
12134 MachineBasicBlock *thisMBB = BB;
12135 MachineFunction *F = BB->getParent();
12136 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12137 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12138 F->insert(It, copy0MBB);
12139 F->insert(It, sinkMBB);
12141 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12142 // live into the sink and copy blocks.
12143 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12144 if (!MI->killsRegister(X86::EFLAGS) &&
12145 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12146 copy0MBB->addLiveIn(X86::EFLAGS);
12147 sinkMBB->addLiveIn(X86::EFLAGS);
12150 // Transfer the remainder of BB and its successor edges to sinkMBB.
12151 sinkMBB->splice(sinkMBB->begin(), BB,
12152 llvm::next(MachineBasicBlock::iterator(MI)),
12154 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12156 // Add the true and fallthrough blocks as its successors.
12157 BB->addSuccessor(copy0MBB);
12158 BB->addSuccessor(sinkMBB);
12160 // Create the conditional branch instruction.
12162 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12163 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12166 // %FalseValue = ...
12167 // # fallthrough to sinkMBB
12168 copy0MBB->addSuccessor(sinkMBB);
12171 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12173 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12174 TII->get(X86::PHI), MI->getOperand(0).getReg())
12175 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12176 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12178 MI->eraseFromParent(); // The pseudo instruction is gone now.
12182 MachineBasicBlock *
12183 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12184 bool Is64Bit) const {
12185 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12186 DebugLoc DL = MI->getDebugLoc();
12187 MachineFunction *MF = BB->getParent();
12188 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12190 assert(getTargetMachine().Options.EnableSegmentedStacks);
12192 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12193 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12196 // ... [Till the alloca]
12197 // If stacklet is not large enough, jump to mallocMBB
12200 // Allocate by subtracting from RSP
12201 // Jump to continueMBB
12204 // Allocate by call to runtime
12208 // [rest of original BB]
12211 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12212 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12213 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12215 MachineRegisterInfo &MRI = MF->getRegInfo();
12216 const TargetRegisterClass *AddrRegClass =
12217 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12219 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12220 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12221 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12222 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12223 sizeVReg = MI->getOperand(1).getReg(),
12224 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12226 MachineFunction::iterator MBBIter = BB;
12229 MF->insert(MBBIter, bumpMBB);
12230 MF->insert(MBBIter, mallocMBB);
12231 MF->insert(MBBIter, continueMBB);
12233 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12234 (MachineBasicBlock::iterator(MI)), BB->end());
12235 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12237 // Add code to the main basic block to check if the stack limit has been hit,
12238 // and if so, jump to mallocMBB otherwise to bumpMBB.
12239 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12240 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12241 .addReg(tmpSPVReg).addReg(sizeVReg);
12242 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12243 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12244 .addReg(SPLimitVReg);
12245 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12247 // bumpMBB simply decreases the stack pointer, since we know the current
12248 // stacklet has enough space.
12249 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12250 .addReg(SPLimitVReg);
12251 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12252 .addReg(SPLimitVReg);
12253 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12255 // Calls into a routine in libgcc to allocate more space from the heap.
12256 const uint32_t *RegMask =
12257 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12259 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12261 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12262 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12263 .addRegMask(RegMask)
12264 .addReg(X86::RAX, RegState::ImplicitDefine);
12266 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12268 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12269 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12270 .addExternalSymbol("__morestack_allocate_stack_space")
12271 .addRegMask(RegMask)
12272 .addReg(X86::EAX, RegState::ImplicitDefine);
12276 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12279 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12280 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12281 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12283 // Set up the CFG correctly.
12284 BB->addSuccessor(bumpMBB);
12285 BB->addSuccessor(mallocMBB);
12286 mallocMBB->addSuccessor(continueMBB);
12287 bumpMBB->addSuccessor(continueMBB);
12289 // Take care of the PHI nodes.
12290 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12291 MI->getOperand(0).getReg())
12292 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12293 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12295 // Delete the original pseudo instruction.
12296 MI->eraseFromParent();
12299 return continueMBB;
12302 MachineBasicBlock *
12303 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12304 MachineBasicBlock *BB) const {
12305 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12306 DebugLoc DL = MI->getDebugLoc();
12308 assert(!Subtarget->isTargetEnvMacho());
12310 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12311 // non-trivial part is impdef of ESP.
12313 if (Subtarget->isTargetWin64()) {
12314 if (Subtarget->isTargetCygMing()) {
12315 // ___chkstk(Mingw64):
12316 // Clobbers R10, R11, RAX and EFLAGS.
12318 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12319 .addExternalSymbol("___chkstk")
12320 .addReg(X86::RAX, RegState::Implicit)
12321 .addReg(X86::RSP, RegState::Implicit)
12322 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12323 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12324 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12326 // __chkstk(MSVCRT): does not update stack pointer.
12327 // Clobbers R10, R11 and EFLAGS.
12328 // FIXME: RAX(allocated size) might be reused and not killed.
12329 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12330 .addExternalSymbol("__chkstk")
12331 .addReg(X86::RAX, RegState::Implicit)
12332 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12333 // RAX has the offset to subtracted from RSP.
12334 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12339 const char *StackProbeSymbol =
12340 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12342 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12343 .addExternalSymbol(StackProbeSymbol)
12344 .addReg(X86::EAX, RegState::Implicit)
12345 .addReg(X86::ESP, RegState::Implicit)
12346 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12347 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12348 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12351 MI->eraseFromParent(); // The pseudo instruction is gone now.
12355 MachineBasicBlock *
12356 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12357 MachineBasicBlock *BB) const {
12358 // This is pretty easy. We're taking the value that we received from
12359 // our load from the relocation, sticking it in either RDI (x86-64)
12360 // or EAX and doing an indirect call. The return value will then
12361 // be in the normal return register.
12362 const X86InstrInfo *TII
12363 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12364 DebugLoc DL = MI->getDebugLoc();
12365 MachineFunction *F = BB->getParent();
12367 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12368 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12370 // Get a register mask for the lowered call.
12371 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12372 // proper register mask.
12373 const uint32_t *RegMask =
12374 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12375 if (Subtarget->is64Bit()) {
12376 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12377 TII->get(X86::MOV64rm), X86::RDI)
12379 .addImm(0).addReg(0)
12380 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12381 MI->getOperand(3).getTargetFlags())
12383 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12384 addDirectMem(MIB, X86::RDI);
12385 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12386 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12387 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12388 TII->get(X86::MOV32rm), X86::EAX)
12390 .addImm(0).addReg(0)
12391 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12392 MI->getOperand(3).getTargetFlags())
12394 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12395 addDirectMem(MIB, X86::EAX);
12396 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12398 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12399 TII->get(X86::MOV32rm), X86::EAX)
12400 .addReg(TII->getGlobalBaseReg(F))
12401 .addImm(0).addReg(0)
12402 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12403 MI->getOperand(3).getTargetFlags())
12405 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12406 addDirectMem(MIB, X86::EAX);
12407 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12410 MI->eraseFromParent(); // The pseudo instruction is gone now.
12414 MachineBasicBlock *
12415 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12416 MachineBasicBlock *BB) const {
12417 switch (MI->getOpcode()) {
12418 default: llvm_unreachable("Unexpected instr type to insert");
12419 case X86::TAILJMPd64:
12420 case X86::TAILJMPr64:
12421 case X86::TAILJMPm64:
12422 llvm_unreachable("TAILJMP64 would not be touched here.");
12423 case X86::TCRETURNdi64:
12424 case X86::TCRETURNri64:
12425 case X86::TCRETURNmi64:
12427 case X86::WIN_ALLOCA:
12428 return EmitLoweredWinAlloca(MI, BB);
12429 case X86::SEG_ALLOCA_32:
12430 return EmitLoweredSegAlloca(MI, BB, false);
12431 case X86::SEG_ALLOCA_64:
12432 return EmitLoweredSegAlloca(MI, BB, true);
12433 case X86::TLSCall_32:
12434 case X86::TLSCall_64:
12435 return EmitLoweredTLSCall(MI, BB);
12436 case X86::CMOV_GR8:
12437 case X86::CMOV_FR32:
12438 case X86::CMOV_FR64:
12439 case X86::CMOV_V4F32:
12440 case X86::CMOV_V2F64:
12441 case X86::CMOV_V2I64:
12442 case X86::CMOV_V8F32:
12443 case X86::CMOV_V4F64:
12444 case X86::CMOV_V4I64:
12445 case X86::CMOV_GR16:
12446 case X86::CMOV_GR32:
12447 case X86::CMOV_RFP32:
12448 case X86::CMOV_RFP64:
12449 case X86::CMOV_RFP80:
12450 return EmitLoweredSelect(MI, BB);
12452 case X86::FP32_TO_INT16_IN_MEM:
12453 case X86::FP32_TO_INT32_IN_MEM:
12454 case X86::FP32_TO_INT64_IN_MEM:
12455 case X86::FP64_TO_INT16_IN_MEM:
12456 case X86::FP64_TO_INT32_IN_MEM:
12457 case X86::FP64_TO_INT64_IN_MEM:
12458 case X86::FP80_TO_INT16_IN_MEM:
12459 case X86::FP80_TO_INT32_IN_MEM:
12460 case X86::FP80_TO_INT64_IN_MEM: {
12461 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12462 DebugLoc DL = MI->getDebugLoc();
12464 // Change the floating point control register to use "round towards zero"
12465 // mode when truncating to an integer value.
12466 MachineFunction *F = BB->getParent();
12467 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12468 addFrameReference(BuildMI(*BB, MI, DL,
12469 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12471 // Load the old value of the high byte of the control word...
12473 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12474 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12477 // Set the high part to be round to zero...
12478 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12481 // Reload the modified control word now...
12482 addFrameReference(BuildMI(*BB, MI, DL,
12483 TII->get(X86::FLDCW16m)), CWFrameIdx);
12485 // Restore the memory image of control word to original value
12486 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12489 // Get the X86 opcode to use.
12491 switch (MI->getOpcode()) {
12492 default: llvm_unreachable("illegal opcode!");
12493 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12494 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12495 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12496 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12497 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12498 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12499 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12500 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12501 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12505 MachineOperand &Op = MI->getOperand(0);
12507 AM.BaseType = X86AddressMode::RegBase;
12508 AM.Base.Reg = Op.getReg();
12510 AM.BaseType = X86AddressMode::FrameIndexBase;
12511 AM.Base.FrameIndex = Op.getIndex();
12513 Op = MI->getOperand(1);
12515 AM.Scale = Op.getImm();
12516 Op = MI->getOperand(2);
12518 AM.IndexReg = Op.getImm();
12519 Op = MI->getOperand(3);
12520 if (Op.isGlobal()) {
12521 AM.GV = Op.getGlobal();
12523 AM.Disp = Op.getImm();
12525 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12526 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12528 // Reload the original control word now.
12529 addFrameReference(BuildMI(*BB, MI, DL,
12530 TII->get(X86::FLDCW16m)), CWFrameIdx);
12532 MI->eraseFromParent(); // The pseudo instruction is gone now.
12535 // String/text processing lowering.
12536 case X86::PCMPISTRM128REG:
12537 case X86::VPCMPISTRM128REG:
12538 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12539 case X86::PCMPISTRM128MEM:
12540 case X86::VPCMPISTRM128MEM:
12541 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12542 case X86::PCMPESTRM128REG:
12543 case X86::VPCMPESTRM128REG:
12544 return EmitPCMP(MI, BB, 5, false /* in mem */);
12545 case X86::PCMPESTRM128MEM:
12546 case X86::VPCMPESTRM128MEM:
12547 return EmitPCMP(MI, BB, 5, true /* in mem */);
12549 // Thread synchronization.
12551 return EmitMonitor(MI, BB);
12553 return EmitMwait(MI, BB);
12555 // Atomic Lowering.
12556 case X86::ATOMAND32:
12557 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12558 X86::AND32ri, X86::MOV32rm,
12560 X86::NOT32r, X86::EAX,
12561 X86::GR32RegisterClass);
12562 case X86::ATOMOR32:
12563 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12564 X86::OR32ri, X86::MOV32rm,
12566 X86::NOT32r, X86::EAX,
12567 X86::GR32RegisterClass);
12568 case X86::ATOMXOR32:
12569 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12570 X86::XOR32ri, X86::MOV32rm,
12572 X86::NOT32r, X86::EAX,
12573 X86::GR32RegisterClass);
12574 case X86::ATOMNAND32:
12575 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12576 X86::AND32ri, X86::MOV32rm,
12578 X86::NOT32r, X86::EAX,
12579 X86::GR32RegisterClass, true);
12580 case X86::ATOMMIN32:
12581 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12582 case X86::ATOMMAX32:
12583 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12584 case X86::ATOMUMIN32:
12585 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12586 case X86::ATOMUMAX32:
12587 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12589 case X86::ATOMAND16:
12590 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12591 X86::AND16ri, X86::MOV16rm,
12593 X86::NOT16r, X86::AX,
12594 X86::GR16RegisterClass);
12595 case X86::ATOMOR16:
12596 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12597 X86::OR16ri, X86::MOV16rm,
12599 X86::NOT16r, X86::AX,
12600 X86::GR16RegisterClass);
12601 case X86::ATOMXOR16:
12602 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12603 X86::XOR16ri, X86::MOV16rm,
12605 X86::NOT16r, X86::AX,
12606 X86::GR16RegisterClass);
12607 case X86::ATOMNAND16:
12608 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12609 X86::AND16ri, X86::MOV16rm,
12611 X86::NOT16r, X86::AX,
12612 X86::GR16RegisterClass, true);
12613 case X86::ATOMMIN16:
12614 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12615 case X86::ATOMMAX16:
12616 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12617 case X86::ATOMUMIN16:
12618 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12619 case X86::ATOMUMAX16:
12620 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12622 case X86::ATOMAND8:
12623 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12624 X86::AND8ri, X86::MOV8rm,
12626 X86::NOT8r, X86::AL,
12627 X86::GR8RegisterClass);
12629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12630 X86::OR8ri, X86::MOV8rm,
12632 X86::NOT8r, X86::AL,
12633 X86::GR8RegisterClass);
12634 case X86::ATOMXOR8:
12635 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12636 X86::XOR8ri, X86::MOV8rm,
12638 X86::NOT8r, X86::AL,
12639 X86::GR8RegisterClass);
12640 case X86::ATOMNAND8:
12641 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12642 X86::AND8ri, X86::MOV8rm,
12644 X86::NOT8r, X86::AL,
12645 X86::GR8RegisterClass, true);
12646 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12647 // This group is for 64-bit host.
12648 case X86::ATOMAND64:
12649 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12650 X86::AND64ri32, X86::MOV64rm,
12652 X86::NOT64r, X86::RAX,
12653 X86::GR64RegisterClass);
12654 case X86::ATOMOR64:
12655 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12656 X86::OR64ri32, X86::MOV64rm,
12658 X86::NOT64r, X86::RAX,
12659 X86::GR64RegisterClass);
12660 case X86::ATOMXOR64:
12661 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12662 X86::XOR64ri32, X86::MOV64rm,
12664 X86::NOT64r, X86::RAX,
12665 X86::GR64RegisterClass);
12666 case X86::ATOMNAND64:
12667 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12668 X86::AND64ri32, X86::MOV64rm,
12670 X86::NOT64r, X86::RAX,
12671 X86::GR64RegisterClass, true);
12672 case X86::ATOMMIN64:
12673 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12674 case X86::ATOMMAX64:
12675 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12676 case X86::ATOMUMIN64:
12677 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12678 case X86::ATOMUMAX64:
12679 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12681 // This group does 64-bit operations on a 32-bit host.
12682 case X86::ATOMAND6432:
12683 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12684 X86::AND32rr, X86::AND32rr,
12685 X86::AND32ri, X86::AND32ri,
12687 case X86::ATOMOR6432:
12688 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12689 X86::OR32rr, X86::OR32rr,
12690 X86::OR32ri, X86::OR32ri,
12692 case X86::ATOMXOR6432:
12693 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12694 X86::XOR32rr, X86::XOR32rr,
12695 X86::XOR32ri, X86::XOR32ri,
12697 case X86::ATOMNAND6432:
12698 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12699 X86::AND32rr, X86::AND32rr,
12700 X86::AND32ri, X86::AND32ri,
12702 case X86::ATOMADD6432:
12703 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12704 X86::ADD32rr, X86::ADC32rr,
12705 X86::ADD32ri, X86::ADC32ri,
12707 case X86::ATOMSUB6432:
12708 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12709 X86::SUB32rr, X86::SBB32rr,
12710 X86::SUB32ri, X86::SBB32ri,
12712 case X86::ATOMSWAP6432:
12713 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12714 X86::MOV32rr, X86::MOV32rr,
12715 X86::MOV32ri, X86::MOV32ri,
12717 case X86::VASTART_SAVE_XMM_REGS:
12718 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12720 case X86::VAARG_64:
12721 return EmitVAARG64WithCustomInserter(MI, BB);
12725 //===----------------------------------------------------------------------===//
12726 // X86 Optimization Hooks
12727 //===----------------------------------------------------------------------===//
12729 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12732 const SelectionDAG &DAG,
12733 unsigned Depth) const {
12734 unsigned BitWidth = KnownZero.getBitWidth();
12735 unsigned Opc = Op.getOpcode();
12736 assert((Opc >= ISD::BUILTIN_OP_END ||
12737 Opc == ISD::INTRINSIC_WO_CHAIN ||
12738 Opc == ISD::INTRINSIC_W_CHAIN ||
12739 Opc == ISD::INTRINSIC_VOID) &&
12740 "Should use MaskedValueIsZero if you don't know whether Op"
12741 " is a target node!");
12743 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12757 // These nodes' second result is a boolean.
12758 if (Op.getResNo() == 0)
12761 case X86ISD::SETCC:
12762 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12764 case ISD::INTRINSIC_WO_CHAIN: {
12765 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12766 unsigned NumLoBits = 0;
12769 case Intrinsic::x86_sse_movmsk_ps:
12770 case Intrinsic::x86_avx_movmsk_ps_256:
12771 case Intrinsic::x86_sse2_movmsk_pd:
12772 case Intrinsic::x86_avx_movmsk_pd_256:
12773 case Intrinsic::x86_mmx_pmovmskb:
12774 case Intrinsic::x86_sse2_pmovmskb_128:
12775 case Intrinsic::x86_avx2_pmovmskb: {
12776 // High bits of movmskp{s|d}, pmovmskb are known zero.
12778 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12779 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12780 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12781 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12782 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12783 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12784 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12785 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12787 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12796 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12797 unsigned Depth) const {
12798 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12799 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12800 return Op.getValueType().getScalarType().getSizeInBits();
12806 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12807 /// node is a GlobalAddress + offset.
12808 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12809 const GlobalValue* &GA,
12810 int64_t &Offset) const {
12811 if (N->getOpcode() == X86ISD::Wrapper) {
12812 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12813 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12814 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12818 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12821 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12822 /// same as extracting the high 128-bit part of 256-bit vector and then
12823 /// inserting the result into the low part of a new 256-bit vector
12824 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12825 EVT VT = SVOp->getValueType(0);
12826 int NumElems = VT.getVectorNumElements();
12828 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12829 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12830 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12831 SVOp->getMaskElt(j) >= 0)
12837 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12838 /// same as extracting the low 128-bit part of 256-bit vector and then
12839 /// inserting the result into the high part of a new 256-bit vector
12840 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12841 EVT VT = SVOp->getValueType(0);
12842 int NumElems = VT.getVectorNumElements();
12844 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12845 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12846 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12847 SVOp->getMaskElt(j) >= 0)
12853 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12854 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12855 TargetLowering::DAGCombinerInfo &DCI,
12856 const X86Subtarget* Subtarget) {
12857 DebugLoc dl = N->getDebugLoc();
12858 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12859 SDValue V1 = SVOp->getOperand(0);
12860 SDValue V2 = SVOp->getOperand(1);
12861 EVT VT = SVOp->getValueType(0);
12862 int NumElems = VT.getVectorNumElements();
12864 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12865 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12869 // V UNDEF BUILD_VECTOR UNDEF
12871 // CONCAT_VECTOR CONCAT_VECTOR
12874 // RESULT: V + zero extended
12876 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12877 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12878 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12881 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12884 // To match the shuffle mask, the first half of the mask should
12885 // be exactly the first vector, and all the rest a splat with the
12886 // first element of the second one.
12887 for (int i = 0; i < NumElems/2; ++i)
12888 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12889 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12892 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12893 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12894 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12895 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12897 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12899 Ld->getPointerInfo(),
12900 Ld->getAlignment(),
12901 false/*isVolatile*/, true/*ReadMem*/,
12902 false/*WriteMem*/);
12903 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12906 // Emit a zeroed vector and insert the desired subvector on its
12908 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12909 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12910 DAG.getConstant(0, MVT::i32), DAG, dl);
12911 return DCI.CombineTo(N, InsV);
12914 //===--------------------------------------------------------------------===//
12915 // Combine some shuffles into subvector extracts and inserts:
12918 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12919 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12920 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12922 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12923 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12924 return DCI.CombineTo(N, InsV);
12927 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12928 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12929 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12930 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12931 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12932 return DCI.CombineTo(N, InsV);
12938 /// PerformShuffleCombine - Performs several different shuffle combines.
12939 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12940 TargetLowering::DAGCombinerInfo &DCI,
12941 const X86Subtarget *Subtarget) {
12942 DebugLoc dl = N->getDebugLoc();
12943 EVT VT = N->getValueType(0);
12945 // Don't create instructions with illegal types after legalize types has run.
12946 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12947 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12950 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12951 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12952 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12953 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
12955 // Only handle 128 wide vector from here on.
12956 if (VT.getSizeInBits() != 128)
12959 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12960 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12961 // consecutive, non-overlapping, and in the right order.
12962 SmallVector<SDValue, 16> Elts;
12963 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12964 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12966 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12970 /// PerformTruncateCombine - Converts truncate operation to
12971 /// a sequence of vector shuffle operations.
12972 /// It is possible when we truncate 256-bit vector to 128-bit vector
12974 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
12975 DAGCombinerInfo &DCI) const {
12976 if (!DCI.isBeforeLegalizeOps())
12979 if (!Subtarget->hasAVX()) return SDValue();
12981 EVT VT = N->getValueType(0);
12982 SDValue Op = N->getOperand(0);
12983 EVT OpVT = Op.getValueType();
12984 DebugLoc dl = N->getDebugLoc();
12986 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
12988 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12989 DAG.getIntPtrConstant(0));
12991 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12992 DAG.getIntPtrConstant(2));
12994 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12995 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12998 int ShufMask1[] = {0, 2, 0, 0};
13000 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
13002 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
13006 int ShufMask2[] = {0, 1, 4, 5};
13008 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13010 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13012 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13013 DAG.getIntPtrConstant(0));
13015 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13016 DAG.getIntPtrConstant(4));
13018 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13019 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13022 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13023 -1, -1, -1, -1, -1, -1, -1, -1};
13025 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
13026 DAG.getUNDEF(MVT::v16i8),
13028 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
13029 DAG.getUNDEF(MVT::v16i8),
13032 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13033 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13036 int ShufMask2[] = {0, 1, 4, 5};
13038 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13039 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13045 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13046 /// specific shuffle of a load can be folded into a single element load.
13047 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13048 /// shuffles have been customed lowered so we need to handle those here.
13049 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13050 TargetLowering::DAGCombinerInfo &DCI) {
13051 if (DCI.isBeforeLegalizeOps())
13054 SDValue InVec = N->getOperand(0);
13055 SDValue EltNo = N->getOperand(1);
13057 if (!isa<ConstantSDNode>(EltNo))
13060 EVT VT = InVec.getValueType();
13062 bool HasShuffleIntoBitcast = false;
13063 if (InVec.getOpcode() == ISD::BITCAST) {
13064 // Don't duplicate a load with other uses.
13065 if (!InVec.hasOneUse())
13067 EVT BCVT = InVec.getOperand(0).getValueType();
13068 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13070 InVec = InVec.getOperand(0);
13071 HasShuffleIntoBitcast = true;
13074 if (!isTargetShuffle(InVec.getOpcode()))
13077 // Don't duplicate a load with other uses.
13078 if (!InVec.hasOneUse())
13081 SmallVector<int, 16> ShuffleMask;
13083 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
13086 // Select the input vector, guarding against out of range extract vector.
13087 unsigned NumElems = VT.getVectorNumElements();
13088 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13089 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13090 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13091 : InVec.getOperand(1);
13093 // If inputs to shuffle are the same for both ops, then allow 2 uses
13094 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13096 if (LdNode.getOpcode() == ISD::BITCAST) {
13097 // Don't duplicate a load with other uses.
13098 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13101 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13102 LdNode = LdNode.getOperand(0);
13105 if (!ISD::isNormalLoad(LdNode.getNode()))
13108 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13110 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13113 if (HasShuffleIntoBitcast) {
13114 // If there's a bitcast before the shuffle, check if the load type and
13115 // alignment is valid.
13116 unsigned Align = LN0->getAlignment();
13117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13118 unsigned NewAlign = TLI.getTargetData()->
13119 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13121 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13125 // All checks match so transform back to vector_shuffle so that DAG combiner
13126 // can finish the job
13127 DebugLoc dl = N->getDebugLoc();
13129 // Create shuffle node taking into account the case that its a unary shuffle
13130 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13131 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13132 InVec.getOperand(0), Shuffle,
13134 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13135 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13139 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13140 /// generation and convert it from being a bunch of shuffles and extracts
13141 /// to a simple store and scalar loads to extract the elements.
13142 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13143 TargetLowering::DAGCombinerInfo &DCI) {
13144 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13145 if (NewOp.getNode())
13148 SDValue InputVector = N->getOperand(0);
13150 // Only operate on vectors of 4 elements, where the alternative shuffling
13151 // gets to be more expensive.
13152 if (InputVector.getValueType() != MVT::v4i32)
13155 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13156 // single use which is a sign-extend or zero-extend, and all elements are
13158 SmallVector<SDNode *, 4> Uses;
13159 unsigned ExtractedElements = 0;
13160 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13161 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13162 if (UI.getUse().getResNo() != InputVector.getResNo())
13165 SDNode *Extract = *UI;
13166 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13169 if (Extract->getValueType(0) != MVT::i32)
13171 if (!Extract->hasOneUse())
13173 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13174 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13176 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13179 // Record which element was extracted.
13180 ExtractedElements |=
13181 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13183 Uses.push_back(Extract);
13186 // If not all the elements were used, this may not be worthwhile.
13187 if (ExtractedElements != 15)
13190 // Ok, we've now decided to do the transformation.
13191 DebugLoc dl = InputVector.getDebugLoc();
13193 // Store the value to a temporary stack slot.
13194 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13195 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13196 MachinePointerInfo(), false, false, 0);
13198 // Replace each use (extract) with a load of the appropriate element.
13199 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13200 UE = Uses.end(); UI != UE; ++UI) {
13201 SDNode *Extract = *UI;
13203 // cOMpute the element's address.
13204 SDValue Idx = Extract->getOperand(1);
13206 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13207 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13208 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13209 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13211 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13212 StackPtr, OffsetVal);
13214 // Load the scalar.
13215 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13216 ScalarAddr, MachinePointerInfo(),
13217 false, false, false, 0);
13219 // Replace the exact with the load.
13220 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13223 // The replacement was made in place; don't return anything.
13227 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13229 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13230 TargetLowering::DAGCombinerInfo &DCI,
13231 const X86Subtarget *Subtarget) {
13234 DebugLoc DL = N->getDebugLoc();
13235 SDValue Cond = N->getOperand(0);
13236 // Get the LHS/RHS of the select.
13237 SDValue LHS = N->getOperand(1);
13238 SDValue RHS = N->getOperand(2);
13239 EVT VT = LHS.getValueType();
13241 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13242 // instructions match the semantics of the common C idiom x<y?x:y but not
13243 // x<=y?x:y, because of how they handle negative zero (which can be
13244 // ignored in unsafe-math mode).
13245 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13246 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13247 (Subtarget->hasSSE2() ||
13248 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13249 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13251 unsigned Opcode = 0;
13252 // Check for x CC y ? x : y.
13253 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13254 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13258 // Converting this to a min would handle NaNs incorrectly, and swapping
13259 // the operands would cause it to handle comparisons between positive
13260 // and negative zero incorrectly.
13261 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13262 if (!DAG.getTarget().Options.UnsafeFPMath &&
13263 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13265 std::swap(LHS, RHS);
13267 Opcode = X86ISD::FMIN;
13270 // Converting this to a min would handle comparisons between positive
13271 // and negative zero incorrectly.
13272 if (!DAG.getTarget().Options.UnsafeFPMath &&
13273 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13275 Opcode = X86ISD::FMIN;
13278 // Converting this to a min would handle both negative zeros and NaNs
13279 // incorrectly, but we can swap the operands to fix both.
13280 std::swap(LHS, RHS);
13284 Opcode = X86ISD::FMIN;
13288 // Converting this to a max would handle comparisons between positive
13289 // and negative zero incorrectly.
13290 if (!DAG.getTarget().Options.UnsafeFPMath &&
13291 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13293 Opcode = X86ISD::FMAX;
13296 // Converting this to a max would handle NaNs incorrectly, and swapping
13297 // the operands would cause it to handle comparisons between positive
13298 // and negative zero incorrectly.
13299 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13300 if (!DAG.getTarget().Options.UnsafeFPMath &&
13301 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13303 std::swap(LHS, RHS);
13305 Opcode = X86ISD::FMAX;
13308 // Converting this to a max would handle both negative zeros and NaNs
13309 // incorrectly, but we can swap the operands to fix both.
13310 std::swap(LHS, RHS);
13314 Opcode = X86ISD::FMAX;
13317 // Check for x CC y ? y : x -- a min/max with reversed arms.
13318 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13319 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13323 // Converting this to a min would handle comparisons between positive
13324 // and negative zero incorrectly, and swapping the operands would
13325 // cause it to handle NaNs incorrectly.
13326 if (!DAG.getTarget().Options.UnsafeFPMath &&
13327 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13328 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13330 std::swap(LHS, RHS);
13332 Opcode = X86ISD::FMIN;
13335 // Converting this to a min would handle NaNs incorrectly.
13336 if (!DAG.getTarget().Options.UnsafeFPMath &&
13337 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13339 Opcode = X86ISD::FMIN;
13342 // Converting this to a min would handle both negative zeros and NaNs
13343 // incorrectly, but we can swap the operands to fix both.
13344 std::swap(LHS, RHS);
13348 Opcode = X86ISD::FMIN;
13352 // Converting this to a max would handle NaNs incorrectly.
13353 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13355 Opcode = X86ISD::FMAX;
13358 // Converting this to a max would handle comparisons between positive
13359 // and negative zero incorrectly, and swapping the operands would
13360 // cause it to handle NaNs incorrectly.
13361 if (!DAG.getTarget().Options.UnsafeFPMath &&
13362 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13363 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13365 std::swap(LHS, RHS);
13367 Opcode = X86ISD::FMAX;
13370 // Converting this to a max would handle both negative zeros and NaNs
13371 // incorrectly, but we can swap the operands to fix both.
13372 std::swap(LHS, RHS);
13376 Opcode = X86ISD::FMAX;
13382 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13385 // If this is a select between two integer constants, try to do some
13387 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13388 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13389 // Don't do this for crazy integer types.
13390 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13391 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13392 // so that TrueC (the true value) is larger than FalseC.
13393 bool NeedsCondInvert = false;
13395 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13396 // Efficiently invertible.
13397 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13398 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13399 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13400 NeedsCondInvert = true;
13401 std::swap(TrueC, FalseC);
13404 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13405 if (FalseC->getAPIntValue() == 0 &&
13406 TrueC->getAPIntValue().isPowerOf2()) {
13407 if (NeedsCondInvert) // Invert the condition if needed.
13408 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13409 DAG.getConstant(1, Cond.getValueType()));
13411 // Zero extend the condition if needed.
13412 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13414 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13415 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13416 DAG.getConstant(ShAmt, MVT::i8));
13419 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13420 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13421 if (NeedsCondInvert) // Invert the condition if needed.
13422 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13423 DAG.getConstant(1, Cond.getValueType()));
13425 // Zero extend the condition if needed.
13426 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13427 FalseC->getValueType(0), Cond);
13428 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13429 SDValue(FalseC, 0));
13432 // Optimize cases that will turn into an LEA instruction. This requires
13433 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13434 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13435 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13436 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13438 bool isFastMultiplier = false;
13440 switch ((unsigned char)Diff) {
13442 case 1: // result = add base, cond
13443 case 2: // result = lea base( , cond*2)
13444 case 3: // result = lea base(cond, cond*2)
13445 case 4: // result = lea base( , cond*4)
13446 case 5: // result = lea base(cond, cond*4)
13447 case 8: // result = lea base( , cond*8)
13448 case 9: // result = lea base(cond, cond*8)
13449 isFastMultiplier = true;
13454 if (isFastMultiplier) {
13455 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13456 if (NeedsCondInvert) // Invert the condition if needed.
13457 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13458 DAG.getConstant(1, Cond.getValueType()));
13460 // Zero extend the condition if needed.
13461 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13463 // Scale the condition by the difference.
13465 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13466 DAG.getConstant(Diff, Cond.getValueType()));
13468 // Add the base if non-zero.
13469 if (FalseC->getAPIntValue() != 0)
13470 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13471 SDValue(FalseC, 0));
13478 // Canonicalize max and min:
13479 // (x > y) ? x : y -> (x >= y) ? x : y
13480 // (x < y) ? x : y -> (x <= y) ? x : y
13481 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13482 // the need for an extra compare
13483 // against zero. e.g.
13484 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13486 // testl %edi, %edi
13488 // cmovgl %edi, %eax
13492 // cmovsl %eax, %edi
13493 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13494 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13495 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13496 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13501 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13502 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13503 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13504 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13509 // If we know that this node is legal then we know that it is going to be
13510 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13511 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13512 // to simplify previous instructions.
13513 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13514 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13515 !DCI.isBeforeLegalize() &&
13516 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13517 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13518 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13519 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13521 APInt KnownZero, KnownOne;
13522 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13523 DCI.isBeforeLegalizeOps());
13524 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13525 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13526 DCI.CommitTargetLoweringOpt(TLO);
13532 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13533 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13534 TargetLowering::DAGCombinerInfo &DCI) {
13535 DebugLoc DL = N->getDebugLoc();
13537 // If the flag operand isn't dead, don't touch this CMOV.
13538 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13541 SDValue FalseOp = N->getOperand(0);
13542 SDValue TrueOp = N->getOperand(1);
13543 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13544 SDValue Cond = N->getOperand(3);
13545 if (CC == X86::COND_E || CC == X86::COND_NE) {
13546 switch (Cond.getOpcode()) {
13550 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13551 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13552 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13556 // If this is a select between two integer constants, try to do some
13557 // optimizations. Note that the operands are ordered the opposite of SELECT
13559 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13560 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13561 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13562 // larger than FalseC (the false value).
13563 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13564 CC = X86::GetOppositeBranchCondition(CC);
13565 std::swap(TrueC, FalseC);
13568 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13569 // This is efficient for any integer data type (including i8/i16) and
13571 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13572 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13573 DAG.getConstant(CC, MVT::i8), Cond);
13575 // Zero extend the condition if needed.
13576 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13578 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13579 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13580 DAG.getConstant(ShAmt, MVT::i8));
13581 if (N->getNumValues() == 2) // Dead flag value?
13582 return DCI.CombineTo(N, Cond, SDValue());
13586 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13587 // for any integer data type, including i8/i16.
13588 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13589 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13590 DAG.getConstant(CC, MVT::i8), Cond);
13592 // Zero extend the condition if needed.
13593 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13594 FalseC->getValueType(0), Cond);
13595 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13596 SDValue(FalseC, 0));
13598 if (N->getNumValues() == 2) // Dead flag value?
13599 return DCI.CombineTo(N, Cond, SDValue());
13603 // Optimize cases that will turn into an LEA instruction. This requires
13604 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13605 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13606 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13607 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13609 bool isFastMultiplier = false;
13611 switch ((unsigned char)Diff) {
13613 case 1: // result = add base, cond
13614 case 2: // result = lea base( , cond*2)
13615 case 3: // result = lea base(cond, cond*2)
13616 case 4: // result = lea base( , cond*4)
13617 case 5: // result = lea base(cond, cond*4)
13618 case 8: // result = lea base( , cond*8)
13619 case 9: // result = lea base(cond, cond*8)
13620 isFastMultiplier = true;
13625 if (isFastMultiplier) {
13626 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13627 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13628 DAG.getConstant(CC, MVT::i8), Cond);
13629 // Zero extend the condition if needed.
13630 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13632 // Scale the condition by the difference.
13634 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13635 DAG.getConstant(Diff, Cond.getValueType()));
13637 // Add the base if non-zero.
13638 if (FalseC->getAPIntValue() != 0)
13639 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13640 SDValue(FalseC, 0));
13641 if (N->getNumValues() == 2) // Dead flag value?
13642 return DCI.CombineTo(N, Cond, SDValue());
13652 /// PerformMulCombine - Optimize a single multiply with constant into two
13653 /// in order to implement it with two cheaper instructions, e.g.
13654 /// LEA + SHL, LEA + LEA.
13655 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13656 TargetLowering::DAGCombinerInfo &DCI) {
13657 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13660 EVT VT = N->getValueType(0);
13661 if (VT != MVT::i64)
13664 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13667 uint64_t MulAmt = C->getZExtValue();
13668 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13671 uint64_t MulAmt1 = 0;
13672 uint64_t MulAmt2 = 0;
13673 if ((MulAmt % 9) == 0) {
13675 MulAmt2 = MulAmt / 9;
13676 } else if ((MulAmt % 5) == 0) {
13678 MulAmt2 = MulAmt / 5;
13679 } else if ((MulAmt % 3) == 0) {
13681 MulAmt2 = MulAmt / 3;
13684 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13685 DebugLoc DL = N->getDebugLoc();
13687 if (isPowerOf2_64(MulAmt2) &&
13688 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13689 // If second multiplifer is pow2, issue it first. We want the multiply by
13690 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13692 std::swap(MulAmt1, MulAmt2);
13695 if (isPowerOf2_64(MulAmt1))
13696 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13697 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13699 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13700 DAG.getConstant(MulAmt1, VT));
13702 if (isPowerOf2_64(MulAmt2))
13703 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13704 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13706 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13707 DAG.getConstant(MulAmt2, VT));
13709 // Do not add new nodes to DAG combiner worklist.
13710 DCI.CombineTo(N, NewMul, false);
13715 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13716 SDValue N0 = N->getOperand(0);
13717 SDValue N1 = N->getOperand(1);
13718 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13719 EVT VT = N0.getValueType();
13721 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13722 // since the result of setcc_c is all zero's or all ones.
13723 if (VT.isInteger() && !VT.isVector() &&
13724 N1C && N0.getOpcode() == ISD::AND &&
13725 N0.getOperand(1).getOpcode() == ISD::Constant) {
13726 SDValue N00 = N0.getOperand(0);
13727 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13728 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13729 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13730 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13731 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13732 APInt ShAmt = N1C->getAPIntValue();
13733 Mask = Mask.shl(ShAmt);
13735 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13736 N00, DAG.getConstant(Mask, VT));
13741 // Hardware support for vector shifts is sparse which makes us scalarize the
13742 // vector operations in many cases. Also, on sandybridge ADD is faster than
13744 // (shl V, 1) -> add V,V
13745 if (isSplatVector(N1.getNode())) {
13746 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13747 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13748 // We shift all of the values by one. In many cases we do not have
13749 // hardware support for this operation. This is better expressed as an ADD
13751 if (N1C && (1 == N1C->getZExtValue())) {
13752 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13759 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13761 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13762 TargetLowering::DAGCombinerInfo &DCI,
13763 const X86Subtarget *Subtarget) {
13764 EVT VT = N->getValueType(0);
13765 if (N->getOpcode() == ISD::SHL) {
13766 SDValue V = PerformSHLCombine(N, DAG);
13767 if (V.getNode()) return V;
13770 // On X86 with SSE2 support, we can transform this to a vector shift if
13771 // all elements are shifted by the same amount. We can't do this in legalize
13772 // because the a constant vector is typically transformed to a constant pool
13773 // so we have no knowledge of the shift amount.
13774 if (!Subtarget->hasSSE2())
13777 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13778 (!Subtarget->hasAVX2() ||
13779 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13782 SDValue ShAmtOp = N->getOperand(1);
13783 EVT EltVT = VT.getVectorElementType();
13784 DebugLoc DL = N->getDebugLoc();
13785 SDValue BaseShAmt = SDValue();
13786 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13787 unsigned NumElts = VT.getVectorNumElements();
13789 for (; i != NumElts; ++i) {
13790 SDValue Arg = ShAmtOp.getOperand(i);
13791 if (Arg.getOpcode() == ISD::UNDEF) continue;
13795 // Handle the case where the build_vector is all undef
13796 // FIXME: Should DAG allow this?
13800 for (; i != NumElts; ++i) {
13801 SDValue Arg = ShAmtOp.getOperand(i);
13802 if (Arg.getOpcode() == ISD::UNDEF) continue;
13803 if (Arg != BaseShAmt) {
13807 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13808 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13809 SDValue InVec = ShAmtOp.getOperand(0);
13810 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13811 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13813 for (; i != NumElts; ++i) {
13814 SDValue Arg = InVec.getOperand(i);
13815 if (Arg.getOpcode() == ISD::UNDEF) continue;
13819 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13820 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13821 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13822 if (C->getZExtValue() == SplatIdx)
13823 BaseShAmt = InVec.getOperand(1);
13826 if (BaseShAmt.getNode() == 0) {
13827 // Don't create instructions with illegal types after legalize
13829 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13830 !DCI.isBeforeLegalize())
13833 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13834 DAG.getIntPtrConstant(0));
13839 // The shift amount is an i32.
13840 if (EltVT.bitsGT(MVT::i32))
13841 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13842 else if (EltVT.bitsLT(MVT::i32))
13843 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13845 // The shift amount is identical so we can do a vector shift.
13846 SDValue ValOp = N->getOperand(0);
13847 switch (N->getOpcode()) {
13849 llvm_unreachable("Unknown shift opcode!");
13851 switch (VT.getSimpleVT().SimpleTy) {
13852 default: return SDValue();
13859 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13862 switch (VT.getSimpleVT().SimpleTy) {
13863 default: return SDValue();
13868 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13871 switch (VT.getSimpleVT().SimpleTy) {
13872 default: return SDValue();
13879 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13885 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13886 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13887 // and friends. Likewise for OR -> CMPNEQSS.
13888 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13889 TargetLowering::DAGCombinerInfo &DCI,
13890 const X86Subtarget *Subtarget) {
13893 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13894 // we're requiring SSE2 for both.
13895 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13896 SDValue N0 = N->getOperand(0);
13897 SDValue N1 = N->getOperand(1);
13898 SDValue CMP0 = N0->getOperand(1);
13899 SDValue CMP1 = N1->getOperand(1);
13900 DebugLoc DL = N->getDebugLoc();
13902 // The SETCCs should both refer to the same CMP.
13903 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13906 SDValue CMP00 = CMP0->getOperand(0);
13907 SDValue CMP01 = CMP0->getOperand(1);
13908 EVT VT = CMP00.getValueType();
13910 if (VT == MVT::f32 || VT == MVT::f64) {
13911 bool ExpectingFlags = false;
13912 // Check for any users that want flags:
13913 for (SDNode::use_iterator UI = N->use_begin(),
13915 !ExpectingFlags && UI != UE; ++UI)
13916 switch (UI->getOpcode()) {
13921 ExpectingFlags = true;
13923 case ISD::CopyToReg:
13924 case ISD::SIGN_EXTEND:
13925 case ISD::ZERO_EXTEND:
13926 case ISD::ANY_EXTEND:
13930 if (!ExpectingFlags) {
13931 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13932 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13934 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13935 X86::CondCode tmp = cc0;
13940 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13941 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13942 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13943 X86ISD::NodeType NTOperator = is64BitFP ?
13944 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13945 // FIXME: need symbolic constants for these magic numbers.
13946 // See X86ATTInstPrinter.cpp:printSSECC().
13947 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13948 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13949 DAG.getConstant(x86cc, MVT::i8));
13950 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13952 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13953 DAG.getConstant(1, MVT::i32));
13954 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13955 return OneBitOfTruth;
13963 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13964 /// so it can be folded inside ANDNP.
13965 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13966 EVT VT = N->getValueType(0);
13968 // Match direct AllOnes for 128 and 256-bit vectors
13969 if (ISD::isBuildVectorAllOnes(N))
13972 // Look through a bit convert.
13973 if (N->getOpcode() == ISD::BITCAST)
13974 N = N->getOperand(0).getNode();
13976 // Sometimes the operand may come from a insert_subvector building a 256-bit
13978 if (VT.getSizeInBits() == 256 &&
13979 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13980 SDValue V1 = N->getOperand(0);
13981 SDValue V2 = N->getOperand(1);
13983 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13984 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13985 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13986 ISD::isBuildVectorAllOnes(V2.getNode()))
13993 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13994 TargetLowering::DAGCombinerInfo &DCI,
13995 const X86Subtarget *Subtarget) {
13996 if (DCI.isBeforeLegalizeOps())
13999 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14003 EVT VT = N->getValueType(0);
14005 // Create ANDN, BLSI, and BLSR instructions
14006 // BLSI is X & (-X)
14007 // BLSR is X & (X-1)
14008 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14009 SDValue N0 = N->getOperand(0);
14010 SDValue N1 = N->getOperand(1);
14011 DebugLoc DL = N->getDebugLoc();
14013 // Check LHS for not
14014 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14015 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14016 // Check RHS for not
14017 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14018 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14020 // Check LHS for neg
14021 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14022 isZero(N0.getOperand(0)))
14023 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14025 // Check RHS for neg
14026 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14027 isZero(N1.getOperand(0)))
14028 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14030 // Check LHS for X-1
14031 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14032 isAllOnes(N0.getOperand(1)))
14033 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14035 // Check RHS for X-1
14036 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14037 isAllOnes(N1.getOperand(1)))
14038 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14043 // Want to form ANDNP nodes:
14044 // 1) In the hopes of then easily combining them with OR and AND nodes
14045 // to form PBLEND/PSIGN.
14046 // 2) To match ANDN packed intrinsics
14047 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14050 SDValue N0 = N->getOperand(0);
14051 SDValue N1 = N->getOperand(1);
14052 DebugLoc DL = N->getDebugLoc();
14054 // Check LHS for vnot
14055 if (N0.getOpcode() == ISD::XOR &&
14056 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14057 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14058 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14060 // Check RHS for vnot
14061 if (N1.getOpcode() == ISD::XOR &&
14062 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14063 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14064 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14069 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14070 TargetLowering::DAGCombinerInfo &DCI,
14071 const X86Subtarget *Subtarget) {
14072 if (DCI.isBeforeLegalizeOps())
14075 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14079 EVT VT = N->getValueType(0);
14081 SDValue N0 = N->getOperand(0);
14082 SDValue N1 = N->getOperand(1);
14084 // look for psign/blend
14085 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14086 if (!Subtarget->hasSSSE3() ||
14087 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14090 // Canonicalize pandn to RHS
14091 if (N0.getOpcode() == X86ISD::ANDNP)
14093 // or (and (m, y), (pandn m, x))
14094 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14095 SDValue Mask = N1.getOperand(0);
14096 SDValue X = N1.getOperand(1);
14098 if (N0.getOperand(0) == Mask)
14099 Y = N0.getOperand(1);
14100 if (N0.getOperand(1) == Mask)
14101 Y = N0.getOperand(0);
14103 // Check to see if the mask appeared in both the AND and ANDNP and
14107 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14108 // Look through mask bitcast.
14109 if (Mask.getOpcode() == ISD::BITCAST)
14110 Mask = Mask.getOperand(0);
14111 if (X.getOpcode() == ISD::BITCAST)
14112 X = X.getOperand(0);
14113 if (Y.getOpcode() == ISD::BITCAST)
14114 Y = Y.getOperand(0);
14116 EVT MaskVT = Mask.getValueType();
14118 // Validate that the Mask operand is a vector sra node.
14119 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14120 // there is no psrai.b
14121 if (Mask.getOpcode() != X86ISD::VSRAI)
14124 // Check that the SRA is all signbits.
14125 SDValue SraC = Mask.getOperand(1);
14126 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14127 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14128 if ((SraAmt + 1) != EltBits)
14131 DebugLoc DL = N->getDebugLoc();
14133 // Now we know we at least have a plendvb with the mask val. See if
14134 // we can form a psignb/w/d.
14135 // psign = x.type == y.type == mask.type && y = sub(0, x);
14136 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14137 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14138 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14139 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14140 "Unsupported VT for PSIGN");
14141 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14142 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14144 // PBLENDVB only available on SSE 4.1
14145 if (!Subtarget->hasSSE41())
14148 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14150 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14151 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14152 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14153 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14154 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14158 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14161 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14162 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14164 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14166 if (!N0.hasOneUse() || !N1.hasOneUse())
14169 SDValue ShAmt0 = N0.getOperand(1);
14170 if (ShAmt0.getValueType() != MVT::i8)
14172 SDValue ShAmt1 = N1.getOperand(1);
14173 if (ShAmt1.getValueType() != MVT::i8)
14175 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14176 ShAmt0 = ShAmt0.getOperand(0);
14177 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14178 ShAmt1 = ShAmt1.getOperand(0);
14180 DebugLoc DL = N->getDebugLoc();
14181 unsigned Opc = X86ISD::SHLD;
14182 SDValue Op0 = N0.getOperand(0);
14183 SDValue Op1 = N1.getOperand(0);
14184 if (ShAmt0.getOpcode() == ISD::SUB) {
14185 Opc = X86ISD::SHRD;
14186 std::swap(Op0, Op1);
14187 std::swap(ShAmt0, ShAmt1);
14190 unsigned Bits = VT.getSizeInBits();
14191 if (ShAmt1.getOpcode() == ISD::SUB) {
14192 SDValue Sum = ShAmt1.getOperand(0);
14193 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14194 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14195 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14196 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14197 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14198 return DAG.getNode(Opc, DL, VT,
14200 DAG.getNode(ISD::TRUNCATE, DL,
14203 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14204 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14206 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14207 return DAG.getNode(Opc, DL, VT,
14208 N0.getOperand(0), N1.getOperand(0),
14209 DAG.getNode(ISD::TRUNCATE, DL,
14216 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14217 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14218 TargetLowering::DAGCombinerInfo &DCI,
14219 const X86Subtarget *Subtarget) {
14220 if (DCI.isBeforeLegalizeOps())
14223 EVT VT = N->getValueType(0);
14225 if (VT != MVT::i32 && VT != MVT::i64)
14228 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14230 // Create BLSMSK instructions by finding X ^ (X-1)
14231 SDValue N0 = N->getOperand(0);
14232 SDValue N1 = N->getOperand(1);
14233 DebugLoc DL = N->getDebugLoc();
14235 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14236 isAllOnes(N0.getOperand(1)))
14237 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14239 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14240 isAllOnes(N1.getOperand(1)))
14241 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14246 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14247 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14248 const X86Subtarget *Subtarget) {
14249 LoadSDNode *Ld = cast<LoadSDNode>(N);
14250 EVT RegVT = Ld->getValueType(0);
14251 EVT MemVT = Ld->getMemoryVT();
14252 DebugLoc dl = Ld->getDebugLoc();
14253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14255 ISD::LoadExtType Ext = Ld->getExtensionType();
14257 // If this is a vector EXT Load then attempt to optimize it using a
14258 // shuffle. We need SSE4 for the shuffles.
14259 // TODO: It is possible to support ZExt by zeroing the undef values
14260 // during the shuffle phase or after the shuffle.
14261 if (RegVT.isVector() && RegVT.isInteger() &&
14262 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14263 assert(MemVT != RegVT && "Cannot extend to the same type");
14264 assert(MemVT.isVector() && "Must load a vector from memory");
14266 unsigned NumElems = RegVT.getVectorNumElements();
14267 unsigned RegSz = RegVT.getSizeInBits();
14268 unsigned MemSz = MemVT.getSizeInBits();
14269 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14270 // All sizes must be a power of two
14271 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14273 // Attempt to load the original value using a single load op.
14274 // Find a scalar type which is equal to the loaded word size.
14275 MVT SclrLoadTy = MVT::i8;
14276 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14277 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14278 MVT Tp = (MVT::SimpleValueType)tp;
14279 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14285 // Proceed if a load word is found.
14286 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14288 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14289 RegSz/SclrLoadTy.getSizeInBits());
14291 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14292 RegSz/MemVT.getScalarType().getSizeInBits());
14293 // Can't shuffle using an illegal type.
14294 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14296 // Perform a single load.
14297 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14299 Ld->getPointerInfo(), Ld->isVolatile(),
14300 Ld->isNonTemporal(), Ld->isInvariant(),
14301 Ld->getAlignment());
14303 // Insert the word loaded into a vector.
14304 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14305 LoadUnitVecVT, ScalarLoad);
14307 // Bitcast the loaded value to a vector of the original element type, in
14308 // the size of the target vector type.
14309 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14311 unsigned SizeRatio = RegSz/MemSz;
14313 // Redistribute the loaded elements into the different locations.
14314 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14315 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14317 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14318 DAG.getUNDEF(SlicedVec.getValueType()),
14319 ShuffleVec.data());
14321 // Bitcast to the requested type.
14322 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14323 // Replace the original load with the new sequence
14324 // and return the new chain.
14325 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14326 return SDValue(ScalarLoad.getNode(), 1);
14332 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14333 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14334 const X86Subtarget *Subtarget) {
14335 StoreSDNode *St = cast<StoreSDNode>(N);
14336 EVT VT = St->getValue().getValueType();
14337 EVT StVT = St->getMemoryVT();
14338 DebugLoc dl = St->getDebugLoc();
14339 SDValue StoredVal = St->getOperand(1);
14340 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14342 // If we are saving a concatenation of two XMM registers, perform two stores.
14343 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14344 // 128-bit ones. If in the future the cost becomes only one memory access the
14345 // first version would be better.
14346 if (VT.getSizeInBits() == 256 &&
14347 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14348 StoredVal.getNumOperands() == 2) {
14350 SDValue Value0 = StoredVal.getOperand(0);
14351 SDValue Value1 = StoredVal.getOperand(1);
14353 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14354 SDValue Ptr0 = St->getBasePtr();
14355 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14357 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14358 St->getPointerInfo(), St->isVolatile(),
14359 St->isNonTemporal(), St->getAlignment());
14360 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14361 St->getPointerInfo(), St->isVolatile(),
14362 St->isNonTemporal(), St->getAlignment());
14363 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14366 // Optimize trunc store (of multiple scalars) to shuffle and store.
14367 // First, pack all of the elements in one place. Next, store to memory
14368 // in fewer chunks.
14369 if (St->isTruncatingStore() && VT.isVector()) {
14370 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14371 unsigned NumElems = VT.getVectorNumElements();
14372 assert(StVT != VT && "Cannot truncate to the same type");
14373 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14374 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14376 // From, To sizes and ElemCount must be pow of two
14377 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14378 // We are going to use the original vector elt for storing.
14379 // Accumulated smaller vector elements must be a multiple of the store size.
14380 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14382 unsigned SizeRatio = FromSz / ToSz;
14384 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14386 // Create a type on which we perform the shuffle
14387 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14388 StVT.getScalarType(), NumElems*SizeRatio);
14390 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14392 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14393 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14394 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14396 // Can't shuffle using an illegal type
14397 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14399 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14400 DAG.getUNDEF(WideVec.getValueType()),
14401 ShuffleVec.data());
14402 // At this point all of the data is stored at the bottom of the
14403 // register. We now need to save it to mem.
14405 // Find the largest store unit
14406 MVT StoreType = MVT::i8;
14407 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14408 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14409 MVT Tp = (MVT::SimpleValueType)tp;
14410 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14414 // Bitcast the original vector into a vector of store-size units
14415 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14416 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14417 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14418 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14419 SmallVector<SDValue, 8> Chains;
14420 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14421 TLI.getPointerTy());
14422 SDValue Ptr = St->getBasePtr();
14424 // Perform one or more big stores into memory.
14425 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14426 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14427 StoreType, ShuffWide,
14428 DAG.getIntPtrConstant(i));
14429 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14430 St->getPointerInfo(), St->isVolatile(),
14431 St->isNonTemporal(), St->getAlignment());
14432 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14433 Chains.push_back(Ch);
14436 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14441 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14442 // the FP state in cases where an emms may be missing.
14443 // A preferable solution to the general problem is to figure out the right
14444 // places to insert EMMS. This qualifies as a quick hack.
14446 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14447 if (VT.getSizeInBits() != 64)
14450 const Function *F = DAG.getMachineFunction().getFunction();
14451 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14452 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14453 && Subtarget->hasSSE2();
14454 if ((VT.isVector() ||
14455 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14456 isa<LoadSDNode>(St->getValue()) &&
14457 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14458 St->getChain().hasOneUse() && !St->isVolatile()) {
14459 SDNode* LdVal = St->getValue().getNode();
14460 LoadSDNode *Ld = 0;
14461 int TokenFactorIndex = -1;
14462 SmallVector<SDValue, 8> Ops;
14463 SDNode* ChainVal = St->getChain().getNode();
14464 // Must be a store of a load. We currently handle two cases: the load
14465 // is a direct child, and it's under an intervening TokenFactor. It is
14466 // possible to dig deeper under nested TokenFactors.
14467 if (ChainVal == LdVal)
14468 Ld = cast<LoadSDNode>(St->getChain());
14469 else if (St->getValue().hasOneUse() &&
14470 ChainVal->getOpcode() == ISD::TokenFactor) {
14471 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14472 if (ChainVal->getOperand(i).getNode() == LdVal) {
14473 TokenFactorIndex = i;
14474 Ld = cast<LoadSDNode>(St->getValue());
14476 Ops.push_back(ChainVal->getOperand(i));
14480 if (!Ld || !ISD::isNormalLoad(Ld))
14483 // If this is not the MMX case, i.e. we are just turning i64 load/store
14484 // into f64 load/store, avoid the transformation if there are multiple
14485 // uses of the loaded value.
14486 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14489 DebugLoc LdDL = Ld->getDebugLoc();
14490 DebugLoc StDL = N->getDebugLoc();
14491 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14492 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14494 if (Subtarget->is64Bit() || F64IsLegal) {
14495 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14496 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14497 Ld->getPointerInfo(), Ld->isVolatile(),
14498 Ld->isNonTemporal(), Ld->isInvariant(),
14499 Ld->getAlignment());
14500 SDValue NewChain = NewLd.getValue(1);
14501 if (TokenFactorIndex != -1) {
14502 Ops.push_back(NewChain);
14503 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14506 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14507 St->getPointerInfo(),
14508 St->isVolatile(), St->isNonTemporal(),
14509 St->getAlignment());
14512 // Otherwise, lower to two pairs of 32-bit loads / stores.
14513 SDValue LoAddr = Ld->getBasePtr();
14514 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14515 DAG.getConstant(4, MVT::i32));
14517 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14518 Ld->getPointerInfo(),
14519 Ld->isVolatile(), Ld->isNonTemporal(),
14520 Ld->isInvariant(), Ld->getAlignment());
14521 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14522 Ld->getPointerInfo().getWithOffset(4),
14523 Ld->isVolatile(), Ld->isNonTemporal(),
14525 MinAlign(Ld->getAlignment(), 4));
14527 SDValue NewChain = LoLd.getValue(1);
14528 if (TokenFactorIndex != -1) {
14529 Ops.push_back(LoLd);
14530 Ops.push_back(HiLd);
14531 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14535 LoAddr = St->getBasePtr();
14536 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14537 DAG.getConstant(4, MVT::i32));
14539 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14540 St->getPointerInfo(),
14541 St->isVolatile(), St->isNonTemporal(),
14542 St->getAlignment());
14543 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14544 St->getPointerInfo().getWithOffset(4),
14546 St->isNonTemporal(),
14547 MinAlign(St->getAlignment(), 4));
14548 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14553 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14554 /// and return the operands for the horizontal operation in LHS and RHS. A
14555 /// horizontal operation performs the binary operation on successive elements
14556 /// of its first operand, then on successive elements of its second operand,
14557 /// returning the resulting values in a vector. For example, if
14558 /// A = < float a0, float a1, float a2, float a3 >
14560 /// B = < float b0, float b1, float b2, float b3 >
14561 /// then the result of doing a horizontal operation on A and B is
14562 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14563 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14564 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14565 /// set to A, RHS to B, and the routine returns 'true'.
14566 /// Note that the binary operation should have the property that if one of the
14567 /// operands is UNDEF then the result is UNDEF.
14568 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14569 // Look for the following pattern: if
14570 // A = < float a0, float a1, float a2, float a3 >
14571 // B = < float b0, float b1, float b2, float b3 >
14573 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14574 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14575 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14576 // which is A horizontal-op B.
14578 // At least one of the operands should be a vector shuffle.
14579 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14580 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14583 EVT VT = LHS.getValueType();
14585 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14586 "Unsupported vector type for horizontal add/sub");
14588 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14589 // operate independently on 128-bit lanes.
14590 unsigned NumElts = VT.getVectorNumElements();
14591 unsigned NumLanes = VT.getSizeInBits()/128;
14592 unsigned NumLaneElts = NumElts / NumLanes;
14593 assert((NumLaneElts % 2 == 0) &&
14594 "Vector type should have an even number of elements in each lane");
14595 unsigned HalfLaneElts = NumLaneElts/2;
14597 // View LHS in the form
14598 // LHS = VECTOR_SHUFFLE A, B, LMask
14599 // If LHS is not a shuffle then pretend it is the shuffle
14600 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14601 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14604 SmallVector<int, 16> LMask(NumElts);
14605 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14606 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14607 A = LHS.getOperand(0);
14608 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14609 B = LHS.getOperand(1);
14610 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14611 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14613 if (LHS.getOpcode() != ISD::UNDEF)
14615 for (unsigned i = 0; i != NumElts; ++i)
14619 // Likewise, view RHS in the form
14620 // RHS = VECTOR_SHUFFLE C, D, RMask
14622 SmallVector<int, 16> RMask(NumElts);
14623 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14624 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14625 C = RHS.getOperand(0);
14626 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14627 D = RHS.getOperand(1);
14628 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14629 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14631 if (RHS.getOpcode() != ISD::UNDEF)
14633 for (unsigned i = 0; i != NumElts; ++i)
14637 // Check that the shuffles are both shuffling the same vectors.
14638 if (!(A == C && B == D) && !(A == D && B == C))
14641 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14642 if (!A.getNode() && !B.getNode())
14645 // If A and B occur in reverse order in RHS, then "swap" them (which means
14646 // rewriting the mask).
14648 CommuteVectorShuffleMask(RMask, NumElts);
14650 // At this point LHS and RHS are equivalent to
14651 // LHS = VECTOR_SHUFFLE A, B, LMask
14652 // RHS = VECTOR_SHUFFLE A, B, RMask
14653 // Check that the masks correspond to performing a horizontal operation.
14654 for (unsigned i = 0; i != NumElts; ++i) {
14655 int LIdx = LMask[i], RIdx = RMask[i];
14657 // Ignore any UNDEF components.
14658 if (LIdx < 0 || RIdx < 0 ||
14659 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14660 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14663 // Check that successive elements are being operated on. If not, this is
14664 // not a horizontal operation.
14665 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14666 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14667 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14668 if (!(LIdx == Index && RIdx == Index + 1) &&
14669 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14673 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14674 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14678 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14679 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14680 const X86Subtarget *Subtarget) {
14681 EVT VT = N->getValueType(0);
14682 SDValue LHS = N->getOperand(0);
14683 SDValue RHS = N->getOperand(1);
14685 // Try to synthesize horizontal adds from adds of shuffles.
14686 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14687 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14688 isHorizontalBinOp(LHS, RHS, true))
14689 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14693 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14694 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14695 const X86Subtarget *Subtarget) {
14696 EVT VT = N->getValueType(0);
14697 SDValue LHS = N->getOperand(0);
14698 SDValue RHS = N->getOperand(1);
14700 // Try to synthesize horizontal subs from subs of shuffles.
14701 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14702 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14703 isHorizontalBinOp(LHS, RHS, false))
14704 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14708 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14709 /// X86ISD::FXOR nodes.
14710 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14711 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14712 // F[X]OR(0.0, x) -> x
14713 // F[X]OR(x, 0.0) -> x
14714 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14715 if (C->getValueAPF().isPosZero())
14716 return N->getOperand(1);
14717 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14718 if (C->getValueAPF().isPosZero())
14719 return N->getOperand(0);
14723 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14724 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14725 // FAND(0.0, x) -> 0.0
14726 // FAND(x, 0.0) -> 0.0
14727 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14728 if (C->getValueAPF().isPosZero())
14729 return N->getOperand(0);
14730 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14731 if (C->getValueAPF().isPosZero())
14732 return N->getOperand(1);
14736 static SDValue PerformBTCombine(SDNode *N,
14738 TargetLowering::DAGCombinerInfo &DCI) {
14739 // BT ignores high bits in the bit index operand.
14740 SDValue Op1 = N->getOperand(1);
14741 if (Op1.hasOneUse()) {
14742 unsigned BitWidth = Op1.getValueSizeInBits();
14743 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14744 APInt KnownZero, KnownOne;
14745 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14746 !DCI.isBeforeLegalizeOps());
14747 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14748 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14749 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14750 DCI.CommitTargetLoweringOpt(TLO);
14755 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14756 SDValue Op = N->getOperand(0);
14757 if (Op.getOpcode() == ISD::BITCAST)
14758 Op = Op.getOperand(0);
14759 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14760 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14761 VT.getVectorElementType().getSizeInBits() ==
14762 OpVT.getVectorElementType().getSizeInBits()) {
14763 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14768 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14769 TargetLowering::DAGCombinerInfo &DCI,
14770 const X86Subtarget *Subtarget) {
14771 if (!DCI.isBeforeLegalizeOps())
14774 if (!Subtarget->hasAVX())
14777 // Optimize vectors in AVX mode
14778 // Sign extend v8i16 to v8i32 and
14781 // Divide input vector into two parts
14782 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14783 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14784 // concat the vectors to original VT
14786 EVT VT = N->getValueType(0);
14787 SDValue Op = N->getOperand(0);
14788 EVT OpVT = Op.getValueType();
14789 DebugLoc dl = N->getDebugLoc();
14791 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14792 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14794 unsigned NumElems = OpVT.getVectorNumElements();
14795 SmallVector<int,8> ShufMask1(NumElems, -1);
14796 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
14798 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14801 SmallVector<int,8> ShufMask2(NumElems, -1);
14802 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
14804 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14807 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14808 VT.getVectorNumElements()/2);
14810 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14811 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14813 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14818 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14819 const X86Subtarget *Subtarget) {
14820 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14821 // (and (i32 x86isd::setcc_carry), 1)
14822 // This eliminates the zext. This transformation is necessary because
14823 // ISD::SETCC is always legalized to i8.
14824 DebugLoc dl = N->getDebugLoc();
14825 SDValue N0 = N->getOperand(0);
14826 EVT VT = N->getValueType(0);
14827 EVT OpVT = N0.getValueType();
14829 if (N0.getOpcode() == ISD::AND &&
14831 N0.getOperand(0).hasOneUse()) {
14832 SDValue N00 = N0.getOperand(0);
14833 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14835 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14836 if (!C || C->getZExtValue() != 1)
14838 return DAG.getNode(ISD::AND, dl, VT,
14839 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14840 N00.getOperand(0), N00.getOperand(1)),
14841 DAG.getConstant(1, VT));
14843 // Optimize vectors in AVX mode:
14846 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14847 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14848 // Concat upper and lower parts.
14851 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14852 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14853 // Concat upper and lower parts.
14855 if (Subtarget->hasAVX()) {
14857 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14858 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14860 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14861 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
14862 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
14864 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14865 VT.getVectorNumElements()/2);
14867 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14868 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14870 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14878 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14879 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14880 unsigned X86CC = N->getConstantOperandVal(0);
14881 SDValue EFLAG = N->getOperand(1);
14882 DebugLoc DL = N->getDebugLoc();
14884 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14885 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14887 if (X86CC == X86::COND_B)
14888 return DAG.getNode(ISD::AND, DL, MVT::i8,
14889 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14890 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14891 DAG.getConstant(1, MVT::i8));
14896 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14897 const X86TargetLowering *XTLI) {
14898 SDValue Op0 = N->getOperand(0);
14899 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14900 // a 32-bit target where SSE doesn't support i64->FP operations.
14901 if (Op0.getOpcode() == ISD::LOAD) {
14902 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14903 EVT VT = Ld->getValueType(0);
14904 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14905 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14906 !XTLI->getSubtarget()->is64Bit() &&
14907 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14908 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14909 Ld->getChain(), Op0, DAG);
14910 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14917 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14918 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14919 X86TargetLowering::DAGCombinerInfo &DCI) {
14920 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14921 // the result is either zero or one (depending on the input carry bit).
14922 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14923 if (X86::isZeroNode(N->getOperand(0)) &&
14924 X86::isZeroNode(N->getOperand(1)) &&
14925 // We don't have a good way to replace an EFLAGS use, so only do this when
14927 SDValue(N, 1).use_empty()) {
14928 DebugLoc DL = N->getDebugLoc();
14929 EVT VT = N->getValueType(0);
14930 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14931 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14932 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14933 DAG.getConstant(X86::COND_B,MVT::i8),
14935 DAG.getConstant(1, VT));
14936 return DCI.CombineTo(N, Res1, CarryOut);
14942 // fold (add Y, (sete X, 0)) -> adc 0, Y
14943 // (add Y, (setne X, 0)) -> sbb -1, Y
14944 // (sub (sete X, 0), Y) -> sbb 0, Y
14945 // (sub (setne X, 0), Y) -> adc -1, Y
14946 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14947 DebugLoc DL = N->getDebugLoc();
14949 // Look through ZExts.
14950 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14951 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14954 SDValue SetCC = Ext.getOperand(0);
14955 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14958 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14959 if (CC != X86::COND_E && CC != X86::COND_NE)
14962 SDValue Cmp = SetCC.getOperand(1);
14963 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14964 !X86::isZeroNode(Cmp.getOperand(1)) ||
14965 !Cmp.getOperand(0).getValueType().isInteger())
14968 SDValue CmpOp0 = Cmp.getOperand(0);
14969 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14970 DAG.getConstant(1, CmpOp0.getValueType()));
14972 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14973 if (CC == X86::COND_NE)
14974 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14975 DL, OtherVal.getValueType(), OtherVal,
14976 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14977 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14978 DL, OtherVal.getValueType(), OtherVal,
14979 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14982 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14983 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14984 const X86Subtarget *Subtarget) {
14985 EVT VT = N->getValueType(0);
14986 SDValue Op0 = N->getOperand(0);
14987 SDValue Op1 = N->getOperand(1);
14989 // Try to synthesize horizontal adds from adds of shuffles.
14990 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14991 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14992 isHorizontalBinOp(Op0, Op1, true))
14993 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14995 return OptimizeConditionalInDecrement(N, DAG);
14998 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14999 const X86Subtarget *Subtarget) {
15000 SDValue Op0 = N->getOperand(0);
15001 SDValue Op1 = N->getOperand(1);
15003 // X86 can't encode an immediate LHS of a sub. See if we can push the
15004 // negation into a preceding instruction.
15005 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15006 // If the RHS of the sub is a XOR with one use and a constant, invert the
15007 // immediate. Then add one to the LHS of the sub so we can turn
15008 // X-Y -> X+~Y+1, saving one register.
15009 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15010 isa<ConstantSDNode>(Op1.getOperand(1))) {
15011 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15012 EVT VT = Op0.getValueType();
15013 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15015 DAG.getConstant(~XorC, VT));
15016 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15017 DAG.getConstant(C->getAPIntValue()+1, VT));
15021 // Try to synthesize horizontal adds from adds of shuffles.
15022 EVT VT = N->getValueType(0);
15023 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15024 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15025 isHorizontalBinOp(Op0, Op1, true))
15026 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15028 return OptimizeConditionalInDecrement(N, DAG);
15031 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15032 DAGCombinerInfo &DCI) const {
15033 SelectionDAG &DAG = DCI.DAG;
15034 switch (N->getOpcode()) {
15036 case ISD::EXTRACT_VECTOR_ELT:
15037 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15039 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15040 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15041 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15042 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15043 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15044 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15047 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15048 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15049 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15050 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15051 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15052 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15053 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15054 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15055 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15057 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15058 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15059 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15060 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15061 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
15062 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15063 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15064 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15065 case X86ISD::SHUFP: // Handle all target specific shuffles
15066 case X86ISD::PALIGN:
15067 case X86ISD::UNPCKH:
15068 case X86ISD::UNPCKL:
15069 case X86ISD::MOVHLPS:
15070 case X86ISD::MOVLHPS:
15071 case X86ISD::PSHUFD:
15072 case X86ISD::PSHUFHW:
15073 case X86ISD::PSHUFLW:
15074 case X86ISD::MOVSS:
15075 case X86ISD::MOVSD:
15076 case X86ISD::VPERMILP:
15077 case X86ISD::VPERM2X128:
15078 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15084 /// isTypeDesirableForOp - Return true if the target has native support for
15085 /// the specified value type and it is 'desirable' to use the type for the
15086 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15087 /// instruction encodings are longer and some i16 instructions are slow.
15088 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15089 if (!isTypeLegal(VT))
15091 if (VT != MVT::i16)
15098 case ISD::SIGN_EXTEND:
15099 case ISD::ZERO_EXTEND:
15100 case ISD::ANY_EXTEND:
15113 /// IsDesirableToPromoteOp - This method query the target whether it is
15114 /// beneficial for dag combiner to promote the specified node. If true, it
15115 /// should return the desired promotion type by reference.
15116 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15117 EVT VT = Op.getValueType();
15118 if (VT != MVT::i16)
15121 bool Promote = false;
15122 bool Commute = false;
15123 switch (Op.getOpcode()) {
15126 LoadSDNode *LD = cast<LoadSDNode>(Op);
15127 // If the non-extending load has a single use and it's not live out, then it
15128 // might be folded.
15129 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15130 Op.hasOneUse()*/) {
15131 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15132 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15133 // The only case where we'd want to promote LOAD (rather then it being
15134 // promoted as an operand is when it's only use is liveout.
15135 if (UI->getOpcode() != ISD::CopyToReg)
15142 case ISD::SIGN_EXTEND:
15143 case ISD::ZERO_EXTEND:
15144 case ISD::ANY_EXTEND:
15149 SDValue N0 = Op.getOperand(0);
15150 // Look out for (store (shl (load), x)).
15151 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15164 SDValue N0 = Op.getOperand(0);
15165 SDValue N1 = Op.getOperand(1);
15166 if (!Commute && MayFoldLoad(N1))
15168 // Avoid disabling potential load folding opportunities.
15169 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15171 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15181 //===----------------------------------------------------------------------===//
15182 // X86 Inline Assembly Support
15183 //===----------------------------------------------------------------------===//
15186 // Helper to match a string separated by whitespace.
15187 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15188 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15190 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15191 StringRef piece(*args[i]);
15192 if (!s.startswith(piece)) // Check if the piece matches.
15195 s = s.substr(piece.size());
15196 StringRef::size_type pos = s.find_first_not_of(" \t");
15197 if (pos == 0) // We matched a prefix.
15205 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15208 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15209 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15211 std::string AsmStr = IA->getAsmString();
15213 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15214 if (!Ty || Ty->getBitWidth() % 16 != 0)
15217 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15218 SmallVector<StringRef, 4> AsmPieces;
15219 SplitString(AsmStr, AsmPieces, ";\n");
15221 switch (AsmPieces.size()) {
15222 default: return false;
15224 // FIXME: this should verify that we are targeting a 486 or better. If not,
15225 // we will turn this bswap into something that will be lowered to logical
15226 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15227 // lower so don't worry about this.
15229 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15230 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15231 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15232 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15233 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15234 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15235 // No need to check constraints, nothing other than the equivalent of
15236 // "=r,0" would be valid here.
15237 return IntrinsicLowering::LowerToByteSwap(CI);
15240 // rorw $$8, ${0:w} --> llvm.bswap.i16
15241 if (CI->getType()->isIntegerTy(16) &&
15242 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15243 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15244 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15246 const std::string &ConstraintsStr = IA->getConstraintString();
15247 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15248 std::sort(AsmPieces.begin(), AsmPieces.end());
15249 if (AsmPieces.size() == 4 &&
15250 AsmPieces[0] == "~{cc}" &&
15251 AsmPieces[1] == "~{dirflag}" &&
15252 AsmPieces[2] == "~{flags}" &&
15253 AsmPieces[3] == "~{fpsr}")
15254 return IntrinsicLowering::LowerToByteSwap(CI);
15258 if (CI->getType()->isIntegerTy(32) &&
15259 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15260 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15261 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15262 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15264 const std::string &ConstraintsStr = IA->getConstraintString();
15265 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15266 std::sort(AsmPieces.begin(), AsmPieces.end());
15267 if (AsmPieces.size() == 4 &&
15268 AsmPieces[0] == "~{cc}" &&
15269 AsmPieces[1] == "~{dirflag}" &&
15270 AsmPieces[2] == "~{flags}" &&
15271 AsmPieces[3] == "~{fpsr}")
15272 return IntrinsicLowering::LowerToByteSwap(CI);
15275 if (CI->getType()->isIntegerTy(64)) {
15276 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15277 if (Constraints.size() >= 2 &&
15278 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15279 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15280 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15281 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15282 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15283 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15284 return IntrinsicLowering::LowerToByteSwap(CI);
15294 /// getConstraintType - Given a constraint letter, return the type of
15295 /// constraint it is for this target.
15296 X86TargetLowering::ConstraintType
15297 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15298 if (Constraint.size() == 1) {
15299 switch (Constraint[0]) {
15310 return C_RegisterClass;
15334 return TargetLowering::getConstraintType(Constraint);
15337 /// Examine constraint type and operand type and determine a weight value.
15338 /// This object must already have been set up with the operand type
15339 /// and the current alternative constraint selected.
15340 TargetLowering::ConstraintWeight
15341 X86TargetLowering::getSingleConstraintMatchWeight(
15342 AsmOperandInfo &info, const char *constraint) const {
15343 ConstraintWeight weight = CW_Invalid;
15344 Value *CallOperandVal = info.CallOperandVal;
15345 // If we don't have a value, we can't do a match,
15346 // but allow it at the lowest weight.
15347 if (CallOperandVal == NULL)
15349 Type *type = CallOperandVal->getType();
15350 // Look at the constraint type.
15351 switch (*constraint) {
15353 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15364 if (CallOperandVal->getType()->isIntegerTy())
15365 weight = CW_SpecificReg;
15370 if (type->isFloatingPointTy())
15371 weight = CW_SpecificReg;
15374 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15375 weight = CW_SpecificReg;
15379 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15380 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15381 weight = CW_Register;
15384 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15385 if (C->getZExtValue() <= 31)
15386 weight = CW_Constant;
15390 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15391 if (C->getZExtValue() <= 63)
15392 weight = CW_Constant;
15396 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15397 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15398 weight = CW_Constant;
15402 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15403 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15404 weight = CW_Constant;
15408 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15409 if (C->getZExtValue() <= 3)
15410 weight = CW_Constant;
15414 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15415 if (C->getZExtValue() <= 0xff)
15416 weight = CW_Constant;
15421 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15422 weight = CW_Constant;
15426 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15427 if ((C->getSExtValue() >= -0x80000000LL) &&
15428 (C->getSExtValue() <= 0x7fffffffLL))
15429 weight = CW_Constant;
15433 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15434 if (C->getZExtValue() <= 0xffffffff)
15435 weight = CW_Constant;
15442 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15443 /// with another that has more specific requirements based on the type of the
15444 /// corresponding operand.
15445 const char *X86TargetLowering::
15446 LowerXConstraint(EVT ConstraintVT) const {
15447 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15448 // 'f' like normal targets.
15449 if (ConstraintVT.isFloatingPoint()) {
15450 if (Subtarget->hasSSE2())
15452 if (Subtarget->hasSSE1())
15456 return TargetLowering::LowerXConstraint(ConstraintVT);
15459 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15460 /// vector. If it is invalid, don't add anything to Ops.
15461 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15462 std::string &Constraint,
15463 std::vector<SDValue>&Ops,
15464 SelectionDAG &DAG) const {
15465 SDValue Result(0, 0);
15467 // Only support length 1 constraints for now.
15468 if (Constraint.length() > 1) return;
15470 char ConstraintLetter = Constraint[0];
15471 switch (ConstraintLetter) {
15474 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15475 if (C->getZExtValue() <= 31) {
15476 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15483 if (C->getZExtValue() <= 63) {
15484 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15491 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15492 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15498 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15499 if (C->getZExtValue() <= 255) {
15500 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15506 // 32-bit signed value
15507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15508 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15509 C->getSExtValue())) {
15510 // Widen to 64 bits here to get it sign extended.
15511 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15514 // FIXME gcc accepts some relocatable values here too, but only in certain
15515 // memory models; it's complicated.
15520 // 32-bit unsigned value
15521 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15522 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15523 C->getZExtValue())) {
15524 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15528 // FIXME gcc accepts some relocatable values here too, but only in certain
15529 // memory models; it's complicated.
15533 // Literal immediates are always ok.
15534 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15535 // Widen to 64 bits here to get it sign extended.
15536 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15540 // In any sort of PIC mode addresses need to be computed at runtime by
15541 // adding in a register or some sort of table lookup. These can't
15542 // be used as immediates.
15543 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15546 // If we are in non-pic codegen mode, we allow the address of a global (with
15547 // an optional displacement) to be used with 'i'.
15548 GlobalAddressSDNode *GA = 0;
15549 int64_t Offset = 0;
15551 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15553 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15554 Offset += GA->getOffset();
15556 } else if (Op.getOpcode() == ISD::ADD) {
15557 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15558 Offset += C->getZExtValue();
15559 Op = Op.getOperand(0);
15562 } else if (Op.getOpcode() == ISD::SUB) {
15563 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15564 Offset += -C->getZExtValue();
15565 Op = Op.getOperand(0);
15570 // Otherwise, this isn't something we can handle, reject it.
15574 const GlobalValue *GV = GA->getGlobal();
15575 // If we require an extra load to get this address, as in PIC mode, we
15576 // can't accept it.
15577 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15578 getTargetMachine())))
15581 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15582 GA->getValueType(0), Offset);
15587 if (Result.getNode()) {
15588 Ops.push_back(Result);
15591 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15594 std::pair<unsigned, const TargetRegisterClass*>
15595 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15597 // First, see if this is a constraint that directly corresponds to an LLVM
15599 if (Constraint.size() == 1) {
15600 // GCC Constraint Letters
15601 switch (Constraint[0]) {
15603 // TODO: Slight differences here in allocation order and leaving
15604 // RIP in the class. Do they matter any more here than they do
15605 // in the normal allocation?
15606 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15607 if (Subtarget->is64Bit()) {
15608 if (VT == MVT::i32 || VT == MVT::f32)
15609 return std::make_pair(0U, X86::GR32RegisterClass);
15610 else if (VT == MVT::i16)
15611 return std::make_pair(0U, X86::GR16RegisterClass);
15612 else if (VT == MVT::i8 || VT == MVT::i1)
15613 return std::make_pair(0U, X86::GR8RegisterClass);
15614 else if (VT == MVT::i64 || VT == MVT::f64)
15615 return std::make_pair(0U, X86::GR64RegisterClass);
15618 // 32-bit fallthrough
15619 case 'Q': // Q_REGS
15620 if (VT == MVT::i32 || VT == MVT::f32)
15621 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15622 else if (VT == MVT::i16)
15623 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15624 else if (VT == MVT::i8 || VT == MVT::i1)
15625 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15626 else if (VT == MVT::i64)
15627 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15629 case 'r': // GENERAL_REGS
15630 case 'l': // INDEX_REGS
15631 if (VT == MVT::i8 || VT == MVT::i1)
15632 return std::make_pair(0U, X86::GR8RegisterClass);
15633 if (VT == MVT::i16)
15634 return std::make_pair(0U, X86::GR16RegisterClass);
15635 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15636 return std::make_pair(0U, X86::GR32RegisterClass);
15637 return std::make_pair(0U, X86::GR64RegisterClass);
15638 case 'R': // LEGACY_REGS
15639 if (VT == MVT::i8 || VT == MVT::i1)
15640 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15641 if (VT == MVT::i16)
15642 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15643 if (VT == MVT::i32 || !Subtarget->is64Bit())
15644 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15645 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15646 case 'f': // FP Stack registers.
15647 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15648 // value to the correct fpstack register class.
15649 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15650 return std::make_pair(0U, X86::RFP32RegisterClass);
15651 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15652 return std::make_pair(0U, X86::RFP64RegisterClass);
15653 return std::make_pair(0U, X86::RFP80RegisterClass);
15654 case 'y': // MMX_REGS if MMX allowed.
15655 if (!Subtarget->hasMMX()) break;
15656 return std::make_pair(0U, X86::VR64RegisterClass);
15657 case 'Y': // SSE_REGS if SSE2 allowed
15658 if (!Subtarget->hasSSE2()) break;
15660 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15661 if (!Subtarget->hasSSE1()) break;
15663 switch (VT.getSimpleVT().SimpleTy) {
15665 // Scalar SSE types.
15668 return std::make_pair(0U, X86::FR32RegisterClass);
15671 return std::make_pair(0U, X86::FR64RegisterClass);
15679 return std::make_pair(0U, X86::VR128RegisterClass);
15687 return std::make_pair(0U, X86::VR256RegisterClass);
15694 // Use the default implementation in TargetLowering to convert the register
15695 // constraint into a member of a register class.
15696 std::pair<unsigned, const TargetRegisterClass*> Res;
15697 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15699 // Not found as a standard register?
15700 if (Res.second == 0) {
15701 // Map st(0) -> st(7) -> ST0
15702 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15703 tolower(Constraint[1]) == 's' &&
15704 tolower(Constraint[2]) == 't' &&
15705 Constraint[3] == '(' &&
15706 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15707 Constraint[5] == ')' &&
15708 Constraint[6] == '}') {
15710 Res.first = X86::ST0+Constraint[4]-'0';
15711 Res.second = X86::RFP80RegisterClass;
15715 // GCC allows "st(0)" to be called just plain "st".
15716 if (StringRef("{st}").equals_lower(Constraint)) {
15717 Res.first = X86::ST0;
15718 Res.second = X86::RFP80RegisterClass;
15723 if (StringRef("{flags}").equals_lower(Constraint)) {
15724 Res.first = X86::EFLAGS;
15725 Res.second = X86::CCRRegisterClass;
15729 // 'A' means EAX + EDX.
15730 if (Constraint == "A") {
15731 Res.first = X86::EAX;
15732 Res.second = X86::GR32_ADRegisterClass;
15738 // Otherwise, check to see if this is a register class of the wrong value
15739 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15740 // turn into {ax},{dx}.
15741 if (Res.second->hasType(VT))
15742 return Res; // Correct type already, nothing to do.
15744 // All of the single-register GCC register classes map their values onto
15745 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15746 // really want an 8-bit or 32-bit register, map to the appropriate register
15747 // class and return the appropriate register.
15748 if (Res.second == X86::GR16RegisterClass) {
15749 if (VT == MVT::i8) {
15750 unsigned DestReg = 0;
15751 switch (Res.first) {
15753 case X86::AX: DestReg = X86::AL; break;
15754 case X86::DX: DestReg = X86::DL; break;
15755 case X86::CX: DestReg = X86::CL; break;
15756 case X86::BX: DestReg = X86::BL; break;
15759 Res.first = DestReg;
15760 Res.second = X86::GR8RegisterClass;
15762 } else if (VT == MVT::i32) {
15763 unsigned DestReg = 0;
15764 switch (Res.first) {
15766 case X86::AX: DestReg = X86::EAX; break;
15767 case X86::DX: DestReg = X86::EDX; break;
15768 case X86::CX: DestReg = X86::ECX; break;
15769 case X86::BX: DestReg = X86::EBX; break;
15770 case X86::SI: DestReg = X86::ESI; break;
15771 case X86::DI: DestReg = X86::EDI; break;
15772 case X86::BP: DestReg = X86::EBP; break;
15773 case X86::SP: DestReg = X86::ESP; break;
15776 Res.first = DestReg;
15777 Res.second = X86::GR32RegisterClass;
15779 } else if (VT == MVT::i64) {
15780 unsigned DestReg = 0;
15781 switch (Res.first) {
15783 case X86::AX: DestReg = X86::RAX; break;
15784 case X86::DX: DestReg = X86::RDX; break;
15785 case X86::CX: DestReg = X86::RCX; break;
15786 case X86::BX: DestReg = X86::RBX; break;
15787 case X86::SI: DestReg = X86::RSI; break;
15788 case X86::DI: DestReg = X86::RDI; break;
15789 case X86::BP: DestReg = X86::RBP; break;
15790 case X86::SP: DestReg = X86::RSP; break;
15793 Res.first = DestReg;
15794 Res.second = X86::GR64RegisterClass;
15797 } else if (Res.second == X86::FR32RegisterClass ||
15798 Res.second == X86::FR64RegisterClass ||
15799 Res.second == X86::VR128RegisterClass) {
15800 // Handle references to XMM physical registers that got mapped into the
15801 // wrong class. This can happen with constraints like {xmm0} where the
15802 // target independent register mapper will just pick the first match it can
15803 // find, ignoring the required type.
15804 if (VT == MVT::f32)
15805 Res.second = X86::FR32RegisterClass;
15806 else if (VT == MVT::f64)
15807 Res.second = X86::FR64RegisterClass;
15808 else if (X86::VR128RegisterClass->hasType(VT))
15809 Res.second = X86::VR128RegisterClass;