1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 for (MVT VT : MVT::integer_valuetypes())
296 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
298 // We don't accept any truncstore of integer registers.
299 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
302 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
303 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
304 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
306 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
308 // SETOEQ and SETUNE require checking two conditions.
309 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
311 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
314 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
316 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
318 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
320 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
322 if (Subtarget->is64Bit()) {
323 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
324 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
325 } else if (!TM.Options.UseSoftFloat) {
326 // We have an algorithm for SSE2->double, and we turn this into a
327 // 64-bit FILD followed by conditional FADD for other targets.
328 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
329 // We have an algorithm for SSE2, and we turn this into a 64-bit
330 // FILD for other targets.
331 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
334 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
336 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
337 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
339 if (!TM.Options.UseSoftFloat) {
340 // SSE has no i16 to fp conversion, only i32
341 if (X86ScalarSSEf32) {
342 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
343 // f32 and f64 cases are Legal, f80 case is not
344 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
354 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
355 // are Legal, f80 is custom lowered.
356 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
359 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
361 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
362 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
364 if (X86ScalarSSEf32) {
365 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
366 // f32 and f64 cases are Legal, f80 case is not
367 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
370 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
373 // Handle FP_TO_UINT by promoting the destination to a larger signed
375 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
377 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
379 if (Subtarget->is64Bit()) {
380 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
381 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
382 } else if (!TM.Options.UseSoftFloat) {
383 // Since AVX is a superset of SSE3, only check for SSE here.
384 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
385 // Expand FP_TO_UINT into a select.
386 // FIXME: We would like to use a Custom expander here eventually to do
387 // the optimal thing for SSE vs. the default expansion in the legalizer.
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
390 // With SSE3 we can use fisttpll to convert to a signed i64; without
391 // SSE, we're stuck with a fistpll.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
395 if (isTargetFTOL()) {
396 // Use the _ftol2 runtime function, which has a pseudo-instruction
397 // to handle its weird calling convention.
398 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
401 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
402 if (!X86ScalarSSEf64) {
403 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
404 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
405 if (Subtarget->is64Bit()) {
406 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
407 // Without SSE, i64->f64 goes through memory.
408 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
412 // Scalar integer divide and remainder are lowered to use operations that
413 // produce two results, to match the available instructions. This exposes
414 // the two-result form to trivial CSE, which is able to combine x/y and x%y
415 // into a single instruction.
417 // Scalar integer multiply-high is also lowered to use two-result
418 // operations, to match the available instructions. However, plain multiply
419 // (low) operations are left as Legal, as there are single-result
420 // instructions for this in x86. Using the two-result multiply instructions
421 // when both high and low results are needed must be arranged by dagcombine.
422 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
424 setOperationAction(ISD::MULHS, VT, Expand);
425 setOperationAction(ISD::MULHU, VT, Expand);
426 setOperationAction(ISD::SDIV, VT, Expand);
427 setOperationAction(ISD::UDIV, VT, Expand);
428 setOperationAction(ISD::SREM, VT, Expand);
429 setOperationAction(ISD::UREM, VT, Expand);
431 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
432 setOperationAction(ISD::ADDC, VT, Custom);
433 setOperationAction(ISD::ADDE, VT, Custom);
434 setOperationAction(ISD::SUBC, VT, Custom);
435 setOperationAction(ISD::SUBE, VT, Custom);
438 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
439 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
440 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
442 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
454 if (Subtarget->is64Bit())
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
459 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f32 , Expand);
461 setOperationAction(ISD::FREM , MVT::f64 , Expand);
462 setOperationAction(ISD::FREM , MVT::f80 , Expand);
463 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
465 // Promote the i8 variants and force them on up to i32 which has a shorter
467 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
468 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
469 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
470 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
471 if (Subtarget->hasBMI()) {
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
473 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
474 if (Subtarget->is64Bit())
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
477 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
478 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
479 if (Subtarget->is64Bit())
480 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
483 if (Subtarget->hasLZCNT()) {
484 // When promoting the i8 variants, force them to i32 for a shorter
486 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
487 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
489 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
492 if (Subtarget->is64Bit())
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
495 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
497 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
507 // Special handling for half-precision floating point conversions.
508 // If we don't have F16C support, then lower half float conversions
509 // into library calls.
510 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
511 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
512 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
515 // There's never any support for operations beyond MVT::f32.
516 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
517 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
519 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
521 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
522 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
523 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
524 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
528 if (Subtarget->hasPOPCNT()) {
529 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
531 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
532 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
534 if (Subtarget->is64Bit())
535 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
538 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
540 if (!Subtarget->hasMOVBE())
541 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
543 // These should be promoted to a larger select which is supported.
544 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
545 // X86 wants to expand cmov itself.
546 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
547 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
562 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
563 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
564 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
565 // support continuation, user-level threading, and etc.. As a result, no
566 // other SjLj exception interfaces are implemented and please don't build
567 // your own exception handling based on them.
568 // LLVM/Clang supports zero-cost DWARF exception handling.
569 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
570 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
573 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
574 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
575 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
577 if (Subtarget->is64Bit())
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
579 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
580 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
581 if (Subtarget->is64Bit()) {
582 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
585 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
586 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
588 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
589 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
590 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
592 if (Subtarget->is64Bit()) {
593 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
594 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
598 if (Subtarget->hasSSE1())
599 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
601 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
603 // Expand certain atomics
604 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
606 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
607 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
608 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
611 if (Subtarget->hasCmpxchg16b()) {
612 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
615 // FIXME - use subtarget debug flags
616 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
617 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
618 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
621 if (Subtarget->is64Bit()) {
622 setExceptionPointerRegister(X86::RAX);
623 setExceptionSelectorRegister(X86::RDX);
625 setExceptionPointerRegister(X86::EAX);
626 setExceptionSelectorRegister(X86::EDX);
628 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
631 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::TRAP, MVT::Other, Legal);
635 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
637 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
638 setOperationAction(ISD::VASTART , MVT::Other, Custom);
639 setOperationAction(ISD::VAEND , MVT::Other, Expand);
640 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
641 // TargetInfo::X86_64ABIBuiltinVaList
642 setOperationAction(ISD::VAARG , MVT::Other, Custom);
643 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
645 // TargetInfo::CharPtrBuiltinVaList
646 setOperationAction(ISD::VAARG , MVT::Other, Expand);
647 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
650 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
651 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
653 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
655 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
656 // f32 and f64 use SSE.
657 // Set up the FP register classes.
658 addRegisterClass(MVT::f32, &X86::FR32RegClass);
659 addRegisterClass(MVT::f64, &X86::FR64RegClass);
661 // Use ANDPD to simulate FABS.
662 setOperationAction(ISD::FABS , MVT::f64, Custom);
663 setOperationAction(ISD::FABS , MVT::f32, Custom);
665 // Use XORP to simulate FNEG.
666 setOperationAction(ISD::FNEG , MVT::f64, Custom);
667 setOperationAction(ISD::FNEG , MVT::f32, Custom);
669 // Use ANDPD and ORPD to simulate FCOPYSIGN.
670 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
671 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
673 // Lower this to FGETSIGNx86 plus an AND.
674 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
675 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
677 // We don't support sin/cos/fmod
678 setOperationAction(ISD::FSIN , MVT::f64, Expand);
679 setOperationAction(ISD::FCOS , MVT::f64, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
681 setOperationAction(ISD::FSIN , MVT::f32, Expand);
682 setOperationAction(ISD::FCOS , MVT::f32, Expand);
683 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
685 // Expand FP immediates into loads from the stack, except for the special
687 addLegalFPImmediate(APFloat(+0.0)); // xorpd
688 addLegalFPImmediate(APFloat(+0.0f)); // xorps
689 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
690 // Use SSE for f32, x87 for f64.
691 // Set up the FP register classes.
692 addRegisterClass(MVT::f32, &X86::FR32RegClass);
693 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
695 // Use ANDPS to simulate FABS.
696 setOperationAction(ISD::FABS , MVT::f32, Custom);
698 // Use XORP to simulate FNEG.
699 setOperationAction(ISD::FNEG , MVT::f32, Custom);
701 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
703 // Use ANDPS and ORPS to simulate FCOPYSIGN.
704 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
705 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
707 // We don't support sin/cos/fmod
708 setOperationAction(ISD::FSIN , MVT::f32, Expand);
709 setOperationAction(ISD::FCOS , MVT::f32, Expand);
710 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
712 // Special cases we handle for FP constants.
713 addLegalFPImmediate(APFloat(+0.0f)); // xorps
714 addLegalFPImmediate(APFloat(+0.0)); // FLD0
715 addLegalFPImmediate(APFloat(+1.0)); // FLD1
716 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
717 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
719 if (!TM.Options.UnsafeFPMath) {
720 setOperationAction(ISD::FSIN , MVT::f64, Expand);
721 setOperationAction(ISD::FCOS , MVT::f64, Expand);
722 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
724 } else if (!TM.Options.UseSoftFloat) {
725 // f32 and f64 in x87.
726 // Set up the FP register classes.
727 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
728 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
730 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
731 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
735 if (!TM.Options.UnsafeFPMath) {
736 setOperationAction(ISD::FSIN , MVT::f64, Expand);
737 setOperationAction(ISD::FSIN , MVT::f32, Expand);
738 setOperationAction(ISD::FCOS , MVT::f64, Expand);
739 setOperationAction(ISD::FCOS , MVT::f32, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
743 addLegalFPImmediate(APFloat(+0.0)); // FLD0
744 addLegalFPImmediate(APFloat(+1.0)); // FLD1
745 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
746 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
747 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
748 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
749 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
750 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
753 // We don't support FMA.
754 setOperationAction(ISD::FMA, MVT::f64, Expand);
755 setOperationAction(ISD::FMA, MVT::f32, Expand);
757 // Long double always uses X87.
758 if (!TM.Options.UseSoftFloat) {
759 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
760 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
761 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
763 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
764 addLegalFPImmediate(TmpFlt); // FLD0
766 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
769 APFloat TmpFlt2(+1.0);
770 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
772 addLegalFPImmediate(TmpFlt2); // FLD1
773 TmpFlt2.changeSign();
774 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
777 if (!TM.Options.UnsafeFPMath) {
778 setOperationAction(ISD::FSIN , MVT::f80, Expand);
779 setOperationAction(ISD::FCOS , MVT::f80, Expand);
780 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
783 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
784 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
785 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
786 setOperationAction(ISD::FRINT, MVT::f80, Expand);
787 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
788 setOperationAction(ISD::FMA, MVT::f80, Expand);
791 // Always use a library call for pow.
792 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
796 setOperationAction(ISD::FLOG, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
802 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
804 // First set operation action for all vector types to either promote
805 // (for widening) or expand (for scalarization). Then we will selectively
806 // turn on ones that can be effectively codegen'd.
807 for (MVT VT : MVT::vector_valuetypes()) {
808 setOperationAction(ISD::ADD , VT, Expand);
809 setOperationAction(ISD::SUB , VT, Expand);
810 setOperationAction(ISD::FADD, VT, Expand);
811 setOperationAction(ISD::FNEG, VT, Expand);
812 setOperationAction(ISD::FSUB, VT, Expand);
813 setOperationAction(ISD::MUL , VT, Expand);
814 setOperationAction(ISD::FMUL, VT, Expand);
815 setOperationAction(ISD::SDIV, VT, Expand);
816 setOperationAction(ISD::UDIV, VT, Expand);
817 setOperationAction(ISD::FDIV, VT, Expand);
818 setOperationAction(ISD::SREM, VT, Expand);
819 setOperationAction(ISD::UREM, VT, Expand);
820 setOperationAction(ISD::LOAD, VT, Expand);
821 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
823 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
824 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
826 setOperationAction(ISD::FABS, VT, Expand);
827 setOperationAction(ISD::FSIN, VT, Expand);
828 setOperationAction(ISD::FSINCOS, VT, Expand);
829 setOperationAction(ISD::FCOS, VT, Expand);
830 setOperationAction(ISD::FSINCOS, VT, Expand);
831 setOperationAction(ISD::FREM, VT, Expand);
832 setOperationAction(ISD::FMA, VT, Expand);
833 setOperationAction(ISD::FPOWI, VT, Expand);
834 setOperationAction(ISD::FSQRT, VT, Expand);
835 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
836 setOperationAction(ISD::FFLOOR, VT, Expand);
837 setOperationAction(ISD::FCEIL, VT, Expand);
838 setOperationAction(ISD::FTRUNC, VT, Expand);
839 setOperationAction(ISD::FRINT, VT, Expand);
840 setOperationAction(ISD::FNEARBYINT, VT, Expand);
841 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
842 setOperationAction(ISD::MULHS, VT, Expand);
843 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
844 setOperationAction(ISD::MULHU, VT, Expand);
845 setOperationAction(ISD::SDIVREM, VT, Expand);
846 setOperationAction(ISD::UDIVREM, VT, Expand);
847 setOperationAction(ISD::FPOW, VT, Expand);
848 setOperationAction(ISD::CTPOP, VT, Expand);
849 setOperationAction(ISD::CTTZ, VT, Expand);
850 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
851 setOperationAction(ISD::CTLZ, VT, Expand);
852 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
853 setOperationAction(ISD::SHL, VT, Expand);
854 setOperationAction(ISD::SRA, VT, Expand);
855 setOperationAction(ISD::SRL, VT, Expand);
856 setOperationAction(ISD::ROTL, VT, Expand);
857 setOperationAction(ISD::ROTR, VT, Expand);
858 setOperationAction(ISD::BSWAP, VT, Expand);
859 setOperationAction(ISD::SETCC, VT, Expand);
860 setOperationAction(ISD::FLOG, VT, Expand);
861 setOperationAction(ISD::FLOG2, VT, Expand);
862 setOperationAction(ISD::FLOG10, VT, Expand);
863 setOperationAction(ISD::FEXP, VT, Expand);
864 setOperationAction(ISD::FEXP2, VT, Expand);
865 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
866 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
867 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
869 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
870 setOperationAction(ISD::TRUNCATE, VT, Expand);
871 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
872 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
873 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
874 setOperationAction(ISD::VSELECT, VT, Expand);
875 setOperationAction(ISD::SELECT_CC, VT, Expand);
876 for (MVT InnerVT : MVT::vector_valuetypes()) {
877 setTruncStoreAction(InnerVT, VT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
890 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
891 // with -msoft-float, disable use of MMX as well.
892 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
893 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
894 // No operations on x86mmx supported, everything uses intrinsics.
897 // MMX-sized vectors (other than x86mmx) are expected to be expanded
898 // into smaller operations.
899 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
900 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
901 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
902 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
903 setOperationAction(ISD::AND, MVT::v8i8, Expand);
904 setOperationAction(ISD::AND, MVT::v4i16, Expand);
905 setOperationAction(ISD::AND, MVT::v2i32, Expand);
906 setOperationAction(ISD::AND, MVT::v1i64, Expand);
907 setOperationAction(ISD::OR, MVT::v8i8, Expand);
908 setOperationAction(ISD::OR, MVT::v4i16, Expand);
909 setOperationAction(ISD::OR, MVT::v2i32, Expand);
910 setOperationAction(ISD::OR, MVT::v1i64, Expand);
911 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
912 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
913 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
914 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
920 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
921 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
922 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
923 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
929 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
930 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
932 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
933 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
934 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
935 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
936 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
937 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
938 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
939 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
940 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
941 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
942 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
943 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
944 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
947 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
948 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
950 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
951 // registers cannot be used even for integer operations.
952 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
953 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
954 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
955 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
957 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
958 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
959 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
960 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
961 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
962 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
963 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
965 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
966 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
967 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
968 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
969 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
970 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
971 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
972 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
973 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
974 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
975 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
976 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
977 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
978 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
981 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
982 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
983 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
986 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
991 // Only provide customized ctpop vector bit twiddling for vector types we
992 // know to perform better than using the popcnt instructions on each vector
993 // element. If popcnt isn't supported, always provide the custom version.
994 if (!Subtarget->hasPOPCNT()) {
995 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
996 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
999 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1000 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1001 MVT VT = (MVT::SimpleValueType)i;
1002 // Do not attempt to custom lower non-power-of-2 vectors
1003 if (!isPowerOf2_32(VT.getVectorNumElements()))
1005 // Do not attempt to custom lower non-128-bit vectors
1006 if (!VT.is128BitVector())
1008 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1009 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1013 // We support custom legalizing of sext and anyext loads for specific
1014 // memory vector types which we can load as a scalar (or sequence of
1015 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1016 // loads these must work with a single scalar load.
1017 for (MVT VT : MVT::integer_vector_valuetypes()) {
1018 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
1019 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
1029 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1030 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1031 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1032 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1033 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1034 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1036 if (Subtarget->is64Bit()) {
1037 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1038 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1042 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1043 MVT VT = (MVT::SimpleValueType)i;
1045 // Do not attempt to promote non-128-bit vectors
1046 if (!VT.is128BitVector())
1049 setOperationAction(ISD::AND, VT, Promote);
1050 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1051 setOperationAction(ISD::OR, VT, Promote);
1052 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1053 setOperationAction(ISD::XOR, VT, Promote);
1054 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1055 setOperationAction(ISD::LOAD, VT, Promote);
1056 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1057 setOperationAction(ISD::SELECT, VT, Promote);
1058 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 // Custom lower v2i64 and v2f64 selects.
1062 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1064 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1067 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1068 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1070 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1071 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1072 // As there is no 64-bit GPR available, we need build a special custom
1073 // sequence to convert from v2i32 to v2f32.
1074 if (!Subtarget->is64Bit())
1075 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1077 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1078 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1080 for (MVT VT : MVT::fp_vector_valuetypes())
1081 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
1083 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1084 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1088 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1089 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1090 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1091 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1092 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1093 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1095 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1096 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1097 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1098 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1100 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1101 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1106 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1111 // FIXME: Do we need to handle scalar-to-vector here?
1112 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1114 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1115 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1119 // There is no BLENDI for byte vectors. We don't need to custom lower
1120 // some vselects for now.
1121 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1123 // SSE41 brings specific instructions for doing vector sign extend even in
1124 // cases where we don't have SRA.
1125 for (MVT VT : MVT::integer_vector_valuetypes()) {
1126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
1131 // i8 and i16 vectors are custom because the source register and source
1132 // source memory operand types are not the same width. f32 vectors are
1133 // custom since the immediate controlling the insert encodes additional
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1145 // FIXME: these should be Legal, but that's only for the case where
1146 // the index is constant. For now custom expand to deal with that.
1147 if (Subtarget->is64Bit()) {
1148 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1153 if (Subtarget->hasSSE2()) {
1154 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1157 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1158 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1160 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1161 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1163 // In the customized shift lowering, the legal cases in AVX2 will be
1165 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1166 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1168 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1169 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1171 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1174 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1175 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1180 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1182 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1184 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1186 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1197 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1199 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1210 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1212 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1213 // even though v8i16 is a legal type.
1214 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1216 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1219 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1220 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1223 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1225 for (MVT VT : MVT::fp_vector_valuetypes())
1226 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1228 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1234 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1235 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1239 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1243 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1244 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1248 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1249 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1253 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1255 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1256 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1258 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1259 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1261 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1262 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1264 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1265 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1269 setOperationAction(ISD::FMA, MVT::f32, Legal);
1270 setOperationAction(ISD::FMA, MVT::f64, Legal);
1273 if (Subtarget->hasInt256()) {
1274 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1275 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1276 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1277 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1279 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1280 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1281 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1282 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1284 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1285 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1286 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1287 // Don't lower v32i8 because there is no 128-bit byte mul
1289 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1290 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1291 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1292 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1294 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1295 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1297 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1298 // when we have a 256bit-wide blend with immediate.
1299 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1301 // Only provide customized ctpop vector bit twiddling for vector types we
1302 // know to perform better than using the popcnt instructions on each
1303 // vector element. If popcnt isn't supported, always provide the custom
1305 if (!Subtarget->hasPOPCNT())
1306 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1308 // Custom CTPOP always performs better on natively supported v8i32
1309 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1311 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1312 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1313 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1314 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1316 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1318 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1319 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1321 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1322 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1323 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1324 // Don't lower v32i8 because there is no 128-bit byte mul
1327 // In the customized shift lowering, the legal cases in AVX2 will be
1329 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1330 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1332 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1333 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1335 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1337 // Custom lower several nodes for 256-bit types.
1338 for (MVT VT : MVT::vector_valuetypes()) {
1339 if (VT.getScalarSizeInBits() >= 32) {
1340 setOperationAction(ISD::MLOAD, VT, Legal);
1341 setOperationAction(ISD::MSTORE, VT, Legal);
1343 // Extract subvector is special because the value type
1344 // (result) is 128-bit but the source is 256-bit wide.
1345 if (VT.is128BitVector()) {
1346 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1348 // Do not attempt to custom lower other non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1353 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1354 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1355 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1356 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1357 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1361 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1362 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1363 MVT VT = (MVT::SimpleValueType)i;
1365 // Do not attempt to promote non-256-bit vectors
1366 if (!VT.is256BitVector())
1369 setOperationAction(ISD::AND, VT, Promote);
1370 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1371 setOperationAction(ISD::OR, VT, Promote);
1372 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1373 setOperationAction(ISD::XOR, VT, Promote);
1374 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1375 setOperationAction(ISD::LOAD, VT, Promote);
1376 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1377 setOperationAction(ISD::SELECT, VT, Promote);
1378 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1382 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1383 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1384 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1385 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1386 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1388 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1389 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1390 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1392 for (MVT VT : MVT::fp_vector_valuetypes())
1393 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1395 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1396 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1397 setOperationAction(ISD::XOR, MVT::i1, Legal);
1398 setOperationAction(ISD::OR, MVT::i1, Legal);
1399 setOperationAction(ISD::AND, MVT::i1, Legal);
1400 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1401 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1402 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1403 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1404 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1406 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1407 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1408 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1409 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1410 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1411 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1413 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1414 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1415 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1416 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1417 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1418 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1419 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1420 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1423 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1426 if (Subtarget->is64Bit()) {
1427 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1428 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1429 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1430 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1432 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1433 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1434 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1435 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1436 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1437 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1438 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1439 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1440 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1441 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1442 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1443 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1444 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1445 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1447 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1448 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1449 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1450 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1451 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1452 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1453 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1454 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1455 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1456 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1458 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1459 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1461 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1462 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1463 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1464 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1465 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1466 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1468 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1469 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1471 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1473 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1474 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1475 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1477 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1478 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1479 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1480 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1481 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1483 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1484 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1486 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1487 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1489 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1491 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1494 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1495 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1497 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1498 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1500 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1501 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1502 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1503 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1504 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1505 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1507 if (Subtarget->hasCDI()) {
1508 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1509 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1512 // Custom lower several nodes.
1513 for (MVT VT : MVT::vector_valuetypes()) {
1514 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1515 // Extract subvector is special because the value type
1516 // (result) is 256/128-bit but the source is 512-bit wide.
1517 if (VT.is128BitVector() || VT.is256BitVector()) {
1518 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1520 if (VT.getVectorElementType() == MVT::i1)
1521 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1523 // Do not attempt to custom lower other non-512-bit vectors
1524 if (!VT.is512BitVector())
1527 if ( EltSize >= 32) {
1528 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1529 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1530 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1531 setOperationAction(ISD::VSELECT, VT, Legal);
1532 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1533 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1534 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1535 setOperationAction(ISD::MLOAD, VT, Legal);
1536 setOperationAction(ISD::MSTORE, VT, Legal);
1539 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1540 MVT VT = (MVT::SimpleValueType)i;
1542 // Do not attempt to promote non-512-bit vectors.
1543 if (!VT.is512BitVector())
1546 setOperationAction(ISD::SELECT, VT, Promote);
1547 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1551 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1552 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1553 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1555 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1556 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1558 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1559 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1560 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1561 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1562 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1563 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1564 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1565 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1566 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1568 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1569 const MVT VT = (MVT::SimpleValueType)i;
1571 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1573 // Do not attempt to promote non-512-bit vectors.
1574 if (!VT.is512BitVector())
1578 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1579 setOperationAction(ISD::VSELECT, VT, Legal);
1584 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1585 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1586 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1588 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1589 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1590 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1592 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1593 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1594 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1595 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1596 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1597 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1600 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1601 // of this type with custom code.
1602 for (MVT VT : MVT::vector_valuetypes())
1603 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
1605 // We want to custom lower some of our intrinsics.
1606 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1607 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1608 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1609 if (!Subtarget->is64Bit())
1610 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1612 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1613 // handle type legalization for these operations here.
1615 // FIXME: We really should do custom legalization for addition and
1616 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1617 // than generic legalization for 64-bit multiplication-with-overflow, though.
1618 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1619 // Add/Sub/Mul with overflow operations are custom lowered.
1621 setOperationAction(ISD::SADDO, VT, Custom);
1622 setOperationAction(ISD::UADDO, VT, Custom);
1623 setOperationAction(ISD::SSUBO, VT, Custom);
1624 setOperationAction(ISD::USUBO, VT, Custom);
1625 setOperationAction(ISD::SMULO, VT, Custom);
1626 setOperationAction(ISD::UMULO, VT, Custom);
1630 if (!Subtarget->is64Bit()) {
1631 // These libcalls are not available in 32-bit.
1632 setLibcallName(RTLIB::SHL_I128, nullptr);
1633 setLibcallName(RTLIB::SRL_I128, nullptr);
1634 setLibcallName(RTLIB::SRA_I128, nullptr);
1637 // Combine sin / cos into one node or libcall if possible.
1638 if (Subtarget->hasSinCos()) {
1639 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1640 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1641 if (Subtarget->isTargetDarwin()) {
1642 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1643 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1644 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1645 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1649 if (Subtarget->isTargetWin64()) {
1650 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1651 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1652 setOperationAction(ISD::SREM, MVT::i128, Custom);
1653 setOperationAction(ISD::UREM, MVT::i128, Custom);
1654 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1655 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1658 // We have target-specific dag combine patterns for the following nodes:
1659 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1660 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1661 setTargetDAGCombine(ISD::VSELECT);
1662 setTargetDAGCombine(ISD::SELECT);
1663 setTargetDAGCombine(ISD::SHL);
1664 setTargetDAGCombine(ISD::SRA);
1665 setTargetDAGCombine(ISD::SRL);
1666 setTargetDAGCombine(ISD::OR);
1667 setTargetDAGCombine(ISD::AND);
1668 setTargetDAGCombine(ISD::ADD);
1669 setTargetDAGCombine(ISD::FADD);
1670 setTargetDAGCombine(ISD::FSUB);
1671 setTargetDAGCombine(ISD::FMA);
1672 setTargetDAGCombine(ISD::SUB);
1673 setTargetDAGCombine(ISD::LOAD);
1674 setTargetDAGCombine(ISD::STORE);
1675 setTargetDAGCombine(ISD::ZERO_EXTEND);
1676 setTargetDAGCombine(ISD::ANY_EXTEND);
1677 setTargetDAGCombine(ISD::SIGN_EXTEND);
1678 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1679 setTargetDAGCombine(ISD::TRUNCATE);
1680 setTargetDAGCombine(ISD::SINT_TO_FP);
1681 setTargetDAGCombine(ISD::SETCC);
1682 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1683 setTargetDAGCombine(ISD::BUILD_VECTOR);
1684 if (Subtarget->is64Bit())
1685 setTargetDAGCombine(ISD::MUL);
1686 setTargetDAGCombine(ISD::XOR);
1688 computeRegisterProperties();
1690 // On Darwin, -Os means optimize for size without hurting performance,
1691 // do not reduce the limit.
1692 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1693 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1694 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1695 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1696 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1697 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1698 setPrefLoopAlignment(4); // 2^4 bytes.
1700 // Predictable cmov don't hurt on atom because it's in-order.
1701 PredictableSelectIsExpensive = !Subtarget->isAtom();
1702 EnableExtLdPromotion = true;
1703 setPrefFunctionAlignment(4); // 2^4 bytes.
1705 verifyIntrinsicTables();
1708 // This has so far only been implemented for 64-bit MachO.
1709 bool X86TargetLowering::useLoadStackGuardNode() const {
1710 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1713 TargetLoweringBase::LegalizeTypeAction
1714 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1715 if (ExperimentalVectorWideningLegalization &&
1716 VT.getVectorNumElements() != 1 &&
1717 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1718 return TypeWidenVector;
1720 return TargetLoweringBase::getPreferredVectorAction(VT);
1723 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1725 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1727 const unsigned NumElts = VT.getVectorNumElements();
1728 const EVT EltVT = VT.getVectorElementType();
1729 if (VT.is512BitVector()) {
1730 if (Subtarget->hasAVX512())
1731 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1732 EltVT == MVT::f32 || EltVT == MVT::f64)
1734 case 8: return MVT::v8i1;
1735 case 16: return MVT::v16i1;
1737 if (Subtarget->hasBWI())
1738 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1740 case 32: return MVT::v32i1;
1741 case 64: return MVT::v64i1;
1745 if (VT.is256BitVector() || VT.is128BitVector()) {
1746 if (Subtarget->hasVLX())
1747 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1748 EltVT == MVT::f32 || EltVT == MVT::f64)
1750 case 2: return MVT::v2i1;
1751 case 4: return MVT::v4i1;
1752 case 8: return MVT::v8i1;
1754 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1755 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1757 case 8: return MVT::v8i1;
1758 case 16: return MVT::v16i1;
1759 case 32: return MVT::v32i1;
1763 return VT.changeVectorElementTypeToInteger();
1766 /// Helper for getByValTypeAlignment to determine
1767 /// the desired ByVal argument alignment.
1768 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1771 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1772 if (VTy->getBitWidth() == 128)
1774 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1775 unsigned EltAlign = 0;
1776 getMaxByValAlign(ATy->getElementType(), EltAlign);
1777 if (EltAlign > MaxAlign)
1778 MaxAlign = EltAlign;
1779 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1780 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1781 unsigned EltAlign = 0;
1782 getMaxByValAlign(STy->getElementType(i), EltAlign);
1783 if (EltAlign > MaxAlign)
1784 MaxAlign = EltAlign;
1791 /// Return the desired alignment for ByVal aggregate
1792 /// function arguments in the caller parameter area. For X86, aggregates
1793 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1794 /// are at 4-byte boundaries.
1795 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1796 if (Subtarget->is64Bit()) {
1797 // Max of 8 and alignment of type.
1798 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1805 if (Subtarget->hasSSE1())
1806 getMaxByValAlign(Ty, Align);
1810 /// Returns the target specific optimal type for load
1811 /// and store operations as a result of memset, memcpy, and memmove
1812 /// lowering. If DstAlign is zero that means it's safe to destination
1813 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1814 /// means there isn't a need to check it against alignment requirement,
1815 /// probably because the source does not need to be loaded. If 'IsMemset' is
1816 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1817 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1818 /// source is constant so it does not need to be loaded.
1819 /// It returns EVT::Other if the type should be determined using generic
1820 /// target-independent logic.
1822 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1823 unsigned DstAlign, unsigned SrcAlign,
1824 bool IsMemset, bool ZeroMemset,
1826 MachineFunction &MF) const {
1827 const Function *F = MF.getFunction();
1828 if ((!IsMemset || ZeroMemset) &&
1829 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1830 Attribute::NoImplicitFloat)) {
1832 (Subtarget->isUnalignedMemAccessFast() ||
1833 ((DstAlign == 0 || DstAlign >= 16) &&
1834 (SrcAlign == 0 || SrcAlign >= 16)))) {
1836 if (Subtarget->hasInt256())
1838 if (Subtarget->hasFp256())
1841 if (Subtarget->hasSSE2())
1843 if (Subtarget->hasSSE1())
1845 } else if (!MemcpyStrSrc && Size >= 8 &&
1846 !Subtarget->is64Bit() &&
1847 Subtarget->hasSSE2()) {
1848 // Do not use f64 to lower memcpy if source is string constant. It's
1849 // better to use i32 to avoid the loads.
1853 if (Subtarget->is64Bit() && Size >= 8)
1858 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1860 return X86ScalarSSEf32;
1861 else if (VT == MVT::f64)
1862 return X86ScalarSSEf64;
1867 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1872 *Fast = Subtarget->isUnalignedMemAccessFast();
1876 /// Return the entry encoding for a jump table in the
1877 /// current function. The returned value is a member of the
1878 /// MachineJumpTableInfo::JTEntryKind enum.
1879 unsigned X86TargetLowering::getJumpTableEncoding() const {
1880 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1882 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1883 Subtarget->isPICStyleGOT())
1884 return MachineJumpTableInfo::EK_Custom32;
1886 // Otherwise, use the normal jump table encoding heuristics.
1887 return TargetLowering::getJumpTableEncoding();
1891 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1892 const MachineBasicBlock *MBB,
1893 unsigned uid,MCContext &Ctx) const{
1894 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1895 Subtarget->isPICStyleGOT());
1896 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1898 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1899 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1902 /// Returns relocation base for the given PIC jumptable.
1903 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1904 SelectionDAG &DAG) const {
1905 if (!Subtarget->is64Bit())
1906 // This doesn't have SDLoc associated with it, but is not really the
1907 // same as a Register.
1908 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1912 /// This returns the relocation base for the given PIC jumptable,
1913 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1914 const MCExpr *X86TargetLowering::
1915 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1916 MCContext &Ctx) const {
1917 // X86-64 uses RIP relative addressing based on the jump table label.
1918 if (Subtarget->isPICStyleRIPRel())
1919 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1921 // Otherwise, the reference is relative to the PIC base.
1922 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1925 // FIXME: Why this routine is here? Move to RegInfo!
1926 std::pair<const TargetRegisterClass*, uint8_t>
1927 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1928 const TargetRegisterClass *RRC = nullptr;
1930 switch (VT.SimpleTy) {
1932 return TargetLowering::findRepresentativeClass(VT);
1933 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1934 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1937 RRC = &X86::VR64RegClass;
1939 case MVT::f32: case MVT::f64:
1940 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1941 case MVT::v4f32: case MVT::v2f64:
1942 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1944 RRC = &X86::VR128RegClass;
1947 return std::make_pair(RRC, Cost);
1950 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1951 unsigned &Offset) const {
1952 if (!Subtarget->isTargetLinux())
1955 if (Subtarget->is64Bit()) {
1956 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1958 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1970 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1971 unsigned DestAS) const {
1972 assert(SrcAS != DestAS && "Expected different address spaces!");
1974 return SrcAS < 256 && DestAS < 256;
1977 //===----------------------------------------------------------------------===//
1978 // Return Value Calling Convention Implementation
1979 //===----------------------------------------------------------------------===//
1981 #include "X86GenCallingConv.inc"
1984 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1985 MachineFunction &MF, bool isVarArg,
1986 const SmallVectorImpl<ISD::OutputArg> &Outs,
1987 LLVMContext &Context) const {
1988 SmallVector<CCValAssign, 16> RVLocs;
1989 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1990 return CCInfo.CheckReturn(Outs, RetCC_X86);
1993 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1994 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1999 X86TargetLowering::LowerReturn(SDValue Chain,
2000 CallingConv::ID CallConv, bool isVarArg,
2001 const SmallVectorImpl<ISD::OutputArg> &Outs,
2002 const SmallVectorImpl<SDValue> &OutVals,
2003 SDLoc dl, SelectionDAG &DAG) const {
2004 MachineFunction &MF = DAG.getMachineFunction();
2005 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2007 SmallVector<CCValAssign, 16> RVLocs;
2008 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2009 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2012 SmallVector<SDValue, 6> RetOps;
2013 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2014 // Operand #1 = Bytes To Pop
2015 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2018 // Copy the result values into the output registers.
2019 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2020 CCValAssign &VA = RVLocs[i];
2021 assert(VA.isRegLoc() && "Can only return in registers!");
2022 SDValue ValToCopy = OutVals[i];
2023 EVT ValVT = ValToCopy.getValueType();
2025 // Promote values to the appropriate types.
2026 if (VA.getLocInfo() == CCValAssign::SExt)
2027 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2028 else if (VA.getLocInfo() == CCValAssign::ZExt)
2029 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2030 else if (VA.getLocInfo() == CCValAssign::AExt)
2031 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2032 else if (VA.getLocInfo() == CCValAssign::BCvt)
2033 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2035 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2036 "Unexpected FP-extend for return value.");
2038 // If this is x86-64, and we disabled SSE, we can't return FP values,
2039 // or SSE or MMX vectors.
2040 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2041 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2042 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2043 report_fatal_error("SSE register return with SSE disabled");
2045 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2046 // llvm-gcc has never done it right and no one has noticed, so this
2047 // should be OK for now.
2048 if (ValVT == MVT::f64 &&
2049 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2050 report_fatal_error("SSE2 register return with SSE2 disabled");
2052 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2053 // the RET instruction and handled by the FP Stackifier.
2054 if (VA.getLocReg() == X86::FP0 ||
2055 VA.getLocReg() == X86::FP1) {
2056 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2057 // change the value to the FP stack register class.
2058 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2059 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2060 RetOps.push_back(ValToCopy);
2061 // Don't emit a copytoreg.
2065 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2066 // which is returned in RAX / RDX.
2067 if (Subtarget->is64Bit()) {
2068 if (ValVT == MVT::x86mmx) {
2069 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2070 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2071 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2073 // If we don't have SSE2 available, convert to v4f32 so the generated
2074 // register is legal.
2075 if (!Subtarget->hasSSE2())
2076 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2081 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2082 Flag = Chain.getValue(1);
2083 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2086 // The x86-64 ABIs require that for returning structs by value we copy
2087 // the sret argument into %rax/%eax (depending on ABI) for the return.
2088 // Win32 requires us to put the sret argument to %eax as well.
2089 // We saved the argument into a virtual register in the entry block,
2090 // so now we copy the value out and into %rax/%eax.
2091 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2092 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2093 MachineFunction &MF = DAG.getMachineFunction();
2094 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2095 unsigned Reg = FuncInfo->getSRetReturnReg();
2097 "SRetReturnReg should have been set in LowerFormalArguments().");
2098 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2101 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2102 X86::RAX : X86::EAX;
2103 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2104 Flag = Chain.getValue(1);
2106 // RAX/EAX now acts like a return value.
2107 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2110 RetOps[0] = Chain; // Update chain.
2112 // Add the flag if we have it.
2114 RetOps.push_back(Flag);
2116 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2119 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2120 if (N->getNumValues() != 1)
2122 if (!N->hasNUsesOfValue(1, 0))
2125 SDValue TCChain = Chain;
2126 SDNode *Copy = *N->use_begin();
2127 if (Copy->getOpcode() == ISD::CopyToReg) {
2128 // If the copy has a glue operand, we conservatively assume it isn't safe to
2129 // perform a tail call.
2130 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2132 TCChain = Copy->getOperand(0);
2133 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2136 bool HasRet = false;
2137 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2139 if (UI->getOpcode() != X86ISD::RET_FLAG)
2141 // If we are returning more than one value, we can definitely
2142 // not make a tail call see PR19530
2143 if (UI->getNumOperands() > 4)
2145 if (UI->getNumOperands() == 4 &&
2146 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2159 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2160 ISD::NodeType ExtendKind) const {
2162 // TODO: Is this also valid on 32-bit?
2163 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2164 ReturnMVT = MVT::i8;
2166 ReturnMVT = MVT::i32;
2168 EVT MinVT = getRegisterType(Context, ReturnMVT);
2169 return VT.bitsLT(MinVT) ? MinVT : VT;
2172 /// Lower the result values of a call into the
2173 /// appropriate copies out of appropriate physical registers.
2176 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2177 CallingConv::ID CallConv, bool isVarArg,
2178 const SmallVectorImpl<ISD::InputArg> &Ins,
2179 SDLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2182 // Assign locations to each value returned by this call.
2183 SmallVector<CCValAssign, 16> RVLocs;
2184 bool Is64Bit = Subtarget->is64Bit();
2185 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2187 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2189 // Copy all of the result registers out of their specified physreg.
2190 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2191 CCValAssign &VA = RVLocs[i];
2192 EVT CopyVT = VA.getValVT();
2194 // If this is x86-64, and we disabled SSE, we can't return FP values
2195 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2196 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2197 report_fatal_error("SSE register return with SSE disabled");
2200 // If we prefer to use the value in xmm registers, copy it out as f80 and
2201 // use a truncate to move it from fp stack reg to xmm reg.
2202 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2203 isScalarFPTypeInSSEReg(VA.getValVT()))
2206 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2207 CopyVT, InFlag).getValue(1);
2208 SDValue Val = Chain.getValue(0);
2210 if (CopyVT != VA.getValVT())
2211 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2212 // This truncation won't change the value.
2213 DAG.getIntPtrConstant(1));
2215 InFlag = Chain.getValue(2);
2216 InVals.push_back(Val);
2222 //===----------------------------------------------------------------------===//
2223 // C & StdCall & Fast Calling Convention implementation
2224 //===----------------------------------------------------------------------===//
2225 // StdCall calling convention seems to be standard for many Windows' API
2226 // routines and around. It differs from C calling convention just a little:
2227 // callee should clean up the stack, not caller. Symbols should be also
2228 // decorated in some fancy way :) It doesn't support any vector arguments.
2229 // For info on fast calling convention see Fast Calling Convention (tail call)
2230 // implementation LowerX86_32FastCCCallTo.
2232 /// CallIsStructReturn - Determines whether a call uses struct return
2234 enum StructReturnType {
2239 static StructReturnType
2240 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2242 return NotStructReturn;
2244 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2245 if (!Flags.isSRet())
2246 return NotStructReturn;
2247 if (Flags.isInReg())
2248 return RegStructReturn;
2249 return StackStructReturn;
2252 /// Determines whether a function uses struct return semantics.
2253 static StructReturnType
2254 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2256 return NotStructReturn;
2258 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2259 if (!Flags.isSRet())
2260 return NotStructReturn;
2261 if (Flags.isInReg())
2262 return RegStructReturn;
2263 return StackStructReturn;
2266 /// Make a copy of an aggregate at address specified by "Src" to address
2267 /// "Dst" with size and alignment information specified by the specific
2268 /// parameter attribute. The copy will be passed as a byval function parameter.
2270 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2271 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2273 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2275 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2276 /*isVolatile*/false, /*AlwaysInline=*/true,
2277 MachinePointerInfo(), MachinePointerInfo());
2280 /// Return true if the calling convention is one that
2281 /// supports tail call optimization.
2282 static bool IsTailCallConvention(CallingConv::ID CC) {
2283 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2284 CC == CallingConv::HiPE);
2287 /// \brief Return true if the calling convention is a C calling convention.
2288 static bool IsCCallConvention(CallingConv::ID CC) {
2289 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2290 CC == CallingConv::X86_64_SysV);
2293 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2294 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2298 CallingConv::ID CalleeCC = CS.getCallingConv();
2299 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2305 /// Return true if the function is being made into
2306 /// a tailcall target by changing its ABI.
2307 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2308 bool GuaranteedTailCallOpt) {
2309 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2313 X86TargetLowering::LowerMemArgument(SDValue Chain,
2314 CallingConv::ID CallConv,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SDLoc dl, SelectionDAG &DAG,
2317 const CCValAssign &VA,
2318 MachineFrameInfo *MFI,
2320 // Create the nodes corresponding to a load from this parameter slot.
2321 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2322 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2323 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2324 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2327 // If value is passed by pointer we have address passed instead of the value
2329 if (VA.getLocInfo() == CCValAssign::Indirect)
2330 ValVT = VA.getLocVT();
2332 ValVT = VA.getValVT();
2334 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2335 // changed with more analysis.
2336 // In case of tail call optimization mark all arguments mutable. Since they
2337 // could be overwritten by lowering of arguments in case of a tail call.
2338 if (Flags.isByVal()) {
2339 unsigned Bytes = Flags.getByValSize();
2340 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2341 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2342 return DAG.getFrameIndex(FI, getPointerTy());
2344 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2345 VA.getLocMemOffset(), isImmutable);
2346 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2347 return DAG.getLoad(ValVT, dl, Chain, FIN,
2348 MachinePointerInfo::getFixedStack(FI),
2349 false, false, false, 0);
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2355 const X86Subtarget *Subtarget) {
2356 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 static const MCPhysReg GPR64ArgRegsWin64[] = {
2360 X86::RCX, X86::RDX, X86::R8, X86::R9
2362 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2365 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2366 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2368 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2371 // FIXME: Get this from tablegen.
2372 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2373 CallingConv::ID CallConv,
2374 const X86Subtarget *Subtarget) {
2375 assert(Subtarget->is64Bit());
2376 if (Subtarget->isCallingConvWin64(CallConv)) {
2377 // The XMM registers which might contain var arg parameters are shadowed
2378 // in their paired GPR. So we only need to save the GPR to their home
2380 // TODO: __vectorcall will change this.
2384 const Function *Fn = MF.getFunction();
2385 bool NoImplicitFloatOps = Fn->getAttributes().
2386 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2387 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2388 "SSE register cannot be used when SSE is disabled!");
2389 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2390 !Subtarget->hasSSE1())
2391 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2395 static const MCPhysReg XMMArgRegs64Bit[] = {
2396 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2397 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2399 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2403 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2404 CallingConv::ID CallConv,
2406 const SmallVectorImpl<ISD::InputArg> &Ins,
2409 SmallVectorImpl<SDValue> &InVals)
2411 MachineFunction &MF = DAG.getMachineFunction();
2412 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2414 const Function* Fn = MF.getFunction();
2415 if (Fn->hasExternalLinkage() &&
2416 Subtarget->isTargetCygMing() &&
2417 Fn->getName() == "main")
2418 FuncInfo->setForceFramePointer(true);
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 bool Is64Bit = Subtarget->is64Bit();
2422 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2424 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2425 "Var args not supported with calling convention fastcc, ghc or hipe");
2427 // Assign locations to all of the incoming arguments.
2428 SmallVector<CCValAssign, 16> ArgLocs;
2429 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2431 // Allocate shadow area for Win64
2433 CCInfo.AllocateStack(32, 8);
2435 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2437 unsigned LastVal = ~0U;
2439 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2440 CCValAssign &VA = ArgLocs[i];
2441 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2443 assert(VA.getValNo() != LastVal &&
2444 "Don't support value assigned to multiple locs yet");
2446 LastVal = VA.getValNo();
2448 if (VA.isRegLoc()) {
2449 EVT RegVT = VA.getLocVT();
2450 const TargetRegisterClass *RC;
2451 if (RegVT == MVT::i32)
2452 RC = &X86::GR32RegClass;
2453 else if (Is64Bit && RegVT == MVT::i64)
2454 RC = &X86::GR64RegClass;
2455 else if (RegVT == MVT::f32)
2456 RC = &X86::FR32RegClass;
2457 else if (RegVT == MVT::f64)
2458 RC = &X86::FR64RegClass;
2459 else if (RegVT.is512BitVector())
2460 RC = &X86::VR512RegClass;
2461 else if (RegVT.is256BitVector())
2462 RC = &X86::VR256RegClass;
2463 else if (RegVT.is128BitVector())
2464 RC = &X86::VR128RegClass;
2465 else if (RegVT == MVT::x86mmx)
2466 RC = &X86::VR64RegClass;
2467 else if (RegVT == MVT::i1)
2468 RC = &X86::VK1RegClass;
2469 else if (RegVT == MVT::v8i1)
2470 RC = &X86::VK8RegClass;
2471 else if (RegVT == MVT::v16i1)
2472 RC = &X86::VK16RegClass;
2473 else if (RegVT == MVT::v32i1)
2474 RC = &X86::VK32RegClass;
2475 else if (RegVT == MVT::v64i1)
2476 RC = &X86::VK64RegClass;
2478 llvm_unreachable("Unknown argument type!");
2480 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2481 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2483 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2484 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2486 if (VA.getLocInfo() == CCValAssign::SExt)
2487 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2488 DAG.getValueType(VA.getValVT()));
2489 else if (VA.getLocInfo() == CCValAssign::ZExt)
2490 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2491 DAG.getValueType(VA.getValVT()));
2492 else if (VA.getLocInfo() == CCValAssign::BCvt)
2493 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2495 if (VA.isExtInLoc()) {
2496 // Handle MMX values passed in XMM regs.
2497 if (RegVT.isVector())
2498 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2500 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2503 assert(VA.isMemLoc());
2504 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2507 // If value is passed via pointer - do a load.
2508 if (VA.getLocInfo() == CCValAssign::Indirect)
2509 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2510 MachinePointerInfo(), false, false, false, 0);
2512 InVals.push_back(ArgValue);
2515 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2516 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2517 // The x86-64 ABIs require that for returning structs by value we copy
2518 // the sret argument into %rax/%eax (depending on ABI) for the return.
2519 // Win32 requires us to put the sret argument to %eax as well.
2520 // Save the argument into a virtual register so that we can access it
2521 // from the return points.
2522 if (Ins[i].Flags.isSRet()) {
2523 unsigned Reg = FuncInfo->getSRetReturnReg();
2525 MVT PtrTy = getPointerTy();
2526 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2527 FuncInfo->setSRetReturnReg(Reg);
2529 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2530 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2536 unsigned StackSize = CCInfo.getNextStackOffset();
2537 // Align stack specially for tail calls.
2538 if (FuncIsMadeTailCallSafe(CallConv,
2539 MF.getTarget().Options.GuaranteedTailCallOpt))
2540 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2542 // If the function takes variable number of arguments, make a frame index for
2543 // the start of the first vararg value... for expansion of llvm.va_start. We
2544 // can skip this if there are no va_start calls.
2545 if (MFI->hasVAStart() &&
2546 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2547 CallConv != CallingConv::X86_ThisCall))) {
2548 FuncInfo->setVarArgsFrameIndex(
2549 MFI->CreateFixedObject(1, StackSize, true));
2552 // Figure out if XMM registers are in use.
2553 assert(!(MF.getTarget().Options.UseSoftFloat &&
2554 Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
2555 Attribute::NoImplicitFloat)) &&
2556 "SSE register cannot be used when SSE is disabled!");
2558 // 64-bit calling conventions support varargs and register parameters, so we
2559 // have to do extra work to spill them in the prologue.
2560 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2561 // Find the first unallocated argument registers.
2562 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2563 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2564 unsigned NumIntRegs =
2565 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2566 unsigned NumXMMRegs =
2567 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2568 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2569 "SSE register cannot be used when SSE is disabled!");
2571 // Gather all the live in physical registers.
2572 SmallVector<SDValue, 6> LiveGPRs;
2573 SmallVector<SDValue, 8> LiveXMMRegs;
2575 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2576 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2578 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2580 if (!ArgXMMs.empty()) {
2581 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2582 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2583 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2584 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2585 LiveXMMRegs.push_back(
2586 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2591 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2592 // Get to the caller-allocated home save location. Add 8 to account
2593 // for the return address.
2594 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2595 FuncInfo->setRegSaveFrameIndex(
2596 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2597 // Fixup to set vararg frame on shadow area (4 x i64).
2599 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2601 // For X86-64, if there are vararg parameters that are passed via
2602 // registers, then we must store them to their spots on the stack so
2603 // they may be loaded by deferencing the result of va_next.
2604 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2605 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2606 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2607 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2610 // Store the integer parameter registers.
2611 SmallVector<SDValue, 8> MemOps;
2612 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2614 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2615 for (SDValue Val : LiveGPRs) {
2616 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2617 DAG.getIntPtrConstant(Offset));
2619 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2620 MachinePointerInfo::getFixedStack(
2621 FuncInfo->getRegSaveFrameIndex(), Offset),
2623 MemOps.push_back(Store);
2627 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2628 // Now store the XMM (fp + vector) parameter registers.
2629 SmallVector<SDValue, 12> SaveXMMOps;
2630 SaveXMMOps.push_back(Chain);
2631 SaveXMMOps.push_back(ALVal);
2632 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2633 FuncInfo->getRegSaveFrameIndex()));
2634 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2635 FuncInfo->getVarArgsFPOffset()));
2636 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2638 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2639 MVT::Other, SaveXMMOps));
2642 if (!MemOps.empty())
2643 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2646 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2647 // Find the largest legal vector type.
2648 MVT VecVT = MVT::Other;
2649 // FIXME: Only some x86_32 calling conventions support AVX512.
2650 if (Subtarget->hasAVX512() &&
2651 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2652 CallConv == CallingConv::Intel_OCL_BI)))
2653 VecVT = MVT::v16f32;
2654 else if (Subtarget->hasAVX())
2656 else if (Subtarget->hasSSE2())
2659 // We forward some GPRs and some vector types.
2660 SmallVector<MVT, 2> RegParmTypes;
2661 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2662 RegParmTypes.push_back(IntVT);
2663 if (VecVT != MVT::Other)
2664 RegParmTypes.push_back(VecVT);
2666 // Compute the set of forwarded registers. The rest are scratch.
2667 SmallVectorImpl<ForwardedRegister> &Forwards =
2668 FuncInfo->getForwardedMustTailRegParms();
2669 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2671 // Conservatively forward AL on x86_64, since it might be used for varargs.
2672 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2673 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2674 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2677 // Copy all forwards from physical to virtual registers.
2678 for (ForwardedRegister &F : Forwards) {
2679 // FIXME: Can we use a less constrained schedule?
2680 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2681 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2682 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2686 // Some CCs need callee pop.
2687 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2688 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2689 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2691 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2692 // If this is an sret function, the return should pop the hidden pointer.
2693 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2694 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2695 argsAreStructReturn(Ins) == StackStructReturn)
2696 FuncInfo->setBytesToPopOnReturn(4);
2700 // RegSaveFrameIndex is X86-64 only.
2701 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2702 if (CallConv == CallingConv::X86_FastCall ||
2703 CallConv == CallingConv::X86_ThisCall)
2704 // fastcc functions can't have varargs.
2705 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2708 FuncInfo->setArgumentStackSize(StackSize);
2714 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2715 SDValue StackPtr, SDValue Arg,
2716 SDLoc dl, SelectionDAG &DAG,
2717 const CCValAssign &VA,
2718 ISD::ArgFlagsTy Flags) const {
2719 unsigned LocMemOffset = VA.getLocMemOffset();
2720 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2721 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2722 if (Flags.isByVal())
2723 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2725 return DAG.getStore(Chain, dl, Arg, PtrOff,
2726 MachinePointerInfo::getStack(LocMemOffset),
2730 /// Emit a load of return address if tail call
2731 /// optimization is performed and it is required.
2733 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2734 SDValue &OutRetAddr, SDValue Chain,
2735 bool IsTailCall, bool Is64Bit,
2736 int FPDiff, SDLoc dl) const {
2737 // Adjust the Return address stack slot.
2738 EVT VT = getPointerTy();
2739 OutRetAddr = getReturnAddressFrameIndex(DAG);
2741 // Load the "old" Return address.
2742 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2743 false, false, false, 0);
2744 return SDValue(OutRetAddr.getNode(), 1);
2747 /// Emit a store of the return address if tail call
2748 /// optimization is performed and it is required (FPDiff!=0).
2749 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2750 SDValue Chain, SDValue RetAddrFrIdx,
2751 EVT PtrVT, unsigned SlotSize,
2752 int FPDiff, SDLoc dl) {
2753 // Store the return address to the appropriate stack slot.
2754 if (!FPDiff) return Chain;
2755 // Calculate the new stack slot for the return address.
2756 int NewReturnAddrFI =
2757 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2759 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2760 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2761 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2767 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2768 SmallVectorImpl<SDValue> &InVals) const {
2769 SelectionDAG &DAG = CLI.DAG;
2771 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2772 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2773 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2774 SDValue Chain = CLI.Chain;
2775 SDValue Callee = CLI.Callee;
2776 CallingConv::ID CallConv = CLI.CallConv;
2777 bool &isTailCall = CLI.IsTailCall;
2778 bool isVarArg = CLI.IsVarArg;
2780 MachineFunction &MF = DAG.getMachineFunction();
2781 bool Is64Bit = Subtarget->is64Bit();
2782 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2783 StructReturnType SR = callIsStructReturn(Outs);
2784 bool IsSibcall = false;
2785 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2787 if (MF.getTarget().Options.DisableTailCalls)
2790 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2792 // Force this to be a tail call. The verifier rules are enough to ensure
2793 // that we can lower this successfully without moving the return address
2796 } else if (isTailCall) {
2797 // Check if it's really possible to do a tail call.
2798 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2799 isVarArg, SR != NotStructReturn,
2800 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2801 Outs, OutVals, Ins, DAG);
2803 // Sibcalls are automatically detected tailcalls which do not require
2805 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2812 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2813 "Var args not supported with calling convention fastcc, ghc or hipe");
2815 // Analyze operands of the call, assigning locations to each operand.
2816 SmallVector<CCValAssign, 16> ArgLocs;
2817 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2819 // Allocate shadow area for Win64
2821 CCInfo.AllocateStack(32, 8);
2823 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2825 // Get a count of how many bytes are to be pushed on the stack.
2826 unsigned NumBytes = CCInfo.getNextStackOffset();
2828 // This is a sibcall. The memory operands are available in caller's
2829 // own caller's stack.
2831 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2832 IsTailCallConvention(CallConv))
2833 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2836 if (isTailCall && !IsSibcall && !IsMustTail) {
2837 // Lower arguments at fp - stackoffset + fpdiff.
2838 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2840 FPDiff = NumBytesCallerPushed - NumBytes;
2842 // Set the delta of movement of the returnaddr stackslot.
2843 // But only set if delta is greater than previous delta.
2844 if (FPDiff < X86Info->getTCReturnAddrDelta())
2845 X86Info->setTCReturnAddrDelta(FPDiff);
2848 unsigned NumBytesToPush = NumBytes;
2849 unsigned NumBytesToPop = NumBytes;
2851 // If we have an inalloca argument, all stack space has already been allocated
2852 // for us and be right at the top of the stack. We don't support multiple
2853 // arguments passed in memory when using inalloca.
2854 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2856 if (!ArgLocs.back().isMemLoc())
2857 report_fatal_error("cannot use inalloca attribute on a register "
2859 if (ArgLocs.back().getLocMemOffset() != 0)
2860 report_fatal_error("any parameter with the inalloca attribute must be "
2861 "the only memory argument");
2865 Chain = DAG.getCALLSEQ_START(
2866 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2868 SDValue RetAddrFrIdx;
2869 // Load return address for tail calls.
2870 if (isTailCall && FPDiff)
2871 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2872 Is64Bit, FPDiff, dl);
2874 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2875 SmallVector<SDValue, 8> MemOpChains;
2878 // Walk the register/memloc assignments, inserting copies/loads. In the case
2879 // of tail call optimization arguments are handle later.
2880 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2881 DAG.getSubtarget().getRegisterInfo());
2882 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2883 // Skip inalloca arguments, they have already been written.
2884 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2885 if (Flags.isInAlloca())
2888 CCValAssign &VA = ArgLocs[i];
2889 EVT RegVT = VA.getLocVT();
2890 SDValue Arg = OutVals[i];
2891 bool isByVal = Flags.isByVal();
2893 // Promote the value if needed.
2894 switch (VA.getLocInfo()) {
2895 default: llvm_unreachable("Unknown loc info!");
2896 case CCValAssign::Full: break;
2897 case CCValAssign::SExt:
2898 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2900 case CCValAssign::ZExt:
2901 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2903 case CCValAssign::AExt:
2904 if (RegVT.is128BitVector()) {
2905 // Special case: passing MMX values in XMM registers.
2906 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2907 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2908 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2910 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2912 case CCValAssign::BCvt:
2913 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2915 case CCValAssign::Indirect: {
2916 // Store the argument.
2917 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2918 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2919 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2920 MachinePointerInfo::getFixedStack(FI),
2927 if (VA.isRegLoc()) {
2928 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2929 if (isVarArg && IsWin64) {
2930 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2931 // shadow reg if callee is a varargs function.
2932 unsigned ShadowReg = 0;
2933 switch (VA.getLocReg()) {
2934 case X86::XMM0: ShadowReg = X86::RCX; break;
2935 case X86::XMM1: ShadowReg = X86::RDX; break;
2936 case X86::XMM2: ShadowReg = X86::R8; break;
2937 case X86::XMM3: ShadowReg = X86::R9; break;
2940 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2942 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2943 assert(VA.isMemLoc());
2944 if (!StackPtr.getNode())
2945 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2947 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2948 dl, DAG, VA, Flags));
2952 if (!MemOpChains.empty())
2953 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2955 if (Subtarget->isPICStyleGOT()) {
2956 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2960 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2962 // If we are tail calling and generating PIC/GOT style code load the
2963 // address of the callee into ECX. The value in ecx is used as target of
2964 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2965 // for tail calls on PIC/GOT architectures. Normally we would just put the
2966 // address of GOT into ebx and then call target@PLT. But for tail calls
2967 // ebx would be restored (since ebx is callee saved) before jumping to the
2970 // Note: The actual moving to ECX is done further down.
2971 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2972 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2973 !G->getGlobal()->hasProtectedVisibility())
2974 Callee = LowerGlobalAddress(Callee, DAG);
2975 else if (isa<ExternalSymbolSDNode>(Callee))
2976 Callee = LowerExternalSymbol(Callee, DAG);
2980 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2981 // From AMD64 ABI document:
2982 // For calls that may call functions that use varargs or stdargs
2983 // (prototype-less calls or calls to functions containing ellipsis (...) in
2984 // the declaration) %al is used as hidden argument to specify the number
2985 // of SSE registers used. The contents of %al do not need to match exactly
2986 // the number of registers, but must be an ubound on the number of SSE
2987 // registers used and is in the range 0 - 8 inclusive.
2989 // Count the number of XMM registers allocated.
2990 static const MCPhysReg XMMArgRegs[] = {
2991 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2992 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2994 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2995 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2996 && "SSE registers cannot be used when SSE is disabled");
2998 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2999 DAG.getConstant(NumXMMRegs, MVT::i8)));
3002 if (isVarArg && IsMustTail) {
3003 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3004 for (const auto &F : Forwards) {
3005 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3006 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3010 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3011 // don't need this because the eligibility check rejects calls that require
3012 // shuffling arguments passed in memory.
3013 if (!IsSibcall && isTailCall) {
3014 // Force all the incoming stack arguments to be loaded from the stack
3015 // before any new outgoing arguments are stored to the stack, because the
3016 // outgoing stack slots may alias the incoming argument stack slots, and
3017 // the alias isn't otherwise explicit. This is slightly more conservative
3018 // than necessary, because it means that each store effectively depends
3019 // on every argument instead of just those arguments it would clobber.
3020 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3022 SmallVector<SDValue, 8> MemOpChains2;
3025 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3026 CCValAssign &VA = ArgLocs[i];
3029 assert(VA.isMemLoc());
3030 SDValue Arg = OutVals[i];
3031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032 // Skip inalloca arguments. They don't require any work.
3033 if (Flags.isInAlloca())
3035 // Create frame index.
3036 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3037 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3038 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3039 FIN = DAG.getFrameIndex(FI, getPointerTy());
3041 if (Flags.isByVal()) {
3042 // Copy relative to framepointer.
3043 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3044 if (!StackPtr.getNode())
3045 StackPtr = DAG.getCopyFromReg(Chain, dl,
3046 RegInfo->getStackRegister(),
3048 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3050 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3054 // Store relative to framepointer.
3055 MemOpChains2.push_back(
3056 DAG.getStore(ArgChain, dl, Arg, FIN,
3057 MachinePointerInfo::getFixedStack(FI),
3062 if (!MemOpChains2.empty())
3063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3065 // Store the return address to the appropriate stack slot.
3066 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3067 getPointerTy(), RegInfo->getSlotSize(),
3071 // Build a sequence of copy-to-reg nodes chained together with token chain
3072 // and flag operands which copy the outgoing args into registers.
3074 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3075 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3076 RegsToPass[i].second, InFlag);
3077 InFlag = Chain.getValue(1);
3080 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3081 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3082 // In the 64-bit large code model, we have to make all calls
3083 // through a register, since the call instruction's 32-bit
3084 // pc-relative offset may not be large enough to hold the whole
3086 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3087 // If the callee is a GlobalAddress node (quite common, every direct call
3088 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3090 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3092 // We should use extra load for direct calls to dllimported functions in
3094 const GlobalValue *GV = G->getGlobal();
3095 if (!GV->hasDLLImportStorageClass()) {
3096 unsigned char OpFlags = 0;
3097 bool ExtraLoad = false;
3098 unsigned WrapperKind = ISD::DELETED_NODE;
3100 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3101 // external symbols most go through the PLT in PIC mode. If the symbol
3102 // has hidden or protected visibility, or if it is static or local, then
3103 // we don't need to use the PLT - we can directly call it.
3104 if (Subtarget->isTargetELF() &&
3105 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3106 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3107 OpFlags = X86II::MO_PLT;
3108 } else if (Subtarget->isPICStyleStubAny() &&
3109 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3110 (!Subtarget->getTargetTriple().isMacOSX() ||
3111 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3112 // PC-relative references to external symbols should go through $stub,
3113 // unless we're building with the leopard linker or later, which
3114 // automatically synthesizes these stubs.
3115 OpFlags = X86II::MO_DARWIN_STUB;
3116 } else if (Subtarget->isPICStyleRIPRel() &&
3117 isa<Function>(GV) &&
3118 cast<Function>(GV)->getAttributes().
3119 hasAttribute(AttributeSet::FunctionIndex,
3120 Attribute::NonLazyBind)) {
3121 // If the function is marked as non-lazy, generate an indirect call
3122 // which loads from the GOT directly. This avoids runtime overhead
3123 // at the cost of eager binding (and one extra byte of encoding).
3124 OpFlags = X86II::MO_GOTPCREL;
3125 WrapperKind = X86ISD::WrapperRIP;
3129 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3130 G->getOffset(), OpFlags);
3132 // Add a wrapper if needed.
3133 if (WrapperKind != ISD::DELETED_NODE)
3134 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3135 // Add extra indirection if needed.
3137 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3138 MachinePointerInfo::getGOT(),
3139 false, false, false, 0);
3141 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3142 unsigned char OpFlags = 0;
3144 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3145 // external symbols should go through the PLT.
3146 if (Subtarget->isTargetELF() &&
3147 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3148 OpFlags = X86II::MO_PLT;
3149 } else if (Subtarget->isPICStyleStubAny() &&
3150 (!Subtarget->getTargetTriple().isMacOSX() ||
3151 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3152 // PC-relative references to external symbols should go through $stub,
3153 // unless we're building with the leopard linker or later, which
3154 // automatically synthesizes these stubs.
3155 OpFlags = X86II::MO_DARWIN_STUB;
3158 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3160 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3161 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3162 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3165 // Returns a chain & a flag for retval copy to use.
3166 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3167 SmallVector<SDValue, 8> Ops;
3169 if (!IsSibcall && isTailCall) {
3170 Chain = DAG.getCALLSEQ_END(Chain,
3171 DAG.getIntPtrConstant(NumBytesToPop, true),
3172 DAG.getIntPtrConstant(0, true), InFlag, dl);
3173 InFlag = Chain.getValue(1);
3176 Ops.push_back(Chain);
3177 Ops.push_back(Callee);
3180 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3182 // Add argument registers to the end of the list so that they are known live
3184 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3185 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3186 RegsToPass[i].second.getValueType()));
3188 // Add a register mask operand representing the call-preserved registers.
3189 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3190 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3191 assert(Mask && "Missing call preserved mask for calling convention");
3192 Ops.push_back(DAG.getRegisterMask(Mask));
3194 if (InFlag.getNode())
3195 Ops.push_back(InFlag);
3199 //// If this is the first return lowered for this function, add the regs
3200 //// to the liveout set for the function.
3201 // This isn't right, although it's probably harmless on x86; liveouts
3202 // should be computed from returns not tail calls. Consider a void
3203 // function making a tail call to a function returning int.
3204 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3207 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3208 InFlag = Chain.getValue(1);
3210 // Create the CALLSEQ_END node.
3211 unsigned NumBytesForCalleeToPop;
3212 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3213 DAG.getTarget().Options.GuaranteedTailCallOpt))
3214 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3215 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3216 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3217 SR == StackStructReturn)
3218 // If this is a call to a struct-return function, the callee
3219 // pops the hidden struct pointer, so we have to push it back.
3220 // This is common for Darwin/X86, Linux & Mingw32 targets.
3221 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3222 NumBytesForCalleeToPop = 4;
3224 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3226 // Returns a flag for retval copy to use.
3228 Chain = DAG.getCALLSEQ_END(Chain,
3229 DAG.getIntPtrConstant(NumBytesToPop, true),
3230 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3233 InFlag = Chain.getValue(1);
3236 // Handle result values, copying them out of physregs into vregs that we
3238 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3239 Ins, dl, DAG, InVals);
3242 //===----------------------------------------------------------------------===//
3243 // Fast Calling Convention (tail call) implementation
3244 //===----------------------------------------------------------------------===//
3246 // Like std call, callee cleans arguments, convention except that ECX is
3247 // reserved for storing the tail called function address. Only 2 registers are
3248 // free for argument passing (inreg). Tail call optimization is performed
3250 // * tailcallopt is enabled
3251 // * caller/callee are fastcc
3252 // On X86_64 architecture with GOT-style position independent code only local
3253 // (within module) calls are supported at the moment.
3254 // To keep the stack aligned according to platform abi the function
3255 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3256 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3257 // If a tail called function callee has more arguments than the caller the
3258 // caller needs to make sure that there is room to move the RETADDR to. This is
3259 // achieved by reserving an area the size of the argument delta right after the
3260 // original RETADDR, but before the saved framepointer or the spilled registers
3261 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3273 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3274 /// for a 16 byte align requirement.
3276 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3277 SelectionDAG& DAG) const {
3278 MachineFunction &MF = DAG.getMachineFunction();
3279 const TargetMachine &TM = MF.getTarget();
3280 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3281 TM.getSubtargetImpl()->getRegisterInfo());
3282 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3283 unsigned StackAlignment = TFI.getStackAlignment();
3284 uint64_t AlignMask = StackAlignment - 1;
3285 int64_t Offset = StackSize;
3286 unsigned SlotSize = RegInfo->getSlotSize();
3287 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3288 // Number smaller than 12 so just add the difference.
3289 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3291 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3292 Offset = ((~AlignMask) & Offset) + StackAlignment +
3293 (StackAlignment-SlotSize);
3298 /// MatchingStackOffset - Return true if the given stack call argument is
3299 /// already available in the same position (relatively) of the caller's
3300 /// incoming argument stack.
3302 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3303 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3304 const X86InstrInfo *TII) {
3305 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3307 if (Arg.getOpcode() == ISD::CopyFromReg) {
3308 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3309 if (!TargetRegisterInfo::isVirtualRegister(VR))
3311 MachineInstr *Def = MRI->getVRegDef(VR);
3314 if (!Flags.isByVal()) {
3315 if (!TII->isLoadFromStackSlot(Def, FI))
3318 unsigned Opcode = Def->getOpcode();
3319 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3320 Def->getOperand(1).isFI()) {
3321 FI = Def->getOperand(1).getIndex();
3322 Bytes = Flags.getByValSize();
3326 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3327 if (Flags.isByVal())
3328 // ByVal argument is passed in as a pointer but it's now being
3329 // dereferenced. e.g.
3330 // define @foo(%struct.X* %A) {
3331 // tail call @bar(%struct.X* byval %A)
3334 SDValue Ptr = Ld->getBasePtr();
3335 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3338 FI = FINode->getIndex();
3339 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3340 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3341 FI = FINode->getIndex();
3342 Bytes = Flags.getByValSize();
3346 assert(FI != INT_MAX);
3347 if (!MFI->isFixedObjectIndex(FI))
3349 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3352 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3353 /// for tail call optimization. Targets which want to do tail call
3354 /// optimization should implement this function.
3356 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3357 CallingConv::ID CalleeCC,
3359 bool isCalleeStructRet,
3360 bool isCallerStructRet,
3362 const SmallVectorImpl<ISD::OutputArg> &Outs,
3363 const SmallVectorImpl<SDValue> &OutVals,
3364 const SmallVectorImpl<ISD::InputArg> &Ins,
3365 SelectionDAG &DAG) const {
3366 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3369 // If -tailcallopt is specified, make fastcc functions tail-callable.
3370 const MachineFunction &MF = DAG.getMachineFunction();
3371 const Function *CallerF = MF.getFunction();
3373 // If the function return type is x86_fp80 and the callee return type is not,
3374 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3375 // perform a tailcall optimization here.
3376 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3379 CallingConv::ID CallerCC = CallerF->getCallingConv();
3380 bool CCMatch = CallerCC == CalleeCC;
3381 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3382 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3384 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3385 if (IsTailCallConvention(CalleeCC) && CCMatch)
3390 // Look for obvious safe cases to perform tail call optimization that do not
3391 // require ABI changes. This is what gcc calls sibcall.
3393 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3394 // emit a special epilogue.
3395 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3396 DAG.getSubtarget().getRegisterInfo());
3397 if (RegInfo->needsStackRealignment(MF))
3400 // Also avoid sibcall optimization if either caller or callee uses struct
3401 // return semantics.
3402 if (isCalleeStructRet || isCallerStructRet)
3405 // An stdcall/thiscall caller is expected to clean up its arguments; the
3406 // callee isn't going to do that.
3407 // FIXME: this is more restrictive than needed. We could produce a tailcall
3408 // when the stack adjustment matches. For example, with a thiscall that takes
3409 // only one argument.
3410 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3411 CallerCC == CallingConv::X86_ThisCall))
3414 // Do not sibcall optimize vararg calls unless all arguments are passed via
3416 if (isVarArg && !Outs.empty()) {
3418 // Optimizing for varargs on Win64 is unlikely to be safe without
3419 // additional testing.
3420 if (IsCalleeWin64 || IsCallerWin64)
3423 SmallVector<CCValAssign, 16> ArgLocs;
3424 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3427 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3428 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3429 if (!ArgLocs[i].isRegLoc())
3433 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3434 // stack. Therefore, if it's not used by the call it is not safe to optimize
3435 // this into a sibcall.
3436 bool Unused = false;
3437 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3444 SmallVector<CCValAssign, 16> RVLocs;
3445 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3447 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3448 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3449 CCValAssign &VA = RVLocs[i];
3450 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3455 // If the calling conventions do not match, then we'd better make sure the
3456 // results are returned in the same way as what the caller expects.
3458 SmallVector<CCValAssign, 16> RVLocs1;
3459 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3461 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3463 SmallVector<CCValAssign, 16> RVLocs2;
3464 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3466 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3468 if (RVLocs1.size() != RVLocs2.size())
3470 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3471 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3473 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3475 if (RVLocs1[i].isRegLoc()) {
3476 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3479 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3485 // If the callee takes no arguments then go on to check the results of the
3487 if (!Outs.empty()) {
3488 // Check if stack adjustment is needed. For now, do not do this if any
3489 // argument is passed on the stack.
3490 SmallVector<CCValAssign, 16> ArgLocs;
3491 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3494 // Allocate shadow area for Win64
3496 CCInfo.AllocateStack(32, 8);
3498 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3499 if (CCInfo.getNextStackOffset()) {
3500 MachineFunction &MF = DAG.getMachineFunction();
3501 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3504 // Check if the arguments are already laid out in the right way as
3505 // the caller's fixed stack objects.
3506 MachineFrameInfo *MFI = MF.getFrameInfo();
3507 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3508 const X86InstrInfo *TII =
3509 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3510 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3511 CCValAssign &VA = ArgLocs[i];
3512 SDValue Arg = OutVals[i];
3513 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3514 if (VA.getLocInfo() == CCValAssign::Indirect)
3516 if (!VA.isRegLoc()) {
3517 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3524 // If the tailcall address may be in a register, then make sure it's
3525 // possible to register allocate for it. In 32-bit, the call address can
3526 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3527 // callee-saved registers are restored. These happen to be the same
3528 // registers used to pass 'inreg' arguments so watch out for those.
3529 if (!Subtarget->is64Bit() &&
3530 ((!isa<GlobalAddressSDNode>(Callee) &&
3531 !isa<ExternalSymbolSDNode>(Callee)) ||
3532 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3533 unsigned NumInRegs = 0;
3534 // In PIC we need an extra register to formulate the address computation
3536 unsigned MaxInRegs =
3537 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3539 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3540 CCValAssign &VA = ArgLocs[i];
3543 unsigned Reg = VA.getLocReg();
3546 case X86::EAX: case X86::EDX: case X86::ECX:
3547 if (++NumInRegs == MaxInRegs)
3559 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3560 const TargetLibraryInfo *libInfo) const {
3561 return X86::createFastISel(funcInfo, libInfo);
3564 //===----------------------------------------------------------------------===//
3565 // Other Lowering Hooks
3566 //===----------------------------------------------------------------------===//
3568 static bool MayFoldLoad(SDValue Op) {
3569 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3572 static bool MayFoldIntoStore(SDValue Op) {
3573 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3576 static bool isTargetShuffle(unsigned Opcode) {
3578 default: return false;
3579 case X86ISD::BLENDI:
3580 case X86ISD::PSHUFB:
3581 case X86ISD::PSHUFD:
3582 case X86ISD::PSHUFHW:
3583 case X86ISD::PSHUFLW:
3585 case X86ISD::PALIGNR:
3586 case X86ISD::MOVLHPS:
3587 case X86ISD::MOVLHPD:
3588 case X86ISD::MOVHLPS:
3589 case X86ISD::MOVLPS:
3590 case X86ISD::MOVLPD:
3591 case X86ISD::MOVSHDUP:
3592 case X86ISD::MOVSLDUP:
3593 case X86ISD::MOVDDUP:
3596 case X86ISD::UNPCKL:
3597 case X86ISD::UNPCKH:
3598 case X86ISD::VPERMILPI:
3599 case X86ISD::VPERM2X128:
3600 case X86ISD::VPERMI:
3605 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3606 SDValue V1, SelectionDAG &DAG) {
3608 default: llvm_unreachable("Unknown x86 shuffle node");
3609 case X86ISD::MOVSHDUP:
3610 case X86ISD::MOVSLDUP:
3611 case X86ISD::MOVDDUP:
3612 return DAG.getNode(Opc, dl, VT, V1);
3616 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3617 SDValue V1, unsigned TargetMask,
3618 SelectionDAG &DAG) {
3620 default: llvm_unreachable("Unknown x86 shuffle node");
3621 case X86ISD::PSHUFD:
3622 case X86ISD::PSHUFHW:
3623 case X86ISD::PSHUFLW:
3624 case X86ISD::VPERMILPI:
3625 case X86ISD::VPERMI:
3626 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3630 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3631 SDValue V1, SDValue V2, unsigned TargetMask,
3632 SelectionDAG &DAG) {
3634 default: llvm_unreachable("Unknown x86 shuffle node");
3635 case X86ISD::PALIGNR:
3636 case X86ISD::VALIGN:
3638 case X86ISD::VPERM2X128:
3639 return DAG.getNode(Opc, dl, VT, V1, V2,
3640 DAG.getConstant(TargetMask, MVT::i8));
3644 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3645 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3647 default: llvm_unreachable("Unknown x86 shuffle node");
3648 case X86ISD::MOVLHPS:
3649 case X86ISD::MOVLHPD:
3650 case X86ISD::MOVHLPS:
3651 case X86ISD::MOVLPS:
3652 case X86ISD::MOVLPD:
3655 case X86ISD::UNPCKL:
3656 case X86ISD::UNPCKH:
3657 return DAG.getNode(Opc, dl, VT, V1, V2);
3661 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3662 MachineFunction &MF = DAG.getMachineFunction();
3663 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3664 DAG.getSubtarget().getRegisterInfo());
3665 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3666 int ReturnAddrIndex = FuncInfo->getRAIndex();
3668 if (ReturnAddrIndex == 0) {
3669 // Set up a frame object for the return address.
3670 unsigned SlotSize = RegInfo->getSlotSize();
3671 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3674 FuncInfo->setRAIndex(ReturnAddrIndex);
3677 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3680 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3681 bool hasSymbolicDisplacement) {
3682 // Offset should fit into 32 bit immediate field.
3683 if (!isInt<32>(Offset))
3686 // If we don't have a symbolic displacement - we don't have any extra
3688 if (!hasSymbolicDisplacement)
3691 // FIXME: Some tweaks might be needed for medium code model.
3692 if (M != CodeModel::Small && M != CodeModel::Kernel)
3695 // For small code model we assume that latest object is 16MB before end of 31
3696 // bits boundary. We may also accept pretty large negative constants knowing
3697 // that all objects are in the positive half of address space.
3698 if (M == CodeModel::Small && Offset < 16*1024*1024)
3701 // For kernel code model we know that all object resist in the negative half
3702 // of 32bits address space. We may not accept negative offsets, since they may
3703 // be just off and we may accept pretty large positive ones.
3704 if (M == CodeModel::Kernel && Offset >= 0)
3710 /// isCalleePop - Determines whether the callee is required to pop its
3711 /// own arguments. Callee pop is necessary to support tail calls.
3712 bool X86::isCalleePop(CallingConv::ID CallingConv,
3713 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3714 switch (CallingConv) {
3717 case CallingConv::X86_StdCall:
3718 case CallingConv::X86_FastCall:
3719 case CallingConv::X86_ThisCall:
3721 case CallingConv::Fast:
3722 case CallingConv::GHC:
3723 case CallingConv::HiPE:
3730 /// \brief Return true if the condition is an unsigned comparison operation.
3731 static bool isX86CCUnsigned(unsigned X86CC) {
3733 default: llvm_unreachable("Invalid integer condition!");
3734 case X86::COND_E: return true;
3735 case X86::COND_G: return false;
3736 case X86::COND_GE: return false;
3737 case X86::COND_L: return false;
3738 case X86::COND_LE: return false;
3739 case X86::COND_NE: return true;
3740 case X86::COND_B: return true;
3741 case X86::COND_A: return true;
3742 case X86::COND_BE: return true;
3743 case X86::COND_AE: return true;
3745 llvm_unreachable("covered switch fell through?!");
3748 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3749 /// specific condition code, returning the condition code and the LHS/RHS of the
3750 /// comparison to make.
3751 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3752 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3754 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3755 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3756 // X > -1 -> X == 0, jump !sign.
3757 RHS = DAG.getConstant(0, RHS.getValueType());
3758 return X86::COND_NS;
3760 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3761 // X < 0 -> X == 0, jump on sign.
3764 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3766 RHS = DAG.getConstant(0, RHS.getValueType());
3767 return X86::COND_LE;
3771 switch (SetCCOpcode) {
3772 default: llvm_unreachable("Invalid integer condition!");
3773 case ISD::SETEQ: return X86::COND_E;
3774 case ISD::SETGT: return X86::COND_G;
3775 case ISD::SETGE: return X86::COND_GE;
3776 case ISD::SETLT: return X86::COND_L;
3777 case ISD::SETLE: return X86::COND_LE;
3778 case ISD::SETNE: return X86::COND_NE;
3779 case ISD::SETULT: return X86::COND_B;
3780 case ISD::SETUGT: return X86::COND_A;
3781 case ISD::SETULE: return X86::COND_BE;
3782 case ISD::SETUGE: return X86::COND_AE;
3786 // First determine if it is required or is profitable to flip the operands.
3788 // If LHS is a foldable load, but RHS is not, flip the condition.
3789 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3790 !ISD::isNON_EXTLoad(RHS.getNode())) {
3791 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3792 std::swap(LHS, RHS);
3795 switch (SetCCOpcode) {
3801 std::swap(LHS, RHS);
3805 // On a floating point condition, the flags are set as follows:
3807 // 0 | 0 | 0 | X > Y
3808 // 0 | 0 | 1 | X < Y
3809 // 1 | 0 | 0 | X == Y
3810 // 1 | 1 | 1 | unordered
3811 switch (SetCCOpcode) {
3812 default: llvm_unreachable("Condcode should be pre-legalized away");
3814 case ISD::SETEQ: return X86::COND_E;
3815 case ISD::SETOLT: // flipped
3817 case ISD::SETGT: return X86::COND_A;
3818 case ISD::SETOLE: // flipped
3820 case ISD::SETGE: return X86::COND_AE;
3821 case ISD::SETUGT: // flipped
3823 case ISD::SETLT: return X86::COND_B;
3824 case ISD::SETUGE: // flipped
3826 case ISD::SETLE: return X86::COND_BE;
3828 case ISD::SETNE: return X86::COND_NE;
3829 case ISD::SETUO: return X86::COND_P;
3830 case ISD::SETO: return X86::COND_NP;
3832 case ISD::SETUNE: return X86::COND_INVALID;
3836 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3837 /// code. Current x86 isa includes the following FP cmov instructions:
3838 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3839 static bool hasFPCMov(unsigned X86CC) {
3855 /// isFPImmLegal - Returns true if the target can instruction select the
3856 /// specified FP immediate natively. If false, the legalizer will
3857 /// materialize the FP immediate as a load from a constant pool.
3858 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3859 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3860 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3866 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3867 ISD::LoadExtType ExtTy,
3869 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3870 // relocation target a movq or addq instruction: don't let the load shrink.
3871 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3872 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3873 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3874 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3878 /// \brief Returns true if it is beneficial to convert a load of a constant
3879 /// to just the constant itself.
3880 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3882 assert(Ty->isIntegerTy());
3884 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3885 if (BitSize == 0 || BitSize > 64)
3890 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3891 unsigned Index) const {
3892 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3895 return (Index == 0 || Index == ResVT.getVectorNumElements());
3898 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3899 // Speculate cttz only if we can directly use TZCNT.
3900 return Subtarget->hasBMI();
3903 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3904 // Speculate ctlz only if we can directly use LZCNT.
3905 return Subtarget->hasLZCNT();
3908 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3909 /// the specified range (L, H].
3910 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3911 return (Val < 0) || (Val >= Low && Val < Hi);
3914 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3915 /// specified value.
3916 static bool isUndefOrEqual(int Val, int CmpVal) {
3917 return (Val < 0 || Val == CmpVal);
3920 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3921 /// from position Pos and ending in Pos+Size, falls within the specified
3922 /// sequential range (Low, Low+Size]. or is undef.
3923 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3924 unsigned Pos, unsigned Size, int Low) {
3925 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3926 if (!isUndefOrEqual(Mask[i], Low))
3931 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3932 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3933 /// operand - by default will match for first operand.
3934 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3935 bool TestSecondOperand = false) {
3936 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3937 VT != MVT::v2f64 && VT != MVT::v2i64)
3940 unsigned NumElems = VT.getVectorNumElements();
3941 unsigned Lo = TestSecondOperand ? NumElems : 0;
3942 unsigned Hi = Lo + NumElems;
3944 for (unsigned i = 0; i < NumElems; ++i)
3945 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3951 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3952 /// is suitable for input to PSHUFHW.
3953 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3954 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3957 // Lower quadword copied in order or undef.
3958 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3961 // Upper quadword shuffled.
3962 for (unsigned i = 4; i != 8; ++i)
3963 if (!isUndefOrInRange(Mask[i], 4, 8))
3966 if (VT == MVT::v16i16) {
3967 // Lower quadword copied in order or undef.
3968 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3971 // Upper quadword shuffled.
3972 for (unsigned i = 12; i != 16; ++i)
3973 if (!isUndefOrInRange(Mask[i], 12, 16))
3980 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3981 /// is suitable for input to PSHUFLW.
3982 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3983 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3986 // Upper quadword copied in order.
3987 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3990 // Lower quadword shuffled.
3991 for (unsigned i = 0; i != 4; ++i)
3992 if (!isUndefOrInRange(Mask[i], 0, 4))
3995 if (VT == MVT::v16i16) {
3996 // Upper quadword copied in order.
3997 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
4000 // Lower quadword shuffled.
4001 for (unsigned i = 8; i != 12; ++i)
4002 if (!isUndefOrInRange(Mask[i], 8, 12))
4009 /// \brief Return true if the mask specifies a shuffle of elements that is
4010 /// suitable for input to intralane (palignr) or interlane (valign) vector
4012 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
4013 unsigned NumElts = VT.getVectorNumElements();
4014 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
4015 unsigned NumLaneElts = NumElts/NumLanes;
4017 // Do not handle 64-bit element shuffles with palignr.
4018 if (NumLaneElts == 2)
4021 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4023 for (i = 0; i != NumLaneElts; ++i) {
4028 // Lane is all undef, go to next lane
4029 if (i == NumLaneElts)
4032 int Start = Mask[i+l];
4034 // Make sure its in this lane in one of the sources
4035 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4036 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4039 // If not lane 0, then we must match lane 0
4040 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4043 // Correct second source to be contiguous with first source
4044 if (Start >= (int)NumElts)
4045 Start -= NumElts - NumLaneElts;
4047 // Make sure we're shifting in the right direction.
4048 if (Start <= (int)(i+l))
4053 // Check the rest of the elements to see if they are consecutive.
4054 for (++i; i != NumLaneElts; ++i) {
4055 int Idx = Mask[i+l];
4057 // Make sure its in this lane
4058 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4059 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4062 // If not lane 0, then we must match lane 0
4063 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4066 if (Idx >= (int)NumElts)
4067 Idx -= NumElts - NumLaneElts;
4069 if (!isUndefOrEqual(Idx, Start+i))
4078 /// \brief Return true if the node specifies a shuffle of elements that is
4079 /// suitable for input to PALIGNR.
4080 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4081 const X86Subtarget *Subtarget) {
4082 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4083 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4084 VT.is512BitVector())
4085 // FIXME: Add AVX512BW.
4088 return isAlignrMask(Mask, VT, false);
4091 /// \brief Return true if the node specifies a shuffle of elements that is
4092 /// suitable for input to VALIGN.
4093 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4094 const X86Subtarget *Subtarget) {
4095 // FIXME: Add AVX512VL.
4096 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4098 return isAlignrMask(Mask, VT, true);
4101 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4102 /// the two vector operands have swapped position.
4103 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4104 unsigned NumElems) {
4105 for (unsigned i = 0; i != NumElems; ++i) {
4109 else if (idx < (int)NumElems)
4110 Mask[i] = idx + NumElems;
4112 Mask[i] = idx - NumElems;
4116 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4117 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4118 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4119 /// reverse of what x86 shuffles want.
4120 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4122 unsigned NumElems = VT.getVectorNumElements();
4123 unsigned NumLanes = VT.getSizeInBits()/128;
4124 unsigned NumLaneElems = NumElems/NumLanes;
4126 if (NumLaneElems != 2 && NumLaneElems != 4)
4129 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4130 bool symetricMaskRequired =
4131 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4133 // VSHUFPSY divides the resulting vector into 4 chunks.
4134 // The sources are also splitted into 4 chunks, and each destination
4135 // chunk must come from a different source chunk.
4137 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4138 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4140 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4141 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4143 // VSHUFPDY divides the resulting vector into 4 chunks.
4144 // The sources are also splitted into 4 chunks, and each destination
4145 // chunk must come from a different source chunk.
4147 // SRC1 => X3 X2 X1 X0
4148 // SRC2 => Y3 Y2 Y1 Y0
4150 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4152 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4153 unsigned HalfLaneElems = NumLaneElems/2;
4154 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4155 for (unsigned i = 0; i != NumLaneElems; ++i) {
4156 int Idx = Mask[i+l];
4157 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4158 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4160 // For VSHUFPSY, the mask of the second half must be the same as the
4161 // first but with the appropriate offsets. This works in the same way as
4162 // VPERMILPS works with masks.
4163 if (!symetricMaskRequired || Idx < 0)
4165 if (MaskVal[i] < 0) {
4166 MaskVal[i] = Idx - l;
4169 if ((signed)(Idx - l) != MaskVal[i])
4177 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4178 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4179 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4180 if (!VT.is128BitVector())
4183 unsigned NumElems = VT.getVectorNumElements();
4188 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4189 return isUndefOrEqual(Mask[0], 6) &&
4190 isUndefOrEqual(Mask[1], 7) &&
4191 isUndefOrEqual(Mask[2], 2) &&
4192 isUndefOrEqual(Mask[3], 3);
4195 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4196 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4198 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4199 if (!VT.is128BitVector())
4202 unsigned NumElems = VT.getVectorNumElements();
4207 return isUndefOrEqual(Mask[0], 2) &&
4208 isUndefOrEqual(Mask[1], 3) &&
4209 isUndefOrEqual(Mask[2], 2) &&
4210 isUndefOrEqual(Mask[3], 3);
4213 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4214 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4215 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4216 if (!VT.is128BitVector())
4219 unsigned NumElems = VT.getVectorNumElements();
4221 if (NumElems != 2 && NumElems != 4)
4224 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4225 if (!isUndefOrEqual(Mask[i], i + NumElems))
4228 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4229 if (!isUndefOrEqual(Mask[i], i))
4235 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4236 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4237 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4238 if (!VT.is128BitVector())
4241 unsigned NumElems = VT.getVectorNumElements();
4243 if (NumElems != 2 && NumElems != 4)
4246 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4247 if (!isUndefOrEqual(Mask[i], i))
4250 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4251 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4257 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4258 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4259 /// i. e: If all but one element come from the same vector.
4260 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4261 // TODO: Deal with AVX's VINSERTPS
4262 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4265 unsigned CorrectPosV1 = 0;
4266 unsigned CorrectPosV2 = 0;
4267 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4268 if (Mask[i] == -1) {
4276 else if (Mask[i] == i + 4)
4280 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4281 // We have 3 elements (undefs count as elements from any vector) from one
4282 // vector, and one from another.
4289 // Some special combinations that can be optimized.
4292 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4293 SelectionDAG &DAG) {
4294 MVT VT = SVOp->getSimpleValueType(0);
4297 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4300 ArrayRef<int> Mask = SVOp->getMask();
4302 // These are the special masks that may be optimized.
4303 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4304 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4305 bool MatchEvenMask = true;
4306 bool MatchOddMask = true;
4307 for (int i=0; i<8; ++i) {
4308 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4309 MatchEvenMask = false;
4310 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4311 MatchOddMask = false;
4314 if (!MatchEvenMask && !MatchOddMask)
4317 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4319 SDValue Op0 = SVOp->getOperand(0);
4320 SDValue Op1 = SVOp->getOperand(1);
4322 if (MatchEvenMask) {
4323 // Shift the second operand right to 32 bits.
4324 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4325 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4327 // Shift the first operand left to 32 bits.
4328 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4329 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4331 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4332 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4335 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4336 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4337 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4338 bool HasInt256, bool V2IsSplat = false) {
4340 assert(VT.getSizeInBits() >= 128 &&
4341 "Unsupported vector type for unpckl");
4343 unsigned NumElts = VT.getVectorNumElements();
4344 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4345 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4348 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4349 "Unsupported vector type for unpckh");
4351 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4352 unsigned NumLanes = VT.getSizeInBits()/128;
4353 unsigned NumLaneElts = NumElts/NumLanes;
4355 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4356 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4357 int BitI = Mask[l+i];
4358 int BitI1 = Mask[l+i+1];
4359 if (!isUndefOrEqual(BitI, j))
4362 if (!isUndefOrEqual(BitI1, NumElts))
4365 if (!isUndefOrEqual(BitI1, j + NumElts))
4374 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4375 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4376 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4377 bool HasInt256, bool V2IsSplat = false) {
4378 assert(VT.getSizeInBits() >= 128 &&
4379 "Unsupported vector type for unpckh");
4381 unsigned NumElts = VT.getVectorNumElements();
4382 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4383 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4386 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4387 "Unsupported vector type for unpckh");
4389 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4390 unsigned NumLanes = VT.getSizeInBits()/128;
4391 unsigned NumLaneElts = NumElts/NumLanes;
4393 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4394 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4395 int BitI = Mask[l+i];
4396 int BitI1 = Mask[l+i+1];
4397 if (!isUndefOrEqual(BitI, j))
4400 if (isUndefOrEqual(BitI1, NumElts))
4403 if (!isUndefOrEqual(BitI1, j+NumElts))
4411 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4412 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4414 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4415 unsigned NumElts = VT.getVectorNumElements();
4416 bool Is256BitVec = VT.is256BitVector();
4418 if (VT.is512BitVector())
4420 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4421 "Unsupported vector type for unpckh");
4423 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4424 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4427 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4428 // FIXME: Need a better way to get rid of this, there's no latency difference
4429 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4430 // the former later. We should also remove the "_undef" special mask.
4431 if (NumElts == 4 && Is256BitVec)
4434 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4435 // independently on 128-bit lanes.
4436 unsigned NumLanes = VT.getSizeInBits()/128;
4437 unsigned NumLaneElts = NumElts/NumLanes;
4439 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4440 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4441 int BitI = Mask[l+i];
4442 int BitI1 = Mask[l+i+1];
4444 if (!isUndefOrEqual(BitI, j))
4446 if (!isUndefOrEqual(BitI1, j))
4454 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4455 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4457 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4458 unsigned NumElts = VT.getVectorNumElements();
4460 if (VT.is512BitVector())
4463 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4464 "Unsupported vector type for unpckh");
4466 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4467 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4470 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4471 // independently on 128-bit lanes.
4472 unsigned NumLanes = VT.getSizeInBits()/128;
4473 unsigned NumLaneElts = NumElts/NumLanes;
4475 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4476 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4477 int BitI = Mask[l+i];
4478 int BitI1 = Mask[l+i+1];
4479 if (!isUndefOrEqual(BitI, j))
4481 if (!isUndefOrEqual(BitI1, j))
4488 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4489 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4490 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4491 if (!VT.is512BitVector())
4494 unsigned NumElts = VT.getVectorNumElements();
4495 unsigned HalfSize = NumElts/2;
4496 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4497 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4502 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4503 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4511 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4512 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4513 /// MOVSD, and MOVD, i.e. setting the lowest element.
4514 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4515 if (VT.getVectorElementType().getSizeInBits() < 32)
4517 if (!VT.is128BitVector())
4520 unsigned NumElts = VT.getVectorNumElements();
4522 if (!isUndefOrEqual(Mask[0], NumElts))
4525 for (unsigned i = 1; i != NumElts; ++i)
4526 if (!isUndefOrEqual(Mask[i], i))
4532 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4533 /// as permutations between 128-bit chunks or halves. As an example: this
4535 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4536 /// The first half comes from the second half of V1 and the second half from the
4537 /// the second half of V2.
4538 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4539 if (!HasFp256 || !VT.is256BitVector())
4542 // The shuffle result is divided into half A and half B. In total the two
4543 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4544 // B must come from C, D, E or F.
4545 unsigned HalfSize = VT.getVectorNumElements()/2;
4546 bool MatchA = false, MatchB = false;
4548 // Check if A comes from one of C, D, E, F.
4549 for (unsigned Half = 0; Half != 4; ++Half) {
4550 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4556 // Check if B comes from one of C, D, E, F.
4557 for (unsigned Half = 0; Half != 4; ++Half) {
4558 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4564 return MatchA && MatchB;
4567 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4568 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4569 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4570 MVT VT = SVOp->getSimpleValueType(0);
4572 unsigned HalfSize = VT.getVectorNumElements()/2;
4574 unsigned FstHalf = 0, SndHalf = 0;
4575 for (unsigned i = 0; i < HalfSize; ++i) {
4576 if (SVOp->getMaskElt(i) > 0) {
4577 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4581 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4582 if (SVOp->getMaskElt(i) > 0) {
4583 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4588 return (FstHalf | (SndHalf << 4));
4591 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4592 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4593 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4597 unsigned NumElts = VT.getVectorNumElements();
4599 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4600 for (unsigned i = 0; i != NumElts; ++i) {
4603 Imm8 |= Mask[i] << (i*2);
4608 unsigned LaneSize = 4;
4609 SmallVector<int, 4> MaskVal(LaneSize, -1);
4611 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4612 for (unsigned i = 0; i != LaneSize; ++i) {
4613 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4617 if (MaskVal[i] < 0) {
4618 MaskVal[i] = Mask[i+l] - l;
4619 Imm8 |= MaskVal[i] << (i*2);
4622 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4629 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4630 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4631 /// Note that VPERMIL mask matching is different depending whether theunderlying
4632 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4633 /// to the same elements of the low, but to the higher half of the source.
4634 /// In VPERMILPD the two lanes could be shuffled independently of each other
4635 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4636 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4637 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4638 if (VT.getSizeInBits() < 256 || EltSize < 32)
4640 bool symetricMaskRequired = (EltSize == 32);
4641 unsigned NumElts = VT.getVectorNumElements();
4643 unsigned NumLanes = VT.getSizeInBits()/128;
4644 unsigned LaneSize = NumElts/NumLanes;
4645 // 2 or 4 elements in one lane
4647 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4648 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4649 for (unsigned i = 0; i != LaneSize; ++i) {
4650 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4652 if (symetricMaskRequired) {
4653 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4654 ExpectedMaskVal[i] = Mask[i+l] - l;
4657 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4665 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4666 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4667 /// element of vector 2 and the other elements to come from vector 1 in order.
4668 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4669 bool V2IsSplat = false, bool V2IsUndef = false) {
4670 if (!VT.is128BitVector())
4673 unsigned NumOps = VT.getVectorNumElements();
4674 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4677 if (!isUndefOrEqual(Mask[0], 0))
4680 for (unsigned i = 1; i != NumOps; ++i)
4681 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4682 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4683 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4689 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4690 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4691 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4692 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4693 const X86Subtarget *Subtarget) {
4694 if (!Subtarget->hasSSE3())
4697 unsigned NumElems = VT.getVectorNumElements();
4699 if ((VT.is128BitVector() && NumElems != 4) ||
4700 (VT.is256BitVector() && NumElems != 8) ||
4701 (VT.is512BitVector() && NumElems != 16))
4704 // "i+1" is the value the indexed mask element must have
4705 for (unsigned i = 0; i != NumElems; i += 2)
4706 if (!isUndefOrEqual(Mask[i], i+1) ||
4707 !isUndefOrEqual(Mask[i+1], i+1))
4713 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4714 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4715 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4716 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4717 const X86Subtarget *Subtarget) {
4718 if (!Subtarget->hasSSE3())
4721 unsigned NumElems = VT.getVectorNumElements();
4723 if ((VT.is128BitVector() && NumElems != 4) ||
4724 (VT.is256BitVector() && NumElems != 8) ||
4725 (VT.is512BitVector() && NumElems != 16))
4728 // "i" is the value the indexed mask element must have
4729 for (unsigned i = 0; i != NumElems; i += 2)
4730 if (!isUndefOrEqual(Mask[i], i) ||
4731 !isUndefOrEqual(Mask[i+1], i))
4737 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4738 /// specifies a shuffle of elements that is suitable for input to 256-bit
4739 /// version of MOVDDUP.
4740 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4741 if (!HasFp256 || !VT.is256BitVector())
4744 unsigned NumElts = VT.getVectorNumElements();
4748 for (unsigned i = 0; i != NumElts/2; ++i)
4749 if (!isUndefOrEqual(Mask[i], 0))
4751 for (unsigned i = NumElts/2; i != NumElts; ++i)
4752 if (!isUndefOrEqual(Mask[i], NumElts/2))
4757 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4758 /// specifies a shuffle of elements that is suitable for input to 128-bit
4759 /// version of MOVDDUP.
4760 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4761 if (!VT.is128BitVector())
4764 unsigned e = VT.getVectorNumElements() / 2;
4765 for (unsigned i = 0; i != e; ++i)
4766 if (!isUndefOrEqual(Mask[i], i))
4768 for (unsigned i = 0; i != e; ++i)
4769 if (!isUndefOrEqual(Mask[e+i], i))
4774 /// isVEXTRACTIndex - Return true if the specified
4775 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4776 /// suitable for instruction that extract 128 or 256 bit vectors
4777 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4778 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4779 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4782 // The index should be aligned on a vecWidth-bit boundary.
4784 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4786 MVT VT = N->getSimpleValueType(0);
4787 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4788 bool Result = (Index * ElSize) % vecWidth == 0;
4793 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4794 /// operand specifies a subvector insert that is suitable for input to
4795 /// insertion of 128 or 256-bit subvectors
4796 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4797 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4798 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4800 // The index should be aligned on a vecWidth-bit boundary.
4802 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4804 MVT VT = N->getSimpleValueType(0);
4805 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4806 bool Result = (Index * ElSize) % vecWidth == 0;
4811 bool X86::isVINSERT128Index(SDNode *N) {
4812 return isVINSERTIndex(N, 128);
4815 bool X86::isVINSERT256Index(SDNode *N) {
4816 return isVINSERTIndex(N, 256);
4819 bool X86::isVEXTRACT128Index(SDNode *N) {
4820 return isVEXTRACTIndex(N, 128);
4823 bool X86::isVEXTRACT256Index(SDNode *N) {
4824 return isVEXTRACTIndex(N, 256);
4827 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4828 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4829 /// Handles 128-bit and 256-bit.
4830 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4831 MVT VT = N->getSimpleValueType(0);
4833 assert((VT.getSizeInBits() >= 128) &&
4834 "Unsupported vector type for PSHUF/SHUFP");
4836 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4837 // independently on 128-bit lanes.
4838 unsigned NumElts = VT.getVectorNumElements();
4839 unsigned NumLanes = VT.getSizeInBits()/128;
4840 unsigned NumLaneElts = NumElts/NumLanes;
4842 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4843 "Only supports 2, 4 or 8 elements per lane");
4845 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4847 for (unsigned i = 0; i != NumElts; ++i) {
4848 int Elt = N->getMaskElt(i);
4849 if (Elt < 0) continue;
4850 Elt &= NumLaneElts - 1;
4851 unsigned ShAmt = (i << Shift) % 8;
4852 Mask |= Elt << ShAmt;
4858 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4859 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4860 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4861 MVT VT = N->getSimpleValueType(0);
4863 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4864 "Unsupported vector type for PSHUFHW");
4866 unsigned NumElts = VT.getVectorNumElements();
4869 for (unsigned l = 0; l != NumElts; l += 8) {
4870 // 8 nodes per lane, but we only care about the last 4.
4871 for (unsigned i = 0; i < 4; ++i) {
4872 int Elt = N->getMaskElt(l+i+4);
4873 if (Elt < 0) continue;
4874 Elt &= 0x3; // only 2-bits.
4875 Mask |= Elt << (i * 2);
4882 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4883 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4884 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4885 MVT VT = N->getSimpleValueType(0);
4887 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4888 "Unsupported vector type for PSHUFHW");
4890 unsigned NumElts = VT.getVectorNumElements();
4893 for (unsigned l = 0; l != NumElts; l += 8) {
4894 // 8 nodes per lane, but we only care about the first 4.
4895 for (unsigned i = 0; i < 4; ++i) {
4896 int Elt = N->getMaskElt(l+i);
4897 if (Elt < 0) continue;
4898 Elt &= 0x3; // only 2-bits
4899 Mask |= Elt << (i * 2);
4906 /// \brief Return the appropriate immediate to shuffle the specified
4907 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4908 /// VALIGN (if Interlane is true) instructions.
4909 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4911 MVT VT = SVOp->getSimpleValueType(0);
4912 unsigned EltSize = InterLane ? 1 :
4913 VT.getVectorElementType().getSizeInBits() >> 3;
4915 unsigned NumElts = VT.getVectorNumElements();
4916 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4917 unsigned NumLaneElts = NumElts/NumLanes;
4921 for (i = 0; i != NumElts; ++i) {
4922 Val = SVOp->getMaskElt(i);
4926 if (Val >= (int)NumElts)
4927 Val -= NumElts - NumLaneElts;
4929 assert(Val - i > 0 && "PALIGNR imm should be positive");
4930 return (Val - i) * EltSize;
4933 /// \brief Return the appropriate immediate to shuffle the specified
4934 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4935 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4936 return getShuffleAlignrImmediate(SVOp, false);
4939 /// \brief Return the appropriate immediate to shuffle the specified
4940 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4941 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4942 return getShuffleAlignrImmediate(SVOp, true);
4946 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4947 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4948 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4949 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4952 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4954 MVT VecVT = N->getOperand(0).getSimpleValueType();
4955 MVT ElVT = VecVT.getVectorElementType();
4957 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4958 return Index / NumElemsPerChunk;
4961 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4962 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4963 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4964 llvm_unreachable("Illegal insert subvector for VINSERT");
4967 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4969 MVT VecVT = N->getSimpleValueType(0);
4970 MVT ElVT = VecVT.getVectorElementType();
4972 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4973 return Index / NumElemsPerChunk;
4976 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4977 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4978 /// and VINSERTI128 instructions.
4979 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4980 return getExtractVEXTRACTImmediate(N, 128);
4983 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4984 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4985 /// and VINSERTI64x4 instructions.
4986 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4987 return getExtractVEXTRACTImmediate(N, 256);
4990 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4991 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4992 /// and VINSERTI128 instructions.
4993 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4994 return getInsertVINSERTImmediate(N, 128);
4997 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4998 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4999 /// and VINSERTI64x4 instructions.
5000 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
5001 return getInsertVINSERTImmediate(N, 256);
5004 /// isZero - Returns true if Elt is a constant integer zero
5005 static bool isZero(SDValue V) {
5006 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
5007 return C && C->isNullValue();
5010 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
5012 bool X86::isZeroNode(SDValue Elt) {
5015 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
5016 return CFP->getValueAPF().isPosZero();
5020 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5021 /// match movhlps. The lower half elements should come from upper half of
5022 /// V1 (and in order), and the upper half elements should come from the upper
5023 /// half of V2 (and in order).
5024 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5025 if (!VT.is128BitVector())
5027 if (VT.getVectorNumElements() != 4)
5029 for (unsigned i = 0, e = 2; i != e; ++i)
5030 if (!isUndefOrEqual(Mask[i], i+2))
5032 for (unsigned i = 2; i != 4; ++i)
5033 if (!isUndefOrEqual(Mask[i], i+4))
5038 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5039 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5041 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5042 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5044 N = N->getOperand(0).getNode();
5045 if (!ISD::isNON_EXTLoad(N))
5048 *LD = cast<LoadSDNode>(N);
5052 // Test whether the given value is a vector value which will be legalized
5054 static bool WillBeConstantPoolLoad(SDNode *N) {
5055 if (N->getOpcode() != ISD::BUILD_VECTOR)
5058 // Check for any non-constant elements.
5059 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5060 switch (N->getOperand(i).getNode()->getOpcode()) {
5062 case ISD::ConstantFP:
5069 // Vectors of all-zeros and all-ones are materialized with special
5070 // instructions rather than being loaded.
5071 return !ISD::isBuildVectorAllZeros(N) &&
5072 !ISD::isBuildVectorAllOnes(N);
5075 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5076 /// match movlp{s|d}. The lower half elements should come from lower half of
5077 /// V1 (and in order), and the upper half elements should come from the upper
5078 /// half of V2 (and in order). And since V1 will become the source of the
5079 /// MOVLP, it must be either a vector load or a scalar load to vector.
5080 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5081 ArrayRef<int> Mask, MVT VT) {
5082 if (!VT.is128BitVector())
5085 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5087 // Is V2 is a vector load, don't do this transformation. We will try to use
5088 // load folding shufps op.
5089 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5092 unsigned NumElems = VT.getVectorNumElements();
5094 if (NumElems != 2 && NumElems != 4)
5096 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5097 if (!isUndefOrEqual(Mask[i], i))
5099 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5100 if (!isUndefOrEqual(Mask[i], i+NumElems))
5105 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5106 /// to an zero vector.
5107 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5108 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5109 SDValue V1 = N->getOperand(0);
5110 SDValue V2 = N->getOperand(1);
5111 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5112 for (unsigned i = 0; i != NumElems; ++i) {
5113 int Idx = N->getMaskElt(i);
5114 if (Idx >= (int)NumElems) {
5115 unsigned Opc = V2.getOpcode();
5116 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5118 if (Opc != ISD::BUILD_VECTOR ||
5119 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5121 } else if (Idx >= 0) {
5122 unsigned Opc = V1.getOpcode();
5123 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5125 if (Opc != ISD::BUILD_VECTOR ||
5126 !X86::isZeroNode(V1.getOperand(Idx)))
5133 /// getZeroVector - Returns a vector of specified type with all zero elements.
5135 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5136 SelectionDAG &DAG, SDLoc dl) {
5137 assert(VT.isVector() && "Expected a vector type");
5139 // Always build SSE zero vectors as <4 x i32> bitcasted
5140 // to their dest type. This ensures they get CSE'd.
5142 if (VT.is128BitVector()) { // SSE
5143 if (Subtarget->hasSSE2()) { // SSE2
5144 SDValue Cst = DAG.getConstant(0, MVT::i32);
5145 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5147 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5148 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5150 } else if (VT.is256BitVector()) { // AVX
5151 if (Subtarget->hasInt256()) { // AVX2
5152 SDValue Cst = DAG.getConstant(0, MVT::i32);
5153 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5154 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5156 // 256-bit logic and arithmetic instructions in AVX are all
5157 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5158 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5159 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5160 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5162 } else if (VT.is512BitVector()) { // AVX-512
5163 SDValue Cst = DAG.getConstant(0, MVT::i32);
5164 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5165 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5166 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5167 } else if (VT.getScalarType() == MVT::i1) {
5168 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5169 SDValue Cst = DAG.getConstant(0, MVT::i1);
5170 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5171 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5173 llvm_unreachable("Unexpected vector type");
5175 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5178 /// getOnesVector - Returns a vector of specified type with all bits set.
5179 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5180 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5181 /// Then bitcast to their original type, ensuring they get CSE'd.
5182 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5184 assert(VT.isVector() && "Expected a vector type");
5186 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5188 if (VT.is256BitVector()) {
5189 if (HasInt256) { // AVX2
5190 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5191 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5193 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5194 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5196 } else if (VT.is128BitVector()) {
5197 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5199 llvm_unreachable("Unexpected vector type");
5201 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5204 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5205 /// that point to V2 points to its first element.
5206 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5207 for (unsigned i = 0; i != NumElems; ++i) {
5208 if (Mask[i] > (int)NumElems) {
5214 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5215 /// operation of specified width.
5216 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5218 unsigned NumElems = VT.getVectorNumElements();
5219 SmallVector<int, 8> Mask;
5220 Mask.push_back(NumElems);
5221 for (unsigned i = 1; i != NumElems; ++i)
5223 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5226 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5227 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5229 unsigned NumElems = VT.getVectorNumElements();
5230 SmallVector<int, 8> Mask;
5231 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5233 Mask.push_back(i + NumElems);
5235 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5238 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5239 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5241 unsigned NumElems = VT.getVectorNumElements();
5242 SmallVector<int, 8> Mask;
5243 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5244 Mask.push_back(i + Half);
5245 Mask.push_back(i + NumElems + Half);
5247 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5250 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5251 // a generic shuffle instruction because the target has no such instructions.
5252 // Generate shuffles which repeat i16 and i8 several times until they can be
5253 // represented by v4f32 and then be manipulated by target suported shuffles.
5254 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5255 MVT VT = V.getSimpleValueType();
5256 int NumElems = VT.getVectorNumElements();
5259 while (NumElems > 4) {
5260 if (EltNo < NumElems/2) {
5261 V = getUnpackl(DAG, dl, VT, V, V);
5263 V = getUnpackh(DAG, dl, VT, V, V);
5264 EltNo -= NumElems/2;
5271 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5272 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5273 MVT VT = V.getSimpleValueType();
5276 if (VT.is128BitVector()) {
5277 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5278 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5279 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5281 } else if (VT.is256BitVector()) {
5282 // To use VPERMILPS to splat scalars, the second half of indicies must
5283 // refer to the higher part, which is a duplication of the lower one,
5284 // because VPERMILPS can only handle in-lane permutations.
5285 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5286 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5288 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5289 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5292 llvm_unreachable("Vector size not supported");
5294 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5297 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5298 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5299 MVT SrcVT = SV->getSimpleValueType(0);
5300 SDValue V1 = SV->getOperand(0);
5303 int EltNo = SV->getSplatIndex();
5304 int NumElems = SrcVT.getVectorNumElements();
5305 bool Is256BitVec = SrcVT.is256BitVector();
5307 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5308 "Unknown how to promote splat for type");
5310 // Extract the 128-bit part containing the splat element and update
5311 // the splat element index when it refers to the higher register.
5313 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5314 if (EltNo >= NumElems/2)
5315 EltNo -= NumElems/2;
5318 // All i16 and i8 vector types can't be used directly by a generic shuffle
5319 // instruction because the target has no such instruction. Generate shuffles
5320 // which repeat i16 and i8 several times until they fit in i32, and then can
5321 // be manipulated by target suported shuffles.
5322 MVT EltVT = SrcVT.getVectorElementType();
5323 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5324 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5326 // Recreate the 256-bit vector and place the same 128-bit vector
5327 // into the low and high part. This is necessary because we want
5328 // to use VPERM* to shuffle the vectors
5330 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5333 return getLegalSplat(DAG, V1, EltNo);
5336 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5337 /// vector of zero or undef vector. This produces a shuffle where the low
5338 /// element of V2 is swizzled into the zero/undef vector, landing at element
5339 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5340 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5342 const X86Subtarget *Subtarget,
5343 SelectionDAG &DAG) {
5344 MVT VT = V2.getSimpleValueType();
5346 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5347 unsigned NumElems = VT.getVectorNumElements();
5348 SmallVector<int, 16> MaskVec;
5349 for (unsigned i = 0; i != NumElems; ++i)
5350 // If this is the insertion idx, put the low elt of V2 here.
5351 MaskVec.push_back(i == Idx ? NumElems : i);
5352 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5355 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5356 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5357 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5358 /// shuffles which use a single input multiple times, and in those cases it will
5359 /// adjust the mask to only have indices within that single input.
5360 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5361 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5362 unsigned NumElems = VT.getVectorNumElements();
5366 bool IsFakeUnary = false;
5367 switch(N->getOpcode()) {
5368 case X86ISD::BLENDI:
5369 ImmN = N->getOperand(N->getNumOperands()-1);
5370 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5373 ImmN = N->getOperand(N->getNumOperands()-1);
5374 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5375 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5377 case X86ISD::UNPCKH:
5378 DecodeUNPCKHMask(VT, Mask);
5379 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5381 case X86ISD::UNPCKL:
5382 DecodeUNPCKLMask(VT, Mask);
5383 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5385 case X86ISD::MOVHLPS:
5386 DecodeMOVHLPSMask(NumElems, Mask);
5387 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5389 case X86ISD::MOVLHPS:
5390 DecodeMOVLHPSMask(NumElems, Mask);
5391 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5393 case X86ISD::PALIGNR:
5394 ImmN = N->getOperand(N->getNumOperands()-1);
5395 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5397 case X86ISD::PSHUFD:
5398 case X86ISD::VPERMILPI:
5399 ImmN = N->getOperand(N->getNumOperands()-1);
5400 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5403 case X86ISD::PSHUFHW:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5408 case X86ISD::PSHUFLW:
5409 ImmN = N->getOperand(N->getNumOperands()-1);
5410 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5413 case X86ISD::PSHUFB: {
5415 SDValue MaskNode = N->getOperand(1);
5416 while (MaskNode->getOpcode() == ISD::BITCAST)
5417 MaskNode = MaskNode->getOperand(0);
5419 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5420 // If we have a build-vector, then things are easy.
5421 EVT VT = MaskNode.getValueType();
5422 assert(VT.isVector() &&
5423 "Can't produce a non-vector with a build_vector!");
5424 if (!VT.isInteger())
5427 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5429 SmallVector<uint64_t, 32> RawMask;
5430 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5431 SDValue Op = MaskNode->getOperand(i);
5432 if (Op->getOpcode() == ISD::UNDEF) {
5433 RawMask.push_back((uint64_t)SM_SentinelUndef);
5436 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5439 APInt MaskElement = CN->getAPIntValue();
5441 // We now have to decode the element which could be any integer size and
5442 // extract each byte of it.
5443 for (int j = 0; j < NumBytesPerElement; ++j) {
5444 // Note that this is x86 and so always little endian: the low byte is
5445 // the first byte of the mask.
5446 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5447 MaskElement = MaskElement.lshr(8);
5450 DecodePSHUFBMask(RawMask, Mask);
5454 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5458 SDValue Ptr = MaskLoad->getBasePtr();
5459 if (Ptr->getOpcode() == X86ISD::Wrapper)
5460 Ptr = Ptr->getOperand(0);
5462 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5463 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5466 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5467 // FIXME: Support AVX-512 here.
5468 Type *Ty = C->getType();
5469 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5470 Ty->getVectorNumElements() != 32))
5473 DecodePSHUFBMask(C, Mask);
5479 case X86ISD::VPERMI:
5480 ImmN = N->getOperand(N->getNumOperands()-1);
5481 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5485 case X86ISD::MOVSD: {
5486 // The index 0 always comes from the first element of the second source,
5487 // this is why MOVSS and MOVSD are used in the first place. The other
5488 // elements come from the other positions of the first source vector
5489 Mask.push_back(NumElems);
5490 for (unsigned i = 1; i != NumElems; ++i) {
5495 case X86ISD::VPERM2X128:
5496 ImmN = N->getOperand(N->getNumOperands()-1);
5497 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5498 if (Mask.empty()) return false;
5500 case X86ISD::MOVSLDUP:
5501 DecodeMOVSLDUPMask(VT, Mask);
5503 case X86ISD::MOVSHDUP:
5504 DecodeMOVSHDUPMask(VT, Mask);
5506 case X86ISD::MOVDDUP:
5507 case X86ISD::MOVLHPD:
5508 case X86ISD::MOVLPD:
5509 case X86ISD::MOVLPS:
5510 // Not yet implemented
5512 default: llvm_unreachable("unknown target shuffle node");
5515 // If we have a fake unary shuffle, the shuffle mask is spread across two
5516 // inputs that are actually the same node. Re-map the mask to always point
5517 // into the first input.
5520 if (M >= (int)Mask.size())
5526 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5527 /// element of the result of the vector shuffle.
5528 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5531 return SDValue(); // Limit search depth.
5533 SDValue V = SDValue(N, 0);
5534 EVT VT = V.getValueType();
5535 unsigned Opcode = V.getOpcode();
5537 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5538 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5539 int Elt = SV->getMaskElt(Index);
5542 return DAG.getUNDEF(VT.getVectorElementType());
5544 unsigned NumElems = VT.getVectorNumElements();
5545 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5546 : SV->getOperand(1);
5547 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5550 // Recurse into target specific vector shuffles to find scalars.
5551 if (isTargetShuffle(Opcode)) {
5552 MVT ShufVT = V.getSimpleValueType();
5553 unsigned NumElems = ShufVT.getVectorNumElements();
5554 SmallVector<int, 16> ShuffleMask;
5557 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5560 int Elt = ShuffleMask[Index];
5562 return DAG.getUNDEF(ShufVT.getVectorElementType());
5564 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5566 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5570 // Actual nodes that may contain scalar elements
5571 if (Opcode == ISD::BITCAST) {
5572 V = V.getOperand(0);
5573 EVT SrcVT = V.getValueType();
5574 unsigned NumElems = VT.getVectorNumElements();
5576 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5580 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5581 return (Index == 0) ? V.getOperand(0)
5582 : DAG.getUNDEF(VT.getVectorElementType());
5584 if (V.getOpcode() == ISD::BUILD_VECTOR)
5585 return V.getOperand(Index);
5590 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5591 /// shuffle operation which come from a consecutively from a zero. The
5592 /// search can start in two different directions, from left or right.
5593 /// We count undefs as zeros until PreferredNum is reached.
5594 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5595 unsigned NumElems, bool ZerosFromLeft,
5597 unsigned PreferredNum = -1U) {
5598 unsigned NumZeros = 0;
5599 for (unsigned i = 0; i != NumElems; ++i) {
5600 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5601 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5605 if (X86::isZeroNode(Elt))
5607 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5608 NumZeros = std::min(NumZeros + 1, PreferredNum);
5616 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5617 /// correspond consecutively to elements from one of the vector operands,
5618 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5620 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5621 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5622 unsigned NumElems, unsigned &OpNum) {
5623 bool SeenV1 = false;
5624 bool SeenV2 = false;
5626 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5627 int Idx = SVOp->getMaskElt(i);
5628 // Ignore undef indicies
5632 if (Idx < (int)NumElems)
5637 // Only accept consecutive elements from the same vector
5638 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5642 OpNum = SeenV1 ? 0 : 1;
5646 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5647 /// logical left shift of a vector.
5648 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5649 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5651 SVOp->getSimpleValueType(0).getVectorNumElements();
5652 unsigned NumZeros = getNumOfConsecutiveZeros(
5653 SVOp, NumElems, false /* check zeros from right */, DAG,
5654 SVOp->getMaskElt(0));
5660 // Considering the elements in the mask that are not consecutive zeros,
5661 // check if they consecutively come from only one of the source vectors.
5663 // V1 = {X, A, B, C} 0
5665 // vector_shuffle V1, V2 <1, 2, 3, X>
5667 if (!isShuffleMaskConsecutive(SVOp,
5668 0, // Mask Start Index
5669 NumElems-NumZeros, // Mask End Index(exclusive)
5670 NumZeros, // Where to start looking in the src vector
5671 NumElems, // Number of elements in vector
5672 OpSrc)) // Which source operand ?
5677 ShVal = SVOp->getOperand(OpSrc);
5681 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5682 /// logical left shift of a vector.
5683 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5684 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5686 SVOp->getSimpleValueType(0).getVectorNumElements();
5687 unsigned NumZeros = getNumOfConsecutiveZeros(
5688 SVOp, NumElems, true /* check zeros from left */, DAG,
5689 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5695 // Considering the elements in the mask that are not consecutive zeros,
5696 // check if they consecutively come from only one of the source vectors.
5698 // 0 { A, B, X, X } = V2
5700 // vector_shuffle V1, V2 <X, X, 4, 5>
5702 if (!isShuffleMaskConsecutive(SVOp,
5703 NumZeros, // Mask Start Index
5704 NumElems, // Mask End Index(exclusive)
5705 0, // Where to start looking in the src vector
5706 NumElems, // Number of elements in vector
5707 OpSrc)) // Which source operand ?
5712 ShVal = SVOp->getOperand(OpSrc);
5716 /// isVectorShift - Returns true if the shuffle can be implemented as a
5717 /// logical left or right shift of a vector.
5718 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5719 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5720 // Although the logic below support any bitwidth size, there are no
5721 // shift instructions which handle more than 128-bit vectors.
5722 if (!SVOp->getSimpleValueType(0).is128BitVector())
5725 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5726 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5732 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5734 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5735 unsigned NumNonZero, unsigned NumZero,
5737 const X86Subtarget* Subtarget,
5738 const TargetLowering &TLI) {
5745 for (unsigned i = 0; i < 16; ++i) {
5746 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5747 if (ThisIsNonZero && First) {
5749 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5751 V = DAG.getUNDEF(MVT::v8i16);
5756 SDValue ThisElt, LastElt;
5757 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5758 if (LastIsNonZero) {
5759 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5760 MVT::i16, Op.getOperand(i-1));
5762 if (ThisIsNonZero) {
5763 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5764 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5765 ThisElt, DAG.getConstant(8, MVT::i8));
5767 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5771 if (ThisElt.getNode())
5772 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5773 DAG.getIntPtrConstant(i/2));
5777 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5780 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5782 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5783 unsigned NumNonZero, unsigned NumZero,
5785 const X86Subtarget* Subtarget,
5786 const TargetLowering &TLI) {
5793 for (unsigned i = 0; i < 8; ++i) {
5794 bool isNonZero = (NonZeros & (1 << i)) != 0;
5798 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5800 V = DAG.getUNDEF(MVT::v8i16);
5803 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5804 MVT::v8i16, V, Op.getOperand(i),
5805 DAG.getIntPtrConstant(i));
5812 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5813 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5814 const X86Subtarget *Subtarget,
5815 const TargetLowering &TLI) {
5816 // Find all zeroable elements.
5818 for (int i=0; i < 4; ++i) {
5819 SDValue Elt = Op->getOperand(i);
5820 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5822 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5823 [](bool M) { return !M; }) > 1 &&
5824 "We expect at least two non-zero elements!");
5826 // We only know how to deal with build_vector nodes where elements are either
5827 // zeroable or extract_vector_elt with constant index.
5828 SDValue FirstNonZero;
5829 unsigned FirstNonZeroIdx;
5830 for (unsigned i=0; i < 4; ++i) {
5833 SDValue Elt = Op->getOperand(i);
5834 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5835 !isa<ConstantSDNode>(Elt.getOperand(1)))
5837 // Make sure that this node is extracting from a 128-bit vector.
5838 MVT VT = Elt.getOperand(0).getSimpleValueType();
5839 if (!VT.is128BitVector())
5841 if (!FirstNonZero.getNode()) {
5843 FirstNonZeroIdx = i;
5847 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5848 SDValue V1 = FirstNonZero.getOperand(0);
5849 MVT VT = V1.getSimpleValueType();
5851 // See if this build_vector can be lowered as a blend with zero.
5853 unsigned EltMaskIdx, EltIdx;
5855 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5856 if (Zeroable[EltIdx]) {
5857 // The zero vector will be on the right hand side.
5858 Mask[EltIdx] = EltIdx+4;
5862 Elt = Op->getOperand(EltIdx);
5863 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5864 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5865 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5867 Mask[EltIdx] = EltIdx;
5871 // Let the shuffle legalizer deal with blend operations.
5872 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5873 if (V1.getSimpleValueType() != VT)
5874 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5875 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5878 // See if we can lower this build_vector to a INSERTPS.
5879 if (!Subtarget->hasSSE41())
5882 SDValue V2 = Elt.getOperand(0);
5883 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5886 bool CanFold = true;
5887 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5891 SDValue Current = Op->getOperand(i);
5892 SDValue SrcVector = Current->getOperand(0);
5895 CanFold = SrcVector == V1 &&
5896 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5902 assert(V1.getNode() && "Expected at least two non-zero elements!");
5903 if (V1.getSimpleValueType() != MVT::v4f32)
5904 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5905 if (V2.getSimpleValueType() != MVT::v4f32)
5906 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5908 // Ok, we can emit an INSERTPS instruction.
5910 for (int i = 0; i < 4; ++i)
5914 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5915 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5916 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5917 DAG.getIntPtrConstant(InsertPSMask));
5918 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5921 /// getVShift - Return a vector logical shift node.
5923 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5924 unsigned NumBits, SelectionDAG &DAG,
5925 const TargetLowering &TLI, SDLoc dl) {
5926 assert(VT.is128BitVector() && "Unknown type for VShift");
5927 EVT ShVT = MVT::v2i64;
5928 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5929 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5930 return DAG.getNode(ISD::BITCAST, dl, VT,
5931 DAG.getNode(Opc, dl, ShVT, SrcOp,
5932 DAG.getConstant(NumBits,
5933 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5937 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5939 // Check if the scalar load can be widened into a vector load. And if
5940 // the address is "base + cst" see if the cst can be "absorbed" into
5941 // the shuffle mask.
5942 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5943 SDValue Ptr = LD->getBasePtr();
5944 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5946 EVT PVT = LD->getValueType(0);
5947 if (PVT != MVT::i32 && PVT != MVT::f32)
5952 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5953 FI = FINode->getIndex();
5955 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5956 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5957 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5958 Offset = Ptr.getConstantOperandVal(1);
5959 Ptr = Ptr.getOperand(0);
5964 // FIXME: 256-bit vector instructions don't require a strict alignment,
5965 // improve this code to support it better.
5966 unsigned RequiredAlign = VT.getSizeInBits()/8;
5967 SDValue Chain = LD->getChain();
5968 // Make sure the stack object alignment is at least 16 or 32.
5969 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5970 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5971 if (MFI->isFixedObjectIndex(FI)) {
5972 // Can't change the alignment. FIXME: It's possible to compute
5973 // the exact stack offset and reference FI + adjust offset instead.
5974 // If someone *really* cares about this. That's the way to implement it.
5977 MFI->setObjectAlignment(FI, RequiredAlign);
5981 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5982 // Ptr + (Offset & ~15).
5985 if ((Offset % RequiredAlign) & 3)
5987 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5989 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5990 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5992 int EltNo = (Offset - StartOffset) >> 2;
5993 unsigned NumElems = VT.getVectorNumElements();
5995 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5996 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5997 LD->getPointerInfo().getWithOffset(StartOffset),
5998 false, false, false, 0);
6000 SmallVector<int, 8> Mask;
6001 for (unsigned i = 0; i != NumElems; ++i)
6002 Mask.push_back(EltNo);
6004 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
6010 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
6011 /// vector of type 'VT', see if the elements can be replaced by a single large
6012 /// load which has the same value as a build_vector whose operands are 'elts'.
6014 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
6016 /// FIXME: we'd also like to handle the case where the last elements are zero
6017 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
6018 /// There's even a handy isZeroNode for that purpose.
6019 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6020 SDLoc &DL, SelectionDAG &DAG,
6021 bool isAfterLegalize) {
6022 EVT EltVT = VT.getVectorElementType();
6023 unsigned NumElems = Elts.size();
6025 LoadSDNode *LDBase = nullptr;
6026 unsigned LastLoadedElt = -1U;
6028 // For each element in the initializer, see if we've found a load or an undef.
6029 // If we don't find an initial load element, or later load elements are
6030 // non-consecutive, bail out.
6031 for (unsigned i = 0; i < NumElems; ++i) {
6032 SDValue Elt = Elts[i];
6034 if (!Elt.getNode() ||
6035 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6038 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6040 LDBase = cast<LoadSDNode>(Elt.getNode());
6044 if (Elt.getOpcode() == ISD::UNDEF)
6047 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6048 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6053 // If we have found an entire vector of loads and undefs, then return a large
6054 // load of the entire vector width starting at the base pointer. If we found
6055 // consecutive loads for the low half, generate a vzext_load node.
6056 if (LastLoadedElt == NumElems - 1) {
6058 if (isAfterLegalize &&
6059 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6062 SDValue NewLd = SDValue();
6064 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6065 LDBase->getPointerInfo(), LDBase->isVolatile(),
6066 LDBase->isNonTemporal(), LDBase->isInvariant(),
6067 LDBase->getAlignment());
6069 if (LDBase->hasAnyUseOfValue(1)) {
6070 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6072 SDValue(NewLd.getNode(), 1));
6073 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6074 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6075 SDValue(NewLd.getNode(), 1));
6081 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6082 //of a v4i32 / v4f32. It's probably worth generalizing.
6083 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6084 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6085 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6086 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6088 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6089 LDBase->getPointerInfo(),
6090 LDBase->getAlignment(),
6091 false/*isVolatile*/, true/*ReadMem*/,
6094 // Make sure the newly-created LOAD is in the same position as LDBase in
6095 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6096 // update uses of LDBase's output chain to use the TokenFactor.
6097 if (LDBase->hasAnyUseOfValue(1)) {
6098 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6099 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6100 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6101 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6102 SDValue(ResNode.getNode(), 1));
6105 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6110 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6111 /// to generate a splat value for the following cases:
6112 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6113 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6114 /// a scalar load, or a constant.
6115 /// The VBROADCAST node is returned when a pattern is found,
6116 /// or SDValue() otherwise.
6117 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6118 SelectionDAG &DAG) {
6119 // VBROADCAST requires AVX.
6120 // TODO: Splats could be generated for non-AVX CPUs using SSE
6121 // instructions, but there's less potential gain for only 128-bit vectors.
6122 if (!Subtarget->hasAVX())
6125 MVT VT = Op.getSimpleValueType();
6128 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6129 "Unsupported vector type for broadcast.");
6134 switch (Op.getOpcode()) {
6136 // Unknown pattern found.
6139 case ISD::BUILD_VECTOR: {
6140 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6141 BitVector UndefElements;
6142 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6144 // We need a splat of a single value to use broadcast, and it doesn't
6145 // make any sense if the value is only in one element of the vector.
6146 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6150 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6151 Ld.getOpcode() == ISD::ConstantFP);
6153 // Make sure that all of the users of a non-constant load are from the
6154 // BUILD_VECTOR node.
6155 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6160 case ISD::VECTOR_SHUFFLE: {
6161 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6163 // Shuffles must have a splat mask where the first element is
6165 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6168 SDValue Sc = Op.getOperand(0);
6169 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6170 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6172 if (!Subtarget->hasInt256())
6175 // Use the register form of the broadcast instruction available on AVX2.
6176 if (VT.getSizeInBits() >= 256)
6177 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6178 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6181 Ld = Sc.getOperand(0);
6182 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6183 Ld.getOpcode() == ISD::ConstantFP);
6185 // The scalar_to_vector node and the suspected
6186 // load node must have exactly one user.
6187 // Constants may have multiple users.
6189 // AVX-512 has register version of the broadcast
6190 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6191 Ld.getValueType().getSizeInBits() >= 32;
6192 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6199 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6200 bool IsGE256 = (VT.getSizeInBits() >= 256);
6202 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6203 // instruction to save 8 or more bytes of constant pool data.
6204 // TODO: If multiple splats are generated to load the same constant,
6205 // it may be detrimental to overall size. There needs to be a way to detect
6206 // that condition to know if this is truly a size win.
6207 const Function *F = DAG.getMachineFunction().getFunction();
6208 bool OptForSize = F->getAttributes().
6209 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6211 // Handle broadcasting a single constant scalar from the constant pool
6213 // On Sandybridge (no AVX2), it is still better to load a constant vector
6214 // from the constant pool and not to broadcast it from a scalar.
6215 // But override that restriction when optimizing for size.
6216 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6217 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6218 EVT CVT = Ld.getValueType();
6219 assert(!CVT.isVector() && "Must not broadcast a vector type");
6221 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6222 // For size optimization, also splat v2f64 and v2i64, and for size opt
6223 // with AVX2, also splat i8 and i16.
6224 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6225 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6226 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6227 const Constant *C = nullptr;
6228 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6229 C = CI->getConstantIntValue();
6230 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6231 C = CF->getConstantFPValue();
6233 assert(C && "Invalid constant type");
6235 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6236 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6237 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6238 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6239 MachinePointerInfo::getConstantPool(),
6240 false, false, false, Alignment);
6242 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6246 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6248 // Handle AVX2 in-register broadcasts.
6249 if (!IsLoad && Subtarget->hasInt256() &&
6250 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6251 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6253 // The scalar source must be a normal load.
6257 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6258 (Subtarget->hasVLX() && ScalarSize == 64))
6259 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6261 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6262 // double since there is no vbroadcastsd xmm
6263 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6264 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6265 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6268 // Unsupported broadcast.
6272 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6273 /// underlying vector and index.
6275 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6277 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6279 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6280 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6283 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6285 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6287 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6288 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6291 // In this case the vector is the extract_subvector expression and the index
6292 // is 2, as specified by the shuffle.
6293 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6294 SDValue ShuffleVec = SVOp->getOperand(0);
6295 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6296 assert(ShuffleVecVT.getVectorElementType() ==
6297 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6299 int ShuffleIdx = SVOp->getMaskElt(Idx);
6300 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6301 ExtractedFromVec = ShuffleVec;
6307 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6308 MVT VT = Op.getSimpleValueType();
6310 // Skip if insert_vec_elt is not supported.
6311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6312 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6316 unsigned NumElems = Op.getNumOperands();
6320 SmallVector<unsigned, 4> InsertIndices;
6321 SmallVector<int, 8> Mask(NumElems, -1);
6323 for (unsigned i = 0; i != NumElems; ++i) {
6324 unsigned Opc = Op.getOperand(i).getOpcode();
6326 if (Opc == ISD::UNDEF)
6329 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6330 // Quit if more than 1 elements need inserting.
6331 if (InsertIndices.size() > 1)
6334 InsertIndices.push_back(i);
6338 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6339 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6340 // Quit if non-constant index.
6341 if (!isa<ConstantSDNode>(ExtIdx))
6343 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6345 // Quit if extracted from vector of different type.
6346 if (ExtractedFromVec.getValueType() != VT)
6349 if (!VecIn1.getNode())
6350 VecIn1 = ExtractedFromVec;
6351 else if (VecIn1 != ExtractedFromVec) {
6352 if (!VecIn2.getNode())
6353 VecIn2 = ExtractedFromVec;
6354 else if (VecIn2 != ExtractedFromVec)
6355 // Quit if more than 2 vectors to shuffle
6359 if (ExtractedFromVec == VecIn1)
6361 else if (ExtractedFromVec == VecIn2)
6362 Mask[i] = Idx + NumElems;
6365 if (!VecIn1.getNode())
6368 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6369 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6370 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6371 unsigned Idx = InsertIndices[i];
6372 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6373 DAG.getIntPtrConstant(Idx));
6379 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6381 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6383 MVT VT = Op.getSimpleValueType();
6384 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6385 "Unexpected type in LowerBUILD_VECTORvXi1!");
6388 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6389 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6390 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6391 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6394 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6395 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6396 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6397 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6400 bool AllContants = true;
6401 uint64_t Immediate = 0;
6402 int NonConstIdx = -1;
6403 bool IsSplat = true;
6404 unsigned NumNonConsts = 0;
6405 unsigned NumConsts = 0;
6406 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6407 SDValue In = Op.getOperand(idx);
6408 if (In.getOpcode() == ISD::UNDEF)
6410 if (!isa<ConstantSDNode>(In)) {
6411 AllContants = false;
6416 if (cast<ConstantSDNode>(In)->getZExtValue())
6417 Immediate |= (1ULL << idx);
6419 if (In != Op.getOperand(0))
6424 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6425 DAG.getConstant(Immediate, MVT::i16));
6426 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6427 DAG.getIntPtrConstant(0));
6430 if (NumNonConsts == 1 && NonConstIdx != 0) {
6433 SDValue VecAsImm = DAG.getConstant(Immediate,
6434 MVT::getIntegerVT(VT.getSizeInBits()));
6435 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6438 DstVec = DAG.getUNDEF(VT);
6439 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6440 Op.getOperand(NonConstIdx),
6441 DAG.getIntPtrConstant(NonConstIdx));
6443 if (!IsSplat && (NonConstIdx != 0))
6444 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6445 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6448 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6449 DAG.getConstant(-1, SelectVT),
6450 DAG.getConstant(0, SelectVT));
6452 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6453 DAG.getConstant((Immediate | 1), SelectVT),
6454 DAG.getConstant(Immediate, SelectVT));
6455 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6458 /// \brief Return true if \p N implements a horizontal binop and return the
6459 /// operands for the horizontal binop into V0 and V1.
6461 /// This is a helper function of PerformBUILD_VECTORCombine.
6462 /// This function checks that the build_vector \p N in input implements a
6463 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6464 /// operation to match.
6465 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6466 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6467 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6470 /// This function only analyzes elements of \p N whose indices are
6471 /// in range [BaseIdx, LastIdx).
6472 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6474 unsigned BaseIdx, unsigned LastIdx,
6475 SDValue &V0, SDValue &V1) {
6476 EVT VT = N->getValueType(0);
6478 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6479 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6480 "Invalid Vector in input!");
6482 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6483 bool CanFold = true;
6484 unsigned ExpectedVExtractIdx = BaseIdx;
6485 unsigned NumElts = LastIdx - BaseIdx;
6486 V0 = DAG.getUNDEF(VT);
6487 V1 = DAG.getUNDEF(VT);
6489 // Check if N implements a horizontal binop.
6490 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6491 SDValue Op = N->getOperand(i + BaseIdx);
6494 if (Op->getOpcode() == ISD::UNDEF) {
6495 // Update the expected vector extract index.
6496 if (i * 2 == NumElts)
6497 ExpectedVExtractIdx = BaseIdx;
6498 ExpectedVExtractIdx += 2;
6502 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6507 SDValue Op0 = Op.getOperand(0);
6508 SDValue Op1 = Op.getOperand(1);
6510 // Try to match the following pattern:
6511 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6512 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6513 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6514 Op0.getOperand(0) == Op1.getOperand(0) &&
6515 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6516 isa<ConstantSDNode>(Op1.getOperand(1)));
6520 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6521 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6523 if (i * 2 < NumElts) {
6524 if (V0.getOpcode() == ISD::UNDEF)
6525 V0 = Op0.getOperand(0);
6527 if (V1.getOpcode() == ISD::UNDEF)
6528 V1 = Op0.getOperand(0);
6529 if (i * 2 == NumElts)
6530 ExpectedVExtractIdx = BaseIdx;
6533 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6534 if (I0 == ExpectedVExtractIdx)
6535 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6536 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6537 // Try to match the following dag sequence:
6538 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6539 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6543 ExpectedVExtractIdx += 2;
6549 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6550 /// a concat_vector.
6552 /// This is a helper function of PerformBUILD_VECTORCombine.
6553 /// This function expects two 256-bit vectors called V0 and V1.
6554 /// At first, each vector is split into two separate 128-bit vectors.
6555 /// Then, the resulting 128-bit vectors are used to implement two
6556 /// horizontal binary operations.
6558 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6560 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6561 /// the two new horizontal binop.
6562 /// When Mode is set, the first horizontal binop dag node would take as input
6563 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6564 /// horizontal binop dag node would take as input the lower 128-bit of V1
6565 /// and the upper 128-bit of V1.
6567 /// HADD V0_LO, V0_HI
6568 /// HADD V1_LO, V1_HI
6570 /// Otherwise, the first horizontal binop dag node takes as input the lower
6571 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6572 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6574 /// HADD V0_LO, V1_LO
6575 /// HADD V0_HI, V1_HI
6577 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6578 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6579 /// the upper 128-bits of the result.
6580 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6581 SDLoc DL, SelectionDAG &DAG,
6582 unsigned X86Opcode, bool Mode,
6583 bool isUndefLO, bool isUndefHI) {
6584 EVT VT = V0.getValueType();
6585 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6586 "Invalid nodes in input!");
6588 unsigned NumElts = VT.getVectorNumElements();
6589 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6590 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6591 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6592 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6593 EVT NewVT = V0_LO.getValueType();
6595 SDValue LO = DAG.getUNDEF(NewVT);
6596 SDValue HI = DAG.getUNDEF(NewVT);
6599 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6600 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6601 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6602 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6603 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6605 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6606 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6607 V1_LO->getOpcode() != ISD::UNDEF))
6608 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6610 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6611 V1_HI->getOpcode() != ISD::UNDEF))
6612 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6615 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6618 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6619 /// sequence of 'vadd + vsub + blendi'.
6620 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6621 const X86Subtarget *Subtarget) {
6623 EVT VT = BV->getValueType(0);
6624 unsigned NumElts = VT.getVectorNumElements();
6625 SDValue InVec0 = DAG.getUNDEF(VT);
6626 SDValue InVec1 = DAG.getUNDEF(VT);
6628 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6629 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6631 // Odd-numbered elements in the input build vector are obtained from
6632 // adding two integer/float elements.
6633 // Even-numbered elements in the input build vector are obtained from
6634 // subtracting two integer/float elements.
6635 unsigned ExpectedOpcode = ISD::FSUB;
6636 unsigned NextExpectedOpcode = ISD::FADD;
6637 bool AddFound = false;
6638 bool SubFound = false;
6640 for (unsigned i = 0, e = NumElts; i != e; i++) {
6641 SDValue Op = BV->getOperand(i);
6643 // Skip 'undef' values.
6644 unsigned Opcode = Op.getOpcode();
6645 if (Opcode == ISD::UNDEF) {
6646 std::swap(ExpectedOpcode, NextExpectedOpcode);
6650 // Early exit if we found an unexpected opcode.
6651 if (Opcode != ExpectedOpcode)
6654 SDValue Op0 = Op.getOperand(0);
6655 SDValue Op1 = Op.getOperand(1);
6657 // Try to match the following pattern:
6658 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6659 // Early exit if we cannot match that sequence.
6660 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6661 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6662 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6663 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6664 Op0.getOperand(1) != Op1.getOperand(1))
6667 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6671 // We found a valid add/sub node. Update the information accordingly.
6677 // Update InVec0 and InVec1.
6678 if (InVec0.getOpcode() == ISD::UNDEF)
6679 InVec0 = Op0.getOperand(0);
6680 if (InVec1.getOpcode() == ISD::UNDEF)
6681 InVec1 = Op1.getOperand(0);
6683 // Make sure that operands in input to each add/sub node always
6684 // come from a same pair of vectors.
6685 if (InVec0 != Op0.getOperand(0)) {
6686 if (ExpectedOpcode == ISD::FSUB)
6689 // FADD is commutable. Try to commute the operands
6690 // and then test again.
6691 std::swap(Op0, Op1);
6692 if (InVec0 != Op0.getOperand(0))
6696 if (InVec1 != Op1.getOperand(0))
6699 // Update the pair of expected opcodes.
6700 std::swap(ExpectedOpcode, NextExpectedOpcode);
6703 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6704 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6705 InVec1.getOpcode() != ISD::UNDEF)
6706 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6711 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6712 const X86Subtarget *Subtarget) {
6714 EVT VT = N->getValueType(0);
6715 unsigned NumElts = VT.getVectorNumElements();
6716 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6717 SDValue InVec0, InVec1;
6719 // Try to match an ADDSUB.
6720 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6721 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6722 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6723 if (Value.getNode())
6727 // Try to match horizontal ADD/SUB.
6728 unsigned NumUndefsLO = 0;
6729 unsigned NumUndefsHI = 0;
6730 unsigned Half = NumElts/2;
6732 // Count the number of UNDEF operands in the build_vector in input.
6733 for (unsigned i = 0, e = Half; i != e; ++i)
6734 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6737 for (unsigned i = Half, e = NumElts; i != e; ++i)
6738 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6741 // Early exit if this is either a build_vector of all UNDEFs or all the
6742 // operands but one are UNDEF.
6743 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6746 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6747 // Try to match an SSE3 float HADD/HSUB.
6748 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6749 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6751 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6752 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6753 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6754 // Try to match an SSSE3 integer HADD/HSUB.
6755 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6756 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6758 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6759 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6762 if (!Subtarget->hasAVX())
6765 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6766 // Try to match an AVX horizontal add/sub of packed single/double
6767 // precision floating point values from 256-bit vectors.
6768 SDValue InVec2, InVec3;
6769 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6770 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6771 ((InVec0.getOpcode() == ISD::UNDEF ||
6772 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6773 ((InVec1.getOpcode() == ISD::UNDEF ||
6774 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6775 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6777 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6778 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6779 ((InVec0.getOpcode() == ISD::UNDEF ||
6780 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6781 ((InVec1.getOpcode() == ISD::UNDEF ||
6782 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6783 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6784 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6785 // Try to match an AVX2 horizontal add/sub of signed integers.
6786 SDValue InVec2, InVec3;
6788 bool CanFold = true;
6790 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6791 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6792 ((InVec0.getOpcode() == ISD::UNDEF ||
6793 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6794 ((InVec1.getOpcode() == ISD::UNDEF ||
6795 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6796 X86Opcode = X86ISD::HADD;
6797 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6798 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6799 ((InVec0.getOpcode() == ISD::UNDEF ||
6800 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6801 ((InVec1.getOpcode() == ISD::UNDEF ||
6802 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6803 X86Opcode = X86ISD::HSUB;
6808 // Fold this build_vector into a single horizontal add/sub.
6809 // Do this only if the target has AVX2.
6810 if (Subtarget->hasAVX2())
6811 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6813 // Do not try to expand this build_vector into a pair of horizontal
6814 // add/sub if we can emit a pair of scalar add/sub.
6815 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6818 // Convert this build_vector into a pair of horizontal binop followed by
6820 bool isUndefLO = NumUndefsLO == Half;
6821 bool isUndefHI = NumUndefsHI == Half;
6822 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6823 isUndefLO, isUndefHI);
6827 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6828 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6830 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6831 X86Opcode = X86ISD::HADD;
6832 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6833 X86Opcode = X86ISD::HSUB;
6834 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6835 X86Opcode = X86ISD::FHADD;
6836 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6837 X86Opcode = X86ISD::FHSUB;
6841 // Don't try to expand this build_vector into a pair of horizontal add/sub
6842 // if we can simply emit a pair of scalar add/sub.
6843 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6846 // Convert this build_vector into two horizontal add/sub followed by
6848 bool isUndefLO = NumUndefsLO == Half;
6849 bool isUndefHI = NumUndefsHI == Half;
6850 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6851 isUndefLO, isUndefHI);
6858 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6861 MVT VT = Op.getSimpleValueType();
6862 MVT ExtVT = VT.getVectorElementType();
6863 unsigned NumElems = Op.getNumOperands();
6865 // Generate vectors for predicate vectors.
6866 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6867 return LowerBUILD_VECTORvXi1(Op, DAG);
6869 // Vectors containing all zeros can be matched by pxor and xorps later
6870 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6871 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6872 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6873 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6876 return getZeroVector(VT, Subtarget, DAG, dl);
6879 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6880 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6881 // vpcmpeqd on 256-bit vectors.
6882 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6883 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6886 if (!VT.is512BitVector())
6887 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6890 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6891 if (Broadcast.getNode())
6894 unsigned EVTBits = ExtVT.getSizeInBits();
6896 unsigned NumZero = 0;
6897 unsigned NumNonZero = 0;
6898 unsigned NonZeros = 0;
6899 bool IsAllConstants = true;
6900 SmallSet<SDValue, 8> Values;
6901 for (unsigned i = 0; i < NumElems; ++i) {
6902 SDValue Elt = Op.getOperand(i);
6903 if (Elt.getOpcode() == ISD::UNDEF)
6906 if (Elt.getOpcode() != ISD::Constant &&
6907 Elt.getOpcode() != ISD::ConstantFP)
6908 IsAllConstants = false;
6909 if (X86::isZeroNode(Elt))
6912 NonZeros |= (1 << i);
6917 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6918 if (NumNonZero == 0)
6919 return DAG.getUNDEF(VT);
6921 // Special case for single non-zero, non-undef, element.
6922 if (NumNonZero == 1) {
6923 unsigned Idx = countTrailingZeros(NonZeros);
6924 SDValue Item = Op.getOperand(Idx);
6926 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6927 // the value are obviously zero, truncate the value to i32 and do the
6928 // insertion that way. Only do this if the value is non-constant or if the
6929 // value is a constant being inserted into element 0. It is cheaper to do
6930 // a constant pool load than it is to do a movd + shuffle.
6931 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6932 (!IsAllConstants || Idx == 0)) {
6933 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6935 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6936 EVT VecVT = MVT::v4i32;
6937 unsigned VecElts = 4;
6939 // Truncate the value (which may itself be a constant) to i32, and
6940 // convert it to a vector with movd (S2V+shuffle to zero extend).
6941 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6942 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6944 // If using the new shuffle lowering, just directly insert this.
6945 if (ExperimentalVectorShuffleLowering)
6947 ISD::BITCAST, dl, VT,
6948 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6950 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6952 // Now we have our 32-bit value zero extended in the low element of
6953 // a vector. If Idx != 0, swizzle it into place.
6955 SmallVector<int, 4> Mask;
6956 Mask.push_back(Idx);
6957 for (unsigned i = 1; i != VecElts; ++i)
6959 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6962 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6966 // If we have a constant or non-constant insertion into the low element of
6967 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6968 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6969 // depending on what the source datatype is.
6972 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6974 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6975 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6976 if (VT.is256BitVector() || VT.is512BitVector()) {
6977 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6978 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6979 Item, DAG.getIntPtrConstant(0));
6981 assert(VT.is128BitVector() && "Expected an SSE value type!");
6982 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6983 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6984 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6987 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6988 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6989 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6990 if (VT.is256BitVector()) {
6991 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6992 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6994 assert(VT.is128BitVector() && "Expected an SSE value type!");
6995 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6997 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
7001 // Is it a vector logical left shift?
7002 if (NumElems == 2 && Idx == 1 &&
7003 X86::isZeroNode(Op.getOperand(0)) &&
7004 !X86::isZeroNode(Op.getOperand(1))) {
7005 unsigned NumBits = VT.getSizeInBits();
7006 return getVShift(true, VT,
7007 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7008 VT, Op.getOperand(1)),
7009 NumBits/2, DAG, *this, dl);
7012 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
7015 // Otherwise, if this is a vector with i32 or f32 elements, and the element
7016 // is a non-constant being inserted into an element other than the low one,
7017 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
7018 // movd/movss) to move this into the low element, then shuffle it into
7020 if (EVTBits == 32) {
7021 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7023 // If using the new shuffle lowering, just directly insert this.
7024 if (ExperimentalVectorShuffleLowering)
7025 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7027 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7028 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7029 SmallVector<int, 8> MaskVec;
7030 for (unsigned i = 0; i != NumElems; ++i)
7031 MaskVec.push_back(i == Idx ? 0 : 1);
7032 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7036 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7037 if (Values.size() == 1) {
7038 if (EVTBits == 32) {
7039 // Instead of a shuffle like this:
7040 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7041 // Check if it's possible to issue this instead.
7042 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7043 unsigned Idx = countTrailingZeros(NonZeros);
7044 SDValue Item = Op.getOperand(Idx);
7045 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7046 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7051 // A vector full of immediates; various special cases are already
7052 // handled, so this is best done with a single constant-pool load.
7056 // For AVX-length vectors, see if we can use a vector load to get all of the
7057 // elements, otherwise build the individual 128-bit pieces and use
7058 // shuffles to put them in place.
7059 if (VT.is256BitVector() || VT.is512BitVector()) {
7060 SmallVector<SDValue, 64> V;
7061 for (unsigned i = 0; i != NumElems; ++i)
7062 V.push_back(Op.getOperand(i));
7064 // Check for a build vector of consecutive loads.
7065 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7068 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7070 // Build both the lower and upper subvector.
7071 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7072 makeArrayRef(&V[0], NumElems/2));
7073 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7074 makeArrayRef(&V[NumElems / 2], NumElems/2));
7076 // Recreate the wider vector with the lower and upper part.
7077 if (VT.is256BitVector())
7078 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7079 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7082 // Let legalizer expand 2-wide build_vectors.
7083 if (EVTBits == 64) {
7084 if (NumNonZero == 1) {
7085 // One half is zero or undef.
7086 unsigned Idx = countTrailingZeros(NonZeros);
7087 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7088 Op.getOperand(Idx));
7089 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7094 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7095 if (EVTBits == 8 && NumElems == 16) {
7096 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7098 if (V.getNode()) return V;
7101 if (EVTBits == 16 && NumElems == 8) {
7102 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7104 if (V.getNode()) return V;
7107 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7108 if (EVTBits == 32 && NumElems == 4) {
7109 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7114 // If element VT is == 32 bits, turn it into a number of shuffles.
7115 SmallVector<SDValue, 8> V(NumElems);
7116 if (NumElems == 4 && NumZero > 0) {
7117 for (unsigned i = 0; i < 4; ++i) {
7118 bool isZero = !(NonZeros & (1 << i));
7120 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7122 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7125 for (unsigned i = 0; i < 2; ++i) {
7126 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7129 V[i] = V[i*2]; // Must be a zero vector.
7132 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7135 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7138 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7143 bool Reverse1 = (NonZeros & 0x3) == 2;
7144 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7148 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7149 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7151 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7154 if (Values.size() > 1 && VT.is128BitVector()) {
7155 // Check for a build vector of consecutive loads.
7156 for (unsigned i = 0; i < NumElems; ++i)
7157 V[i] = Op.getOperand(i);
7159 // Check for elements which are consecutive loads.
7160 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7164 // Check for a build vector from mostly shuffle plus few inserting.
7165 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7169 // For SSE 4.1, use insertps to put the high elements into the low element.
7170 if (getSubtarget()->hasSSE41()) {
7172 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7173 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7175 Result = DAG.getUNDEF(VT);
7177 for (unsigned i = 1; i < NumElems; ++i) {
7178 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7179 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7180 Op.getOperand(i), DAG.getIntPtrConstant(i));
7185 // Otherwise, expand into a number of unpckl*, start by extending each of
7186 // our (non-undef) elements to the full vector width with the element in the
7187 // bottom slot of the vector (which generates no code for SSE).
7188 for (unsigned i = 0; i < NumElems; ++i) {
7189 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7190 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7192 V[i] = DAG.getUNDEF(VT);
7195 // Next, we iteratively mix elements, e.g. for v4f32:
7196 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7197 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7198 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7199 unsigned EltStride = NumElems >> 1;
7200 while (EltStride != 0) {
7201 for (unsigned i = 0; i < EltStride; ++i) {
7202 // If V[i+EltStride] is undef and this is the first round of mixing,
7203 // then it is safe to just drop this shuffle: V[i] is already in the
7204 // right place, the one element (since it's the first round) being
7205 // inserted as undef can be dropped. This isn't safe for successive
7206 // rounds because they will permute elements within both vectors.
7207 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7208 EltStride == NumElems/2)
7211 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7220 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7221 // to create 256-bit vectors from two other 128-bit ones.
7222 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7224 MVT ResVT = Op.getSimpleValueType();
7226 assert((ResVT.is256BitVector() ||
7227 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7229 SDValue V1 = Op.getOperand(0);
7230 SDValue V2 = Op.getOperand(1);
7231 unsigned NumElems = ResVT.getVectorNumElements();
7232 if(ResVT.is256BitVector())
7233 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7235 if (Op.getNumOperands() == 4) {
7236 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7237 ResVT.getVectorNumElements()/2);
7238 SDValue V3 = Op.getOperand(2);
7239 SDValue V4 = Op.getOperand(3);
7240 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7241 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7243 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7246 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7247 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7248 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7249 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7250 Op.getNumOperands() == 4)));
7252 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7253 // from two other 128-bit ones.
7255 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7256 return LowerAVXCONCAT_VECTORS(Op, DAG);
7260 //===----------------------------------------------------------------------===//
7261 // Vector shuffle lowering
7263 // This is an experimental code path for lowering vector shuffles on x86. It is
7264 // designed to handle arbitrary vector shuffles and blends, gracefully
7265 // degrading performance as necessary. It works hard to recognize idiomatic
7266 // shuffles and lower them to optimal instruction patterns without leaving
7267 // a framework that allows reasonably efficient handling of all vector shuffle
7269 //===----------------------------------------------------------------------===//
7271 /// \brief Tiny helper function to identify a no-op mask.
7273 /// This is a somewhat boring predicate function. It checks whether the mask
7274 /// array input, which is assumed to be a single-input shuffle mask of the kind
7275 /// used by the X86 shuffle instructions (not a fully general
7276 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7277 /// in-place shuffle are 'no-op's.
7278 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7279 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7280 if (Mask[i] != -1 && Mask[i] != i)
7285 /// \brief Helper function to classify a mask as a single-input mask.
7287 /// This isn't a generic single-input test because in the vector shuffle
7288 /// lowering we canonicalize single inputs to be the first input operand. This
7289 /// means we can more quickly test for a single input by only checking whether
7290 /// an input from the second operand exists. We also assume that the size of
7291 /// mask corresponds to the size of the input vectors which isn't true in the
7292 /// fully general case.
7293 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7295 if (M >= (int)Mask.size())
7300 /// \brief Test whether there are elements crossing 128-bit lanes in this
7303 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7304 /// and we routinely test for these.
7305 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7306 int LaneSize = 128 / VT.getScalarSizeInBits();
7307 int Size = Mask.size();
7308 for (int i = 0; i < Size; ++i)
7309 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7314 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7316 /// This checks a shuffle mask to see if it is performing the same
7317 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7318 /// that it is also not lane-crossing. It may however involve a blend from the
7319 /// same lane of a second vector.
7321 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7322 /// non-trivial to compute in the face of undef lanes. The representation is
7323 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7324 /// entries from both V1 and V2 inputs to the wider mask.
7326 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7327 SmallVectorImpl<int> &RepeatedMask) {
7328 int LaneSize = 128 / VT.getScalarSizeInBits();
7329 RepeatedMask.resize(LaneSize, -1);
7330 int Size = Mask.size();
7331 for (int i = 0; i < Size; ++i) {
7334 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7335 // This entry crosses lanes, so there is no way to model this shuffle.
7338 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7339 if (RepeatedMask[i % LaneSize] == -1)
7340 // This is the first non-undef entry in this slot of a 128-bit lane.
7341 RepeatedMask[i % LaneSize] =
7342 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7343 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7344 // Found a mismatch with the repeated mask.
7350 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7351 // 2013 will allow us to use it as a non-type template parameter.
7354 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7356 /// See its documentation for details.
7357 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7358 if (Mask.size() != Args.size())
7360 for (int i = 0, e = Mask.size(); i < e; ++i) {
7361 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7362 if (Mask[i] != -1 && Mask[i] != *Args[i])
7370 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7373 /// This is a fast way to test a shuffle mask against a fixed pattern:
7375 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7377 /// It returns true if the mask is exactly as wide as the argument list, and
7378 /// each element of the mask is either -1 (signifying undef) or the value given
7379 /// in the argument.
7380 static const VariadicFunction1<
7381 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7383 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7385 /// This helper function produces an 8-bit shuffle immediate corresponding to
7386 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7387 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7390 /// NB: We rely heavily on "undef" masks preserving the input lane.
7391 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7392 SelectionDAG &DAG) {
7393 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7394 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7395 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7396 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7397 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7400 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7401 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7402 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7403 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7404 return DAG.getConstant(Imm, MVT::i8);
7407 /// \brief Try to emit a blend instruction for a shuffle.
7409 /// This doesn't do any checks for the availability of instructions for blending
7410 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7411 /// be matched in the backend with the type given. What it does check for is
7412 /// that the shuffle mask is in fact a blend.
7413 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7414 SDValue V2, ArrayRef<int> Mask,
7415 const X86Subtarget *Subtarget,
7416 SelectionDAG &DAG) {
7418 unsigned BlendMask = 0;
7419 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7420 if (Mask[i] >= Size) {
7421 if (Mask[i] != i + Size)
7422 return SDValue(); // Shuffled V2 input!
7423 BlendMask |= 1u << i;
7426 if (Mask[i] >= 0 && Mask[i] != i)
7427 return SDValue(); // Shuffled V1 input!
7429 switch (VT.SimpleTy) {
7434 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7435 DAG.getConstant(BlendMask, MVT::i8));
7439 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7443 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7444 // that instruction.
7445 if (Subtarget->hasAVX2()) {
7446 // Scale the blend by the number of 32-bit dwords per element.
7447 int Scale = VT.getScalarSizeInBits() / 32;
7449 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7450 if (Mask[i] >= Size)
7451 for (int j = 0; j < Scale; ++j)
7452 BlendMask |= 1u << (i * Scale + j);
7454 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7455 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7456 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7457 return DAG.getNode(ISD::BITCAST, DL, VT,
7458 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7459 DAG.getConstant(BlendMask, MVT::i8)));
7463 // For integer shuffles we need to expand the mask and cast the inputs to
7464 // v8i16s prior to blending.
7465 int Scale = 8 / VT.getVectorNumElements();
7467 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7468 if (Mask[i] >= Size)
7469 for (int j = 0; j < Scale; ++j)
7470 BlendMask |= 1u << (i * Scale + j);
7472 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7473 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7474 return DAG.getNode(ISD::BITCAST, DL, VT,
7475 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7476 DAG.getConstant(BlendMask, MVT::i8)));
7480 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7481 SmallVector<int, 8> RepeatedMask;
7482 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7483 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7484 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7486 for (int i = 0; i < 8; ++i)
7487 if (RepeatedMask[i] >= 16)
7488 BlendMask |= 1u << i;
7489 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7490 DAG.getConstant(BlendMask, MVT::i8));
7495 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7496 // Scale the blend by the number of bytes per element.
7497 int Scale = VT.getScalarSizeInBits() / 8;
7498 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7500 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7501 // mix of LLVM's code generator and the x86 backend. We tell the code
7502 // generator that boolean values in the elements of an x86 vector register
7503 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7504 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7505 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7506 // of the element (the remaining are ignored) and 0 in that high bit would
7507 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7508 // the LLVM model for boolean values in vector elements gets the relevant
7509 // bit set, it is set backwards and over constrained relative to x86's
7511 SDValue VSELECTMask[32];
7512 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7513 for (int j = 0; j < Scale; ++j)
7514 VSELECTMask[Scale * i + j] =
7515 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7516 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7518 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7519 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7521 ISD::BITCAST, DL, VT,
7522 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7523 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7528 llvm_unreachable("Not a supported integer vector type!");
7532 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7533 /// unblended shuffles followed by an unshuffled blend.
7535 /// This matches the extremely common pattern for handling combined
7536 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7538 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7542 SelectionDAG &DAG) {
7543 // Shuffle the input elements into the desired positions in V1 and V2 and
7544 // blend them together.
7545 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7546 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7547 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7548 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7549 if (Mask[i] >= 0 && Mask[i] < Size) {
7550 V1Mask[i] = Mask[i];
7552 } else if (Mask[i] >= Size) {
7553 V2Mask[i] = Mask[i] - Size;
7554 BlendMask[i] = i + Size;
7557 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7558 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7559 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7562 /// \brief Try to lower a vector shuffle as a byte rotation.
7564 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7565 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7566 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7567 /// try to generically lower a vector shuffle through such an pattern. It
7568 /// does not check for the profitability of lowering either as PALIGNR or
7569 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7570 /// This matches shuffle vectors that look like:
7572 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7574 /// Essentially it concatenates V1 and V2, shifts right by some number of
7575 /// elements, and takes the low elements as the result. Note that while this is
7576 /// specified as a *right shift* because x86 is little-endian, it is a *left
7577 /// rotate* of the vector lanes.
7579 /// Note that this only handles 128-bit vector widths currently.
7580 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7583 const X86Subtarget *Subtarget,
7584 SelectionDAG &DAG) {
7585 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7587 // We need to detect various ways of spelling a rotation:
7588 // [11, 12, 13, 14, 15, 0, 1, 2]
7589 // [-1, 12, 13, 14, -1, -1, 1, -1]
7590 // [-1, -1, -1, -1, -1, -1, 1, 2]
7591 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7592 // [-1, 4, 5, 6, -1, -1, 9, -1]
7593 // [-1, 4, 5, 6, -1, -1, -1, -1]
7596 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7599 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7601 // Based on the mod-Size value of this mask element determine where
7602 // a rotated vector would have started.
7603 int StartIdx = i - (Mask[i] % Size);
7605 // The identity rotation isn't interesting, stop.
7608 // If we found the tail of a vector the rotation must be the missing
7609 // front. If we found the head of a vector, it must be how much of the head.
7610 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7613 Rotation = CandidateRotation;
7614 else if (Rotation != CandidateRotation)
7615 // The rotations don't match, so we can't match this mask.
7618 // Compute which value this mask is pointing at.
7619 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7621 // Compute which of the two target values this index should be assigned to.
7622 // This reflects whether the high elements are remaining or the low elements
7624 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7626 // Either set up this value if we've not encountered it before, or check
7627 // that it remains consistent.
7630 else if (TargetV != MaskV)
7631 // This may be a rotation, but it pulls from the inputs in some
7632 // unsupported interleaving.
7636 // Check that we successfully analyzed the mask, and normalize the results.
7637 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7638 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7644 assert(VT.getSizeInBits() == 128 &&
7645 "Rotate-based lowering only supports 128-bit lowering!");
7646 assert(Mask.size() <= 16 &&
7647 "Can shuffle at most 16 bytes in a 128-bit vector!");
7649 // The actual rotate instruction rotates bytes, so we need to scale the
7650 // rotation based on how many bytes are in the vector.
7651 int Scale = 16 / Mask.size();
7653 // SSSE3 targets can use the palignr instruction
7654 if (Subtarget->hasSSSE3()) {
7655 // Cast the inputs to v16i8 to match PALIGNR.
7656 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7657 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7659 return DAG.getNode(ISD::BITCAST, DL, VT,
7660 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7661 DAG.getConstant(Rotation * Scale, MVT::i8)));
7664 // Default SSE2 implementation
7665 int LoByteShift = 16 - Rotation * Scale;
7666 int HiByteShift = Rotation * Scale;
7668 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7669 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7670 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7672 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7673 DAG.getConstant(8 * LoByteShift, MVT::i8));
7674 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7675 DAG.getConstant(8 * HiByteShift, MVT::i8));
7676 return DAG.getNode(ISD::BITCAST, DL, VT,
7677 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7680 /// \brief Compute whether each element of a shuffle is zeroable.
7682 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7683 /// Either it is an undef element in the shuffle mask, the element of the input
7684 /// referenced is undef, or the element of the input referenced is known to be
7685 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7686 /// as many lanes with this technique as possible to simplify the remaining
7688 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7689 SDValue V1, SDValue V2) {
7690 SmallBitVector Zeroable(Mask.size(), false);
7692 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7693 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7695 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7697 // Handle the easy cases.
7698 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7703 // If this is an index into a build_vector node, dig out the input value and
7705 SDValue V = M < Size ? V1 : V2;
7706 if (V.getOpcode() != ISD::BUILD_VECTOR)
7709 SDValue Input = V.getOperand(M % Size);
7710 // The UNDEF opcode check really should be dead code here, but not quite
7711 // worth asserting on (it isn't invalid, just unexpected).
7712 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7719 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7721 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7722 /// byte-shift instructions. The mask must consist of a shifted sequential
7723 /// shuffle from one of the input vectors and zeroable elements for the
7724 /// remaining 'shifted in' elements.
7726 /// Note that this only handles 128-bit vector widths currently.
7727 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7728 SDValue V2, ArrayRef<int> Mask,
7729 SelectionDAG &DAG) {
7730 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7732 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7734 int Size = Mask.size();
7735 int Scale = 16 / Size;
7737 for (int Shift = 1; Shift < Size; Shift++) {
7738 int ByteShift = Shift * Scale;
7740 // PSRLDQ : (little-endian) right byte shift
7741 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7742 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7743 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7744 bool ZeroableRight = true;
7745 for (int i = Size - Shift; i < Size; i++) {
7746 ZeroableRight &= Zeroable[i];
7749 if (ZeroableRight) {
7750 bool ValidShiftRight1 =
7751 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Shift);
7752 bool ValidShiftRight2 =
7753 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Size + Shift);
7755 if (ValidShiftRight1 || ValidShiftRight2) {
7756 // Cast the inputs to v2i64 to match PSRLDQ.
7757 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7758 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7759 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7760 DAG.getConstant(ByteShift * 8, MVT::i8));
7761 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7765 // PSLLDQ : (little-endian) left byte shift
7766 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7767 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7768 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7769 bool ZeroableLeft = true;
7770 for (int i = 0; i < Shift; i++) {
7771 ZeroableLeft &= Zeroable[i];
7775 bool ValidShiftLeft1 =
7776 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, 0);
7777 bool ValidShiftLeft2 =
7778 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, Size);
7780 if (ValidShiftLeft1 || ValidShiftLeft2) {
7781 // Cast the inputs to v2i64 to match PSLLDQ.
7782 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7783 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7784 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7785 DAG.getConstant(ByteShift * 8, MVT::i8));
7786 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7794 /// \brief Lower a vector shuffle as a zero or any extension.
7796 /// Given a specific number of elements, element bit width, and extension
7797 /// stride, produce either a zero or any extension based on the available
7798 /// features of the subtarget.
7799 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7800 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7801 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7802 assert(Scale > 1 && "Need a scale to extend.");
7803 int EltBits = VT.getSizeInBits() / NumElements;
7804 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7805 "Only 8, 16, and 32 bit elements can be extended.");
7806 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7808 // Found a valid zext mask! Try various lowering strategies based on the
7809 // input type and available ISA extensions.
7810 if (Subtarget->hasSSE41()) {
7811 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7812 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7813 NumElements / Scale);
7814 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7815 return DAG.getNode(ISD::BITCAST, DL, VT,
7816 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7819 // For any extends we can cheat for larger element sizes and use shuffle
7820 // instructions that can fold with a load and/or copy.
7821 if (AnyExt && EltBits == 32) {
7822 int PSHUFDMask[4] = {0, -1, 1, -1};
7824 ISD::BITCAST, DL, VT,
7825 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7826 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7827 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7829 if (AnyExt && EltBits == 16 && Scale > 2) {
7830 int PSHUFDMask[4] = {0, -1, 0, -1};
7831 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7832 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7833 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7834 int PSHUFHWMask[4] = {1, -1, -1, -1};
7836 ISD::BITCAST, DL, VT,
7837 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7838 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7839 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7842 // If this would require more than 2 unpack instructions to expand, use
7843 // pshufb when available. We can only use more than 2 unpack instructions
7844 // when zero extending i8 elements which also makes it easier to use pshufb.
7845 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7846 assert(NumElements == 16 && "Unexpected byte vector width!");
7847 SDValue PSHUFBMask[16];
7848 for (int i = 0; i < 16; ++i)
7850 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7851 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7852 return DAG.getNode(ISD::BITCAST, DL, VT,
7853 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7854 DAG.getNode(ISD::BUILD_VECTOR, DL,
7855 MVT::v16i8, PSHUFBMask)));
7858 // Otherwise emit a sequence of unpacks.
7860 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7861 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7862 : getZeroVector(InputVT, Subtarget, DAG, DL);
7863 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7864 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7868 } while (Scale > 1);
7869 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7872 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7874 /// This routine will try to do everything in its power to cleverly lower
7875 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7876 /// check for the profitability of this lowering, it tries to aggressively
7877 /// match this pattern. It will use all of the micro-architectural details it
7878 /// can to emit an efficient lowering. It handles both blends with all-zero
7879 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7880 /// masking out later).
7882 /// The reason we have dedicated lowering for zext-style shuffles is that they
7883 /// are both incredibly common and often quite performance sensitive.
7884 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7885 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7886 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7887 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7889 int Bits = VT.getSizeInBits();
7890 int NumElements = Mask.size();
7892 // Define a helper function to check a particular ext-scale and lower to it if
7894 auto Lower = [&](int Scale) -> SDValue {
7897 for (int i = 0; i < NumElements; ++i) {
7899 continue; // Valid anywhere but doesn't tell us anything.
7900 if (i % Scale != 0) {
7901 // Each of the extend elements needs to be zeroable.
7905 // We no lorger are in the anyext case.
7910 // Each of the base elements needs to be consecutive indices into the
7911 // same input vector.
7912 SDValue V = Mask[i] < NumElements ? V1 : V2;
7915 else if (InputV != V)
7916 return SDValue(); // Flip-flopping inputs.
7918 if (Mask[i] % NumElements != i / Scale)
7919 return SDValue(); // Non-consecutive strided elemenst.
7922 // If we fail to find an input, we have a zero-shuffle which should always
7923 // have already been handled.
7924 // FIXME: Maybe handle this here in case during blending we end up with one?
7928 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7929 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7932 // The widest scale possible for extending is to a 64-bit integer.
7933 assert(Bits % 64 == 0 &&
7934 "The number of bits in a vector must be divisible by 64 on x86!");
7935 int NumExtElements = Bits / 64;
7937 // Each iteration, try extending the elements half as much, but into twice as
7939 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7940 assert(NumElements % NumExtElements == 0 &&
7941 "The input vector size must be divisble by the extended size.");
7942 if (SDValue V = Lower(NumElements / NumExtElements))
7946 // No viable ext lowering found.
7950 /// \brief Try to get a scalar value for a specific element of a vector.
7952 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7953 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7954 SelectionDAG &DAG) {
7955 MVT VT = V.getSimpleValueType();
7956 MVT EltVT = VT.getVectorElementType();
7957 while (V.getOpcode() == ISD::BITCAST)
7958 V = V.getOperand(0);
7959 // If the bitcasts shift the element size, we can't extract an equivalent
7961 MVT NewVT = V.getSimpleValueType();
7962 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7965 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7966 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7967 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7972 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7974 /// This is particularly important because the set of instructions varies
7975 /// significantly based on whether the operand is a load or not.
7976 static bool isShuffleFoldableLoad(SDValue V) {
7977 while (V.getOpcode() == ISD::BITCAST)
7978 V = V.getOperand(0);
7980 return ISD::isNON_EXTLoad(V.getNode());
7983 /// \brief Try to lower insertion of a single element into a zero vector.
7985 /// This is a common pattern that we have especially efficient patterns to lower
7986 /// across all subtarget feature sets.
7987 static SDValue lowerVectorShuffleAsElementInsertion(
7988 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7989 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7990 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7992 MVT EltVT = VT.getVectorElementType();
7994 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7995 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7997 bool IsV1Zeroable = true;
7998 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7999 if (i != V2Index && !Zeroable[i]) {
8000 IsV1Zeroable = false;
8004 // Check for a single input from a SCALAR_TO_VECTOR node.
8005 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
8006 // all the smarts here sunk into that routine. However, the current
8007 // lowering of BUILD_VECTOR makes that nearly impossible until the old
8008 // vector shuffle lowering is dead.
8009 if (SDValue V2S = getScalarValueForVectorElement(
8010 V2, Mask[V2Index] - Mask.size(), DAG)) {
8011 // We need to zext the scalar if it is smaller than an i32.
8012 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8013 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8014 // Using zext to expand a narrow element won't work for non-zero
8019 // Zero-extend directly to i32.
8021 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8023 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8024 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8025 EltVT == MVT::i16) {
8026 // Either not inserting from the low element of the input or the input
8027 // element size is too small to use VZEXT_MOVL to clear the high bits.
8031 if (!IsV1Zeroable) {
8032 // If V1 can't be treated as a zero vector we have fewer options to lower
8033 // this. We can't support integer vectors or non-zero targets cheaply, and
8034 // the V1 elements can't be permuted in any way.
8035 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8036 if (!VT.isFloatingPoint() || V2Index != 0)
8038 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8039 V1Mask[V2Index] = -1;
8040 if (!isNoopShuffleMask(V1Mask))
8042 // This is essentially a special case blend operation, but if we have
8043 // general purpose blend operations, they are always faster. Bail and let
8044 // the rest of the lowering handle these as blends.
8045 if (Subtarget->hasSSE41())
8048 // Otherwise, use MOVSD or MOVSS.
8049 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8050 "Only two types of floating point element types to handle!");
8051 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8055 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8057 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8060 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8061 // the desired position. Otherwise it is more efficient to do a vector
8062 // shift left. We know that we can do a vector shift left because all
8063 // the inputs are zero.
8064 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8065 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8066 V2Shuffle[V2Index] = 0;
8067 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8069 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8071 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8073 V2Index * EltVT.getSizeInBits(),
8074 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8075 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8081 /// \brief Try to lower broadcast of a single element.
8083 /// For convenience, this code also bundles all of the subtarget feature set
8084 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8085 /// a convenient way to factor it out.
8086 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8088 const X86Subtarget *Subtarget,
8089 SelectionDAG &DAG) {
8090 if (!Subtarget->hasAVX())
8092 if (VT.isInteger() && !Subtarget->hasAVX2())
8095 // Check that the mask is a broadcast.
8096 int BroadcastIdx = -1;
8098 if (M >= 0 && BroadcastIdx == -1)
8100 else if (M >= 0 && M != BroadcastIdx)
8103 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8104 "a sorted mask where the broadcast "
8107 // Go up the chain of (vector) values to try and find a scalar load that
8108 // we can combine with the broadcast.
8110 switch (V.getOpcode()) {
8111 case ISD::CONCAT_VECTORS: {
8112 int OperandSize = Mask.size() / V.getNumOperands();
8113 V = V.getOperand(BroadcastIdx / OperandSize);
8114 BroadcastIdx %= OperandSize;
8118 case ISD::INSERT_SUBVECTOR: {
8119 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8120 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8124 int BeginIdx = (int)ConstantIdx->getZExtValue();
8126 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8127 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8128 BroadcastIdx -= BeginIdx;
8139 // Check if this is a broadcast of a scalar. We special case lowering
8140 // for scalars so that we can more effectively fold with loads.
8141 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8142 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8143 V = V.getOperand(BroadcastIdx);
8145 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8147 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8149 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8150 // We can't broadcast from a vector register w/o AVX2, and we can only
8151 // broadcast from the zero-element of a vector register.
8155 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8158 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8160 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8161 /// support for floating point shuffles but not integer shuffles. These
8162 /// instructions will incur a domain crossing penalty on some chips though so
8163 /// it is better to avoid lowering through this for integer vectors where
8165 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8166 const X86Subtarget *Subtarget,
8167 SelectionDAG &DAG) {
8169 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8170 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8171 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8173 ArrayRef<int> Mask = SVOp->getMask();
8174 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8176 if (isSingleInputShuffleMask(Mask)) {
8177 // Straight shuffle of a single input vector. Simulate this by using the
8178 // single input as both of the "inputs" to this instruction..
8179 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8181 if (Subtarget->hasAVX()) {
8182 // If we have AVX, we can use VPERMILPS which will allow folding a load
8183 // into the shuffle.
8184 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8185 DAG.getConstant(SHUFPDMask, MVT::i8));
8188 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8189 DAG.getConstant(SHUFPDMask, MVT::i8));
8191 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8192 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8194 // Use dedicated unpack instructions for masks that match their pattern.
8195 if (isShuffleEquivalent(Mask, 0, 2))
8196 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8197 if (isShuffleEquivalent(Mask, 1, 3))
8198 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8200 // If we have a single input, insert that into V1 if we can do so cheaply.
8201 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8202 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8203 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8205 // Try inverting the insertion since for v2 masks it is easy to do and we
8206 // can't reliably sort the mask one way or the other.
8207 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8208 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8209 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8210 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8214 // Try to use one of the special instruction patterns to handle two common
8215 // blend patterns if a zero-blend above didn't work.
8216 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8217 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8218 // We can either use a special instruction to load over the low double or
8219 // to move just the low double.
8221 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8223 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8225 if (Subtarget->hasSSE41())
8226 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8230 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8231 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8232 DAG.getConstant(SHUFPDMask, MVT::i8));
8235 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8237 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8238 /// the integer unit to minimize domain crossing penalties. However, for blends
8239 /// it falls back to the floating point shuffle operation with appropriate bit
8241 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8242 const X86Subtarget *Subtarget,
8243 SelectionDAG &DAG) {
8245 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8246 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8247 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8248 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8249 ArrayRef<int> Mask = SVOp->getMask();
8250 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8252 if (isSingleInputShuffleMask(Mask)) {
8253 // Check for being able to broadcast a single element.
8254 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8255 Mask, Subtarget, DAG))
8258 // Straight shuffle of a single input vector. For everything from SSE2
8259 // onward this has a single fast instruction with no scary immediates.
8260 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8261 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8262 int WidenedMask[4] = {
8263 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8264 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8266 ISD::BITCAST, DL, MVT::v2i64,
8267 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8268 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8271 // Try to use byte shift instructions.
8272 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8273 DL, MVT::v2i64, V1, V2, Mask, DAG))
8276 // If we have a single input from V2 insert that into V1 if we can do so
8278 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8279 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8280 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8282 // Try inverting the insertion since for v2 masks it is easy to do and we
8283 // can't reliably sort the mask one way or the other.
8284 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8285 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8286 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8287 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8291 // Use dedicated unpack instructions for masks that match their pattern.
8292 if (isShuffleEquivalent(Mask, 0, 2))
8293 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8294 if (isShuffleEquivalent(Mask, 1, 3))
8295 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8297 if (Subtarget->hasSSE41())
8298 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8302 // Try to use byte rotation instructions.
8303 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8304 if (Subtarget->hasSSSE3())
8305 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8306 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8309 // We implement this with SHUFPD which is pretty lame because it will likely
8310 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8311 // However, all the alternatives are still more cycles and newer chips don't
8312 // have this problem. It would be really nice if x86 had better shuffles here.
8313 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8314 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8315 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8316 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8319 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8321 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8322 /// It makes no assumptions about whether this is the *best* lowering, it simply
8324 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8325 ArrayRef<int> Mask, SDValue V1,
8326 SDValue V2, SelectionDAG &DAG) {
8327 SDValue LowV = V1, HighV = V2;
8328 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8331 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8333 if (NumV2Elements == 1) {
8335 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8338 // Compute the index adjacent to V2Index and in the same half by toggling
8340 int V2AdjIndex = V2Index ^ 1;
8342 if (Mask[V2AdjIndex] == -1) {
8343 // Handles all the cases where we have a single V2 element and an undef.
8344 // This will only ever happen in the high lanes because we commute the
8345 // vector otherwise.
8347 std::swap(LowV, HighV);
8348 NewMask[V2Index] -= 4;
8350 // Handle the case where the V2 element ends up adjacent to a V1 element.
8351 // To make this work, blend them together as the first step.
8352 int V1Index = V2AdjIndex;
8353 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8354 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8355 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8357 // Now proceed to reconstruct the final blend as we have the necessary
8358 // high or low half formed.
8365 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8366 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8368 } else if (NumV2Elements == 2) {
8369 if (Mask[0] < 4 && Mask[1] < 4) {
8370 // Handle the easy case where we have V1 in the low lanes and V2 in the
8374 } else if (Mask[2] < 4 && Mask[3] < 4) {
8375 // We also handle the reversed case because this utility may get called
8376 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8377 // arrange things in the right direction.
8383 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8384 // trying to place elements directly, just blend them and set up the final
8385 // shuffle to place them.
8387 // The first two blend mask elements are for V1, the second two are for
8389 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8390 Mask[2] < 4 ? Mask[2] : Mask[3],
8391 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8392 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8393 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8394 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8396 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8399 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8400 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8401 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8402 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8405 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8406 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8409 /// \brief Lower 4-lane 32-bit floating point shuffles.
8411 /// Uses instructions exclusively from the floating point unit to minimize
8412 /// domain crossing penalties, as these are sufficient to implement all v4f32
8414 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8415 const X86Subtarget *Subtarget,
8416 SelectionDAG &DAG) {
8418 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8419 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8420 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8421 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8422 ArrayRef<int> Mask = SVOp->getMask();
8423 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8426 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8428 if (NumV2Elements == 0) {
8429 // Check for being able to broadcast a single element.
8430 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8431 Mask, Subtarget, DAG))
8434 if (Subtarget->hasAVX()) {
8435 // If we have AVX, we can use VPERMILPS which will allow folding a load
8436 // into the shuffle.
8437 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8438 getV4X86ShuffleImm8ForMask(Mask, DAG));
8441 // Otherwise, use a straight shuffle of a single input vector. We pass the
8442 // input vector to both operands to simulate this with a SHUFPS.
8443 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8444 getV4X86ShuffleImm8ForMask(Mask, DAG));
8447 // Use dedicated unpack instructions for masks that match their pattern.
8448 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8449 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8450 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8451 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8453 // There are special ways we can lower some single-element blends. However, we
8454 // have custom ways we can lower more complex single-element blends below that
8455 // we defer to if both this and BLENDPS fail to match, so restrict this to
8456 // when the V2 input is targeting element 0 of the mask -- that is the fast
8458 if (NumV2Elements == 1 && Mask[0] >= 4)
8459 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8460 Mask, Subtarget, DAG))
8463 if (Subtarget->hasSSE41())
8464 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8468 // Check for whether we can use INSERTPS to perform the blend. We only use
8469 // INSERTPS when the V1 elements are already in the correct locations
8470 // because otherwise we can just always use two SHUFPS instructions which
8471 // are much smaller to encode than a SHUFPS and an INSERTPS.
8472 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8474 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8477 // When using INSERTPS we can zero any lane of the destination. Collect
8478 // the zero inputs into a mask and drop them from the lanes of V1 which
8479 // actually need to be present as inputs to the INSERTPS.
8480 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8482 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8483 bool InsertNeedsShuffle = false;
8485 for (int i = 0; i < 4; ++i)
8489 } else if (Mask[i] != i) {
8490 InsertNeedsShuffle = true;
8495 // We don't want to use INSERTPS or other insertion techniques if it will
8496 // require shuffling anyways.
8497 if (!InsertNeedsShuffle) {
8498 // If all of V1 is zeroable, replace it with undef.
8499 if ((ZMask | 1 << V2Index) == 0xF)
8500 V1 = DAG.getUNDEF(MVT::v4f32);
8502 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8503 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8505 // Insert the V2 element into the desired position.
8506 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8507 DAG.getConstant(InsertPSMask, MVT::i8));
8511 // Otherwise fall back to a SHUFPS lowering strategy.
8512 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8515 /// \brief Lower 4-lane i32 vector shuffles.
8517 /// We try to handle these with integer-domain shuffles where we can, but for
8518 /// blends we use the floating point domain blend instructions.
8519 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8520 const X86Subtarget *Subtarget,
8521 SelectionDAG &DAG) {
8523 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8524 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8525 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8526 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8527 ArrayRef<int> Mask = SVOp->getMask();
8528 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8530 // Whenever we can lower this as a zext, that instruction is strictly faster
8531 // than any alternative. It also allows us to fold memory operands into the
8532 // shuffle in many cases.
8533 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8534 Mask, Subtarget, DAG))
8538 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8540 if (NumV2Elements == 0) {
8541 // Check for being able to broadcast a single element.
8542 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8543 Mask, Subtarget, DAG))
8546 // Straight shuffle of a single input vector. For everything from SSE2
8547 // onward this has a single fast instruction with no scary immediates.
8548 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8549 // but we aren't actually going to use the UNPCK instruction because doing
8550 // so prevents folding a load into this instruction or making a copy.
8551 const int UnpackLoMask[] = {0, 0, 1, 1};
8552 const int UnpackHiMask[] = {2, 2, 3, 3};
8553 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8554 Mask = UnpackLoMask;
8555 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8556 Mask = UnpackHiMask;
8558 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8559 getV4X86ShuffleImm8ForMask(Mask, DAG));
8562 // Try to use byte shift instructions.
8563 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8564 DL, MVT::v4i32, V1, V2, Mask, DAG))
8567 // There are special ways we can lower some single-element blends.
8568 if (NumV2Elements == 1)
8569 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8570 Mask, Subtarget, DAG))
8573 // Use dedicated unpack instructions for masks that match their pattern.
8574 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8575 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8576 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8577 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8579 if (Subtarget->hasSSE41())
8580 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8584 // Try to use byte rotation instructions.
8585 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8586 if (Subtarget->hasSSSE3())
8587 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8588 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8591 // We implement this with SHUFPS because it can blend from two vectors.
8592 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8593 // up the inputs, bypassing domain shift penalties that we would encur if we
8594 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8596 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8597 DAG.getVectorShuffle(
8599 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8600 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8603 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8604 /// shuffle lowering, and the most complex part.
8606 /// The lowering strategy is to try to form pairs of input lanes which are
8607 /// targeted at the same half of the final vector, and then use a dword shuffle
8608 /// to place them onto the right half, and finally unpack the paired lanes into
8609 /// their final position.
8611 /// The exact breakdown of how to form these dword pairs and align them on the
8612 /// correct sides is really tricky. See the comments within the function for
8613 /// more of the details.
8614 static SDValue lowerV8I16SingleInputVectorShuffle(
8615 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8616 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8617 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8618 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8619 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8621 SmallVector<int, 4> LoInputs;
8622 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8623 [](int M) { return M >= 0; });
8624 std::sort(LoInputs.begin(), LoInputs.end());
8625 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8626 SmallVector<int, 4> HiInputs;
8627 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8628 [](int M) { return M >= 0; });
8629 std::sort(HiInputs.begin(), HiInputs.end());
8630 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8632 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8633 int NumHToL = LoInputs.size() - NumLToL;
8635 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8636 int NumHToH = HiInputs.size() - NumLToH;
8637 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8638 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8639 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8640 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8642 // Check for being able to broadcast a single element.
8643 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8644 Mask, Subtarget, DAG))
8647 // Try to use byte shift instructions.
8648 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8649 DL, MVT::v8i16, V, V, Mask, DAG))
8652 // Use dedicated unpack instructions for masks that match their pattern.
8653 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8654 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8655 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8656 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8658 // Try to use byte rotation instructions.
8659 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8660 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8663 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8664 // such inputs we can swap two of the dwords across the half mark and end up
8665 // with <=2 inputs to each half in each half. Once there, we can fall through
8666 // to the generic code below. For example:
8668 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8669 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8671 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8672 // and an existing 2-into-2 on the other half. In this case we may have to
8673 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8674 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8675 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8676 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8677 // half than the one we target for fixing) will be fixed when we re-enter this
8678 // path. We will also combine away any sequence of PSHUFD instructions that
8679 // result into a single instruction. Here is an example of the tricky case:
8681 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8682 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8684 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8686 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8687 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8689 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8690 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8692 // The result is fine to be handled by the generic logic.
8693 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8694 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8695 int AOffset, int BOffset) {
8696 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8697 "Must call this with A having 3 or 1 inputs from the A half.");
8698 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8699 "Must call this with B having 1 or 3 inputs from the B half.");
8700 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8701 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8703 // Compute the index of dword with only one word among the three inputs in
8704 // a half by taking the sum of the half with three inputs and subtracting
8705 // the sum of the actual three inputs. The difference is the remaining
8708 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8709 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8710 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8711 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8712 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8713 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8714 int TripleNonInputIdx =
8715 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8716 TripleDWord = TripleNonInputIdx / 2;
8718 // We use xor with one to compute the adjacent DWord to whichever one the
8720 OneInputDWord = (OneInput / 2) ^ 1;
8722 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8723 // and BToA inputs. If there is also such a problem with the BToB and AToB
8724 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8725 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8726 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8727 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8728 // Compute how many inputs will be flipped by swapping these DWords. We
8730 // to balance this to ensure we don't form a 3-1 shuffle in the other
8732 int NumFlippedAToBInputs =
8733 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8734 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8735 int NumFlippedBToBInputs =
8736 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8737 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8738 if ((NumFlippedAToBInputs == 1 &&
8739 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8740 (NumFlippedBToBInputs == 1 &&
8741 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8742 // We choose whether to fix the A half or B half based on whether that
8743 // half has zero flipped inputs. At zero, we may not be able to fix it
8744 // with that half. We also bias towards fixing the B half because that
8745 // will more commonly be the high half, and we have to bias one way.
8746 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8747 ArrayRef<int> Inputs) {
8748 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8749 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8750 PinnedIdx ^ 1) != Inputs.end();
8751 // Determine whether the free index is in the flipped dword or the
8752 // unflipped dword based on where the pinned index is. We use this bit
8753 // in an xor to conditionally select the adjacent dword.
8754 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8755 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8756 FixFreeIdx) != Inputs.end();
8757 if (IsFixIdxInput == IsFixFreeIdxInput)
8759 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8760 FixFreeIdx) != Inputs.end();
8761 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8762 "We need to be changing the number of flipped inputs!");
8763 int PSHUFHalfMask[] = {0, 1, 2, 3};
8764 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8765 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8767 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8770 if (M != -1 && M == FixIdx)
8772 else if (M != -1 && M == FixFreeIdx)
8775 if (NumFlippedBToBInputs != 0) {
8777 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8778 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8780 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8782 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8783 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8788 int PSHUFDMask[] = {0, 1, 2, 3};
8789 PSHUFDMask[ADWord] = BDWord;
8790 PSHUFDMask[BDWord] = ADWord;
8791 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8792 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8793 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8794 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8796 // Adjust the mask to match the new locations of A and B.
8798 if (M != -1 && M/2 == ADWord)
8799 M = 2 * BDWord + M % 2;
8800 else if (M != -1 && M/2 == BDWord)
8801 M = 2 * ADWord + M % 2;
8803 // Recurse back into this routine to re-compute state now that this isn't
8804 // a 3 and 1 problem.
8805 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8808 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8809 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8810 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8811 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8813 // At this point there are at most two inputs to the low and high halves from
8814 // each half. That means the inputs can always be grouped into dwords and
8815 // those dwords can then be moved to the correct half with a dword shuffle.
8816 // We use at most one low and one high word shuffle to collect these paired
8817 // inputs into dwords, and finally a dword shuffle to place them.
8818 int PSHUFLMask[4] = {-1, -1, -1, -1};
8819 int PSHUFHMask[4] = {-1, -1, -1, -1};
8820 int PSHUFDMask[4] = {-1, -1, -1, -1};
8822 // First fix the masks for all the inputs that are staying in their
8823 // original halves. This will then dictate the targets of the cross-half
8825 auto fixInPlaceInputs =
8826 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8827 MutableArrayRef<int> SourceHalfMask,
8828 MutableArrayRef<int> HalfMask, int HalfOffset) {
8829 if (InPlaceInputs.empty())
8831 if (InPlaceInputs.size() == 1) {
8832 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8833 InPlaceInputs[0] - HalfOffset;
8834 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8837 if (IncomingInputs.empty()) {
8838 // Just fix all of the in place inputs.
8839 for (int Input : InPlaceInputs) {
8840 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8841 PSHUFDMask[Input / 2] = Input / 2;
8846 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8847 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8848 InPlaceInputs[0] - HalfOffset;
8849 // Put the second input next to the first so that they are packed into
8850 // a dword. We find the adjacent index by toggling the low bit.
8851 int AdjIndex = InPlaceInputs[0] ^ 1;
8852 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8853 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8854 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8856 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8857 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8859 // Now gather the cross-half inputs and place them into a free dword of
8860 // their target half.
8861 // FIXME: This operation could almost certainly be simplified dramatically to
8862 // look more like the 3-1 fixing operation.
8863 auto moveInputsToRightHalf = [&PSHUFDMask](
8864 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8865 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8866 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8868 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8869 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8871 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8873 int LowWord = Word & ~1;
8874 int HighWord = Word | 1;
8875 return isWordClobbered(SourceHalfMask, LowWord) ||
8876 isWordClobbered(SourceHalfMask, HighWord);
8879 if (IncomingInputs.empty())
8882 if (ExistingInputs.empty()) {
8883 // Map any dwords with inputs from them into the right half.
8884 for (int Input : IncomingInputs) {
8885 // If the source half mask maps over the inputs, turn those into
8886 // swaps and use the swapped lane.
8887 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8888 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8889 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8890 Input - SourceOffset;
8891 // We have to swap the uses in our half mask in one sweep.
8892 for (int &M : HalfMask)
8893 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8895 else if (M == Input)
8896 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8898 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8899 Input - SourceOffset &&
8900 "Previous placement doesn't match!");
8902 // Note that this correctly re-maps both when we do a swap and when
8903 // we observe the other side of the swap above. We rely on that to
8904 // avoid swapping the members of the input list directly.
8905 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8908 // Map the input's dword into the correct half.
8909 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8910 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8912 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8914 "Previous placement doesn't match!");
8917 // And just directly shift any other-half mask elements to be same-half
8918 // as we will have mirrored the dword containing the element into the
8919 // same position within that half.
8920 for (int &M : HalfMask)
8921 if (M >= SourceOffset && M < SourceOffset + 4) {
8922 M = M - SourceOffset + DestOffset;
8923 assert(M >= 0 && "This should never wrap below zero!");
8928 // Ensure we have the input in a viable dword of its current half. This
8929 // is particularly tricky because the original position may be clobbered
8930 // by inputs being moved and *staying* in that half.
8931 if (IncomingInputs.size() == 1) {
8932 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8933 int InputFixed = std::find(std::begin(SourceHalfMask),
8934 std::end(SourceHalfMask), -1) -
8935 std::begin(SourceHalfMask) + SourceOffset;
8936 SourceHalfMask[InputFixed - SourceOffset] =
8937 IncomingInputs[0] - SourceOffset;
8938 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8940 IncomingInputs[0] = InputFixed;
8942 } else if (IncomingInputs.size() == 2) {
8943 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8944 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8945 // We have two non-adjacent or clobbered inputs we need to extract from
8946 // the source half. To do this, we need to map them into some adjacent
8947 // dword slot in the source mask.
8948 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8949 IncomingInputs[1] - SourceOffset};
8951 // If there is a free slot in the source half mask adjacent to one of
8952 // the inputs, place the other input in it. We use (Index XOR 1) to
8953 // compute an adjacent index.
8954 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8955 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8956 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8957 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8958 InputsFixed[1] = InputsFixed[0] ^ 1;
8959 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8960 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8961 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8962 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8963 InputsFixed[0] = InputsFixed[1] ^ 1;
8964 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8965 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8966 // The two inputs are in the same DWord but it is clobbered and the
8967 // adjacent DWord isn't used at all. Move both inputs to the free
8969 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8970 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8971 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8972 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8974 // The only way we hit this point is if there is no clobbering
8975 // (because there are no off-half inputs to this half) and there is no
8976 // free slot adjacent to one of the inputs. In this case, we have to
8977 // swap an input with a non-input.
8978 for (int i = 0; i < 4; ++i)
8979 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8980 "We can't handle any clobbers here!");
8981 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8982 "Cannot have adjacent inputs here!");
8984 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8985 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8987 // We also have to update the final source mask in this case because
8988 // it may need to undo the above swap.
8989 for (int &M : FinalSourceHalfMask)
8990 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8991 M = InputsFixed[1] + SourceOffset;
8992 else if (M == InputsFixed[1] + SourceOffset)
8993 M = (InputsFixed[0] ^ 1) + SourceOffset;
8995 InputsFixed[1] = InputsFixed[0] ^ 1;
8998 // Point everything at the fixed inputs.
8999 for (int &M : HalfMask)
9000 if (M == IncomingInputs[0])
9001 M = InputsFixed[0] + SourceOffset;
9002 else if (M == IncomingInputs[1])
9003 M = InputsFixed[1] + SourceOffset;
9005 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9006 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9009 llvm_unreachable("Unhandled input size!");
9012 // Now hoist the DWord down to the right half.
9013 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9014 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9015 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9016 for (int &M : HalfMask)
9017 for (int Input : IncomingInputs)
9019 M = FreeDWord * 2 + Input % 2;
9021 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9022 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9023 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9024 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9026 // Now enact all the shuffles we've computed to move the inputs into their
9028 if (!isNoopShuffleMask(PSHUFLMask))
9029 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9030 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9031 if (!isNoopShuffleMask(PSHUFHMask))
9032 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9033 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9034 if (!isNoopShuffleMask(PSHUFDMask))
9035 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9036 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9037 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9038 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9040 // At this point, each half should contain all its inputs, and we can then
9041 // just shuffle them into their final position.
9042 assert(std::count_if(LoMask.begin(), LoMask.end(),
9043 [](int M) { return M >= 4; }) == 0 &&
9044 "Failed to lift all the high half inputs to the low mask!");
9045 assert(std::count_if(HiMask.begin(), HiMask.end(),
9046 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9047 "Failed to lift all the low half inputs to the high mask!");
9049 // Do a half shuffle for the low mask.
9050 if (!isNoopShuffleMask(LoMask))
9051 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9052 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9054 // Do a half shuffle with the high mask after shifting its values down.
9055 for (int &M : HiMask)
9058 if (!isNoopShuffleMask(HiMask))
9059 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9060 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9065 /// \brief Detect whether the mask pattern should be lowered through
9068 /// This essentially tests whether viewing the mask as an interleaving of two
9069 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9070 /// lowering it through interleaving is a significantly better strategy.
9071 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9072 int NumEvenInputs[2] = {0, 0};
9073 int NumOddInputs[2] = {0, 0};
9074 int NumLoInputs[2] = {0, 0};
9075 int NumHiInputs[2] = {0, 0};
9076 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9080 int InputIdx = Mask[i] >= Size;
9083 ++NumLoInputs[InputIdx];
9085 ++NumHiInputs[InputIdx];
9088 ++NumEvenInputs[InputIdx];
9090 ++NumOddInputs[InputIdx];
9093 // The minimum number of cross-input results for both the interleaved and
9094 // split cases. If interleaving results in fewer cross-input results, return
9096 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9097 NumEvenInputs[0] + NumOddInputs[1]);
9098 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9099 NumLoInputs[0] + NumHiInputs[1]);
9100 return InterleavedCrosses < SplitCrosses;
9103 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9105 /// This strategy only works when the inputs from each vector fit into a single
9106 /// half of that vector, and generally there are not so many inputs as to leave
9107 /// the in-place shuffles required highly constrained (and thus expensive). It
9108 /// shifts all the inputs into a single side of both input vectors and then
9109 /// uses an unpack to interleave these inputs in a single vector. At that
9110 /// point, we will fall back on the generic single input shuffle lowering.
9111 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9113 MutableArrayRef<int> Mask,
9114 const X86Subtarget *Subtarget,
9115 SelectionDAG &DAG) {
9116 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9117 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9118 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9119 for (int i = 0; i < 8; ++i)
9120 if (Mask[i] >= 0 && Mask[i] < 4)
9121 LoV1Inputs.push_back(i);
9122 else if (Mask[i] >= 4 && Mask[i] < 8)
9123 HiV1Inputs.push_back(i);
9124 else if (Mask[i] >= 8 && Mask[i] < 12)
9125 LoV2Inputs.push_back(i);
9126 else if (Mask[i] >= 12)
9127 HiV2Inputs.push_back(i);
9129 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9130 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9133 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9134 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9135 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9137 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9138 HiV1Inputs.size() + HiV2Inputs.size();
9140 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9141 ArrayRef<int> HiInputs, bool MoveToLo,
9143 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9144 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9145 if (BadInputs.empty())
9148 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9149 int MoveOffset = MoveToLo ? 0 : 4;
9151 if (GoodInputs.empty()) {
9152 for (int BadInput : BadInputs) {
9153 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9154 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9157 if (GoodInputs.size() == 2) {
9158 // If the low inputs are spread across two dwords, pack them into
9160 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9161 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9162 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9163 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9165 // Otherwise pin the good inputs.
9166 for (int GoodInput : GoodInputs)
9167 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9170 if (BadInputs.size() == 2) {
9171 // If we have two bad inputs then there may be either one or two good
9172 // inputs fixed in place. Find a fixed input, and then find the *other*
9173 // two adjacent indices by using modular arithmetic.
9175 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9176 [](int M) { return M >= 0; }) -
9177 std::begin(MoveMask);
9179 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9180 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9181 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9182 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9183 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9184 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9185 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9187 assert(BadInputs.size() == 1 && "All sizes handled");
9188 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9189 std::end(MoveMask), -1) -
9190 std::begin(MoveMask);
9191 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9192 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9196 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9199 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9201 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9204 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9205 // cross-half traffic in the final shuffle.
9207 // Munge the mask to be a single-input mask after the unpack merges the
9211 M = 2 * (M % 4) + (M / 8);
9213 return DAG.getVectorShuffle(
9214 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9215 DL, MVT::v8i16, V1, V2),
9216 DAG.getUNDEF(MVT::v8i16), Mask);
9219 /// \brief Generic lowering of 8-lane i16 shuffles.
9221 /// This handles both single-input shuffles and combined shuffle/blends with
9222 /// two inputs. The single input shuffles are immediately delegated to
9223 /// a dedicated lowering routine.
9225 /// The blends are lowered in one of three fundamental ways. If there are few
9226 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9227 /// of the input is significantly cheaper when lowered as an interleaving of
9228 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9229 /// halves of the inputs separately (making them have relatively few inputs)
9230 /// and then concatenate them.
9231 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9232 const X86Subtarget *Subtarget,
9233 SelectionDAG &DAG) {
9235 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9236 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9237 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9238 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9239 ArrayRef<int> OrigMask = SVOp->getMask();
9240 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9241 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9242 MutableArrayRef<int> Mask(MaskStorage);
9244 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9246 // Whenever we can lower this as a zext, that instruction is strictly faster
9247 // than any alternative.
9248 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9249 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9252 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9253 auto isV2 = [](int M) { return M >= 8; };
9255 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9256 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9258 if (NumV2Inputs == 0)
9259 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9261 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9262 "to be V1-input shuffles.");
9264 // Try to use byte shift instructions.
9265 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9266 DL, MVT::v8i16, V1, V2, Mask, DAG))
9269 // There are special ways we can lower some single-element blends.
9270 if (NumV2Inputs == 1)
9271 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9272 Mask, Subtarget, DAG))
9275 // Use dedicated unpack instructions for masks that match their pattern.
9276 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9277 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9278 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9279 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9281 if (Subtarget->hasSSE41())
9282 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9286 // Try to use byte rotation instructions.
9287 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9288 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9291 if (NumV1Inputs + NumV2Inputs <= 4)
9292 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9294 // Check whether an interleaving lowering is likely to be more efficient.
9295 // This isn't perfect but it is a strong heuristic that tends to work well on
9296 // the kinds of shuffles that show up in practice.
9298 // FIXME: Handle 1x, 2x, and 4x interleaving.
9299 if (shouldLowerAsInterleaving(Mask)) {
9300 // FIXME: Figure out whether we should pack these into the low or high
9303 int EMask[8], OMask[8];
9304 for (int i = 0; i < 4; ++i) {
9305 EMask[i] = Mask[2*i];
9306 OMask[i] = Mask[2*i + 1];
9311 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9312 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9314 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9317 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9318 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9320 for (int i = 0; i < 4; ++i) {
9321 LoBlendMask[i] = Mask[i];
9322 HiBlendMask[i] = Mask[i + 4];
9325 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9326 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9327 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9328 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9330 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9331 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9334 /// \brief Check whether a compaction lowering can be done by dropping even
9335 /// elements and compute how many times even elements must be dropped.
9337 /// This handles shuffles which take every Nth element where N is a power of
9338 /// two. Example shuffle masks:
9340 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9341 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9342 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9343 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9344 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9345 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9347 /// Any of these lanes can of course be undef.
9349 /// This routine only supports N <= 3.
9350 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9353 /// \returns N above, or the number of times even elements must be dropped if
9354 /// there is such a number. Otherwise returns zero.
9355 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9356 // Figure out whether we're looping over two inputs or just one.
9357 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9359 // The modulus for the shuffle vector entries is based on whether this is
9360 // a single input or not.
9361 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9362 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9363 "We should only be called with masks with a power-of-2 size!");
9365 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9367 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9368 // and 2^3 simultaneously. This is because we may have ambiguity with
9369 // partially undef inputs.
9370 bool ViableForN[3] = {true, true, true};
9372 for (int i = 0, e = Mask.size(); i < e; ++i) {
9373 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9378 bool IsAnyViable = false;
9379 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9380 if (ViableForN[j]) {
9383 // The shuffle mask must be equal to (i * 2^N) % M.
9384 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9387 ViableForN[j] = false;
9389 // Early exit if we exhaust the possible powers of two.
9394 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9398 // Return 0 as there is no viable power of two.
9402 /// \brief Generic lowering of v16i8 shuffles.
9404 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9405 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9406 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9407 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9409 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9410 const X86Subtarget *Subtarget,
9411 SelectionDAG &DAG) {
9413 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9414 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9415 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9416 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9417 ArrayRef<int> OrigMask = SVOp->getMask();
9418 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9420 // Try to use byte shift instructions.
9421 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9422 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9425 // Try to use byte rotation instructions.
9426 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9427 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9430 // Try to use a zext lowering.
9431 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9432 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9435 int MaskStorage[16] = {
9436 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9437 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9438 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9439 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9440 MutableArrayRef<int> Mask(MaskStorage);
9441 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9442 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9445 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9447 // For single-input shuffles, there are some nicer lowering tricks we can use.
9448 if (NumV2Elements == 0) {
9449 // Check for being able to broadcast a single element.
9450 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9451 Mask, Subtarget, DAG))
9454 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9455 // Notably, this handles splat and partial-splat shuffles more efficiently.
9456 // However, it only makes sense if the pre-duplication shuffle simplifies
9457 // things significantly. Currently, this means we need to be able to
9458 // express the pre-duplication shuffle as an i16 shuffle.
9460 // FIXME: We should check for other patterns which can be widened into an
9461 // i16 shuffle as well.
9462 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9463 for (int i = 0; i < 16; i += 2)
9464 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9469 auto tryToWidenViaDuplication = [&]() -> SDValue {
9470 if (!canWidenViaDuplication(Mask))
9472 SmallVector<int, 4> LoInputs;
9473 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9474 [](int M) { return M >= 0 && M < 8; });
9475 std::sort(LoInputs.begin(), LoInputs.end());
9476 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9478 SmallVector<int, 4> HiInputs;
9479 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9480 [](int M) { return M >= 8; });
9481 std::sort(HiInputs.begin(), HiInputs.end());
9482 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9485 bool TargetLo = LoInputs.size() >= HiInputs.size();
9486 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9487 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9489 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9490 SmallDenseMap<int, int, 8> LaneMap;
9491 for (int I : InPlaceInputs) {
9492 PreDupI16Shuffle[I/2] = I/2;
9495 int j = TargetLo ? 0 : 4, je = j + 4;
9496 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9497 // Check if j is already a shuffle of this input. This happens when
9498 // there are two adjacent bytes after we move the low one.
9499 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9500 // If we haven't yet mapped the input, search for a slot into which
9502 while (j < je && PreDupI16Shuffle[j] != -1)
9506 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9509 // Map this input with the i16 shuffle.
9510 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9513 // Update the lane map based on the mapping we ended up with.
9514 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9517 ISD::BITCAST, DL, MVT::v16i8,
9518 DAG.getVectorShuffle(MVT::v8i16, DL,
9519 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9520 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9522 // Unpack the bytes to form the i16s that will be shuffled into place.
9523 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9524 MVT::v16i8, V1, V1);
9526 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9527 for (int i = 0; i < 16; ++i)
9528 if (Mask[i] != -1) {
9529 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9530 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9531 if (PostDupI16Shuffle[i / 2] == -1)
9532 PostDupI16Shuffle[i / 2] = MappedMask;
9534 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9535 "Conflicting entrties in the original shuffle!");
9538 ISD::BITCAST, DL, MVT::v16i8,
9539 DAG.getVectorShuffle(MVT::v8i16, DL,
9540 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9541 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9543 if (SDValue V = tryToWidenViaDuplication())
9547 // Check whether an interleaving lowering is likely to be more efficient.
9548 // This isn't perfect but it is a strong heuristic that tends to work well on
9549 // the kinds of shuffles that show up in practice.
9551 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9552 if (shouldLowerAsInterleaving(Mask)) {
9553 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9554 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9556 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9557 return (M >= 8 && M < 16) || M >= 24;
9559 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9560 -1, -1, -1, -1, -1, -1, -1, -1};
9561 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9562 -1, -1, -1, -1, -1, -1, -1, -1};
9563 bool UnpackLo = NumLoHalf >= NumHiHalf;
9564 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9565 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9566 for (int i = 0; i < 8; ++i) {
9567 TargetEMask[i] = Mask[2 * i];
9568 TargetOMask[i] = Mask[2 * i + 1];
9571 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9572 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9574 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9575 MVT::v16i8, Evens, Odds);
9578 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9579 // with PSHUFB. It is important to do this before we attempt to generate any
9580 // blends but after all of the single-input lowerings. If the single input
9581 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9582 // want to preserve that and we can DAG combine any longer sequences into
9583 // a PSHUFB in the end. But once we start blending from multiple inputs,
9584 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9585 // and there are *very* few patterns that would actually be faster than the
9586 // PSHUFB approach because of its ability to zero lanes.
9588 // FIXME: The only exceptions to the above are blends which are exact
9589 // interleavings with direct instructions supporting them. We currently don't
9590 // handle those well here.
9591 if (Subtarget->hasSSSE3()) {
9594 for (int i = 0; i < 16; ++i)
9595 if (Mask[i] == -1) {
9596 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9598 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9600 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9602 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9603 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9604 if (isSingleInputShuffleMask(Mask))
9605 return V1; // Single inputs are easy.
9607 // Otherwise, blend the two.
9608 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9609 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9610 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9613 // There are special ways we can lower some single-element blends.
9614 if (NumV2Elements == 1)
9615 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9616 Mask, Subtarget, DAG))
9619 // Check whether a compaction lowering can be done. This handles shuffles
9620 // which take every Nth element for some even N. See the helper function for
9623 // We special case these as they can be particularly efficiently handled with
9624 // the PACKUSB instruction on x86 and they show up in common patterns of
9625 // rearranging bytes to truncate wide elements.
9626 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9627 // NumEvenDrops is the power of two stride of the elements. Another way of
9628 // thinking about it is that we need to drop the even elements this many
9629 // times to get the original input.
9630 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9632 // First we need to zero all the dropped bytes.
9633 assert(NumEvenDrops <= 3 &&
9634 "No support for dropping even elements more than 3 times.");
9635 // We use the mask type to pick which bytes are preserved based on how many
9636 // elements are dropped.
9637 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9638 SDValue ByteClearMask =
9639 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9640 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9641 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9643 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9645 // Now pack things back together.
9646 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9647 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9648 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9649 for (int i = 1; i < NumEvenDrops; ++i) {
9650 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9651 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9657 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9658 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9659 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9660 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9662 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9663 MutableArrayRef<int> V1HalfBlendMask,
9664 MutableArrayRef<int> V2HalfBlendMask) {
9665 for (int i = 0; i < 8; ++i)
9666 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9667 V1HalfBlendMask[i] = HalfMask[i];
9669 } else if (HalfMask[i] >= 16) {
9670 V2HalfBlendMask[i] = HalfMask[i] - 16;
9671 HalfMask[i] = i + 8;
9674 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9675 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9677 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9679 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9680 MutableArrayRef<int> HiBlendMask) {
9682 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9683 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9685 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9686 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9687 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9688 [](int M) { return M >= 0 && M % 2 == 1; })) {
9689 // Use a mask to drop the high bytes.
9690 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9691 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9692 DAG.getConstant(0x00FF, MVT::v8i16));
9694 // This will be a single vector shuffle instead of a blend so nuke V2.
9695 V2 = DAG.getUNDEF(MVT::v8i16);
9697 // Squash the masks to point directly into V1.
9698 for (int &M : LoBlendMask)
9701 for (int &M : HiBlendMask)
9705 // Otherwise just unpack the low half of V into V1 and the high half into
9706 // V2 so that we can blend them as i16s.
9707 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9708 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9709 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9710 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9713 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9714 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9715 return std::make_pair(BlendedLo, BlendedHi);
9717 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9718 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9719 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9721 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9722 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9724 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9727 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9729 /// This routine breaks down the specific type of 128-bit shuffle and
9730 /// dispatches to the lowering routines accordingly.
9731 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9732 MVT VT, const X86Subtarget *Subtarget,
9733 SelectionDAG &DAG) {
9734 switch (VT.SimpleTy) {
9736 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9738 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9740 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9742 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9744 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9746 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9749 llvm_unreachable("Unimplemented!");
9753 /// \brief Helper function to test whether a shuffle mask could be
9754 /// simplified by widening the elements being shuffled.
9756 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9757 /// leaves it in an unspecified state.
9759 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9760 /// shuffle masks. The latter have the special property of a '-2' representing
9761 /// a zero-ed lane of a vector.
9762 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9763 SmallVectorImpl<int> &WidenedMask) {
9764 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9765 // If both elements are undef, its trivial.
9766 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9767 WidenedMask.push_back(SM_SentinelUndef);
9771 // Check for an undef mask and a mask value properly aligned to fit with
9772 // a pair of values. If we find such a case, use the non-undef mask's value.
9773 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9774 WidenedMask.push_back(Mask[i + 1] / 2);
9777 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9778 WidenedMask.push_back(Mask[i] / 2);
9782 // When zeroing, we need to spread the zeroing across both lanes to widen.
9783 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9784 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9785 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9786 WidenedMask.push_back(SM_SentinelZero);
9792 // Finally check if the two mask values are adjacent and aligned with
9794 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9795 WidenedMask.push_back(Mask[i] / 2);
9799 // Otherwise we can't safely widen the elements used in this shuffle.
9802 assert(WidenedMask.size() == Mask.size() / 2 &&
9803 "Incorrect size of mask after widening the elements!");
9808 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9810 /// This routine just extracts two subvectors, shuffles them independently, and
9811 /// then concatenates them back together. This should work effectively with all
9812 /// AVX vector shuffle types.
9813 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9814 SDValue V2, ArrayRef<int> Mask,
9815 SelectionDAG &DAG) {
9816 assert(VT.getSizeInBits() >= 256 &&
9817 "Only for 256-bit or wider vector shuffles!");
9818 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9819 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9821 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9822 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9824 int NumElements = VT.getVectorNumElements();
9825 int SplitNumElements = NumElements / 2;
9826 MVT ScalarVT = VT.getScalarType();
9827 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9829 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9830 DAG.getIntPtrConstant(0));
9831 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9832 DAG.getIntPtrConstant(SplitNumElements));
9833 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9834 DAG.getIntPtrConstant(0));
9835 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9836 DAG.getIntPtrConstant(SplitNumElements));
9838 // Now create two 4-way blends of these half-width vectors.
9839 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9840 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9841 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9842 for (int i = 0; i < SplitNumElements; ++i) {
9843 int M = HalfMask[i];
9844 if (M >= NumElements) {
9845 if (M >= NumElements + SplitNumElements)
9849 V2BlendMask.push_back(M - NumElements);
9850 V1BlendMask.push_back(-1);
9851 BlendMask.push_back(SplitNumElements + i);
9852 } else if (M >= 0) {
9853 if (M >= SplitNumElements)
9857 V2BlendMask.push_back(-1);
9858 V1BlendMask.push_back(M);
9859 BlendMask.push_back(i);
9861 V2BlendMask.push_back(-1);
9862 V1BlendMask.push_back(-1);
9863 BlendMask.push_back(-1);
9867 // Because the lowering happens after all combining takes place, we need to
9868 // manually combine these blend masks as much as possible so that we create
9869 // a minimal number of high-level vector shuffle nodes.
9871 // First try just blending the halves of V1 or V2.
9872 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9873 return DAG.getUNDEF(SplitVT);
9874 if (!UseLoV2 && !UseHiV2)
9875 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9876 if (!UseLoV1 && !UseHiV1)
9877 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9879 SDValue V1Blend, V2Blend;
9880 if (UseLoV1 && UseHiV1) {
9882 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9884 // We only use half of V1 so map the usage down into the final blend mask.
9885 V1Blend = UseLoV1 ? LoV1 : HiV1;
9886 for (int i = 0; i < SplitNumElements; ++i)
9887 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9888 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9890 if (UseLoV2 && UseHiV2) {
9892 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9894 // We only use half of V2 so map the usage down into the final blend mask.
9895 V2Blend = UseLoV2 ? LoV2 : HiV2;
9896 for (int i = 0; i < SplitNumElements; ++i)
9897 if (BlendMask[i] >= SplitNumElements)
9898 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9900 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9902 SDValue Lo = HalfBlend(LoMask);
9903 SDValue Hi = HalfBlend(HiMask);
9904 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9907 /// \brief Either split a vector in halves or decompose the shuffles and the
9910 /// This is provided as a good fallback for many lowerings of non-single-input
9911 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9912 /// between splitting the shuffle into 128-bit components and stitching those
9913 /// back together vs. extracting the single-input shuffles and blending those
9915 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9916 SDValue V2, ArrayRef<int> Mask,
9917 SelectionDAG &DAG) {
9918 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9919 "lower single-input shuffles as it "
9920 "could then recurse on itself.");
9921 int Size = Mask.size();
9923 // If this can be modeled as a broadcast of two elements followed by a blend,
9924 // prefer that lowering. This is especially important because broadcasts can
9925 // often fold with memory operands.
9926 auto DoBothBroadcast = [&] {
9927 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9930 if (V2BroadcastIdx == -1)
9931 V2BroadcastIdx = M - Size;
9932 else if (M - Size != V2BroadcastIdx)
9934 } else if (M >= 0) {
9935 if (V1BroadcastIdx == -1)
9937 else if (M != V1BroadcastIdx)
9942 if (DoBothBroadcast())
9943 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9946 // If the inputs all stem from a single 128-bit lane of each input, then we
9947 // split them rather than blending because the split will decompose to
9948 // unusually few instructions.
9949 int LaneCount = VT.getSizeInBits() / 128;
9950 int LaneSize = Size / LaneCount;
9951 SmallBitVector LaneInputs[2];
9952 LaneInputs[0].resize(LaneCount, false);
9953 LaneInputs[1].resize(LaneCount, false);
9954 for (int i = 0; i < Size; ++i)
9956 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9957 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9958 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9960 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9961 // that the decomposed single-input shuffles don't end up here.
9962 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9965 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9966 /// a permutation and blend of those lanes.
9968 /// This essentially blends the out-of-lane inputs to each lane into the lane
9969 /// from a permuted copy of the vector. This lowering strategy results in four
9970 /// instructions in the worst case for a single-input cross lane shuffle which
9971 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9972 /// of. Special cases for each particular shuffle pattern should be handled
9973 /// prior to trying this lowering.
9974 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9975 SDValue V1, SDValue V2,
9977 SelectionDAG &DAG) {
9978 // FIXME: This should probably be generalized for 512-bit vectors as well.
9979 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9980 int LaneSize = Mask.size() / 2;
9982 // If there are only inputs from one 128-bit lane, splitting will in fact be
9983 // less expensive. The flags track wether the given lane contains an element
9984 // that crosses to another lane.
9985 bool LaneCrossing[2] = {false, false};
9986 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9987 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9988 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9989 if (!LaneCrossing[0] || !LaneCrossing[1])
9990 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9992 if (isSingleInputShuffleMask(Mask)) {
9993 SmallVector<int, 32> FlippedBlendMask;
9994 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9995 FlippedBlendMask.push_back(
9996 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9998 : Mask[i] % LaneSize +
9999 (i / LaneSize) * LaneSize + Size));
10001 // Flip the vector, and blend the results which should now be in-lane. The
10002 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10003 // 5 for the high source. The value 3 selects the high half of source 2 and
10004 // the value 2 selects the low half of source 2. We only use source 2 to
10005 // allow folding it into a memory operand.
10006 unsigned PERMMask = 3 | 2 << 4;
10007 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10008 V1, DAG.getConstant(PERMMask, MVT::i8));
10009 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10012 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10013 // will be handled by the above logic and a blend of the results, much like
10014 // other patterns in AVX.
10015 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10018 /// \brief Handle lowering 2-lane 128-bit shuffles.
10019 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10020 SDValue V2, ArrayRef<int> Mask,
10021 const X86Subtarget *Subtarget,
10022 SelectionDAG &DAG) {
10023 // Blends are faster and handle all the non-lane-crossing cases.
10024 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10028 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10029 VT.getVectorNumElements() / 2);
10030 // Check for patterns which can be matched with a single insert of a 128-bit
10032 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10033 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10034 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10035 DAG.getIntPtrConstant(0));
10036 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10037 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10038 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10040 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10041 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10042 DAG.getIntPtrConstant(0));
10043 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10044 DAG.getIntPtrConstant(2));
10045 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10048 // Otherwise form a 128-bit permutation.
10049 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10050 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10051 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10052 DAG.getConstant(PermMask, MVT::i8));
10055 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10056 /// shuffling each lane.
10058 /// This will only succeed when the result of fixing the 128-bit lanes results
10059 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10060 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10061 /// the lane crosses early and then use simpler shuffles within each lane.
10063 /// FIXME: It might be worthwhile at some point to support this without
10064 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10065 /// in x86 only floating point has interesting non-repeating shuffles, and even
10066 /// those are still *marginally* more expensive.
10067 static SDValue lowerVectorShuffleByMerging128BitLanes(
10068 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10069 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10070 assert(!isSingleInputShuffleMask(Mask) &&
10071 "This is only useful with multiple inputs.");
10073 int Size = Mask.size();
10074 int LaneSize = 128 / VT.getScalarSizeInBits();
10075 int NumLanes = Size / LaneSize;
10076 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10078 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10079 // check whether the in-128-bit lane shuffles share a repeating pattern.
10080 SmallVector<int, 4> Lanes;
10081 Lanes.resize(NumLanes, -1);
10082 SmallVector<int, 4> InLaneMask;
10083 InLaneMask.resize(LaneSize, -1);
10084 for (int i = 0; i < Size; ++i) {
10088 int j = i / LaneSize;
10090 if (Lanes[j] < 0) {
10091 // First entry we've seen for this lane.
10092 Lanes[j] = Mask[i] / LaneSize;
10093 } else if (Lanes[j] != Mask[i] / LaneSize) {
10094 // This doesn't match the lane selected previously!
10098 // Check that within each lane we have a consistent shuffle mask.
10099 int k = i % LaneSize;
10100 if (InLaneMask[k] < 0) {
10101 InLaneMask[k] = Mask[i] % LaneSize;
10102 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10103 // This doesn't fit a repeating in-lane mask.
10108 // First shuffle the lanes into place.
10109 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10110 VT.getSizeInBits() / 64);
10111 SmallVector<int, 8> LaneMask;
10112 LaneMask.resize(NumLanes * 2, -1);
10113 for (int i = 0; i < NumLanes; ++i)
10114 if (Lanes[i] >= 0) {
10115 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10116 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10119 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10120 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10121 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10123 // Cast it back to the type we actually want.
10124 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10126 // Now do a simple shuffle that isn't lane crossing.
10127 SmallVector<int, 8> NewMask;
10128 NewMask.resize(Size, -1);
10129 for (int i = 0; i < Size; ++i)
10131 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10132 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10133 "Must not introduce lane crosses at this point!");
10135 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10138 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10141 /// This returns true if the elements from a particular input are already in the
10142 /// slot required by the given mask and require no permutation.
10143 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10144 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10145 int Size = Mask.size();
10146 for (int i = 0; i < Size; ++i)
10147 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10153 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10155 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10156 /// isn't available.
10157 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10158 const X86Subtarget *Subtarget,
10159 SelectionDAG &DAG) {
10161 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10162 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10164 ArrayRef<int> Mask = SVOp->getMask();
10165 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10167 SmallVector<int, 4> WidenedMask;
10168 if (canWidenShuffleElements(Mask, WidenedMask))
10169 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10172 if (isSingleInputShuffleMask(Mask)) {
10173 // Check for being able to broadcast a single element.
10174 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10175 Mask, Subtarget, DAG))
10178 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10179 // Non-half-crossing single input shuffles can be lowerid with an
10180 // interleaved permutation.
10181 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10182 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10183 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10184 DAG.getConstant(VPERMILPMask, MVT::i8));
10187 // With AVX2 we have direct support for this permutation.
10188 if (Subtarget->hasAVX2())
10189 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10190 getV4X86ShuffleImm8ForMask(Mask, DAG));
10192 // Otherwise, fall back.
10193 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10197 // X86 has dedicated unpack instructions that can handle specific blend
10198 // operations: UNPCKH and UNPCKL.
10199 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10200 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10201 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10202 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10204 // If we have a single input to the zero element, insert that into V1 if we
10205 // can do so cheaply.
10206 int NumV2Elements =
10207 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10208 if (NumV2Elements == 1 && Mask[0] >= 4)
10209 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10210 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10213 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10217 // Check if the blend happens to exactly fit that of SHUFPD.
10218 if ((Mask[0] == -1 || Mask[0] < 2) &&
10219 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10220 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10221 (Mask[3] == -1 || Mask[3] >= 6)) {
10222 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10223 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10224 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10225 DAG.getConstant(SHUFPDMask, MVT::i8));
10227 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10228 (Mask[1] == -1 || Mask[1] < 2) &&
10229 (Mask[2] == -1 || Mask[2] >= 6) &&
10230 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10231 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10232 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10233 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10234 DAG.getConstant(SHUFPDMask, MVT::i8));
10237 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10238 // shuffle. However, if we have AVX2 and either inputs are already in place,
10239 // we will be able to shuffle even across lanes the other input in a single
10240 // instruction so skip this pattern.
10241 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10242 isShuffleMaskInputInPlace(1, Mask))))
10243 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10244 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10247 // If we have AVX2 then we always want to lower with a blend because an v4 we
10248 // can fully permute the elements.
10249 if (Subtarget->hasAVX2())
10250 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10253 // Otherwise fall back on generic lowering.
10254 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10257 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10259 /// This routine is only called when we have AVX2 and thus a reasonable
10260 /// instruction set for v4i64 shuffling..
10261 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10262 const X86Subtarget *Subtarget,
10263 SelectionDAG &DAG) {
10265 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10266 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10267 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10268 ArrayRef<int> Mask = SVOp->getMask();
10269 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10270 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10272 SmallVector<int, 4> WidenedMask;
10273 if (canWidenShuffleElements(Mask, WidenedMask))
10274 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10277 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10281 // Check for being able to broadcast a single element.
10282 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10283 Mask, Subtarget, DAG))
10286 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10287 // use lower latency instructions that will operate on both 128-bit lanes.
10288 SmallVector<int, 2> RepeatedMask;
10289 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10290 if (isSingleInputShuffleMask(Mask)) {
10291 int PSHUFDMask[] = {-1, -1, -1, -1};
10292 for (int i = 0; i < 2; ++i)
10293 if (RepeatedMask[i] >= 0) {
10294 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10295 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10297 return DAG.getNode(
10298 ISD::BITCAST, DL, MVT::v4i64,
10299 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10300 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10301 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10304 // Use dedicated unpack instructions for masks that match their pattern.
10305 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10306 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10307 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10308 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10311 // AVX2 provides a direct instruction for permuting a single input across
10313 if (isSingleInputShuffleMask(Mask))
10314 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10315 getV4X86ShuffleImm8ForMask(Mask, DAG));
10317 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10318 // shuffle. However, if we have AVX2 and either inputs are already in place,
10319 // we will be able to shuffle even across lanes the other input in a single
10320 // instruction so skip this pattern.
10321 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10322 isShuffleMaskInputInPlace(1, Mask))))
10323 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10324 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10327 // Otherwise fall back on generic blend lowering.
10328 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10332 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10334 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10335 /// isn't available.
10336 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10337 const X86Subtarget *Subtarget,
10338 SelectionDAG &DAG) {
10340 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10341 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10342 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10343 ArrayRef<int> Mask = SVOp->getMask();
10344 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10346 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10350 // Check for being able to broadcast a single element.
10351 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10352 Mask, Subtarget, DAG))
10355 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10356 // options to efficiently lower the shuffle.
10357 SmallVector<int, 4> RepeatedMask;
10358 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10359 assert(RepeatedMask.size() == 4 &&
10360 "Repeated masks must be half the mask width!");
10361 if (isSingleInputShuffleMask(Mask))
10362 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10363 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10365 // Use dedicated unpack instructions for masks that match their pattern.
10366 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10367 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10368 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10369 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10371 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10372 // have already handled any direct blends. We also need to squash the
10373 // repeated mask into a simulated v4f32 mask.
10374 for (int i = 0; i < 4; ++i)
10375 if (RepeatedMask[i] >= 8)
10376 RepeatedMask[i] -= 4;
10377 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10380 // If we have a single input shuffle with different shuffle patterns in the
10381 // two 128-bit lanes use the variable mask to VPERMILPS.
10382 if (isSingleInputShuffleMask(Mask)) {
10383 SDValue VPermMask[8];
10384 for (int i = 0; i < 8; ++i)
10385 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10386 : DAG.getConstant(Mask[i], MVT::i32);
10387 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10388 return DAG.getNode(
10389 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10390 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10392 if (Subtarget->hasAVX2())
10393 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10394 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10395 DAG.getNode(ISD::BUILD_VECTOR, DL,
10396 MVT::v8i32, VPermMask)),
10399 // Otherwise, fall back.
10400 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10404 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10406 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10407 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10410 // If we have AVX2 then we always want to lower with a blend because at v8 we
10411 // can fully permute the elements.
10412 if (Subtarget->hasAVX2())
10413 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10416 // Otherwise fall back on generic lowering.
10417 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10420 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10422 /// This routine is only called when we have AVX2 and thus a reasonable
10423 /// instruction set for v8i32 shuffling..
10424 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10425 const X86Subtarget *Subtarget,
10426 SelectionDAG &DAG) {
10428 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10429 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10430 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10431 ArrayRef<int> Mask = SVOp->getMask();
10432 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10433 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10435 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10439 // Check for being able to broadcast a single element.
10440 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10441 Mask, Subtarget, DAG))
10444 // If the shuffle mask is repeated in each 128-bit lane we can use more
10445 // efficient instructions that mirror the shuffles across the two 128-bit
10447 SmallVector<int, 4> RepeatedMask;
10448 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10449 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10450 if (isSingleInputShuffleMask(Mask))
10451 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10452 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10454 // Use dedicated unpack instructions for masks that match their pattern.
10455 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10456 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10457 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10458 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10461 // If the shuffle patterns aren't repeated but it is a single input, directly
10462 // generate a cross-lane VPERMD instruction.
10463 if (isSingleInputShuffleMask(Mask)) {
10464 SDValue VPermMask[8];
10465 for (int i = 0; i < 8; ++i)
10466 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10467 : DAG.getConstant(Mask[i], MVT::i32);
10468 return DAG.getNode(
10469 X86ISD::VPERMV, DL, MVT::v8i32,
10470 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10473 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10475 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10476 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10479 // Otherwise fall back on generic blend lowering.
10480 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10484 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10486 /// This routine is only called when we have AVX2 and thus a reasonable
10487 /// instruction set for v16i16 shuffling..
10488 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10489 const X86Subtarget *Subtarget,
10490 SelectionDAG &DAG) {
10492 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10493 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10494 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10495 ArrayRef<int> Mask = SVOp->getMask();
10496 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10497 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10499 // Check for being able to broadcast a single element.
10500 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10501 Mask, Subtarget, DAG))
10504 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10508 // Use dedicated unpack instructions for masks that match their pattern.
10509 if (isShuffleEquivalent(Mask,
10510 // First 128-bit lane:
10511 0, 16, 1, 17, 2, 18, 3, 19,
10512 // Second 128-bit lane:
10513 8, 24, 9, 25, 10, 26, 11, 27))
10514 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10515 if (isShuffleEquivalent(Mask,
10516 // First 128-bit lane:
10517 4, 20, 5, 21, 6, 22, 7, 23,
10518 // Second 128-bit lane:
10519 12, 28, 13, 29, 14, 30, 15, 31))
10520 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10522 if (isSingleInputShuffleMask(Mask)) {
10523 // There are no generalized cross-lane shuffle operations available on i16
10525 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10526 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10529 SDValue PSHUFBMask[32];
10530 for (int i = 0; i < 16; ++i) {
10531 if (Mask[i] == -1) {
10532 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10536 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10537 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10538 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10539 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10541 return DAG.getNode(
10542 ISD::BITCAST, DL, MVT::v16i16,
10544 X86ISD::PSHUFB, DL, MVT::v32i8,
10545 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10546 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10549 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10551 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10552 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10555 // Otherwise fall back on generic lowering.
10556 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10559 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10561 /// This routine is only called when we have AVX2 and thus a reasonable
10562 /// instruction set for v32i8 shuffling..
10563 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10564 const X86Subtarget *Subtarget,
10565 SelectionDAG &DAG) {
10567 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10568 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10569 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10570 ArrayRef<int> Mask = SVOp->getMask();
10571 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10572 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10574 // Check for being able to broadcast a single element.
10575 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10576 Mask, Subtarget, DAG))
10579 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10583 // Use dedicated unpack instructions for masks that match their pattern.
10584 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10586 if (isShuffleEquivalent(
10588 // First 128-bit lane:
10589 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10590 // Second 128-bit lane:
10591 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10592 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10593 if (isShuffleEquivalent(
10595 // First 128-bit lane:
10596 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10597 // Second 128-bit lane:
10598 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10599 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10601 if (isSingleInputShuffleMask(Mask)) {
10602 // There are no generalized cross-lane shuffle operations available on i8
10604 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10605 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10608 SDValue PSHUFBMask[32];
10609 for (int i = 0; i < 32; ++i)
10612 ? DAG.getUNDEF(MVT::i8)
10613 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10615 return DAG.getNode(
10616 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10617 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10620 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10622 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10623 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10626 // Otherwise fall back on generic lowering.
10627 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10630 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10632 /// This routine either breaks down the specific type of a 256-bit x86 vector
10633 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10634 /// together based on the available instructions.
10635 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10636 MVT VT, const X86Subtarget *Subtarget,
10637 SelectionDAG &DAG) {
10639 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10640 ArrayRef<int> Mask = SVOp->getMask();
10642 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10643 // check for those subtargets here and avoid much of the subtarget querying in
10644 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10645 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10646 // floating point types there eventually, just immediately cast everything to
10647 // a float and operate entirely in that domain.
10648 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10649 int ElementBits = VT.getScalarSizeInBits();
10650 if (ElementBits < 32)
10651 // No floating point type available, decompose into 128-bit vectors.
10652 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10654 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10655 VT.getVectorNumElements());
10656 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10657 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10658 return DAG.getNode(ISD::BITCAST, DL, VT,
10659 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10662 switch (VT.SimpleTy) {
10664 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10666 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10668 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10670 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10672 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10674 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10677 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10681 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10682 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10683 const X86Subtarget *Subtarget,
10684 SelectionDAG &DAG) {
10686 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10687 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10688 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10689 ArrayRef<int> Mask = SVOp->getMask();
10690 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10692 // FIXME: Implement direct support for this type!
10693 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10696 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10697 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10698 const X86Subtarget *Subtarget,
10699 SelectionDAG &DAG) {
10701 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10702 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10704 ArrayRef<int> Mask = SVOp->getMask();
10705 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10707 // FIXME: Implement direct support for this type!
10708 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10711 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10712 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10713 const X86Subtarget *Subtarget,
10714 SelectionDAG &DAG) {
10716 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10717 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10718 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10719 ArrayRef<int> Mask = SVOp->getMask();
10720 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10722 // FIXME: Implement direct support for this type!
10723 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10726 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10727 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10728 const X86Subtarget *Subtarget,
10729 SelectionDAG &DAG) {
10731 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10732 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10733 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10734 ArrayRef<int> Mask = SVOp->getMask();
10735 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10737 // FIXME: Implement direct support for this type!
10738 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10741 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10742 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10743 const X86Subtarget *Subtarget,
10744 SelectionDAG &DAG) {
10746 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10747 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10748 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10749 ArrayRef<int> Mask = SVOp->getMask();
10750 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10751 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10753 // FIXME: Implement direct support for this type!
10754 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10757 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10758 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10759 const X86Subtarget *Subtarget,
10760 SelectionDAG &DAG) {
10762 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10763 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10764 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10765 ArrayRef<int> Mask = SVOp->getMask();
10766 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10767 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10769 // FIXME: Implement direct support for this type!
10770 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10773 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10775 /// This routine either breaks down the specific type of a 512-bit x86 vector
10776 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10777 /// together based on the available instructions.
10778 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10779 MVT VT, const X86Subtarget *Subtarget,
10780 SelectionDAG &DAG) {
10782 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10783 ArrayRef<int> Mask = SVOp->getMask();
10784 assert(Subtarget->hasAVX512() &&
10785 "Cannot lower 512-bit vectors w/ basic ISA!");
10787 // Check for being able to broadcast a single element.
10788 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10789 Mask, Subtarget, DAG))
10792 // Dispatch to each element type for lowering. If we don't have supprot for
10793 // specific element type shuffles at 512 bits, immediately split them and
10794 // lower them. Each lowering routine of a given type is allowed to assume that
10795 // the requisite ISA extensions for that element type are available.
10796 switch (VT.SimpleTy) {
10798 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10800 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10802 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10804 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10806 if (Subtarget->hasBWI())
10807 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10810 if (Subtarget->hasBWI())
10811 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10815 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10818 // Otherwise fall back on splitting.
10819 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10822 /// \brief Top-level lowering for x86 vector shuffles.
10824 /// This handles decomposition, canonicalization, and lowering of all x86
10825 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10826 /// above in helper routines. The canonicalization attempts to widen shuffles
10827 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10828 /// s.t. only one of the two inputs needs to be tested, etc.
10829 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10830 SelectionDAG &DAG) {
10831 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10832 ArrayRef<int> Mask = SVOp->getMask();
10833 SDValue V1 = Op.getOperand(0);
10834 SDValue V2 = Op.getOperand(1);
10835 MVT VT = Op.getSimpleValueType();
10836 int NumElements = VT.getVectorNumElements();
10839 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10841 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10842 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10843 if (V1IsUndef && V2IsUndef)
10844 return DAG.getUNDEF(VT);
10846 // When we create a shuffle node we put the UNDEF node to second operand,
10847 // but in some cases the first operand may be transformed to UNDEF.
10848 // In this case we should just commute the node.
10850 return DAG.getCommutedVectorShuffle(*SVOp);
10852 // Check for non-undef masks pointing at an undef vector and make the masks
10853 // undef as well. This makes it easier to match the shuffle based solely on
10857 if (M >= NumElements) {
10858 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10859 for (int &M : NewMask)
10860 if (M >= NumElements)
10862 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10865 // Try to collapse shuffles into using a vector type with fewer elements but
10866 // wider element types. We cap this to not form integers or floating point
10867 // elements wider than 64 bits, but it might be interesting to form i128
10868 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10869 SmallVector<int, 16> WidenedMask;
10870 if (VT.getScalarSizeInBits() < 64 &&
10871 canWidenShuffleElements(Mask, WidenedMask)) {
10872 MVT NewEltVT = VT.isFloatingPoint()
10873 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10874 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10875 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10876 // Make sure that the new vector type is legal. For example, v2f64 isn't
10878 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10879 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10880 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10881 return DAG.getNode(ISD::BITCAST, dl, VT,
10882 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10886 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10887 for (int M : SVOp->getMask())
10889 ++NumUndefElements;
10890 else if (M < NumElements)
10895 // Commute the shuffle as needed such that more elements come from V1 than
10896 // V2. This allows us to match the shuffle pattern strictly on how many
10897 // elements come from V1 without handling the symmetric cases.
10898 if (NumV2Elements > NumV1Elements)
10899 return DAG.getCommutedVectorShuffle(*SVOp);
10901 // When the number of V1 and V2 elements are the same, try to minimize the
10902 // number of uses of V2 in the low half of the vector. When that is tied,
10903 // ensure that the sum of indices for V1 is equal to or lower than the sum
10904 // indices for V2. When those are equal, try to ensure that the number of odd
10905 // indices for V1 is lower than the number of odd indices for V2.
10906 if (NumV1Elements == NumV2Elements) {
10907 int LowV1Elements = 0, LowV2Elements = 0;
10908 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10909 if (M >= NumElements)
10913 if (LowV2Elements > LowV1Elements) {
10914 return DAG.getCommutedVectorShuffle(*SVOp);
10915 } else if (LowV2Elements == LowV1Elements) {
10916 int SumV1Indices = 0, SumV2Indices = 0;
10917 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10918 if (SVOp->getMask()[i] >= NumElements)
10920 else if (SVOp->getMask()[i] >= 0)
10922 if (SumV2Indices < SumV1Indices) {
10923 return DAG.getCommutedVectorShuffle(*SVOp);
10924 } else if (SumV2Indices == SumV1Indices) {
10925 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10926 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10927 if (SVOp->getMask()[i] >= NumElements)
10928 NumV2OddIndices += i % 2;
10929 else if (SVOp->getMask()[i] >= 0)
10930 NumV1OddIndices += i % 2;
10931 if (NumV2OddIndices < NumV1OddIndices)
10932 return DAG.getCommutedVectorShuffle(*SVOp);
10937 // For each vector width, delegate to a specialized lowering routine.
10938 if (VT.getSizeInBits() == 128)
10939 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10941 if (VT.getSizeInBits() == 256)
10942 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10944 // Force AVX-512 vectors to be scalarized for now.
10945 // FIXME: Implement AVX-512 support!
10946 if (VT.getSizeInBits() == 512)
10947 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10949 llvm_unreachable("Unimplemented!");
10953 //===----------------------------------------------------------------------===//
10954 // Legacy vector shuffle lowering
10956 // This code is the legacy code handling vector shuffles until the above
10957 // replaces its functionality and performance.
10958 //===----------------------------------------------------------------------===//
10960 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10961 bool hasInt256, unsigned *MaskOut = nullptr) {
10962 MVT EltVT = VT.getVectorElementType();
10964 // There is no blend with immediate in AVX-512.
10965 if (VT.is512BitVector())
10968 if (!hasSSE41 || EltVT == MVT::i8)
10970 if (!hasInt256 && VT == MVT::v16i16)
10973 unsigned MaskValue = 0;
10974 unsigned NumElems = VT.getVectorNumElements();
10975 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10976 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10977 unsigned NumElemsInLane = NumElems / NumLanes;
10979 // Blend for v16i16 should be symetric for the both lanes.
10980 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10982 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10983 int EltIdx = MaskVals[i];
10985 if ((EltIdx < 0 || EltIdx == (int)i) &&
10986 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10989 if (((unsigned)EltIdx == (i + NumElems)) &&
10990 (SndLaneEltIdx < 0 ||
10991 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10992 MaskValue |= (1 << i);
10998 *MaskOut = MaskValue;
11002 // Try to lower a shuffle node into a simple blend instruction.
11003 // This function assumes isBlendMask returns true for this
11004 // SuffleVectorSDNode
11005 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
11006 unsigned MaskValue,
11007 const X86Subtarget *Subtarget,
11008 SelectionDAG &DAG) {
11009 MVT VT = SVOp->getSimpleValueType(0);
11010 MVT EltVT = VT.getVectorElementType();
11011 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
11012 Subtarget->hasInt256() && "Trying to lower a "
11013 "VECTOR_SHUFFLE to a Blend but "
11014 "with the wrong mask"));
11015 SDValue V1 = SVOp->getOperand(0);
11016 SDValue V2 = SVOp->getOperand(1);
11018 unsigned NumElems = VT.getVectorNumElements();
11020 // Convert i32 vectors to floating point if it is not AVX2.
11021 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11023 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11024 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11026 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11027 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11030 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11031 DAG.getConstant(MaskValue, MVT::i32));
11032 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11035 /// In vector type \p VT, return true if the element at index \p InputIdx
11036 /// falls on a different 128-bit lane than \p OutputIdx.
11037 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11038 unsigned OutputIdx) {
11039 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11040 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11043 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11044 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11045 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11046 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11048 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11049 SelectionDAG &DAG) {
11050 MVT VT = V1.getSimpleValueType();
11051 assert(VT.is128BitVector() || VT.is256BitVector());
11053 MVT EltVT = VT.getVectorElementType();
11054 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11055 unsigned NumElts = VT.getVectorNumElements();
11057 SmallVector<SDValue, 32> PshufbMask;
11058 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11059 int InputIdx = MaskVals[OutputIdx];
11060 unsigned InputByteIdx;
11062 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11063 InputByteIdx = 0x80;
11065 // Cross lane is not allowed.
11066 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11068 InputByteIdx = InputIdx * EltSizeInBytes;
11069 // Index is an byte offset within the 128-bit lane.
11070 InputByteIdx &= 0xf;
11073 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11074 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11075 if (InputByteIdx != 0x80)
11080 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11082 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11083 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11084 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11087 // v8i16 shuffles - Prefer shuffles in the following order:
11088 // 1. [all] pshuflw, pshufhw, optional move
11089 // 2. [ssse3] 1 x pshufb
11090 // 3. [ssse3] 2 x pshufb + 1 x por
11091 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11093 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11094 SelectionDAG &DAG) {
11095 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11096 SDValue V1 = SVOp->getOperand(0);
11097 SDValue V2 = SVOp->getOperand(1);
11099 SmallVector<int, 8> MaskVals;
11101 // Determine if more than 1 of the words in each of the low and high quadwords
11102 // of the result come from the same quadword of one of the two inputs. Undef
11103 // mask values count as coming from any quadword, for better codegen.
11105 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11106 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11107 unsigned LoQuad[] = { 0, 0, 0, 0 };
11108 unsigned HiQuad[] = { 0, 0, 0, 0 };
11109 // Indices of quads used.
11110 std::bitset<4> InputQuads;
11111 for (unsigned i = 0; i < 8; ++i) {
11112 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11113 int EltIdx = SVOp->getMaskElt(i);
11114 MaskVals.push_back(EltIdx);
11122 ++Quad[EltIdx / 4];
11123 InputQuads.set(EltIdx / 4);
11126 int BestLoQuad = -1;
11127 unsigned MaxQuad = 1;
11128 for (unsigned i = 0; i < 4; ++i) {
11129 if (LoQuad[i] > MaxQuad) {
11131 MaxQuad = LoQuad[i];
11135 int BestHiQuad = -1;
11137 for (unsigned i = 0; i < 4; ++i) {
11138 if (HiQuad[i] > MaxQuad) {
11140 MaxQuad = HiQuad[i];
11144 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11145 // of the two input vectors, shuffle them into one input vector so only a
11146 // single pshufb instruction is necessary. If there are more than 2 input
11147 // quads, disable the next transformation since it does not help SSSE3.
11148 bool V1Used = InputQuads[0] || InputQuads[1];
11149 bool V2Used = InputQuads[2] || InputQuads[3];
11150 if (Subtarget->hasSSSE3()) {
11151 if (InputQuads.count() == 2 && V1Used && V2Used) {
11152 BestLoQuad = InputQuads[0] ? 0 : 1;
11153 BestHiQuad = InputQuads[2] ? 2 : 3;
11155 if (InputQuads.count() > 2) {
11161 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11162 // the shuffle mask. If a quad is scored as -1, that means that it contains
11163 // words from all 4 input quadwords.
11165 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11167 BestLoQuad < 0 ? 0 : BestLoQuad,
11168 BestHiQuad < 0 ? 1 : BestHiQuad
11170 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11171 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11172 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11173 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11175 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11176 // source words for the shuffle, to aid later transformations.
11177 bool AllWordsInNewV = true;
11178 bool InOrder[2] = { true, true };
11179 for (unsigned i = 0; i != 8; ++i) {
11180 int idx = MaskVals[i];
11182 InOrder[i/4] = false;
11183 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11185 AllWordsInNewV = false;
11189 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11190 if (AllWordsInNewV) {
11191 for (int i = 0; i != 8; ++i) {
11192 int idx = MaskVals[i];
11195 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11196 if ((idx != i) && idx < 4)
11198 if ((idx != i) && idx > 3)
11207 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11208 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11209 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11210 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11211 unsigned TargetMask = 0;
11212 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11213 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11214 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11215 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11216 getShufflePSHUFLWImmediate(SVOp);
11217 V1 = NewV.getOperand(0);
11218 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11222 // Promote splats to a larger type which usually leads to more efficient code.
11223 // FIXME: Is this true if pshufb is available?
11224 if (SVOp->isSplat())
11225 return PromoteSplat(SVOp, DAG);
11227 // If we have SSSE3, and all words of the result are from 1 input vector,
11228 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11229 // is present, fall back to case 4.
11230 if (Subtarget->hasSSSE3()) {
11231 SmallVector<SDValue,16> pshufbMask;
11233 // If we have elements from both input vectors, set the high bit of the
11234 // shuffle mask element to zero out elements that come from V2 in the V1
11235 // mask, and elements that come from V1 in the V2 mask, so that the two
11236 // results can be OR'd together.
11237 bool TwoInputs = V1Used && V2Used;
11238 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11240 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11242 // Calculate the shuffle mask for the second input, shuffle it, and
11243 // OR it with the first shuffled input.
11244 CommuteVectorShuffleMask(MaskVals, 8);
11245 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11246 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11247 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11250 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11251 // and update MaskVals with new element order.
11252 std::bitset<8> InOrder;
11253 if (BestLoQuad >= 0) {
11254 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11255 for (int i = 0; i != 4; ++i) {
11256 int idx = MaskVals[i];
11259 } else if ((idx / 4) == BestLoQuad) {
11260 MaskV[i] = idx & 3;
11264 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11267 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11268 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11269 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11270 NewV.getOperand(0),
11271 getShufflePSHUFLWImmediate(SVOp), DAG);
11275 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11276 // and update MaskVals with the new element order.
11277 if (BestHiQuad >= 0) {
11278 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11279 for (unsigned i = 4; i != 8; ++i) {
11280 int idx = MaskVals[i];
11283 } else if ((idx / 4) == BestHiQuad) {
11284 MaskV[i] = (idx & 3) + 4;
11288 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11291 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11293 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11294 NewV.getOperand(0),
11295 getShufflePSHUFHWImmediate(SVOp), DAG);
11299 // In case BestHi & BestLo were both -1, which means each quadword has a word
11300 // from each of the four input quadwords, calculate the InOrder bitvector now
11301 // before falling through to the insert/extract cleanup.
11302 if (BestLoQuad == -1 && BestHiQuad == -1) {
11304 for (int i = 0; i != 8; ++i)
11305 if (MaskVals[i] < 0 || MaskVals[i] == i)
11309 // The other elements are put in the right place using pextrw and pinsrw.
11310 for (unsigned i = 0; i != 8; ++i) {
11313 int EltIdx = MaskVals[i];
11316 SDValue ExtOp = (EltIdx < 8) ?
11317 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11318 DAG.getIntPtrConstant(EltIdx)) :
11319 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11320 DAG.getIntPtrConstant(EltIdx - 8));
11321 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11322 DAG.getIntPtrConstant(i));
11327 /// \brief v16i16 shuffles
11329 /// FIXME: We only support generation of a single pshufb currently. We can
11330 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11331 /// well (e.g 2 x pshufb + 1 x por).
11333 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11334 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11335 SDValue V1 = SVOp->getOperand(0);
11336 SDValue V2 = SVOp->getOperand(1);
11339 if (V2.getOpcode() != ISD::UNDEF)
11342 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11343 return getPSHUFB(MaskVals, V1, dl, DAG);
11346 // v16i8 shuffles - Prefer shuffles in the following order:
11347 // 1. [ssse3] 1 x pshufb
11348 // 2. [ssse3] 2 x pshufb + 1 x por
11349 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11350 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11351 const X86Subtarget* Subtarget,
11352 SelectionDAG &DAG) {
11353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11354 SDValue V1 = SVOp->getOperand(0);
11355 SDValue V2 = SVOp->getOperand(1);
11357 ArrayRef<int> MaskVals = SVOp->getMask();
11359 // Promote splats to a larger type which usually leads to more efficient code.
11360 // FIXME: Is this true if pshufb is available?
11361 if (SVOp->isSplat())
11362 return PromoteSplat(SVOp, DAG);
11364 // If we have SSSE3, case 1 is generated when all result bytes come from
11365 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11366 // present, fall back to case 3.
11368 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11369 if (Subtarget->hasSSSE3()) {
11370 SmallVector<SDValue,16> pshufbMask;
11372 // If all result elements are from one input vector, then only translate
11373 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11375 // Otherwise, we have elements from both input vectors, and must zero out
11376 // elements that come from V2 in the first mask, and V1 in the second mask
11377 // so that we can OR them together.
11378 for (unsigned i = 0; i != 16; ++i) {
11379 int EltIdx = MaskVals[i];
11380 if (EltIdx < 0 || EltIdx >= 16)
11382 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11384 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11385 DAG.getNode(ISD::BUILD_VECTOR, dl,
11386 MVT::v16i8, pshufbMask));
11388 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11389 // the 2nd operand if it's undefined or zero.
11390 if (V2.getOpcode() == ISD::UNDEF ||
11391 ISD::isBuildVectorAllZeros(V2.getNode()))
11394 // Calculate the shuffle mask for the second input, shuffle it, and
11395 // OR it with the first shuffled input.
11396 pshufbMask.clear();
11397 for (unsigned i = 0; i != 16; ++i) {
11398 int EltIdx = MaskVals[i];
11399 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11400 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11402 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11403 DAG.getNode(ISD::BUILD_VECTOR, dl,
11404 MVT::v16i8, pshufbMask));
11405 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11408 // No SSSE3 - Calculate in place words and then fix all out of place words
11409 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11410 // the 16 different words that comprise the two doublequadword input vectors.
11411 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11412 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11414 for (int i = 0; i != 8; ++i) {
11415 int Elt0 = MaskVals[i*2];
11416 int Elt1 = MaskVals[i*2+1];
11418 // This word of the result is all undef, skip it.
11419 if (Elt0 < 0 && Elt1 < 0)
11422 // This word of the result is already in the correct place, skip it.
11423 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11426 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11427 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11430 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11431 // using a single extract together, load it and store it.
11432 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11433 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11434 DAG.getIntPtrConstant(Elt1 / 2));
11435 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11436 DAG.getIntPtrConstant(i));
11440 // If Elt1 is defined, extract it from the appropriate source. If the
11441 // source byte is not also odd, shift the extracted word left 8 bits
11442 // otherwise clear the bottom 8 bits if we need to do an or.
11444 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11445 DAG.getIntPtrConstant(Elt1 / 2));
11446 if ((Elt1 & 1) == 0)
11447 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11449 TLI.getShiftAmountTy(InsElt.getValueType())));
11450 else if (Elt0 >= 0)
11451 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11452 DAG.getConstant(0xFF00, MVT::i16));
11454 // If Elt0 is defined, extract it from the appropriate source. If the
11455 // source byte is not also even, shift the extracted word right 8 bits. If
11456 // Elt1 was also defined, OR the extracted values together before
11457 // inserting them in the result.
11459 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11460 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11461 if ((Elt0 & 1) != 0)
11462 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11464 TLI.getShiftAmountTy(InsElt0.getValueType())));
11465 else if (Elt1 >= 0)
11466 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11467 DAG.getConstant(0x00FF, MVT::i16));
11468 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11471 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11472 DAG.getIntPtrConstant(i));
11474 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11477 // v32i8 shuffles - Translate to VPSHUFB if possible.
11479 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11480 const X86Subtarget *Subtarget,
11481 SelectionDAG &DAG) {
11482 MVT VT = SVOp->getSimpleValueType(0);
11483 SDValue V1 = SVOp->getOperand(0);
11484 SDValue V2 = SVOp->getOperand(1);
11486 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11488 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11489 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11490 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11492 // VPSHUFB may be generated if
11493 // (1) one of input vector is undefined or zeroinitializer.
11494 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11495 // And (2) the mask indexes don't cross the 128-bit lane.
11496 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11497 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11500 if (V1IsAllZero && !V2IsAllZero) {
11501 CommuteVectorShuffleMask(MaskVals, 32);
11504 return getPSHUFB(MaskVals, V1, dl, DAG);
11507 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11508 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11509 /// done when every pair / quad of shuffle mask elements point to elements in
11510 /// the right sequence. e.g.
11511 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11513 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11514 SelectionDAG &DAG) {
11515 MVT VT = SVOp->getSimpleValueType(0);
11517 unsigned NumElems = VT.getVectorNumElements();
11520 switch (VT.SimpleTy) {
11521 default: llvm_unreachable("Unexpected!");
11524 return SDValue(SVOp, 0);
11525 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11526 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11527 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11528 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11529 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11530 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11533 SmallVector<int, 8> MaskVec;
11534 for (unsigned i = 0; i != NumElems; i += Scale) {
11536 for (unsigned j = 0; j != Scale; ++j) {
11537 int EltIdx = SVOp->getMaskElt(i+j);
11541 StartIdx = (EltIdx / Scale);
11542 if (EltIdx != (int)(StartIdx*Scale + j))
11545 MaskVec.push_back(StartIdx);
11548 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11549 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11550 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11553 /// getVZextMovL - Return a zero-extending vector move low node.
11555 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11556 SDValue SrcOp, SelectionDAG &DAG,
11557 const X86Subtarget *Subtarget, SDLoc dl) {
11558 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11559 LoadSDNode *LD = nullptr;
11560 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11561 LD = dyn_cast<LoadSDNode>(SrcOp);
11563 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11565 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11566 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11567 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11568 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11569 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11571 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11572 return DAG.getNode(ISD::BITCAST, dl, VT,
11573 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11574 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11576 SrcOp.getOperand(0)
11582 return DAG.getNode(ISD::BITCAST, dl, VT,
11583 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11584 DAG.getNode(ISD::BITCAST, dl,
11588 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11589 /// which could not be matched by any known target speficic shuffle
11591 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11593 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11594 if (NewOp.getNode())
11597 MVT VT = SVOp->getSimpleValueType(0);
11599 unsigned NumElems = VT.getVectorNumElements();
11600 unsigned NumLaneElems = NumElems / 2;
11603 MVT EltVT = VT.getVectorElementType();
11604 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11607 SmallVector<int, 16> Mask;
11608 for (unsigned l = 0; l < 2; ++l) {
11609 // Build a shuffle mask for the output, discovering on the fly which
11610 // input vectors to use as shuffle operands (recorded in InputUsed).
11611 // If building a suitable shuffle vector proves too hard, then bail
11612 // out with UseBuildVector set.
11613 bool UseBuildVector = false;
11614 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11615 unsigned LaneStart = l * NumLaneElems;
11616 for (unsigned i = 0; i != NumLaneElems; ++i) {
11617 // The mask element. This indexes into the input.
11618 int Idx = SVOp->getMaskElt(i+LaneStart);
11620 // the mask element does not index into any input vector.
11621 Mask.push_back(-1);
11625 // The input vector this mask element indexes into.
11626 int Input = Idx / NumLaneElems;
11628 // Turn the index into an offset from the start of the input vector.
11629 Idx -= Input * NumLaneElems;
11631 // Find or create a shuffle vector operand to hold this input.
11633 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11634 if (InputUsed[OpNo] == Input)
11635 // This input vector is already an operand.
11637 if (InputUsed[OpNo] < 0) {
11638 // Create a new operand for this input vector.
11639 InputUsed[OpNo] = Input;
11644 if (OpNo >= array_lengthof(InputUsed)) {
11645 // More than two input vectors used! Give up on trying to create a
11646 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11647 UseBuildVector = true;
11651 // Add the mask index for the new shuffle vector.
11652 Mask.push_back(Idx + OpNo * NumLaneElems);
11655 if (UseBuildVector) {
11656 SmallVector<SDValue, 16> SVOps;
11657 for (unsigned i = 0; i != NumLaneElems; ++i) {
11658 // The mask element. This indexes into the input.
11659 int Idx = SVOp->getMaskElt(i+LaneStart);
11661 SVOps.push_back(DAG.getUNDEF(EltVT));
11665 // The input vector this mask element indexes into.
11666 int Input = Idx / NumElems;
11668 // Turn the index into an offset from the start of the input vector.
11669 Idx -= Input * NumElems;
11671 // Extract the vector element by hand.
11672 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11673 SVOp->getOperand(Input),
11674 DAG.getIntPtrConstant(Idx)));
11677 // Construct the output using a BUILD_VECTOR.
11678 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11679 } else if (InputUsed[0] < 0) {
11680 // No input vectors were used! The result is undefined.
11681 Output[l] = DAG.getUNDEF(NVT);
11683 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11684 (InputUsed[0] % 2) * NumLaneElems,
11686 // If only one input was used, use an undefined vector for the other.
11687 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11688 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11689 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11690 // At least one input vector was used. Create a new shuffle vector.
11691 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11697 // Concatenate the result back
11698 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11701 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11702 /// 4 elements, and match them with several different shuffle types.
11704 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11705 SDValue V1 = SVOp->getOperand(0);
11706 SDValue V2 = SVOp->getOperand(1);
11708 MVT VT = SVOp->getSimpleValueType(0);
11710 assert(VT.is128BitVector() && "Unsupported vector size");
11712 std::pair<int, int> Locs[4];
11713 int Mask1[] = { -1, -1, -1, -1 };
11714 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11716 unsigned NumHi = 0;
11717 unsigned NumLo = 0;
11718 for (unsigned i = 0; i != 4; ++i) {
11719 int Idx = PermMask[i];
11721 Locs[i] = std::make_pair(-1, -1);
11723 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11725 Locs[i] = std::make_pair(0, NumLo);
11726 Mask1[NumLo] = Idx;
11729 Locs[i] = std::make_pair(1, NumHi);
11731 Mask1[2+NumHi] = Idx;
11737 if (NumLo <= 2 && NumHi <= 2) {
11738 // If no more than two elements come from either vector. This can be
11739 // implemented with two shuffles. First shuffle gather the elements.
11740 // The second shuffle, which takes the first shuffle as both of its
11741 // vector operands, put the elements into the right order.
11742 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11744 int Mask2[] = { -1, -1, -1, -1 };
11746 for (unsigned i = 0; i != 4; ++i)
11747 if (Locs[i].first != -1) {
11748 unsigned Idx = (i < 2) ? 0 : 4;
11749 Idx += Locs[i].first * 2 + Locs[i].second;
11753 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11756 if (NumLo == 3 || NumHi == 3) {
11757 // Otherwise, we must have three elements from one vector, call it X, and
11758 // one element from the other, call it Y. First, use a shufps to build an
11759 // intermediate vector with the one element from Y and the element from X
11760 // that will be in the same half in the final destination (the indexes don't
11761 // matter). Then, use a shufps to build the final vector, taking the half
11762 // containing the element from Y from the intermediate, and the other half
11765 // Normalize it so the 3 elements come from V1.
11766 CommuteVectorShuffleMask(PermMask, 4);
11770 // Find the element from V2.
11772 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11773 int Val = PermMask[HiIndex];
11780 Mask1[0] = PermMask[HiIndex];
11782 Mask1[2] = PermMask[HiIndex^1];
11784 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11786 if (HiIndex >= 2) {
11787 Mask1[0] = PermMask[0];
11788 Mask1[1] = PermMask[1];
11789 Mask1[2] = HiIndex & 1 ? 6 : 4;
11790 Mask1[3] = HiIndex & 1 ? 4 : 6;
11791 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11794 Mask1[0] = HiIndex & 1 ? 2 : 0;
11795 Mask1[1] = HiIndex & 1 ? 0 : 2;
11796 Mask1[2] = PermMask[2];
11797 Mask1[3] = PermMask[3];
11802 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11805 // Break it into (shuffle shuffle_hi, shuffle_lo).
11806 int LoMask[] = { -1, -1, -1, -1 };
11807 int HiMask[] = { -1, -1, -1, -1 };
11809 int *MaskPtr = LoMask;
11810 unsigned MaskIdx = 0;
11811 unsigned LoIdx = 0;
11812 unsigned HiIdx = 2;
11813 for (unsigned i = 0; i != 4; ++i) {
11820 int Idx = PermMask[i];
11822 Locs[i] = std::make_pair(-1, -1);
11823 } else if (Idx < 4) {
11824 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11825 MaskPtr[LoIdx] = Idx;
11828 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11829 MaskPtr[HiIdx] = Idx;
11834 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11835 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11836 int MaskOps[] = { -1, -1, -1, -1 };
11837 for (unsigned i = 0; i != 4; ++i)
11838 if (Locs[i].first != -1)
11839 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11840 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11843 static bool MayFoldVectorLoad(SDValue V) {
11844 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11845 V = V.getOperand(0);
11847 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11848 V = V.getOperand(0);
11849 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11850 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11851 // BUILD_VECTOR (load), undef
11852 V = V.getOperand(0);
11854 return MayFoldLoad(V);
11858 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11859 MVT VT = Op.getSimpleValueType();
11861 // Canonizalize to v2f64.
11862 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11863 return DAG.getNode(ISD::BITCAST, dl, VT,
11864 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11869 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11871 SDValue V1 = Op.getOperand(0);
11872 SDValue V2 = Op.getOperand(1);
11873 MVT VT = Op.getSimpleValueType();
11875 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11877 if (HasSSE2 && VT == MVT::v2f64)
11878 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11880 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11881 return DAG.getNode(ISD::BITCAST, dl, VT,
11882 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11883 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11884 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11888 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11889 SDValue V1 = Op.getOperand(0);
11890 SDValue V2 = Op.getOperand(1);
11891 MVT VT = Op.getSimpleValueType();
11893 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11894 "unsupported shuffle type");
11896 if (V2.getOpcode() == ISD::UNDEF)
11900 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11904 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11905 SDValue V1 = Op.getOperand(0);
11906 SDValue V2 = Op.getOperand(1);
11907 MVT VT = Op.getSimpleValueType();
11908 unsigned NumElems = VT.getVectorNumElements();
11910 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11911 // operand of these instructions is only memory, so check if there's a
11912 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11914 bool CanFoldLoad = false;
11916 // Trivial case, when V2 comes from a load.
11917 if (MayFoldVectorLoad(V2))
11918 CanFoldLoad = true;
11920 // When V1 is a load, it can be folded later into a store in isel, example:
11921 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11923 // (MOVLPSmr addr:$src1, VR128:$src2)
11924 // So, recognize this potential and also use MOVLPS or MOVLPD
11925 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11926 CanFoldLoad = true;
11928 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11930 if (HasSSE2 && NumElems == 2)
11931 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11934 // If we don't care about the second element, proceed to use movss.
11935 if (SVOp->getMaskElt(1) != -1)
11936 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11939 // movl and movlp will both match v2i64, but v2i64 is never matched by
11940 // movl earlier because we make it strict to avoid messing with the movlp load
11941 // folding logic (see the code above getMOVLP call). Match it here then,
11942 // this is horrible, but will stay like this until we move all shuffle
11943 // matching to x86 specific nodes. Note that for the 1st condition all
11944 // types are matched with movsd.
11946 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11947 // as to remove this logic from here, as much as possible
11948 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11949 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11950 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11953 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11955 // Invert the operand order and use SHUFPS to match it.
11956 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11957 getShuffleSHUFImmediate(SVOp), DAG);
11960 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11961 SelectionDAG &DAG) {
11963 MVT VT = Load->getSimpleValueType(0);
11964 MVT EVT = VT.getVectorElementType();
11965 SDValue Addr = Load->getOperand(1);
11966 SDValue NewAddr = DAG.getNode(
11967 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11968 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11971 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11972 DAG.getMachineFunction().getMachineMemOperand(
11973 Load->getMemOperand(), 0, EVT.getStoreSize()));
11977 // It is only safe to call this function if isINSERTPSMask is true for
11978 // this shufflevector mask.
11979 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11980 SelectionDAG &DAG) {
11981 // Generate an insertps instruction when inserting an f32 from memory onto a
11982 // v4f32 or when copying a member from one v4f32 to another.
11983 // We also use it for transferring i32 from one register to another,
11984 // since it simply copies the same bits.
11985 // If we're transferring an i32 from memory to a specific element in a
11986 // register, we output a generic DAG that will match the PINSRD
11988 MVT VT = SVOp->getSimpleValueType(0);
11989 MVT EVT = VT.getVectorElementType();
11990 SDValue V1 = SVOp->getOperand(0);
11991 SDValue V2 = SVOp->getOperand(1);
11992 auto Mask = SVOp->getMask();
11993 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11994 "unsupported vector type for insertps/pinsrd");
11996 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11997 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11998 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
12002 unsigned DestIndex;
12006 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
12009 // If we have 1 element from each vector, we have to check if we're
12010 // changing V1's element's place. If so, we're done. Otherwise, we
12011 // should assume we're changing V2's element's place and behave
12013 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12014 assert(DestIndex <= INT32_MAX && "truncated destination index");
12015 if (FromV1 == FromV2 &&
12016 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12020 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12023 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12024 "More than one element from V1 and from V2, or no elements from one "
12025 "of the vectors. This case should not have returned true from "
12030 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12033 // Get an index into the source vector in the range [0,4) (the mask is
12034 // in the range [0,8) because it can address V1 and V2)
12035 unsigned SrcIndex = Mask[DestIndex] % 4;
12036 if (MayFoldLoad(From)) {
12037 // Trivial case, when From comes from a load and is only used by the
12038 // shuffle. Make it use insertps from the vector that we need from that
12041 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12042 if (!NewLoad.getNode())
12045 if (EVT == MVT::f32) {
12046 // Create this as a scalar to vector to match the instruction pattern.
12047 SDValue LoadScalarToVector =
12048 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12049 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12050 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12052 } else { // EVT == MVT::i32
12053 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12054 // instruction, to match the PINSRD instruction, which loads an i32 to a
12055 // certain vector element.
12056 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12057 DAG.getConstant(DestIndex, MVT::i32));
12061 // Vector-element-to-vector
12062 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12063 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12066 // Reduce a vector shuffle to zext.
12067 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12068 SelectionDAG &DAG) {
12069 // PMOVZX is only available from SSE41.
12070 if (!Subtarget->hasSSE41())
12073 MVT VT = Op.getSimpleValueType();
12075 // Only AVX2 support 256-bit vector integer extending.
12076 if (!Subtarget->hasInt256() && VT.is256BitVector())
12079 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12081 SDValue V1 = Op.getOperand(0);
12082 SDValue V2 = Op.getOperand(1);
12083 unsigned NumElems = VT.getVectorNumElements();
12085 // Extending is an unary operation and the element type of the source vector
12086 // won't be equal to or larger than i64.
12087 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12088 VT.getVectorElementType() == MVT::i64)
12091 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12092 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12093 while ((1U << Shift) < NumElems) {
12094 if (SVOp->getMaskElt(1U << Shift) == 1)
12097 // The maximal ratio is 8, i.e. from i8 to i64.
12102 // Check the shuffle mask.
12103 unsigned Mask = (1U << Shift) - 1;
12104 for (unsigned i = 0; i != NumElems; ++i) {
12105 int EltIdx = SVOp->getMaskElt(i);
12106 if ((i & Mask) != 0 && EltIdx != -1)
12108 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12112 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12113 MVT NeVT = MVT::getIntegerVT(NBits);
12114 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12116 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12119 return DAG.getNode(ISD::BITCAST, DL, VT,
12120 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12123 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12124 SelectionDAG &DAG) {
12125 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12126 MVT VT = Op.getSimpleValueType();
12128 SDValue V1 = Op.getOperand(0);
12129 SDValue V2 = Op.getOperand(1);
12131 if (isZeroShuffle(SVOp))
12132 return getZeroVector(VT, Subtarget, DAG, dl);
12134 // Handle splat operations
12135 if (SVOp->isSplat()) {
12136 // Use vbroadcast whenever the splat comes from a foldable load
12137 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12138 if (Broadcast.getNode())
12142 // Check integer expanding shuffles.
12143 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12144 if (NewOp.getNode())
12147 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12149 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12150 VT == MVT::v32i8) {
12151 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12152 if (NewOp.getNode())
12153 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12154 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12155 // FIXME: Figure out a cleaner way to do this.
12156 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12157 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12158 if (NewOp.getNode()) {
12159 MVT NewVT = NewOp.getSimpleValueType();
12160 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12161 NewVT, true, false))
12162 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12165 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12166 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12167 if (NewOp.getNode()) {
12168 MVT NewVT = NewOp.getSimpleValueType();
12169 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12170 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12179 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12181 SDValue V1 = Op.getOperand(0);
12182 SDValue V2 = Op.getOperand(1);
12183 MVT VT = Op.getSimpleValueType();
12185 unsigned NumElems = VT.getVectorNumElements();
12186 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12187 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12188 bool V1IsSplat = false;
12189 bool V2IsSplat = false;
12190 bool HasSSE2 = Subtarget->hasSSE2();
12191 bool HasFp256 = Subtarget->hasFp256();
12192 bool HasInt256 = Subtarget->hasInt256();
12193 MachineFunction &MF = DAG.getMachineFunction();
12194 bool OptForSize = MF.getFunction()->getAttributes().
12195 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12197 // Check if we should use the experimental vector shuffle lowering. If so,
12198 // delegate completely to that code path.
12199 if (ExperimentalVectorShuffleLowering)
12200 return lowerVectorShuffle(Op, Subtarget, DAG);
12202 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12204 if (V1IsUndef && V2IsUndef)
12205 return DAG.getUNDEF(VT);
12207 // When we create a shuffle node we put the UNDEF node to second operand,
12208 // but in some cases the first operand may be transformed to UNDEF.
12209 // In this case we should just commute the node.
12211 return DAG.getCommutedVectorShuffle(*SVOp);
12213 // Vector shuffle lowering takes 3 steps:
12215 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12216 // narrowing and commutation of operands should be handled.
12217 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12219 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12220 // so the shuffle can be broken into other shuffles and the legalizer can
12221 // try the lowering again.
12223 // The general idea is that no vector_shuffle operation should be left to
12224 // be matched during isel, all of them must be converted to a target specific
12227 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12228 // narrowing and commutation of operands should be handled. The actual code
12229 // doesn't include all of those, work in progress...
12230 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12231 if (NewOp.getNode())
12234 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12236 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12237 // unpckh_undef). Only use pshufd if speed is more important than size.
12238 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12239 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12240 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12241 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12243 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12244 V2IsUndef && MayFoldVectorLoad(V1))
12245 return getMOVDDup(Op, dl, V1, DAG);
12247 if (isMOVHLPS_v_undef_Mask(M, VT))
12248 return getMOVHighToLow(Op, dl, DAG);
12250 // Use to match splats
12251 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12252 (VT == MVT::v2f64 || VT == MVT::v2i64))
12253 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12255 if (isPSHUFDMask(M, VT)) {
12256 // The actual implementation will match the mask in the if above and then
12257 // during isel it can match several different instructions, not only pshufd
12258 // as its name says, sad but true, emulate the behavior for now...
12259 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12260 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12262 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12264 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12265 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12267 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12268 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12271 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12275 if (isPALIGNRMask(M, VT, Subtarget))
12276 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12277 getShufflePALIGNRImmediate(SVOp),
12280 if (isVALIGNMask(M, VT, Subtarget))
12281 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12282 getShuffleVALIGNImmediate(SVOp),
12285 // Check if this can be converted into a logical shift.
12286 bool isLeft = false;
12287 unsigned ShAmt = 0;
12289 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12290 if (isShift && ShVal.hasOneUse()) {
12291 // If the shifted value has multiple uses, it may be cheaper to use
12292 // v_set0 + movlhps or movhlps, etc.
12293 MVT EltVT = VT.getVectorElementType();
12294 ShAmt *= EltVT.getSizeInBits();
12295 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12298 if (isMOVLMask(M, VT)) {
12299 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12300 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12301 if (!isMOVLPMask(M, VT)) {
12302 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12303 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12305 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12306 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12310 // FIXME: fold these into legal mask.
12311 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12312 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12314 if (isMOVHLPSMask(M, VT))
12315 return getMOVHighToLow(Op, dl, DAG);
12317 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12318 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12320 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12321 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12323 if (isMOVLPMask(M, VT))
12324 return getMOVLP(Op, dl, DAG, HasSSE2);
12326 if (ShouldXformToMOVHLPS(M, VT) ||
12327 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12328 return DAG.getCommutedVectorShuffle(*SVOp);
12331 // No better options. Use a vshldq / vsrldq.
12332 MVT EltVT = VT.getVectorElementType();
12333 ShAmt *= EltVT.getSizeInBits();
12334 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12337 bool Commuted = false;
12338 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12339 // 1,1,1,1 -> v8i16 though.
12340 BitVector UndefElements;
12341 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12342 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12344 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12345 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12348 // Canonicalize the splat or undef, if present, to be on the RHS.
12349 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12350 CommuteVectorShuffleMask(M, NumElems);
12352 std::swap(V1IsSplat, V2IsSplat);
12356 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12357 // Shuffling low element of v1 into undef, just return v1.
12360 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12361 // the instruction selector will not match, so get a canonical MOVL with
12362 // swapped operands to undo the commute.
12363 return getMOVL(DAG, dl, VT, V2, V1);
12366 if (isUNPCKLMask(M, VT, HasInt256))
12367 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12369 if (isUNPCKHMask(M, VT, HasInt256))
12370 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12373 // Normalize mask so all entries that point to V2 points to its first
12374 // element then try to match unpck{h|l} again. If match, return a
12375 // new vector_shuffle with the corrected mask.p
12376 SmallVector<int, 8> NewMask(M.begin(), M.end());
12377 NormalizeMask(NewMask, NumElems);
12378 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12379 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12380 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12381 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12385 // Commute is back and try unpck* again.
12386 // FIXME: this seems wrong.
12387 CommuteVectorShuffleMask(M, NumElems);
12389 std::swap(V1IsSplat, V2IsSplat);
12391 if (isUNPCKLMask(M, VT, HasInt256))
12392 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12394 if (isUNPCKHMask(M, VT, HasInt256))
12395 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12398 // Normalize the node to match x86 shuffle ops if needed
12399 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12400 return DAG.getCommutedVectorShuffle(*SVOp);
12402 // The checks below are all present in isShuffleMaskLegal, but they are
12403 // inlined here right now to enable us to directly emit target specific
12404 // nodes, and remove one by one until they don't return Op anymore.
12406 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12407 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12408 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12409 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12412 if (isPSHUFHWMask(M, VT, HasInt256))
12413 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12414 getShufflePSHUFHWImmediate(SVOp),
12417 if (isPSHUFLWMask(M, VT, HasInt256))
12418 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12419 getShufflePSHUFLWImmediate(SVOp),
12422 unsigned MaskValue;
12423 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12425 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12427 if (isSHUFPMask(M, VT))
12428 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12429 getShuffleSHUFImmediate(SVOp), DAG);
12431 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12432 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12433 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12434 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12436 //===--------------------------------------------------------------------===//
12437 // Generate target specific nodes for 128 or 256-bit shuffles only
12438 // supported in the AVX instruction set.
12441 // Handle VMOVDDUPY permutations
12442 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12443 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12445 // Handle VPERMILPS/D* permutations
12446 if (isVPERMILPMask(M, VT)) {
12447 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12448 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12449 getShuffleSHUFImmediate(SVOp), DAG);
12450 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12451 getShuffleSHUFImmediate(SVOp), DAG);
12455 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12456 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12457 Idx*(NumElems/2), DAG, dl);
12459 // Handle VPERM2F128/VPERM2I128 permutations
12460 if (isVPERM2X128Mask(M, VT, HasFp256))
12461 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12462 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12464 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12465 return getINSERTPS(SVOp, dl, DAG);
12468 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12469 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12471 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12472 VT.is512BitVector()) {
12473 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12474 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12475 SmallVector<SDValue, 16> permclMask;
12476 for (unsigned i = 0; i != NumElems; ++i) {
12477 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12480 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12482 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12483 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12484 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12485 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12486 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12489 //===--------------------------------------------------------------------===//
12490 // Since no target specific shuffle was selected for this generic one,
12491 // lower it into other known shuffles. FIXME: this isn't true yet, but
12492 // this is the plan.
12495 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12496 if (VT == MVT::v8i16) {
12497 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12498 if (NewOp.getNode())
12502 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12503 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12504 if (NewOp.getNode())
12508 if (VT == MVT::v16i8) {
12509 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12510 if (NewOp.getNode())
12514 if (VT == MVT::v32i8) {
12515 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12516 if (NewOp.getNode())
12520 // Handle all 128-bit wide vectors with 4 elements, and match them with
12521 // several different shuffle types.
12522 if (NumElems == 4 && VT.is128BitVector())
12523 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12525 // Handle general 256-bit shuffles
12526 if (VT.is256BitVector())
12527 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12532 // This function assumes its argument is a BUILD_VECTOR of constants or
12533 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12535 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12536 unsigned &MaskValue) {
12538 unsigned NumElems = BuildVector->getNumOperands();
12539 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12540 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12541 unsigned NumElemsInLane = NumElems / NumLanes;
12543 // Blend for v16i16 should be symetric for the both lanes.
12544 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12545 SDValue EltCond = BuildVector->getOperand(i);
12546 SDValue SndLaneEltCond =
12547 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12549 int Lane1Cond = -1, Lane2Cond = -1;
12550 if (isa<ConstantSDNode>(EltCond))
12551 Lane1Cond = !isZero(EltCond);
12552 if (isa<ConstantSDNode>(SndLaneEltCond))
12553 Lane2Cond = !isZero(SndLaneEltCond);
12555 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12556 // Lane1Cond != 0, means we want the first argument.
12557 // Lane1Cond == 0, means we want the second argument.
12558 // The encoding of this argument is 0 for the first argument, 1
12559 // for the second. Therefore, invert the condition.
12560 MaskValue |= !Lane1Cond << i;
12561 else if (Lane1Cond < 0)
12562 MaskValue |= !Lane2Cond << i;
12569 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12571 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12572 SelectionDAG &DAG) {
12573 SDValue Cond = Op.getOperand(0);
12574 SDValue LHS = Op.getOperand(1);
12575 SDValue RHS = Op.getOperand(2);
12577 MVT VT = Op.getSimpleValueType();
12578 MVT EltVT = VT.getVectorElementType();
12579 unsigned NumElems = VT.getVectorNumElements();
12581 // There is no blend with immediate in AVX-512.
12582 if (VT.is512BitVector())
12585 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12587 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12590 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12593 // Check the mask for BLEND and build the value.
12594 unsigned MaskValue = 0;
12595 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12598 // Convert i32 vectors to floating point if it is not AVX2.
12599 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12601 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12602 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12604 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12605 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12608 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12609 DAG.getConstant(MaskValue, MVT::i32));
12610 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12613 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12614 // A vselect where all conditions and data are constants can be optimized into
12615 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12616 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12617 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12618 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12621 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12622 if (BlendOp.getNode())
12625 // Some types for vselect were previously set to Expand, not Legal or
12626 // Custom. Return an empty SDValue so we fall-through to Expand, after
12627 // the Custom lowering phase.
12628 MVT VT = Op.getSimpleValueType();
12629 switch (VT.SimpleTy) {
12634 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12639 // We couldn't create a "Blend with immediate" node.
12640 // This node should still be legal, but we'll have to emit a blendv*
12645 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12646 MVT VT = Op.getSimpleValueType();
12649 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12652 if (VT.getSizeInBits() == 8) {
12653 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12654 Op.getOperand(0), Op.getOperand(1));
12655 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12656 DAG.getValueType(VT));
12657 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12660 if (VT.getSizeInBits() == 16) {
12661 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12662 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12664 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12665 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12666 DAG.getNode(ISD::BITCAST, dl,
12669 Op.getOperand(1)));
12670 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12671 Op.getOperand(0), Op.getOperand(1));
12672 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12673 DAG.getValueType(VT));
12674 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12677 if (VT == MVT::f32) {
12678 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12679 // the result back to FR32 register. It's only worth matching if the
12680 // result has a single use which is a store or a bitcast to i32. And in
12681 // the case of a store, it's not worth it if the index is a constant 0,
12682 // because a MOVSSmr can be used instead, which is smaller and faster.
12683 if (!Op.hasOneUse())
12685 SDNode *User = *Op.getNode()->use_begin();
12686 if ((User->getOpcode() != ISD::STORE ||
12687 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12688 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12689 (User->getOpcode() != ISD::BITCAST ||
12690 User->getValueType(0) != MVT::i32))
12692 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12693 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12696 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12699 if (VT == MVT::i32 || VT == MVT::i64) {
12700 // ExtractPS/pextrq works with constant index.
12701 if (isa<ConstantSDNode>(Op.getOperand(1)))
12707 /// Extract one bit from mask vector, like v16i1 or v8i1.
12708 /// AVX-512 feature.
12710 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12711 SDValue Vec = Op.getOperand(0);
12713 MVT VecVT = Vec.getSimpleValueType();
12714 SDValue Idx = Op.getOperand(1);
12715 MVT EltVT = Op.getSimpleValueType();
12717 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12719 // variable index can't be handled in mask registers,
12720 // extend vector to VR512
12721 if (!isa<ConstantSDNode>(Idx)) {
12722 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12723 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12724 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12725 ExtVT.getVectorElementType(), Ext, Idx);
12726 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12729 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12730 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12731 unsigned MaxSift = rc->getSize()*8 - 1;
12732 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12733 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12734 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12735 DAG.getConstant(MaxSift, MVT::i8));
12736 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12737 DAG.getIntPtrConstant(0));
12741 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12742 SelectionDAG &DAG) const {
12744 SDValue Vec = Op.getOperand(0);
12745 MVT VecVT = Vec.getSimpleValueType();
12746 SDValue Idx = Op.getOperand(1);
12748 if (Op.getSimpleValueType() == MVT::i1)
12749 return ExtractBitFromMaskVector(Op, DAG);
12751 if (!isa<ConstantSDNode>(Idx)) {
12752 if (VecVT.is512BitVector() ||
12753 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12754 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12757 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12758 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12759 MaskEltVT.getSizeInBits());
12761 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12762 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12763 getZeroVector(MaskVT, Subtarget, DAG, dl),
12764 Idx, DAG.getConstant(0, getPointerTy()));
12765 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12766 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12767 Perm, DAG.getConstant(0, getPointerTy()));
12772 // If this is a 256-bit vector result, first extract the 128-bit vector and
12773 // then extract the element from the 128-bit vector.
12774 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12776 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12777 // Get the 128-bit vector.
12778 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12779 MVT EltVT = VecVT.getVectorElementType();
12781 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12783 //if (IdxVal >= NumElems/2)
12784 // IdxVal -= NumElems/2;
12785 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12786 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12787 DAG.getConstant(IdxVal, MVT::i32));
12790 assert(VecVT.is128BitVector() && "Unexpected vector length");
12792 if (Subtarget->hasSSE41()) {
12793 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12798 MVT VT = Op.getSimpleValueType();
12799 // TODO: handle v16i8.
12800 if (VT.getSizeInBits() == 16) {
12801 SDValue Vec = Op.getOperand(0);
12802 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12804 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12805 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12806 DAG.getNode(ISD::BITCAST, dl,
12808 Op.getOperand(1)));
12809 // Transform it so it match pextrw which produces a 32-bit result.
12810 MVT EltVT = MVT::i32;
12811 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12812 Op.getOperand(0), Op.getOperand(1));
12813 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12814 DAG.getValueType(VT));
12815 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12818 if (VT.getSizeInBits() == 32) {
12819 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12823 // SHUFPS the element to the lowest double word, then movss.
12824 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12825 MVT VVT = Op.getOperand(0).getSimpleValueType();
12826 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12827 DAG.getUNDEF(VVT), Mask);
12828 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12829 DAG.getIntPtrConstant(0));
12832 if (VT.getSizeInBits() == 64) {
12833 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12834 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12835 // to match extract_elt for f64.
12836 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12840 // UNPCKHPD the element to the lowest double word, then movsd.
12841 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12842 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12843 int Mask[2] = { 1, -1 };
12844 MVT VVT = Op.getOperand(0).getSimpleValueType();
12845 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12846 DAG.getUNDEF(VVT), Mask);
12847 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12848 DAG.getIntPtrConstant(0));
12854 /// Insert one bit to mask vector, like v16i1 or v8i1.
12855 /// AVX-512 feature.
12857 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12859 SDValue Vec = Op.getOperand(0);
12860 SDValue Elt = Op.getOperand(1);
12861 SDValue Idx = Op.getOperand(2);
12862 MVT VecVT = Vec.getSimpleValueType();
12864 if (!isa<ConstantSDNode>(Idx)) {
12865 // Non constant index. Extend source and destination,
12866 // insert element and then truncate the result.
12867 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12868 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12869 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12870 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12871 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12872 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12875 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12876 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12877 if (Vec.getOpcode() == ISD::UNDEF)
12878 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12879 DAG.getConstant(IdxVal, MVT::i8));
12880 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12881 unsigned MaxSift = rc->getSize()*8 - 1;
12882 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12883 DAG.getConstant(MaxSift, MVT::i8));
12884 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12885 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12886 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12889 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12890 SelectionDAG &DAG) const {
12891 MVT VT = Op.getSimpleValueType();
12892 MVT EltVT = VT.getVectorElementType();
12894 if (EltVT == MVT::i1)
12895 return InsertBitToMaskVector(Op, DAG);
12898 SDValue N0 = Op.getOperand(0);
12899 SDValue N1 = Op.getOperand(1);
12900 SDValue N2 = Op.getOperand(2);
12901 if (!isa<ConstantSDNode>(N2))
12903 auto *N2C = cast<ConstantSDNode>(N2);
12904 unsigned IdxVal = N2C->getZExtValue();
12906 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12907 // into that, and then insert the subvector back into the result.
12908 if (VT.is256BitVector() || VT.is512BitVector()) {
12909 // Get the desired 128-bit vector half.
12910 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12912 // Insert the element into the desired half.
12913 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12914 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12916 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12917 DAG.getConstant(IdxIn128, MVT::i32));
12919 // Insert the changed part back to the 256-bit vector
12920 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12922 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12924 if (Subtarget->hasSSE41()) {
12925 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12927 if (VT == MVT::v8i16) {
12928 Opc = X86ISD::PINSRW;
12930 assert(VT == MVT::v16i8);
12931 Opc = X86ISD::PINSRB;
12934 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12936 if (N1.getValueType() != MVT::i32)
12937 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12938 if (N2.getValueType() != MVT::i32)
12939 N2 = DAG.getIntPtrConstant(IdxVal);
12940 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12943 if (EltVT == MVT::f32) {
12944 // Bits [7:6] of the constant are the source select. This will always be
12945 // zero here. The DAG Combiner may combine an extract_elt index into
12947 // bits. For example (insert (extract, 3), 2) could be matched by
12949 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12950 // Bits [5:4] of the constant are the destination select. This is the
12951 // value of the incoming immediate.
12952 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12953 // combine either bitwise AND or insert of float 0.0 to set these bits.
12954 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12955 // Create this as a scalar to vector..
12956 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12957 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12960 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12961 // PINSR* works with constant index.
12966 if (EltVT == MVT::i8)
12969 if (EltVT.getSizeInBits() == 16) {
12970 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12971 // as its second argument.
12972 if (N1.getValueType() != MVT::i32)
12973 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12974 if (N2.getValueType() != MVT::i32)
12975 N2 = DAG.getIntPtrConstant(IdxVal);
12976 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12981 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12983 MVT OpVT = Op.getSimpleValueType();
12985 // If this is a 256-bit vector result, first insert into a 128-bit
12986 // vector and then insert into the 256-bit vector.
12987 if (!OpVT.is128BitVector()) {
12988 // Insert into a 128-bit vector.
12989 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12990 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12991 OpVT.getVectorNumElements() / SizeFactor);
12993 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12995 // Insert the 128-bit vector.
12996 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12999 if (OpVT == MVT::v1i64 &&
13000 Op.getOperand(0).getValueType() == MVT::i64)
13001 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
13003 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
13004 assert(OpVT.is128BitVector() && "Expected an SSE type!");
13005 return DAG.getNode(ISD::BITCAST, dl, OpVT,
13006 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
13009 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
13010 // a simple subregister reference or explicit instructions to grab
13011 // upper bits of a vector.
13012 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13013 SelectionDAG &DAG) {
13015 SDValue In = Op.getOperand(0);
13016 SDValue Idx = Op.getOperand(1);
13017 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13018 MVT ResVT = Op.getSimpleValueType();
13019 MVT InVT = In.getSimpleValueType();
13021 if (Subtarget->hasFp256()) {
13022 if (ResVT.is128BitVector() &&
13023 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13024 isa<ConstantSDNode>(Idx)) {
13025 return Extract128BitVector(In, IdxVal, DAG, dl);
13027 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13028 isa<ConstantSDNode>(Idx)) {
13029 return Extract256BitVector(In, IdxVal, DAG, dl);
13035 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13036 // simple superregister reference or explicit instructions to insert
13037 // the upper bits of a vector.
13038 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13039 SelectionDAG &DAG) {
13040 if (Subtarget->hasFp256()) {
13041 SDLoc dl(Op.getNode());
13042 SDValue Vec = Op.getNode()->getOperand(0);
13043 SDValue SubVec = Op.getNode()->getOperand(1);
13044 SDValue Idx = Op.getNode()->getOperand(2);
13046 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13047 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13048 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13049 isa<ConstantSDNode>(Idx)) {
13050 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13051 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13054 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13055 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13056 isa<ConstantSDNode>(Idx)) {
13057 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13058 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13064 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13065 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13066 // one of the above mentioned nodes. It has to be wrapped because otherwise
13067 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13068 // be used to form addressing mode. These wrapped nodes will be selected
13071 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13072 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13074 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13075 // global base reg.
13076 unsigned char OpFlag = 0;
13077 unsigned WrapperKind = X86ISD::Wrapper;
13078 CodeModel::Model M = DAG.getTarget().getCodeModel();
13080 if (Subtarget->isPICStyleRIPRel() &&
13081 (M == CodeModel::Small || M == CodeModel::Kernel))
13082 WrapperKind = X86ISD::WrapperRIP;
13083 else if (Subtarget->isPICStyleGOT())
13084 OpFlag = X86II::MO_GOTOFF;
13085 else if (Subtarget->isPICStyleStubPIC())
13086 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13088 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13089 CP->getAlignment(),
13090 CP->getOffset(), OpFlag);
13092 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13093 // With PIC, the address is actually $g + Offset.
13095 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13096 DAG.getNode(X86ISD::GlobalBaseReg,
13097 SDLoc(), getPointerTy()),
13104 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13105 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13107 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13108 // global base reg.
13109 unsigned char OpFlag = 0;
13110 unsigned WrapperKind = X86ISD::Wrapper;
13111 CodeModel::Model M = DAG.getTarget().getCodeModel();
13113 if (Subtarget->isPICStyleRIPRel() &&
13114 (M == CodeModel::Small || M == CodeModel::Kernel))
13115 WrapperKind = X86ISD::WrapperRIP;
13116 else if (Subtarget->isPICStyleGOT())
13117 OpFlag = X86II::MO_GOTOFF;
13118 else if (Subtarget->isPICStyleStubPIC())
13119 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13121 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13124 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13126 // With PIC, the address is actually $g + Offset.
13128 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13129 DAG.getNode(X86ISD::GlobalBaseReg,
13130 SDLoc(), getPointerTy()),
13137 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13138 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13140 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13141 // global base reg.
13142 unsigned char OpFlag = 0;
13143 unsigned WrapperKind = X86ISD::Wrapper;
13144 CodeModel::Model M = DAG.getTarget().getCodeModel();
13146 if (Subtarget->isPICStyleRIPRel() &&
13147 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13148 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13149 OpFlag = X86II::MO_GOTPCREL;
13150 WrapperKind = X86ISD::WrapperRIP;
13151 } else if (Subtarget->isPICStyleGOT()) {
13152 OpFlag = X86II::MO_GOT;
13153 } else if (Subtarget->isPICStyleStubPIC()) {
13154 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13155 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13156 OpFlag = X86II::MO_DARWIN_NONLAZY;
13159 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13162 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13164 // With PIC, the address is actually $g + Offset.
13165 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13166 !Subtarget->is64Bit()) {
13167 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13168 DAG.getNode(X86ISD::GlobalBaseReg,
13169 SDLoc(), getPointerTy()),
13173 // For symbols that require a load from a stub to get the address, emit the
13175 if (isGlobalStubReference(OpFlag))
13176 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13177 MachinePointerInfo::getGOT(), false, false, false, 0);
13183 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13184 // Create the TargetBlockAddressAddress node.
13185 unsigned char OpFlags =
13186 Subtarget->ClassifyBlockAddressReference();
13187 CodeModel::Model M = DAG.getTarget().getCodeModel();
13188 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13189 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13191 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13194 if (Subtarget->isPICStyleRIPRel() &&
13195 (M == CodeModel::Small || M == CodeModel::Kernel))
13196 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13198 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13200 // With PIC, the address is actually $g + Offset.
13201 if (isGlobalRelativeToPICBase(OpFlags)) {
13202 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13203 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13211 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13212 int64_t Offset, SelectionDAG &DAG) const {
13213 // Create the TargetGlobalAddress node, folding in the constant
13214 // offset if it is legal.
13215 unsigned char OpFlags =
13216 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13217 CodeModel::Model M = DAG.getTarget().getCodeModel();
13219 if (OpFlags == X86II::MO_NO_FLAG &&
13220 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13221 // A direct static reference to a global.
13222 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13225 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13228 if (Subtarget->isPICStyleRIPRel() &&
13229 (M == CodeModel::Small || M == CodeModel::Kernel))
13230 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13232 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13234 // With PIC, the address is actually $g + Offset.
13235 if (isGlobalRelativeToPICBase(OpFlags)) {
13236 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13237 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13241 // For globals that require a load from a stub to get the address, emit the
13243 if (isGlobalStubReference(OpFlags))
13244 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13245 MachinePointerInfo::getGOT(), false, false, false, 0);
13247 // If there was a non-zero offset that we didn't fold, create an explicit
13248 // addition for it.
13250 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13251 DAG.getConstant(Offset, getPointerTy()));
13257 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13258 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13259 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13260 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13264 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13265 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13266 unsigned char OperandFlags, bool LocalDynamic = false) {
13267 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13268 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13270 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13271 GA->getValueType(0),
13275 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13279 SDValue Ops[] = { Chain, TGA, *InFlag };
13280 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13282 SDValue Ops[] = { Chain, TGA };
13283 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13286 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13287 MFI->setAdjustsStack(true);
13288 MFI->setHasCalls(true);
13290 SDValue Flag = Chain.getValue(1);
13291 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13294 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13296 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13299 SDLoc dl(GA); // ? function entry point might be better
13300 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13301 DAG.getNode(X86ISD::GlobalBaseReg,
13302 SDLoc(), PtrVT), InFlag);
13303 InFlag = Chain.getValue(1);
13305 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13308 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13310 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13312 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13313 X86::RAX, X86II::MO_TLSGD);
13316 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13322 // Get the start address of the TLS block for this module.
13323 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13324 .getInfo<X86MachineFunctionInfo>();
13325 MFI->incNumLocalDynamicTLSAccesses();
13329 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13330 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13333 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13334 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13335 InFlag = Chain.getValue(1);
13336 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13337 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13340 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13344 unsigned char OperandFlags = X86II::MO_DTPOFF;
13345 unsigned WrapperKind = X86ISD::Wrapper;
13346 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13347 GA->getValueType(0),
13348 GA->getOffset(), OperandFlags);
13349 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13351 // Add x@dtpoff with the base.
13352 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13355 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13356 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13357 const EVT PtrVT, TLSModel::Model model,
13358 bool is64Bit, bool isPIC) {
13361 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13362 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13363 is64Bit ? 257 : 256));
13365 SDValue ThreadPointer =
13366 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13367 MachinePointerInfo(Ptr), false, false, false, 0);
13369 unsigned char OperandFlags = 0;
13370 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13372 unsigned WrapperKind = X86ISD::Wrapper;
13373 if (model == TLSModel::LocalExec) {
13374 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13375 } else if (model == TLSModel::InitialExec) {
13377 OperandFlags = X86II::MO_GOTTPOFF;
13378 WrapperKind = X86ISD::WrapperRIP;
13380 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13383 llvm_unreachable("Unexpected model");
13386 // emit "addl x@ntpoff,%eax" (local exec)
13387 // or "addl x@indntpoff,%eax" (initial exec)
13388 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13390 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13391 GA->getOffset(), OperandFlags);
13392 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13394 if (model == TLSModel::InitialExec) {
13395 if (isPIC && !is64Bit) {
13396 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13397 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13401 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13402 MachinePointerInfo::getGOT(), false, false, false, 0);
13405 // The address of the thread local variable is the add of the thread
13406 // pointer with the offset of the variable.
13407 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13411 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13413 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13414 const GlobalValue *GV = GA->getGlobal();
13416 if (Subtarget->isTargetELF()) {
13417 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13420 case TLSModel::GeneralDynamic:
13421 if (Subtarget->is64Bit())
13422 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13423 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13424 case TLSModel::LocalDynamic:
13425 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13426 Subtarget->is64Bit());
13427 case TLSModel::InitialExec:
13428 case TLSModel::LocalExec:
13429 return LowerToTLSExecModel(
13430 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13431 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13433 llvm_unreachable("Unknown TLS model.");
13436 if (Subtarget->isTargetDarwin()) {
13437 // Darwin only has one model of TLS. Lower to that.
13438 unsigned char OpFlag = 0;
13439 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13440 X86ISD::WrapperRIP : X86ISD::Wrapper;
13442 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13443 // global base reg.
13444 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13445 !Subtarget->is64Bit();
13447 OpFlag = X86II::MO_TLVP_PIC_BASE;
13449 OpFlag = X86II::MO_TLVP;
13451 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13452 GA->getValueType(0),
13453 GA->getOffset(), OpFlag);
13454 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13456 // With PIC32, the address is actually $g + Offset.
13458 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13459 DAG.getNode(X86ISD::GlobalBaseReg,
13460 SDLoc(), getPointerTy()),
13463 // Lowering the machine isd will make sure everything is in the right
13465 SDValue Chain = DAG.getEntryNode();
13466 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13467 SDValue Args[] = { Chain, Offset };
13468 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13470 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13471 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13472 MFI->setAdjustsStack(true);
13474 // And our return value (tls address) is in the standard call return value
13476 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13477 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13478 Chain.getValue(1));
13481 if (Subtarget->isTargetKnownWindowsMSVC() ||
13482 Subtarget->isTargetWindowsGNU()) {
13483 // Just use the implicit TLS architecture
13484 // Need to generate someting similar to:
13485 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13487 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13488 // mov rcx, qword [rdx+rcx*8]
13489 // mov eax, .tls$:tlsvar
13490 // [rax+rcx] contains the address
13491 // Windows 64bit: gs:0x58
13492 // Windows 32bit: fs:__tls_array
13495 SDValue Chain = DAG.getEntryNode();
13497 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13498 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13499 // use its literal value of 0x2C.
13500 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13501 ? Type::getInt8PtrTy(*DAG.getContext(),
13503 : Type::getInt32PtrTy(*DAG.getContext(),
13507 Subtarget->is64Bit()
13508 ? DAG.getIntPtrConstant(0x58)
13509 : (Subtarget->isTargetWindowsGNU()
13510 ? DAG.getIntPtrConstant(0x2C)
13511 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13513 SDValue ThreadPointer =
13514 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13515 MachinePointerInfo(Ptr), false, false, false, 0);
13517 // Load the _tls_index variable
13518 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13519 if (Subtarget->is64Bit())
13520 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13521 IDX, MachinePointerInfo(), MVT::i32,
13522 false, false, false, 0);
13524 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13525 false, false, false, 0);
13527 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13529 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13531 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13532 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13533 false, false, false, 0);
13535 // Get the offset of start of .tls section
13536 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13537 GA->getValueType(0),
13538 GA->getOffset(), X86II::MO_SECREL);
13539 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13541 // The address of the thread local variable is the add of the thread
13542 // pointer with the offset of the variable.
13543 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13546 llvm_unreachable("TLS not implemented for this target.");
13549 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13550 /// and take a 2 x i32 value to shift plus a shift amount.
13551 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13552 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13553 MVT VT = Op.getSimpleValueType();
13554 unsigned VTBits = VT.getSizeInBits();
13556 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13557 SDValue ShOpLo = Op.getOperand(0);
13558 SDValue ShOpHi = Op.getOperand(1);
13559 SDValue ShAmt = Op.getOperand(2);
13560 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13561 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13563 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13564 DAG.getConstant(VTBits - 1, MVT::i8));
13565 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13566 DAG.getConstant(VTBits - 1, MVT::i8))
13567 : DAG.getConstant(0, VT);
13569 SDValue Tmp2, Tmp3;
13570 if (Op.getOpcode() == ISD::SHL_PARTS) {
13571 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13572 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13574 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13575 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13578 // If the shift amount is larger or equal than the width of a part we can't
13579 // rely on the results of shld/shrd. Insert a test and select the appropriate
13580 // values for large shift amounts.
13581 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13582 DAG.getConstant(VTBits, MVT::i8));
13583 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13584 AndNode, DAG.getConstant(0, MVT::i8));
13587 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13588 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13589 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13591 if (Op.getOpcode() == ISD::SHL_PARTS) {
13592 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13593 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13595 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13596 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13599 SDValue Ops[2] = { Lo, Hi };
13600 return DAG.getMergeValues(Ops, dl);
13603 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13604 SelectionDAG &DAG) const {
13605 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13608 if (SrcVT.isVector()) {
13609 if (SrcVT.getVectorElementType() == MVT::i1) {
13610 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13611 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13612 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13613 Op.getOperand(0)));
13618 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13619 "Unknown SINT_TO_FP to lower!");
13621 // These are really Legal; return the operand so the caller accepts it as
13623 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13625 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13626 Subtarget->is64Bit()) {
13630 unsigned Size = SrcVT.getSizeInBits()/8;
13631 MachineFunction &MF = DAG.getMachineFunction();
13632 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13633 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13634 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13636 MachinePointerInfo::getFixedStack(SSFI),
13638 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13641 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13643 SelectionDAG &DAG) const {
13647 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13649 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13651 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13653 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13655 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13656 MachineMemOperand *MMO;
13658 int SSFI = FI->getIndex();
13660 DAG.getMachineFunction()
13661 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13662 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13664 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13665 StackSlot = StackSlot.getOperand(1);
13667 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13668 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13670 Tys, Ops, SrcVT, MMO);
13673 Chain = Result.getValue(1);
13674 SDValue InFlag = Result.getValue(2);
13676 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13677 // shouldn't be necessary except that RFP cannot be live across
13678 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13679 MachineFunction &MF = DAG.getMachineFunction();
13680 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13681 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13682 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13683 Tys = DAG.getVTList(MVT::Other);
13685 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13687 MachineMemOperand *MMO =
13688 DAG.getMachineFunction()
13689 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13690 MachineMemOperand::MOStore, SSFISize, SSFISize);
13692 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13693 Ops, Op.getValueType(), MMO);
13694 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13695 MachinePointerInfo::getFixedStack(SSFI),
13696 false, false, false, 0);
13702 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13703 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13704 SelectionDAG &DAG) const {
13705 // This algorithm is not obvious. Here it is what we're trying to output:
13708 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13709 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13711 haddpd %xmm0, %xmm0
13713 pshufd $0x4e, %xmm0, %xmm1
13719 LLVMContext *Context = DAG.getContext();
13721 // Build some magic constants.
13722 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13723 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13724 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13726 SmallVector<Constant*,2> CV1;
13728 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13729 APInt(64, 0x4330000000000000ULL))));
13731 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13732 APInt(64, 0x4530000000000000ULL))));
13733 Constant *C1 = ConstantVector::get(CV1);
13734 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13736 // Load the 64-bit value into an XMM register.
13737 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13739 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13740 MachinePointerInfo::getConstantPool(),
13741 false, false, false, 16);
13742 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13743 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13746 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13747 MachinePointerInfo::getConstantPool(),
13748 false, false, false, 16);
13749 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13750 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13753 if (Subtarget->hasSSE3()) {
13754 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13755 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13757 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13758 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13760 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13761 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13765 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13766 DAG.getIntPtrConstant(0));
13769 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13770 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13771 SelectionDAG &DAG) const {
13773 // FP constant to bias correct the final result.
13774 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13777 // Load the 32-bit value into an XMM register.
13778 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13781 // Zero out the upper parts of the register.
13782 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13784 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13785 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13786 DAG.getIntPtrConstant(0));
13788 // Or the load with the bias.
13789 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13790 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13791 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13792 MVT::v2f64, Load)),
13793 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13794 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13795 MVT::v2f64, Bias)));
13796 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13797 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13798 DAG.getIntPtrConstant(0));
13800 // Subtract the bias.
13801 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13803 // Handle final rounding.
13804 EVT DestVT = Op.getValueType();
13806 if (DestVT.bitsLT(MVT::f64))
13807 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13808 DAG.getIntPtrConstant(0));
13809 if (DestVT.bitsGT(MVT::f64))
13810 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13812 // Handle final rounding.
13816 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13817 const X86Subtarget &Subtarget) {
13818 // The algorithm is the following:
13819 // #ifdef __SSE4_1__
13820 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13821 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13822 // (uint4) 0x53000000, 0xaa);
13824 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13825 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13827 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13828 // return (float4) lo + fhi;
13831 SDValue V = Op->getOperand(0);
13832 EVT VecIntVT = V.getValueType();
13833 bool Is128 = VecIntVT == MVT::v4i32;
13834 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13835 // If we convert to something else than the supported type, e.g., to v4f64,
13837 if (VecFloatVT != Op->getValueType(0))
13840 unsigned NumElts = VecIntVT.getVectorNumElements();
13841 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13842 "Unsupported custom type");
13843 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13845 // In the #idef/#else code, we have in common:
13846 // - The vector of constants:
13852 // Create the splat vector for 0x4b000000.
13853 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13854 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13855 CstLow, CstLow, CstLow, CstLow};
13856 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13857 makeArrayRef(&CstLowArray[0], NumElts));
13858 // Create the splat vector for 0x53000000.
13859 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13860 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13861 CstHigh, CstHigh, CstHigh, CstHigh};
13862 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13863 makeArrayRef(&CstHighArray[0], NumElts));
13865 // Create the right shift.
13866 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13867 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13868 CstShift, CstShift, CstShift, CstShift};
13869 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13870 makeArrayRef(&CstShiftArray[0], NumElts));
13871 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13874 if (Subtarget.hasSSE41()) {
13875 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13876 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13877 SDValue VecCstLowBitcast =
13878 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13879 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13880 // Low will be bitcasted right away, so do not bother bitcasting back to its
13882 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13883 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13884 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13885 // (uint4) 0x53000000, 0xaa);
13886 SDValue VecCstHighBitcast =
13887 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13888 SDValue VecShiftBitcast =
13889 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13890 // High will be bitcasted right away, so do not bother bitcasting back to
13891 // its original type.
13892 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13893 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13895 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13896 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13897 CstMask, CstMask, CstMask);
13898 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13899 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13900 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13902 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13903 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13906 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13907 SDValue CstFAdd = DAG.getConstantFP(
13908 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13909 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13910 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13911 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13912 makeArrayRef(&CstFAddArray[0], NumElts));
13914 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13915 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13917 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13918 // return (float4) lo + fhi;
13919 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13920 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13923 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13924 SelectionDAG &DAG) const {
13925 SDValue N0 = Op.getOperand(0);
13926 MVT SVT = N0.getSimpleValueType();
13929 switch (SVT.SimpleTy) {
13931 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13936 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13937 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13938 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13942 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13944 llvm_unreachable(nullptr);
13947 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13948 SelectionDAG &DAG) const {
13949 SDValue N0 = Op.getOperand(0);
13952 if (Op.getValueType().isVector())
13953 return lowerUINT_TO_FP_vec(Op, DAG);
13955 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13956 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13957 // the optimization here.
13958 if (DAG.SignBitIsZero(N0))
13959 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13961 MVT SrcVT = N0.getSimpleValueType();
13962 MVT DstVT = Op.getSimpleValueType();
13963 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13964 return LowerUINT_TO_FP_i64(Op, DAG);
13965 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13966 return LowerUINT_TO_FP_i32(Op, DAG);
13967 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13970 // Make a 64-bit buffer, and use it to build an FILD.
13971 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13972 if (SrcVT == MVT::i32) {
13973 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13974 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13975 getPointerTy(), StackSlot, WordOff);
13976 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13977 StackSlot, MachinePointerInfo(),
13979 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13980 OffsetSlot, MachinePointerInfo(),
13982 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13986 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13987 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13988 StackSlot, MachinePointerInfo(),
13990 // For i64 source, we need to add the appropriate power of 2 if the input
13991 // was negative. This is the same as the optimization in
13992 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13993 // we must be careful to do the computation in x87 extended precision, not
13994 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13995 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13996 MachineMemOperand *MMO =
13997 DAG.getMachineFunction()
13998 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13999 MachineMemOperand::MOLoad, 8, 8);
14001 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
14002 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
14003 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
14006 APInt FF(32, 0x5F800000ULL);
14008 // Check whether the sign bit is set.
14009 SDValue SignSet = DAG.getSetCC(dl,
14010 getSetCCResultType(*DAG.getContext(), MVT::i64),
14011 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14014 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14015 SDValue FudgePtr = DAG.getConstantPool(
14016 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14019 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14020 SDValue Zero = DAG.getIntPtrConstant(0);
14021 SDValue Four = DAG.getIntPtrConstant(4);
14022 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14024 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14026 // Load the value out, extending it from f32 to f80.
14027 // FIXME: Avoid the extend by constructing the right constant pool?
14028 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14029 FudgePtr, MachinePointerInfo::getConstantPool(),
14030 MVT::f32, false, false, false, 4);
14031 // Extend everything to 80 bits to force it to be done on x87.
14032 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14033 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14036 std::pair<SDValue,SDValue>
14037 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14038 bool IsSigned, bool IsReplace) const {
14041 EVT DstTy = Op.getValueType();
14043 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14044 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14048 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14049 DstTy.getSimpleVT() >= MVT::i16 &&
14050 "Unknown FP_TO_INT to lower!");
14052 // These are really Legal.
14053 if (DstTy == MVT::i32 &&
14054 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14055 return std::make_pair(SDValue(), SDValue());
14056 if (Subtarget->is64Bit() &&
14057 DstTy == MVT::i64 &&
14058 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14059 return std::make_pair(SDValue(), SDValue());
14061 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14062 // stack slot, or into the FTOL runtime function.
14063 MachineFunction &MF = DAG.getMachineFunction();
14064 unsigned MemSize = DstTy.getSizeInBits()/8;
14065 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14066 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14069 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14070 Opc = X86ISD::WIN_FTOL;
14072 switch (DstTy.getSimpleVT().SimpleTy) {
14073 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14074 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14075 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14076 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14079 SDValue Chain = DAG.getEntryNode();
14080 SDValue Value = Op.getOperand(0);
14081 EVT TheVT = Op.getOperand(0).getValueType();
14082 // FIXME This causes a redundant load/store if the SSE-class value is already
14083 // in memory, such as if it is on the callstack.
14084 if (isScalarFPTypeInSSEReg(TheVT)) {
14085 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14086 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14087 MachinePointerInfo::getFixedStack(SSFI),
14089 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14091 Chain, StackSlot, DAG.getValueType(TheVT)
14094 MachineMemOperand *MMO =
14095 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14096 MachineMemOperand::MOLoad, MemSize, MemSize);
14097 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14098 Chain = Value.getValue(1);
14099 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14100 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14103 MachineMemOperand *MMO =
14104 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14105 MachineMemOperand::MOStore, MemSize, MemSize);
14107 if (Opc != X86ISD::WIN_FTOL) {
14108 // Build the FP_TO_INT*_IN_MEM
14109 SDValue Ops[] = { Chain, Value, StackSlot };
14110 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14112 return std::make_pair(FIST, StackSlot);
14114 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14115 DAG.getVTList(MVT::Other, MVT::Glue),
14117 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14118 MVT::i32, ftol.getValue(1));
14119 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14120 MVT::i32, eax.getValue(2));
14121 SDValue Ops[] = { eax, edx };
14122 SDValue pair = IsReplace
14123 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14124 : DAG.getMergeValues(Ops, DL);
14125 return std::make_pair(pair, SDValue());
14129 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14130 const X86Subtarget *Subtarget) {
14131 MVT VT = Op->getSimpleValueType(0);
14132 SDValue In = Op->getOperand(0);
14133 MVT InVT = In.getSimpleValueType();
14136 // Optimize vectors in AVX mode:
14139 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14140 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14141 // Concat upper and lower parts.
14144 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14145 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14146 // Concat upper and lower parts.
14149 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14150 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14151 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14154 if (Subtarget->hasInt256())
14155 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14157 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14158 SDValue Undef = DAG.getUNDEF(InVT);
14159 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14160 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14161 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14163 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14164 VT.getVectorNumElements()/2);
14166 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14167 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14169 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14172 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14173 SelectionDAG &DAG) {
14174 MVT VT = Op->getSimpleValueType(0);
14175 SDValue In = Op->getOperand(0);
14176 MVT InVT = In.getSimpleValueType();
14178 unsigned int NumElts = VT.getVectorNumElements();
14179 if (NumElts != 8 && NumElts != 16)
14182 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14183 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14185 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14186 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14187 // Now we have only mask extension
14188 assert(InVT.getVectorElementType() == MVT::i1);
14189 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14190 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14191 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14192 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14193 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14194 MachinePointerInfo::getConstantPool(),
14195 false, false, false, Alignment);
14197 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14198 if (VT.is512BitVector())
14200 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14203 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14204 SelectionDAG &DAG) {
14205 if (Subtarget->hasFp256()) {
14206 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14214 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14215 SelectionDAG &DAG) {
14217 MVT VT = Op.getSimpleValueType();
14218 SDValue In = Op.getOperand(0);
14219 MVT SVT = In.getSimpleValueType();
14221 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14222 return LowerZERO_EXTEND_AVX512(Op, DAG);
14224 if (Subtarget->hasFp256()) {
14225 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14230 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14231 VT.getVectorNumElements() != SVT.getVectorNumElements());
14235 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14237 MVT VT = Op.getSimpleValueType();
14238 SDValue In = Op.getOperand(0);
14239 MVT InVT = In.getSimpleValueType();
14241 if (VT == MVT::i1) {
14242 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14243 "Invalid scalar TRUNCATE operation");
14244 if (InVT.getSizeInBits() >= 32)
14246 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14247 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14249 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14250 "Invalid TRUNCATE operation");
14252 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14253 if (VT.getVectorElementType().getSizeInBits() >=8)
14254 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14256 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14257 unsigned NumElts = InVT.getVectorNumElements();
14258 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14259 if (InVT.getSizeInBits() < 512) {
14260 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14261 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14265 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14266 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14267 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14268 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14269 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14270 MachinePointerInfo::getConstantPool(),
14271 false, false, false, Alignment);
14272 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14273 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14274 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14277 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14278 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14279 if (Subtarget->hasInt256()) {
14280 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14281 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14282 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14284 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14285 DAG.getIntPtrConstant(0));
14288 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14289 DAG.getIntPtrConstant(0));
14290 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14291 DAG.getIntPtrConstant(2));
14292 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14293 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14294 static const int ShufMask[] = {0, 2, 4, 6};
14295 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14298 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14299 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14300 if (Subtarget->hasInt256()) {
14301 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14303 SmallVector<SDValue,32> pshufbMask;
14304 for (unsigned i = 0; i < 2; ++i) {
14305 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14306 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14307 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14308 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14309 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14310 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14311 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14312 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14313 for (unsigned j = 0; j < 8; ++j)
14314 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14316 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14317 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14318 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14320 static const int ShufMask[] = {0, 2, -1, -1};
14321 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14323 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14324 DAG.getIntPtrConstant(0));
14325 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14328 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14329 DAG.getIntPtrConstant(0));
14331 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14332 DAG.getIntPtrConstant(4));
14334 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14335 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14337 // The PSHUFB mask:
14338 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14339 -1, -1, -1, -1, -1, -1, -1, -1};
14341 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14342 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14343 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14345 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14346 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14348 // The MOVLHPS Mask:
14349 static const int ShufMask2[] = {0, 1, 4, 5};
14350 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14351 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14354 // Handle truncation of V256 to V128 using shuffles.
14355 if (!VT.is128BitVector() || !InVT.is256BitVector())
14358 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14360 unsigned NumElems = VT.getVectorNumElements();
14361 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14363 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14364 // Prepare truncation shuffle mask
14365 for (unsigned i = 0; i != NumElems; ++i)
14366 MaskVec[i] = i * 2;
14367 SDValue V = DAG.getVectorShuffle(NVT, DL,
14368 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14369 DAG.getUNDEF(NVT), &MaskVec[0]);
14370 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14371 DAG.getIntPtrConstant(0));
14374 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14375 SelectionDAG &DAG) const {
14376 assert(!Op.getSimpleValueType().isVector());
14378 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14379 /*IsSigned=*/ true, /*IsReplace=*/ false);
14380 SDValue FIST = Vals.first, StackSlot = Vals.second;
14381 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14382 if (!FIST.getNode()) return Op;
14384 if (StackSlot.getNode())
14385 // Load the result.
14386 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14387 FIST, StackSlot, MachinePointerInfo(),
14388 false, false, false, 0);
14390 // The node is the result.
14394 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14395 SelectionDAG &DAG) const {
14396 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14397 /*IsSigned=*/ false, /*IsReplace=*/ false);
14398 SDValue FIST = Vals.first, StackSlot = Vals.second;
14399 assert(FIST.getNode() && "Unexpected failure");
14401 if (StackSlot.getNode())
14402 // Load the result.
14403 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14404 FIST, StackSlot, MachinePointerInfo(),
14405 false, false, false, 0);
14407 // The node is the result.
14411 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14413 MVT VT = Op.getSimpleValueType();
14414 SDValue In = Op.getOperand(0);
14415 MVT SVT = In.getSimpleValueType();
14417 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14419 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14420 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14421 In, DAG.getUNDEF(SVT)));
14424 /// The only differences between FABS and FNEG are the mask and the logic op.
14425 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14426 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14427 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14428 "Wrong opcode for lowering FABS or FNEG.");
14430 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14432 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14433 // into an FNABS. We'll lower the FABS after that if it is still in use.
14435 for (SDNode *User : Op->uses())
14436 if (User->getOpcode() == ISD::FNEG)
14439 SDValue Op0 = Op.getOperand(0);
14440 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14443 MVT VT = Op.getSimpleValueType();
14444 // Assume scalar op for initialization; update for vector if needed.
14445 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14446 // generate a 16-byte vector constant and logic op even for the scalar case.
14447 // Using a 16-byte mask allows folding the load of the mask with
14448 // the logic op, so it can save (~4 bytes) on code size.
14450 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14451 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14452 // decide if we should generate a 16-byte constant mask when we only need 4 or
14453 // 8 bytes for the scalar case.
14454 if (VT.isVector()) {
14455 EltVT = VT.getVectorElementType();
14456 NumElts = VT.getVectorNumElements();
14459 unsigned EltBits = EltVT.getSizeInBits();
14460 LLVMContext *Context = DAG.getContext();
14461 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14463 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14464 Constant *C = ConstantInt::get(*Context, MaskElt);
14465 C = ConstantVector::getSplat(NumElts, C);
14466 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14467 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14468 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14469 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14470 MachinePointerInfo::getConstantPool(),
14471 false, false, false, Alignment);
14473 if (VT.isVector()) {
14474 // For a vector, cast operands to a vector type, perform the logic op,
14475 // and cast the result back to the original value type.
14476 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14477 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14478 SDValue Operand = IsFNABS ?
14479 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14480 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14481 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14482 return DAG.getNode(ISD::BITCAST, dl, VT,
14483 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14486 // If not vector, then scalar.
14487 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14488 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14489 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14492 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14493 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14494 LLVMContext *Context = DAG.getContext();
14495 SDValue Op0 = Op.getOperand(0);
14496 SDValue Op1 = Op.getOperand(1);
14498 MVT VT = Op.getSimpleValueType();
14499 MVT SrcVT = Op1.getSimpleValueType();
14501 // If second operand is smaller, extend it first.
14502 if (SrcVT.bitsLT(VT)) {
14503 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14506 // And if it is bigger, shrink it first.
14507 if (SrcVT.bitsGT(VT)) {
14508 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14512 // At this point the operands and the result should have the same
14513 // type, and that won't be f80 since that is not custom lowered.
14515 const fltSemantics &Sem =
14516 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14517 const unsigned SizeInBits = VT.getSizeInBits();
14519 SmallVector<Constant *, 4> CV(
14520 VT == MVT::f64 ? 2 : 4,
14521 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14523 // First, clear all bits but the sign bit from the second operand (sign).
14524 CV[0] = ConstantFP::get(*Context,
14525 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14526 Constant *C = ConstantVector::get(CV);
14527 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14528 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14529 MachinePointerInfo::getConstantPool(),
14530 false, false, false, 16);
14531 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14533 // Next, clear the sign bit from the first operand (magnitude).
14534 // If it's a constant, we can clear it here.
14535 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
14536 APFloat APF = Op0CN->getValueAPF();
14537 // If the magnitude is a positive zero, the sign bit alone is enough.
14538 if (APF.isPosZero())
14541 CV[0] = ConstantFP::get(*Context, APF);
14543 CV[0] = ConstantFP::get(
14545 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14547 C = ConstantVector::get(CV);
14548 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14549 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14550 MachinePointerInfo::getConstantPool(),
14551 false, false, false, 16);
14552 // If the magnitude operand wasn't a constant, we need to AND out the sign.
14553 if (!isa<ConstantFPSDNode>(Op0))
14554 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
14556 // OR the magnitude value with the sign bit.
14557 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14560 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14561 SDValue N0 = Op.getOperand(0);
14563 MVT VT = Op.getSimpleValueType();
14565 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14566 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14567 DAG.getConstant(1, VT));
14568 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14571 // Check whether an OR'd tree is PTEST-able.
14572 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14573 SelectionDAG &DAG) {
14574 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14576 if (!Subtarget->hasSSE41())
14579 if (!Op->hasOneUse())
14582 SDNode *N = Op.getNode();
14585 SmallVector<SDValue, 8> Opnds;
14586 DenseMap<SDValue, unsigned> VecInMap;
14587 SmallVector<SDValue, 8> VecIns;
14588 EVT VT = MVT::Other;
14590 // Recognize a special case where a vector is casted into wide integer to
14592 Opnds.push_back(N->getOperand(0));
14593 Opnds.push_back(N->getOperand(1));
14595 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14596 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14597 // BFS traverse all OR'd operands.
14598 if (I->getOpcode() == ISD::OR) {
14599 Opnds.push_back(I->getOperand(0));
14600 Opnds.push_back(I->getOperand(1));
14601 // Re-evaluate the number of nodes to be traversed.
14602 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14606 // Quit if a non-EXTRACT_VECTOR_ELT
14607 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14610 // Quit if without a constant index.
14611 SDValue Idx = I->getOperand(1);
14612 if (!isa<ConstantSDNode>(Idx))
14615 SDValue ExtractedFromVec = I->getOperand(0);
14616 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14617 if (M == VecInMap.end()) {
14618 VT = ExtractedFromVec.getValueType();
14619 // Quit if not 128/256-bit vector.
14620 if (!VT.is128BitVector() && !VT.is256BitVector())
14622 // Quit if not the same type.
14623 if (VecInMap.begin() != VecInMap.end() &&
14624 VT != VecInMap.begin()->first.getValueType())
14626 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14627 VecIns.push_back(ExtractedFromVec);
14629 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14632 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14633 "Not extracted from 128-/256-bit vector.");
14635 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14637 for (DenseMap<SDValue, unsigned>::const_iterator
14638 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14639 // Quit if not all elements are used.
14640 if (I->second != FullMask)
14644 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14646 // Cast all vectors into TestVT for PTEST.
14647 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14648 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14650 // If more than one full vectors are evaluated, OR them first before PTEST.
14651 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14652 // Each iteration will OR 2 nodes and append the result until there is only
14653 // 1 node left, i.e. the final OR'd value of all vectors.
14654 SDValue LHS = VecIns[Slot];
14655 SDValue RHS = VecIns[Slot + 1];
14656 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14659 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14660 VecIns.back(), VecIns.back());
14663 /// \brief return true if \c Op has a use that doesn't just read flags.
14664 static bool hasNonFlagsUse(SDValue Op) {
14665 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14667 SDNode *User = *UI;
14668 unsigned UOpNo = UI.getOperandNo();
14669 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14670 // Look pass truncate.
14671 UOpNo = User->use_begin().getOperandNo();
14672 User = *User->use_begin();
14675 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14676 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14682 /// Emit nodes that will be selected as "test Op0,Op0", or something
14684 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14685 SelectionDAG &DAG) const {
14686 if (Op.getValueType() == MVT::i1)
14687 // KORTEST instruction should be selected
14688 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14689 DAG.getConstant(0, Op.getValueType()));
14691 // CF and OF aren't always set the way we want. Determine which
14692 // of these we need.
14693 bool NeedCF = false;
14694 bool NeedOF = false;
14697 case X86::COND_A: case X86::COND_AE:
14698 case X86::COND_B: case X86::COND_BE:
14701 case X86::COND_G: case X86::COND_GE:
14702 case X86::COND_L: case X86::COND_LE:
14703 case X86::COND_O: case X86::COND_NO: {
14704 // Check if we really need to set the
14705 // Overflow flag. If NoSignedWrap is present
14706 // that is not actually needed.
14707 switch (Op->getOpcode()) {
14712 const BinaryWithFlagsSDNode *BinNode =
14713 cast<BinaryWithFlagsSDNode>(Op.getNode());
14714 if (BinNode->hasNoSignedWrap())
14724 // See if we can use the EFLAGS value from the operand instead of
14725 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14726 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14727 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14728 // Emit a CMP with 0, which is the TEST pattern.
14729 //if (Op.getValueType() == MVT::i1)
14730 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14731 // DAG.getConstant(0, MVT::i1));
14732 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14733 DAG.getConstant(0, Op.getValueType()));
14735 unsigned Opcode = 0;
14736 unsigned NumOperands = 0;
14738 // Truncate operations may prevent the merge of the SETCC instruction
14739 // and the arithmetic instruction before it. Attempt to truncate the operands
14740 // of the arithmetic instruction and use a reduced bit-width instruction.
14741 bool NeedTruncation = false;
14742 SDValue ArithOp = Op;
14743 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14744 SDValue Arith = Op->getOperand(0);
14745 // Both the trunc and the arithmetic op need to have one user each.
14746 if (Arith->hasOneUse())
14747 switch (Arith.getOpcode()) {
14754 NeedTruncation = true;
14760 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14761 // which may be the result of a CAST. We use the variable 'Op', which is the
14762 // non-casted variable when we check for possible users.
14763 switch (ArithOp.getOpcode()) {
14765 // Due to an isel shortcoming, be conservative if this add is likely to be
14766 // selected as part of a load-modify-store instruction. When the root node
14767 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14768 // uses of other nodes in the match, such as the ADD in this case. This
14769 // leads to the ADD being left around and reselected, with the result being
14770 // two adds in the output. Alas, even if none our users are stores, that
14771 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14772 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14773 // climbing the DAG back to the root, and it doesn't seem to be worth the
14775 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14776 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14777 if (UI->getOpcode() != ISD::CopyToReg &&
14778 UI->getOpcode() != ISD::SETCC &&
14779 UI->getOpcode() != ISD::STORE)
14782 if (ConstantSDNode *C =
14783 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14784 // An add of one will be selected as an INC.
14785 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14786 Opcode = X86ISD::INC;
14791 // An add of negative one (subtract of one) will be selected as a DEC.
14792 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14793 Opcode = X86ISD::DEC;
14799 // Otherwise use a regular EFLAGS-setting add.
14800 Opcode = X86ISD::ADD;
14805 // If we have a constant logical shift that's only used in a comparison
14806 // against zero turn it into an equivalent AND. This allows turning it into
14807 // a TEST instruction later.
14808 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14809 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14810 EVT VT = Op.getValueType();
14811 unsigned BitWidth = VT.getSizeInBits();
14812 unsigned ShAmt = Op->getConstantOperandVal(1);
14813 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14815 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14816 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14817 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14818 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14820 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14821 DAG.getConstant(Mask, VT));
14822 DAG.ReplaceAllUsesWith(Op, New);
14828 // If the primary and result isn't used, don't bother using X86ISD::AND,
14829 // because a TEST instruction will be better.
14830 if (!hasNonFlagsUse(Op))
14836 // Due to the ISEL shortcoming noted above, be conservative if this op is
14837 // likely to be selected as part of a load-modify-store instruction.
14838 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14839 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14840 if (UI->getOpcode() == ISD::STORE)
14843 // Otherwise use a regular EFLAGS-setting instruction.
14844 switch (ArithOp.getOpcode()) {
14845 default: llvm_unreachable("unexpected operator!");
14846 case ISD::SUB: Opcode = X86ISD::SUB; break;
14847 case ISD::XOR: Opcode = X86ISD::XOR; break;
14848 case ISD::AND: Opcode = X86ISD::AND; break;
14850 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14851 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14852 if (EFLAGS.getNode())
14855 Opcode = X86ISD::OR;
14869 return SDValue(Op.getNode(), 1);
14875 // If we found that truncation is beneficial, perform the truncation and
14877 if (NeedTruncation) {
14878 EVT VT = Op.getValueType();
14879 SDValue WideVal = Op->getOperand(0);
14880 EVT WideVT = WideVal.getValueType();
14881 unsigned ConvertedOp = 0;
14882 // Use a target machine opcode to prevent further DAGCombine
14883 // optimizations that may separate the arithmetic operations
14884 // from the setcc node.
14885 switch (WideVal.getOpcode()) {
14887 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14888 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14889 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14890 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14891 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14896 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14897 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14898 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14899 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14905 // Emit a CMP with 0, which is the TEST pattern.
14906 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14907 DAG.getConstant(0, Op.getValueType()));
14909 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14910 SmallVector<SDValue, 4> Ops;
14911 for (unsigned i = 0; i != NumOperands; ++i)
14912 Ops.push_back(Op.getOperand(i));
14914 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14915 DAG.ReplaceAllUsesWith(Op, New);
14916 return SDValue(New.getNode(), 1);
14919 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14921 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14922 SDLoc dl, SelectionDAG &DAG) const {
14923 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14924 if (C->getAPIntValue() == 0)
14925 return EmitTest(Op0, X86CC, dl, DAG);
14927 if (Op0.getValueType() == MVT::i1)
14928 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14931 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14932 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14933 // Do the comparison at i32 if it's smaller, besides the Atom case.
14934 // This avoids subregister aliasing issues. Keep the smaller reference
14935 // if we're optimizing for size, however, as that'll allow better folding
14936 // of memory operations.
14937 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14938 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14939 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14940 !Subtarget->isAtom()) {
14941 unsigned ExtendOp =
14942 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14943 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14944 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14946 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14947 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14948 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14950 return SDValue(Sub.getNode(), 1);
14952 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14955 /// Convert a comparison if required by the subtarget.
14956 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14957 SelectionDAG &DAG) const {
14958 // If the subtarget does not support the FUCOMI instruction, floating-point
14959 // comparisons have to be converted.
14960 if (Subtarget->hasCMov() ||
14961 Cmp.getOpcode() != X86ISD::CMP ||
14962 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14963 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14966 // The instruction selector will select an FUCOM instruction instead of
14967 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14968 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14969 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14971 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14972 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14973 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14974 DAG.getConstant(8, MVT::i8));
14975 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14976 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14979 /// The minimum architected relative accuracy is 2^-12. We need one
14980 /// Newton-Raphson step to have a good float result (24 bits of precision).
14981 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14982 DAGCombinerInfo &DCI,
14983 unsigned &RefinementSteps,
14984 bool &UseOneConstNR) const {
14985 // FIXME: We should use instruction latency models to calculate the cost of
14986 // each potential sequence, but this is very hard to do reliably because
14987 // at least Intel's Core* chips have variable timing based on the number of
14988 // significant digits in the divisor and/or sqrt operand.
14989 if (!Subtarget->useSqrtEst())
14992 EVT VT = Op.getValueType();
14994 // SSE1 has rsqrtss and rsqrtps.
14995 // TODO: Add support for AVX512 (v16f32).
14996 // It is likely not profitable to do this for f64 because a double-precision
14997 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14998 // instructions: convert to single, rsqrtss, convert back to double, refine
14999 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
15000 // along with FMA, this could be a throughput win.
15001 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15002 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15003 RefinementSteps = 1;
15004 UseOneConstNR = false;
15005 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
15010 /// The minimum architected relative accuracy is 2^-12. We need one
15011 /// Newton-Raphson step to have a good float result (24 bits of precision).
15012 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
15013 DAGCombinerInfo &DCI,
15014 unsigned &RefinementSteps) const {
15015 // FIXME: We should use instruction latency models to calculate the cost of
15016 // each potential sequence, but this is very hard to do reliably because
15017 // at least Intel's Core* chips have variable timing based on the number of
15018 // significant digits in the divisor.
15019 if (!Subtarget->useReciprocalEst())
15022 EVT VT = Op.getValueType();
15024 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
15025 // TODO: Add support for AVX512 (v16f32).
15026 // It is likely not profitable to do this for f64 because a double-precision
15027 // reciprocal estimate with refinement on x86 prior to FMA requires
15028 // 15 instructions: convert to single, rcpss, convert back to double, refine
15029 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15030 // along with FMA, this could be a throughput win.
15031 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15032 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15033 RefinementSteps = ReciprocalEstimateRefinementSteps;
15034 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15039 static bool isAllOnes(SDValue V) {
15040 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15041 return C && C->isAllOnesValue();
15044 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15045 /// if it's possible.
15046 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15047 SDLoc dl, SelectionDAG &DAG) const {
15048 SDValue Op0 = And.getOperand(0);
15049 SDValue Op1 = And.getOperand(1);
15050 if (Op0.getOpcode() == ISD::TRUNCATE)
15051 Op0 = Op0.getOperand(0);
15052 if (Op1.getOpcode() == ISD::TRUNCATE)
15053 Op1 = Op1.getOperand(0);
15056 if (Op1.getOpcode() == ISD::SHL)
15057 std::swap(Op0, Op1);
15058 if (Op0.getOpcode() == ISD::SHL) {
15059 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15060 if (And00C->getZExtValue() == 1) {
15061 // If we looked past a truncate, check that it's only truncating away
15063 unsigned BitWidth = Op0.getValueSizeInBits();
15064 unsigned AndBitWidth = And.getValueSizeInBits();
15065 if (BitWidth > AndBitWidth) {
15067 DAG.computeKnownBits(Op0, Zeros, Ones);
15068 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15072 RHS = Op0.getOperand(1);
15074 } else if (Op1.getOpcode() == ISD::Constant) {
15075 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15076 uint64_t AndRHSVal = AndRHS->getZExtValue();
15077 SDValue AndLHS = Op0;
15079 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15080 LHS = AndLHS.getOperand(0);
15081 RHS = AndLHS.getOperand(1);
15084 // Use BT if the immediate can't be encoded in a TEST instruction.
15085 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15087 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15091 if (LHS.getNode()) {
15092 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15093 // instruction. Since the shift amount is in-range-or-undefined, we know
15094 // that doing a bittest on the i32 value is ok. We extend to i32 because
15095 // the encoding for the i16 version is larger than the i32 version.
15096 // Also promote i16 to i32 for performance / code size reason.
15097 if (LHS.getValueType() == MVT::i8 ||
15098 LHS.getValueType() == MVT::i16)
15099 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15101 // If the operand types disagree, extend the shift amount to match. Since
15102 // BT ignores high bits (like shifts) we can use anyextend.
15103 if (LHS.getValueType() != RHS.getValueType())
15104 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15106 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15107 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15108 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15109 DAG.getConstant(Cond, MVT::i8), BT);
15115 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15117 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15122 // SSE Condition code mapping:
15131 switch (SetCCOpcode) {
15132 default: llvm_unreachable("Unexpected SETCC condition");
15134 case ISD::SETEQ: SSECC = 0; break;
15136 case ISD::SETGT: Swap = true; // Fallthrough
15138 case ISD::SETOLT: SSECC = 1; break;
15140 case ISD::SETGE: Swap = true; // Fallthrough
15142 case ISD::SETOLE: SSECC = 2; break;
15143 case ISD::SETUO: SSECC = 3; break;
15145 case ISD::SETNE: SSECC = 4; break;
15146 case ISD::SETULE: Swap = true; // Fallthrough
15147 case ISD::SETUGE: SSECC = 5; break;
15148 case ISD::SETULT: Swap = true; // Fallthrough
15149 case ISD::SETUGT: SSECC = 6; break;
15150 case ISD::SETO: SSECC = 7; break;
15152 case ISD::SETONE: SSECC = 8; break;
15155 std::swap(Op0, Op1);
15160 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15161 // ones, and then concatenate the result back.
15162 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15163 MVT VT = Op.getSimpleValueType();
15165 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15166 "Unsupported value type for operation");
15168 unsigned NumElems = VT.getVectorNumElements();
15170 SDValue CC = Op.getOperand(2);
15172 // Extract the LHS vectors
15173 SDValue LHS = Op.getOperand(0);
15174 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15175 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15177 // Extract the RHS vectors
15178 SDValue RHS = Op.getOperand(1);
15179 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15180 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15182 // Issue the operation on the smaller types and concatenate the result back
15183 MVT EltVT = VT.getVectorElementType();
15184 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15185 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15186 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15187 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15190 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15191 const X86Subtarget *Subtarget) {
15192 SDValue Op0 = Op.getOperand(0);
15193 SDValue Op1 = Op.getOperand(1);
15194 SDValue CC = Op.getOperand(2);
15195 MVT VT = Op.getSimpleValueType();
15198 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15199 Op.getValueType().getScalarType() == MVT::i1 &&
15200 "Cannot set masked compare for this operation");
15202 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15204 bool Unsigned = false;
15207 switch (SetCCOpcode) {
15208 default: llvm_unreachable("Unexpected SETCC condition");
15209 case ISD::SETNE: SSECC = 4; break;
15210 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15211 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15212 case ISD::SETLT: Swap = true; //fall-through
15213 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15214 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15215 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15216 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15217 case ISD::SETULE: Unsigned = true; //fall-through
15218 case ISD::SETLE: SSECC = 2; break;
15222 std::swap(Op0, Op1);
15224 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15225 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15226 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15227 DAG.getConstant(SSECC, MVT::i8));
15230 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15231 /// operand \p Op1. If non-trivial (for example because it's not constant)
15232 /// return an empty value.
15233 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15235 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15239 MVT VT = Op1.getSimpleValueType();
15240 MVT EVT = VT.getVectorElementType();
15241 unsigned n = VT.getVectorNumElements();
15242 SmallVector<SDValue, 8> ULTOp1;
15244 for (unsigned i = 0; i < n; ++i) {
15245 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15246 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15249 // Avoid underflow.
15250 APInt Val = Elt->getAPIntValue();
15254 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15257 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15260 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15261 SelectionDAG &DAG) {
15262 SDValue Op0 = Op.getOperand(0);
15263 SDValue Op1 = Op.getOperand(1);
15264 SDValue CC = Op.getOperand(2);
15265 MVT VT = Op.getSimpleValueType();
15266 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15267 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15272 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15273 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15276 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15277 unsigned Opc = X86ISD::CMPP;
15278 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15279 assert(VT.getVectorNumElements() <= 16);
15280 Opc = X86ISD::CMPM;
15282 // In the two special cases we can't handle, emit two comparisons.
15285 unsigned CombineOpc;
15286 if (SetCCOpcode == ISD::SETUEQ) {
15287 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15289 assert(SetCCOpcode == ISD::SETONE);
15290 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15293 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15294 DAG.getConstant(CC0, MVT::i8));
15295 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15296 DAG.getConstant(CC1, MVT::i8));
15297 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15299 // Handle all other FP comparisons here.
15300 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15301 DAG.getConstant(SSECC, MVT::i8));
15304 // Break 256-bit integer vector compare into smaller ones.
15305 if (VT.is256BitVector() && !Subtarget->hasInt256())
15306 return Lower256IntVSETCC(Op, DAG);
15308 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15309 EVT OpVT = Op1.getValueType();
15310 if (Subtarget->hasAVX512()) {
15311 if (Op1.getValueType().is512BitVector() ||
15312 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15313 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15314 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15316 // In AVX-512 architecture setcc returns mask with i1 elements,
15317 // But there is no compare instruction for i8 and i16 elements in KNL.
15318 // We are not talking about 512-bit operands in this case, these
15319 // types are illegal.
15321 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15322 OpVT.getVectorElementType().getSizeInBits() >= 8))
15323 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15324 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15327 // We are handling one of the integer comparisons here. Since SSE only has
15328 // GT and EQ comparisons for integer, swapping operands and multiple
15329 // operations may be required for some comparisons.
15331 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15332 bool Subus = false;
15334 switch (SetCCOpcode) {
15335 default: llvm_unreachable("Unexpected SETCC condition");
15336 case ISD::SETNE: Invert = true;
15337 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15338 case ISD::SETLT: Swap = true;
15339 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15340 case ISD::SETGE: Swap = true;
15341 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15342 Invert = true; break;
15343 case ISD::SETULT: Swap = true;
15344 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15345 FlipSigns = true; break;
15346 case ISD::SETUGE: Swap = true;
15347 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15348 FlipSigns = true; Invert = true; break;
15351 // Special case: Use min/max operations for SETULE/SETUGE
15352 MVT VET = VT.getVectorElementType();
15354 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15355 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15358 switch (SetCCOpcode) {
15360 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15361 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15364 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15367 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15368 if (!MinMax && hasSubus) {
15369 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15371 // t = psubus Op0, Op1
15372 // pcmpeq t, <0..0>
15373 switch (SetCCOpcode) {
15375 case ISD::SETULT: {
15376 // If the comparison is against a constant we can turn this into a
15377 // setule. With psubus, setule does not require a swap. This is
15378 // beneficial because the constant in the register is no longer
15379 // destructed as the destination so it can be hoisted out of a loop.
15380 // Only do this pre-AVX since vpcmp* is no longer destructive.
15381 if (Subtarget->hasAVX())
15383 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15384 if (ULEOp1.getNode()) {
15386 Subus = true; Invert = false; Swap = false;
15390 // Psubus is better than flip-sign because it requires no inversion.
15391 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15392 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15396 Opc = X86ISD::SUBUS;
15402 std::swap(Op0, Op1);
15404 // Check that the operation in question is available (most are plain SSE2,
15405 // but PCMPGTQ and PCMPEQQ have different requirements).
15406 if (VT == MVT::v2i64) {
15407 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15408 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15410 // First cast everything to the right type.
15411 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15412 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15414 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15415 // bits of the inputs before performing those operations. The lower
15416 // compare is always unsigned.
15419 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15421 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15422 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15423 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15424 Sign, Zero, Sign, Zero);
15426 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15427 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15429 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15430 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15431 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15433 // Create masks for only the low parts/high parts of the 64 bit integers.
15434 static const int MaskHi[] = { 1, 1, 3, 3 };
15435 static const int MaskLo[] = { 0, 0, 2, 2 };
15436 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15437 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15438 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15440 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15441 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15444 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15446 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15449 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15450 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15451 // pcmpeqd + pshufd + pand.
15452 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15454 // First cast everything to the right type.
15455 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15456 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15459 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15461 // Make sure the lower and upper halves are both all-ones.
15462 static const int Mask[] = { 1, 0, 3, 2 };
15463 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15464 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15467 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15469 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15473 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15474 // bits of the inputs before performing those operations.
15476 EVT EltVT = VT.getVectorElementType();
15477 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15478 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15479 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15482 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15484 // If the logical-not of the result is required, perform that now.
15486 Result = DAG.getNOT(dl, Result, VT);
15489 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15492 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15493 getZeroVector(VT, Subtarget, DAG, dl));
15498 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15500 MVT VT = Op.getSimpleValueType();
15502 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15504 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15505 && "SetCC type must be 8-bit or 1-bit integer");
15506 SDValue Op0 = Op.getOperand(0);
15507 SDValue Op1 = Op.getOperand(1);
15509 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15511 // Optimize to BT if possible.
15512 // Lower (X & (1 << N)) == 0 to BT(X, N).
15513 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15514 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15515 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15516 Op1.getOpcode() == ISD::Constant &&
15517 cast<ConstantSDNode>(Op1)->isNullValue() &&
15518 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15519 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15520 if (NewSetCC.getNode()) {
15522 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15527 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15529 if (Op1.getOpcode() == ISD::Constant &&
15530 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15531 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15532 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15534 // If the input is a setcc, then reuse the input setcc or use a new one with
15535 // the inverted condition.
15536 if (Op0.getOpcode() == X86ISD::SETCC) {
15537 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15538 bool Invert = (CC == ISD::SETNE) ^
15539 cast<ConstantSDNode>(Op1)->isNullValue();
15543 CCode = X86::GetOppositeBranchCondition(CCode);
15544 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15545 DAG.getConstant(CCode, MVT::i8),
15546 Op0.getOperand(1));
15548 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15552 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15553 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15554 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15556 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15557 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15560 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15561 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15562 if (X86CC == X86::COND_INVALID)
15565 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15566 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15567 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15568 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15570 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15574 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15575 static bool isX86LogicalCmp(SDValue Op) {
15576 unsigned Opc = Op.getNode()->getOpcode();
15577 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15578 Opc == X86ISD::SAHF)
15580 if (Op.getResNo() == 1 &&
15581 (Opc == X86ISD::ADD ||
15582 Opc == X86ISD::SUB ||
15583 Opc == X86ISD::ADC ||
15584 Opc == X86ISD::SBB ||
15585 Opc == X86ISD::SMUL ||
15586 Opc == X86ISD::UMUL ||
15587 Opc == X86ISD::INC ||
15588 Opc == X86ISD::DEC ||
15589 Opc == X86ISD::OR ||
15590 Opc == X86ISD::XOR ||
15591 Opc == X86ISD::AND))
15594 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15600 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15601 if (V.getOpcode() != ISD::TRUNCATE)
15604 SDValue VOp0 = V.getOperand(0);
15605 unsigned InBits = VOp0.getValueSizeInBits();
15606 unsigned Bits = V.getValueSizeInBits();
15607 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15610 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15611 bool addTest = true;
15612 SDValue Cond = Op.getOperand(0);
15613 SDValue Op1 = Op.getOperand(1);
15614 SDValue Op2 = Op.getOperand(2);
15616 EVT VT = Op1.getValueType();
15619 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15620 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15621 // sequence later on.
15622 if (Cond.getOpcode() == ISD::SETCC &&
15623 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15624 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15625 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15626 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15627 int SSECC = translateX86FSETCC(
15628 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15631 if (Subtarget->hasAVX512()) {
15632 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15633 DAG.getConstant(SSECC, MVT::i8));
15634 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15636 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15637 DAG.getConstant(SSECC, MVT::i8));
15638 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15639 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15640 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15644 if (Cond.getOpcode() == ISD::SETCC) {
15645 SDValue NewCond = LowerSETCC(Cond, DAG);
15646 if (NewCond.getNode())
15650 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15651 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15652 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15653 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15654 if (Cond.getOpcode() == X86ISD::SETCC &&
15655 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15656 isZero(Cond.getOperand(1).getOperand(1))) {
15657 SDValue Cmp = Cond.getOperand(1);
15659 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15661 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15662 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15663 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15665 SDValue CmpOp0 = Cmp.getOperand(0);
15666 // Apply further optimizations for special cases
15667 // (select (x != 0), -1, 0) -> neg & sbb
15668 // (select (x == 0), 0, -1) -> neg & sbb
15669 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15670 if (YC->isNullValue() &&
15671 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15672 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15673 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15674 DAG.getConstant(0, CmpOp0.getValueType()),
15676 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15677 DAG.getConstant(X86::COND_B, MVT::i8),
15678 SDValue(Neg.getNode(), 1));
15682 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15683 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15684 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15686 SDValue Res = // Res = 0 or -1.
15687 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15688 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15690 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15691 Res = DAG.getNOT(DL, Res, Res.getValueType());
15693 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15694 if (!N2C || !N2C->isNullValue())
15695 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15700 // Look past (and (setcc_carry (cmp ...)), 1).
15701 if (Cond.getOpcode() == ISD::AND &&
15702 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15703 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15704 if (C && C->getAPIntValue() == 1)
15705 Cond = Cond.getOperand(0);
15708 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15709 // setting operand in place of the X86ISD::SETCC.
15710 unsigned CondOpcode = Cond.getOpcode();
15711 if (CondOpcode == X86ISD::SETCC ||
15712 CondOpcode == X86ISD::SETCC_CARRY) {
15713 CC = Cond.getOperand(0);
15715 SDValue Cmp = Cond.getOperand(1);
15716 unsigned Opc = Cmp.getOpcode();
15717 MVT VT = Op.getSimpleValueType();
15719 bool IllegalFPCMov = false;
15720 if (VT.isFloatingPoint() && !VT.isVector() &&
15721 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15722 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15724 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15725 Opc == X86ISD::BT) { // FIXME
15729 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15730 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15731 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15732 Cond.getOperand(0).getValueType() != MVT::i8)) {
15733 SDValue LHS = Cond.getOperand(0);
15734 SDValue RHS = Cond.getOperand(1);
15735 unsigned X86Opcode;
15738 switch (CondOpcode) {
15739 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15740 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15741 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15742 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15743 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15744 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15745 default: llvm_unreachable("unexpected overflowing operator");
15747 if (CondOpcode == ISD::UMULO)
15748 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15751 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15753 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15755 if (CondOpcode == ISD::UMULO)
15756 Cond = X86Op.getValue(2);
15758 Cond = X86Op.getValue(1);
15760 CC = DAG.getConstant(X86Cond, MVT::i8);
15765 // Look pass the truncate if the high bits are known zero.
15766 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15767 Cond = Cond.getOperand(0);
15769 // We know the result of AND is compared against zero. Try to match
15771 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15772 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15773 if (NewSetCC.getNode()) {
15774 CC = NewSetCC.getOperand(0);
15775 Cond = NewSetCC.getOperand(1);
15782 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15783 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15786 // a < b ? -1 : 0 -> RES = ~setcc_carry
15787 // a < b ? 0 : -1 -> RES = setcc_carry
15788 // a >= b ? -1 : 0 -> RES = setcc_carry
15789 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15790 if (Cond.getOpcode() == X86ISD::SUB) {
15791 Cond = ConvertCmpIfNecessary(Cond, DAG);
15792 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15794 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15795 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15796 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15797 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15798 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15799 return DAG.getNOT(DL, Res, Res.getValueType());
15804 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15805 // widen the cmov and push the truncate through. This avoids introducing a new
15806 // branch during isel and doesn't add any extensions.
15807 if (Op.getValueType() == MVT::i8 &&
15808 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15809 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15810 if (T1.getValueType() == T2.getValueType() &&
15811 // Blacklist CopyFromReg to avoid partial register stalls.
15812 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15813 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15814 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15815 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15819 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15820 // condition is true.
15821 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15822 SDValue Ops[] = { Op2, Op1, CC, Cond };
15823 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15826 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15827 SelectionDAG &DAG) {
15828 MVT VT = Op->getSimpleValueType(0);
15829 SDValue In = Op->getOperand(0);
15830 MVT InVT = In.getSimpleValueType();
15831 MVT VTElt = VT.getVectorElementType();
15832 MVT InVTElt = InVT.getVectorElementType();
15836 if ((InVTElt == MVT::i1) &&
15837 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15838 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15840 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15841 VTElt.getSizeInBits() <= 16)) ||
15843 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15844 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15846 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15847 VTElt.getSizeInBits() >= 32))))
15848 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15850 unsigned int NumElts = VT.getVectorNumElements();
15852 if (NumElts != 8 && NumElts != 16)
15855 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15856 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15857 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15858 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15861 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15862 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15864 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15865 Constant *C = ConstantInt::get(*DAG.getContext(),
15866 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15868 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15869 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15870 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15871 MachinePointerInfo::getConstantPool(),
15872 false, false, false, Alignment);
15873 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15874 if (VT.is512BitVector())
15876 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15879 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15880 SelectionDAG &DAG) {
15881 MVT VT = Op->getSimpleValueType(0);
15882 SDValue In = Op->getOperand(0);
15883 MVT InVT = In.getSimpleValueType();
15886 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15887 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15889 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15890 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15891 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15894 if (Subtarget->hasInt256())
15895 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15897 // Optimize vectors in AVX mode
15898 // Sign extend v8i16 to v8i32 and
15901 // Divide input vector into two parts
15902 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15903 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15904 // concat the vectors to original VT
15906 unsigned NumElems = InVT.getVectorNumElements();
15907 SDValue Undef = DAG.getUNDEF(InVT);
15909 SmallVector<int,8> ShufMask1(NumElems, -1);
15910 for (unsigned i = 0; i != NumElems/2; ++i)
15913 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15915 SmallVector<int,8> ShufMask2(NumElems, -1);
15916 for (unsigned i = 0; i != NumElems/2; ++i)
15917 ShufMask2[i] = i + NumElems/2;
15919 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15921 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15922 VT.getVectorNumElements()/2);
15924 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15925 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15927 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15930 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15931 // may emit an illegal shuffle but the expansion is still better than scalar
15932 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15933 // we'll emit a shuffle and a arithmetic shift.
15934 // TODO: It is possible to support ZExt by zeroing the undef values during
15935 // the shuffle phase or after the shuffle.
15936 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15937 SelectionDAG &DAG) {
15938 MVT RegVT = Op.getSimpleValueType();
15939 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15940 assert(RegVT.isInteger() &&
15941 "We only custom lower integer vector sext loads.");
15943 // Nothing useful we can do without SSE2 shuffles.
15944 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15946 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15948 EVT MemVT = Ld->getMemoryVT();
15949 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15950 unsigned RegSz = RegVT.getSizeInBits();
15952 ISD::LoadExtType Ext = Ld->getExtensionType();
15954 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15955 && "Only anyext and sext are currently implemented.");
15956 assert(MemVT != RegVT && "Cannot extend to the same type");
15957 assert(MemVT.isVector() && "Must load a vector from memory");
15959 unsigned NumElems = RegVT.getVectorNumElements();
15960 unsigned MemSz = MemVT.getSizeInBits();
15961 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15963 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15964 // The only way in which we have a legal 256-bit vector result but not the
15965 // integer 256-bit operations needed to directly lower a sextload is if we
15966 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15967 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15968 // correctly legalized. We do this late to allow the canonical form of
15969 // sextload to persist throughout the rest of the DAG combiner -- it wants
15970 // to fold together any extensions it can, and so will fuse a sign_extend
15971 // of an sextload into a sextload targeting a wider value.
15973 if (MemSz == 128) {
15974 // Just switch this to a normal load.
15975 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15976 "it must be a legal 128-bit vector "
15978 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15979 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15980 Ld->isInvariant(), Ld->getAlignment());
15982 assert(MemSz < 128 &&
15983 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15984 // Do an sext load to a 128-bit vector type. We want to use the same
15985 // number of elements, but elements half as wide. This will end up being
15986 // recursively lowered by this routine, but will succeed as we definitely
15987 // have all the necessary features if we're using AVX1.
15989 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15990 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15992 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15993 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15994 Ld->isNonTemporal(), Ld->isInvariant(),
15995 Ld->getAlignment());
15998 // Replace chain users with the new chain.
15999 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
16000 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
16002 // Finally, do a normal sign-extend to the desired register.
16003 return DAG.getSExtOrTrunc(Load, dl, RegVT);
16006 // All sizes must be a power of two.
16007 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
16008 "Non-power-of-two elements are not custom lowered!");
16010 // Attempt to load the original value using scalar loads.
16011 // Find the largest scalar type that divides the total loaded size.
16012 MVT SclrLoadTy = MVT::i8;
16013 for (MVT Tp : MVT::integer_valuetypes()) {
16014 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16019 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16020 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16022 SclrLoadTy = MVT::f64;
16024 // Calculate the number of scalar loads that we need to perform
16025 // in order to load our vector from memory.
16026 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16028 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16029 "Can only lower sext loads with a single scalar load!");
16031 unsigned loadRegZize = RegSz;
16032 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16035 // Represent our vector as a sequence of elements which are the
16036 // largest scalar that we can load.
16037 EVT LoadUnitVecVT = EVT::getVectorVT(
16038 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16040 // Represent the data using the same element type that is stored in
16041 // memory. In practice, we ''widen'' MemVT.
16043 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16044 loadRegZize / MemVT.getScalarType().getSizeInBits());
16046 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16047 "Invalid vector type");
16049 // We can't shuffle using an illegal type.
16050 assert(TLI.isTypeLegal(WideVecVT) &&
16051 "We only lower types that form legal widened vector types");
16053 SmallVector<SDValue, 8> Chains;
16054 SDValue Ptr = Ld->getBasePtr();
16055 SDValue Increment =
16056 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16057 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16059 for (unsigned i = 0; i < NumLoads; ++i) {
16060 // Perform a single load.
16061 SDValue ScalarLoad =
16062 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16063 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16064 Ld->getAlignment());
16065 Chains.push_back(ScalarLoad.getValue(1));
16066 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16067 // another round of DAGCombining.
16069 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16071 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16072 ScalarLoad, DAG.getIntPtrConstant(i));
16074 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16077 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16079 // Bitcast the loaded value to a vector of the original element type, in
16080 // the size of the target vector type.
16081 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16082 unsigned SizeRatio = RegSz / MemSz;
16084 if (Ext == ISD::SEXTLOAD) {
16085 // If we have SSE4.1, we can directly emit a VSEXT node.
16086 if (Subtarget->hasSSE41()) {
16087 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16088 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16092 // Otherwise we'll shuffle the small elements in the high bits of the
16093 // larger type and perform an arithmetic shift. If the shift is not legal
16094 // it's better to scalarize.
16095 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16096 "We can't implement a sext load without an arithmetic right shift!");
16098 // Redistribute the loaded elements into the different locations.
16099 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16100 for (unsigned i = 0; i != NumElems; ++i)
16101 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16103 SDValue Shuff = DAG.getVectorShuffle(
16104 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16106 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16108 // Build the arithmetic shift.
16109 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16110 MemVT.getVectorElementType().getSizeInBits();
16112 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16114 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16118 // Redistribute the loaded elements into the different locations.
16119 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16120 for (unsigned i = 0; i != NumElems; ++i)
16121 ShuffleVec[i * SizeRatio] = i;
16123 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16124 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16126 // Bitcast to the requested type.
16127 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16128 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16132 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16133 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16134 // from the AND / OR.
16135 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16136 Opc = Op.getOpcode();
16137 if (Opc != ISD::OR && Opc != ISD::AND)
16139 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16140 Op.getOperand(0).hasOneUse() &&
16141 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16142 Op.getOperand(1).hasOneUse());
16145 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16146 // 1 and that the SETCC node has a single use.
16147 static bool isXor1OfSetCC(SDValue Op) {
16148 if (Op.getOpcode() != ISD::XOR)
16150 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16151 if (N1C && N1C->getAPIntValue() == 1) {
16152 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16153 Op.getOperand(0).hasOneUse();
16158 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16159 bool addTest = true;
16160 SDValue Chain = Op.getOperand(0);
16161 SDValue Cond = Op.getOperand(1);
16162 SDValue Dest = Op.getOperand(2);
16165 bool Inverted = false;
16167 if (Cond.getOpcode() == ISD::SETCC) {
16168 // Check for setcc([su]{add,sub,mul}o == 0).
16169 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16170 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16171 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16172 Cond.getOperand(0).getResNo() == 1 &&
16173 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16174 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16175 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16176 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16177 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16178 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16180 Cond = Cond.getOperand(0);
16182 SDValue NewCond = LowerSETCC(Cond, DAG);
16183 if (NewCond.getNode())
16188 // FIXME: LowerXALUO doesn't handle these!!
16189 else if (Cond.getOpcode() == X86ISD::ADD ||
16190 Cond.getOpcode() == X86ISD::SUB ||
16191 Cond.getOpcode() == X86ISD::SMUL ||
16192 Cond.getOpcode() == X86ISD::UMUL)
16193 Cond = LowerXALUO(Cond, DAG);
16196 // Look pass (and (setcc_carry (cmp ...)), 1).
16197 if (Cond.getOpcode() == ISD::AND &&
16198 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16199 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16200 if (C && C->getAPIntValue() == 1)
16201 Cond = Cond.getOperand(0);
16204 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16205 // setting operand in place of the X86ISD::SETCC.
16206 unsigned CondOpcode = Cond.getOpcode();
16207 if (CondOpcode == X86ISD::SETCC ||
16208 CondOpcode == X86ISD::SETCC_CARRY) {
16209 CC = Cond.getOperand(0);
16211 SDValue Cmp = Cond.getOperand(1);
16212 unsigned Opc = Cmp.getOpcode();
16213 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16214 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16218 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16222 // These can only come from an arithmetic instruction with overflow,
16223 // e.g. SADDO, UADDO.
16224 Cond = Cond.getNode()->getOperand(1);
16230 CondOpcode = Cond.getOpcode();
16231 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16232 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16233 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16234 Cond.getOperand(0).getValueType() != MVT::i8)) {
16235 SDValue LHS = Cond.getOperand(0);
16236 SDValue RHS = Cond.getOperand(1);
16237 unsigned X86Opcode;
16240 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16241 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16243 switch (CondOpcode) {
16244 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16246 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16248 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16251 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16252 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16256 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16259 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16260 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16261 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16262 default: llvm_unreachable("unexpected overflowing operator");
16265 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16266 if (CondOpcode == ISD::UMULO)
16267 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16270 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16272 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16274 if (CondOpcode == ISD::UMULO)
16275 Cond = X86Op.getValue(2);
16277 Cond = X86Op.getValue(1);
16279 CC = DAG.getConstant(X86Cond, MVT::i8);
16283 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16284 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16285 if (CondOpc == ISD::OR) {
16286 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16287 // two branches instead of an explicit OR instruction with a
16289 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16290 isX86LogicalCmp(Cmp)) {
16291 CC = Cond.getOperand(0).getOperand(0);
16292 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16293 Chain, Dest, CC, Cmp);
16294 CC = Cond.getOperand(1).getOperand(0);
16298 } else { // ISD::AND
16299 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16300 // two branches instead of an explicit AND instruction with a
16301 // separate test. However, we only do this if this block doesn't
16302 // have a fall-through edge, because this requires an explicit
16303 // jmp when the condition is false.
16304 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16305 isX86LogicalCmp(Cmp) &&
16306 Op.getNode()->hasOneUse()) {
16307 X86::CondCode CCode =
16308 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16309 CCode = X86::GetOppositeBranchCondition(CCode);
16310 CC = DAG.getConstant(CCode, MVT::i8);
16311 SDNode *User = *Op.getNode()->use_begin();
16312 // Look for an unconditional branch following this conditional branch.
16313 // We need this because we need to reverse the successors in order
16314 // to implement FCMP_OEQ.
16315 if (User->getOpcode() == ISD::BR) {
16316 SDValue FalseBB = User->getOperand(1);
16318 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16319 assert(NewBR == User);
16323 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16324 Chain, Dest, CC, Cmp);
16325 X86::CondCode CCode =
16326 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16327 CCode = X86::GetOppositeBranchCondition(CCode);
16328 CC = DAG.getConstant(CCode, MVT::i8);
16334 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16335 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16336 // It should be transformed during dag combiner except when the condition
16337 // is set by a arithmetics with overflow node.
16338 X86::CondCode CCode =
16339 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16340 CCode = X86::GetOppositeBranchCondition(CCode);
16341 CC = DAG.getConstant(CCode, MVT::i8);
16342 Cond = Cond.getOperand(0).getOperand(1);
16344 } else if (Cond.getOpcode() == ISD::SETCC &&
16345 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16346 // For FCMP_OEQ, we can emit
16347 // two branches instead of an explicit AND instruction with a
16348 // separate test. However, we only do this if this block doesn't
16349 // have a fall-through edge, because this requires an explicit
16350 // jmp when the condition is false.
16351 if (Op.getNode()->hasOneUse()) {
16352 SDNode *User = *Op.getNode()->use_begin();
16353 // Look for an unconditional branch following this conditional branch.
16354 // We need this because we need to reverse the successors in order
16355 // to implement FCMP_OEQ.
16356 if (User->getOpcode() == ISD::BR) {
16357 SDValue FalseBB = User->getOperand(1);
16359 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16360 assert(NewBR == User);
16364 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16365 Cond.getOperand(0), Cond.getOperand(1));
16366 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16367 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16368 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16369 Chain, Dest, CC, Cmp);
16370 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16375 } else if (Cond.getOpcode() == ISD::SETCC &&
16376 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16377 // For FCMP_UNE, we can emit
16378 // two branches instead of an explicit AND instruction with a
16379 // separate test. However, we only do this if this block doesn't
16380 // have a fall-through edge, because this requires an explicit
16381 // jmp when the condition is false.
16382 if (Op.getNode()->hasOneUse()) {
16383 SDNode *User = *Op.getNode()->use_begin();
16384 // Look for an unconditional branch following this conditional branch.
16385 // We need this because we need to reverse the successors in order
16386 // to implement FCMP_UNE.
16387 if (User->getOpcode() == ISD::BR) {
16388 SDValue FalseBB = User->getOperand(1);
16390 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16391 assert(NewBR == User);
16394 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16395 Cond.getOperand(0), Cond.getOperand(1));
16396 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16397 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16398 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16399 Chain, Dest, CC, Cmp);
16400 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16410 // Look pass the truncate if the high bits are known zero.
16411 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16412 Cond = Cond.getOperand(0);
16414 // We know the result of AND is compared against zero. Try to match
16416 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16417 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16418 if (NewSetCC.getNode()) {
16419 CC = NewSetCC.getOperand(0);
16420 Cond = NewSetCC.getOperand(1);
16427 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16428 CC = DAG.getConstant(X86Cond, MVT::i8);
16429 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16431 Cond = ConvertCmpIfNecessary(Cond, DAG);
16432 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16433 Chain, Dest, CC, Cond);
16436 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16437 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16438 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16439 // that the guard pages used by the OS virtual memory manager are allocated in
16440 // correct sequence.
16442 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16443 SelectionDAG &DAG) const {
16444 MachineFunction &MF = DAG.getMachineFunction();
16445 bool SplitStack = MF.shouldSplitStack();
16446 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16452 SDNode* Node = Op.getNode();
16454 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16455 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16456 " not tell us which reg is the stack pointer!");
16457 EVT VT = Node->getValueType(0);
16458 SDValue Tmp1 = SDValue(Node, 0);
16459 SDValue Tmp2 = SDValue(Node, 1);
16460 SDValue Tmp3 = Node->getOperand(2);
16461 SDValue Chain = Tmp1.getOperand(0);
16463 // Chain the dynamic stack allocation so that it doesn't modify the stack
16464 // pointer when other instructions are using the stack.
16465 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16468 SDValue Size = Tmp2.getOperand(1);
16469 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16470 Chain = SP.getValue(1);
16471 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16472 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16473 unsigned StackAlign = TFI.getStackAlignment();
16474 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16475 if (Align > StackAlign)
16476 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16477 DAG.getConstant(-(uint64_t)Align, VT));
16478 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16480 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16481 DAG.getIntPtrConstant(0, true), SDValue(),
16484 SDValue Ops[2] = { Tmp1, Tmp2 };
16485 return DAG.getMergeValues(Ops, dl);
16489 SDValue Chain = Op.getOperand(0);
16490 SDValue Size = Op.getOperand(1);
16491 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16492 EVT VT = Op.getNode()->getValueType(0);
16494 bool Is64Bit = Subtarget->is64Bit();
16495 EVT SPTy = getPointerTy();
16498 MachineRegisterInfo &MRI = MF.getRegInfo();
16501 // The 64 bit implementation of segmented stacks needs to clobber both r10
16502 // r11. This makes it impossible to use it along with nested parameters.
16503 const Function *F = MF.getFunction();
16505 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16507 if (I->hasNestAttr())
16508 report_fatal_error("Cannot use segmented stacks with functions that "
16509 "have nested arguments.");
16512 const TargetRegisterClass *AddrRegClass =
16513 getRegClassFor(getPointerTy());
16514 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16515 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16516 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16517 DAG.getRegister(Vreg, SPTy));
16518 SDValue Ops1[2] = { Value, Chain };
16519 return DAG.getMergeValues(Ops1, dl);
16522 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16524 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16525 Flag = Chain.getValue(1);
16526 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16528 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16530 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16531 DAG.getSubtarget().getRegisterInfo());
16532 unsigned SPReg = RegInfo->getStackRegister();
16533 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16534 Chain = SP.getValue(1);
16537 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16538 DAG.getConstant(-(uint64_t)Align, VT));
16539 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16542 SDValue Ops1[2] = { SP, Chain };
16543 return DAG.getMergeValues(Ops1, dl);
16547 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16548 MachineFunction &MF = DAG.getMachineFunction();
16549 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16551 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16554 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16555 // vastart just stores the address of the VarArgsFrameIndex slot into the
16556 // memory location argument.
16557 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16559 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16560 MachinePointerInfo(SV), false, false, 0);
16564 // gp_offset (0 - 6 * 8)
16565 // fp_offset (48 - 48 + 8 * 16)
16566 // overflow_arg_area (point to parameters coming in memory).
16568 SmallVector<SDValue, 8> MemOps;
16569 SDValue FIN = Op.getOperand(1);
16571 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16572 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16574 FIN, MachinePointerInfo(SV), false, false, 0);
16575 MemOps.push_back(Store);
16578 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16579 FIN, DAG.getIntPtrConstant(4));
16580 Store = DAG.getStore(Op.getOperand(0), DL,
16581 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16583 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16584 MemOps.push_back(Store);
16586 // Store ptr to overflow_arg_area
16587 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16588 FIN, DAG.getIntPtrConstant(4));
16589 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16591 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16592 MachinePointerInfo(SV, 8),
16594 MemOps.push_back(Store);
16596 // Store ptr to reg_save_area.
16597 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16598 FIN, DAG.getIntPtrConstant(8));
16599 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16601 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16602 MachinePointerInfo(SV, 16), false, false, 0);
16603 MemOps.push_back(Store);
16604 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16607 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16608 assert(Subtarget->is64Bit() &&
16609 "LowerVAARG only handles 64-bit va_arg!");
16610 assert((Subtarget->isTargetLinux() ||
16611 Subtarget->isTargetDarwin()) &&
16612 "Unhandled target in LowerVAARG");
16613 assert(Op.getNode()->getNumOperands() == 4);
16614 SDValue Chain = Op.getOperand(0);
16615 SDValue SrcPtr = Op.getOperand(1);
16616 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16617 unsigned Align = Op.getConstantOperandVal(3);
16620 EVT ArgVT = Op.getNode()->getValueType(0);
16621 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16622 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16625 // Decide which area this value should be read from.
16626 // TODO: Implement the AMD64 ABI in its entirety. This simple
16627 // selection mechanism works only for the basic types.
16628 if (ArgVT == MVT::f80) {
16629 llvm_unreachable("va_arg for f80 not yet implemented");
16630 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16631 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16632 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16633 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16635 llvm_unreachable("Unhandled argument type in LowerVAARG");
16638 if (ArgMode == 2) {
16639 // Sanity Check: Make sure using fp_offset makes sense.
16640 assert(!DAG.getTarget().Options.UseSoftFloat &&
16641 !(DAG.getMachineFunction()
16642 .getFunction()->getAttributes()
16643 .hasAttribute(AttributeSet::FunctionIndex,
16644 Attribute::NoImplicitFloat)) &&
16645 Subtarget->hasSSE1());
16648 // Insert VAARG_64 node into the DAG
16649 // VAARG_64 returns two values: Variable Argument Address, Chain
16650 SmallVector<SDValue, 11> InstOps;
16651 InstOps.push_back(Chain);
16652 InstOps.push_back(SrcPtr);
16653 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16654 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16655 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16656 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16657 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16658 VTs, InstOps, MVT::i64,
16659 MachinePointerInfo(SV),
16661 /*Volatile=*/false,
16663 /*WriteMem=*/true);
16664 Chain = VAARG.getValue(1);
16666 // Load the next argument and return it
16667 return DAG.getLoad(ArgVT, dl,
16670 MachinePointerInfo(),
16671 false, false, false, 0);
16674 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16675 SelectionDAG &DAG) {
16676 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16677 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16678 SDValue Chain = Op.getOperand(0);
16679 SDValue DstPtr = Op.getOperand(1);
16680 SDValue SrcPtr = Op.getOperand(2);
16681 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16682 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16685 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16686 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16688 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16691 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16692 // amount is a constant. Takes immediate version of shift as input.
16693 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16694 SDValue SrcOp, uint64_t ShiftAmt,
16695 SelectionDAG &DAG) {
16696 MVT ElementType = VT.getVectorElementType();
16698 // Fold this packed shift into its first operand if ShiftAmt is 0.
16702 // Check for ShiftAmt >= element width
16703 if (ShiftAmt >= ElementType.getSizeInBits()) {
16704 if (Opc == X86ISD::VSRAI)
16705 ShiftAmt = ElementType.getSizeInBits() - 1;
16707 return DAG.getConstant(0, VT);
16710 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16711 && "Unknown target vector shift-by-constant node");
16713 // Fold this packed vector shift into a build vector if SrcOp is a
16714 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16715 if (VT == SrcOp.getSimpleValueType() &&
16716 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16717 SmallVector<SDValue, 8> Elts;
16718 unsigned NumElts = SrcOp->getNumOperands();
16719 ConstantSDNode *ND;
16722 default: llvm_unreachable(nullptr);
16723 case X86ISD::VSHLI:
16724 for (unsigned i=0; i!=NumElts; ++i) {
16725 SDValue CurrentOp = SrcOp->getOperand(i);
16726 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16727 Elts.push_back(CurrentOp);
16730 ND = cast<ConstantSDNode>(CurrentOp);
16731 const APInt &C = ND->getAPIntValue();
16732 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16735 case X86ISD::VSRLI:
16736 for (unsigned i=0; i!=NumElts; ++i) {
16737 SDValue CurrentOp = SrcOp->getOperand(i);
16738 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16739 Elts.push_back(CurrentOp);
16742 ND = cast<ConstantSDNode>(CurrentOp);
16743 const APInt &C = ND->getAPIntValue();
16744 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16747 case X86ISD::VSRAI:
16748 for (unsigned i=0; i!=NumElts; ++i) {
16749 SDValue CurrentOp = SrcOp->getOperand(i);
16750 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16751 Elts.push_back(CurrentOp);
16754 ND = cast<ConstantSDNode>(CurrentOp);
16755 const APInt &C = ND->getAPIntValue();
16756 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16761 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16764 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16767 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16768 // may or may not be a constant. Takes immediate version of shift as input.
16769 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16770 SDValue SrcOp, SDValue ShAmt,
16771 SelectionDAG &DAG) {
16772 MVT SVT = ShAmt.getSimpleValueType();
16773 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16775 // Catch shift-by-constant.
16776 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16777 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16778 CShAmt->getZExtValue(), DAG);
16780 // Change opcode to non-immediate version
16782 default: llvm_unreachable("Unknown target vector shift node");
16783 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16784 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16785 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16788 const X86Subtarget &Subtarget =
16789 DAG.getTarget().getSubtarget<X86Subtarget>();
16790 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16791 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16792 // Let the shuffle legalizer expand this shift amount node.
16793 SDValue Op0 = ShAmt.getOperand(0);
16794 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16795 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16797 // Need to build a vector containing shift amount.
16798 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16799 SmallVector<SDValue, 4> ShOps;
16800 ShOps.push_back(ShAmt);
16801 if (SVT == MVT::i32) {
16802 ShOps.push_back(DAG.getConstant(0, SVT));
16803 ShOps.push_back(DAG.getUNDEF(SVT));
16805 ShOps.push_back(DAG.getUNDEF(SVT));
16807 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16808 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16811 // The return type has to be a 128-bit type with the same element
16812 // type as the input type.
16813 MVT EltVT = VT.getVectorElementType();
16814 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16816 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16817 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16820 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16821 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16822 /// necessary casting for \p Mask when lowering masking intrinsics.
16823 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16824 SDValue PreservedSrc,
16825 const X86Subtarget *Subtarget,
16826 SelectionDAG &DAG) {
16827 EVT VT = Op.getValueType();
16828 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16829 MVT::i1, VT.getVectorNumElements());
16830 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16831 Mask.getValueType().getSizeInBits());
16834 assert(MaskVT.isSimple() && "invalid mask type");
16836 if (isAllOnes(Mask))
16839 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16840 // are extracted by EXTRACT_SUBVECTOR.
16841 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16842 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16843 DAG.getIntPtrConstant(0));
16845 switch (Op.getOpcode()) {
16847 case X86ISD::PCMPEQM:
16848 case X86ISD::PCMPGTM:
16850 case X86ISD::CMPMU:
16851 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16853 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16854 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16855 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16858 /// \brief Creates an SDNode for a predicated scalar operation.
16859 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16860 /// The mask is comming as MVT::i8 and it should be truncated
16861 /// to MVT::i1 while lowering masking intrinsics.
16862 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16863 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16864 /// a scalar instruction.
16865 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16866 SDValue PreservedSrc,
16867 const X86Subtarget *Subtarget,
16868 SelectionDAG &DAG) {
16869 if (isAllOnes(Mask))
16872 EVT VT = Op.getValueType();
16874 // The mask should be of type MVT::i1
16875 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16877 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16878 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16879 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16882 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16884 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16885 case Intrinsic::x86_fma_vfmadd_ps:
16886 case Intrinsic::x86_fma_vfmadd_pd:
16887 case Intrinsic::x86_fma_vfmadd_ps_256:
16888 case Intrinsic::x86_fma_vfmadd_pd_256:
16889 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16890 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16891 return X86ISD::FMADD;
16892 case Intrinsic::x86_fma_vfmsub_ps:
16893 case Intrinsic::x86_fma_vfmsub_pd:
16894 case Intrinsic::x86_fma_vfmsub_ps_256:
16895 case Intrinsic::x86_fma_vfmsub_pd_256:
16896 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16897 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16898 return X86ISD::FMSUB;
16899 case Intrinsic::x86_fma_vfnmadd_ps:
16900 case Intrinsic::x86_fma_vfnmadd_pd:
16901 case Intrinsic::x86_fma_vfnmadd_ps_256:
16902 case Intrinsic::x86_fma_vfnmadd_pd_256:
16903 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16904 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16905 return X86ISD::FNMADD;
16906 case Intrinsic::x86_fma_vfnmsub_ps:
16907 case Intrinsic::x86_fma_vfnmsub_pd:
16908 case Intrinsic::x86_fma_vfnmsub_ps_256:
16909 case Intrinsic::x86_fma_vfnmsub_pd_256:
16910 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16911 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16912 return X86ISD::FNMSUB;
16913 case Intrinsic::x86_fma_vfmaddsub_ps:
16914 case Intrinsic::x86_fma_vfmaddsub_pd:
16915 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16916 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16917 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16918 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16919 return X86ISD::FMADDSUB;
16920 case Intrinsic::x86_fma_vfmsubadd_ps:
16921 case Intrinsic::x86_fma_vfmsubadd_pd:
16922 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16923 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16924 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16925 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16926 return X86ISD::FMSUBADD;
16930 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16931 SelectionDAG &DAG) {
16933 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16934 EVT VT = Op.getValueType();
16935 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16937 switch(IntrData->Type) {
16938 case INTR_TYPE_1OP:
16939 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16940 case INTR_TYPE_2OP:
16941 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16943 case INTR_TYPE_3OP:
16944 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16945 Op.getOperand(2), Op.getOperand(3));
16946 case INTR_TYPE_1OP_MASK_RM: {
16947 SDValue Src = Op.getOperand(1);
16948 SDValue Src0 = Op.getOperand(2);
16949 SDValue Mask = Op.getOperand(3);
16950 SDValue RoundingMode = Op.getOperand(4);
16951 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16953 Mask, Src0, Subtarget, DAG);
16955 case INTR_TYPE_SCALAR_MASK_RM: {
16956 SDValue Src1 = Op.getOperand(1);
16957 SDValue Src2 = Op.getOperand(2);
16958 SDValue Src0 = Op.getOperand(3);
16959 SDValue Mask = Op.getOperand(4);
16960 SDValue RoundingMode = Op.getOperand(5);
16961 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16963 Mask, Src0, Subtarget, DAG);
16965 case INTR_TYPE_2OP_MASK: {
16966 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16968 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16971 case CMP_MASK_CC: {
16972 // Comparison intrinsics with masks.
16973 // Example of transformation:
16974 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16975 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16977 // (v8i1 (insert_subvector undef,
16978 // (v2i1 (and (PCMPEQM %a, %b),
16979 // (extract_subvector
16980 // (v8i1 (bitcast %mask)), 0))), 0))))
16981 EVT VT = Op.getOperand(1).getValueType();
16982 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16983 VT.getVectorNumElements());
16984 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16985 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16986 Mask.getValueType().getSizeInBits());
16988 if (IntrData->Type == CMP_MASK_CC) {
16989 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16990 Op.getOperand(2), Op.getOperand(3));
16992 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16993 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16996 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16997 DAG.getTargetConstant(0, MaskVT),
16999 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
17000 DAG.getUNDEF(BitcastVT), CmpMask,
17001 DAG.getIntPtrConstant(0));
17002 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
17004 case COMI: { // Comparison intrinsics
17005 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
17006 SDValue LHS = Op.getOperand(1);
17007 SDValue RHS = Op.getOperand(2);
17008 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
17009 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
17010 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
17011 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17012 DAG.getConstant(X86CC, MVT::i8), Cond);
17013 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17016 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
17017 Op.getOperand(1), Op.getOperand(2), DAG);
17019 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
17020 Op.getSimpleValueType(),
17022 Op.getOperand(2), DAG),
17023 Op.getOperand(4), Op.getOperand(3), Subtarget,
17025 case COMPRESS_EXPAND_IN_REG: {
17026 SDValue Mask = Op.getOperand(3);
17027 SDValue DataToCompress = Op.getOperand(1);
17028 SDValue PassThru = Op.getOperand(2);
17029 if (isAllOnes(Mask)) // return data as is
17030 return Op.getOperand(1);
17031 EVT VT = Op.getValueType();
17032 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17033 VT.getVectorNumElements());
17034 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17035 Mask.getValueType().getSizeInBits());
17037 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17038 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17039 DAG.getIntPtrConstant(0));
17041 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17045 SDValue Mask = Op.getOperand(3);
17046 EVT VT = Op.getValueType();
17047 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17048 VT.getVectorNumElements());
17049 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17050 Mask.getValueType().getSizeInBits());
17052 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17053 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17054 DAG.getIntPtrConstant(0));
17055 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17060 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
17061 dl, Op.getValueType(),
17065 Op.getOperand(4), Op.getOperand(1),
17074 default: return SDValue(); // Don't custom lower most intrinsics.
17076 case Intrinsic::x86_avx512_mask_valign_q_512:
17077 case Intrinsic::x86_avx512_mask_valign_d_512:
17078 // Vector source operands are swapped.
17079 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17080 Op.getValueType(), Op.getOperand(2),
17083 Op.getOperand(5), Op.getOperand(4),
17086 // ptest and testp intrinsics. The intrinsic these come from are designed to
17087 // return an integer value, not just an instruction so lower it to the ptest
17088 // or testp pattern and a setcc for the result.
17089 case Intrinsic::x86_sse41_ptestz:
17090 case Intrinsic::x86_sse41_ptestc:
17091 case Intrinsic::x86_sse41_ptestnzc:
17092 case Intrinsic::x86_avx_ptestz_256:
17093 case Intrinsic::x86_avx_ptestc_256:
17094 case Intrinsic::x86_avx_ptestnzc_256:
17095 case Intrinsic::x86_avx_vtestz_ps:
17096 case Intrinsic::x86_avx_vtestc_ps:
17097 case Intrinsic::x86_avx_vtestnzc_ps:
17098 case Intrinsic::x86_avx_vtestz_pd:
17099 case Intrinsic::x86_avx_vtestc_pd:
17100 case Intrinsic::x86_avx_vtestnzc_pd:
17101 case Intrinsic::x86_avx_vtestz_ps_256:
17102 case Intrinsic::x86_avx_vtestc_ps_256:
17103 case Intrinsic::x86_avx_vtestnzc_ps_256:
17104 case Intrinsic::x86_avx_vtestz_pd_256:
17105 case Intrinsic::x86_avx_vtestc_pd_256:
17106 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17107 bool IsTestPacked = false;
17110 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17111 case Intrinsic::x86_avx_vtestz_ps:
17112 case Intrinsic::x86_avx_vtestz_pd:
17113 case Intrinsic::x86_avx_vtestz_ps_256:
17114 case Intrinsic::x86_avx_vtestz_pd_256:
17115 IsTestPacked = true; // Fallthrough
17116 case Intrinsic::x86_sse41_ptestz:
17117 case Intrinsic::x86_avx_ptestz_256:
17119 X86CC = X86::COND_E;
17121 case Intrinsic::x86_avx_vtestc_ps:
17122 case Intrinsic::x86_avx_vtestc_pd:
17123 case Intrinsic::x86_avx_vtestc_ps_256:
17124 case Intrinsic::x86_avx_vtestc_pd_256:
17125 IsTestPacked = true; // Fallthrough
17126 case Intrinsic::x86_sse41_ptestc:
17127 case Intrinsic::x86_avx_ptestc_256:
17129 X86CC = X86::COND_B;
17131 case Intrinsic::x86_avx_vtestnzc_ps:
17132 case Intrinsic::x86_avx_vtestnzc_pd:
17133 case Intrinsic::x86_avx_vtestnzc_ps_256:
17134 case Intrinsic::x86_avx_vtestnzc_pd_256:
17135 IsTestPacked = true; // Fallthrough
17136 case Intrinsic::x86_sse41_ptestnzc:
17137 case Intrinsic::x86_avx_ptestnzc_256:
17139 X86CC = X86::COND_A;
17143 SDValue LHS = Op.getOperand(1);
17144 SDValue RHS = Op.getOperand(2);
17145 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17146 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17147 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17148 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17149 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17151 case Intrinsic::x86_avx512_kortestz_w:
17152 case Intrinsic::x86_avx512_kortestc_w: {
17153 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17154 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17155 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17156 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17157 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17158 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17159 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17162 case Intrinsic::x86_sse42_pcmpistria128:
17163 case Intrinsic::x86_sse42_pcmpestria128:
17164 case Intrinsic::x86_sse42_pcmpistric128:
17165 case Intrinsic::x86_sse42_pcmpestric128:
17166 case Intrinsic::x86_sse42_pcmpistrio128:
17167 case Intrinsic::x86_sse42_pcmpestrio128:
17168 case Intrinsic::x86_sse42_pcmpistris128:
17169 case Intrinsic::x86_sse42_pcmpestris128:
17170 case Intrinsic::x86_sse42_pcmpistriz128:
17171 case Intrinsic::x86_sse42_pcmpestriz128: {
17175 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17176 case Intrinsic::x86_sse42_pcmpistria128:
17177 Opcode = X86ISD::PCMPISTRI;
17178 X86CC = X86::COND_A;
17180 case Intrinsic::x86_sse42_pcmpestria128:
17181 Opcode = X86ISD::PCMPESTRI;
17182 X86CC = X86::COND_A;
17184 case Intrinsic::x86_sse42_pcmpistric128:
17185 Opcode = X86ISD::PCMPISTRI;
17186 X86CC = X86::COND_B;
17188 case Intrinsic::x86_sse42_pcmpestric128:
17189 Opcode = X86ISD::PCMPESTRI;
17190 X86CC = X86::COND_B;
17192 case Intrinsic::x86_sse42_pcmpistrio128:
17193 Opcode = X86ISD::PCMPISTRI;
17194 X86CC = X86::COND_O;
17196 case Intrinsic::x86_sse42_pcmpestrio128:
17197 Opcode = X86ISD::PCMPESTRI;
17198 X86CC = X86::COND_O;
17200 case Intrinsic::x86_sse42_pcmpistris128:
17201 Opcode = X86ISD::PCMPISTRI;
17202 X86CC = X86::COND_S;
17204 case Intrinsic::x86_sse42_pcmpestris128:
17205 Opcode = X86ISD::PCMPESTRI;
17206 X86CC = X86::COND_S;
17208 case Intrinsic::x86_sse42_pcmpistriz128:
17209 Opcode = X86ISD::PCMPISTRI;
17210 X86CC = X86::COND_E;
17212 case Intrinsic::x86_sse42_pcmpestriz128:
17213 Opcode = X86ISD::PCMPESTRI;
17214 X86CC = X86::COND_E;
17217 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17218 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17219 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17220 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17221 DAG.getConstant(X86CC, MVT::i8),
17222 SDValue(PCMP.getNode(), 1));
17223 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17226 case Intrinsic::x86_sse42_pcmpistri128:
17227 case Intrinsic::x86_sse42_pcmpestri128: {
17229 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17230 Opcode = X86ISD::PCMPISTRI;
17232 Opcode = X86ISD::PCMPESTRI;
17234 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17235 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17236 return DAG.getNode(Opcode, dl, VTs, NewOps);
17239 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17240 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17241 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17242 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17243 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17244 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17245 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17246 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17247 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17248 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17249 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17250 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17251 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17252 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17253 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17254 dl, Op.getValueType(),
17258 Op.getOperand(4), Op.getOperand(1),
17264 case Intrinsic::x86_fma_vfmadd_ps:
17265 case Intrinsic::x86_fma_vfmadd_pd:
17266 case Intrinsic::x86_fma_vfmsub_ps:
17267 case Intrinsic::x86_fma_vfmsub_pd:
17268 case Intrinsic::x86_fma_vfnmadd_ps:
17269 case Intrinsic::x86_fma_vfnmadd_pd:
17270 case Intrinsic::x86_fma_vfnmsub_ps:
17271 case Intrinsic::x86_fma_vfnmsub_pd:
17272 case Intrinsic::x86_fma_vfmaddsub_ps:
17273 case Intrinsic::x86_fma_vfmaddsub_pd:
17274 case Intrinsic::x86_fma_vfmsubadd_ps:
17275 case Intrinsic::x86_fma_vfmsubadd_pd:
17276 case Intrinsic::x86_fma_vfmadd_ps_256:
17277 case Intrinsic::x86_fma_vfmadd_pd_256:
17278 case Intrinsic::x86_fma_vfmsub_ps_256:
17279 case Intrinsic::x86_fma_vfmsub_pd_256:
17280 case Intrinsic::x86_fma_vfnmadd_ps_256:
17281 case Intrinsic::x86_fma_vfnmadd_pd_256:
17282 case Intrinsic::x86_fma_vfnmsub_ps_256:
17283 case Intrinsic::x86_fma_vfnmsub_pd_256:
17284 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17285 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17286 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17287 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17288 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17289 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17293 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17294 SDValue Src, SDValue Mask, SDValue Base,
17295 SDValue Index, SDValue ScaleOp, SDValue Chain,
17296 const X86Subtarget * Subtarget) {
17298 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17299 assert(C && "Invalid scale type");
17300 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17301 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17302 Index.getSimpleValueType().getVectorNumElements());
17304 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17306 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17308 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17309 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17310 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17311 SDValue Segment = DAG.getRegister(0, MVT::i32);
17312 if (Src.getOpcode() == ISD::UNDEF)
17313 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17314 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17315 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17316 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17317 return DAG.getMergeValues(RetOps, dl);
17320 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17321 SDValue Src, SDValue Mask, SDValue Base,
17322 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17324 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17325 assert(C && "Invalid scale type");
17326 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17327 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17328 SDValue Segment = DAG.getRegister(0, MVT::i32);
17329 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17330 Index.getSimpleValueType().getVectorNumElements());
17332 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17334 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17336 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17337 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17338 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17339 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17340 return SDValue(Res, 1);
17343 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17344 SDValue Mask, SDValue Base, SDValue Index,
17345 SDValue ScaleOp, SDValue Chain) {
17347 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17348 assert(C && "Invalid scale type");
17349 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17350 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17351 SDValue Segment = DAG.getRegister(0, MVT::i32);
17353 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17355 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17357 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17359 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17360 //SDVTList VTs = DAG.getVTList(MVT::Other);
17361 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17362 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17363 return SDValue(Res, 0);
17366 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17367 // read performance monitor counters (x86_rdpmc).
17368 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17369 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17370 SmallVectorImpl<SDValue> &Results) {
17371 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17372 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17375 // The ECX register is used to select the index of the performance counter
17377 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17379 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17381 // Reads the content of a 64-bit performance counter and returns it in the
17382 // registers EDX:EAX.
17383 if (Subtarget->is64Bit()) {
17384 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17385 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17388 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17389 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17392 Chain = HI.getValue(1);
17394 if (Subtarget->is64Bit()) {
17395 // The EAX register is loaded with the low-order 32 bits. The EDX register
17396 // is loaded with the supported high-order bits of the counter.
17397 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17398 DAG.getConstant(32, MVT::i8));
17399 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17400 Results.push_back(Chain);
17404 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17405 SDValue Ops[] = { LO, HI };
17406 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17407 Results.push_back(Pair);
17408 Results.push_back(Chain);
17411 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17412 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17413 // also used to custom lower READCYCLECOUNTER nodes.
17414 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17415 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17416 SmallVectorImpl<SDValue> &Results) {
17417 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17418 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17421 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17422 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17423 // and the EAX register is loaded with the low-order 32 bits.
17424 if (Subtarget->is64Bit()) {
17425 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17426 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17429 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17430 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17433 SDValue Chain = HI.getValue(1);
17435 if (Opcode == X86ISD::RDTSCP_DAG) {
17436 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17438 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17439 // the ECX register. Add 'ecx' explicitly to the chain.
17440 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17442 // Explicitly store the content of ECX at the location passed in input
17443 // to the 'rdtscp' intrinsic.
17444 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17445 MachinePointerInfo(), false, false, 0);
17448 if (Subtarget->is64Bit()) {
17449 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17450 // the EAX register is loaded with the low-order 32 bits.
17451 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17452 DAG.getConstant(32, MVT::i8));
17453 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17454 Results.push_back(Chain);
17458 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17459 SDValue Ops[] = { LO, HI };
17460 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17461 Results.push_back(Pair);
17462 Results.push_back(Chain);
17465 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17466 SelectionDAG &DAG) {
17467 SmallVector<SDValue, 2> Results;
17469 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17471 return DAG.getMergeValues(Results, DL);
17475 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17476 SelectionDAG &DAG) {
17477 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17479 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17484 switch(IntrData->Type) {
17486 llvm_unreachable("Unknown Intrinsic Type");
17490 // Emit the node with the right value type.
17491 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17492 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17494 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17495 // Otherwise return the value from Rand, which is always 0, casted to i32.
17496 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17497 DAG.getConstant(1, Op->getValueType(1)),
17498 DAG.getConstant(X86::COND_B, MVT::i32),
17499 SDValue(Result.getNode(), 1) };
17500 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17501 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17504 // Return { result, isValid, chain }.
17505 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17506 SDValue(Result.getNode(), 2));
17509 //gather(v1, mask, index, base, scale);
17510 SDValue Chain = Op.getOperand(0);
17511 SDValue Src = Op.getOperand(2);
17512 SDValue Base = Op.getOperand(3);
17513 SDValue Index = Op.getOperand(4);
17514 SDValue Mask = Op.getOperand(5);
17515 SDValue Scale = Op.getOperand(6);
17516 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17520 //scatter(base, mask, index, v1, scale);
17521 SDValue Chain = Op.getOperand(0);
17522 SDValue Base = Op.getOperand(2);
17523 SDValue Mask = Op.getOperand(3);
17524 SDValue Index = Op.getOperand(4);
17525 SDValue Src = Op.getOperand(5);
17526 SDValue Scale = Op.getOperand(6);
17527 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17530 SDValue Hint = Op.getOperand(6);
17532 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17533 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17534 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17535 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17536 SDValue Chain = Op.getOperand(0);
17537 SDValue Mask = Op.getOperand(2);
17538 SDValue Index = Op.getOperand(3);
17539 SDValue Base = Op.getOperand(4);
17540 SDValue Scale = Op.getOperand(5);
17541 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17543 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17545 SmallVector<SDValue, 2> Results;
17546 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17547 return DAG.getMergeValues(Results, dl);
17549 // Read Performance Monitoring Counters.
17551 SmallVector<SDValue, 2> Results;
17552 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17553 return DAG.getMergeValues(Results, dl);
17555 // XTEST intrinsics.
17557 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17558 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17559 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17560 DAG.getConstant(X86::COND_NE, MVT::i8),
17562 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17563 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17564 Ret, SDValue(InTrans.getNode(), 1));
17568 SmallVector<SDValue, 2> Results;
17569 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17570 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17571 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17572 DAG.getConstant(-1, MVT::i8));
17573 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17574 Op.getOperand(4), GenCF.getValue(1));
17575 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17576 Op.getOperand(5), MachinePointerInfo(),
17578 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17579 DAG.getConstant(X86::COND_B, MVT::i8),
17581 Results.push_back(SetCC);
17582 Results.push_back(Store);
17583 return DAG.getMergeValues(Results, dl);
17585 case COMPRESS_TO_MEM: {
17587 SDValue Mask = Op.getOperand(4);
17588 SDValue DataToCompress = Op.getOperand(3);
17589 SDValue Addr = Op.getOperand(2);
17590 SDValue Chain = Op.getOperand(0);
17592 if (isAllOnes(Mask)) // return just a store
17593 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17594 MachinePointerInfo(), false, false, 0);
17596 EVT VT = DataToCompress.getValueType();
17597 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17598 VT.getVectorNumElements());
17599 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17600 Mask.getValueType().getSizeInBits());
17601 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17602 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17603 DAG.getIntPtrConstant(0));
17605 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17606 DataToCompress, DAG.getUNDEF(VT));
17607 return DAG.getStore(Chain, dl, Compressed, Addr,
17608 MachinePointerInfo(), false, false, 0);
17610 case EXPAND_FROM_MEM: {
17612 SDValue Mask = Op.getOperand(4);
17613 SDValue PathThru = Op.getOperand(3);
17614 SDValue Addr = Op.getOperand(2);
17615 SDValue Chain = Op.getOperand(0);
17616 EVT VT = Op.getValueType();
17618 if (isAllOnes(Mask)) // return just a load
17619 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17621 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17622 VT.getVectorNumElements());
17623 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17624 Mask.getValueType().getSizeInBits());
17625 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17626 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17627 DAG.getIntPtrConstant(0));
17629 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17630 false, false, false, 0);
17632 SmallVector<SDValue, 2> Results;
17633 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17635 Results.push_back(Chain);
17636 return DAG.getMergeValues(Results, dl);
17641 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17642 SelectionDAG &DAG) const {
17643 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17644 MFI->setReturnAddressIsTaken(true);
17646 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17649 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17651 EVT PtrVT = getPointerTy();
17654 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17655 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17656 DAG.getSubtarget().getRegisterInfo());
17657 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17658 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17659 DAG.getNode(ISD::ADD, dl, PtrVT,
17660 FrameAddr, Offset),
17661 MachinePointerInfo(), false, false, false, 0);
17664 // Just load the return address.
17665 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17666 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17667 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17670 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17671 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17672 MFI->setFrameAddressIsTaken(true);
17674 EVT VT = Op.getValueType();
17675 SDLoc dl(Op); // FIXME probably not meaningful
17676 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17677 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17678 DAG.getSubtarget().getRegisterInfo());
17679 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17680 DAG.getMachineFunction());
17681 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17682 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17683 "Invalid Frame Register!");
17684 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17686 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17687 MachinePointerInfo(),
17688 false, false, false, 0);
17692 // FIXME? Maybe this could be a TableGen attribute on some registers and
17693 // this table could be generated automatically from RegInfo.
17694 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17696 unsigned Reg = StringSwitch<unsigned>(RegName)
17697 .Case("esp", X86::ESP)
17698 .Case("rsp", X86::RSP)
17702 report_fatal_error("Invalid register name global variable");
17705 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17706 SelectionDAG &DAG) const {
17707 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17708 DAG.getSubtarget().getRegisterInfo());
17709 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17712 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17713 SDValue Chain = Op.getOperand(0);
17714 SDValue Offset = Op.getOperand(1);
17715 SDValue Handler = Op.getOperand(2);
17718 EVT PtrVT = getPointerTy();
17719 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17720 DAG.getSubtarget().getRegisterInfo());
17721 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17722 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17723 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17724 "Invalid Frame Register!");
17725 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17726 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17728 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17729 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17730 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17731 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17733 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17735 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17736 DAG.getRegister(StoreAddrReg, PtrVT));
17739 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17740 SelectionDAG &DAG) const {
17742 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17743 DAG.getVTList(MVT::i32, MVT::Other),
17744 Op.getOperand(0), Op.getOperand(1));
17747 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17748 SelectionDAG &DAG) const {
17750 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17751 Op.getOperand(0), Op.getOperand(1));
17754 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17755 return Op.getOperand(0);
17758 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17759 SelectionDAG &DAG) const {
17760 SDValue Root = Op.getOperand(0);
17761 SDValue Trmp = Op.getOperand(1); // trampoline
17762 SDValue FPtr = Op.getOperand(2); // nested function
17763 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17766 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17767 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17769 if (Subtarget->is64Bit()) {
17770 SDValue OutChains[6];
17772 // Large code-model.
17773 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17774 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17776 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17777 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17779 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17781 // Load the pointer to the nested function into R11.
17782 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17783 SDValue Addr = Trmp;
17784 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17785 Addr, MachinePointerInfo(TrmpAddr),
17788 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17789 DAG.getConstant(2, MVT::i64));
17790 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17791 MachinePointerInfo(TrmpAddr, 2),
17794 // Load the 'nest' parameter value into R10.
17795 // R10 is specified in X86CallingConv.td
17796 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17797 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17798 DAG.getConstant(10, MVT::i64));
17799 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17800 Addr, MachinePointerInfo(TrmpAddr, 10),
17803 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17804 DAG.getConstant(12, MVT::i64));
17805 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17806 MachinePointerInfo(TrmpAddr, 12),
17809 // Jump to the nested function.
17810 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17811 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17812 DAG.getConstant(20, MVT::i64));
17813 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17814 Addr, MachinePointerInfo(TrmpAddr, 20),
17817 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17818 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17819 DAG.getConstant(22, MVT::i64));
17820 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17821 MachinePointerInfo(TrmpAddr, 22),
17824 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17826 const Function *Func =
17827 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17828 CallingConv::ID CC = Func->getCallingConv();
17833 llvm_unreachable("Unsupported calling convention");
17834 case CallingConv::C:
17835 case CallingConv::X86_StdCall: {
17836 // Pass 'nest' parameter in ECX.
17837 // Must be kept in sync with X86CallingConv.td
17838 NestReg = X86::ECX;
17840 // Check that ECX wasn't needed by an 'inreg' parameter.
17841 FunctionType *FTy = Func->getFunctionType();
17842 const AttributeSet &Attrs = Func->getAttributes();
17844 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17845 unsigned InRegCount = 0;
17848 for (FunctionType::param_iterator I = FTy->param_begin(),
17849 E = FTy->param_end(); I != E; ++I, ++Idx)
17850 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17851 // FIXME: should only count parameters that are lowered to integers.
17852 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17854 if (InRegCount > 2) {
17855 report_fatal_error("Nest register in use - reduce number of inreg"
17861 case CallingConv::X86_FastCall:
17862 case CallingConv::X86_ThisCall:
17863 case CallingConv::Fast:
17864 // Pass 'nest' parameter in EAX.
17865 // Must be kept in sync with X86CallingConv.td
17866 NestReg = X86::EAX;
17870 SDValue OutChains[4];
17871 SDValue Addr, Disp;
17873 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17874 DAG.getConstant(10, MVT::i32));
17875 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17877 // This is storing the opcode for MOV32ri.
17878 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17879 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17880 OutChains[0] = DAG.getStore(Root, dl,
17881 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17882 Trmp, MachinePointerInfo(TrmpAddr),
17885 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17886 DAG.getConstant(1, MVT::i32));
17887 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17888 MachinePointerInfo(TrmpAddr, 1),
17891 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17892 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17893 DAG.getConstant(5, MVT::i32));
17894 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17895 MachinePointerInfo(TrmpAddr, 5),
17898 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17899 DAG.getConstant(6, MVT::i32));
17900 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17901 MachinePointerInfo(TrmpAddr, 6),
17904 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17908 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17909 SelectionDAG &DAG) const {
17911 The rounding mode is in bits 11:10 of FPSR, and has the following
17913 00 Round to nearest
17918 FLT_ROUNDS, on the other hand, expects the following:
17925 To perform the conversion, we do:
17926 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17929 MachineFunction &MF = DAG.getMachineFunction();
17930 const TargetMachine &TM = MF.getTarget();
17931 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17932 unsigned StackAlignment = TFI.getStackAlignment();
17933 MVT VT = Op.getSimpleValueType();
17936 // Save FP Control Word to stack slot
17937 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17938 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17940 MachineMemOperand *MMO =
17941 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17942 MachineMemOperand::MOStore, 2, 2);
17944 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17945 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17946 DAG.getVTList(MVT::Other),
17947 Ops, MVT::i16, MMO);
17949 // Load FP Control Word from stack slot
17950 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17951 MachinePointerInfo(), false, false, false, 0);
17953 // Transform as necessary
17955 DAG.getNode(ISD::SRL, DL, MVT::i16,
17956 DAG.getNode(ISD::AND, DL, MVT::i16,
17957 CWD, DAG.getConstant(0x800, MVT::i16)),
17958 DAG.getConstant(11, MVT::i8));
17960 DAG.getNode(ISD::SRL, DL, MVT::i16,
17961 DAG.getNode(ISD::AND, DL, MVT::i16,
17962 CWD, DAG.getConstant(0x400, MVT::i16)),
17963 DAG.getConstant(9, MVT::i8));
17966 DAG.getNode(ISD::AND, DL, MVT::i16,
17967 DAG.getNode(ISD::ADD, DL, MVT::i16,
17968 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17969 DAG.getConstant(1, MVT::i16)),
17970 DAG.getConstant(3, MVT::i16));
17972 return DAG.getNode((VT.getSizeInBits() < 16 ?
17973 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17976 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17977 MVT VT = Op.getSimpleValueType();
17979 unsigned NumBits = VT.getSizeInBits();
17982 Op = Op.getOperand(0);
17983 if (VT == MVT::i8) {
17984 // Zero extend to i32 since there is not an i8 bsr.
17986 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17989 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17990 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17991 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17993 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17996 DAG.getConstant(NumBits+NumBits-1, OpVT),
17997 DAG.getConstant(X86::COND_E, MVT::i8),
18000 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
18002 // Finally xor with NumBits-1.
18003 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18006 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18010 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
18011 MVT VT = Op.getSimpleValueType();
18013 unsigned NumBits = VT.getSizeInBits();
18016 Op = Op.getOperand(0);
18017 if (VT == MVT::i8) {
18018 // Zero extend to i32 since there is not an i8 bsr.
18020 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18023 // Issue a bsr (scan bits in reverse).
18024 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18025 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18027 // And xor with NumBits-1.
18028 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18031 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18035 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18036 MVT VT = Op.getSimpleValueType();
18037 unsigned NumBits = VT.getSizeInBits();
18039 Op = Op.getOperand(0);
18041 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18042 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18043 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18045 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18048 DAG.getConstant(NumBits, VT),
18049 DAG.getConstant(X86::COND_E, MVT::i8),
18052 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18055 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18056 // ones, and then concatenate the result back.
18057 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18058 MVT VT = Op.getSimpleValueType();
18060 assert(VT.is256BitVector() && VT.isInteger() &&
18061 "Unsupported value type for operation");
18063 unsigned NumElems = VT.getVectorNumElements();
18066 // Extract the LHS vectors
18067 SDValue LHS = Op.getOperand(0);
18068 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18069 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18071 // Extract the RHS vectors
18072 SDValue RHS = Op.getOperand(1);
18073 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18074 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18076 MVT EltVT = VT.getVectorElementType();
18077 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18079 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18080 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18081 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18084 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18085 assert(Op.getSimpleValueType().is256BitVector() &&
18086 Op.getSimpleValueType().isInteger() &&
18087 "Only handle AVX 256-bit vector integer operation");
18088 return Lower256IntArith(Op, DAG);
18091 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18092 assert(Op.getSimpleValueType().is256BitVector() &&
18093 Op.getSimpleValueType().isInteger() &&
18094 "Only handle AVX 256-bit vector integer operation");
18095 return Lower256IntArith(Op, DAG);
18098 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18099 SelectionDAG &DAG) {
18101 MVT VT = Op.getSimpleValueType();
18103 // Decompose 256-bit ops into smaller 128-bit ops.
18104 if (VT.is256BitVector() && !Subtarget->hasInt256())
18105 return Lower256IntArith(Op, DAG);
18107 SDValue A = Op.getOperand(0);
18108 SDValue B = Op.getOperand(1);
18110 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18111 if (VT == MVT::v4i32) {
18112 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18113 "Should not custom lower when pmuldq is available!");
18115 // Extract the odd parts.
18116 static const int UnpackMask[] = { 1, -1, 3, -1 };
18117 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18118 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18120 // Multiply the even parts.
18121 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18122 // Now multiply odd parts.
18123 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18125 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18126 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18128 // Merge the two vectors back together with a shuffle. This expands into 2
18130 static const int ShufMask[] = { 0, 4, 2, 6 };
18131 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18134 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18135 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18137 // Ahi = psrlqi(a, 32);
18138 // Bhi = psrlqi(b, 32);
18140 // AloBlo = pmuludq(a, b);
18141 // AloBhi = pmuludq(a, Bhi);
18142 // AhiBlo = pmuludq(Ahi, b);
18144 // AloBhi = psllqi(AloBhi, 32);
18145 // AhiBlo = psllqi(AhiBlo, 32);
18146 // return AloBlo + AloBhi + AhiBlo;
18148 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18149 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18151 // Bit cast to 32-bit vectors for MULUDQ
18152 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18153 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18154 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18155 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18156 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18157 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18159 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18160 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18161 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18163 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18164 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18166 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18167 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18170 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18171 assert(Subtarget->isTargetWin64() && "Unexpected target");
18172 EVT VT = Op.getValueType();
18173 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18174 "Unexpected return type for lowering");
18178 switch (Op->getOpcode()) {
18179 default: llvm_unreachable("Unexpected request for libcall!");
18180 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18181 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18182 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18183 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18184 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18185 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18189 SDValue InChain = DAG.getEntryNode();
18191 TargetLowering::ArgListTy Args;
18192 TargetLowering::ArgListEntry Entry;
18193 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18194 EVT ArgVT = Op->getOperand(i).getValueType();
18195 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18196 "Unexpected argument type for lowering");
18197 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18198 Entry.Node = StackPtr;
18199 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18201 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18202 Entry.Ty = PointerType::get(ArgTy,0);
18203 Entry.isSExt = false;
18204 Entry.isZExt = false;
18205 Args.push_back(Entry);
18208 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18211 TargetLowering::CallLoweringInfo CLI(DAG);
18212 CLI.setDebugLoc(dl).setChain(InChain)
18213 .setCallee(getLibcallCallingConv(LC),
18214 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18215 Callee, std::move(Args), 0)
18216 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18218 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18219 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18222 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18223 SelectionDAG &DAG) {
18224 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18225 EVT VT = Op0.getValueType();
18228 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18229 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18231 // PMULxD operations multiply each even value (starting at 0) of LHS with
18232 // the related value of RHS and produce a widen result.
18233 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18234 // => <2 x i64> <ae|cg>
18236 // In other word, to have all the results, we need to perform two PMULxD:
18237 // 1. one with the even values.
18238 // 2. one with the odd values.
18239 // To achieve #2, with need to place the odd values at an even position.
18241 // Place the odd value at an even position (basically, shift all values 1
18242 // step to the left):
18243 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18244 // <a|b|c|d> => <b|undef|d|undef>
18245 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18246 // <e|f|g|h> => <f|undef|h|undef>
18247 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18249 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18251 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18252 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18254 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18255 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18256 // => <2 x i64> <ae|cg>
18257 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18258 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18259 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18260 // => <2 x i64> <bf|dh>
18261 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18262 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18264 // Shuffle it back into the right order.
18265 SDValue Highs, Lows;
18266 if (VT == MVT::v8i32) {
18267 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18268 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18269 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18270 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18272 const int HighMask[] = {1, 5, 3, 7};
18273 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18274 const int LowMask[] = {0, 4, 2, 6};
18275 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18278 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18279 // unsigned multiply.
18280 if (IsSigned && !Subtarget->hasSSE41()) {
18282 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18283 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18284 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18285 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18286 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18288 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18289 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18292 // The first result of MUL_LOHI is actually the low value, followed by the
18294 SDValue Ops[] = {Lows, Highs};
18295 return DAG.getMergeValues(Ops, dl);
18298 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18299 const X86Subtarget *Subtarget) {
18300 MVT VT = Op.getSimpleValueType();
18302 SDValue R = Op.getOperand(0);
18303 SDValue Amt = Op.getOperand(1);
18305 // Optimize shl/srl/sra with constant shift amount.
18306 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18307 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18308 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18310 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18311 (Subtarget->hasInt256() &&
18312 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18313 (Subtarget->hasAVX512() &&
18314 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18315 if (Op.getOpcode() == ISD::SHL)
18316 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18318 if (Op.getOpcode() == ISD::SRL)
18319 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18321 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18322 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18326 if (VT == MVT::v16i8) {
18327 if (Op.getOpcode() == ISD::SHL) {
18328 // Make a large shift.
18329 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18330 MVT::v8i16, R, ShiftAmt,
18332 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18333 // Zero out the rightmost bits.
18334 SmallVector<SDValue, 16> V(16,
18335 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18337 return DAG.getNode(ISD::AND, dl, VT, SHL,
18338 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18340 if (Op.getOpcode() == ISD::SRL) {
18341 // Make a large shift.
18342 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18343 MVT::v8i16, R, ShiftAmt,
18345 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18346 // Zero out the leftmost bits.
18347 SmallVector<SDValue, 16> V(16,
18348 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18350 return DAG.getNode(ISD::AND, dl, VT, SRL,
18351 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18353 if (Op.getOpcode() == ISD::SRA) {
18354 if (ShiftAmt == 7) {
18355 // R s>> 7 === R s< 0
18356 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18357 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18360 // R s>> a === ((R u>> a) ^ m) - m
18361 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18362 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18364 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18365 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18366 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18369 llvm_unreachable("Unknown shift opcode.");
18372 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18373 if (Op.getOpcode() == ISD::SHL) {
18374 // Make a large shift.
18375 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18376 MVT::v16i16, R, ShiftAmt,
18378 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18379 // Zero out the rightmost bits.
18380 SmallVector<SDValue, 32> V(32,
18381 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18383 return DAG.getNode(ISD::AND, dl, VT, SHL,
18384 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18386 if (Op.getOpcode() == ISD::SRL) {
18387 // Make a large shift.
18388 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18389 MVT::v16i16, R, ShiftAmt,
18391 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18392 // Zero out the leftmost bits.
18393 SmallVector<SDValue, 32> V(32,
18394 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18396 return DAG.getNode(ISD::AND, dl, VT, SRL,
18397 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18399 if (Op.getOpcode() == ISD::SRA) {
18400 if (ShiftAmt == 7) {
18401 // R s>> 7 === R s< 0
18402 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18403 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18406 // R s>> a === ((R u>> a) ^ m) - m
18407 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18408 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18410 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18411 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18412 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18415 llvm_unreachable("Unknown shift opcode.");
18420 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18421 if (!Subtarget->is64Bit() &&
18422 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18423 Amt.getOpcode() == ISD::BITCAST &&
18424 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18425 Amt = Amt.getOperand(0);
18426 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18427 VT.getVectorNumElements();
18428 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18429 uint64_t ShiftAmt = 0;
18430 for (unsigned i = 0; i != Ratio; ++i) {
18431 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18435 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18437 // Check remaining shift amounts.
18438 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18439 uint64_t ShAmt = 0;
18440 for (unsigned j = 0; j != Ratio; ++j) {
18441 ConstantSDNode *C =
18442 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18446 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18448 if (ShAmt != ShiftAmt)
18451 switch (Op.getOpcode()) {
18453 llvm_unreachable("Unknown shift opcode!");
18455 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18458 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18461 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18469 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18470 const X86Subtarget* Subtarget) {
18471 MVT VT = Op.getSimpleValueType();
18473 SDValue R = Op.getOperand(0);
18474 SDValue Amt = Op.getOperand(1);
18476 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18477 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18478 (Subtarget->hasInt256() &&
18479 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18480 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18481 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18483 EVT EltVT = VT.getVectorElementType();
18485 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18486 // Check if this build_vector node is doing a splat.
18487 // If so, then set BaseShAmt equal to the splat value.
18488 BaseShAmt = BV->getSplatValue();
18489 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18490 BaseShAmt = SDValue();
18492 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18493 Amt = Amt.getOperand(0);
18495 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18496 if (SVN && SVN->isSplat()) {
18497 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18498 SDValue InVec = Amt.getOperand(0);
18499 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18500 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18501 "Unexpected shuffle index found!");
18502 BaseShAmt = InVec.getOperand(SplatIdx);
18503 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18504 if (ConstantSDNode *C =
18505 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18506 if (C->getZExtValue() == SplatIdx)
18507 BaseShAmt = InVec.getOperand(1);
18512 // Avoid introducing an extract element from a shuffle.
18513 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18514 DAG.getIntPtrConstant(SplatIdx));
18518 if (BaseShAmt.getNode()) {
18519 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18520 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18521 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18522 else if (EltVT.bitsLT(MVT::i32))
18523 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18525 switch (Op.getOpcode()) {
18527 llvm_unreachable("Unknown shift opcode!");
18529 switch (VT.SimpleTy) {
18530 default: return SDValue();
18539 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18542 switch (VT.SimpleTy) {
18543 default: return SDValue();
18550 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18553 switch (VT.SimpleTy) {
18554 default: return SDValue();
18563 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18569 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18570 if (!Subtarget->is64Bit() &&
18571 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18572 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18573 Amt.getOpcode() == ISD::BITCAST &&
18574 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18575 Amt = Amt.getOperand(0);
18576 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18577 VT.getVectorNumElements();
18578 std::vector<SDValue> Vals(Ratio);
18579 for (unsigned i = 0; i != Ratio; ++i)
18580 Vals[i] = Amt.getOperand(i);
18581 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18582 for (unsigned j = 0; j != Ratio; ++j)
18583 if (Vals[j] != Amt.getOperand(i + j))
18586 switch (Op.getOpcode()) {
18588 llvm_unreachable("Unknown shift opcode!");
18590 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18592 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18594 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18601 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18602 SelectionDAG &DAG) {
18603 MVT VT = Op.getSimpleValueType();
18605 SDValue R = Op.getOperand(0);
18606 SDValue Amt = Op.getOperand(1);
18609 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18610 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18612 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18616 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18620 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18622 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18623 if (Subtarget->hasInt256()) {
18624 if (Op.getOpcode() == ISD::SRL &&
18625 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18626 VT == MVT::v4i64 || VT == MVT::v8i32))
18628 if (Op.getOpcode() == ISD::SHL &&
18629 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18630 VT == MVT::v4i64 || VT == MVT::v8i32))
18632 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18636 // If possible, lower this packed shift into a vector multiply instead of
18637 // expanding it into a sequence of scalar shifts.
18638 // Do this only if the vector shift count is a constant build_vector.
18639 if (Op.getOpcode() == ISD::SHL &&
18640 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18641 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18642 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18643 SmallVector<SDValue, 8> Elts;
18644 EVT SVT = VT.getScalarType();
18645 unsigned SVTBits = SVT.getSizeInBits();
18646 const APInt &One = APInt(SVTBits, 1);
18647 unsigned NumElems = VT.getVectorNumElements();
18649 for (unsigned i=0; i !=NumElems; ++i) {
18650 SDValue Op = Amt->getOperand(i);
18651 if (Op->getOpcode() == ISD::UNDEF) {
18652 Elts.push_back(Op);
18656 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18657 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18658 uint64_t ShAmt = C.getZExtValue();
18659 if (ShAmt >= SVTBits) {
18660 Elts.push_back(DAG.getUNDEF(SVT));
18663 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18665 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18666 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18669 // Lower SHL with variable shift amount.
18670 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18671 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18673 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18674 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18675 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18676 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18679 // If possible, lower this shift as a sequence of two shifts by
18680 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18682 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18684 // Could be rewritten as:
18685 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18687 // The advantage is that the two shifts from the example would be
18688 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18689 // the vector shift into four scalar shifts plus four pairs of vector
18691 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18692 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18693 unsigned TargetOpcode = X86ISD::MOVSS;
18694 bool CanBeSimplified;
18695 // The splat value for the first packed shift (the 'X' from the example).
18696 SDValue Amt1 = Amt->getOperand(0);
18697 // The splat value for the second packed shift (the 'Y' from the example).
18698 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18699 Amt->getOperand(2);
18701 // See if it is possible to replace this node with a sequence of
18702 // two shifts followed by a MOVSS/MOVSD
18703 if (VT == MVT::v4i32) {
18704 // Check if it is legal to use a MOVSS.
18705 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18706 Amt2 == Amt->getOperand(3);
18707 if (!CanBeSimplified) {
18708 // Otherwise, check if we can still simplify this node using a MOVSD.
18709 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18710 Amt->getOperand(2) == Amt->getOperand(3);
18711 TargetOpcode = X86ISD::MOVSD;
18712 Amt2 = Amt->getOperand(2);
18715 // Do similar checks for the case where the machine value type
18717 CanBeSimplified = Amt1 == Amt->getOperand(1);
18718 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18719 CanBeSimplified = Amt2 == Amt->getOperand(i);
18721 if (!CanBeSimplified) {
18722 TargetOpcode = X86ISD::MOVSD;
18723 CanBeSimplified = true;
18724 Amt2 = Amt->getOperand(4);
18725 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18726 CanBeSimplified = Amt1 == Amt->getOperand(i);
18727 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18728 CanBeSimplified = Amt2 == Amt->getOperand(j);
18732 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18733 isa<ConstantSDNode>(Amt2)) {
18734 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18735 EVT CastVT = MVT::v4i32;
18737 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18738 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18740 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18741 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18742 if (TargetOpcode == X86ISD::MOVSD)
18743 CastVT = MVT::v2i64;
18744 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18745 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18746 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18748 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18752 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18753 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18756 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18757 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18759 // Turn 'a' into a mask suitable for VSELECT
18760 SDValue VSelM = DAG.getConstant(0x80, VT);
18761 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18762 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18764 SDValue CM1 = DAG.getConstant(0x0f, VT);
18765 SDValue CM2 = DAG.getConstant(0x3f, VT);
18767 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18768 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18769 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18770 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18771 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18774 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18775 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18776 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18778 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18779 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18780 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18781 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18782 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18785 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18786 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18787 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18789 // return VSELECT(r, r+r, a);
18790 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18791 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18795 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18796 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18797 // solution better.
18798 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18799 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18801 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18802 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18803 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18804 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18805 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18808 // Decompose 256-bit shifts into smaller 128-bit shifts.
18809 if (VT.is256BitVector()) {
18810 unsigned NumElems = VT.getVectorNumElements();
18811 MVT EltVT = VT.getVectorElementType();
18812 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18814 // Extract the two vectors
18815 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18816 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18818 // Recreate the shift amount vectors
18819 SDValue Amt1, Amt2;
18820 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18821 // Constant shift amount
18822 SmallVector<SDValue, 4> Amt1Csts;
18823 SmallVector<SDValue, 4> Amt2Csts;
18824 for (unsigned i = 0; i != NumElems/2; ++i)
18825 Amt1Csts.push_back(Amt->getOperand(i));
18826 for (unsigned i = NumElems/2; i != NumElems; ++i)
18827 Amt2Csts.push_back(Amt->getOperand(i));
18829 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18830 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18832 // Variable shift amount
18833 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18834 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18837 // Issue new vector shifts for the smaller types
18838 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18839 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18841 // Concatenate the result back
18842 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18848 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18849 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18850 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18851 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18852 // has only one use.
18853 SDNode *N = Op.getNode();
18854 SDValue LHS = N->getOperand(0);
18855 SDValue RHS = N->getOperand(1);
18856 unsigned BaseOp = 0;
18859 switch (Op.getOpcode()) {
18860 default: llvm_unreachable("Unknown ovf instruction!");
18862 // A subtract of one will be selected as a INC. Note that INC doesn't
18863 // set CF, so we can't do this for UADDO.
18864 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18866 BaseOp = X86ISD::INC;
18867 Cond = X86::COND_O;
18870 BaseOp = X86ISD::ADD;
18871 Cond = X86::COND_O;
18874 BaseOp = X86ISD::ADD;
18875 Cond = X86::COND_B;
18878 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18879 // set CF, so we can't do this for USUBO.
18880 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18882 BaseOp = X86ISD::DEC;
18883 Cond = X86::COND_O;
18886 BaseOp = X86ISD::SUB;
18887 Cond = X86::COND_O;
18890 BaseOp = X86ISD::SUB;
18891 Cond = X86::COND_B;
18894 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18895 Cond = X86::COND_O;
18897 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18898 if (N->getValueType(0) == MVT::i8) {
18899 BaseOp = X86ISD::UMUL8;
18900 Cond = X86::COND_O;
18903 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18905 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18908 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18909 DAG.getConstant(X86::COND_O, MVT::i32),
18910 SDValue(Sum.getNode(), 2));
18912 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18916 // Also sets EFLAGS.
18917 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18918 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18921 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18922 DAG.getConstant(Cond, MVT::i32),
18923 SDValue(Sum.getNode(), 1));
18925 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18928 // Sign extension of the low part of vector elements. This may be used either
18929 // when sign extend instructions are not available or if the vector element
18930 // sizes already match the sign-extended size. If the vector elements are in
18931 // their pre-extended size and sign extend instructions are available, that will
18932 // be handled by LowerSIGN_EXTEND.
18933 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18934 SelectionDAG &DAG) const {
18936 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18937 MVT VT = Op.getSimpleValueType();
18939 if (!Subtarget->hasSSE2() || !VT.isVector())
18942 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18943 ExtraVT.getScalarType().getSizeInBits();
18945 switch (VT.SimpleTy) {
18946 default: return SDValue();
18949 if (!Subtarget->hasFp256())
18951 if (!Subtarget->hasInt256()) {
18952 // needs to be split
18953 unsigned NumElems = VT.getVectorNumElements();
18955 // Extract the LHS vectors
18956 SDValue LHS = Op.getOperand(0);
18957 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18958 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18960 MVT EltVT = VT.getVectorElementType();
18961 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18963 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18964 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18965 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18967 SDValue Extra = DAG.getValueType(ExtraVT);
18969 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18970 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18972 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18977 SDValue Op0 = Op.getOperand(0);
18979 // This is a sign extension of some low part of vector elements without
18980 // changing the size of the vector elements themselves:
18981 // Shift-Left + Shift-Right-Algebraic.
18982 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18984 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18990 /// Returns true if the operand type is exactly twice the native width, and
18991 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18992 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18993 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18994 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18995 const X86Subtarget &Subtarget =
18996 getTargetMachine().getSubtarget<X86Subtarget>();
18997 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19000 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19001 else if (OpWidth == 128)
19002 return Subtarget.hasCmpxchg16b();
19007 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19008 return needsCmpXchgNb(SI->getValueOperand()->getType());
19011 // Note: this turns large loads into lock cmpxchg8b/16b.
19012 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19013 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19014 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19015 return needsCmpXchgNb(PTy->getElementType());
19018 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19019 const X86Subtarget &Subtarget =
19020 getTargetMachine().getSubtarget<X86Subtarget>();
19021 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19022 const Type *MemType = AI->getType();
19024 // If the operand is too big, we must see if cmpxchg8/16b is available
19025 // and default to library calls otherwise.
19026 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19027 return needsCmpXchgNb(MemType);
19029 AtomicRMWInst::BinOp Op = AI->getOperation();
19032 llvm_unreachable("Unknown atomic operation");
19033 case AtomicRMWInst::Xchg:
19034 case AtomicRMWInst::Add:
19035 case AtomicRMWInst::Sub:
19036 // It's better to use xadd, xsub or xchg for these in all cases.
19038 case AtomicRMWInst::Or:
19039 case AtomicRMWInst::And:
19040 case AtomicRMWInst::Xor:
19041 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19042 // prefix to a normal instruction for these operations.
19043 return !AI->use_empty();
19044 case AtomicRMWInst::Nand:
19045 case AtomicRMWInst::Max:
19046 case AtomicRMWInst::Min:
19047 case AtomicRMWInst::UMax:
19048 case AtomicRMWInst::UMin:
19049 // These always require a non-trivial set of data operations on x86. We must
19050 // use a cmpxchg loop.
19055 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19056 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19057 // no-sse2). There isn't any reason to disable it if the target processor
19059 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19063 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19064 const X86Subtarget &Subtarget =
19065 getTargetMachine().getSubtarget<X86Subtarget>();
19066 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19067 const Type *MemType = AI->getType();
19068 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19069 // there is no benefit in turning such RMWs into loads, and it is actually
19070 // harmful as it introduces a mfence.
19071 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19074 auto Builder = IRBuilder<>(AI);
19075 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19076 auto SynchScope = AI->getSynchScope();
19077 // We must restrict the ordering to avoid generating loads with Release or
19078 // ReleaseAcquire orderings.
19079 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19080 auto Ptr = AI->getPointerOperand();
19082 // Before the load we need a fence. Here is an example lifted from
19083 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19086 // x.store(1, relaxed);
19087 // r1 = y.fetch_add(0, release);
19089 // y.fetch_add(42, acquire);
19090 // r2 = x.load(relaxed);
19091 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19092 // lowered to just a load without a fence. A mfence flushes the store buffer,
19093 // making the optimization clearly correct.
19094 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19095 // otherwise, we might be able to be more agressive on relaxed idempotent
19096 // rmw. In practice, they do not look useful, so we don't try to be
19097 // especially clever.
19098 if (SynchScope == SingleThread) {
19099 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19100 // the IR level, so we must wrap it in an intrinsic.
19102 } else if (hasMFENCE(Subtarget)) {
19103 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19104 Intrinsic::x86_sse2_mfence);
19105 Builder.CreateCall(MFence);
19107 // FIXME: it might make sense to use a locked operation here but on a
19108 // different cache-line to prevent cache-line bouncing. In practice it
19109 // is probably a small win, and x86 processors without mfence are rare
19110 // enough that we do not bother.
19114 // Finally we can emit the atomic load.
19115 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19116 AI->getType()->getPrimitiveSizeInBits());
19117 Loaded->setAtomic(Order, SynchScope);
19118 AI->replaceAllUsesWith(Loaded);
19119 AI->eraseFromParent();
19123 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19124 SelectionDAG &DAG) {
19126 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19127 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19128 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19129 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19131 // The only fence that needs an instruction is a sequentially-consistent
19132 // cross-thread fence.
19133 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19134 if (hasMFENCE(*Subtarget))
19135 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19137 SDValue Chain = Op.getOperand(0);
19138 SDValue Zero = DAG.getConstant(0, MVT::i32);
19140 DAG.getRegister(X86::ESP, MVT::i32), // Base
19141 DAG.getTargetConstant(1, MVT::i8), // Scale
19142 DAG.getRegister(0, MVT::i32), // Index
19143 DAG.getTargetConstant(0, MVT::i32), // Disp
19144 DAG.getRegister(0, MVT::i32), // Segment.
19148 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19149 return SDValue(Res, 0);
19152 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19153 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19156 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19157 SelectionDAG &DAG) {
19158 MVT T = Op.getSimpleValueType();
19162 switch(T.SimpleTy) {
19163 default: llvm_unreachable("Invalid value type!");
19164 case MVT::i8: Reg = X86::AL; size = 1; break;
19165 case MVT::i16: Reg = X86::AX; size = 2; break;
19166 case MVT::i32: Reg = X86::EAX; size = 4; break;
19168 assert(Subtarget->is64Bit() && "Node not type legal!");
19169 Reg = X86::RAX; size = 8;
19172 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19173 Op.getOperand(2), SDValue());
19174 SDValue Ops[] = { cpIn.getValue(0),
19177 DAG.getTargetConstant(size, MVT::i8),
19178 cpIn.getValue(1) };
19179 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19180 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19181 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19185 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19186 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19187 MVT::i32, cpOut.getValue(2));
19188 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19189 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19191 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19192 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19193 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19197 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19198 SelectionDAG &DAG) {
19199 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19200 MVT DstVT = Op.getSimpleValueType();
19202 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19203 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19204 if (DstVT != MVT::f64)
19205 // This conversion needs to be expanded.
19208 SDValue InVec = Op->getOperand(0);
19210 unsigned NumElts = SrcVT.getVectorNumElements();
19211 EVT SVT = SrcVT.getVectorElementType();
19213 // Widen the vector in input in the case of MVT::v2i32.
19214 // Example: from MVT::v2i32 to MVT::v4i32.
19215 SmallVector<SDValue, 16> Elts;
19216 for (unsigned i = 0, e = NumElts; i != e; ++i)
19217 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19218 DAG.getIntPtrConstant(i)));
19220 // Explicitly mark the extra elements as Undef.
19221 SDValue Undef = DAG.getUNDEF(SVT);
19222 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19223 Elts.push_back(Undef);
19225 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19226 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19227 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19228 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19229 DAG.getIntPtrConstant(0));
19232 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19233 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19234 assert((DstVT == MVT::i64 ||
19235 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19236 "Unexpected custom BITCAST");
19237 // i64 <=> MMX conversions are Legal.
19238 if (SrcVT==MVT::i64 && DstVT.isVector())
19240 if (DstVT==MVT::i64 && SrcVT.isVector())
19242 // MMX <=> MMX conversions are Legal.
19243 if (SrcVT.isVector() && DstVT.isVector())
19245 // All other conversions need to be expanded.
19249 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19250 SelectionDAG &DAG) {
19251 SDNode *Node = Op.getNode();
19254 Op = Op.getOperand(0);
19255 EVT VT = Op.getValueType();
19256 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19257 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19259 unsigned NumElts = VT.getVectorNumElements();
19260 EVT EltVT = VT.getVectorElementType();
19261 unsigned Len = EltVT.getSizeInBits();
19263 // This is the vectorized version of the "best" algorithm from
19264 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19265 // with a minor tweak to use a series of adds + shifts instead of vector
19266 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19268 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19269 // v8i32 => Always profitable
19271 // FIXME: There a couple of possible improvements:
19273 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19274 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19276 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19277 "CTPOP not implemented for this vector element type.");
19279 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19280 // extra legalization.
19281 bool NeedsBitcast = EltVT == MVT::i32;
19282 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19284 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19285 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19286 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19288 // v = v - ((v >> 1) & 0x55555555...)
19289 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19290 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19291 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19293 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19295 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19296 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19298 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19300 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19301 if (VT != And.getValueType())
19302 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19303 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19305 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19306 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19307 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19308 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19309 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19311 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19312 if (NeedsBitcast) {
19313 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19314 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19315 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19318 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19319 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19320 if (VT != AndRHS.getValueType()) {
19321 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19322 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19324 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19326 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19327 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19328 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19329 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19330 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19332 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19333 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19334 if (NeedsBitcast) {
19335 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19336 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19338 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19339 if (VT != And.getValueType())
19340 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19342 // The algorithm mentioned above uses:
19343 // v = (v * 0x01010101...) >> (Len - 8)
19345 // Change it to use vector adds + vector shifts which yield faster results on
19346 // Haswell than using vector integer multiplication.
19348 // For i32 elements:
19349 // v = v + (v >> 8)
19350 // v = v + (v >> 16)
19352 // For i64 elements:
19353 // v = v + (v >> 8)
19354 // v = v + (v >> 16)
19355 // v = v + (v >> 32)
19358 SmallVector<SDValue, 8> Csts;
19359 for (unsigned i = 8; i <= Len/2; i *= 2) {
19360 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19361 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19362 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19363 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19367 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19368 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19369 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19370 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19371 if (NeedsBitcast) {
19372 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19373 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19375 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19376 if (VT != And.getValueType())
19377 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19382 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19383 SDNode *Node = Op.getNode();
19385 EVT T = Node->getValueType(0);
19386 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19387 DAG.getConstant(0, T), Node->getOperand(2));
19388 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19389 cast<AtomicSDNode>(Node)->getMemoryVT(),
19390 Node->getOperand(0),
19391 Node->getOperand(1), negOp,
19392 cast<AtomicSDNode>(Node)->getMemOperand(),
19393 cast<AtomicSDNode>(Node)->getOrdering(),
19394 cast<AtomicSDNode>(Node)->getSynchScope());
19397 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19398 SDNode *Node = Op.getNode();
19400 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19402 // Convert seq_cst store -> xchg
19403 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19404 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19405 // (The only way to get a 16-byte store is cmpxchg16b)
19406 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19407 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19408 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19409 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19410 cast<AtomicSDNode>(Node)->getMemoryVT(),
19411 Node->getOperand(0),
19412 Node->getOperand(1), Node->getOperand(2),
19413 cast<AtomicSDNode>(Node)->getMemOperand(),
19414 cast<AtomicSDNode>(Node)->getOrdering(),
19415 cast<AtomicSDNode>(Node)->getSynchScope());
19416 return Swap.getValue(1);
19418 // Other atomic stores have a simple pattern.
19422 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19423 EVT VT = Op.getNode()->getSimpleValueType(0);
19425 // Let legalize expand this if it isn't a legal type yet.
19426 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19429 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19432 bool ExtraOp = false;
19433 switch (Op.getOpcode()) {
19434 default: llvm_unreachable("Invalid code");
19435 case ISD::ADDC: Opc = X86ISD::ADD; break;
19436 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19437 case ISD::SUBC: Opc = X86ISD::SUB; break;
19438 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19442 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19444 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19445 Op.getOperand(1), Op.getOperand(2));
19448 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19449 SelectionDAG &DAG) {
19450 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19452 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19453 // which returns the values as { float, float } (in XMM0) or
19454 // { double, double } (which is returned in XMM0, XMM1).
19456 SDValue Arg = Op.getOperand(0);
19457 EVT ArgVT = Arg.getValueType();
19458 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19460 TargetLowering::ArgListTy Args;
19461 TargetLowering::ArgListEntry Entry;
19465 Entry.isSExt = false;
19466 Entry.isZExt = false;
19467 Args.push_back(Entry);
19469 bool isF64 = ArgVT == MVT::f64;
19470 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19471 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19472 // the results are returned via SRet in memory.
19473 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19475 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19477 Type *RetTy = isF64
19478 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19479 : (Type*)VectorType::get(ArgTy, 4);
19481 TargetLowering::CallLoweringInfo CLI(DAG);
19482 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19483 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19485 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19488 // Returned in xmm0 and xmm1.
19489 return CallResult.first;
19491 // Returned in bits 0:31 and 32:64 xmm0.
19492 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19493 CallResult.first, DAG.getIntPtrConstant(0));
19494 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19495 CallResult.first, DAG.getIntPtrConstant(1));
19496 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19497 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19500 /// LowerOperation - Provide custom lowering hooks for some operations.
19502 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19503 switch (Op.getOpcode()) {
19504 default: llvm_unreachable("Should not custom lower this!");
19505 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19506 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19507 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19508 return LowerCMP_SWAP(Op, Subtarget, DAG);
19509 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19510 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19511 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19512 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19513 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19514 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19515 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19516 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19517 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19518 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19519 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19520 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19521 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19522 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19523 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19524 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19525 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19526 case ISD::SHL_PARTS:
19527 case ISD::SRA_PARTS:
19528 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19529 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19530 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19531 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19532 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19533 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19534 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19535 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19536 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19537 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19538 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19540 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19541 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19542 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19543 case ISD::SETCC: return LowerSETCC(Op, DAG);
19544 case ISD::SELECT: return LowerSELECT(Op, DAG);
19545 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19546 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19547 case ISD::VASTART: return LowerVASTART(Op, DAG);
19548 case ISD::VAARG: return LowerVAARG(Op, DAG);
19549 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19550 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19551 case ISD::INTRINSIC_VOID:
19552 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19553 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19554 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19555 case ISD::FRAME_TO_ARGS_OFFSET:
19556 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19557 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19558 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19559 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19560 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19561 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19562 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19563 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19564 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19565 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19566 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19567 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19568 case ISD::UMUL_LOHI:
19569 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19572 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19578 case ISD::UMULO: return LowerXALUO(Op, DAG);
19579 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19580 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19584 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19585 case ISD::ADD: return LowerADD(Op, DAG);
19586 case ISD::SUB: return LowerSUB(Op, DAG);
19587 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19591 /// ReplaceNodeResults - Replace a node with an illegal result type
19592 /// with a new node built out of custom code.
19593 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19594 SmallVectorImpl<SDValue>&Results,
19595 SelectionDAG &DAG) const {
19597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19598 switch (N->getOpcode()) {
19600 llvm_unreachable("Do not know how to custom type legalize this operation!");
19601 case ISD::SIGN_EXTEND_INREG:
19606 // We don't want to expand or promote these.
19613 case ISD::UDIVREM: {
19614 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19615 Results.push_back(V);
19618 case ISD::FP_TO_SINT:
19619 case ISD::FP_TO_UINT: {
19620 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19622 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19625 std::pair<SDValue,SDValue> Vals =
19626 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19627 SDValue FIST = Vals.first, StackSlot = Vals.second;
19628 if (FIST.getNode()) {
19629 EVT VT = N->getValueType(0);
19630 // Return a load from the stack slot.
19631 if (StackSlot.getNode())
19632 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19633 MachinePointerInfo(),
19634 false, false, false, 0));
19636 Results.push_back(FIST);
19640 case ISD::UINT_TO_FP: {
19641 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19642 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19643 N->getValueType(0) != MVT::v2f32)
19645 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19647 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19649 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19650 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19651 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19652 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19653 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19654 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19657 case ISD::FP_ROUND: {
19658 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19660 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19661 Results.push_back(V);
19664 case ISD::INTRINSIC_W_CHAIN: {
19665 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19667 default : llvm_unreachable("Do not know how to custom type "
19668 "legalize this intrinsic operation!");
19669 case Intrinsic::x86_rdtsc:
19670 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19672 case Intrinsic::x86_rdtscp:
19673 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19675 case Intrinsic::x86_rdpmc:
19676 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19679 case ISD::READCYCLECOUNTER: {
19680 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19683 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19684 EVT T = N->getValueType(0);
19685 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19686 bool Regs64bit = T == MVT::i128;
19687 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19688 SDValue cpInL, cpInH;
19689 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19690 DAG.getConstant(0, HalfT));
19691 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19692 DAG.getConstant(1, HalfT));
19693 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19694 Regs64bit ? X86::RAX : X86::EAX,
19696 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19697 Regs64bit ? X86::RDX : X86::EDX,
19698 cpInH, cpInL.getValue(1));
19699 SDValue swapInL, swapInH;
19700 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19701 DAG.getConstant(0, HalfT));
19702 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19703 DAG.getConstant(1, HalfT));
19704 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19705 Regs64bit ? X86::RBX : X86::EBX,
19706 swapInL, cpInH.getValue(1));
19707 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19708 Regs64bit ? X86::RCX : X86::ECX,
19709 swapInH, swapInL.getValue(1));
19710 SDValue Ops[] = { swapInH.getValue(0),
19712 swapInH.getValue(1) };
19713 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19714 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19715 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19716 X86ISD::LCMPXCHG8_DAG;
19717 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19718 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19719 Regs64bit ? X86::RAX : X86::EAX,
19720 HalfT, Result.getValue(1));
19721 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19722 Regs64bit ? X86::RDX : X86::EDX,
19723 HalfT, cpOutL.getValue(2));
19724 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19726 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19727 MVT::i32, cpOutH.getValue(2));
19729 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19730 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19731 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19733 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19734 Results.push_back(Success);
19735 Results.push_back(EFLAGS.getValue(1));
19738 case ISD::ATOMIC_SWAP:
19739 case ISD::ATOMIC_LOAD_ADD:
19740 case ISD::ATOMIC_LOAD_SUB:
19741 case ISD::ATOMIC_LOAD_AND:
19742 case ISD::ATOMIC_LOAD_OR:
19743 case ISD::ATOMIC_LOAD_XOR:
19744 case ISD::ATOMIC_LOAD_NAND:
19745 case ISD::ATOMIC_LOAD_MIN:
19746 case ISD::ATOMIC_LOAD_MAX:
19747 case ISD::ATOMIC_LOAD_UMIN:
19748 case ISD::ATOMIC_LOAD_UMAX:
19749 case ISD::ATOMIC_LOAD: {
19750 // Delegate to generic TypeLegalization. Situations we can really handle
19751 // should have already been dealt with by AtomicExpandPass.cpp.
19754 case ISD::BITCAST: {
19755 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19756 EVT DstVT = N->getValueType(0);
19757 EVT SrcVT = N->getOperand(0)->getValueType(0);
19759 if (SrcVT != MVT::f64 ||
19760 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19763 unsigned NumElts = DstVT.getVectorNumElements();
19764 EVT SVT = DstVT.getVectorElementType();
19765 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19766 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19767 MVT::v2f64, N->getOperand(0));
19768 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19770 if (ExperimentalVectorWideningLegalization) {
19771 // If we are legalizing vectors by widening, we already have the desired
19772 // legal vector type, just return it.
19773 Results.push_back(ToVecInt);
19777 SmallVector<SDValue, 8> Elts;
19778 for (unsigned i = 0, e = NumElts; i != e; ++i)
19779 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19780 ToVecInt, DAG.getIntPtrConstant(i)));
19782 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19787 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19789 default: return nullptr;
19790 case X86ISD::BSF: return "X86ISD::BSF";
19791 case X86ISD::BSR: return "X86ISD::BSR";
19792 case X86ISD::SHLD: return "X86ISD::SHLD";
19793 case X86ISD::SHRD: return "X86ISD::SHRD";
19794 case X86ISD::FAND: return "X86ISD::FAND";
19795 case X86ISD::FANDN: return "X86ISD::FANDN";
19796 case X86ISD::FOR: return "X86ISD::FOR";
19797 case X86ISD::FXOR: return "X86ISD::FXOR";
19798 case X86ISD::FSRL: return "X86ISD::FSRL";
19799 case X86ISD::FILD: return "X86ISD::FILD";
19800 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19801 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19802 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19803 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19804 case X86ISD::FLD: return "X86ISD::FLD";
19805 case X86ISD::FST: return "X86ISD::FST";
19806 case X86ISD::CALL: return "X86ISD::CALL";
19807 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19808 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19809 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19810 case X86ISD::BT: return "X86ISD::BT";
19811 case X86ISD::CMP: return "X86ISD::CMP";
19812 case X86ISD::COMI: return "X86ISD::COMI";
19813 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19814 case X86ISD::CMPM: return "X86ISD::CMPM";
19815 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19816 case X86ISD::SETCC: return "X86ISD::SETCC";
19817 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19818 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19819 case X86ISD::CMOV: return "X86ISD::CMOV";
19820 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19821 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19822 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19823 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19824 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19825 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19826 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19827 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19828 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19829 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19830 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19831 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19832 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19833 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19834 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19835 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19836 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19837 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19838 case X86ISD::HADD: return "X86ISD::HADD";
19839 case X86ISD::HSUB: return "X86ISD::HSUB";
19840 case X86ISD::FHADD: return "X86ISD::FHADD";
19841 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19842 case X86ISD::UMAX: return "X86ISD::UMAX";
19843 case X86ISD::UMIN: return "X86ISD::UMIN";
19844 case X86ISD::SMAX: return "X86ISD::SMAX";
19845 case X86ISD::SMIN: return "X86ISD::SMIN";
19846 case X86ISD::FMAX: return "X86ISD::FMAX";
19847 case X86ISD::FMIN: return "X86ISD::FMIN";
19848 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19849 case X86ISD::FMINC: return "X86ISD::FMINC";
19850 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19851 case X86ISD::FRCP: return "X86ISD::FRCP";
19852 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19853 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19854 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19855 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19856 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19857 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19858 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19859 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19860 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19861 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19862 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19863 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19864 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19865 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19866 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19867 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19868 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19869 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19870 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19871 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19872 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19873 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19874 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19875 case X86ISD::VSHL: return "X86ISD::VSHL";
19876 case X86ISD::VSRL: return "X86ISD::VSRL";
19877 case X86ISD::VSRA: return "X86ISD::VSRA";
19878 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19879 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19880 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19881 case X86ISD::CMPP: return "X86ISD::CMPP";
19882 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19883 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19884 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19885 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19886 case X86ISD::ADD: return "X86ISD::ADD";
19887 case X86ISD::SUB: return "X86ISD::SUB";
19888 case X86ISD::ADC: return "X86ISD::ADC";
19889 case X86ISD::SBB: return "X86ISD::SBB";
19890 case X86ISD::SMUL: return "X86ISD::SMUL";
19891 case X86ISD::UMUL: return "X86ISD::UMUL";
19892 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19893 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19894 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19895 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19896 case X86ISD::INC: return "X86ISD::INC";
19897 case X86ISD::DEC: return "X86ISD::DEC";
19898 case X86ISD::OR: return "X86ISD::OR";
19899 case X86ISD::XOR: return "X86ISD::XOR";
19900 case X86ISD::AND: return "X86ISD::AND";
19901 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19902 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19903 case X86ISD::PTEST: return "X86ISD::PTEST";
19904 case X86ISD::TESTP: return "X86ISD::TESTP";
19905 case X86ISD::TESTM: return "X86ISD::TESTM";
19906 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19907 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19908 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19909 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19910 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19911 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19912 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19913 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19914 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19915 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19916 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19917 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19918 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19919 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19920 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19921 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19922 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19923 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19924 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19925 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19926 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19927 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19928 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19929 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19930 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19931 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19932 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19933 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19934 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19935 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19936 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19937 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19938 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19939 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19940 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19941 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19942 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19943 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19944 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19945 case X86ISD::SAHF: return "X86ISD::SAHF";
19946 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19947 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19948 case X86ISD::FMADD: return "X86ISD::FMADD";
19949 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19950 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19951 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19952 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19953 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19954 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19955 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19956 case X86ISD::XTEST: return "X86ISD::XTEST";
19957 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19958 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19959 case X86ISD::SELECT: return "X86ISD::SELECT";
19963 // isLegalAddressingMode - Return true if the addressing mode represented
19964 // by AM is legal for this target, for a load/store of the specified type.
19965 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19967 // X86 supports extremely general addressing modes.
19968 CodeModel::Model M = getTargetMachine().getCodeModel();
19969 Reloc::Model R = getTargetMachine().getRelocationModel();
19971 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19972 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19977 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19979 // If a reference to this global requires an extra load, we can't fold it.
19980 if (isGlobalStubReference(GVFlags))
19983 // If BaseGV requires a register for the PIC base, we cannot also have a
19984 // BaseReg specified.
19985 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19988 // If lower 4G is not available, then we must use rip-relative addressing.
19989 if ((M != CodeModel::Small || R != Reloc::Static) &&
19990 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19994 switch (AM.Scale) {
20000 // These scales always work.
20005 // These scales are formed with basereg+scalereg. Only accept if there is
20010 default: // Other stuff never works.
20017 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20018 unsigned Bits = Ty->getScalarSizeInBits();
20020 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20021 // particularly cheaper than those without.
20025 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20026 // variable shifts just as cheap as scalar ones.
20027 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20030 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20031 // fully general vector.
20035 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20036 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20038 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20039 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20040 return NumBits1 > NumBits2;
20043 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20044 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20047 if (!isTypeLegal(EVT::getEVT(Ty1)))
20050 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20052 // Assuming the caller doesn't have a zeroext or signext return parameter,
20053 // truncation all the way down to i1 is valid.
20057 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20058 return isInt<32>(Imm);
20061 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20062 // Can also use sub to handle negated immediates.
20063 return isInt<32>(Imm);
20066 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20067 if (!VT1.isInteger() || !VT2.isInteger())
20069 unsigned NumBits1 = VT1.getSizeInBits();
20070 unsigned NumBits2 = VT2.getSizeInBits();
20071 return NumBits1 > NumBits2;
20074 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20075 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20076 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20079 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20080 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20081 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20084 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20085 EVT VT1 = Val.getValueType();
20086 if (isZExtFree(VT1, VT2))
20089 if (Val.getOpcode() != ISD::LOAD)
20092 if (!VT1.isSimple() || !VT1.isInteger() ||
20093 !VT2.isSimple() || !VT2.isInteger())
20096 switch (VT1.getSimpleVT().SimpleTy) {
20101 // X86 has 8, 16, and 32-bit zero-extending loads.
20109 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20110 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20113 VT = VT.getScalarType();
20115 if (!VT.isSimple())
20118 switch (VT.getSimpleVT().SimpleTy) {
20129 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20130 // i16 instructions are longer (0x66 prefix) and potentially slower.
20131 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20134 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20135 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20136 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20137 /// are assumed to be legal.
20139 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20141 if (!VT.isSimple())
20144 MVT SVT = VT.getSimpleVT();
20146 // Very little shuffling can be done for 64-bit vectors right now.
20147 if (VT.getSizeInBits() == 64)
20150 // If this is a single-input shuffle with no 128 bit lane crossings we can
20151 // lower it into pshufb.
20152 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20153 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20154 bool isLegal = true;
20155 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20156 if (M[I] >= (int)SVT.getVectorNumElements() ||
20157 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20166 // FIXME: blends, shifts.
20167 return (SVT.getVectorNumElements() == 2 ||
20168 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20169 isMOVLMask(M, SVT) ||
20170 isCommutedMOVLMask(M, SVT) ||
20171 isMOVHLPSMask(M, SVT) ||
20172 isSHUFPMask(M, SVT) ||
20173 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20174 isPSHUFDMask(M, SVT) ||
20175 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20176 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20177 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20178 isPALIGNRMask(M, SVT, Subtarget) ||
20179 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20180 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20181 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20182 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20183 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20184 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20188 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20190 if (!VT.isSimple())
20193 MVT SVT = VT.getSimpleVT();
20194 unsigned NumElts = SVT.getVectorNumElements();
20195 // FIXME: This collection of masks seems suspect.
20198 if (NumElts == 4 && SVT.is128BitVector()) {
20199 return (isMOVLMask(Mask, SVT) ||
20200 isCommutedMOVLMask(Mask, SVT, true) ||
20201 isSHUFPMask(Mask, SVT) ||
20202 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20203 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20204 Subtarget->hasInt256()));
20209 //===----------------------------------------------------------------------===//
20210 // X86 Scheduler Hooks
20211 //===----------------------------------------------------------------------===//
20213 /// Utility function to emit xbegin specifying the start of an RTM region.
20214 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20215 const TargetInstrInfo *TII) {
20216 DebugLoc DL = MI->getDebugLoc();
20218 const BasicBlock *BB = MBB->getBasicBlock();
20219 MachineFunction::iterator I = MBB;
20222 // For the v = xbegin(), we generate
20233 MachineBasicBlock *thisMBB = MBB;
20234 MachineFunction *MF = MBB->getParent();
20235 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20236 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20237 MF->insert(I, mainMBB);
20238 MF->insert(I, sinkMBB);
20240 // Transfer the remainder of BB and its successor edges to sinkMBB.
20241 sinkMBB->splice(sinkMBB->begin(), MBB,
20242 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20243 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20247 // # fallthrough to mainMBB
20248 // # abortion to sinkMBB
20249 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20250 thisMBB->addSuccessor(mainMBB);
20251 thisMBB->addSuccessor(sinkMBB);
20255 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20256 mainMBB->addSuccessor(sinkMBB);
20259 // EAX is live into the sinkMBB
20260 sinkMBB->addLiveIn(X86::EAX);
20261 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20262 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20265 MI->eraseFromParent();
20269 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20270 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20271 // in the .td file.
20272 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20273 const TargetInstrInfo *TII) {
20275 switch (MI->getOpcode()) {
20276 default: llvm_unreachable("illegal opcode!");
20277 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20278 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20279 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20280 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20281 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20282 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20283 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20284 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20287 DebugLoc dl = MI->getDebugLoc();
20288 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20290 unsigned NumArgs = MI->getNumOperands();
20291 for (unsigned i = 1; i < NumArgs; ++i) {
20292 MachineOperand &Op = MI->getOperand(i);
20293 if (!(Op.isReg() && Op.isImplicit()))
20294 MIB.addOperand(Op);
20296 if (MI->hasOneMemOperand())
20297 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20299 BuildMI(*BB, MI, dl,
20300 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20301 .addReg(X86::XMM0);
20303 MI->eraseFromParent();
20307 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20308 // defs in an instruction pattern
20309 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20310 const TargetInstrInfo *TII) {
20312 switch (MI->getOpcode()) {
20313 default: llvm_unreachable("illegal opcode!");
20314 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20315 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20316 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20317 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20318 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20319 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20320 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20321 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20324 DebugLoc dl = MI->getDebugLoc();
20325 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20327 unsigned NumArgs = MI->getNumOperands(); // remove the results
20328 for (unsigned i = 1; i < NumArgs; ++i) {
20329 MachineOperand &Op = MI->getOperand(i);
20330 if (!(Op.isReg() && Op.isImplicit()))
20331 MIB.addOperand(Op);
20333 if (MI->hasOneMemOperand())
20334 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20336 BuildMI(*BB, MI, dl,
20337 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20340 MI->eraseFromParent();
20344 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20345 const TargetInstrInfo *TII,
20346 const X86Subtarget* Subtarget) {
20347 DebugLoc dl = MI->getDebugLoc();
20349 // Address into RAX/EAX, other two args into ECX, EDX.
20350 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20351 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20352 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20353 for (int i = 0; i < X86::AddrNumOperands; ++i)
20354 MIB.addOperand(MI->getOperand(i));
20356 unsigned ValOps = X86::AddrNumOperands;
20357 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20358 .addReg(MI->getOperand(ValOps).getReg());
20359 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20360 .addReg(MI->getOperand(ValOps+1).getReg());
20362 // The instruction doesn't actually take any operands though.
20363 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20365 MI->eraseFromParent(); // The pseudo is gone now.
20369 MachineBasicBlock *
20370 X86TargetLowering::EmitVAARG64WithCustomInserter(
20372 MachineBasicBlock *MBB) const {
20373 // Emit va_arg instruction on X86-64.
20375 // Operands to this pseudo-instruction:
20376 // 0 ) Output : destination address (reg)
20377 // 1-5) Input : va_list address (addr, i64mem)
20378 // 6 ) ArgSize : Size (in bytes) of vararg type
20379 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20380 // 8 ) Align : Alignment of type
20381 // 9 ) EFLAGS (implicit-def)
20383 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20384 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20386 unsigned DestReg = MI->getOperand(0).getReg();
20387 MachineOperand &Base = MI->getOperand(1);
20388 MachineOperand &Scale = MI->getOperand(2);
20389 MachineOperand &Index = MI->getOperand(3);
20390 MachineOperand &Disp = MI->getOperand(4);
20391 MachineOperand &Segment = MI->getOperand(5);
20392 unsigned ArgSize = MI->getOperand(6).getImm();
20393 unsigned ArgMode = MI->getOperand(7).getImm();
20394 unsigned Align = MI->getOperand(8).getImm();
20396 // Memory Reference
20397 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20398 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20399 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20401 // Machine Information
20402 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20403 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20404 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20405 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20406 DebugLoc DL = MI->getDebugLoc();
20408 // struct va_list {
20411 // i64 overflow_area (address)
20412 // i64 reg_save_area (address)
20414 // sizeof(va_list) = 24
20415 // alignment(va_list) = 8
20417 unsigned TotalNumIntRegs = 6;
20418 unsigned TotalNumXMMRegs = 8;
20419 bool UseGPOffset = (ArgMode == 1);
20420 bool UseFPOffset = (ArgMode == 2);
20421 unsigned MaxOffset = TotalNumIntRegs * 8 +
20422 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20424 /* Align ArgSize to a multiple of 8 */
20425 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20426 bool NeedsAlign = (Align > 8);
20428 MachineBasicBlock *thisMBB = MBB;
20429 MachineBasicBlock *overflowMBB;
20430 MachineBasicBlock *offsetMBB;
20431 MachineBasicBlock *endMBB;
20433 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20434 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20435 unsigned OffsetReg = 0;
20437 if (!UseGPOffset && !UseFPOffset) {
20438 // If we only pull from the overflow region, we don't create a branch.
20439 // We don't need to alter control flow.
20440 OffsetDestReg = 0; // unused
20441 OverflowDestReg = DestReg;
20443 offsetMBB = nullptr;
20444 overflowMBB = thisMBB;
20447 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20448 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20449 // If not, pull from overflow_area. (branch to overflowMBB)
20454 // offsetMBB overflowMBB
20459 // Registers for the PHI in endMBB
20460 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20461 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20463 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20464 MachineFunction *MF = MBB->getParent();
20465 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20466 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20467 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20469 MachineFunction::iterator MBBIter = MBB;
20472 // Insert the new basic blocks
20473 MF->insert(MBBIter, offsetMBB);
20474 MF->insert(MBBIter, overflowMBB);
20475 MF->insert(MBBIter, endMBB);
20477 // Transfer the remainder of MBB and its successor edges to endMBB.
20478 endMBB->splice(endMBB->begin(), thisMBB,
20479 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20480 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20482 // Make offsetMBB and overflowMBB successors of thisMBB
20483 thisMBB->addSuccessor(offsetMBB);
20484 thisMBB->addSuccessor(overflowMBB);
20486 // endMBB is a successor of both offsetMBB and overflowMBB
20487 offsetMBB->addSuccessor(endMBB);
20488 overflowMBB->addSuccessor(endMBB);
20490 // Load the offset value into a register
20491 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20492 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20496 .addDisp(Disp, UseFPOffset ? 4 : 0)
20497 .addOperand(Segment)
20498 .setMemRefs(MMOBegin, MMOEnd);
20500 // Check if there is enough room left to pull this argument.
20501 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20503 .addImm(MaxOffset + 8 - ArgSizeA8);
20505 // Branch to "overflowMBB" if offset >= max
20506 // Fall through to "offsetMBB" otherwise
20507 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20508 .addMBB(overflowMBB);
20511 // In offsetMBB, emit code to use the reg_save_area.
20513 assert(OffsetReg != 0);
20515 // Read the reg_save_area address.
20516 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20517 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20522 .addOperand(Segment)
20523 .setMemRefs(MMOBegin, MMOEnd);
20525 // Zero-extend the offset
20526 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20527 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20530 .addImm(X86::sub_32bit);
20532 // Add the offset to the reg_save_area to get the final address.
20533 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20534 .addReg(OffsetReg64)
20535 .addReg(RegSaveReg);
20537 // Compute the offset for the next argument
20538 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20539 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20541 .addImm(UseFPOffset ? 16 : 8);
20543 // Store it back into the va_list.
20544 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20548 .addDisp(Disp, UseFPOffset ? 4 : 0)
20549 .addOperand(Segment)
20550 .addReg(NextOffsetReg)
20551 .setMemRefs(MMOBegin, MMOEnd);
20554 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20559 // Emit code to use overflow area
20562 // Load the overflow_area address into a register.
20563 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20564 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20569 .addOperand(Segment)
20570 .setMemRefs(MMOBegin, MMOEnd);
20572 // If we need to align it, do so. Otherwise, just copy the address
20573 // to OverflowDestReg.
20575 // Align the overflow address
20576 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20577 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20579 // aligned_addr = (addr + (align-1)) & ~(align-1)
20580 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20581 .addReg(OverflowAddrReg)
20584 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20586 .addImm(~(uint64_t)(Align-1));
20588 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20589 .addReg(OverflowAddrReg);
20592 // Compute the next overflow address after this argument.
20593 // (the overflow address should be kept 8-byte aligned)
20594 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20595 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20596 .addReg(OverflowDestReg)
20597 .addImm(ArgSizeA8);
20599 // Store the new overflow address.
20600 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20605 .addOperand(Segment)
20606 .addReg(NextAddrReg)
20607 .setMemRefs(MMOBegin, MMOEnd);
20609 // If we branched, emit the PHI to the front of endMBB.
20611 BuildMI(*endMBB, endMBB->begin(), DL,
20612 TII->get(X86::PHI), DestReg)
20613 .addReg(OffsetDestReg).addMBB(offsetMBB)
20614 .addReg(OverflowDestReg).addMBB(overflowMBB);
20617 // Erase the pseudo instruction
20618 MI->eraseFromParent();
20623 MachineBasicBlock *
20624 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20626 MachineBasicBlock *MBB) const {
20627 // Emit code to save XMM registers to the stack. The ABI says that the
20628 // number of registers to save is given in %al, so it's theoretically
20629 // possible to do an indirect jump trick to avoid saving all of them,
20630 // however this code takes a simpler approach and just executes all
20631 // of the stores if %al is non-zero. It's less code, and it's probably
20632 // easier on the hardware branch predictor, and stores aren't all that
20633 // expensive anyway.
20635 // Create the new basic blocks. One block contains all the XMM stores,
20636 // and one block is the final destination regardless of whether any
20637 // stores were performed.
20638 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20639 MachineFunction *F = MBB->getParent();
20640 MachineFunction::iterator MBBIter = MBB;
20642 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20643 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20644 F->insert(MBBIter, XMMSaveMBB);
20645 F->insert(MBBIter, EndMBB);
20647 // Transfer the remainder of MBB and its successor edges to EndMBB.
20648 EndMBB->splice(EndMBB->begin(), MBB,
20649 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20650 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20652 // The original block will now fall through to the XMM save block.
20653 MBB->addSuccessor(XMMSaveMBB);
20654 // The XMMSaveMBB will fall through to the end block.
20655 XMMSaveMBB->addSuccessor(EndMBB);
20657 // Now add the instructions.
20658 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20659 DebugLoc DL = MI->getDebugLoc();
20661 unsigned CountReg = MI->getOperand(0).getReg();
20662 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20663 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20665 if (!Subtarget->isTargetWin64()) {
20666 // If %al is 0, branch around the XMM save block.
20667 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20668 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20669 MBB->addSuccessor(EndMBB);
20672 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20673 // that was just emitted, but clearly shouldn't be "saved".
20674 assert((MI->getNumOperands() <= 3 ||
20675 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20676 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20677 && "Expected last argument to be EFLAGS");
20678 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20679 // In the XMM save block, save all the XMM argument registers.
20680 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20681 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20682 MachineMemOperand *MMO =
20683 F->getMachineMemOperand(
20684 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20685 MachineMemOperand::MOStore,
20686 /*Size=*/16, /*Align=*/16);
20687 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20688 .addFrameIndex(RegSaveFrameIndex)
20689 .addImm(/*Scale=*/1)
20690 .addReg(/*IndexReg=*/0)
20691 .addImm(/*Disp=*/Offset)
20692 .addReg(/*Segment=*/0)
20693 .addReg(MI->getOperand(i).getReg())
20694 .addMemOperand(MMO);
20697 MI->eraseFromParent(); // The pseudo instruction is gone now.
20702 // The EFLAGS operand of SelectItr might be missing a kill marker
20703 // because there were multiple uses of EFLAGS, and ISel didn't know
20704 // which to mark. Figure out whether SelectItr should have had a
20705 // kill marker, and set it if it should. Returns the correct kill
20707 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20708 MachineBasicBlock* BB,
20709 const TargetRegisterInfo* TRI) {
20710 // Scan forward through BB for a use/def of EFLAGS.
20711 MachineBasicBlock::iterator miI(std::next(SelectItr));
20712 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20713 const MachineInstr& mi = *miI;
20714 if (mi.readsRegister(X86::EFLAGS))
20716 if (mi.definesRegister(X86::EFLAGS))
20717 break; // Should have kill-flag - update below.
20720 // If we hit the end of the block, check whether EFLAGS is live into a
20722 if (miI == BB->end()) {
20723 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20724 sEnd = BB->succ_end();
20725 sItr != sEnd; ++sItr) {
20726 MachineBasicBlock* succ = *sItr;
20727 if (succ->isLiveIn(X86::EFLAGS))
20732 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20733 // out. SelectMI should have a kill flag on EFLAGS.
20734 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20738 MachineBasicBlock *
20739 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20740 MachineBasicBlock *BB) const {
20741 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20742 DebugLoc DL = MI->getDebugLoc();
20744 // To "insert" a SELECT_CC instruction, we actually have to insert the
20745 // diamond control-flow pattern. The incoming instruction knows the
20746 // destination vreg to set, the condition code register to branch on, the
20747 // true/false values to select between, and a branch opcode to use.
20748 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20749 MachineFunction::iterator It = BB;
20755 // cmpTY ccX, r1, r2
20757 // fallthrough --> copy0MBB
20758 MachineBasicBlock *thisMBB = BB;
20759 MachineFunction *F = BB->getParent();
20760 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20761 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20762 F->insert(It, copy0MBB);
20763 F->insert(It, sinkMBB);
20765 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20766 // live into the sink and copy blocks.
20767 const TargetRegisterInfo *TRI =
20768 BB->getParent()->getSubtarget().getRegisterInfo();
20769 if (!MI->killsRegister(X86::EFLAGS) &&
20770 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20771 copy0MBB->addLiveIn(X86::EFLAGS);
20772 sinkMBB->addLiveIn(X86::EFLAGS);
20775 // Transfer the remainder of BB and its successor edges to sinkMBB.
20776 sinkMBB->splice(sinkMBB->begin(), BB,
20777 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20778 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20780 // Add the true and fallthrough blocks as its successors.
20781 BB->addSuccessor(copy0MBB);
20782 BB->addSuccessor(sinkMBB);
20784 // Create the conditional branch instruction.
20786 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20787 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20790 // %FalseValue = ...
20791 // # fallthrough to sinkMBB
20792 copy0MBB->addSuccessor(sinkMBB);
20795 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20797 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20798 TII->get(X86::PHI), MI->getOperand(0).getReg())
20799 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20800 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20802 MI->eraseFromParent(); // The pseudo instruction is gone now.
20806 MachineBasicBlock *
20807 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20808 MachineBasicBlock *BB) const {
20809 MachineFunction *MF = BB->getParent();
20810 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20811 DebugLoc DL = MI->getDebugLoc();
20812 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20814 assert(MF->shouldSplitStack());
20816 const bool Is64Bit = Subtarget->is64Bit();
20817 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20819 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20820 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20823 // ... [Till the alloca]
20824 // If stacklet is not large enough, jump to mallocMBB
20827 // Allocate by subtracting from RSP
20828 // Jump to continueMBB
20831 // Allocate by call to runtime
20835 // [rest of original BB]
20838 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20839 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20840 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20842 MachineRegisterInfo &MRI = MF->getRegInfo();
20843 const TargetRegisterClass *AddrRegClass =
20844 getRegClassFor(getPointerTy());
20846 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20847 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20848 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20849 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20850 sizeVReg = MI->getOperand(1).getReg(),
20851 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20853 MachineFunction::iterator MBBIter = BB;
20856 MF->insert(MBBIter, bumpMBB);
20857 MF->insert(MBBIter, mallocMBB);
20858 MF->insert(MBBIter, continueMBB);
20860 continueMBB->splice(continueMBB->begin(), BB,
20861 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20862 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20864 // Add code to the main basic block to check if the stack limit has been hit,
20865 // and if so, jump to mallocMBB otherwise to bumpMBB.
20866 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20867 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20868 .addReg(tmpSPVReg).addReg(sizeVReg);
20869 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20870 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20871 .addReg(SPLimitVReg);
20872 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20874 // bumpMBB simply decreases the stack pointer, since we know the current
20875 // stacklet has enough space.
20876 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20877 .addReg(SPLimitVReg);
20878 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20879 .addReg(SPLimitVReg);
20880 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20882 // Calls into a routine in libgcc to allocate more space from the heap.
20883 const uint32_t *RegMask = MF->getTarget()
20884 .getSubtargetImpl()
20885 ->getRegisterInfo()
20886 ->getCallPreservedMask(CallingConv::C);
20888 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20890 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20891 .addExternalSymbol("__morestack_allocate_stack_space")
20892 .addRegMask(RegMask)
20893 .addReg(X86::RDI, RegState::Implicit)
20894 .addReg(X86::RAX, RegState::ImplicitDefine);
20895 } else if (Is64Bit) {
20896 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20898 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20899 .addExternalSymbol("__morestack_allocate_stack_space")
20900 .addRegMask(RegMask)
20901 .addReg(X86::EDI, RegState::Implicit)
20902 .addReg(X86::EAX, RegState::ImplicitDefine);
20904 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20906 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20907 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20908 .addExternalSymbol("__morestack_allocate_stack_space")
20909 .addRegMask(RegMask)
20910 .addReg(X86::EAX, RegState::ImplicitDefine);
20914 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20917 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20918 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20919 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20921 // Set up the CFG correctly.
20922 BB->addSuccessor(bumpMBB);
20923 BB->addSuccessor(mallocMBB);
20924 mallocMBB->addSuccessor(continueMBB);
20925 bumpMBB->addSuccessor(continueMBB);
20927 // Take care of the PHI nodes.
20928 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20929 MI->getOperand(0).getReg())
20930 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20931 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20933 // Delete the original pseudo instruction.
20934 MI->eraseFromParent();
20937 return continueMBB;
20940 MachineBasicBlock *
20941 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20942 MachineBasicBlock *BB) const {
20943 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20944 DebugLoc DL = MI->getDebugLoc();
20946 assert(!Subtarget->isTargetMachO());
20948 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20949 // non-trivial part is impdef of ESP.
20951 if (Subtarget->isTargetWin64()) {
20952 if (Subtarget->isTargetCygMing()) {
20953 // ___chkstk(Mingw64):
20954 // Clobbers R10, R11, RAX and EFLAGS.
20956 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20957 .addExternalSymbol("___chkstk")
20958 .addReg(X86::RAX, RegState::Implicit)
20959 .addReg(X86::RSP, RegState::Implicit)
20960 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20961 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20962 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20964 // __chkstk(MSVCRT): does not update stack pointer.
20965 // Clobbers R10, R11 and EFLAGS.
20966 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20967 .addExternalSymbol("__chkstk")
20968 .addReg(X86::RAX, RegState::Implicit)
20969 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20970 // RAX has the offset to be subtracted from RSP.
20971 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20976 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20977 Subtarget->isTargetWindowsItanium())
20981 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20982 .addExternalSymbol(StackProbeSymbol)
20983 .addReg(X86::EAX, RegState::Implicit)
20984 .addReg(X86::ESP, RegState::Implicit)
20985 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20986 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20987 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20990 MI->eraseFromParent(); // The pseudo instruction is gone now.
20994 MachineBasicBlock *
20995 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20996 MachineBasicBlock *BB) const {
20997 // This is pretty easy. We're taking the value that we received from
20998 // our load from the relocation, sticking it in either RDI (x86-64)
20999 // or EAX and doing an indirect call. The return value will then
21000 // be in the normal return register.
21001 MachineFunction *F = BB->getParent();
21002 const X86InstrInfo *TII =
21003 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
21004 DebugLoc DL = MI->getDebugLoc();
21006 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21007 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21009 // Get a register mask for the lowered call.
21010 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21011 // proper register mask.
21012 const uint32_t *RegMask = F->getTarget()
21013 .getSubtargetImpl()
21014 ->getRegisterInfo()
21015 ->getCallPreservedMask(CallingConv::C);
21016 if (Subtarget->is64Bit()) {
21017 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21018 TII->get(X86::MOV64rm), X86::RDI)
21020 .addImm(0).addReg(0)
21021 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21022 MI->getOperand(3).getTargetFlags())
21024 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21025 addDirectMem(MIB, X86::RDI);
21026 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21027 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21028 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21029 TII->get(X86::MOV32rm), X86::EAX)
21031 .addImm(0).addReg(0)
21032 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21033 MI->getOperand(3).getTargetFlags())
21035 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21036 addDirectMem(MIB, X86::EAX);
21037 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21039 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21040 TII->get(X86::MOV32rm), X86::EAX)
21041 .addReg(TII->getGlobalBaseReg(F))
21042 .addImm(0).addReg(0)
21043 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21044 MI->getOperand(3).getTargetFlags())
21046 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21047 addDirectMem(MIB, X86::EAX);
21048 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21051 MI->eraseFromParent(); // The pseudo instruction is gone now.
21055 MachineBasicBlock *
21056 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21057 MachineBasicBlock *MBB) const {
21058 DebugLoc DL = MI->getDebugLoc();
21059 MachineFunction *MF = MBB->getParent();
21060 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21061 MachineRegisterInfo &MRI = MF->getRegInfo();
21063 const BasicBlock *BB = MBB->getBasicBlock();
21064 MachineFunction::iterator I = MBB;
21067 // Memory Reference
21068 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21069 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21072 unsigned MemOpndSlot = 0;
21074 unsigned CurOp = 0;
21076 DstReg = MI->getOperand(CurOp++).getReg();
21077 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21078 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21079 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21080 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21082 MemOpndSlot = CurOp;
21084 MVT PVT = getPointerTy();
21085 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21086 "Invalid Pointer Size!");
21088 // For v = setjmp(buf), we generate
21091 // buf[LabelOffset] = restoreMBB
21092 // SjLjSetup restoreMBB
21098 // v = phi(main, restore)
21101 // if base pointer being used, load it from frame
21104 MachineBasicBlock *thisMBB = MBB;
21105 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21106 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21107 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21108 MF->insert(I, mainMBB);
21109 MF->insert(I, sinkMBB);
21110 MF->push_back(restoreMBB);
21112 MachineInstrBuilder MIB;
21114 // Transfer the remainder of BB and its successor edges to sinkMBB.
21115 sinkMBB->splice(sinkMBB->begin(), MBB,
21116 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21117 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21120 unsigned PtrStoreOpc = 0;
21121 unsigned LabelReg = 0;
21122 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21123 Reloc::Model RM = MF->getTarget().getRelocationModel();
21124 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21125 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21127 // Prepare IP either in reg or imm.
21128 if (!UseImmLabel) {
21129 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21130 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21131 LabelReg = MRI.createVirtualRegister(PtrRC);
21132 if (Subtarget->is64Bit()) {
21133 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21137 .addMBB(restoreMBB)
21140 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21141 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21142 .addReg(XII->getGlobalBaseReg(MF))
21145 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21149 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21151 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21152 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21153 if (i == X86::AddrDisp)
21154 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21156 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21159 MIB.addReg(LabelReg);
21161 MIB.addMBB(restoreMBB);
21162 MIB.setMemRefs(MMOBegin, MMOEnd);
21164 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21165 .addMBB(restoreMBB);
21167 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21168 MF->getSubtarget().getRegisterInfo());
21169 MIB.addRegMask(RegInfo->getNoPreservedMask());
21170 thisMBB->addSuccessor(mainMBB);
21171 thisMBB->addSuccessor(restoreMBB);
21175 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21176 mainMBB->addSuccessor(sinkMBB);
21179 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21180 TII->get(X86::PHI), DstReg)
21181 .addReg(mainDstReg).addMBB(mainMBB)
21182 .addReg(restoreDstReg).addMBB(restoreMBB);
21185 if (RegInfo->hasBasePointer(*MF)) {
21186 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21187 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21188 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21189 X86FI->setRestoreBasePointer(MF);
21190 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21191 unsigned BasePtr = RegInfo->getBaseRegister();
21192 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21193 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21194 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21195 .setMIFlag(MachineInstr::FrameSetup);
21197 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21198 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21199 restoreMBB->addSuccessor(sinkMBB);
21201 MI->eraseFromParent();
21205 MachineBasicBlock *
21206 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21207 MachineBasicBlock *MBB) const {
21208 DebugLoc DL = MI->getDebugLoc();
21209 MachineFunction *MF = MBB->getParent();
21210 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21211 MachineRegisterInfo &MRI = MF->getRegInfo();
21213 // Memory Reference
21214 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21215 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21217 MVT PVT = getPointerTy();
21218 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21219 "Invalid Pointer Size!");
21221 const TargetRegisterClass *RC =
21222 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21223 unsigned Tmp = MRI.createVirtualRegister(RC);
21224 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21225 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21226 MF->getSubtarget().getRegisterInfo());
21227 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21228 unsigned SP = RegInfo->getStackRegister();
21230 MachineInstrBuilder MIB;
21232 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21233 const int64_t SPOffset = 2 * PVT.getStoreSize();
21235 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21236 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21239 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21240 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21241 MIB.addOperand(MI->getOperand(i));
21242 MIB.setMemRefs(MMOBegin, MMOEnd);
21244 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21245 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21246 if (i == X86::AddrDisp)
21247 MIB.addDisp(MI->getOperand(i), LabelOffset);
21249 MIB.addOperand(MI->getOperand(i));
21251 MIB.setMemRefs(MMOBegin, MMOEnd);
21253 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21254 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21255 if (i == X86::AddrDisp)
21256 MIB.addDisp(MI->getOperand(i), SPOffset);
21258 MIB.addOperand(MI->getOperand(i));
21260 MIB.setMemRefs(MMOBegin, MMOEnd);
21262 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21264 MI->eraseFromParent();
21268 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21269 // accumulator loops. Writing back to the accumulator allows the coalescer
21270 // to remove extra copies in the loop.
21271 MachineBasicBlock *
21272 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21273 MachineBasicBlock *MBB) const {
21274 MachineOperand &AddendOp = MI->getOperand(3);
21276 // Bail out early if the addend isn't a register - we can't switch these.
21277 if (!AddendOp.isReg())
21280 MachineFunction &MF = *MBB->getParent();
21281 MachineRegisterInfo &MRI = MF.getRegInfo();
21283 // Check whether the addend is defined by a PHI:
21284 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21285 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21286 if (!AddendDef.isPHI())
21289 // Look for the following pattern:
21291 // %addend = phi [%entry, 0], [%loop, %result]
21293 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21297 // %addend = phi [%entry, 0], [%loop, %result]
21299 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21301 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21302 assert(AddendDef.getOperand(i).isReg());
21303 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21304 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21305 if (&PHISrcInst == MI) {
21306 // Found a matching instruction.
21307 unsigned NewFMAOpc = 0;
21308 switch (MI->getOpcode()) {
21309 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21310 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21311 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21312 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21313 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21314 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21315 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21316 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21317 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21318 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21319 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21320 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21321 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21322 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21323 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21324 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21325 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21326 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21327 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21328 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21330 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21331 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21332 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21333 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21334 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21335 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21336 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21337 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21338 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21339 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21340 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21341 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21342 default: llvm_unreachable("Unrecognized FMA variant.");
21345 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21346 MachineInstrBuilder MIB =
21347 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21348 .addOperand(MI->getOperand(0))
21349 .addOperand(MI->getOperand(3))
21350 .addOperand(MI->getOperand(2))
21351 .addOperand(MI->getOperand(1));
21352 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21353 MI->eraseFromParent();
21360 MachineBasicBlock *
21361 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21362 MachineBasicBlock *BB) const {
21363 switch (MI->getOpcode()) {
21364 default: llvm_unreachable("Unexpected instr type to insert");
21365 case X86::TAILJMPd64:
21366 case X86::TAILJMPr64:
21367 case X86::TAILJMPm64:
21368 llvm_unreachable("TAILJMP64 would not be touched here.");
21369 case X86::TCRETURNdi64:
21370 case X86::TCRETURNri64:
21371 case X86::TCRETURNmi64:
21373 case X86::WIN_ALLOCA:
21374 return EmitLoweredWinAlloca(MI, BB);
21375 case X86::SEG_ALLOCA_32:
21376 case X86::SEG_ALLOCA_64:
21377 return EmitLoweredSegAlloca(MI, BB);
21378 case X86::TLSCall_32:
21379 case X86::TLSCall_64:
21380 return EmitLoweredTLSCall(MI, BB);
21381 case X86::CMOV_GR8:
21382 case X86::CMOV_FR32:
21383 case X86::CMOV_FR64:
21384 case X86::CMOV_V4F32:
21385 case X86::CMOV_V2F64:
21386 case X86::CMOV_V2I64:
21387 case X86::CMOV_V8F32:
21388 case X86::CMOV_V4F64:
21389 case X86::CMOV_V4I64:
21390 case X86::CMOV_V16F32:
21391 case X86::CMOV_V8F64:
21392 case X86::CMOV_V8I64:
21393 case X86::CMOV_GR16:
21394 case X86::CMOV_GR32:
21395 case X86::CMOV_RFP32:
21396 case X86::CMOV_RFP64:
21397 case X86::CMOV_RFP80:
21398 return EmitLoweredSelect(MI, BB);
21400 case X86::FP32_TO_INT16_IN_MEM:
21401 case X86::FP32_TO_INT32_IN_MEM:
21402 case X86::FP32_TO_INT64_IN_MEM:
21403 case X86::FP64_TO_INT16_IN_MEM:
21404 case X86::FP64_TO_INT32_IN_MEM:
21405 case X86::FP64_TO_INT64_IN_MEM:
21406 case X86::FP80_TO_INT16_IN_MEM:
21407 case X86::FP80_TO_INT32_IN_MEM:
21408 case X86::FP80_TO_INT64_IN_MEM: {
21409 MachineFunction *F = BB->getParent();
21410 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21411 DebugLoc DL = MI->getDebugLoc();
21413 // Change the floating point control register to use "round towards zero"
21414 // mode when truncating to an integer value.
21415 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21416 addFrameReference(BuildMI(*BB, MI, DL,
21417 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21419 // Load the old value of the high byte of the control word...
21421 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21422 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21425 // Set the high part to be round to zero...
21426 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21429 // Reload the modified control word now...
21430 addFrameReference(BuildMI(*BB, MI, DL,
21431 TII->get(X86::FLDCW16m)), CWFrameIdx);
21433 // Restore the memory image of control word to original value
21434 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21437 // Get the X86 opcode to use.
21439 switch (MI->getOpcode()) {
21440 default: llvm_unreachable("illegal opcode!");
21441 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21442 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21443 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21444 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21445 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21446 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21447 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21448 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21449 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21453 MachineOperand &Op = MI->getOperand(0);
21455 AM.BaseType = X86AddressMode::RegBase;
21456 AM.Base.Reg = Op.getReg();
21458 AM.BaseType = X86AddressMode::FrameIndexBase;
21459 AM.Base.FrameIndex = Op.getIndex();
21461 Op = MI->getOperand(1);
21463 AM.Scale = Op.getImm();
21464 Op = MI->getOperand(2);
21466 AM.IndexReg = Op.getImm();
21467 Op = MI->getOperand(3);
21468 if (Op.isGlobal()) {
21469 AM.GV = Op.getGlobal();
21471 AM.Disp = Op.getImm();
21473 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21474 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21476 // Reload the original control word now.
21477 addFrameReference(BuildMI(*BB, MI, DL,
21478 TII->get(X86::FLDCW16m)), CWFrameIdx);
21480 MI->eraseFromParent(); // The pseudo instruction is gone now.
21483 // String/text processing lowering.
21484 case X86::PCMPISTRM128REG:
21485 case X86::VPCMPISTRM128REG:
21486 case X86::PCMPISTRM128MEM:
21487 case X86::VPCMPISTRM128MEM:
21488 case X86::PCMPESTRM128REG:
21489 case X86::VPCMPESTRM128REG:
21490 case X86::PCMPESTRM128MEM:
21491 case X86::VPCMPESTRM128MEM:
21492 assert(Subtarget->hasSSE42() &&
21493 "Target must have SSE4.2 or AVX features enabled");
21494 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21496 // String/text processing lowering.
21497 case X86::PCMPISTRIREG:
21498 case X86::VPCMPISTRIREG:
21499 case X86::PCMPISTRIMEM:
21500 case X86::VPCMPISTRIMEM:
21501 case X86::PCMPESTRIREG:
21502 case X86::VPCMPESTRIREG:
21503 case X86::PCMPESTRIMEM:
21504 case X86::VPCMPESTRIMEM:
21505 assert(Subtarget->hasSSE42() &&
21506 "Target must have SSE4.2 or AVX features enabled");
21507 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21509 // Thread synchronization.
21511 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21516 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21518 case X86::VASTART_SAVE_XMM_REGS:
21519 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21521 case X86::VAARG_64:
21522 return EmitVAARG64WithCustomInserter(MI, BB);
21524 case X86::EH_SjLj_SetJmp32:
21525 case X86::EH_SjLj_SetJmp64:
21526 return emitEHSjLjSetJmp(MI, BB);
21528 case X86::EH_SjLj_LongJmp32:
21529 case X86::EH_SjLj_LongJmp64:
21530 return emitEHSjLjLongJmp(MI, BB);
21532 case TargetOpcode::STATEPOINT:
21533 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21534 // this point in the process. We diverge later.
21535 return emitPatchPoint(MI, BB);
21537 case TargetOpcode::STACKMAP:
21538 case TargetOpcode::PATCHPOINT:
21539 return emitPatchPoint(MI, BB);
21541 case X86::VFMADDPDr213r:
21542 case X86::VFMADDPSr213r:
21543 case X86::VFMADDSDr213r:
21544 case X86::VFMADDSSr213r:
21545 case X86::VFMSUBPDr213r:
21546 case X86::VFMSUBPSr213r:
21547 case X86::VFMSUBSDr213r:
21548 case X86::VFMSUBSSr213r:
21549 case X86::VFNMADDPDr213r:
21550 case X86::VFNMADDPSr213r:
21551 case X86::VFNMADDSDr213r:
21552 case X86::VFNMADDSSr213r:
21553 case X86::VFNMSUBPDr213r:
21554 case X86::VFNMSUBPSr213r:
21555 case X86::VFNMSUBSDr213r:
21556 case X86::VFNMSUBSSr213r:
21557 case X86::VFMADDSUBPDr213r:
21558 case X86::VFMADDSUBPSr213r:
21559 case X86::VFMSUBADDPDr213r:
21560 case X86::VFMSUBADDPSr213r:
21561 case X86::VFMADDPDr213rY:
21562 case X86::VFMADDPSr213rY:
21563 case X86::VFMSUBPDr213rY:
21564 case X86::VFMSUBPSr213rY:
21565 case X86::VFNMADDPDr213rY:
21566 case X86::VFNMADDPSr213rY:
21567 case X86::VFNMSUBPDr213rY:
21568 case X86::VFNMSUBPSr213rY:
21569 case X86::VFMADDSUBPDr213rY:
21570 case X86::VFMADDSUBPSr213rY:
21571 case X86::VFMSUBADDPDr213rY:
21572 case X86::VFMSUBADDPSr213rY:
21573 return emitFMA3Instr(MI, BB);
21577 //===----------------------------------------------------------------------===//
21578 // X86 Optimization Hooks
21579 //===----------------------------------------------------------------------===//
21581 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21584 const SelectionDAG &DAG,
21585 unsigned Depth) const {
21586 unsigned BitWidth = KnownZero.getBitWidth();
21587 unsigned Opc = Op.getOpcode();
21588 assert((Opc >= ISD::BUILTIN_OP_END ||
21589 Opc == ISD::INTRINSIC_WO_CHAIN ||
21590 Opc == ISD::INTRINSIC_W_CHAIN ||
21591 Opc == ISD::INTRINSIC_VOID) &&
21592 "Should use MaskedValueIsZero if you don't know whether Op"
21593 " is a target node!");
21595 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21609 // These nodes' second result is a boolean.
21610 if (Op.getResNo() == 0)
21613 case X86ISD::SETCC:
21614 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21616 case ISD::INTRINSIC_WO_CHAIN: {
21617 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21618 unsigned NumLoBits = 0;
21621 case Intrinsic::x86_sse_movmsk_ps:
21622 case Intrinsic::x86_avx_movmsk_ps_256:
21623 case Intrinsic::x86_sse2_movmsk_pd:
21624 case Intrinsic::x86_avx_movmsk_pd_256:
21625 case Intrinsic::x86_mmx_pmovmskb:
21626 case Intrinsic::x86_sse2_pmovmskb_128:
21627 case Intrinsic::x86_avx2_pmovmskb: {
21628 // High bits of movmskp{s|d}, pmovmskb are known zero.
21630 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21631 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21632 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21633 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21634 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21635 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21636 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21637 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21639 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21648 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21650 const SelectionDAG &,
21651 unsigned Depth) const {
21652 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21653 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21654 return Op.getValueType().getScalarType().getSizeInBits();
21660 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21661 /// node is a GlobalAddress + offset.
21662 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21663 const GlobalValue* &GA,
21664 int64_t &Offset) const {
21665 if (N->getOpcode() == X86ISD::Wrapper) {
21666 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21667 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21668 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21672 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21675 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21676 /// same as extracting the high 128-bit part of 256-bit vector and then
21677 /// inserting the result into the low part of a new 256-bit vector
21678 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21679 EVT VT = SVOp->getValueType(0);
21680 unsigned NumElems = VT.getVectorNumElements();
21682 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21683 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21684 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21685 SVOp->getMaskElt(j) >= 0)
21691 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21692 /// same as extracting the low 128-bit part of 256-bit vector and then
21693 /// inserting the result into the high part of a new 256-bit vector
21694 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21695 EVT VT = SVOp->getValueType(0);
21696 unsigned NumElems = VT.getVectorNumElements();
21698 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21699 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21700 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21701 SVOp->getMaskElt(j) >= 0)
21707 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21708 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21709 TargetLowering::DAGCombinerInfo &DCI,
21710 const X86Subtarget* Subtarget) {
21712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21713 SDValue V1 = SVOp->getOperand(0);
21714 SDValue V2 = SVOp->getOperand(1);
21715 EVT VT = SVOp->getValueType(0);
21716 unsigned NumElems = VT.getVectorNumElements();
21718 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21719 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21723 // V UNDEF BUILD_VECTOR UNDEF
21725 // CONCAT_VECTOR CONCAT_VECTOR
21728 // RESULT: V + zero extended
21730 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21731 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21732 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21735 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21738 // To match the shuffle mask, the first half of the mask should
21739 // be exactly the first vector, and all the rest a splat with the
21740 // first element of the second one.
21741 for (unsigned i = 0; i != NumElems/2; ++i)
21742 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21743 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21746 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21747 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21748 if (Ld->hasNUsesOfValue(1, 0)) {
21749 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21750 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21752 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21754 Ld->getPointerInfo(),
21755 Ld->getAlignment(),
21756 false/*isVolatile*/, true/*ReadMem*/,
21757 false/*WriteMem*/);
21759 // Make sure the newly-created LOAD is in the same position as Ld in
21760 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21761 // and update uses of Ld's output chain to use the TokenFactor.
21762 if (Ld->hasAnyUseOfValue(1)) {
21763 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21764 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21765 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21766 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21767 SDValue(ResNode.getNode(), 1));
21770 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21774 // Emit a zeroed vector and insert the desired subvector on its
21776 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21777 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21778 return DCI.CombineTo(N, InsV);
21781 //===--------------------------------------------------------------------===//
21782 // Combine some shuffles into subvector extracts and inserts:
21785 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21786 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21787 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21788 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21789 return DCI.CombineTo(N, InsV);
21792 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21793 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21794 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21795 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21796 return DCI.CombineTo(N, InsV);
21802 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21805 /// This is the leaf of the recursive combinine below. When we have found some
21806 /// chain of single-use x86 shuffle instructions and accumulated the combined
21807 /// shuffle mask represented by them, this will try to pattern match that mask
21808 /// into either a single instruction if there is a special purpose instruction
21809 /// for this operation, or into a PSHUFB instruction which is a fully general
21810 /// instruction but should only be used to replace chains over a certain depth.
21811 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21812 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21813 TargetLowering::DAGCombinerInfo &DCI,
21814 const X86Subtarget *Subtarget) {
21815 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21817 // Find the operand that enters the chain. Note that multiple uses are OK
21818 // here, we're not going to remove the operand we find.
21819 SDValue Input = Op.getOperand(0);
21820 while (Input.getOpcode() == ISD::BITCAST)
21821 Input = Input.getOperand(0);
21823 MVT VT = Input.getSimpleValueType();
21824 MVT RootVT = Root.getSimpleValueType();
21827 // Just remove no-op shuffle masks.
21828 if (Mask.size() == 1) {
21829 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21834 // Use the float domain if the operand type is a floating point type.
21835 bool FloatDomain = VT.isFloatingPoint();
21837 // For floating point shuffles, we don't have free copies in the shuffle
21838 // instructions or the ability to load as part of the instruction, so
21839 // canonicalize their shuffles to UNPCK or MOV variants.
21841 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21842 // vectors because it can have a load folded into it that UNPCK cannot. This
21843 // doesn't preclude something switching to the shorter encoding post-RA.
21845 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21846 bool Lo = Mask.equals(0, 0);
21849 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21850 // is no slower than UNPCKLPD but has the option to fold the input operand
21851 // into even an unaligned memory load.
21852 if (Lo && Subtarget->hasSSE3()) {
21853 Shuffle = X86ISD::MOVDDUP;
21854 ShuffleVT = MVT::v2f64;
21856 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21857 // than the UNPCK variants.
21858 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21859 ShuffleVT = MVT::v4f32;
21861 if (Depth == 1 && Root->getOpcode() == Shuffle)
21862 return false; // Nothing to do!
21863 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21864 DCI.AddToWorklist(Op.getNode());
21865 if (Shuffle == X86ISD::MOVDDUP)
21866 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21868 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21869 DCI.AddToWorklist(Op.getNode());
21870 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21874 if (Subtarget->hasSSE3() &&
21875 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21876 bool Lo = Mask.equals(0, 0, 2, 2);
21877 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21878 MVT ShuffleVT = MVT::v4f32;
21879 if (Depth == 1 && Root->getOpcode() == Shuffle)
21880 return false; // Nothing to do!
21881 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21882 DCI.AddToWorklist(Op.getNode());
21883 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21884 DCI.AddToWorklist(Op.getNode());
21885 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21889 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21890 bool Lo = Mask.equals(0, 0, 1, 1);
21891 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21892 MVT ShuffleVT = MVT::v4f32;
21893 if (Depth == 1 && Root->getOpcode() == Shuffle)
21894 return false; // Nothing to do!
21895 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21896 DCI.AddToWorklist(Op.getNode());
21897 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21898 DCI.AddToWorklist(Op.getNode());
21899 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21905 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21906 // variants as none of these have single-instruction variants that are
21907 // superior to the UNPCK formulation.
21908 if (!FloatDomain &&
21909 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21910 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21911 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21912 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21914 bool Lo = Mask[0] == 0;
21915 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21916 if (Depth == 1 && Root->getOpcode() == Shuffle)
21917 return false; // Nothing to do!
21919 switch (Mask.size()) {
21921 ShuffleVT = MVT::v8i16;
21924 ShuffleVT = MVT::v16i8;
21927 llvm_unreachable("Impossible mask size!");
21929 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21930 DCI.AddToWorklist(Op.getNode());
21931 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21932 DCI.AddToWorklist(Op.getNode());
21933 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21938 // Don't try to re-form single instruction chains under any circumstances now
21939 // that we've done encoding canonicalization for them.
21943 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21944 // can replace them with a single PSHUFB instruction profitably. Intel's
21945 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21946 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21947 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21948 SmallVector<SDValue, 16> PSHUFBMask;
21949 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21950 int Ratio = 16 / Mask.size();
21951 for (unsigned i = 0; i < 16; ++i) {
21952 if (Mask[i / Ratio] == SM_SentinelUndef) {
21953 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21956 int M = Mask[i / Ratio] != SM_SentinelZero
21957 ? Ratio * Mask[i / Ratio] + i % Ratio
21959 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21961 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21962 DCI.AddToWorklist(Op.getNode());
21963 SDValue PSHUFBMaskOp =
21964 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21965 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21966 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21967 DCI.AddToWorklist(Op.getNode());
21968 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21973 // Failed to find any combines.
21977 /// \brief Fully generic combining of x86 shuffle instructions.
21979 /// This should be the last combine run over the x86 shuffle instructions. Once
21980 /// they have been fully optimized, this will recursively consider all chains
21981 /// of single-use shuffle instructions, build a generic model of the cumulative
21982 /// shuffle operation, and check for simpler instructions which implement this
21983 /// operation. We use this primarily for two purposes:
21985 /// 1) Collapse generic shuffles to specialized single instructions when
21986 /// equivalent. In most cases, this is just an encoding size win, but
21987 /// sometimes we will collapse multiple generic shuffles into a single
21988 /// special-purpose shuffle.
21989 /// 2) Look for sequences of shuffle instructions with 3 or more total
21990 /// instructions, and replace them with the slightly more expensive SSSE3
21991 /// PSHUFB instruction if available. We do this as the last combining step
21992 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21993 /// a suitable short sequence of other instructions. The PHUFB will either
21994 /// use a register or have to read from memory and so is slightly (but only
21995 /// slightly) more expensive than the other shuffle instructions.
21997 /// Because this is inherently a quadratic operation (for each shuffle in
21998 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21999 /// This should never be an issue in practice as the shuffle lowering doesn't
22000 /// produce sequences of more than 8 instructions.
22002 /// FIXME: We will currently miss some cases where the redundant shuffling
22003 /// would simplify under the threshold for PSHUFB formation because of
22004 /// combine-ordering. To fix this, we should do the redundant instruction
22005 /// combining in this recursive walk.
22006 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22007 ArrayRef<int> RootMask,
22008 int Depth, bool HasPSHUFB,
22010 TargetLowering::DAGCombinerInfo &DCI,
22011 const X86Subtarget *Subtarget) {
22012 // Bound the depth of our recursive combine because this is ultimately
22013 // quadratic in nature.
22017 // Directly rip through bitcasts to find the underlying operand.
22018 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22019 Op = Op.getOperand(0);
22021 MVT VT = Op.getSimpleValueType();
22022 if (!VT.isVector())
22023 return false; // Bail if we hit a non-vector.
22024 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
22025 // version should be added.
22026 if (VT.getSizeInBits() != 128)
22029 assert(Root.getSimpleValueType().isVector() &&
22030 "Shuffles operate on vector types!");
22031 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22032 "Can only combine shuffles of the same vector register size.");
22034 if (!isTargetShuffle(Op.getOpcode()))
22036 SmallVector<int, 16> OpMask;
22038 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22039 // We only can combine unary shuffles which we can decode the mask for.
22040 if (!HaveMask || !IsUnary)
22043 assert(VT.getVectorNumElements() == OpMask.size() &&
22044 "Different mask size from vector size!");
22045 assert(((RootMask.size() > OpMask.size() &&
22046 RootMask.size() % OpMask.size() == 0) ||
22047 (OpMask.size() > RootMask.size() &&
22048 OpMask.size() % RootMask.size() == 0) ||
22049 OpMask.size() == RootMask.size()) &&
22050 "The smaller number of elements must divide the larger.");
22051 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22052 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22053 assert(((RootRatio == 1 && OpRatio == 1) ||
22054 (RootRatio == 1) != (OpRatio == 1)) &&
22055 "Must not have a ratio for both incoming and op masks!");
22057 SmallVector<int, 16> Mask;
22058 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22060 // Merge this shuffle operation's mask into our accumulated mask. Note that
22061 // this shuffle's mask will be the first applied to the input, followed by the
22062 // root mask to get us all the way to the root value arrangement. The reason
22063 // for this order is that we are recursing up the operation chain.
22064 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22065 int RootIdx = i / RootRatio;
22066 if (RootMask[RootIdx] < 0) {
22067 // This is a zero or undef lane, we're done.
22068 Mask.push_back(RootMask[RootIdx]);
22072 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22073 int OpIdx = RootMaskedIdx / OpRatio;
22074 if (OpMask[OpIdx] < 0) {
22075 // The incoming lanes are zero or undef, it doesn't matter which ones we
22077 Mask.push_back(OpMask[OpIdx]);
22081 // Ok, we have non-zero lanes, map them through.
22082 Mask.push_back(OpMask[OpIdx] * OpRatio +
22083 RootMaskedIdx % OpRatio);
22086 // See if we can recurse into the operand to combine more things.
22087 switch (Op.getOpcode()) {
22088 case X86ISD::PSHUFB:
22090 case X86ISD::PSHUFD:
22091 case X86ISD::PSHUFHW:
22092 case X86ISD::PSHUFLW:
22093 if (Op.getOperand(0).hasOneUse() &&
22094 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22095 HasPSHUFB, DAG, DCI, Subtarget))
22099 case X86ISD::UNPCKL:
22100 case X86ISD::UNPCKH:
22101 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22102 // We can't check for single use, we have to check that this shuffle is the only user.
22103 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22104 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22105 HasPSHUFB, DAG, DCI, Subtarget))
22110 // Minor canonicalization of the accumulated shuffle mask to make it easier
22111 // to match below. All this does is detect masks with squential pairs of
22112 // elements, and shrink them to the half-width mask. It does this in a loop
22113 // so it will reduce the size of the mask to the minimal width mask which
22114 // performs an equivalent shuffle.
22115 SmallVector<int, 16> WidenedMask;
22116 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22117 Mask = std::move(WidenedMask);
22118 WidenedMask.clear();
22121 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22125 /// \brief Get the PSHUF-style mask from PSHUF node.
22127 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22128 /// PSHUF-style masks that can be reused with such instructions.
22129 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22130 SmallVector<int, 4> Mask;
22132 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22136 switch (N.getOpcode()) {
22137 case X86ISD::PSHUFD:
22139 case X86ISD::PSHUFLW:
22142 case X86ISD::PSHUFHW:
22143 Mask.erase(Mask.begin(), Mask.begin() + 4);
22144 for (int &M : Mask)
22148 llvm_unreachable("No valid shuffle instruction found!");
22152 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22154 /// We walk up the chain and look for a combinable shuffle, skipping over
22155 /// shuffles that we could hoist this shuffle's transformation past without
22156 /// altering anything.
22158 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22160 TargetLowering::DAGCombinerInfo &DCI) {
22161 assert(N.getOpcode() == X86ISD::PSHUFD &&
22162 "Called with something other than an x86 128-bit half shuffle!");
22165 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22166 // of the shuffles in the chain so that we can form a fresh chain to replace
22168 SmallVector<SDValue, 8> Chain;
22169 SDValue V = N.getOperand(0);
22170 for (; V.hasOneUse(); V = V.getOperand(0)) {
22171 switch (V.getOpcode()) {
22173 return SDValue(); // Nothing combined!
22176 // Skip bitcasts as we always know the type for the target specific
22180 case X86ISD::PSHUFD:
22181 // Found another dword shuffle.
22184 case X86ISD::PSHUFLW:
22185 // Check that the low words (being shuffled) are the identity in the
22186 // dword shuffle, and the high words are self-contained.
22187 if (Mask[0] != 0 || Mask[1] != 1 ||
22188 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22191 Chain.push_back(V);
22194 case X86ISD::PSHUFHW:
22195 // Check that the high words (being shuffled) are the identity in the
22196 // dword shuffle, and the low words are self-contained.
22197 if (Mask[2] != 2 || Mask[3] != 3 ||
22198 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22201 Chain.push_back(V);
22204 case X86ISD::UNPCKL:
22205 case X86ISD::UNPCKH:
22206 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22207 // shuffle into a preceding word shuffle.
22208 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22211 // Search for a half-shuffle which we can combine with.
22212 unsigned CombineOp =
22213 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22214 if (V.getOperand(0) != V.getOperand(1) ||
22215 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22217 Chain.push_back(V);
22218 V = V.getOperand(0);
22220 switch (V.getOpcode()) {
22222 return SDValue(); // Nothing to combine.
22224 case X86ISD::PSHUFLW:
22225 case X86ISD::PSHUFHW:
22226 if (V.getOpcode() == CombineOp)
22229 Chain.push_back(V);
22233 V = V.getOperand(0);
22237 } while (V.hasOneUse());
22240 // Break out of the loop if we break out of the switch.
22244 if (!V.hasOneUse())
22245 // We fell out of the loop without finding a viable combining instruction.
22248 // Merge this node's mask and our incoming mask.
22249 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22250 for (int &M : Mask)
22252 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22253 getV4X86ShuffleImm8ForMask(Mask, DAG));
22255 // Rebuild the chain around this new shuffle.
22256 while (!Chain.empty()) {
22257 SDValue W = Chain.pop_back_val();
22259 if (V.getValueType() != W.getOperand(0).getValueType())
22260 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22262 switch (W.getOpcode()) {
22264 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22266 case X86ISD::UNPCKL:
22267 case X86ISD::UNPCKH:
22268 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22271 case X86ISD::PSHUFD:
22272 case X86ISD::PSHUFLW:
22273 case X86ISD::PSHUFHW:
22274 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22278 if (V.getValueType() != N.getValueType())
22279 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22281 // Return the new chain to replace N.
22285 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22287 /// We walk up the chain, skipping shuffles of the other half and looking
22288 /// through shuffles which switch halves trying to find a shuffle of the same
22289 /// pair of dwords.
22290 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22292 TargetLowering::DAGCombinerInfo &DCI) {
22294 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22295 "Called with something other than an x86 128-bit half shuffle!");
22297 unsigned CombineOpcode = N.getOpcode();
22299 // Walk up a single-use chain looking for a combinable shuffle.
22300 SDValue V = N.getOperand(0);
22301 for (; V.hasOneUse(); V = V.getOperand(0)) {
22302 switch (V.getOpcode()) {
22304 return false; // Nothing combined!
22307 // Skip bitcasts as we always know the type for the target specific
22311 case X86ISD::PSHUFLW:
22312 case X86ISD::PSHUFHW:
22313 if (V.getOpcode() == CombineOpcode)
22316 // Other-half shuffles are no-ops.
22319 // Break out of the loop if we break out of the switch.
22323 if (!V.hasOneUse())
22324 // We fell out of the loop without finding a viable combining instruction.
22327 // Combine away the bottom node as its shuffle will be accumulated into
22328 // a preceding shuffle.
22329 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22331 // Record the old value.
22334 // Merge this node's mask and our incoming mask (adjusted to account for all
22335 // the pshufd instructions encountered).
22336 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22337 for (int &M : Mask)
22339 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22340 getV4X86ShuffleImm8ForMask(Mask, DAG));
22342 // Check that the shuffles didn't cancel each other out. If not, we need to
22343 // combine to the new one.
22345 // Replace the combinable shuffle with the combined one, updating all users
22346 // so that we re-evaluate the chain here.
22347 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22352 /// \brief Try to combine x86 target specific shuffles.
22353 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22354 TargetLowering::DAGCombinerInfo &DCI,
22355 const X86Subtarget *Subtarget) {
22357 MVT VT = N.getSimpleValueType();
22358 SmallVector<int, 4> Mask;
22360 switch (N.getOpcode()) {
22361 case X86ISD::PSHUFD:
22362 case X86ISD::PSHUFLW:
22363 case X86ISD::PSHUFHW:
22364 Mask = getPSHUFShuffleMask(N);
22365 assert(Mask.size() == 4);
22371 // Nuke no-op shuffles that show up after combining.
22372 if (isNoopShuffleMask(Mask))
22373 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22375 // Look for simplifications involving one or two shuffle instructions.
22376 SDValue V = N.getOperand(0);
22377 switch (N.getOpcode()) {
22380 case X86ISD::PSHUFLW:
22381 case X86ISD::PSHUFHW:
22382 assert(VT == MVT::v8i16);
22385 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22386 return SDValue(); // We combined away this shuffle, so we're done.
22388 // See if this reduces to a PSHUFD which is no more expensive and can
22389 // combine with more operations. Note that it has to at least flip the
22390 // dwords as otherwise it would have been removed as a no-op.
22391 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22392 int DMask[] = {0, 1, 2, 3};
22393 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22394 DMask[DOffset + 0] = DOffset + 1;
22395 DMask[DOffset + 1] = DOffset + 0;
22396 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22397 DCI.AddToWorklist(V.getNode());
22398 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22399 getV4X86ShuffleImm8ForMask(DMask, DAG));
22400 DCI.AddToWorklist(V.getNode());
22401 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22404 // Look for shuffle patterns which can be implemented as a single unpack.
22405 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22406 // only works when we have a PSHUFD followed by two half-shuffles.
22407 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22408 (V.getOpcode() == X86ISD::PSHUFLW ||
22409 V.getOpcode() == X86ISD::PSHUFHW) &&
22410 V.getOpcode() != N.getOpcode() &&
22412 SDValue D = V.getOperand(0);
22413 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22414 D = D.getOperand(0);
22415 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22416 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22417 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22418 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22419 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22421 for (int i = 0; i < 4; ++i) {
22422 WordMask[i + NOffset] = Mask[i] + NOffset;
22423 WordMask[i + VOffset] = VMask[i] + VOffset;
22425 // Map the word mask through the DWord mask.
22427 for (int i = 0; i < 8; ++i)
22428 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22429 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22430 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22431 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22432 std::begin(UnpackLoMask)) ||
22433 std::equal(std::begin(MappedMask), std::end(MappedMask),
22434 std::begin(UnpackHiMask))) {
22435 // We can replace all three shuffles with an unpack.
22436 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22437 DCI.AddToWorklist(V.getNode());
22438 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22440 DL, MVT::v8i16, V, V);
22447 case X86ISD::PSHUFD:
22448 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22457 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22459 /// We combine this directly on the abstract vector shuffle nodes so it is
22460 /// easier to generically match. We also insert dummy vector shuffle nodes for
22461 /// the operands which explicitly discard the lanes which are unused by this
22462 /// operation to try to flow through the rest of the combiner the fact that
22463 /// they're unused.
22464 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22466 EVT VT = N->getValueType(0);
22468 // We only handle target-independent shuffles.
22469 // FIXME: It would be easy and harmless to use the target shuffle mask
22470 // extraction tool to support more.
22471 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22474 auto *SVN = cast<ShuffleVectorSDNode>(N);
22475 ArrayRef<int> Mask = SVN->getMask();
22476 SDValue V1 = N->getOperand(0);
22477 SDValue V2 = N->getOperand(1);
22479 // We require the first shuffle operand to be the SUB node, and the second to
22480 // be the ADD node.
22481 // FIXME: We should support the commuted patterns.
22482 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22485 // If there are other uses of these operations we can't fold them.
22486 if (!V1->hasOneUse() || !V2->hasOneUse())
22489 // Ensure that both operations have the same operands. Note that we can
22490 // commute the FADD operands.
22491 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22492 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22493 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22496 // We're looking for blends between FADD and FSUB nodes. We insist on these
22497 // nodes being lined up in a specific expected pattern.
22498 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22499 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22500 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22503 // Only specific types are legal at this point, assert so we notice if and
22504 // when these change.
22505 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22506 VT == MVT::v4f64) &&
22507 "Unknown vector type encountered!");
22509 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22512 /// PerformShuffleCombine - Performs several different shuffle combines.
22513 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22514 TargetLowering::DAGCombinerInfo &DCI,
22515 const X86Subtarget *Subtarget) {
22517 SDValue N0 = N->getOperand(0);
22518 SDValue N1 = N->getOperand(1);
22519 EVT VT = N->getValueType(0);
22521 // Don't create instructions with illegal types after legalize types has run.
22522 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22523 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22526 // If we have legalized the vector types, look for blends of FADD and FSUB
22527 // nodes that we can fuse into an ADDSUB node.
22528 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22529 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22532 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22533 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22534 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22535 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22537 // During Type Legalization, when promoting illegal vector types,
22538 // the backend might introduce new shuffle dag nodes and bitcasts.
22540 // This code performs the following transformation:
22541 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22542 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22544 // We do this only if both the bitcast and the BINOP dag nodes have
22545 // one use. Also, perform this transformation only if the new binary
22546 // operation is legal. This is to avoid introducing dag nodes that
22547 // potentially need to be further expanded (or custom lowered) into a
22548 // less optimal sequence of dag nodes.
22549 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22550 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22551 N0.getOpcode() == ISD::BITCAST) {
22552 SDValue BC0 = N0.getOperand(0);
22553 EVT SVT = BC0.getValueType();
22554 unsigned Opcode = BC0.getOpcode();
22555 unsigned NumElts = VT.getVectorNumElements();
22557 if (BC0.hasOneUse() && SVT.isVector() &&
22558 SVT.getVectorNumElements() * 2 == NumElts &&
22559 TLI.isOperationLegal(Opcode, VT)) {
22560 bool CanFold = false;
22572 unsigned SVTNumElts = SVT.getVectorNumElements();
22573 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22574 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22575 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22576 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22577 CanFold = SVOp->getMaskElt(i) < 0;
22580 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22581 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22582 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22583 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22588 // Only handle 128 wide vector from here on.
22589 if (!VT.is128BitVector())
22592 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22593 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22594 // consecutive, non-overlapping, and in the right order.
22595 SmallVector<SDValue, 16> Elts;
22596 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22597 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22599 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22603 if (isTargetShuffle(N->getOpcode())) {
22605 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22606 if (Shuffle.getNode())
22609 // Try recursively combining arbitrary sequences of x86 shuffle
22610 // instructions into higher-order shuffles. We do this after combining
22611 // specific PSHUF instruction sequences into their minimal form so that we
22612 // can evaluate how many specialized shuffle instructions are involved in
22613 // a particular chain.
22614 SmallVector<int, 1> NonceMask; // Just a placeholder.
22615 NonceMask.push_back(0);
22616 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22617 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22619 return SDValue(); // This routine will use CombineTo to replace N.
22625 /// PerformTruncateCombine - Converts truncate operation to
22626 /// a sequence of vector shuffle operations.
22627 /// It is possible when we truncate 256-bit vector to 128-bit vector
22628 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22629 TargetLowering::DAGCombinerInfo &DCI,
22630 const X86Subtarget *Subtarget) {
22634 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22635 /// specific shuffle of a load can be folded into a single element load.
22636 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22637 /// shuffles have been custom lowered so we need to handle those here.
22638 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22639 TargetLowering::DAGCombinerInfo &DCI) {
22640 if (DCI.isBeforeLegalizeOps())
22643 SDValue InVec = N->getOperand(0);
22644 SDValue EltNo = N->getOperand(1);
22646 if (!isa<ConstantSDNode>(EltNo))
22649 EVT OriginalVT = InVec.getValueType();
22651 if (InVec.getOpcode() == ISD::BITCAST) {
22652 // Don't duplicate a load with other uses.
22653 if (!InVec.hasOneUse())
22655 EVT BCVT = InVec.getOperand(0).getValueType();
22656 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22658 InVec = InVec.getOperand(0);
22661 EVT CurrentVT = InVec.getValueType();
22663 if (!isTargetShuffle(InVec.getOpcode()))
22666 // Don't duplicate a load with other uses.
22667 if (!InVec.hasOneUse())
22670 SmallVector<int, 16> ShuffleMask;
22672 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22673 ShuffleMask, UnaryShuffle))
22676 // Select the input vector, guarding against out of range extract vector.
22677 unsigned NumElems = CurrentVT.getVectorNumElements();
22678 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22679 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22680 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22681 : InVec.getOperand(1);
22683 // If inputs to shuffle are the same for both ops, then allow 2 uses
22684 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22686 if (LdNode.getOpcode() == ISD::BITCAST) {
22687 // Don't duplicate a load with other uses.
22688 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22691 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22692 LdNode = LdNode.getOperand(0);
22695 if (!ISD::isNormalLoad(LdNode.getNode()))
22698 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22700 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22703 EVT EltVT = N->getValueType(0);
22704 // If there's a bitcast before the shuffle, check if the load type and
22705 // alignment is valid.
22706 unsigned Align = LN0->getAlignment();
22707 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22708 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22709 EltVT.getTypeForEVT(*DAG.getContext()));
22711 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22714 // All checks match so transform back to vector_shuffle so that DAG combiner
22715 // can finish the job
22718 // Create shuffle node taking into account the case that its a unary shuffle
22719 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22720 : InVec.getOperand(1);
22721 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22722 InVec.getOperand(0), Shuffle,
22724 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22725 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22729 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22730 /// generation and convert it from being a bunch of shuffles and extracts
22731 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22732 /// storing the value and loading scalars back, while for x64 we should
22733 /// use 64-bit extracts and shifts.
22734 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22735 TargetLowering::DAGCombinerInfo &DCI) {
22736 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22737 if (NewOp.getNode())
22740 SDValue InputVector = N->getOperand(0);
22742 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22743 // from mmx to v2i32 has a single usage.
22744 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22745 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22746 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22747 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22748 N->getValueType(0),
22749 InputVector.getNode()->getOperand(0));
22751 // Only operate on vectors of 4 elements, where the alternative shuffling
22752 // gets to be more expensive.
22753 if (InputVector.getValueType() != MVT::v4i32)
22756 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22757 // single use which is a sign-extend or zero-extend, and all elements are
22759 SmallVector<SDNode *, 4> Uses;
22760 unsigned ExtractedElements = 0;
22761 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22762 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22763 if (UI.getUse().getResNo() != InputVector.getResNo())
22766 SDNode *Extract = *UI;
22767 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22770 if (Extract->getValueType(0) != MVT::i32)
22772 if (!Extract->hasOneUse())
22774 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22775 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22777 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22780 // Record which element was extracted.
22781 ExtractedElements |=
22782 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22784 Uses.push_back(Extract);
22787 // If not all the elements were used, this may not be worthwhile.
22788 if (ExtractedElements != 15)
22791 // Ok, we've now decided to do the transformation.
22792 // If 64-bit shifts are legal, use the extract-shift sequence,
22793 // otherwise bounce the vector off the cache.
22794 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22796 SDLoc dl(InputVector);
22798 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22799 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22800 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22801 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22802 DAG.getConstant(0, VecIdxTy));
22803 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22804 DAG.getConstant(1, VecIdxTy));
22806 SDValue ShAmt = DAG.getConstant(32,
22807 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22808 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22809 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22810 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22811 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22812 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22813 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22815 // Store the value to a temporary stack slot.
22816 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22817 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22818 MachinePointerInfo(), false, false, 0);
22820 EVT ElementType = InputVector.getValueType().getVectorElementType();
22821 unsigned EltSize = ElementType.getSizeInBits() / 8;
22823 // Replace each use (extract) with a load of the appropriate element.
22824 for (unsigned i = 0; i < 4; ++i) {
22825 uint64_t Offset = EltSize * i;
22826 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22828 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22829 StackPtr, OffsetVal);
22831 // Load the scalar.
22832 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22833 ScalarAddr, MachinePointerInfo(),
22834 false, false, false, 0);
22839 // Replace the extracts
22840 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22841 UE = Uses.end(); UI != UE; ++UI) {
22842 SDNode *Extract = *UI;
22844 SDValue Idx = Extract->getOperand(1);
22845 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22846 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22849 // The replacement was made in place; don't return anything.
22853 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22854 static std::pair<unsigned, bool>
22855 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22856 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22857 if (!VT.isVector())
22858 return std::make_pair(0, false);
22860 bool NeedSplit = false;
22861 switch (VT.getSimpleVT().SimpleTy) {
22862 default: return std::make_pair(0, false);
22865 if (!Subtarget->hasVLX())
22866 return std::make_pair(0, false);
22870 if (!Subtarget->hasBWI())
22871 return std::make_pair(0, false);
22875 if (!Subtarget->hasAVX512())
22876 return std::make_pair(0, false);
22881 if (!Subtarget->hasAVX2())
22883 if (!Subtarget->hasAVX())
22884 return std::make_pair(0, false);
22889 if (!Subtarget->hasSSE2())
22890 return std::make_pair(0, false);
22893 // SSE2 has only a small subset of the operations.
22894 bool hasUnsigned = Subtarget->hasSSE41() ||
22895 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22896 bool hasSigned = Subtarget->hasSSE41() ||
22897 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22899 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22902 // Check for x CC y ? x : y.
22903 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22904 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22909 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22912 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22915 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22918 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22920 // Check for x CC y ? y : x -- a min/max with reversed arms.
22921 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22922 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22927 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22930 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22933 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22936 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22940 return std::make_pair(Opc, NeedSplit);
22944 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22945 const X86Subtarget *Subtarget) {
22947 SDValue Cond = N->getOperand(0);
22948 SDValue LHS = N->getOperand(1);
22949 SDValue RHS = N->getOperand(2);
22951 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22952 SDValue CondSrc = Cond->getOperand(0);
22953 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22954 Cond = CondSrc->getOperand(0);
22957 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22960 // A vselect where all conditions and data are constants can be optimized into
22961 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22962 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22963 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22966 unsigned MaskValue = 0;
22967 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22970 MVT VT = N->getSimpleValueType(0);
22971 unsigned NumElems = VT.getVectorNumElements();
22972 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22973 for (unsigned i = 0; i < NumElems; ++i) {
22974 // Be sure we emit undef where we can.
22975 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22976 ShuffleMask[i] = -1;
22978 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22981 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22982 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22984 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22987 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22989 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22990 TargetLowering::DAGCombinerInfo &DCI,
22991 const X86Subtarget *Subtarget) {
22993 SDValue Cond = N->getOperand(0);
22994 // Get the LHS/RHS of the select.
22995 SDValue LHS = N->getOperand(1);
22996 SDValue RHS = N->getOperand(2);
22997 EVT VT = LHS.getValueType();
22998 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23000 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23001 // instructions match the semantics of the common C idiom x<y?x:y but not
23002 // x<=y?x:y, because of how they handle negative zero (which can be
23003 // ignored in unsafe-math mode).
23004 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23005 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
23006 (Subtarget->hasSSE2() ||
23007 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23008 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23010 unsigned Opcode = 0;
23011 // Check for x CC y ? x : y.
23012 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23013 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23017 // Converting this to a min would handle NaNs incorrectly, and swapping
23018 // the operands would cause it to handle comparisons between positive
23019 // and negative zero incorrectly.
23020 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23021 if (!DAG.getTarget().Options.UnsafeFPMath &&
23022 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23024 std::swap(LHS, RHS);
23026 Opcode = X86ISD::FMIN;
23029 // Converting this to a min would handle comparisons between positive
23030 // and negative zero incorrectly.
23031 if (!DAG.getTarget().Options.UnsafeFPMath &&
23032 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23034 Opcode = X86ISD::FMIN;
23037 // Converting this to a min would handle both negative zeros and NaNs
23038 // incorrectly, but we can swap the operands to fix both.
23039 std::swap(LHS, RHS);
23043 Opcode = X86ISD::FMIN;
23047 // Converting this to a max would handle comparisons between positive
23048 // and negative zero incorrectly.
23049 if (!DAG.getTarget().Options.UnsafeFPMath &&
23050 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23052 Opcode = X86ISD::FMAX;
23055 // Converting this to a max would handle NaNs incorrectly, and swapping
23056 // the operands would cause it to handle comparisons between positive
23057 // and negative zero incorrectly.
23058 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23059 if (!DAG.getTarget().Options.UnsafeFPMath &&
23060 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23062 std::swap(LHS, RHS);
23064 Opcode = X86ISD::FMAX;
23067 // Converting this to a max would handle both negative zeros and NaNs
23068 // incorrectly, but we can swap the operands to fix both.
23069 std::swap(LHS, RHS);
23073 Opcode = X86ISD::FMAX;
23076 // Check for x CC y ? y : x -- a min/max with reversed arms.
23077 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23078 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23082 // Converting this to a min would handle comparisons between positive
23083 // and negative zero incorrectly, and swapping the operands would
23084 // cause it to handle NaNs incorrectly.
23085 if (!DAG.getTarget().Options.UnsafeFPMath &&
23086 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23087 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23089 std::swap(LHS, RHS);
23091 Opcode = X86ISD::FMIN;
23094 // Converting this to a min would handle NaNs incorrectly.
23095 if (!DAG.getTarget().Options.UnsafeFPMath &&
23096 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23098 Opcode = X86ISD::FMIN;
23101 // Converting this to a min would handle both negative zeros and NaNs
23102 // incorrectly, but we can swap the operands to fix both.
23103 std::swap(LHS, RHS);
23107 Opcode = X86ISD::FMIN;
23111 // Converting this to a max would handle NaNs incorrectly.
23112 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23114 Opcode = X86ISD::FMAX;
23117 // Converting this to a max would handle comparisons between positive
23118 // and negative zero incorrectly, and swapping the operands would
23119 // cause it to handle NaNs incorrectly.
23120 if (!DAG.getTarget().Options.UnsafeFPMath &&
23121 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23122 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23124 std::swap(LHS, RHS);
23126 Opcode = X86ISD::FMAX;
23129 // Converting this to a max would handle both negative zeros and NaNs
23130 // incorrectly, but we can swap the operands to fix both.
23131 std::swap(LHS, RHS);
23135 Opcode = X86ISD::FMAX;
23141 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23144 EVT CondVT = Cond.getValueType();
23145 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23146 CondVT.getVectorElementType() == MVT::i1) {
23147 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23148 // lowering on KNL. In this case we convert it to
23149 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23150 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23151 // Since SKX these selects have a proper lowering.
23152 EVT OpVT = LHS.getValueType();
23153 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23154 (OpVT.getVectorElementType() == MVT::i8 ||
23155 OpVT.getVectorElementType() == MVT::i16) &&
23156 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23157 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23158 DCI.AddToWorklist(Cond.getNode());
23159 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23162 // If this is a select between two integer constants, try to do some
23164 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23165 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23166 // Don't do this for crazy integer types.
23167 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23168 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23169 // so that TrueC (the true value) is larger than FalseC.
23170 bool NeedsCondInvert = false;
23172 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23173 // Efficiently invertible.
23174 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23175 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23176 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23177 NeedsCondInvert = true;
23178 std::swap(TrueC, FalseC);
23181 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23182 if (FalseC->getAPIntValue() == 0 &&
23183 TrueC->getAPIntValue().isPowerOf2()) {
23184 if (NeedsCondInvert) // Invert the condition if needed.
23185 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23186 DAG.getConstant(1, Cond.getValueType()));
23188 // Zero extend the condition if needed.
23189 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23191 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23192 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23193 DAG.getConstant(ShAmt, MVT::i8));
23196 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23197 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23198 if (NeedsCondInvert) // Invert the condition if needed.
23199 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23200 DAG.getConstant(1, Cond.getValueType()));
23202 // Zero extend the condition if needed.
23203 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23204 FalseC->getValueType(0), Cond);
23205 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23206 SDValue(FalseC, 0));
23209 // Optimize cases that will turn into an LEA instruction. This requires
23210 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23211 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23212 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23213 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23215 bool isFastMultiplier = false;
23217 switch ((unsigned char)Diff) {
23219 case 1: // result = add base, cond
23220 case 2: // result = lea base( , cond*2)
23221 case 3: // result = lea base(cond, cond*2)
23222 case 4: // result = lea base( , cond*4)
23223 case 5: // result = lea base(cond, cond*4)
23224 case 8: // result = lea base( , cond*8)
23225 case 9: // result = lea base(cond, cond*8)
23226 isFastMultiplier = true;
23231 if (isFastMultiplier) {
23232 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23233 if (NeedsCondInvert) // Invert the condition if needed.
23234 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23235 DAG.getConstant(1, Cond.getValueType()));
23237 // Zero extend the condition if needed.
23238 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23240 // Scale the condition by the difference.
23242 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23243 DAG.getConstant(Diff, Cond.getValueType()));
23245 // Add the base if non-zero.
23246 if (FalseC->getAPIntValue() != 0)
23247 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23248 SDValue(FalseC, 0));
23255 // Canonicalize max and min:
23256 // (x > y) ? x : y -> (x >= y) ? x : y
23257 // (x < y) ? x : y -> (x <= y) ? x : y
23258 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23259 // the need for an extra compare
23260 // against zero. e.g.
23261 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23263 // testl %edi, %edi
23265 // cmovgl %edi, %eax
23269 // cmovsl %eax, %edi
23270 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23271 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23272 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23273 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23278 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23279 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23280 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23281 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23286 // Early exit check
23287 if (!TLI.isTypeLegal(VT))
23290 // Match VSELECTs into subs with unsigned saturation.
23291 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23292 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23293 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23294 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23295 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23297 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23298 // left side invert the predicate to simplify logic below.
23300 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23302 CC = ISD::getSetCCInverse(CC, true);
23303 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23307 if (Other.getNode() && Other->getNumOperands() == 2 &&
23308 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23309 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23310 SDValue CondRHS = Cond->getOperand(1);
23312 // Look for a general sub with unsigned saturation first.
23313 // x >= y ? x-y : 0 --> subus x, y
23314 // x > y ? x-y : 0 --> subus x, y
23315 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23316 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23317 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23319 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23320 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23321 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23322 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23323 // If the RHS is a constant we have to reverse the const
23324 // canonicalization.
23325 // x > C-1 ? x+-C : 0 --> subus x, C
23326 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23327 CondRHSConst->getAPIntValue() ==
23328 (-OpRHSConst->getAPIntValue() - 1))
23329 return DAG.getNode(
23330 X86ISD::SUBUS, DL, VT, OpLHS,
23331 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23333 // Another special case: If C was a sign bit, the sub has been
23334 // canonicalized into a xor.
23335 // FIXME: Would it be better to use computeKnownBits to determine
23336 // whether it's safe to decanonicalize the xor?
23337 // x s< 0 ? x^C : 0 --> subus x, C
23338 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23339 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23340 OpRHSConst->getAPIntValue().isSignBit())
23341 // Note that we have to rebuild the RHS constant here to ensure we
23342 // don't rely on particular values of undef lanes.
23343 return DAG.getNode(
23344 X86ISD::SUBUS, DL, VT, OpLHS,
23345 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23350 // Try to match a min/max vector operation.
23351 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23352 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23353 unsigned Opc = ret.first;
23354 bool NeedSplit = ret.second;
23356 if (Opc && NeedSplit) {
23357 unsigned NumElems = VT.getVectorNumElements();
23358 // Extract the LHS vectors
23359 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23360 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23362 // Extract the RHS vectors
23363 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23364 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23366 // Create min/max for each subvector
23367 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23368 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23370 // Merge the result
23371 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23373 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23376 // Simplify vector selection if condition value type matches vselect
23378 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23379 assert(Cond.getValueType().isVector() &&
23380 "vector select expects a vector selector!");
23382 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23383 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23385 // Try invert the condition if true value is not all 1s and false value
23387 if (!TValIsAllOnes && !FValIsAllZeros &&
23388 // Check if the selector will be produced by CMPP*/PCMP*
23389 Cond.getOpcode() == ISD::SETCC &&
23390 // Check if SETCC has already been promoted
23391 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23392 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23393 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23395 if (TValIsAllZeros || FValIsAllOnes) {
23396 SDValue CC = Cond.getOperand(2);
23397 ISD::CondCode NewCC =
23398 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23399 Cond.getOperand(0).getValueType().isInteger());
23400 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23401 std::swap(LHS, RHS);
23402 TValIsAllOnes = FValIsAllOnes;
23403 FValIsAllZeros = TValIsAllZeros;
23407 if (TValIsAllOnes || FValIsAllZeros) {
23410 if (TValIsAllOnes && FValIsAllZeros)
23412 else if (TValIsAllOnes)
23413 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23414 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23415 else if (FValIsAllZeros)
23416 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23417 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23419 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23423 // If we know that this node is legal then we know that it is going to be
23424 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23425 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23426 // to simplify previous instructions.
23427 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23428 !DCI.isBeforeLegalize() &&
23429 // We explicitly check against v8i16 and v16i16 because, although
23430 // they're marked as Custom, they might only be legal when Cond is a
23431 // build_vector of constants. This will be taken care in a later
23433 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23434 VT != MVT::v8i16) &&
23435 // Don't optimize vector of constants. Those are handled by
23436 // the generic code and all the bits must be properly set for
23437 // the generic optimizer.
23438 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23439 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23441 // Don't optimize vector selects that map to mask-registers.
23445 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23446 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23448 APInt KnownZero, KnownOne;
23449 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23450 DCI.isBeforeLegalizeOps());
23451 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23452 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23454 // If we changed the computation somewhere in the DAG, this change
23455 // will affect all users of Cond.
23456 // Make sure it is fine and update all the nodes so that we do not
23457 // use the generic VSELECT anymore. Otherwise, we may perform
23458 // wrong optimizations as we messed up with the actual expectation
23459 // for the vector boolean values.
23460 if (Cond != TLO.Old) {
23461 // Check all uses of that condition operand to check whether it will be
23462 // consumed by non-BLEND instructions, which may depend on all bits are
23464 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23466 if (I->getOpcode() != ISD::VSELECT)
23467 // TODO: Add other opcodes eventually lowered into BLEND.
23470 // Update all the users of the condition, before committing the change,
23471 // so that the VSELECT optimizations that expect the correct vector
23472 // boolean value will not be triggered.
23473 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23475 DAG.ReplaceAllUsesOfValueWith(
23477 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23478 Cond, I->getOperand(1), I->getOperand(2)));
23479 DCI.CommitTargetLoweringOpt(TLO);
23482 // At this point, only Cond is changed. Change the condition
23483 // just for N to keep the opportunity to optimize all other
23484 // users their own way.
23485 DAG.ReplaceAllUsesOfValueWith(
23487 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23488 TLO.New, N->getOperand(1), N->getOperand(2)));
23493 // We should generate an X86ISD::BLENDI from a vselect if its argument
23494 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23495 // constants. This specific pattern gets generated when we split a
23496 // selector for a 512 bit vector in a machine without AVX512 (but with
23497 // 256-bit vectors), during legalization:
23499 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23501 // Iff we find this pattern and the build_vectors are built from
23502 // constants, we translate the vselect into a shuffle_vector that we
23503 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23504 if ((N->getOpcode() == ISD::VSELECT ||
23505 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23506 !DCI.isBeforeLegalize()) {
23507 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23508 if (Shuffle.getNode())
23515 // Check whether a boolean test is testing a boolean value generated by
23516 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23519 // Simplify the following patterns:
23520 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23521 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23522 // to (Op EFLAGS Cond)
23524 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23525 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23526 // to (Op EFLAGS !Cond)
23528 // where Op could be BRCOND or CMOV.
23530 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23531 // Quit if not CMP and SUB with its value result used.
23532 if (Cmp.getOpcode() != X86ISD::CMP &&
23533 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23536 // Quit if not used as a boolean value.
23537 if (CC != X86::COND_E && CC != X86::COND_NE)
23540 // Check CMP operands. One of them should be 0 or 1 and the other should be
23541 // an SetCC or extended from it.
23542 SDValue Op1 = Cmp.getOperand(0);
23543 SDValue Op2 = Cmp.getOperand(1);
23546 const ConstantSDNode* C = nullptr;
23547 bool needOppositeCond = (CC == X86::COND_E);
23548 bool checkAgainstTrue = false; // Is it a comparison against 1?
23550 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23552 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23554 else // Quit if all operands are not constants.
23557 if (C->getZExtValue() == 1) {
23558 needOppositeCond = !needOppositeCond;
23559 checkAgainstTrue = true;
23560 } else if (C->getZExtValue() != 0)
23561 // Quit if the constant is neither 0 or 1.
23564 bool truncatedToBoolWithAnd = false;
23565 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23566 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23567 SetCC.getOpcode() == ISD::TRUNCATE ||
23568 SetCC.getOpcode() == ISD::AND) {
23569 if (SetCC.getOpcode() == ISD::AND) {
23571 ConstantSDNode *CS;
23572 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23573 CS->getZExtValue() == 1)
23575 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23576 CS->getZExtValue() == 1)
23580 SetCC = SetCC.getOperand(OpIdx);
23581 truncatedToBoolWithAnd = true;
23583 SetCC = SetCC.getOperand(0);
23586 switch (SetCC.getOpcode()) {
23587 case X86ISD::SETCC_CARRY:
23588 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23589 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23590 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23591 // truncated to i1 using 'and'.
23592 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23594 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23595 "Invalid use of SETCC_CARRY!");
23597 case X86ISD::SETCC:
23598 // Set the condition code or opposite one if necessary.
23599 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23600 if (needOppositeCond)
23601 CC = X86::GetOppositeBranchCondition(CC);
23602 return SetCC.getOperand(1);
23603 case X86ISD::CMOV: {
23604 // Check whether false/true value has canonical one, i.e. 0 or 1.
23605 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23606 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23607 // Quit if true value is not a constant.
23610 // Quit if false value is not a constant.
23612 SDValue Op = SetCC.getOperand(0);
23613 // Skip 'zext' or 'trunc' node.
23614 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23615 Op.getOpcode() == ISD::TRUNCATE)
23616 Op = Op.getOperand(0);
23617 // A special case for rdrand/rdseed, where 0 is set if false cond is
23619 if ((Op.getOpcode() != X86ISD::RDRAND &&
23620 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23623 // Quit if false value is not the constant 0 or 1.
23624 bool FValIsFalse = true;
23625 if (FVal && FVal->getZExtValue() != 0) {
23626 if (FVal->getZExtValue() != 1)
23628 // If FVal is 1, opposite cond is needed.
23629 needOppositeCond = !needOppositeCond;
23630 FValIsFalse = false;
23632 // Quit if TVal is not the constant opposite of FVal.
23633 if (FValIsFalse && TVal->getZExtValue() != 1)
23635 if (!FValIsFalse && TVal->getZExtValue() != 0)
23637 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23638 if (needOppositeCond)
23639 CC = X86::GetOppositeBranchCondition(CC);
23640 return SetCC.getOperand(3);
23647 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23648 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23649 TargetLowering::DAGCombinerInfo &DCI,
23650 const X86Subtarget *Subtarget) {
23653 // If the flag operand isn't dead, don't touch this CMOV.
23654 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23657 SDValue FalseOp = N->getOperand(0);
23658 SDValue TrueOp = N->getOperand(1);
23659 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23660 SDValue Cond = N->getOperand(3);
23662 if (CC == X86::COND_E || CC == X86::COND_NE) {
23663 switch (Cond.getOpcode()) {
23667 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23668 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23669 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23675 Flags = checkBoolTestSetCCCombine(Cond, CC);
23676 if (Flags.getNode() &&
23677 // Extra check as FCMOV only supports a subset of X86 cond.
23678 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23679 SDValue Ops[] = { FalseOp, TrueOp,
23680 DAG.getConstant(CC, MVT::i8), Flags };
23681 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23684 // If this is a select between two integer constants, try to do some
23685 // optimizations. Note that the operands are ordered the opposite of SELECT
23687 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23688 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23689 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23690 // larger than FalseC (the false value).
23691 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23692 CC = X86::GetOppositeBranchCondition(CC);
23693 std::swap(TrueC, FalseC);
23694 std::swap(TrueOp, FalseOp);
23697 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23698 // This is efficient for any integer data type (including i8/i16) and
23700 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23701 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23702 DAG.getConstant(CC, MVT::i8), Cond);
23704 // Zero extend the condition if needed.
23705 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23707 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23708 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23709 DAG.getConstant(ShAmt, MVT::i8));
23710 if (N->getNumValues() == 2) // Dead flag value?
23711 return DCI.CombineTo(N, Cond, SDValue());
23715 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23716 // for any integer data type, including i8/i16.
23717 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23718 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23719 DAG.getConstant(CC, MVT::i8), Cond);
23721 // Zero extend the condition if needed.
23722 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23723 FalseC->getValueType(0), Cond);
23724 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23725 SDValue(FalseC, 0));
23727 if (N->getNumValues() == 2) // Dead flag value?
23728 return DCI.CombineTo(N, Cond, SDValue());
23732 // Optimize cases that will turn into an LEA instruction. This requires
23733 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23734 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23735 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23736 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23738 bool isFastMultiplier = false;
23740 switch ((unsigned char)Diff) {
23742 case 1: // result = add base, cond
23743 case 2: // result = lea base( , cond*2)
23744 case 3: // result = lea base(cond, cond*2)
23745 case 4: // result = lea base( , cond*4)
23746 case 5: // result = lea base(cond, cond*4)
23747 case 8: // result = lea base( , cond*8)
23748 case 9: // result = lea base(cond, cond*8)
23749 isFastMultiplier = true;
23754 if (isFastMultiplier) {
23755 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23756 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23757 DAG.getConstant(CC, MVT::i8), Cond);
23758 // Zero extend the condition if needed.
23759 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23761 // Scale the condition by the difference.
23763 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23764 DAG.getConstant(Diff, Cond.getValueType()));
23766 // Add the base if non-zero.
23767 if (FalseC->getAPIntValue() != 0)
23768 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23769 SDValue(FalseC, 0));
23770 if (N->getNumValues() == 2) // Dead flag value?
23771 return DCI.CombineTo(N, Cond, SDValue());
23778 // Handle these cases:
23779 // (select (x != c), e, c) -> select (x != c), e, x),
23780 // (select (x == c), c, e) -> select (x == c), x, e)
23781 // where the c is an integer constant, and the "select" is the combination
23782 // of CMOV and CMP.
23784 // The rationale for this change is that the conditional-move from a constant
23785 // needs two instructions, however, conditional-move from a register needs
23786 // only one instruction.
23788 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23789 // some instruction-combining opportunities. This opt needs to be
23790 // postponed as late as possible.
23792 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23793 // the DCI.xxxx conditions are provided to postpone the optimization as
23794 // late as possible.
23796 ConstantSDNode *CmpAgainst = nullptr;
23797 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23798 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23799 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23801 if (CC == X86::COND_NE &&
23802 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23803 CC = X86::GetOppositeBranchCondition(CC);
23804 std::swap(TrueOp, FalseOp);
23807 if (CC == X86::COND_E &&
23808 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23809 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23810 DAG.getConstant(CC, MVT::i8), Cond };
23811 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23819 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23820 const X86Subtarget *Subtarget) {
23821 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23823 default: return SDValue();
23824 // SSE/AVX/AVX2 blend intrinsics.
23825 case Intrinsic::x86_avx2_pblendvb:
23826 case Intrinsic::x86_avx2_pblendw:
23827 case Intrinsic::x86_avx2_pblendd_128:
23828 case Intrinsic::x86_avx2_pblendd_256:
23829 // Don't try to simplify this intrinsic if we don't have AVX2.
23830 if (!Subtarget->hasAVX2())
23833 case Intrinsic::x86_avx_blend_pd_256:
23834 case Intrinsic::x86_avx_blend_ps_256:
23835 case Intrinsic::x86_avx_blendv_pd_256:
23836 case Intrinsic::x86_avx_blendv_ps_256:
23837 // Don't try to simplify this intrinsic if we don't have AVX.
23838 if (!Subtarget->hasAVX())
23841 case Intrinsic::x86_sse41_pblendw:
23842 case Intrinsic::x86_sse41_blendpd:
23843 case Intrinsic::x86_sse41_blendps:
23844 case Intrinsic::x86_sse41_blendvps:
23845 case Intrinsic::x86_sse41_blendvpd:
23846 case Intrinsic::x86_sse41_pblendvb: {
23847 SDValue Op0 = N->getOperand(1);
23848 SDValue Op1 = N->getOperand(2);
23849 SDValue Mask = N->getOperand(3);
23851 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23852 if (!Subtarget->hasSSE41())
23855 // fold (blend A, A, Mask) -> A
23858 // fold (blend A, B, allZeros) -> A
23859 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23861 // fold (blend A, B, allOnes) -> B
23862 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23865 // Simplify the case where the mask is a constant i32 value.
23866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23867 if (C->isNullValue())
23869 if (C->isAllOnesValue())
23876 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23877 case Intrinsic::x86_sse2_psrai_w:
23878 case Intrinsic::x86_sse2_psrai_d:
23879 case Intrinsic::x86_avx2_psrai_w:
23880 case Intrinsic::x86_avx2_psrai_d:
23881 case Intrinsic::x86_sse2_psra_w:
23882 case Intrinsic::x86_sse2_psra_d:
23883 case Intrinsic::x86_avx2_psra_w:
23884 case Intrinsic::x86_avx2_psra_d: {
23885 SDValue Op0 = N->getOperand(1);
23886 SDValue Op1 = N->getOperand(2);
23887 EVT VT = Op0.getValueType();
23888 assert(VT.isVector() && "Expected a vector type!");
23890 if (isa<BuildVectorSDNode>(Op1))
23891 Op1 = Op1.getOperand(0);
23893 if (!isa<ConstantSDNode>(Op1))
23896 EVT SVT = VT.getVectorElementType();
23897 unsigned SVTBits = SVT.getSizeInBits();
23899 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23900 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23901 uint64_t ShAmt = C.getZExtValue();
23903 // Don't try to convert this shift into a ISD::SRA if the shift
23904 // count is bigger than or equal to the element size.
23905 if (ShAmt >= SVTBits)
23908 // Trivial case: if the shift count is zero, then fold this
23909 // into the first operand.
23913 // Replace this packed shift intrinsic with a target independent
23915 SDValue Splat = DAG.getConstant(C, VT);
23916 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23921 /// PerformMulCombine - Optimize a single multiply with constant into two
23922 /// in order to implement it with two cheaper instructions, e.g.
23923 /// LEA + SHL, LEA + LEA.
23924 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23925 TargetLowering::DAGCombinerInfo &DCI) {
23926 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23929 EVT VT = N->getValueType(0);
23930 if (VT != MVT::i64)
23933 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23936 uint64_t MulAmt = C->getZExtValue();
23937 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23940 uint64_t MulAmt1 = 0;
23941 uint64_t MulAmt2 = 0;
23942 if ((MulAmt % 9) == 0) {
23944 MulAmt2 = MulAmt / 9;
23945 } else if ((MulAmt % 5) == 0) {
23947 MulAmt2 = MulAmt / 5;
23948 } else if ((MulAmt % 3) == 0) {
23950 MulAmt2 = MulAmt / 3;
23953 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23956 if (isPowerOf2_64(MulAmt2) &&
23957 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23958 // If second multiplifer is pow2, issue it first. We want the multiply by
23959 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23961 std::swap(MulAmt1, MulAmt2);
23964 if (isPowerOf2_64(MulAmt1))
23965 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23966 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23968 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23969 DAG.getConstant(MulAmt1, VT));
23971 if (isPowerOf2_64(MulAmt2))
23972 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23973 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23975 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23976 DAG.getConstant(MulAmt2, VT));
23978 // Do not add new nodes to DAG combiner worklist.
23979 DCI.CombineTo(N, NewMul, false);
23984 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23985 SDValue N0 = N->getOperand(0);
23986 SDValue N1 = N->getOperand(1);
23987 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23988 EVT VT = N0.getValueType();
23990 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23991 // since the result of setcc_c is all zero's or all ones.
23992 if (VT.isInteger() && !VT.isVector() &&
23993 N1C && N0.getOpcode() == ISD::AND &&
23994 N0.getOperand(1).getOpcode() == ISD::Constant) {
23995 SDValue N00 = N0.getOperand(0);
23996 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23997 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23998 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23999 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
24000 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24001 APInt ShAmt = N1C->getAPIntValue();
24002 Mask = Mask.shl(ShAmt);
24004 return DAG.getNode(ISD::AND, SDLoc(N), VT,
24005 N00, DAG.getConstant(Mask, VT));
24009 // Hardware support for vector shifts is sparse which makes us scalarize the
24010 // vector operations in many cases. Also, on sandybridge ADD is faster than
24012 // (shl V, 1) -> add V,V
24013 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24014 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24015 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24016 // We shift all of the values by one. In many cases we do not have
24017 // hardware support for this operation. This is better expressed as an ADD
24019 if (N1SplatC->getZExtValue() == 1)
24020 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24026 /// \brief Returns a vector of 0s if the node in input is a vector logical
24027 /// shift by a constant amount which is known to be bigger than or equal
24028 /// to the vector element size in bits.
24029 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24030 const X86Subtarget *Subtarget) {
24031 EVT VT = N->getValueType(0);
24033 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24034 (!Subtarget->hasInt256() ||
24035 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24038 SDValue Amt = N->getOperand(1);
24040 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24041 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24042 APInt ShiftAmt = AmtSplat->getAPIntValue();
24043 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24045 // SSE2/AVX2 logical shifts always return a vector of 0s
24046 // if the shift amount is bigger than or equal to
24047 // the element size. The constant shift amount will be
24048 // encoded as a 8-bit immediate.
24049 if (ShiftAmt.trunc(8).uge(MaxAmount))
24050 return getZeroVector(VT, Subtarget, DAG, DL);
24056 /// PerformShiftCombine - Combine shifts.
24057 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24058 TargetLowering::DAGCombinerInfo &DCI,
24059 const X86Subtarget *Subtarget) {
24060 if (N->getOpcode() == ISD::SHL) {
24061 SDValue V = PerformSHLCombine(N, DAG);
24062 if (V.getNode()) return V;
24065 if (N->getOpcode() != ISD::SRA) {
24066 // Try to fold this logical shift into a zero vector.
24067 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24068 if (V.getNode()) return V;
24074 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24075 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24076 // and friends. Likewise for OR -> CMPNEQSS.
24077 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24078 TargetLowering::DAGCombinerInfo &DCI,
24079 const X86Subtarget *Subtarget) {
24082 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24083 // we're requiring SSE2 for both.
24084 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24085 SDValue N0 = N->getOperand(0);
24086 SDValue N1 = N->getOperand(1);
24087 SDValue CMP0 = N0->getOperand(1);
24088 SDValue CMP1 = N1->getOperand(1);
24091 // The SETCCs should both refer to the same CMP.
24092 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24095 SDValue CMP00 = CMP0->getOperand(0);
24096 SDValue CMP01 = CMP0->getOperand(1);
24097 EVT VT = CMP00.getValueType();
24099 if (VT == MVT::f32 || VT == MVT::f64) {
24100 bool ExpectingFlags = false;
24101 // Check for any users that want flags:
24102 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24103 !ExpectingFlags && UI != UE; ++UI)
24104 switch (UI->getOpcode()) {
24109 ExpectingFlags = true;
24111 case ISD::CopyToReg:
24112 case ISD::SIGN_EXTEND:
24113 case ISD::ZERO_EXTEND:
24114 case ISD::ANY_EXTEND:
24118 if (!ExpectingFlags) {
24119 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24120 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24122 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24123 X86::CondCode tmp = cc0;
24128 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24129 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24130 // FIXME: need symbolic constants for these magic numbers.
24131 // See X86ATTInstPrinter.cpp:printSSECC().
24132 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24133 if (Subtarget->hasAVX512()) {
24134 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24135 CMP01, DAG.getConstant(x86cc, MVT::i8));
24136 if (N->getValueType(0) != MVT::i1)
24137 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24141 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24142 CMP00.getValueType(), CMP00, CMP01,
24143 DAG.getConstant(x86cc, MVT::i8));
24145 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24146 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24148 if (is64BitFP && !Subtarget->is64Bit()) {
24149 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24150 // 64-bit integer, since that's not a legal type. Since
24151 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24152 // bits, but can do this little dance to extract the lowest 32 bits
24153 // and work with those going forward.
24154 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24156 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24158 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24159 Vector32, DAG.getIntPtrConstant(0));
24163 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24164 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24165 DAG.getConstant(1, IntVT));
24166 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24167 return OneBitOfTruth;
24175 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24176 /// so it can be folded inside ANDNP.
24177 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24178 EVT VT = N->getValueType(0);
24180 // Match direct AllOnes for 128 and 256-bit vectors
24181 if (ISD::isBuildVectorAllOnes(N))
24184 // Look through a bit convert.
24185 if (N->getOpcode() == ISD::BITCAST)
24186 N = N->getOperand(0).getNode();
24188 // Sometimes the operand may come from a insert_subvector building a 256-bit
24190 if (VT.is256BitVector() &&
24191 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24192 SDValue V1 = N->getOperand(0);
24193 SDValue V2 = N->getOperand(1);
24195 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24196 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24197 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24198 ISD::isBuildVectorAllOnes(V2.getNode()))
24205 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24206 // register. In most cases we actually compare or select YMM-sized registers
24207 // and mixing the two types creates horrible code. This method optimizes
24208 // some of the transition sequences.
24209 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24210 TargetLowering::DAGCombinerInfo &DCI,
24211 const X86Subtarget *Subtarget) {
24212 EVT VT = N->getValueType(0);
24213 if (!VT.is256BitVector())
24216 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24217 N->getOpcode() == ISD::ZERO_EXTEND ||
24218 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24220 SDValue Narrow = N->getOperand(0);
24221 EVT NarrowVT = Narrow->getValueType(0);
24222 if (!NarrowVT.is128BitVector())
24225 if (Narrow->getOpcode() != ISD::XOR &&
24226 Narrow->getOpcode() != ISD::AND &&
24227 Narrow->getOpcode() != ISD::OR)
24230 SDValue N0 = Narrow->getOperand(0);
24231 SDValue N1 = Narrow->getOperand(1);
24234 // The Left side has to be a trunc.
24235 if (N0.getOpcode() != ISD::TRUNCATE)
24238 // The type of the truncated inputs.
24239 EVT WideVT = N0->getOperand(0)->getValueType(0);
24243 // The right side has to be a 'trunc' or a constant vector.
24244 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24245 ConstantSDNode *RHSConstSplat = nullptr;
24246 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24247 RHSConstSplat = RHSBV->getConstantSplatNode();
24248 if (!RHSTrunc && !RHSConstSplat)
24251 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24253 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24256 // Set N0 and N1 to hold the inputs to the new wide operation.
24257 N0 = N0->getOperand(0);
24258 if (RHSConstSplat) {
24259 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24260 SDValue(RHSConstSplat, 0));
24261 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24262 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24263 } else if (RHSTrunc) {
24264 N1 = N1->getOperand(0);
24267 // Generate the wide operation.
24268 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24269 unsigned Opcode = N->getOpcode();
24271 case ISD::ANY_EXTEND:
24273 case ISD::ZERO_EXTEND: {
24274 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24275 APInt Mask = APInt::getAllOnesValue(InBits);
24276 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24277 return DAG.getNode(ISD::AND, DL, VT,
24278 Op, DAG.getConstant(Mask, VT));
24280 case ISD::SIGN_EXTEND:
24281 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24282 Op, DAG.getValueType(NarrowVT));
24284 llvm_unreachable("Unexpected opcode");
24288 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24289 TargetLowering::DAGCombinerInfo &DCI,
24290 const X86Subtarget *Subtarget) {
24291 EVT VT = N->getValueType(0);
24292 if (DCI.isBeforeLegalizeOps())
24295 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24299 // Create BEXTR instructions
24300 // BEXTR is ((X >> imm) & (2**size-1))
24301 if (VT == MVT::i32 || VT == MVT::i64) {
24302 SDValue N0 = N->getOperand(0);
24303 SDValue N1 = N->getOperand(1);
24306 // Check for BEXTR.
24307 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24308 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24309 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24310 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24311 if (MaskNode && ShiftNode) {
24312 uint64_t Mask = MaskNode->getZExtValue();
24313 uint64_t Shift = ShiftNode->getZExtValue();
24314 if (isMask_64(Mask)) {
24315 uint64_t MaskSize = CountPopulation_64(Mask);
24316 if (Shift + MaskSize <= VT.getSizeInBits())
24317 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24318 DAG.getConstant(Shift | (MaskSize << 8), VT));
24326 // Want to form ANDNP nodes:
24327 // 1) In the hopes of then easily combining them with OR and AND nodes
24328 // to form PBLEND/PSIGN.
24329 // 2) To match ANDN packed intrinsics
24330 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24333 SDValue N0 = N->getOperand(0);
24334 SDValue N1 = N->getOperand(1);
24337 // Check LHS for vnot
24338 if (N0.getOpcode() == ISD::XOR &&
24339 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24340 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24341 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24343 // Check RHS for vnot
24344 if (N1.getOpcode() == ISD::XOR &&
24345 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24346 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24347 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24352 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24353 TargetLowering::DAGCombinerInfo &DCI,
24354 const X86Subtarget *Subtarget) {
24355 if (DCI.isBeforeLegalizeOps())
24358 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24362 SDValue N0 = N->getOperand(0);
24363 SDValue N1 = N->getOperand(1);
24364 EVT VT = N->getValueType(0);
24366 // look for psign/blend
24367 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24368 if (!Subtarget->hasSSSE3() ||
24369 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24372 // Canonicalize pandn to RHS
24373 if (N0.getOpcode() == X86ISD::ANDNP)
24375 // or (and (m, y), (pandn m, x))
24376 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24377 SDValue Mask = N1.getOperand(0);
24378 SDValue X = N1.getOperand(1);
24380 if (N0.getOperand(0) == Mask)
24381 Y = N0.getOperand(1);
24382 if (N0.getOperand(1) == Mask)
24383 Y = N0.getOperand(0);
24385 // Check to see if the mask appeared in both the AND and ANDNP and
24389 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24390 // Look through mask bitcast.
24391 if (Mask.getOpcode() == ISD::BITCAST)
24392 Mask = Mask.getOperand(0);
24393 if (X.getOpcode() == ISD::BITCAST)
24394 X = X.getOperand(0);
24395 if (Y.getOpcode() == ISD::BITCAST)
24396 Y = Y.getOperand(0);
24398 EVT MaskVT = Mask.getValueType();
24400 // Validate that the Mask operand is a vector sra node.
24401 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24402 // there is no psrai.b
24403 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24404 unsigned SraAmt = ~0;
24405 if (Mask.getOpcode() == ISD::SRA) {
24406 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24407 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24408 SraAmt = AmtConst->getZExtValue();
24409 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24410 SDValue SraC = Mask.getOperand(1);
24411 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24413 if ((SraAmt + 1) != EltBits)
24418 // Now we know we at least have a plendvb with the mask val. See if
24419 // we can form a psignb/w/d.
24420 // psign = x.type == y.type == mask.type && y = sub(0, x);
24421 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24422 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24423 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24424 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24425 "Unsupported VT for PSIGN");
24426 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24427 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24429 // PBLENDVB only available on SSE 4.1
24430 if (!Subtarget->hasSSE41())
24433 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24435 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24436 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24437 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24438 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24439 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24443 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24446 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24447 MachineFunction &MF = DAG.getMachineFunction();
24448 bool OptForSize = MF.getFunction()->getAttributes().
24449 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24451 // SHLD/SHRD instructions have lower register pressure, but on some
24452 // platforms they have higher latency than the equivalent
24453 // series of shifts/or that would otherwise be generated.
24454 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24455 // have higher latencies and we are not optimizing for size.
24456 if (!OptForSize && Subtarget->isSHLDSlow())
24459 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24461 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24463 if (!N0.hasOneUse() || !N1.hasOneUse())
24466 SDValue ShAmt0 = N0.getOperand(1);
24467 if (ShAmt0.getValueType() != MVT::i8)
24469 SDValue ShAmt1 = N1.getOperand(1);
24470 if (ShAmt1.getValueType() != MVT::i8)
24472 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24473 ShAmt0 = ShAmt0.getOperand(0);
24474 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24475 ShAmt1 = ShAmt1.getOperand(0);
24478 unsigned Opc = X86ISD::SHLD;
24479 SDValue Op0 = N0.getOperand(0);
24480 SDValue Op1 = N1.getOperand(0);
24481 if (ShAmt0.getOpcode() == ISD::SUB) {
24482 Opc = X86ISD::SHRD;
24483 std::swap(Op0, Op1);
24484 std::swap(ShAmt0, ShAmt1);
24487 unsigned Bits = VT.getSizeInBits();
24488 if (ShAmt1.getOpcode() == ISD::SUB) {
24489 SDValue Sum = ShAmt1.getOperand(0);
24490 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24491 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24492 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24493 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24494 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24495 return DAG.getNode(Opc, DL, VT,
24497 DAG.getNode(ISD::TRUNCATE, DL,
24500 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24501 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24503 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24504 return DAG.getNode(Opc, DL, VT,
24505 N0.getOperand(0), N1.getOperand(0),
24506 DAG.getNode(ISD::TRUNCATE, DL,
24513 // Generate NEG and CMOV for integer abs.
24514 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24515 EVT VT = N->getValueType(0);
24517 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24518 // 8-bit integer abs to NEG and CMOV.
24519 if (VT.isInteger() && VT.getSizeInBits() == 8)
24522 SDValue N0 = N->getOperand(0);
24523 SDValue N1 = N->getOperand(1);
24526 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24527 // and change it to SUB and CMOV.
24528 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24529 N0.getOpcode() == ISD::ADD &&
24530 N0.getOperand(1) == N1 &&
24531 N1.getOpcode() == ISD::SRA &&
24532 N1.getOperand(0) == N0.getOperand(0))
24533 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24534 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24535 // Generate SUB & CMOV.
24536 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24537 DAG.getConstant(0, VT), N0.getOperand(0));
24539 SDValue Ops[] = { N0.getOperand(0), Neg,
24540 DAG.getConstant(X86::COND_GE, MVT::i8),
24541 SDValue(Neg.getNode(), 1) };
24542 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24547 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24548 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24549 TargetLowering::DAGCombinerInfo &DCI,
24550 const X86Subtarget *Subtarget) {
24551 if (DCI.isBeforeLegalizeOps())
24554 if (Subtarget->hasCMov()) {
24555 SDValue RV = performIntegerAbsCombine(N, DAG);
24563 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24564 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24565 TargetLowering::DAGCombinerInfo &DCI,
24566 const X86Subtarget *Subtarget) {
24567 LoadSDNode *Ld = cast<LoadSDNode>(N);
24568 EVT RegVT = Ld->getValueType(0);
24569 EVT MemVT = Ld->getMemoryVT();
24571 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24573 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24574 // into two 16-byte operations.
24575 ISD::LoadExtType Ext = Ld->getExtensionType();
24576 unsigned Alignment = Ld->getAlignment();
24577 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24578 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24579 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24580 unsigned NumElems = RegVT.getVectorNumElements();
24584 SDValue Ptr = Ld->getBasePtr();
24585 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24587 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24589 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24590 Ld->getPointerInfo(), Ld->isVolatile(),
24591 Ld->isNonTemporal(), Ld->isInvariant(),
24593 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24594 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24595 Ld->getPointerInfo(), Ld->isVolatile(),
24596 Ld->isNonTemporal(), Ld->isInvariant(),
24597 std::min(16U, Alignment));
24598 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24600 Load2.getValue(1));
24602 SDValue NewVec = DAG.getUNDEF(RegVT);
24603 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24604 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24605 return DCI.CombineTo(N, NewVec, TF, true);
24611 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24612 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24613 const X86Subtarget *Subtarget) {
24614 StoreSDNode *St = cast<StoreSDNode>(N);
24615 EVT VT = St->getValue().getValueType();
24616 EVT StVT = St->getMemoryVT();
24618 SDValue StoredVal = St->getOperand(1);
24619 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24621 // If we are saving a concatenation of two XMM registers and 32-byte stores
24622 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24623 unsigned Alignment = St->getAlignment();
24624 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24625 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24626 StVT == VT && !IsAligned) {
24627 unsigned NumElems = VT.getVectorNumElements();
24631 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24632 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24634 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24635 SDValue Ptr0 = St->getBasePtr();
24636 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24638 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24639 St->getPointerInfo(), St->isVolatile(),
24640 St->isNonTemporal(), Alignment);
24641 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24642 St->getPointerInfo(), St->isVolatile(),
24643 St->isNonTemporal(),
24644 std::min(16U, Alignment));
24645 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24648 // Optimize trunc store (of multiple scalars) to shuffle and store.
24649 // First, pack all of the elements in one place. Next, store to memory
24650 // in fewer chunks.
24651 if (St->isTruncatingStore() && VT.isVector()) {
24652 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24653 unsigned NumElems = VT.getVectorNumElements();
24654 assert(StVT != VT && "Cannot truncate to the same type");
24655 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24656 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24658 // From, To sizes and ElemCount must be pow of two
24659 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24660 // We are going to use the original vector elt for storing.
24661 // Accumulated smaller vector elements must be a multiple of the store size.
24662 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24664 unsigned SizeRatio = FromSz / ToSz;
24666 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24668 // Create a type on which we perform the shuffle
24669 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24670 StVT.getScalarType(), NumElems*SizeRatio);
24672 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24674 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24675 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24676 for (unsigned i = 0; i != NumElems; ++i)
24677 ShuffleVec[i] = i * SizeRatio;
24679 // Can't shuffle using an illegal type.
24680 if (!TLI.isTypeLegal(WideVecVT))
24683 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24684 DAG.getUNDEF(WideVecVT),
24686 // At this point all of the data is stored at the bottom of the
24687 // register. We now need to save it to mem.
24689 // Find the largest store unit
24690 MVT StoreType = MVT::i8;
24691 for (MVT Tp : MVT::integer_valuetypes()) {
24692 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24696 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24697 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24698 (64 <= NumElems * ToSz))
24699 StoreType = MVT::f64;
24701 // Bitcast the original vector into a vector of store-size units
24702 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24703 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24704 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24705 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24706 SmallVector<SDValue, 8> Chains;
24707 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24708 TLI.getPointerTy());
24709 SDValue Ptr = St->getBasePtr();
24711 // Perform one or more big stores into memory.
24712 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24713 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24714 StoreType, ShuffWide,
24715 DAG.getIntPtrConstant(i));
24716 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24717 St->getPointerInfo(), St->isVolatile(),
24718 St->isNonTemporal(), St->getAlignment());
24719 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24720 Chains.push_back(Ch);
24723 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24726 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24727 // the FP state in cases where an emms may be missing.
24728 // A preferable solution to the general problem is to figure out the right
24729 // places to insert EMMS. This qualifies as a quick hack.
24731 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24732 if (VT.getSizeInBits() != 64)
24735 const Function *F = DAG.getMachineFunction().getFunction();
24736 bool NoImplicitFloatOps = F->getAttributes().
24737 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24738 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24739 && Subtarget->hasSSE2();
24740 if ((VT.isVector() ||
24741 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24742 isa<LoadSDNode>(St->getValue()) &&
24743 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24744 St->getChain().hasOneUse() && !St->isVolatile()) {
24745 SDNode* LdVal = St->getValue().getNode();
24746 LoadSDNode *Ld = nullptr;
24747 int TokenFactorIndex = -1;
24748 SmallVector<SDValue, 8> Ops;
24749 SDNode* ChainVal = St->getChain().getNode();
24750 // Must be a store of a load. We currently handle two cases: the load
24751 // is a direct child, and it's under an intervening TokenFactor. It is
24752 // possible to dig deeper under nested TokenFactors.
24753 if (ChainVal == LdVal)
24754 Ld = cast<LoadSDNode>(St->getChain());
24755 else if (St->getValue().hasOneUse() &&
24756 ChainVal->getOpcode() == ISD::TokenFactor) {
24757 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24758 if (ChainVal->getOperand(i).getNode() == LdVal) {
24759 TokenFactorIndex = i;
24760 Ld = cast<LoadSDNode>(St->getValue());
24762 Ops.push_back(ChainVal->getOperand(i));
24766 if (!Ld || !ISD::isNormalLoad(Ld))
24769 // If this is not the MMX case, i.e. we are just turning i64 load/store
24770 // into f64 load/store, avoid the transformation if there are multiple
24771 // uses of the loaded value.
24772 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24777 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24778 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24780 if (Subtarget->is64Bit() || F64IsLegal) {
24781 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24782 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24783 Ld->getPointerInfo(), Ld->isVolatile(),
24784 Ld->isNonTemporal(), Ld->isInvariant(),
24785 Ld->getAlignment());
24786 SDValue NewChain = NewLd.getValue(1);
24787 if (TokenFactorIndex != -1) {
24788 Ops.push_back(NewChain);
24789 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24791 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24792 St->getPointerInfo(),
24793 St->isVolatile(), St->isNonTemporal(),
24794 St->getAlignment());
24797 // Otherwise, lower to two pairs of 32-bit loads / stores.
24798 SDValue LoAddr = Ld->getBasePtr();
24799 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24800 DAG.getConstant(4, MVT::i32));
24802 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24803 Ld->getPointerInfo(),
24804 Ld->isVolatile(), Ld->isNonTemporal(),
24805 Ld->isInvariant(), Ld->getAlignment());
24806 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24807 Ld->getPointerInfo().getWithOffset(4),
24808 Ld->isVolatile(), Ld->isNonTemporal(),
24810 MinAlign(Ld->getAlignment(), 4));
24812 SDValue NewChain = LoLd.getValue(1);
24813 if (TokenFactorIndex != -1) {
24814 Ops.push_back(LoLd);
24815 Ops.push_back(HiLd);
24816 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24819 LoAddr = St->getBasePtr();
24820 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24821 DAG.getConstant(4, MVT::i32));
24823 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24824 St->getPointerInfo(),
24825 St->isVolatile(), St->isNonTemporal(),
24826 St->getAlignment());
24827 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24828 St->getPointerInfo().getWithOffset(4),
24830 St->isNonTemporal(),
24831 MinAlign(St->getAlignment(), 4));
24832 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24837 /// Return 'true' if this vector operation is "horizontal"
24838 /// and return the operands for the horizontal operation in LHS and RHS. A
24839 /// horizontal operation performs the binary operation on successive elements
24840 /// of its first operand, then on successive elements of its second operand,
24841 /// returning the resulting values in a vector. For example, if
24842 /// A = < float a0, float a1, float a2, float a3 >
24844 /// B = < float b0, float b1, float b2, float b3 >
24845 /// then the result of doing a horizontal operation on A and B is
24846 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24847 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24848 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24849 /// set to A, RHS to B, and the routine returns 'true'.
24850 /// Note that the binary operation should have the property that if one of the
24851 /// operands is UNDEF then the result is UNDEF.
24852 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24853 // Look for the following pattern: if
24854 // A = < float a0, float a1, float a2, float a3 >
24855 // B = < float b0, float b1, float b2, float b3 >
24857 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24858 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24859 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24860 // which is A horizontal-op B.
24862 // At least one of the operands should be a vector shuffle.
24863 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24864 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24867 MVT VT = LHS.getSimpleValueType();
24869 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24870 "Unsupported vector type for horizontal add/sub");
24872 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24873 // operate independently on 128-bit lanes.
24874 unsigned NumElts = VT.getVectorNumElements();
24875 unsigned NumLanes = VT.getSizeInBits()/128;
24876 unsigned NumLaneElts = NumElts / NumLanes;
24877 assert((NumLaneElts % 2 == 0) &&
24878 "Vector type should have an even number of elements in each lane");
24879 unsigned HalfLaneElts = NumLaneElts/2;
24881 // View LHS in the form
24882 // LHS = VECTOR_SHUFFLE A, B, LMask
24883 // If LHS is not a shuffle then pretend it is the shuffle
24884 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24885 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24888 SmallVector<int, 16> LMask(NumElts);
24889 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24890 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24891 A = LHS.getOperand(0);
24892 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24893 B = LHS.getOperand(1);
24894 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24895 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24897 if (LHS.getOpcode() != ISD::UNDEF)
24899 for (unsigned i = 0; i != NumElts; ++i)
24903 // Likewise, view RHS in the form
24904 // RHS = VECTOR_SHUFFLE C, D, RMask
24906 SmallVector<int, 16> RMask(NumElts);
24907 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24908 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24909 C = RHS.getOperand(0);
24910 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24911 D = RHS.getOperand(1);
24912 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24913 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24915 if (RHS.getOpcode() != ISD::UNDEF)
24917 for (unsigned i = 0; i != NumElts; ++i)
24921 // Check that the shuffles are both shuffling the same vectors.
24922 if (!(A == C && B == D) && !(A == D && B == C))
24925 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24926 if (!A.getNode() && !B.getNode())
24929 // If A and B occur in reverse order in RHS, then "swap" them (which means
24930 // rewriting the mask).
24932 CommuteVectorShuffleMask(RMask, NumElts);
24934 // At this point LHS and RHS are equivalent to
24935 // LHS = VECTOR_SHUFFLE A, B, LMask
24936 // RHS = VECTOR_SHUFFLE A, B, RMask
24937 // Check that the masks correspond to performing a horizontal operation.
24938 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24939 for (unsigned i = 0; i != NumLaneElts; ++i) {
24940 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24942 // Ignore any UNDEF components.
24943 if (LIdx < 0 || RIdx < 0 ||
24944 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24945 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24948 // Check that successive elements are being operated on. If not, this is
24949 // not a horizontal operation.
24950 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24951 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24952 if (!(LIdx == Index && RIdx == Index + 1) &&
24953 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24958 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24959 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24963 /// Do target-specific dag combines on floating point adds.
24964 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24965 const X86Subtarget *Subtarget) {
24966 EVT VT = N->getValueType(0);
24967 SDValue LHS = N->getOperand(0);
24968 SDValue RHS = N->getOperand(1);
24970 // Try to synthesize horizontal adds from adds of shuffles.
24971 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24972 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24973 isHorizontalBinOp(LHS, RHS, true))
24974 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24978 /// Do target-specific dag combines on floating point subs.
24979 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24980 const X86Subtarget *Subtarget) {
24981 EVT VT = N->getValueType(0);
24982 SDValue LHS = N->getOperand(0);
24983 SDValue RHS = N->getOperand(1);
24985 // Try to synthesize horizontal subs from subs of shuffles.
24986 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24987 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24988 isHorizontalBinOp(LHS, RHS, false))
24989 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24993 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24994 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24995 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24996 // F[X]OR(0.0, x) -> x
24997 // F[X]OR(x, 0.0) -> x
24998 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24999 if (C->getValueAPF().isPosZero())
25000 return N->getOperand(1);
25001 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25002 if (C->getValueAPF().isPosZero())
25003 return N->getOperand(0);
25007 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25008 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25009 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25011 // Only perform optimizations if UnsafeMath is used.
25012 if (!DAG.getTarget().Options.UnsafeFPMath)
25015 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25016 // into FMINC and FMAXC, which are Commutative operations.
25017 unsigned NewOp = 0;
25018 switch (N->getOpcode()) {
25019 default: llvm_unreachable("unknown opcode");
25020 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25021 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25024 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25025 N->getOperand(0), N->getOperand(1));
25028 /// Do target-specific dag combines on X86ISD::FAND nodes.
25029 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25030 // FAND(0.0, x) -> 0.0
25031 // FAND(x, 0.0) -> 0.0
25032 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25033 if (C->getValueAPF().isPosZero())
25034 return N->getOperand(0);
25035 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25036 if (C->getValueAPF().isPosZero())
25037 return N->getOperand(1);
25041 /// Do target-specific dag combines on X86ISD::FANDN nodes
25042 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25043 // FANDN(x, 0.0) -> 0.0
25044 // FANDN(0.0, x) -> x
25045 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25046 if (C->getValueAPF().isPosZero())
25047 return N->getOperand(1);
25048 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25049 if (C->getValueAPF().isPosZero())
25050 return N->getOperand(1);
25054 static SDValue PerformBTCombine(SDNode *N,
25056 TargetLowering::DAGCombinerInfo &DCI) {
25057 // BT ignores high bits in the bit index operand.
25058 SDValue Op1 = N->getOperand(1);
25059 if (Op1.hasOneUse()) {
25060 unsigned BitWidth = Op1.getValueSizeInBits();
25061 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25062 APInt KnownZero, KnownOne;
25063 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25064 !DCI.isBeforeLegalizeOps());
25065 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25066 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25067 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25068 DCI.CommitTargetLoweringOpt(TLO);
25073 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25074 SDValue Op = N->getOperand(0);
25075 if (Op.getOpcode() == ISD::BITCAST)
25076 Op = Op.getOperand(0);
25077 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25078 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25079 VT.getVectorElementType().getSizeInBits() ==
25080 OpVT.getVectorElementType().getSizeInBits()) {
25081 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25086 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25087 const X86Subtarget *Subtarget) {
25088 EVT VT = N->getValueType(0);
25089 if (!VT.isVector())
25092 SDValue N0 = N->getOperand(0);
25093 SDValue N1 = N->getOperand(1);
25094 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25097 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25098 // both SSE and AVX2 since there is no sign-extended shift right
25099 // operation on a vector with 64-bit elements.
25100 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25101 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25102 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25103 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25104 SDValue N00 = N0.getOperand(0);
25106 // EXTLOAD has a better solution on AVX2,
25107 // it may be replaced with X86ISD::VSEXT node.
25108 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25109 if (!ISD::isNormalLoad(N00.getNode()))
25112 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25113 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25115 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25121 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25122 TargetLowering::DAGCombinerInfo &DCI,
25123 const X86Subtarget *Subtarget) {
25124 SDValue N0 = N->getOperand(0);
25125 EVT VT = N->getValueType(0);
25127 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25128 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25129 // This exposes the sext to the sdivrem lowering, so that it directly extends
25130 // from AH (which we otherwise need to do contortions to access).
25131 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25132 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25134 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25135 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25136 N0.getOperand(0), N0.getOperand(1));
25137 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25138 return R.getValue(1);
25141 if (!DCI.isBeforeLegalizeOps())
25144 if (!Subtarget->hasFp256())
25147 if (VT.isVector() && VT.getSizeInBits() == 256) {
25148 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25156 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25157 const X86Subtarget* Subtarget) {
25159 EVT VT = N->getValueType(0);
25161 // Let legalize expand this if it isn't a legal type yet.
25162 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25165 EVT ScalarVT = VT.getScalarType();
25166 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25167 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25170 SDValue A = N->getOperand(0);
25171 SDValue B = N->getOperand(1);
25172 SDValue C = N->getOperand(2);
25174 bool NegA = (A.getOpcode() == ISD::FNEG);
25175 bool NegB = (B.getOpcode() == ISD::FNEG);
25176 bool NegC = (C.getOpcode() == ISD::FNEG);
25178 // Negative multiplication when NegA xor NegB
25179 bool NegMul = (NegA != NegB);
25181 A = A.getOperand(0);
25183 B = B.getOperand(0);
25185 C = C.getOperand(0);
25189 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25191 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25193 return DAG.getNode(Opcode, dl, VT, A, B, C);
25196 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25197 TargetLowering::DAGCombinerInfo &DCI,
25198 const X86Subtarget *Subtarget) {
25199 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25200 // (and (i32 x86isd::setcc_carry), 1)
25201 // This eliminates the zext. This transformation is necessary because
25202 // ISD::SETCC is always legalized to i8.
25204 SDValue N0 = N->getOperand(0);
25205 EVT VT = N->getValueType(0);
25207 if (N0.getOpcode() == ISD::AND &&
25209 N0.getOperand(0).hasOneUse()) {
25210 SDValue N00 = N0.getOperand(0);
25211 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25212 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25213 if (!C || C->getZExtValue() != 1)
25215 return DAG.getNode(ISD::AND, dl, VT,
25216 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25217 N00.getOperand(0), N00.getOperand(1)),
25218 DAG.getConstant(1, VT));
25222 if (N0.getOpcode() == ISD::TRUNCATE &&
25224 N0.getOperand(0).hasOneUse()) {
25225 SDValue N00 = N0.getOperand(0);
25226 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25227 return DAG.getNode(ISD::AND, dl, VT,
25228 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25229 N00.getOperand(0), N00.getOperand(1)),
25230 DAG.getConstant(1, VT));
25233 if (VT.is256BitVector()) {
25234 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25239 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25240 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25241 // This exposes the zext to the udivrem lowering, so that it directly extends
25242 // from AH (which we otherwise need to do contortions to access).
25243 if (N0.getOpcode() == ISD::UDIVREM &&
25244 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25245 (VT == MVT::i32 || VT == MVT::i64)) {
25246 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25247 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25248 N0.getOperand(0), N0.getOperand(1));
25249 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25250 return R.getValue(1);
25256 // Optimize x == -y --> x+y == 0
25257 // x != -y --> x+y != 0
25258 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25259 const X86Subtarget* Subtarget) {
25260 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25261 SDValue LHS = N->getOperand(0);
25262 SDValue RHS = N->getOperand(1);
25263 EVT VT = N->getValueType(0);
25266 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25267 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25268 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25269 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25270 LHS.getValueType(), RHS, LHS.getOperand(1));
25271 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25272 addV, DAG.getConstant(0, addV.getValueType()), CC);
25274 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25275 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25276 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25277 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25278 RHS.getValueType(), LHS, RHS.getOperand(1));
25279 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25280 addV, DAG.getConstant(0, addV.getValueType()), CC);
25283 if (VT.getScalarType() == MVT::i1) {
25284 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25285 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25286 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25287 if (!IsSEXT0 && !IsVZero0)
25289 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25290 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25291 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25293 if (!IsSEXT1 && !IsVZero1)
25296 if (IsSEXT0 && IsVZero1) {
25297 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25298 if (CC == ISD::SETEQ)
25299 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25300 return LHS.getOperand(0);
25302 if (IsSEXT1 && IsVZero0) {
25303 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25304 if (CC == ISD::SETEQ)
25305 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25306 return RHS.getOperand(0);
25313 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25314 const X86Subtarget *Subtarget) {
25316 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25317 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25318 "X86insertps is only defined for v4x32");
25320 SDValue Ld = N->getOperand(1);
25321 if (MayFoldLoad(Ld)) {
25322 // Extract the countS bits from the immediate so we can get the proper
25323 // address when narrowing the vector load to a specific element.
25324 // When the second source op is a memory address, interps doesn't use
25325 // countS and just gets an f32 from that address.
25326 unsigned DestIndex =
25327 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25328 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25332 // Create this as a scalar to vector to match the instruction pattern.
25333 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25334 // countS bits are ignored when loading from memory on insertps, which
25335 // means we don't need to explicitly set them to 0.
25336 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25337 LoadScalarToVector, N->getOperand(2));
25340 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25341 // as "sbb reg,reg", since it can be extended without zext and produces
25342 // an all-ones bit which is more useful than 0/1 in some cases.
25343 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25346 return DAG.getNode(ISD::AND, DL, VT,
25347 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25348 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25349 DAG.getConstant(1, VT));
25350 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25351 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25352 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25353 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25356 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25357 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25358 TargetLowering::DAGCombinerInfo &DCI,
25359 const X86Subtarget *Subtarget) {
25361 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25362 SDValue EFLAGS = N->getOperand(1);
25364 if (CC == X86::COND_A) {
25365 // Try to convert COND_A into COND_B in an attempt to facilitate
25366 // materializing "setb reg".
25368 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25369 // cannot take an immediate as its first operand.
25371 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25372 EFLAGS.getValueType().isInteger() &&
25373 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25374 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25375 EFLAGS.getNode()->getVTList(),
25376 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25377 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25378 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25382 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25383 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25385 if (CC == X86::COND_B)
25386 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25390 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25391 if (Flags.getNode()) {
25392 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25393 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25399 // Optimize branch condition evaluation.
25401 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25402 TargetLowering::DAGCombinerInfo &DCI,
25403 const X86Subtarget *Subtarget) {
25405 SDValue Chain = N->getOperand(0);
25406 SDValue Dest = N->getOperand(1);
25407 SDValue EFLAGS = N->getOperand(3);
25408 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25412 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25413 if (Flags.getNode()) {
25414 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25415 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25422 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25423 SelectionDAG &DAG) {
25424 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25425 // optimize away operation when it's from a constant.
25427 // The general transformation is:
25428 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25429 // AND(VECTOR_CMP(x,y), constant2)
25430 // constant2 = UNARYOP(constant)
25432 // Early exit if this isn't a vector operation, the operand of the
25433 // unary operation isn't a bitwise AND, or if the sizes of the operations
25434 // aren't the same.
25435 EVT VT = N->getValueType(0);
25436 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25437 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25438 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25441 // Now check that the other operand of the AND is a constant. We could
25442 // make the transformation for non-constant splats as well, but it's unclear
25443 // that would be a benefit as it would not eliminate any operations, just
25444 // perform one more step in scalar code before moving to the vector unit.
25445 if (BuildVectorSDNode *BV =
25446 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25447 // Bail out if the vector isn't a constant.
25448 if (!BV->isConstant())
25451 // Everything checks out. Build up the new and improved node.
25453 EVT IntVT = BV->getValueType(0);
25454 // Create a new constant of the appropriate type for the transformed
25456 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25457 // The AND node needs bitcasts to/from an integer vector type around it.
25458 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25459 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25460 N->getOperand(0)->getOperand(0), MaskConst);
25461 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25468 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25469 const X86TargetLowering *XTLI) {
25470 // First try to optimize away the conversion entirely when it's
25471 // conditionally from a constant. Vectors only.
25472 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25473 if (Res != SDValue())
25476 // Now move on to more general possibilities.
25477 SDValue Op0 = N->getOperand(0);
25478 EVT InVT = Op0->getValueType(0);
25480 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25481 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25483 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25484 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25485 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25488 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25489 // a 32-bit target where SSE doesn't support i64->FP operations.
25490 if (Op0.getOpcode() == ISD::LOAD) {
25491 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25492 EVT VT = Ld->getValueType(0);
25493 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25494 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25495 !XTLI->getSubtarget()->is64Bit() &&
25497 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25498 Ld->getChain(), Op0, DAG);
25499 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25506 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25507 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25508 X86TargetLowering::DAGCombinerInfo &DCI) {
25509 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25510 // the result is either zero or one (depending on the input carry bit).
25511 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25512 if (X86::isZeroNode(N->getOperand(0)) &&
25513 X86::isZeroNode(N->getOperand(1)) &&
25514 // We don't have a good way to replace an EFLAGS use, so only do this when
25516 SDValue(N, 1).use_empty()) {
25518 EVT VT = N->getValueType(0);
25519 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25520 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25521 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25522 DAG.getConstant(X86::COND_B,MVT::i8),
25524 DAG.getConstant(1, VT));
25525 return DCI.CombineTo(N, Res1, CarryOut);
25531 // fold (add Y, (sete X, 0)) -> adc 0, Y
25532 // (add Y, (setne X, 0)) -> sbb -1, Y
25533 // (sub (sete X, 0), Y) -> sbb 0, Y
25534 // (sub (setne X, 0), Y) -> adc -1, Y
25535 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25538 // Look through ZExts.
25539 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25540 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25543 SDValue SetCC = Ext.getOperand(0);
25544 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25547 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25548 if (CC != X86::COND_E && CC != X86::COND_NE)
25551 SDValue Cmp = SetCC.getOperand(1);
25552 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25553 !X86::isZeroNode(Cmp.getOperand(1)) ||
25554 !Cmp.getOperand(0).getValueType().isInteger())
25557 SDValue CmpOp0 = Cmp.getOperand(0);
25558 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25559 DAG.getConstant(1, CmpOp0.getValueType()));
25561 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25562 if (CC == X86::COND_NE)
25563 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25564 DL, OtherVal.getValueType(), OtherVal,
25565 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25566 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25567 DL, OtherVal.getValueType(), OtherVal,
25568 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25571 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25572 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25573 const X86Subtarget *Subtarget) {
25574 EVT VT = N->getValueType(0);
25575 SDValue Op0 = N->getOperand(0);
25576 SDValue Op1 = N->getOperand(1);
25578 // Try to synthesize horizontal adds from adds of shuffles.
25579 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25580 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25581 isHorizontalBinOp(Op0, Op1, true))
25582 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25584 return OptimizeConditionalInDecrement(N, DAG);
25587 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25588 const X86Subtarget *Subtarget) {
25589 SDValue Op0 = N->getOperand(0);
25590 SDValue Op1 = N->getOperand(1);
25592 // X86 can't encode an immediate LHS of a sub. See if we can push the
25593 // negation into a preceding instruction.
25594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25595 // If the RHS of the sub is a XOR with one use and a constant, invert the
25596 // immediate. Then add one to the LHS of the sub so we can turn
25597 // X-Y -> X+~Y+1, saving one register.
25598 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25599 isa<ConstantSDNode>(Op1.getOperand(1))) {
25600 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25601 EVT VT = Op0.getValueType();
25602 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25604 DAG.getConstant(~XorC, VT));
25605 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25606 DAG.getConstant(C->getAPIntValue()+1, VT));
25610 // Try to synthesize horizontal adds from adds of shuffles.
25611 EVT VT = N->getValueType(0);
25612 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25613 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25614 isHorizontalBinOp(Op0, Op1, true))
25615 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25617 return OptimizeConditionalInDecrement(N, DAG);
25620 /// performVZEXTCombine - Performs build vector combines
25621 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25622 TargetLowering::DAGCombinerInfo &DCI,
25623 const X86Subtarget *Subtarget) {
25625 MVT VT = N->getSimpleValueType(0);
25626 SDValue Op = N->getOperand(0);
25627 MVT OpVT = Op.getSimpleValueType();
25628 MVT OpEltVT = OpVT.getVectorElementType();
25629 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25631 // (vzext (bitcast (vzext (x)) -> (vzext x)
25633 while (V.getOpcode() == ISD::BITCAST)
25634 V = V.getOperand(0);
25636 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25637 MVT InnerVT = V.getSimpleValueType();
25638 MVT InnerEltVT = InnerVT.getVectorElementType();
25640 // If the element sizes match exactly, we can just do one larger vzext. This
25641 // is always an exact type match as vzext operates on integer types.
25642 if (OpEltVT == InnerEltVT) {
25643 assert(OpVT == InnerVT && "Types must match for vzext!");
25644 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25647 // The only other way we can combine them is if only a single element of the
25648 // inner vzext is used in the input to the outer vzext.
25649 if (InnerEltVT.getSizeInBits() < InputBits)
25652 // In this case, the inner vzext is completely dead because we're going to
25653 // only look at bits inside of the low element. Just do the outer vzext on
25654 // a bitcast of the input to the inner.
25655 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25656 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25659 // Check if we can bypass extracting and re-inserting an element of an input
25660 // vector. Essentialy:
25661 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25662 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25663 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25664 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25665 SDValue ExtractedV = V.getOperand(0);
25666 SDValue OrigV = ExtractedV.getOperand(0);
25667 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25668 if (ExtractIdx->getZExtValue() == 0) {
25669 MVT OrigVT = OrigV.getSimpleValueType();
25670 // Extract a subvector if necessary...
25671 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25672 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25673 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25674 OrigVT.getVectorNumElements() / Ratio);
25675 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25676 DAG.getIntPtrConstant(0));
25678 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25679 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25686 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25687 DAGCombinerInfo &DCI) const {
25688 SelectionDAG &DAG = DCI.DAG;
25689 switch (N->getOpcode()) {
25691 case ISD::EXTRACT_VECTOR_ELT:
25692 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25695 case X86ISD::SHRUNKBLEND:
25696 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25697 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25698 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25699 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25700 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25701 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25704 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25705 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25706 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25707 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25708 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25709 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25710 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25711 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25712 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25714 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25716 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25717 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25718 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25719 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25720 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25721 case ISD::ANY_EXTEND:
25722 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25723 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25724 case ISD::SIGN_EXTEND_INREG:
25725 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25726 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25727 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25728 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25729 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25730 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25731 case X86ISD::SHUFP: // Handle all target specific shuffles
25732 case X86ISD::PALIGNR:
25733 case X86ISD::UNPCKH:
25734 case X86ISD::UNPCKL:
25735 case X86ISD::MOVHLPS:
25736 case X86ISD::MOVLHPS:
25737 case X86ISD::PSHUFB:
25738 case X86ISD::PSHUFD:
25739 case X86ISD::PSHUFHW:
25740 case X86ISD::PSHUFLW:
25741 case X86ISD::MOVSS:
25742 case X86ISD::MOVSD:
25743 case X86ISD::VPERMILPI:
25744 case X86ISD::VPERM2X128:
25745 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25746 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25747 case ISD::INTRINSIC_WO_CHAIN:
25748 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25749 case X86ISD::INSERTPS:
25750 return PerformINSERTPSCombine(N, DAG, Subtarget);
25751 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25757 /// isTypeDesirableForOp - Return true if the target has native support for
25758 /// the specified value type and it is 'desirable' to use the type for the
25759 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25760 /// instruction encodings are longer and some i16 instructions are slow.
25761 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25762 if (!isTypeLegal(VT))
25764 if (VT != MVT::i16)
25771 case ISD::SIGN_EXTEND:
25772 case ISD::ZERO_EXTEND:
25773 case ISD::ANY_EXTEND:
25786 /// IsDesirableToPromoteOp - This method query the target whether it is
25787 /// beneficial for dag combiner to promote the specified node. If true, it
25788 /// should return the desired promotion type by reference.
25789 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25790 EVT VT = Op.getValueType();
25791 if (VT != MVT::i16)
25794 bool Promote = false;
25795 bool Commute = false;
25796 switch (Op.getOpcode()) {
25799 LoadSDNode *LD = cast<LoadSDNode>(Op);
25800 // If the non-extending load has a single use and it's not live out, then it
25801 // might be folded.
25802 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25803 Op.hasOneUse()*/) {
25804 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25805 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25806 // The only case where we'd want to promote LOAD (rather then it being
25807 // promoted as an operand is when it's only use is liveout.
25808 if (UI->getOpcode() != ISD::CopyToReg)
25815 case ISD::SIGN_EXTEND:
25816 case ISD::ZERO_EXTEND:
25817 case ISD::ANY_EXTEND:
25822 SDValue N0 = Op.getOperand(0);
25823 // Look out for (store (shl (load), x)).
25824 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25837 SDValue N0 = Op.getOperand(0);
25838 SDValue N1 = Op.getOperand(1);
25839 if (!Commute && MayFoldLoad(N1))
25841 // Avoid disabling potential load folding opportunities.
25842 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25844 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25854 //===----------------------------------------------------------------------===//
25855 // X86 Inline Assembly Support
25856 //===----------------------------------------------------------------------===//
25859 // Helper to match a string separated by whitespace.
25860 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25861 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25863 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25864 StringRef piece(*args[i]);
25865 if (!s.startswith(piece)) // Check if the piece matches.
25868 s = s.substr(piece.size());
25869 StringRef::size_type pos = s.find_first_not_of(" \t");
25870 if (pos == 0) // We matched a prefix.
25878 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25881 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25883 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25884 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25885 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25886 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25888 if (AsmPieces.size() == 3)
25890 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25897 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25898 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25900 std::string AsmStr = IA->getAsmString();
25902 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25903 if (!Ty || Ty->getBitWidth() % 16 != 0)
25906 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25907 SmallVector<StringRef, 4> AsmPieces;
25908 SplitString(AsmStr, AsmPieces, ";\n");
25910 switch (AsmPieces.size()) {
25911 default: return false;
25913 // FIXME: this should verify that we are targeting a 486 or better. If not,
25914 // we will turn this bswap into something that will be lowered to logical
25915 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25916 // lower so don't worry about this.
25918 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25919 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25920 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25921 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25922 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25923 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25924 // No need to check constraints, nothing other than the equivalent of
25925 // "=r,0" would be valid here.
25926 return IntrinsicLowering::LowerToByteSwap(CI);
25929 // rorw $$8, ${0:w} --> llvm.bswap.i16
25930 if (CI->getType()->isIntegerTy(16) &&
25931 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25932 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25933 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25935 const std::string &ConstraintsStr = IA->getConstraintString();
25936 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25937 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25938 if (clobbersFlagRegisters(AsmPieces))
25939 return IntrinsicLowering::LowerToByteSwap(CI);
25943 if (CI->getType()->isIntegerTy(32) &&
25944 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25945 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25946 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25947 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25949 const std::string &ConstraintsStr = IA->getConstraintString();
25950 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25951 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25952 if (clobbersFlagRegisters(AsmPieces))
25953 return IntrinsicLowering::LowerToByteSwap(CI);
25956 if (CI->getType()->isIntegerTy(64)) {
25957 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25958 if (Constraints.size() >= 2 &&
25959 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25960 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25961 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25962 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25963 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25964 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25965 return IntrinsicLowering::LowerToByteSwap(CI);
25973 /// getConstraintType - Given a constraint letter, return the type of
25974 /// constraint it is for this target.
25975 X86TargetLowering::ConstraintType
25976 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25977 if (Constraint.size() == 1) {
25978 switch (Constraint[0]) {
25989 return C_RegisterClass;
26013 return TargetLowering::getConstraintType(Constraint);
26016 /// Examine constraint type and operand type and determine a weight value.
26017 /// This object must already have been set up with the operand type
26018 /// and the current alternative constraint selected.
26019 TargetLowering::ConstraintWeight
26020 X86TargetLowering::getSingleConstraintMatchWeight(
26021 AsmOperandInfo &info, const char *constraint) const {
26022 ConstraintWeight weight = CW_Invalid;
26023 Value *CallOperandVal = info.CallOperandVal;
26024 // If we don't have a value, we can't do a match,
26025 // but allow it at the lowest weight.
26026 if (!CallOperandVal)
26028 Type *type = CallOperandVal->getType();
26029 // Look at the constraint type.
26030 switch (*constraint) {
26032 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26043 if (CallOperandVal->getType()->isIntegerTy())
26044 weight = CW_SpecificReg;
26049 if (type->isFloatingPointTy())
26050 weight = CW_SpecificReg;
26053 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26054 weight = CW_SpecificReg;
26058 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26059 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26060 weight = CW_Register;
26063 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26064 if (C->getZExtValue() <= 31)
26065 weight = CW_Constant;
26069 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26070 if (C->getZExtValue() <= 63)
26071 weight = CW_Constant;
26075 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26076 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26077 weight = CW_Constant;
26081 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26082 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26083 weight = CW_Constant;
26087 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26088 if (C->getZExtValue() <= 3)
26089 weight = CW_Constant;
26093 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26094 if (C->getZExtValue() <= 0xff)
26095 weight = CW_Constant;
26100 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26101 weight = CW_Constant;
26105 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26106 if ((C->getSExtValue() >= -0x80000000LL) &&
26107 (C->getSExtValue() <= 0x7fffffffLL))
26108 weight = CW_Constant;
26112 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26113 if (C->getZExtValue() <= 0xffffffff)
26114 weight = CW_Constant;
26121 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26122 /// with another that has more specific requirements based on the type of the
26123 /// corresponding operand.
26124 const char *X86TargetLowering::
26125 LowerXConstraint(EVT ConstraintVT) const {
26126 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26127 // 'f' like normal targets.
26128 if (ConstraintVT.isFloatingPoint()) {
26129 if (Subtarget->hasSSE2())
26131 if (Subtarget->hasSSE1())
26135 return TargetLowering::LowerXConstraint(ConstraintVT);
26138 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26139 /// vector. If it is invalid, don't add anything to Ops.
26140 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26141 std::string &Constraint,
26142 std::vector<SDValue>&Ops,
26143 SelectionDAG &DAG) const {
26146 // Only support length 1 constraints for now.
26147 if (Constraint.length() > 1) return;
26149 char ConstraintLetter = Constraint[0];
26150 switch (ConstraintLetter) {
26153 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26154 if (C->getZExtValue() <= 31) {
26155 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26161 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26162 if (C->getZExtValue() <= 63) {
26163 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26169 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26170 if (isInt<8>(C->getSExtValue())) {
26171 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26177 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26178 if (C->getZExtValue() <= 255) {
26179 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26185 // 32-bit signed value
26186 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26187 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26188 C->getSExtValue())) {
26189 // Widen to 64 bits here to get it sign extended.
26190 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26193 // FIXME gcc accepts some relocatable values here too, but only in certain
26194 // memory models; it's complicated.
26199 // 32-bit unsigned value
26200 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26201 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26202 C->getZExtValue())) {
26203 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26207 // FIXME gcc accepts some relocatable values here too, but only in certain
26208 // memory models; it's complicated.
26212 // Literal immediates are always ok.
26213 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26214 // Widen to 64 bits here to get it sign extended.
26215 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26219 // In any sort of PIC mode addresses need to be computed at runtime by
26220 // adding in a register or some sort of table lookup. These can't
26221 // be used as immediates.
26222 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26225 // If we are in non-pic codegen mode, we allow the address of a global (with
26226 // an optional displacement) to be used with 'i'.
26227 GlobalAddressSDNode *GA = nullptr;
26228 int64_t Offset = 0;
26230 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26232 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26233 Offset += GA->getOffset();
26235 } else if (Op.getOpcode() == ISD::ADD) {
26236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26237 Offset += C->getZExtValue();
26238 Op = Op.getOperand(0);
26241 } else if (Op.getOpcode() == ISD::SUB) {
26242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26243 Offset += -C->getZExtValue();
26244 Op = Op.getOperand(0);
26249 // Otherwise, this isn't something we can handle, reject it.
26253 const GlobalValue *GV = GA->getGlobal();
26254 // If we require an extra load to get this address, as in PIC mode, we
26255 // can't accept it.
26256 if (isGlobalStubReference(
26257 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26260 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26261 GA->getValueType(0), Offset);
26266 if (Result.getNode()) {
26267 Ops.push_back(Result);
26270 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26273 std::pair<unsigned, const TargetRegisterClass*>
26274 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26276 // First, see if this is a constraint that directly corresponds to an LLVM
26278 if (Constraint.size() == 1) {
26279 // GCC Constraint Letters
26280 switch (Constraint[0]) {
26282 // TODO: Slight differences here in allocation order and leaving
26283 // RIP in the class. Do they matter any more here than they do
26284 // in the normal allocation?
26285 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26286 if (Subtarget->is64Bit()) {
26287 if (VT == MVT::i32 || VT == MVT::f32)
26288 return std::make_pair(0U, &X86::GR32RegClass);
26289 if (VT == MVT::i16)
26290 return std::make_pair(0U, &X86::GR16RegClass);
26291 if (VT == MVT::i8 || VT == MVT::i1)
26292 return std::make_pair(0U, &X86::GR8RegClass);
26293 if (VT == MVT::i64 || VT == MVT::f64)
26294 return std::make_pair(0U, &X86::GR64RegClass);
26297 // 32-bit fallthrough
26298 case 'Q': // Q_REGS
26299 if (VT == MVT::i32 || VT == MVT::f32)
26300 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26301 if (VT == MVT::i16)
26302 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26303 if (VT == MVT::i8 || VT == MVT::i1)
26304 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26305 if (VT == MVT::i64)
26306 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26308 case 'r': // GENERAL_REGS
26309 case 'l': // INDEX_REGS
26310 if (VT == MVT::i8 || VT == MVT::i1)
26311 return std::make_pair(0U, &X86::GR8RegClass);
26312 if (VT == MVT::i16)
26313 return std::make_pair(0U, &X86::GR16RegClass);
26314 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26315 return std::make_pair(0U, &X86::GR32RegClass);
26316 return std::make_pair(0U, &X86::GR64RegClass);
26317 case 'R': // LEGACY_REGS
26318 if (VT == MVT::i8 || VT == MVT::i1)
26319 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26320 if (VT == MVT::i16)
26321 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26322 if (VT == MVT::i32 || !Subtarget->is64Bit())
26323 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26324 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26325 case 'f': // FP Stack registers.
26326 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26327 // value to the correct fpstack register class.
26328 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26329 return std::make_pair(0U, &X86::RFP32RegClass);
26330 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26331 return std::make_pair(0U, &X86::RFP64RegClass);
26332 return std::make_pair(0U, &X86::RFP80RegClass);
26333 case 'y': // MMX_REGS if MMX allowed.
26334 if (!Subtarget->hasMMX()) break;
26335 return std::make_pair(0U, &X86::VR64RegClass);
26336 case 'Y': // SSE_REGS if SSE2 allowed
26337 if (!Subtarget->hasSSE2()) break;
26339 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26340 if (!Subtarget->hasSSE1()) break;
26342 switch (VT.SimpleTy) {
26344 // Scalar SSE types.
26347 return std::make_pair(0U, &X86::FR32RegClass);
26350 return std::make_pair(0U, &X86::FR64RegClass);
26358 return std::make_pair(0U, &X86::VR128RegClass);
26366 return std::make_pair(0U, &X86::VR256RegClass);
26371 return std::make_pair(0U, &X86::VR512RegClass);
26377 // Use the default implementation in TargetLowering to convert the register
26378 // constraint into a member of a register class.
26379 std::pair<unsigned, const TargetRegisterClass*> Res;
26380 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26382 // Not found as a standard register?
26384 // Map st(0) -> st(7) -> ST0
26385 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26386 tolower(Constraint[1]) == 's' &&
26387 tolower(Constraint[2]) == 't' &&
26388 Constraint[3] == '(' &&
26389 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26390 Constraint[5] == ')' &&
26391 Constraint[6] == '}') {
26393 Res.first = X86::FP0+Constraint[4]-'0';
26394 Res.second = &X86::RFP80RegClass;
26398 // GCC allows "st(0)" to be called just plain "st".
26399 if (StringRef("{st}").equals_lower(Constraint)) {
26400 Res.first = X86::FP0;
26401 Res.second = &X86::RFP80RegClass;
26406 if (StringRef("{flags}").equals_lower(Constraint)) {
26407 Res.first = X86::EFLAGS;
26408 Res.second = &X86::CCRRegClass;
26412 // 'A' means EAX + EDX.
26413 if (Constraint == "A") {
26414 Res.first = X86::EAX;
26415 Res.second = &X86::GR32_ADRegClass;
26421 // Otherwise, check to see if this is a register class of the wrong value
26422 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26423 // turn into {ax},{dx}.
26424 if (Res.second->hasType(VT))
26425 return Res; // Correct type already, nothing to do.
26427 // All of the single-register GCC register classes map their values onto
26428 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26429 // really want an 8-bit or 32-bit register, map to the appropriate register
26430 // class and return the appropriate register.
26431 if (Res.second == &X86::GR16RegClass) {
26432 if (VT == MVT::i8 || VT == MVT::i1) {
26433 unsigned DestReg = 0;
26434 switch (Res.first) {
26436 case X86::AX: DestReg = X86::AL; break;
26437 case X86::DX: DestReg = X86::DL; break;
26438 case X86::CX: DestReg = X86::CL; break;
26439 case X86::BX: DestReg = X86::BL; break;
26442 Res.first = DestReg;
26443 Res.second = &X86::GR8RegClass;
26445 } else if (VT == MVT::i32 || VT == MVT::f32) {
26446 unsigned DestReg = 0;
26447 switch (Res.first) {
26449 case X86::AX: DestReg = X86::EAX; break;
26450 case X86::DX: DestReg = X86::EDX; break;
26451 case X86::CX: DestReg = X86::ECX; break;
26452 case X86::BX: DestReg = X86::EBX; break;
26453 case X86::SI: DestReg = X86::ESI; break;
26454 case X86::DI: DestReg = X86::EDI; break;
26455 case X86::BP: DestReg = X86::EBP; break;
26456 case X86::SP: DestReg = X86::ESP; break;
26459 Res.first = DestReg;
26460 Res.second = &X86::GR32RegClass;
26462 } else if (VT == MVT::i64 || VT == MVT::f64) {
26463 unsigned DestReg = 0;
26464 switch (Res.first) {
26466 case X86::AX: DestReg = X86::RAX; break;
26467 case X86::DX: DestReg = X86::RDX; break;
26468 case X86::CX: DestReg = X86::RCX; break;
26469 case X86::BX: DestReg = X86::RBX; break;
26470 case X86::SI: DestReg = X86::RSI; break;
26471 case X86::DI: DestReg = X86::RDI; break;
26472 case X86::BP: DestReg = X86::RBP; break;
26473 case X86::SP: DestReg = X86::RSP; break;
26476 Res.first = DestReg;
26477 Res.second = &X86::GR64RegClass;
26480 } else if (Res.second == &X86::FR32RegClass ||
26481 Res.second == &X86::FR64RegClass ||
26482 Res.second == &X86::VR128RegClass ||
26483 Res.second == &X86::VR256RegClass ||
26484 Res.second == &X86::FR32XRegClass ||
26485 Res.second == &X86::FR64XRegClass ||
26486 Res.second == &X86::VR128XRegClass ||
26487 Res.second == &X86::VR256XRegClass ||
26488 Res.second == &X86::VR512RegClass) {
26489 // Handle references to XMM physical registers that got mapped into the
26490 // wrong class. This can happen with constraints like {xmm0} where the
26491 // target independent register mapper will just pick the first match it can
26492 // find, ignoring the required type.
26494 if (VT == MVT::f32 || VT == MVT::i32)
26495 Res.second = &X86::FR32RegClass;
26496 else if (VT == MVT::f64 || VT == MVT::i64)
26497 Res.second = &X86::FR64RegClass;
26498 else if (X86::VR128RegClass.hasType(VT))
26499 Res.second = &X86::VR128RegClass;
26500 else if (X86::VR256RegClass.hasType(VT))
26501 Res.second = &X86::VR256RegClass;
26502 else if (X86::VR512RegClass.hasType(VT))
26503 Res.second = &X86::VR512RegClass;
26509 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26511 // Scaling factors are not free at all.
26512 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26513 // will take 2 allocations in the out of order engine instead of 1
26514 // for plain addressing mode, i.e. inst (reg1).
26516 // vaddps (%rsi,%drx), %ymm0, %ymm1
26517 // Requires two allocations (one for the load, one for the computation)
26519 // vaddps (%rsi), %ymm0, %ymm1
26520 // Requires just 1 allocation, i.e., freeing allocations for other operations
26521 // and having less micro operations to execute.
26523 // For some X86 architectures, this is even worse because for instance for
26524 // stores, the complex addressing mode forces the instruction to use the
26525 // "load" ports instead of the dedicated "store" port.
26526 // E.g., on Haswell:
26527 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26528 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26529 if (isLegalAddressingMode(AM, Ty))
26530 // Scale represents reg2 * scale, thus account for 1
26531 // as soon as we use a second register.
26532 return AM.Scale != 0;
26536 bool X86TargetLowering::isTargetFTOL() const {
26537 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();