1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/ADT/SmallSet.h"
41 #include "llvm/ADT/StringExtras.h"
44 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
45 : TargetLowering(TM) {
46 Subtarget = &TM.getSubtarget<X86Subtarget>();
47 X86ScalarSSEf64 = Subtarget->hasSSE2();
48 X86ScalarSSEf32 = Subtarget->hasSSE1();
49 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
53 RegInfo = TM.getRegisterInfo();
55 // Set up the TargetLowering object.
57 // X86 is weird, it always uses i8 for shift amounts and setcc results.
58 setShiftAmountType(MVT::i8);
59 setSetCCResultContents(ZeroOrOneSetCCResult);
60 setSchedulingPreference(SchedulingForRegPressure);
61 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
62 setStackPointerRegisterToSaveRestore(X86StackPtr);
64 if (Subtarget->isTargetDarwin()) {
65 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(false);
67 setUseUnderscoreLongJmp(false);
68 } else if (Subtarget->isTargetMingw()) {
69 // MS runtime is weird: it exports _setjmp, but longjmp!
70 setUseUnderscoreSetJmp(true);
71 setUseUnderscoreLongJmp(false);
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
77 // Set up the register classes.
78 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
79 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
80 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
81 if (Subtarget->is64Bit())
82 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
84 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
86 // We don't accept any truncstore of integer registers.
87 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
88 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
89 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
90 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
91 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
92 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
96 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
97 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
98 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
100 if (Subtarget->is64Bit()) {
101 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
102 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
105 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
106 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
108 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
111 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
113 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
114 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
115 // SSE has no i16 to fp conversion, only i32
116 if (X86ScalarSSEf32) {
117 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
118 // f32 and f64 cases are Legal, f80 case is not
119 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
121 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
125 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
126 // are Legal, f80 is custom lowered.
127 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
128 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
130 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
132 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
133 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
135 if (X86ScalarSSEf32) {
136 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
137 // f32 and f64 cases are Legal, f80 case is not
138 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
140 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
144 // Handle FP_TO_UINT by promoting the destination to a larger signed
146 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
147 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
148 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
150 if (Subtarget->is64Bit()) {
151 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
152 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
154 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
155 // Expand FP_TO_UINT into a select.
156 // FIXME: We would like to use a Custom expander here eventually to do
157 // the optimal thing for SSE vs. the default expansion in the legalizer.
158 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
160 // With SSE3 we can use fisttpll to convert to a signed i64.
161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
164 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
165 if (!X86ScalarSSEf64) {
166 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
167 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
170 // Scalar integer divide and remainder are lowered to use operations that
171 // produce two results, to match the available instructions. This exposes
172 // the two-result form to trivial CSE, which is able to combine x/y and x%y
173 // into a single instruction.
175 // Scalar integer multiply-high is also lowered to use two-result
176 // operations, to match the available instructions. However, plain multiply
177 // (low) operations are left as Legal, as there are single-result
178 // instructions for this in x86. Using the two-result multiply instructions
179 // when both high and low results are needed must be arranged by dagcombine.
180 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
181 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
182 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
183 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
184 setOperationAction(ISD::SREM , MVT::i8 , Expand);
185 setOperationAction(ISD::UREM , MVT::i8 , Expand);
186 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
187 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
188 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
189 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
190 setOperationAction(ISD::SREM , MVT::i16 , Expand);
191 setOperationAction(ISD::UREM , MVT::i16 , Expand);
192 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
193 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
194 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
195 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
196 setOperationAction(ISD::SREM , MVT::i32 , Expand);
197 setOperationAction(ISD::UREM , MVT::i32 , Expand);
198 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
199 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
200 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
201 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
202 setOperationAction(ISD::SREM , MVT::i64 , Expand);
203 setOperationAction(ISD::UREM , MVT::i64 , Expand);
205 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
206 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
207 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
208 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
209 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
210 if (Subtarget->is64Bit())
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
215 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
216 setOperationAction(ISD::FREM , MVT::f32 , Expand);
217 setOperationAction(ISD::FREM , MVT::f64 , Expand);
218 setOperationAction(ISD::FREM , MVT::f80 , Expand);
219 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
221 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
222 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
223 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
224 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
225 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
226 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
227 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
228 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
229 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
230 if (Subtarget->is64Bit()) {
231 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
232 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
233 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
236 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
237 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
239 // These should be promoted to a larger select which is supported.
240 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
241 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
242 // X86 wants to expand cmov itself.
243 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
244 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
245 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
246 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
247 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
248 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
249 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
250 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
251 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
252 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
253 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
256 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
258 // X86 ret instruction may pop stack.
259 setOperationAction(ISD::RET , MVT::Other, Custom);
260 if (!Subtarget->is64Bit())
261 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
264 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
265 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
266 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
267 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
268 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
269 if (Subtarget->is64Bit()) {
270 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
271 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
272 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
273 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
275 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
276 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
277 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
278 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
279 if (Subtarget->is64Bit()) {
280 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
281 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
282 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
284 // X86 wants to expand memset / memcpy itself.
285 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
286 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
288 if (Subtarget->hasSSE1())
289 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
291 if (!Subtarget->hasSSE2())
292 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
294 setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom);
295 setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom);
296 setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom);
297 setOperationAction(ISD::ATOMIC_LCS , MVT::i64, Custom);
299 // Use the default ISD::LOCATION, ISD::DECLARE expansion.
300 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
301 // FIXME - use subtarget debug flags
302 if (!Subtarget->isTargetDarwin() &&
303 !Subtarget->isTargetELF() &&
304 !Subtarget->isTargetCygMing())
305 setOperationAction(ISD::LABEL, MVT::Other, Expand);
307 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
308 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
309 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
310 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
311 if (Subtarget->is64Bit()) {
313 setExceptionPointerRegister(X86::RAX);
314 setExceptionSelectorRegister(X86::RDX);
316 setExceptionPointerRegister(X86::EAX);
317 setExceptionSelectorRegister(X86::EDX);
319 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
321 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
323 setOperationAction(ISD::TRAP, MVT::Other, Legal);
325 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
326 setOperationAction(ISD::VASTART , MVT::Other, Custom);
327 setOperationAction(ISD::VAARG , MVT::Other, Expand);
328 setOperationAction(ISD::VAEND , MVT::Other, Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
332 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
334 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
335 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
336 if (Subtarget->is64Bit())
337 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
338 if (Subtarget->isTargetCygMing())
339 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
341 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
343 if (X86ScalarSSEf64) {
344 // f32 and f64 use SSE.
345 // Set up the FP register classes.
346 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
347 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
349 // Use ANDPD to simulate FABS.
350 setOperationAction(ISD::FABS , MVT::f64, Custom);
351 setOperationAction(ISD::FABS , MVT::f32, Custom);
353 // Use XORP to simulate FNEG.
354 setOperationAction(ISD::FNEG , MVT::f64, Custom);
355 setOperationAction(ISD::FNEG , MVT::f32, Custom);
357 // Use ANDPD and ORPD to simulate FCOPYSIGN.
358 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
359 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
361 // We don't support sin/cos/fmod
362 setOperationAction(ISD::FSIN , MVT::f64, Expand);
363 setOperationAction(ISD::FCOS , MVT::f64, Expand);
364 setOperationAction(ISD::FSIN , MVT::f32, Expand);
365 setOperationAction(ISD::FCOS , MVT::f32, Expand);
367 // Expand FP immediates into loads from the stack, except for the special
369 addLegalFPImmediate(APFloat(+0.0)); // xorpd
370 addLegalFPImmediate(APFloat(+0.0f)); // xorps
372 // Floating truncations from f80 and extensions to f80 go through memory.
373 // If optimizing, we lie about this though and handle it in
374 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
376 setConvertAction(MVT::f32, MVT::f80, Expand);
377 setConvertAction(MVT::f64, MVT::f80, Expand);
378 setConvertAction(MVT::f80, MVT::f32, Expand);
379 setConvertAction(MVT::f80, MVT::f64, Expand);
381 } else if (X86ScalarSSEf32) {
382 // Use SSE for f32, x87 for f64.
383 // Set up the FP register classes.
384 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
385 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
387 // Use ANDPS to simulate FABS.
388 setOperationAction(ISD::FABS , MVT::f32, Custom);
390 // Use XORP to simulate FNEG.
391 setOperationAction(ISD::FNEG , MVT::f32, Custom);
393 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
395 // Use ANDPS and ORPS to simulate FCOPYSIGN.
396 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
397 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
399 // We don't support sin/cos/fmod
400 setOperationAction(ISD::FSIN , MVT::f32, Expand);
401 setOperationAction(ISD::FCOS , MVT::f32, Expand);
403 // Special cases we handle for FP constants.
404 addLegalFPImmediate(APFloat(+0.0f)); // xorps
405 addLegalFPImmediate(APFloat(+0.0)); // FLD0
406 addLegalFPImmediate(APFloat(+1.0)); // FLD1
407 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
408 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
410 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
411 // this though and handle it in InstructionSelectPreprocess so that
412 // dagcombine2 can hack on these.
414 setConvertAction(MVT::f32, MVT::f64, Expand);
415 setConvertAction(MVT::f32, MVT::f80, Expand);
416 setConvertAction(MVT::f80, MVT::f32, Expand);
417 setConvertAction(MVT::f64, MVT::f32, Expand);
418 // And x87->x87 truncations also.
419 setConvertAction(MVT::f80, MVT::f64, Expand);
423 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
424 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
427 // f32 and f64 in x87.
428 // Set up the FP register classes.
429 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
430 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
432 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
433 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
434 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
435 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
437 // Floating truncations go through memory. If optimizing, we lie about
438 // this though and handle it in InstructionSelectPreprocess so that
439 // dagcombine2 can hack on these.
441 setConvertAction(MVT::f80, MVT::f32, Expand);
442 setConvertAction(MVT::f64, MVT::f32, Expand);
443 setConvertAction(MVT::f80, MVT::f64, Expand);
447 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
448 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
450 addLegalFPImmediate(APFloat(+0.0)); // FLD0
451 addLegalFPImmediate(APFloat(+1.0)); // FLD1
452 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
453 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
454 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
455 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
456 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
457 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
460 // Long double always uses X87.
461 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
462 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
463 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
465 APFloat TmpFlt(+0.0);
466 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
467 addLegalFPImmediate(TmpFlt); // FLD0
469 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
470 APFloat TmpFlt2(+1.0);
471 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
472 addLegalFPImmediate(TmpFlt2); // FLD1
473 TmpFlt2.changeSign();
474 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
478 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
479 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
482 // Always use a library call for pow.
483 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
484 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
485 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
487 // First set operation action for all vector types to expand. Then we
488 // will selectively turn on ones that can be effectively codegen'd.
489 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
490 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
491 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
492 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
493 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
494 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
495 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
496 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
497 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
498 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
499 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
500 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
501 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
502 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
503 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
504 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
505 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
506 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
507 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
508 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
509 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
510 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
511 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
512 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
513 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
514 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
515 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
516 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
517 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
518 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
519 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
520 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
521 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
522 setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand);
523 setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand);
524 setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand);
525 setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
526 setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
527 setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
530 if (Subtarget->hasMMX()) {
531 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
532 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
533 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
534 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
536 // FIXME: add MMX packed arithmetics
538 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
539 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
540 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
541 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
543 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
544 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
545 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
546 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
548 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
549 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
551 setOperationAction(ISD::AND, MVT::v8i8, Promote);
552 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
553 setOperationAction(ISD::AND, MVT::v4i16, Promote);
554 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
555 setOperationAction(ISD::AND, MVT::v2i32, Promote);
556 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
557 setOperationAction(ISD::AND, MVT::v1i64, Legal);
559 setOperationAction(ISD::OR, MVT::v8i8, Promote);
560 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
561 setOperationAction(ISD::OR, MVT::v4i16, Promote);
562 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
563 setOperationAction(ISD::OR, MVT::v2i32, Promote);
564 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
565 setOperationAction(ISD::OR, MVT::v1i64, Legal);
567 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
568 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
569 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
570 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
571 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
572 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
573 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
575 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
576 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
577 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
578 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
579 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
580 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
581 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
583 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
584 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
585 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
586 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
588 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
589 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
590 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
591 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
593 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
594 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
595 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
598 if (Subtarget->hasSSE1()) {
599 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
601 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
602 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
603 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
604 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
605 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
606 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
607 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
608 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
609 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
610 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
611 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
614 if (Subtarget->hasSSE2()) {
615 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
616 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
617 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
618 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
619 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
621 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
622 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
623 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
624 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
625 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
626 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
627 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
628 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
629 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
630 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
631 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
632 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
633 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
634 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
635 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
637 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
638 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
639 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
640 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
641 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
643 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
644 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
645 // Do not attempt to custom lower non-power-of-2 vectors
646 if (!isPowerOf2_32(MVT::getVectorNumElements(VT)))
648 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
649 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
650 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
652 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
653 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
654 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
655 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
656 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
657 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
658 if (Subtarget->is64Bit()) {
659 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
660 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
663 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
664 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
665 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
666 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
667 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
668 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
669 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
670 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
671 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
672 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
673 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
674 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
677 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
679 // Custom lower v2i64 and v2f64 selects.
680 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
681 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
682 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
683 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
686 if (Subtarget->hasSSE41()) {
687 // FIXME: Do we need to handle scalar-to-vector here?
688 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
690 // i8 and i16 vectors are custom , because the source register and source
691 // source memory operand types are not the same width. f32 vectors are
692 // custom since the immediate controlling the insert encodes additional
694 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
696 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
697 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
699 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
700 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
701 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
702 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
704 if (Subtarget->is64Bit()) {
705 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
706 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
710 // We want to custom lower some of our intrinsics.
711 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
713 // We have target-specific dag combine patterns for the following nodes:
714 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
715 setTargetDAGCombine(ISD::SELECT);
716 setTargetDAGCombine(ISD::STORE);
718 computeRegisterProperties();
720 // FIXME: These should be based on subtarget info. Plus, the values should
721 // be smaller when we are in optimizing for size mode.
722 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
723 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
724 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
725 allowUnalignedMemoryAccesses = true; // x86 supports it!
726 setPrefLoopAlignment(16);
731 X86TargetLowering::getSetCCResultType(const SDOperand &) const {
736 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
737 /// the desired ByVal argument alignment.
738 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
741 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
742 if (VTy->getBitWidth() == 128)
744 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
745 unsigned EltAlign = 0;
746 getMaxByValAlign(ATy->getElementType(), EltAlign);
747 if (EltAlign > MaxAlign)
749 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
750 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
751 unsigned EltAlign = 0;
752 getMaxByValAlign(STy->getElementType(i), EltAlign);
753 if (EltAlign > MaxAlign)
762 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
763 /// function arguments in the caller parameter area. For X86, aggregates
764 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
765 /// are at 4-byte boundaries.
766 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
767 if (Subtarget->is64Bit())
768 return getTargetData()->getABITypeAlignment(Ty);
770 if (Subtarget->hasSSE1())
771 getMaxByValAlign(Ty, Align);
775 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
777 SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
778 SelectionDAG &DAG) const {
779 if (usesGlobalOffsetTable())
780 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
781 if (!Subtarget->isPICStyleRIPRel())
782 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
786 //===----------------------------------------------------------------------===//
787 // Return Value Calling Convention Implementation
788 //===----------------------------------------------------------------------===//
790 #include "X86GenCallingConv.inc"
792 /// GetPossiblePreceedingTailCall - Get preceeding X86ISD::TAILCALL node if it
793 /// exists skip possible ISD:TokenFactor.
794 static SDOperand GetPossiblePreceedingTailCall(SDOperand Chain) {
795 if (Chain.getOpcode() == X86ISD::TAILCALL) {
797 } else if (Chain.getOpcode() == ISD::TokenFactor) {
798 if (Chain.getNumOperands() &&
799 Chain.getOperand(0).getOpcode() == X86ISD::TAILCALL)
800 return Chain.getOperand(0);
805 /// LowerRET - Lower an ISD::RET node.
806 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
807 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
809 SmallVector<CCValAssign, 16> RVLocs;
810 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
811 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
812 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
813 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
815 // If this is the first return lowered for this function, add the regs to the
816 // liveout set for the function.
817 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
818 for (unsigned i = 0; i != RVLocs.size(); ++i)
819 if (RVLocs[i].isRegLoc())
820 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
822 SDOperand Chain = Op.getOperand(0);
824 // Handle tail call return.
825 Chain = GetPossiblePreceedingTailCall(Chain);
826 if (Chain.getOpcode() == X86ISD::TAILCALL) {
827 SDOperand TailCall = Chain;
828 SDOperand TargetAddress = TailCall.getOperand(1);
829 SDOperand StackAdjustment = TailCall.getOperand(2);
830 assert(((TargetAddress.getOpcode() == ISD::Register &&
831 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
832 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
833 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
834 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
835 "Expecting an global address, external symbol, or register");
836 assert(StackAdjustment.getOpcode() == ISD::Constant &&
837 "Expecting a const value");
839 SmallVector<SDOperand,8> Operands;
840 Operands.push_back(Chain.getOperand(0));
841 Operands.push_back(TargetAddress);
842 Operands.push_back(StackAdjustment);
843 // Copy registers used by the call. Last operand is a flag so it is not
845 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
846 Operands.push_back(Chain.getOperand(i));
848 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
855 SmallVector<SDOperand, 6> RetOps;
856 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
857 // Operand #1 = Bytes To Pop
858 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
860 // Copy the result values into the output registers.
861 for (unsigned i = 0; i != RVLocs.size(); ++i) {
862 CCValAssign &VA = RVLocs[i];
863 assert(VA.isRegLoc() && "Can only return in registers!");
864 SDOperand ValToCopy = Op.getOperand(i*2+1);
866 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
867 // the RET instruction and handled by the FP Stackifier.
868 if (RVLocs[i].getLocReg() == X86::ST0 ||
869 RVLocs[i].getLocReg() == X86::ST1) {
870 // If this is a copy from an xmm register to ST(0), use an FPExtend to
871 // change the value to the FP stack register class.
872 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
873 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
874 RetOps.push_back(ValToCopy);
875 // Don't emit a copytoreg.
879 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
880 Flag = Chain.getValue(1);
883 RetOps[0] = Chain; // Update chain.
885 // Add the flag if we have it.
887 RetOps.push_back(Flag);
889 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
893 /// LowerCallResult - Lower the result values of an ISD::CALL into the
894 /// appropriate copies out of appropriate physical registers. This assumes that
895 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
896 /// being lowered. The returns a SDNode with the same number of values as the
898 SDNode *X86TargetLowering::
899 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
900 unsigned CallingConv, SelectionDAG &DAG) {
902 // Assign locations to each value returned by this call.
903 SmallVector<CCValAssign, 16> RVLocs;
904 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
905 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
906 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
908 SmallVector<SDOperand, 8> ResultVals;
910 // Copy all of the result registers out of their specified physreg.
911 for (unsigned i = 0; i != RVLocs.size(); ++i) {
912 MVT::ValueType CopyVT = RVLocs[i].getValVT();
914 // If this is a call to a function that returns an fp value on the floating
915 // point stack, but where we prefer to use the value in xmm registers, copy
916 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
917 if (RVLocs[i].getLocReg() == X86::ST0 &&
918 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
922 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
923 CopyVT, InFlag).getValue(1);
924 SDOperand Val = Chain.getValue(0);
925 InFlag = Chain.getValue(2);
927 if (CopyVT != RVLocs[i].getValVT()) {
928 // Round the F80 the right size, which also moves to the appropriate xmm
930 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
931 // This truncation won't change the value.
932 DAG.getIntPtrConstant(1));
935 ResultVals.push_back(Val);
938 // Merge everything together with a MERGE_VALUES node.
939 ResultVals.push_back(Chain);
940 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
941 &ResultVals[0], ResultVals.size()).Val;
945 //===----------------------------------------------------------------------===//
946 // C & StdCall & Fast Calling Convention implementation
947 //===----------------------------------------------------------------------===//
948 // StdCall calling convention seems to be standard for many Windows' API
949 // routines and around. It differs from C calling convention just a little:
950 // callee should clean up the stack, not caller. Symbols should be also
951 // decorated in some fancy way :) It doesn't support any vector arguments.
952 // For info on fast calling convention see Fast Calling Convention (tail call)
953 // implementation LowerX86_32FastCCCallTo.
955 /// AddLiveIn - This helper function adds the specified physical register to the
956 /// MachineFunction as a live in value. It also creates a corresponding virtual
958 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
959 const TargetRegisterClass *RC) {
960 assert(RC->contains(PReg) && "Not the correct regclass!");
961 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
962 MF.getRegInfo().addLiveIn(PReg, VReg);
966 /// CallIsStructReturn - Determines whether a CALL node uses struct return
968 static bool CallIsStructReturn(SDOperand Op) {
969 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
973 return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet();
976 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
977 /// return semantics.
978 static bool ArgsAreStructReturn(SDOperand Op) {
979 unsigned NumArgs = Op.Val->getNumValues() - 1;
983 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
986 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires the
987 /// callee to pop its own arguments. Callee pop is necessary to support tail
989 bool X86TargetLowering::IsCalleePop(SDOperand Op) {
990 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
994 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
997 case CallingConv::X86_StdCall:
998 return !Subtarget->is64Bit();
999 case CallingConv::X86_FastCall:
1000 return !Subtarget->is64Bit();
1001 case CallingConv::Fast:
1002 return PerformTailCallOpt;
1006 /// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
1007 /// FORMAL_ARGUMENTS node.
1008 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
1009 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1011 if (Subtarget->is64Bit()) {
1012 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw())
1013 return CC_X86_Win64_C;
1015 if (CC == CallingConv::Fast && PerformTailCallOpt)
1016 return CC_X86_64_TailCall;
1022 if (CC == CallingConv::X86_FastCall)
1023 return CC_X86_32_FastCall;
1024 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1025 return CC_X86_32_TailCall;
1030 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1031 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1033 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
1034 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1035 if (CC == CallingConv::X86_FastCall)
1037 else if (CC == CallingConv::X86_StdCall)
1042 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
1043 /// possibly be overwritten when lowering the outgoing arguments in a tail
1044 /// call. Currently the implementation of this call is very conservative and
1045 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
1046 /// virtual registers would be overwritten by direct lowering.
1047 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op,
1048 MachineFrameInfo * MFI) {
1049 RegisterSDNode * OpReg = NULL;
1050 FrameIndexSDNode * FrameIdxNode = NULL;
1052 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
1053 (Op.getOpcode()== ISD::CopyFromReg &&
1054 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) &&
1055 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
1056 (Op.getOpcode() == ISD::LOAD &&
1057 (FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op.getOperand(1))) &&
1058 (MFI->isFixedObjectIndex((FrameIdx = FrameIdxNode->getIndex()))) &&
1059 (MFI->getObjectOffset(FrameIdx) >= 0)))
1064 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1065 /// in a register before calling.
1066 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1067 return !IsTailCall && !Is64Bit &&
1068 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1069 Subtarget->isPICStyleGOT();
1073 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1074 /// address to be loaded in a register.
1076 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1077 return !Is64Bit && IsTailCall &&
1078 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1079 Subtarget->isPICStyleGOT();
1082 /// CopyTailCallClobberedArgumentsToVRegs - Create virtual registers for all
1083 /// arguments to force loading and guarantee that arguments sourcing from
1084 /// incomming parameters are not overwriting each other.
1086 CopyTailCallClobberedArgumentsToVRegs(SDOperand Chain,
1087 SmallVector<std::pair<unsigned, SDOperand>, 8> &TailCallClobberedVRegs,
1089 MachineFunction &MF,
1090 const TargetLowering * TL) {
1093 for (unsigned i = 0, e = TailCallClobberedVRegs.size(); i != e; i++) {
1094 SDOperand Arg = TailCallClobberedVRegs[i].second;
1095 unsigned Idx = TailCallClobberedVRegs[i].first;
1098 createVirtualRegister(TL->getRegClassFor(Arg.getValueType()));
1099 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
1100 InFlag = Chain.getValue(1);
1101 Arg = DAG.getCopyFromReg(Chain, VReg, Arg.getValueType(), InFlag);
1102 TailCallClobberedVRegs[i] = std::make_pair(Idx, Arg);
1103 Chain = Arg.getValue(1);
1104 InFlag = Arg.getValue(2);
1109 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1110 /// by "Src" to address "Dst" with size and alignment information specified by
1111 /// the specific parameter attribute. The copy will be passed as a byval function
1114 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
1115 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1116 SDOperand AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1117 SDOperand SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1118 SDOperand AlwaysInline = DAG.getConstant(1, MVT::i32);
1119 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline);
1122 SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
1123 const CCValAssign &VA,
1124 MachineFrameInfo *MFI,
1126 SDOperand Root, unsigned i) {
1127 // Create the nodes corresponding to a load from this parameter slot.
1128 ISD::ArgFlagsTy Flags =
1129 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1130 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1131 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1133 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1134 // changed with more analysis.
1135 // In case of tail call optimization mark all arguments mutable. Since they
1136 // could be overwritten by lowering of arguments in case of a tail call.
1137 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1138 VA.getLocMemOffset(), isImmutable);
1139 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1140 if (Flags.isByVal())
1142 return DAG.getLoad(VA.getValVT(), Root, FIN,
1143 PseudoSourceValue::getFixedStack(), FI);
1147 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
1148 MachineFunction &MF = DAG.getMachineFunction();
1149 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1151 const Function* Fn = MF.getFunction();
1152 if (Fn->hasExternalLinkage() &&
1153 Subtarget->isTargetCygMing() &&
1154 Fn->getName() == "main")
1155 FuncInfo->setForceFramePointer(true);
1157 // Decorate the function name.
1158 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1160 MachineFrameInfo *MFI = MF.getFrameInfo();
1161 SDOperand Root = Op.getOperand(0);
1162 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1163 unsigned CC = MF.getFunction()->getCallingConv();
1164 bool Is64Bit = Subtarget->is64Bit();
1166 assert(!(isVarArg && CC == CallingConv::Fast) &&
1167 "Var args not supported with calling convention fastcc");
1169 // Assign locations to all of the incoming arguments.
1170 SmallVector<CCValAssign, 16> ArgLocs;
1171 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1172 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
1174 SmallVector<SDOperand, 8> ArgValues;
1175 unsigned LastVal = ~0U;
1176 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1177 CCValAssign &VA = ArgLocs[i];
1178 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1180 assert(VA.getValNo() != LastVal &&
1181 "Don't support value assigned to multiple locs yet");
1182 LastVal = VA.getValNo();
1184 if (VA.isRegLoc()) {
1185 MVT::ValueType RegVT = VA.getLocVT();
1186 TargetRegisterClass *RC;
1187 if (RegVT == MVT::i32)
1188 RC = X86::GR32RegisterClass;
1189 else if (Is64Bit && RegVT == MVT::i64)
1190 RC = X86::GR64RegisterClass;
1191 else if (RegVT == MVT::f32)
1192 RC = X86::FR32RegisterClass;
1193 else if (RegVT == MVT::f64)
1194 RC = X86::FR64RegisterClass;
1196 assert(MVT::isVector(RegVT));
1197 if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) {
1198 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1201 RC = X86::VR128RegisterClass;
1204 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1205 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1207 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1208 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1210 if (VA.getLocInfo() == CCValAssign::SExt)
1211 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1212 DAG.getValueType(VA.getValVT()));
1213 else if (VA.getLocInfo() == CCValAssign::ZExt)
1214 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1215 DAG.getValueType(VA.getValVT()));
1217 if (VA.getLocInfo() != CCValAssign::Full)
1218 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1220 // Handle MMX values passed in GPRs.
1221 if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1222 MVT::getSizeInBits(RegVT) == 64)
1223 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1225 ArgValues.push_back(ArgValue);
1227 assert(VA.isMemLoc());
1228 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1232 unsigned StackSize = CCInfo.getNextStackOffset();
1233 // align stack specially for tail calls
1234 if (CC == CallingConv::Fast)
1235 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1237 // If the function takes variable number of arguments, make a frame index for
1238 // the start of the first vararg value... for expansion of llvm.va_start.
1240 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1241 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1244 static const unsigned GPR64ArgRegs[] = {
1245 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1247 static const unsigned XMMArgRegs[] = {
1248 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1249 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1252 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1253 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1255 // For X86-64, if there are vararg parameters that are passed via
1256 // registers, then we must store them to their spots on the stack so they
1257 // may be loaded by deferencing the result of va_next.
1258 VarArgsGPOffset = NumIntRegs * 8;
1259 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1260 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1262 // Store the integer parameter registers.
1263 SmallVector<SDOperand, 8> MemOps;
1264 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1265 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1266 DAG.getIntPtrConstant(VarArgsGPOffset));
1267 for (; NumIntRegs != 6; ++NumIntRegs) {
1268 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1269 X86::GR64RegisterClass);
1270 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1272 DAG.getStore(Val.getValue(1), Val, FIN,
1273 PseudoSourceValue::getFixedStack(),
1275 MemOps.push_back(Store);
1276 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1277 DAG.getIntPtrConstant(8));
1280 // Now store the XMM (fp + vector) parameter registers.
1281 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1282 DAG.getIntPtrConstant(VarArgsFPOffset));
1283 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1284 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1285 X86::VR128RegisterClass);
1286 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1288 DAG.getStore(Val.getValue(1), Val, FIN,
1289 PseudoSourceValue::getFixedStack(),
1291 MemOps.push_back(Store);
1292 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1293 DAG.getIntPtrConstant(16));
1295 if (!MemOps.empty())
1296 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1297 &MemOps[0], MemOps.size());
1301 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1302 // arguments and the arguments after the retaddr has been pushed are
1304 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1305 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1306 (StackSize & 7) == 0)
1309 ArgValues.push_back(Root);
1311 // Some CCs need callee pop.
1312 if (IsCalleePop(Op)) {
1313 BytesToPopOnReturn = StackSize; // Callee pops everything.
1314 BytesCallerReserves = 0;
1316 BytesToPopOnReturn = 0; // Callee pops nothing.
1317 // If this is an sret function, the return should pop the hidden pointer.
1318 if (!Is64Bit && ArgsAreStructReturn(Op))
1319 BytesToPopOnReturn = 4;
1320 BytesCallerReserves = StackSize;
1324 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1325 if (CC == CallingConv::X86_FastCall)
1326 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1329 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1331 // Return the new list of results.
1332 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1333 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1337 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1338 const SDOperand &StackPtr,
1339 const CCValAssign &VA,
1342 unsigned LocMemOffset = VA.getLocMemOffset();
1343 SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1344 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1345 ISD::ArgFlagsTy Flags =
1346 cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags();
1347 if (Flags.isByVal()) {
1348 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1350 return DAG.getStore(Chain, Arg, PtrOff,
1351 PseudoSourceValue::getStack(), LocMemOffset);
1355 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1356 MachineFunction &MF = DAG.getMachineFunction();
1357 MachineFrameInfo * MFI = MF.getFrameInfo();
1358 SDOperand Chain = Op.getOperand(0);
1359 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1360 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1361 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1362 && CC == CallingConv::Fast && PerformTailCallOpt;
1363 SDOperand Callee = Op.getOperand(4);
1364 bool Is64Bit = Subtarget->is64Bit();
1365 bool IsStructRet = CallIsStructReturn(Op);
1367 assert(!(isVarArg && CC == CallingConv::Fast) &&
1368 "Var args not supported with calling convention fastcc");
1370 // Analyze operands of the call, assigning locations to each operand.
1371 SmallVector<CCValAssign, 16> ArgLocs;
1372 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1373 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
1375 // Get a count of how many bytes are to be pushed on the stack.
1376 unsigned NumBytes = CCInfo.getNextStackOffset();
1377 if (CC == CallingConv::Fast)
1378 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1380 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1381 // arguments and the arguments after the retaddr has been pushed are aligned.
1382 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1383 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1384 (NumBytes & 7) == 0)
1389 // Lower arguments at fp - stackoffset + fpdiff.
1390 unsigned NumBytesCallerPushed =
1391 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1392 FPDiff = NumBytesCallerPushed - NumBytes;
1394 // Set the delta of movement of the returnaddr stackslot.
1395 // But only set if delta is greater than previous delta.
1396 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1397 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1400 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
1402 SDOperand RetAddrFrIdx;
1404 // Adjust the Return address stack slot.
1406 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32;
1407 RetAddrFrIdx = getReturnAddressFrameIndex(DAG);
1408 // Load the "old" Return address.
1410 DAG.getLoad(VT, Chain,RetAddrFrIdx, NULL, 0);
1411 Chain = SDOperand(RetAddrFrIdx.Val, 1);
1415 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1416 SmallVector<std::pair<unsigned, SDOperand>, 8> TailCallClobberedVRegs;
1417 SmallVector<SDOperand, 8> MemOpChains;
1421 // Walk the register/memloc assignments, inserting copies/loads. For tail
1422 // calls, remember all arguments for later special lowering.
1423 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1424 CCValAssign &VA = ArgLocs[i];
1425 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1427 // Promote the value if needed.
1428 switch (VA.getLocInfo()) {
1429 default: assert(0 && "Unknown loc info!");
1430 case CCValAssign::Full: break;
1431 case CCValAssign::SExt:
1432 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1434 case CCValAssign::ZExt:
1435 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1437 case CCValAssign::AExt:
1438 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1442 if (VA.isRegLoc()) {
1443 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1446 assert(VA.isMemLoc());
1447 if (StackPtr.Val == 0)
1448 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1450 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1452 } else if (IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
1453 TailCallClobberedVRegs.push_back(std::make_pair(i,Arg));
1458 if (!MemOpChains.empty())
1459 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1460 &MemOpChains[0], MemOpChains.size());
1462 // Build a sequence of copy-to-reg nodes chained together with token chain
1463 // and flag operands which copy the outgoing args into registers.
1465 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1466 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1468 InFlag = Chain.getValue(1);
1471 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1473 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1474 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1475 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1477 InFlag = Chain.getValue(1);
1479 // If we are tail calling and generating PIC/GOT style code load the address
1480 // of the callee into ecx. The value in ecx is used as target of the tail
1481 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1482 // calls on PIC/GOT architectures. Normally we would just put the address of
1483 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1484 // restored (since ebx is callee saved) before jumping to the target@PLT.
1485 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1486 // Note: The actual moving to ecx is done further down.
1487 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1488 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1489 !G->getGlobal()->hasProtectedVisibility())
1490 Callee = LowerGlobalAddress(Callee, DAG);
1491 else if (isa<ExternalSymbolSDNode>(Callee))
1492 Callee = LowerExternalSymbol(Callee,DAG);
1495 if (Is64Bit && isVarArg) {
1496 // From AMD64 ABI document:
1497 // For calls that may call functions that use varargs or stdargs
1498 // (prototype-less calls or calls to functions containing ellipsis (...) in
1499 // the declaration) %al is used as hidden argument to specify the number
1500 // of SSE registers used. The contents of %al do not need to match exactly
1501 // the number of registers, but must be an ubound on the number of SSE
1502 // registers used and is in the range 0 - 8 inclusive.
1504 // Count the number of XMM registers allocated.
1505 static const unsigned XMMArgRegs[] = {
1506 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1507 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1509 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1511 Chain = DAG.getCopyToReg(Chain, X86::AL,
1512 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1513 InFlag = Chain.getValue(1);
1517 // For tail calls lower the arguments to the 'real' stack slot.
1519 SmallVector<SDOperand, 8> MemOpChains2;
1522 // Do not flag preceeding copytoreg stuff together with the following stuff.
1523 InFlag = SDOperand();
1525 Chain = CopyTailCallClobberedArgumentsToVRegs(Chain, TailCallClobberedVRegs,
1528 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1529 CCValAssign &VA = ArgLocs[i];
1530 if (!VA.isRegLoc()) {
1531 assert(VA.isMemLoc());
1532 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1533 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1534 ISD::ArgFlagsTy Flags =
1535 cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags();
1536 // Create frame index.
1537 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1538 uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8;
1539 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1540 FIN = DAG.getFrameIndex(FI, MVT::i32);
1542 // Find virtual register for this argument.
1544 for (unsigned idx=0, e= TailCallClobberedVRegs.size(); idx < e; idx++)
1545 if (TailCallClobberedVRegs[idx].first==i) {
1546 Arg = TailCallClobberedVRegs[idx].second;
1550 assert(IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)==false ||
1551 (Found==true && "No corresponding Argument was found"));
1553 if (Flags.isByVal()) {
1554 // Copy relative to framepointer.
1555 MemOpChains2.push_back(CreateCopyOfByValArgument(Arg, FIN, Chain,
1558 // Store relative to framepointer.
1559 MemOpChains2.push_back(
1560 DAG.getStore(Chain, Arg, FIN,
1561 PseudoSourceValue::getFixedStack(), FI));
1566 if (!MemOpChains2.empty())
1567 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1568 &MemOpChains2[0], MemOpChains2.size());
1570 // Store the return address to the appropriate stack slot.
1572 // Calculate the new stack slot for the return address.
1573 int SlotSize = Is64Bit ? 8 : 4;
1574 int NewReturnAddrFI =
1575 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1576 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32;
1577 SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1578 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1579 PseudoSourceValue::getFixedStack(), NewReturnAddrFI);
1583 // If the callee is a GlobalAddress node (quite common, every direct call is)
1584 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1585 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1586 // We should use extra load for direct calls to dllimported functions in
1588 if ((IsTailCall || !Is64Bit ||
1589 getTargetMachine().getCodeModel() != CodeModel::Large)
1590 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1591 getTargetMachine(), true))
1592 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1593 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1594 if (IsTailCall || !Is64Bit ||
1595 getTargetMachine().getCodeModel() != CodeModel::Large)
1596 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1597 } else if (IsTailCall) {
1598 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1600 Chain = DAG.getCopyToReg(Chain,
1601 DAG.getRegister(Opc, getPointerTy()),
1603 Callee = DAG.getRegister(Opc, getPointerTy());
1604 // Add register as live out.
1605 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1608 // Returns a chain & a flag for retval copy to use.
1609 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1610 SmallVector<SDOperand, 8> Ops;
1613 Ops.push_back(Chain);
1614 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1615 Ops.push_back(DAG.getIntPtrConstant(0));
1617 Ops.push_back(InFlag);
1618 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1619 InFlag = Chain.getValue(1);
1621 // Returns a chain & a flag for retval copy to use.
1622 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1626 Ops.push_back(Chain);
1627 Ops.push_back(Callee);
1630 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1632 // Add argument registers to the end of the list so that they are known live
1634 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1635 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1636 RegsToPass[i].second.getValueType()));
1638 // Add an implicit use GOT pointer in EBX.
1639 if (!IsTailCall && !Is64Bit &&
1640 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1641 Subtarget->isPICStyleGOT())
1642 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1644 // Add an implicit use of AL for x86 vararg functions.
1645 if (Is64Bit && isVarArg)
1646 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1649 Ops.push_back(InFlag);
1652 assert(InFlag.Val &&
1653 "Flag must be set. Depend on flag being set in LowerRET");
1654 Chain = DAG.getNode(X86ISD::TAILCALL,
1655 Op.Val->getVTList(), &Ops[0], Ops.size());
1657 return SDOperand(Chain.Val, Op.ResNo);
1660 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1661 InFlag = Chain.getValue(1);
1663 // Create the CALLSEQ_END node.
1664 unsigned NumBytesForCalleeToPush;
1665 if (IsCalleePop(Op))
1666 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1667 else if (!Is64Bit && IsStructRet)
1668 // If this is is a call to a struct-return function, the callee
1669 // pops the hidden struct pointer, so we have to push it back.
1670 // This is common for Darwin/X86, Linux & Mingw32 targets.
1671 NumBytesForCalleeToPush = 4;
1673 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1675 // Returns a flag for retval copy to use.
1676 Chain = DAG.getCALLSEQ_END(Chain,
1677 DAG.getIntPtrConstant(NumBytes),
1678 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
1680 InFlag = Chain.getValue(1);
1682 // Handle result values, copying them out of physregs into vregs that we
1684 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1688 //===----------------------------------------------------------------------===//
1689 // Fast Calling Convention (tail call) implementation
1690 //===----------------------------------------------------------------------===//
1692 // Like std call, callee cleans arguments, convention except that ECX is
1693 // reserved for storing the tail called function address. Only 2 registers are
1694 // free for argument passing (inreg). Tail call optimization is performed
1696 // * tailcallopt is enabled
1697 // * caller/callee are fastcc
1698 // On X86_64 architecture with GOT-style position independent code only local
1699 // (within module) calls are supported at the moment.
1700 // To keep the stack aligned according to platform abi the function
1701 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1702 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1703 // If a tail called function callee has more arguments than the caller the
1704 // caller needs to make sure that there is room to move the RETADDR to. This is
1705 // achieved by reserving an area the size of the argument delta right after the
1706 // original REtADDR, but before the saved framepointer or the spilled registers
1707 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1719 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1720 /// for a 16 byte align requirement.
1721 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1722 SelectionDAG& DAG) {
1723 if (PerformTailCallOpt) {
1724 MachineFunction &MF = DAG.getMachineFunction();
1725 const TargetMachine &TM = MF.getTarget();
1726 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1727 unsigned StackAlignment = TFI.getStackAlignment();
1728 uint64_t AlignMask = StackAlignment - 1;
1729 int64_t Offset = StackSize;
1730 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1731 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1732 // Number smaller than 12 so just add the difference.
1733 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1735 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1736 Offset = ((~AlignMask) & Offset) + StackAlignment +
1737 (StackAlignment-SlotSize);
1744 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1745 /// following the call is a return. A function is eligible if caller/callee
1746 /// calling conventions match, currently only fastcc supports tail calls, and
1747 /// the function CALL is immediatly followed by a RET.
1748 bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1750 SelectionDAG& DAG) const {
1751 if (!PerformTailCallOpt)
1754 // Check whether CALL node immediatly preceeds the RET node and whether the
1755 // return uses the result of the node or is a void return.
1756 unsigned NumOps = Ret.getNumOperands();
1758 (Ret.getOperand(0) == SDOperand(Call.Val,1) ||
1759 Ret.getOperand(0) == SDOperand(Call.Val,0))) ||
1761 Ret.getOperand(0) == SDOperand(Call.Val,Call.Val->getNumValues()-1) &&
1762 Ret.getOperand(1) == SDOperand(Call.Val,0))) {
1763 MachineFunction &MF = DAG.getMachineFunction();
1764 unsigned CallerCC = MF.getFunction()->getCallingConv();
1765 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1766 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1767 SDOperand Callee = Call.getOperand(4);
1768 // On x86/32Bit PIC/GOT tail calls are supported.
1769 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1770 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1773 // Can only do local tail calls (in same module, hidden or protected) on
1774 // x86_64 PIC/GOT at the moment.
1775 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1776 return G->getGlobal()->hasHiddenVisibility()
1777 || G->getGlobal()->hasProtectedVisibility();
1784 //===----------------------------------------------------------------------===//
1785 // Other Lowering Hooks
1786 //===----------------------------------------------------------------------===//
1789 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1790 MachineFunction &MF = DAG.getMachineFunction();
1791 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1792 int ReturnAddrIndex = FuncInfo->getRAIndex();
1794 if (ReturnAddrIndex == 0) {
1795 // Set up a frame object for the return address.
1796 if (Subtarget->is64Bit())
1797 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1799 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1801 FuncInfo->setRAIndex(ReturnAddrIndex);
1804 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1809 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1810 /// specific condition code. It returns a false if it cannot do a direct
1811 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1813 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1814 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1815 SelectionDAG &DAG) {
1816 X86CC = X86::COND_INVALID;
1818 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1819 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1820 // X > -1 -> X == 0, jump !sign.
1821 RHS = DAG.getConstant(0, RHS.getValueType());
1822 X86CC = X86::COND_NS;
1824 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1825 // X < 0 -> X == 0, jump on sign.
1826 X86CC = X86::COND_S;
1828 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1830 RHS = DAG.getConstant(0, RHS.getValueType());
1831 X86CC = X86::COND_LE;
1836 switch (SetCCOpcode) {
1838 case ISD::SETEQ: X86CC = X86::COND_E; break;
1839 case ISD::SETGT: X86CC = X86::COND_G; break;
1840 case ISD::SETGE: X86CC = X86::COND_GE; break;
1841 case ISD::SETLT: X86CC = X86::COND_L; break;
1842 case ISD::SETLE: X86CC = X86::COND_LE; break;
1843 case ISD::SETNE: X86CC = X86::COND_NE; break;
1844 case ISD::SETULT: X86CC = X86::COND_B; break;
1845 case ISD::SETUGT: X86CC = X86::COND_A; break;
1846 case ISD::SETULE: X86CC = X86::COND_BE; break;
1847 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1850 // On a floating point condition, the flags are set as follows:
1852 // 0 | 0 | 0 | X > Y
1853 // 0 | 0 | 1 | X < Y
1854 // 1 | 0 | 0 | X == Y
1855 // 1 | 1 | 1 | unordered
1857 switch (SetCCOpcode) {
1860 case ISD::SETEQ: X86CC = X86::COND_E; break;
1861 case ISD::SETOLT: Flip = true; // Fallthrough
1863 case ISD::SETGT: X86CC = X86::COND_A; break;
1864 case ISD::SETOLE: Flip = true; // Fallthrough
1866 case ISD::SETGE: X86CC = X86::COND_AE; break;
1867 case ISD::SETUGT: Flip = true; // Fallthrough
1869 case ISD::SETLT: X86CC = X86::COND_B; break;
1870 case ISD::SETUGE: Flip = true; // Fallthrough
1872 case ISD::SETLE: X86CC = X86::COND_BE; break;
1874 case ISD::SETNE: X86CC = X86::COND_NE; break;
1875 case ISD::SETUO: X86CC = X86::COND_P; break;
1876 case ISD::SETO: X86CC = X86::COND_NP; break;
1879 std::swap(LHS, RHS);
1882 return X86CC != X86::COND_INVALID;
1885 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1886 /// code. Current x86 isa includes the following FP cmov instructions:
1887 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1888 static bool hasFPCMov(unsigned X86CC) {
1904 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1905 /// true if Op is undef or if its value falls within the specified range (L, H].
1906 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1907 if (Op.getOpcode() == ISD::UNDEF)
1910 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1911 return (Val >= Low && Val < Hi);
1914 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1915 /// true if Op is undef or if its value equal to the specified value.
1916 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1917 if (Op.getOpcode() == ISD::UNDEF)
1919 return cast<ConstantSDNode>(Op)->getValue() == Val;
1922 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1923 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1924 bool X86::isPSHUFDMask(SDNode *N) {
1925 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1927 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
1930 // Check if the value doesn't reference the second vector.
1931 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1932 SDOperand Arg = N->getOperand(i);
1933 if (Arg.getOpcode() == ISD::UNDEF) continue;
1934 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1935 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
1942 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1943 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1944 bool X86::isPSHUFHWMask(SDNode *N) {
1945 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1947 if (N->getNumOperands() != 8)
1950 // Lower quadword copied in order.
1951 for (unsigned i = 0; i != 4; ++i) {
1952 SDOperand Arg = N->getOperand(i);
1953 if (Arg.getOpcode() == ISD::UNDEF) continue;
1954 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1955 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1959 // Upper quadword shuffled.
1960 for (unsigned i = 4; i != 8; ++i) {
1961 SDOperand Arg = N->getOperand(i);
1962 if (Arg.getOpcode() == ISD::UNDEF) continue;
1963 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1964 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1965 if (Val < 4 || Val > 7)
1972 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1973 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1974 bool X86::isPSHUFLWMask(SDNode *N) {
1975 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1977 if (N->getNumOperands() != 8)
1980 // Upper quadword copied in order.
1981 for (unsigned i = 4; i != 8; ++i)
1982 if (!isUndefOrEqual(N->getOperand(i), i))
1985 // Lower quadword shuffled.
1986 for (unsigned i = 0; i != 4; ++i)
1987 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1993 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1994 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1995 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1996 if (NumElems != 2 && NumElems != 4) return false;
1998 unsigned Half = NumElems / 2;
1999 for (unsigned i = 0; i < Half; ++i)
2000 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2002 for (unsigned i = Half; i < NumElems; ++i)
2003 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2009 bool X86::isSHUFPMask(SDNode *N) {
2010 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2011 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2014 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2015 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2016 /// half elements to come from vector 1 (which would equal the dest.) and
2017 /// the upper half to come from vector 2.
2018 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
2019 if (NumOps != 2 && NumOps != 4) return false;
2021 unsigned Half = NumOps / 2;
2022 for (unsigned i = 0; i < Half; ++i)
2023 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2025 for (unsigned i = Half; i < NumOps; ++i)
2026 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2031 static bool isCommutedSHUFP(SDNode *N) {
2032 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2033 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2036 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2037 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2038 bool X86::isMOVHLPSMask(SDNode *N) {
2039 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2041 if (N->getNumOperands() != 4)
2044 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2045 return isUndefOrEqual(N->getOperand(0), 6) &&
2046 isUndefOrEqual(N->getOperand(1), 7) &&
2047 isUndefOrEqual(N->getOperand(2), 2) &&
2048 isUndefOrEqual(N->getOperand(3), 3);
2051 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2052 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2054 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2055 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2057 if (N->getNumOperands() != 4)
2060 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2061 return isUndefOrEqual(N->getOperand(0), 2) &&
2062 isUndefOrEqual(N->getOperand(1), 3) &&
2063 isUndefOrEqual(N->getOperand(2), 2) &&
2064 isUndefOrEqual(N->getOperand(3), 3);
2067 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2068 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2069 bool X86::isMOVLPMask(SDNode *N) {
2070 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2072 unsigned NumElems = N->getNumOperands();
2073 if (NumElems != 2 && NumElems != 4)
2076 for (unsigned i = 0; i < NumElems/2; ++i)
2077 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2080 for (unsigned i = NumElems/2; i < NumElems; ++i)
2081 if (!isUndefOrEqual(N->getOperand(i), i))
2087 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2088 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2090 bool X86::isMOVHPMask(SDNode *N) {
2091 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2093 unsigned NumElems = N->getNumOperands();
2094 if (NumElems != 2 && NumElems != 4)
2097 for (unsigned i = 0; i < NumElems/2; ++i)
2098 if (!isUndefOrEqual(N->getOperand(i), i))
2101 for (unsigned i = 0; i < NumElems/2; ++i) {
2102 SDOperand Arg = N->getOperand(i + NumElems/2);
2103 if (!isUndefOrEqual(Arg, i + NumElems))
2110 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2111 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2112 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
2113 bool V2IsSplat = false) {
2114 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2117 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2118 SDOperand BitI = Elts[i];
2119 SDOperand BitI1 = Elts[i+1];
2120 if (!isUndefOrEqual(BitI, j))
2123 if (isUndefOrEqual(BitI1, NumElts))
2126 if (!isUndefOrEqual(BitI1, j + NumElts))
2134 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2135 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2136 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2139 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2140 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2141 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
2142 bool V2IsSplat = false) {
2143 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2146 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2147 SDOperand BitI = Elts[i];
2148 SDOperand BitI1 = Elts[i+1];
2149 if (!isUndefOrEqual(BitI, j + NumElts/2))
2152 if (isUndefOrEqual(BitI1, NumElts))
2155 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2163 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2164 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2165 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2168 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2169 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2171 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2172 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2174 unsigned NumElems = N->getNumOperands();
2175 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2178 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2179 SDOperand BitI = N->getOperand(i);
2180 SDOperand BitI1 = N->getOperand(i+1);
2182 if (!isUndefOrEqual(BitI, j))
2184 if (!isUndefOrEqual(BitI1, j))
2191 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2192 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2194 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2195 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2197 unsigned NumElems = N->getNumOperands();
2198 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2201 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2202 SDOperand BitI = N->getOperand(i);
2203 SDOperand BitI1 = N->getOperand(i + 1);
2205 if (!isUndefOrEqual(BitI, j))
2207 if (!isUndefOrEqual(BitI1, j))
2214 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2215 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2216 /// MOVSD, and MOVD, i.e. setting the lowest element.
2217 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
2218 if (NumElts != 2 && NumElts != 4)
2221 if (!isUndefOrEqual(Elts[0], NumElts))
2224 for (unsigned i = 1; i < NumElts; ++i) {
2225 if (!isUndefOrEqual(Elts[i], i))
2232 bool X86::isMOVLMask(SDNode *N) {
2233 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2234 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2237 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2238 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2239 /// element of vector 2 and the other elements to come from vector 1 in order.
2240 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
2241 bool V2IsSplat = false,
2242 bool V2IsUndef = false) {
2243 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2246 if (!isUndefOrEqual(Ops[0], 0))
2249 for (unsigned i = 1; i < NumOps; ++i) {
2250 SDOperand Arg = Ops[i];
2251 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2252 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2253 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2260 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2261 bool V2IsUndef = false) {
2262 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2263 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2264 V2IsSplat, V2IsUndef);
2267 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2268 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2269 bool X86::isMOVSHDUPMask(SDNode *N) {
2270 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2272 if (N->getNumOperands() != 4)
2275 // Expect 1, 1, 3, 3
2276 for (unsigned i = 0; i < 2; ++i) {
2277 SDOperand Arg = N->getOperand(i);
2278 if (Arg.getOpcode() == ISD::UNDEF) continue;
2279 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2280 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2281 if (Val != 1) return false;
2285 for (unsigned i = 2; i < 4; ++i) {
2286 SDOperand Arg = N->getOperand(i);
2287 if (Arg.getOpcode() == ISD::UNDEF) continue;
2288 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2289 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2290 if (Val != 3) return false;
2294 // Don't use movshdup if it can be done with a shufps.
2298 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2299 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2300 bool X86::isMOVSLDUPMask(SDNode *N) {
2301 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2303 if (N->getNumOperands() != 4)
2306 // Expect 0, 0, 2, 2
2307 for (unsigned i = 0; i < 2; ++i) {
2308 SDOperand Arg = N->getOperand(i);
2309 if (Arg.getOpcode() == ISD::UNDEF) continue;
2310 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2311 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2312 if (Val != 0) return false;
2316 for (unsigned i = 2; i < 4; ++i) {
2317 SDOperand Arg = N->getOperand(i);
2318 if (Arg.getOpcode() == ISD::UNDEF) continue;
2319 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2320 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2321 if (Val != 2) return false;
2325 // Don't use movshdup if it can be done with a shufps.
2329 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2330 /// specifies a identity operation on the LHS or RHS.
2331 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2332 unsigned NumElems = N->getNumOperands();
2333 for (unsigned i = 0; i < NumElems; ++i)
2334 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2339 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2340 /// a splat of a single element.
2341 static bool isSplatMask(SDNode *N) {
2342 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2344 // This is a splat operation if each element of the permute is the same, and
2345 // if the value doesn't reference the second vector.
2346 unsigned NumElems = N->getNumOperands();
2347 SDOperand ElementBase;
2349 for (; i != NumElems; ++i) {
2350 SDOperand Elt = N->getOperand(i);
2351 if (isa<ConstantSDNode>(Elt)) {
2357 if (!ElementBase.Val)
2360 for (; i != NumElems; ++i) {
2361 SDOperand Arg = N->getOperand(i);
2362 if (Arg.getOpcode() == ISD::UNDEF) continue;
2363 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2364 if (Arg != ElementBase) return false;
2367 // Make sure it is a splat of the first vector operand.
2368 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2371 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2372 /// a splat of a single element and it's a 2 or 4 element mask.
2373 bool X86::isSplatMask(SDNode *N) {
2374 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2376 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2377 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2379 return ::isSplatMask(N);
2382 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2383 /// specifies a splat of zero element.
2384 bool X86::isSplatLoMask(SDNode *N) {
2385 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2387 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2388 if (!isUndefOrEqual(N->getOperand(i), 0))
2393 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2394 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2396 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2397 unsigned NumOperands = N->getNumOperands();
2398 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2400 for (unsigned i = 0; i < NumOperands; ++i) {
2402 SDOperand Arg = N->getOperand(NumOperands-i-1);
2403 if (Arg.getOpcode() != ISD::UNDEF)
2404 Val = cast<ConstantSDNode>(Arg)->getValue();
2405 if (Val >= NumOperands) Val -= NumOperands;
2407 if (i != NumOperands - 1)
2414 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2415 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2417 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2419 // 8 nodes, but we only care about the last 4.
2420 for (unsigned i = 7; i >= 4; --i) {
2422 SDOperand Arg = N->getOperand(i);
2423 if (Arg.getOpcode() != ISD::UNDEF)
2424 Val = cast<ConstantSDNode>(Arg)->getValue();
2433 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2434 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2436 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2438 // 8 nodes, but we only care about the first 4.
2439 for (int i = 3; i >= 0; --i) {
2441 SDOperand Arg = N->getOperand(i);
2442 if (Arg.getOpcode() != ISD::UNDEF)
2443 Val = cast<ConstantSDNode>(Arg)->getValue();
2452 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2453 /// specifies a 8 element shuffle that can be broken into a pair of
2454 /// PSHUFHW and PSHUFLW.
2455 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2456 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2458 if (N->getNumOperands() != 8)
2461 // Lower quadword shuffled.
2462 for (unsigned i = 0; i != 4; ++i) {
2463 SDOperand Arg = N->getOperand(i);
2464 if (Arg.getOpcode() == ISD::UNDEF) continue;
2465 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2466 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2471 // Upper quadword shuffled.
2472 for (unsigned i = 4; i != 8; ++i) {
2473 SDOperand Arg = N->getOperand(i);
2474 if (Arg.getOpcode() == ISD::UNDEF) continue;
2475 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2476 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2477 if (Val < 4 || Val > 7)
2484 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2485 /// values in ther permute mask.
2486 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2487 SDOperand &V2, SDOperand &Mask,
2488 SelectionDAG &DAG) {
2489 MVT::ValueType VT = Op.getValueType();
2490 MVT::ValueType MaskVT = Mask.getValueType();
2491 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2492 unsigned NumElems = Mask.getNumOperands();
2493 SmallVector<SDOperand, 8> MaskVec;
2495 for (unsigned i = 0; i != NumElems; ++i) {
2496 SDOperand Arg = Mask.getOperand(i);
2497 if (Arg.getOpcode() == ISD::UNDEF) {
2498 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2501 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2502 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2504 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2506 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2510 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2511 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2514 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2515 /// the two vector operands have swapped position.
2517 SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
2518 MVT::ValueType MaskVT = Mask.getValueType();
2519 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2520 unsigned NumElems = Mask.getNumOperands();
2521 SmallVector<SDOperand, 8> MaskVec;
2522 for (unsigned i = 0; i != NumElems; ++i) {
2523 SDOperand Arg = Mask.getOperand(i);
2524 if (Arg.getOpcode() == ISD::UNDEF) {
2525 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2528 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2529 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2531 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2533 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2535 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2539 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2540 /// match movhlps. The lower half elements should come from upper half of
2541 /// V1 (and in order), and the upper half elements should come from the upper
2542 /// half of V2 (and in order).
2543 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2544 unsigned NumElems = Mask->getNumOperands();
2547 for (unsigned i = 0, e = 2; i != e; ++i)
2548 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2550 for (unsigned i = 2; i != 4; ++i)
2551 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2556 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2557 /// is promoted to a vector.
2558 static inline bool isScalarLoadToVector(SDNode *N) {
2559 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2560 N = N->getOperand(0).Val;
2561 return ISD::isNON_EXTLoad(N);
2566 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2567 /// match movlp{s|d}. The lower half elements should come from lower half of
2568 /// V1 (and in order), and the upper half elements should come from the upper
2569 /// half of V2 (and in order). And since V1 will become the source of the
2570 /// MOVLP, it must be either a vector load or a scalar load to vector.
2571 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2572 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2574 // Is V2 is a vector load, don't do this transformation. We will try to use
2575 // load folding shufps op.
2576 if (ISD::isNON_EXTLoad(V2))
2579 unsigned NumElems = Mask->getNumOperands();
2580 if (NumElems != 2 && NumElems != 4)
2582 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2583 if (!isUndefOrEqual(Mask->getOperand(i), i))
2585 for (unsigned i = NumElems/2; i != NumElems; ++i)
2586 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2591 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2593 static bool isSplatVector(SDNode *N) {
2594 if (N->getOpcode() != ISD::BUILD_VECTOR)
2597 SDOperand SplatValue = N->getOperand(0);
2598 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2599 if (N->getOperand(i) != SplatValue)
2604 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2606 static bool isUndefShuffle(SDNode *N) {
2607 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2610 SDOperand V1 = N->getOperand(0);
2611 SDOperand V2 = N->getOperand(1);
2612 SDOperand Mask = N->getOperand(2);
2613 unsigned NumElems = Mask.getNumOperands();
2614 for (unsigned i = 0; i != NumElems; ++i) {
2615 SDOperand Arg = Mask.getOperand(i);
2616 if (Arg.getOpcode() != ISD::UNDEF) {
2617 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2618 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2620 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2627 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2629 static inline bool isZeroNode(SDOperand Elt) {
2630 return ((isa<ConstantSDNode>(Elt) &&
2631 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2632 (isa<ConstantFPSDNode>(Elt) &&
2633 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2636 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2637 /// to an zero vector.
2638 static bool isZeroShuffle(SDNode *N) {
2639 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2642 SDOperand V1 = N->getOperand(0);
2643 SDOperand V2 = N->getOperand(1);
2644 SDOperand Mask = N->getOperand(2);
2645 unsigned NumElems = Mask.getNumOperands();
2646 for (unsigned i = 0; i != NumElems; ++i) {
2647 SDOperand Arg = Mask.getOperand(i);
2648 if (Arg.getOpcode() == ISD::UNDEF)
2651 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2652 if (Idx < NumElems) {
2653 unsigned Opc = V1.Val->getOpcode();
2654 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2656 if (Opc != ISD::BUILD_VECTOR ||
2657 !isZeroNode(V1.Val->getOperand(Idx)))
2659 } else if (Idx >= NumElems) {
2660 unsigned Opc = V2.Val->getOpcode();
2661 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2663 if (Opc != ISD::BUILD_VECTOR ||
2664 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2671 /// getZeroVector - Returns a vector of specified type with all zero elements.
2673 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2674 assert(MVT::isVector(VT) && "Expected a vector type");
2676 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2677 // type. This ensures they get CSE'd.
2678 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2680 if (MVT::getSizeInBits(VT) == 64) // MMX
2681 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2683 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2684 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2687 /// getOnesVector - Returns a vector of specified type with all bits set.
2689 static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) {
2690 assert(MVT::isVector(VT) && "Expected a vector type");
2692 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2693 // type. This ensures they get CSE'd.
2694 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
2696 if (MVT::getSizeInBits(VT) == 64) // MMX
2697 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2699 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2700 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2704 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2705 /// that point to V2 points to its first element.
2706 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2707 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2709 bool Changed = false;
2710 SmallVector<SDOperand, 8> MaskVec;
2711 unsigned NumElems = Mask.getNumOperands();
2712 for (unsigned i = 0; i != NumElems; ++i) {
2713 SDOperand Arg = Mask.getOperand(i);
2714 if (Arg.getOpcode() != ISD::UNDEF) {
2715 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2716 if (Val > NumElems) {
2717 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2721 MaskVec.push_back(Arg);
2725 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2726 &MaskVec[0], MaskVec.size());
2730 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2731 /// operation of specified width.
2732 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2733 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2734 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2736 SmallVector<SDOperand, 8> MaskVec;
2737 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2738 for (unsigned i = 1; i != NumElems; ++i)
2739 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2740 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2743 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2744 /// of specified width.
2745 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2746 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2747 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2748 SmallVector<SDOperand, 8> MaskVec;
2749 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2750 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2751 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2753 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2756 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2757 /// of specified width.
2758 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2759 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2760 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2761 unsigned Half = NumElems/2;
2762 SmallVector<SDOperand, 8> MaskVec;
2763 for (unsigned i = 0; i != Half; ++i) {
2764 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2765 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2767 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2770 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2771 /// element #0 of a vector with the specified index, leaving the rest of the
2772 /// elements in place.
2773 static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2774 SelectionDAG &DAG) {
2775 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2776 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2777 SmallVector<SDOperand, 8> MaskVec;
2778 // Element #0 of the result gets the elt we are replacing.
2779 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2780 for (unsigned i = 1; i != NumElems; ++i)
2781 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2782 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2785 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2787 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2788 SDOperand V1 = Op.getOperand(0);
2789 SDOperand Mask = Op.getOperand(2);
2790 MVT::ValueType VT = Op.getValueType();
2791 unsigned NumElems = Mask.getNumOperands();
2792 Mask = getUnpacklMask(NumElems, DAG);
2793 while (NumElems != 4) {
2794 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2797 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2799 Mask = getZeroVector(MVT::v4i32, DAG);
2800 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2801 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2802 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2805 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2806 /// vector of zero or undef vector. This produces a shuffle where the low
2807 /// element of V2 is swizzled into the zero/undef vector, landing at element
2808 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2809 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx,
2810 bool isZero, SelectionDAG &DAG) {
2811 MVT::ValueType VT = V2.getValueType();
2812 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2813 unsigned NumElems = MVT::getVectorNumElements(V2.getValueType());
2814 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2815 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2816 SmallVector<SDOperand, 16> MaskVec;
2817 for (unsigned i = 0; i != NumElems; ++i)
2818 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2819 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2821 MaskVec.push_back(DAG.getConstant(i, EVT));
2822 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2823 &MaskVec[0], MaskVec.size());
2824 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2827 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2829 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2830 unsigned NumNonZero, unsigned NumZero,
2831 SelectionDAG &DAG, TargetLowering &TLI) {
2837 for (unsigned i = 0; i < 16; ++i) {
2838 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2839 if (ThisIsNonZero && First) {
2841 V = getZeroVector(MVT::v8i16, DAG);
2843 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2848 SDOperand ThisElt(0, 0), LastElt(0, 0);
2849 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2850 if (LastIsNonZero) {
2851 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2853 if (ThisIsNonZero) {
2854 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2855 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2856 ThisElt, DAG.getConstant(8, MVT::i8));
2858 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2863 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2864 DAG.getIntPtrConstant(i/2));
2868 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2871 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2873 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2874 unsigned NumNonZero, unsigned NumZero,
2875 SelectionDAG &DAG, TargetLowering &TLI) {
2881 for (unsigned i = 0; i < 8; ++i) {
2882 bool isNonZero = (NonZeros & (1 << i)) != 0;
2886 V = getZeroVector(MVT::v8i16, DAG);
2888 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2891 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2892 DAG.getIntPtrConstant(i));
2900 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2901 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
2902 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
2903 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
2904 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
2905 // eliminated on x86-32 hosts.
2906 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
2909 if (ISD::isBuildVectorAllOnes(Op.Val))
2910 return getOnesVector(Op.getValueType(), DAG);
2911 return getZeroVector(Op.getValueType(), DAG);
2914 MVT::ValueType VT = Op.getValueType();
2915 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2916 unsigned EVTBits = MVT::getSizeInBits(EVT);
2918 unsigned NumElems = Op.getNumOperands();
2919 unsigned NumZero = 0;
2920 unsigned NumNonZero = 0;
2921 unsigned NonZeros = 0;
2922 bool IsAllConstants = true;
2923 SmallSet<SDOperand, 8> Values;
2924 for (unsigned i = 0; i < NumElems; ++i) {
2925 SDOperand Elt = Op.getOperand(i);
2926 if (Elt.getOpcode() == ISD::UNDEF)
2929 if (Elt.getOpcode() != ISD::Constant &&
2930 Elt.getOpcode() != ISD::ConstantFP)
2931 IsAllConstants = false;
2932 if (isZeroNode(Elt))
2935 NonZeros |= (1 << i);
2940 if (NumNonZero == 0) {
2941 // All undef vector. Return an UNDEF. All zero vectors were handled above.
2942 return DAG.getNode(ISD::UNDEF, VT);
2945 // Special case for single non-zero, non-undef, element.
2946 if (NumNonZero == 1 && NumElems <= 4) {
2947 unsigned Idx = CountTrailingZeros_32(NonZeros);
2948 SDOperand Item = Op.getOperand(Idx);
2950 // If this is an insertion of an i64 value on x86-32, and if the top bits of
2951 // the value are obviously zero, truncate the value to i32 and do the
2952 // insertion that way. Only do this if the value is non-constant or if the
2953 // value is a constant being inserted into element 0. It is cheaper to do
2954 // a constant pool load than it is to do a movd + shuffle.
2955 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
2956 (!IsAllConstants || Idx == 0)) {
2957 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
2958 // Handle MMX and SSE both.
2959 MVT::ValueType VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
2960 MVT::ValueType VecElts = VT == MVT::v2i64 ? 4 : 2;
2962 // Truncate the value (which may itself be a constant) to i32, and
2963 // convert it to a vector with movd (S2V+shuffle to zero extend).
2964 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
2965 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
2966 Item = getShuffleVectorZeroOrUndef(Item, 0, true, DAG);
2968 // Now we have our 32-bit value zero extended in the low element of
2969 // a vector. If Idx != 0, swizzle it into place.
2972 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
2973 getSwapEltZeroMask(VecElts, Idx, DAG)
2975 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
2977 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
2981 // If we have a constant or non-constant insertion into the low element of
2982 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
2983 // the rest of the elements. This will be matched as movd/movq/movss/movsd
2984 // depending on what the source datatype is. Because we can only get here
2985 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
2987 // Don't do this for i64 values on x86-32.
2988 (EVT != MVT::i64 || Subtarget->is64Bit())) {
2989 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2990 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2991 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, DAG);
2994 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
2997 // Otherwise, if this is a vector with i32 or f32 elements, and the element
2998 // is a non-constant being inserted into an element other than the low one,
2999 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3000 // movd/movss) to move this into the low element, then shuffle it into
3002 if (EVTBits == 32) {
3003 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3005 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3006 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, DAG);
3007 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3008 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3009 SmallVector<SDOperand, 8> MaskVec;
3010 for (unsigned i = 0; i < NumElems; i++)
3011 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3012 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3013 &MaskVec[0], MaskVec.size());
3014 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3015 DAG.getNode(ISD::UNDEF, VT), Mask);
3019 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3020 if (Values.size() == 1)
3023 // A vector full of immediates; various special cases are already
3024 // handled, so this is best done with a single constant-pool load.
3028 // Let legalizer expand 2-wide build_vectors.
3032 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3033 if (EVTBits == 8 && NumElems == 16) {
3034 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3036 if (V.Val) return V;
3039 if (EVTBits == 16 && NumElems == 8) {
3040 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3042 if (V.Val) return V;
3045 // If element VT is == 32 bits, turn it into a number of shuffles.
3046 SmallVector<SDOperand, 8> V;
3048 if (NumElems == 4 && NumZero > 0) {
3049 for (unsigned i = 0; i < 4; ++i) {
3050 bool isZero = !(NonZeros & (1 << i));
3052 V[i] = getZeroVector(VT, DAG);
3054 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3057 for (unsigned i = 0; i < 2; ++i) {
3058 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3061 V[i] = V[i*2]; // Must be a zero vector.
3064 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3065 getMOVLMask(NumElems, DAG));
3068 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3069 getMOVLMask(NumElems, DAG));
3072 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3073 getUnpacklMask(NumElems, DAG));
3078 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
3079 // clears the upper bits.
3080 // FIXME: we can do the same for v4f32 case when we know both parts of
3081 // the lower half come from scalar_to_vector (loadf32). We should do
3082 // that in post legalizer dag combiner with target specific hooks.
3083 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
3085 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3086 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
3087 SmallVector<SDOperand, 8> MaskVec;
3088 bool Reverse = (NonZeros & 0x3) == 2;
3089 for (unsigned i = 0; i < 2; ++i)
3091 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3093 MaskVec.push_back(DAG.getConstant(i, EVT));
3094 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3095 for (unsigned i = 0; i < 2; ++i)
3097 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3099 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3100 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3101 &MaskVec[0], MaskVec.size());
3102 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3105 if (Values.size() > 2) {
3106 // Expand into a number of unpckl*.
3108 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3109 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3110 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3111 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
3112 for (unsigned i = 0; i < NumElems; ++i)
3113 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3115 while (NumElems != 0) {
3116 for (unsigned i = 0; i < NumElems; ++i)
3117 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3128 SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
3129 SDOperand PermMask, SelectionDAG &DAG,
3130 TargetLowering &TLI) {
3132 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8);
3133 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3134 MVT::ValueType PtrVT = TLI.getPointerTy();
3135 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
3136 PermMask.Val->op_end());
3138 // First record which half of which vector the low elements come from.
3139 SmallVector<unsigned, 4> LowQuad(4);
3140 for (unsigned i = 0; i < 4; ++i) {
3141 SDOperand Elt = MaskElts[i];
3142 if (Elt.getOpcode() == ISD::UNDEF)
3144 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3145 int QuadIdx = EltIdx / 4;
3148 int BestLowQuad = -1;
3149 unsigned MaxQuad = 1;
3150 for (unsigned i = 0; i < 4; ++i) {
3151 if (LowQuad[i] > MaxQuad) {
3153 MaxQuad = LowQuad[i];
3157 // Record which half of which vector the high elements come from.
3158 SmallVector<unsigned, 4> HighQuad(4);
3159 for (unsigned i = 4; i < 8; ++i) {
3160 SDOperand Elt = MaskElts[i];
3161 if (Elt.getOpcode() == ISD::UNDEF)
3163 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3164 int QuadIdx = EltIdx / 4;
3165 ++HighQuad[QuadIdx];
3167 int BestHighQuad = -1;
3169 for (unsigned i = 0; i < 4; ++i) {
3170 if (HighQuad[i] > MaxQuad) {
3172 MaxQuad = HighQuad[i];
3176 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3177 if (BestLowQuad != -1 || BestHighQuad != -1) {
3178 // First sort the 4 chunks in order using shufpd.
3179 SmallVector<SDOperand, 8> MaskVec;
3180 if (BestLowQuad != -1)
3181 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3183 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3184 if (BestHighQuad != -1)
3185 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3187 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3188 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3189 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3190 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3191 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3192 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3194 // Now sort high and low parts separately.
3195 BitVector InOrder(8);
3196 if (BestLowQuad != -1) {
3197 // Sort lower half in order using PSHUFLW.
3199 bool AnyOutOrder = false;
3200 for (unsigned i = 0; i != 4; ++i) {
3201 SDOperand Elt = MaskElts[i];
3202 if (Elt.getOpcode() == ISD::UNDEF) {
3203 MaskVec.push_back(Elt);
3206 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3209 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3210 // If this element is in the right place after this shuffle, then
3212 if ((int)(EltIdx / 4) == BestLowQuad)
3217 for (unsigned i = 4; i != 8; ++i)
3218 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3219 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3220 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3224 if (BestHighQuad != -1) {
3225 // Sort high half in order using PSHUFHW if possible.
3227 for (unsigned i = 0; i != 4; ++i)
3228 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3229 bool AnyOutOrder = false;
3230 for (unsigned i = 4; i != 8; ++i) {
3231 SDOperand Elt = MaskElts[i];
3232 if (Elt.getOpcode() == ISD::UNDEF) {
3233 MaskVec.push_back(Elt);
3236 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3239 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3240 // If this element is in the right place after this shuffle, then
3242 if ((int)(EltIdx / 4) == BestHighQuad)
3247 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3248 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3252 // The other elements are put in the right place using pextrw and pinsrw.
3253 for (unsigned i = 0; i != 8; ++i) {
3256 SDOperand Elt = MaskElts[i];
3257 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3260 SDOperand ExtOp = (EltIdx < 8)
3261 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3262 DAG.getConstant(EltIdx, PtrVT))
3263 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3264 DAG.getConstant(EltIdx - 8, PtrVT));
3265 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3266 DAG.getConstant(i, PtrVT));
3271 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3272 ///as few as possible.
3273 // First, let's find out how many elements are already in the right order.
3274 unsigned V1InOrder = 0;
3275 unsigned V1FromV1 = 0;
3276 unsigned V2InOrder = 0;
3277 unsigned V2FromV2 = 0;
3278 SmallVector<SDOperand, 8> V1Elts;
3279 SmallVector<SDOperand, 8> V2Elts;
3280 for (unsigned i = 0; i < 8; ++i) {
3281 SDOperand Elt = MaskElts[i];
3282 if (Elt.getOpcode() == ISD::UNDEF) {
3283 V1Elts.push_back(Elt);
3284 V2Elts.push_back(Elt);
3289 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3291 V1Elts.push_back(Elt);
3292 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3294 } else if (EltIdx == i+8) {
3295 V1Elts.push_back(Elt);
3296 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3298 } else if (EltIdx < 8) {
3299 V1Elts.push_back(Elt);
3302 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3307 if (V2InOrder > V1InOrder) {
3308 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3310 std::swap(V1Elts, V2Elts);
3311 std::swap(V1FromV1, V2FromV2);
3314 if ((V1FromV1 + V1InOrder) != 8) {
3315 // Some elements are from V2.
3317 // If there are elements that are from V1 but out of place,
3318 // then first sort them in place
3319 SmallVector<SDOperand, 8> MaskVec;
3320 for (unsigned i = 0; i < 8; ++i) {
3321 SDOperand Elt = V1Elts[i];
3322 if (Elt.getOpcode() == ISD::UNDEF) {
3323 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3326 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3328 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3330 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3332 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3333 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3337 for (unsigned i = 0; i < 8; ++i) {
3338 SDOperand Elt = V1Elts[i];
3339 if (Elt.getOpcode() == ISD::UNDEF)
3341 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3344 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3345 DAG.getConstant(EltIdx - 8, PtrVT));
3346 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3347 DAG.getConstant(i, PtrVT));
3351 // All elements are from V1.
3353 for (unsigned i = 0; i < 8; ++i) {
3354 SDOperand Elt = V1Elts[i];
3355 if (Elt.getOpcode() == ISD::UNDEF)
3357 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3358 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3359 DAG.getConstant(EltIdx, PtrVT));
3360 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3361 DAG.getConstant(i, PtrVT));
3367 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3368 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3369 /// done when every pair / quad of shuffle mask elements point to elements in
3370 /// the right sequence. e.g.
3371 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3373 SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
3375 SDOperand PermMask, SelectionDAG &DAG,
3376 TargetLowering &TLI) {
3377 unsigned NumElems = PermMask.getNumOperands();
3378 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3379 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3380 MVT::ValueType NewVT = MaskVT;
3382 case MVT::v4f32: NewVT = MVT::v2f64; break;
3383 case MVT::v4i32: NewVT = MVT::v2i64; break;
3384 case MVT::v8i16: NewVT = MVT::v4i32; break;
3385 case MVT::v16i8: NewVT = MVT::v4i32; break;
3386 default: assert(false && "Unexpected!");
3389 if (NewWidth == 2) {
3390 if (MVT::isInteger(VT))
3395 unsigned Scale = NumElems / NewWidth;
3396 SmallVector<SDOperand, 8> MaskVec;
3397 for (unsigned i = 0; i < NumElems; i += Scale) {
3398 unsigned StartIdx = ~0U;
3399 for (unsigned j = 0; j < Scale; ++j) {
3400 SDOperand Elt = PermMask.getOperand(i+j);
3401 if (Elt.getOpcode() == ISD::UNDEF)
3403 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3404 if (StartIdx == ~0U)
3405 StartIdx = EltIdx - (EltIdx % Scale);
3406 if (EltIdx != StartIdx + j)
3409 if (StartIdx == ~0U)
3410 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3412 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
3415 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3416 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3417 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3418 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3419 &MaskVec[0], MaskVec.size()));
3423 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3424 SDOperand V1 = Op.getOperand(0);
3425 SDOperand V2 = Op.getOperand(1);
3426 SDOperand PermMask = Op.getOperand(2);
3427 MVT::ValueType VT = Op.getValueType();
3428 unsigned NumElems = PermMask.getNumOperands();
3429 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3430 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3431 bool V1IsSplat = false;
3432 bool V2IsSplat = false;
3434 if (isUndefShuffle(Op.Val))
3435 return DAG.getNode(ISD::UNDEF, VT);
3437 if (isZeroShuffle(Op.Val))
3438 return getZeroVector(VT, DAG);
3440 if (isIdentityMask(PermMask.Val))
3442 else if (isIdentityMask(PermMask.Val, true))
3445 if (isSplatMask(PermMask.Val)) {
3446 if (NumElems <= 4) return Op;
3447 // Promote it to a v4i32 splat.
3448 return PromoteSplat(Op, DAG);
3451 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3453 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3454 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3456 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3457 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3458 // FIXME: Figure out a cleaner way to do this.
3459 // Try to make use of movq to zero out the top part.
3460 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3461 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3463 SDOperand NewV1 = NewOp.getOperand(0);
3464 SDOperand NewV2 = NewOp.getOperand(1);
3465 SDOperand NewMask = NewOp.getOperand(2);
3466 if (isCommutedMOVL(NewMask.Val, true, false)) {
3467 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3468 NewOp = DAG.getNode(ISD::VECTOR_SHUFFLE, NewOp.getValueType(),
3469 NewV1, NewV2, getMOVLMask(2, DAG));
3470 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3473 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3474 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3475 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3476 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3480 if (X86::isMOVLMask(PermMask.Val))
3481 return (V1IsUndef) ? V2 : Op;
3483 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3484 X86::isMOVSLDUPMask(PermMask.Val) ||
3485 X86::isMOVHLPSMask(PermMask.Val) ||
3486 X86::isMOVHPMask(PermMask.Val) ||
3487 X86::isMOVLPMask(PermMask.Val))
3490 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3491 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3492 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3494 bool Commuted = false;
3495 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3496 // 1,1,1,1 -> v8i16 though.
3497 V1IsSplat = isSplatVector(V1.Val);
3498 V2IsSplat = isSplatVector(V2.Val);
3500 // Canonicalize the splat or undef, if present, to be on the RHS.
3501 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3502 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3503 std::swap(V1IsSplat, V2IsSplat);
3504 std::swap(V1IsUndef, V2IsUndef);
3508 // FIXME: Figure out a cleaner way to do this.
3509 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3510 if (V2IsUndef) return V1;
3511 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3513 // V2 is a splat, so the mask may be malformed. That is, it may point
3514 // to any V2 element. The instruction selectior won't like this. Get
3515 // a corrected mask and commute to form a proper MOVS{S|D}.
3516 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3517 if (NewMask.Val != PermMask.Val)
3518 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3523 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3524 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3525 X86::isUNPCKLMask(PermMask.Val) ||
3526 X86::isUNPCKHMask(PermMask.Val))
3530 // Normalize mask so all entries that point to V2 points to its first
3531 // element then try to match unpck{h|l} again. If match, return a
3532 // new vector_shuffle with the corrected mask.
3533 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3534 if (NewMask.Val != PermMask.Val) {
3535 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3536 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3537 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3538 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3539 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3540 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3545 // Normalize the node to match x86 shuffle ops if needed
3546 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3547 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3550 // Commute is back and try unpck* again.
3551 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3552 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3553 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3554 X86::isUNPCKLMask(PermMask.Val) ||
3555 X86::isUNPCKHMask(PermMask.Val))
3559 // If VT is integer, try PSHUF* first, then SHUFP*.
3560 if (MVT::isInteger(VT)) {
3561 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically
3562 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3563 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) &&
3564 X86::isPSHUFDMask(PermMask.Val)) ||
3565 X86::isPSHUFHWMask(PermMask.Val) ||
3566 X86::isPSHUFLWMask(PermMask.Val)) {
3567 if (V2.getOpcode() != ISD::UNDEF)
3568 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3569 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3573 if (X86::isSHUFPMask(PermMask.Val) &&
3574 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
3577 // Floating point cases in the other order.
3578 if (X86::isSHUFPMask(PermMask.Val))
3580 if (X86::isPSHUFDMask(PermMask.Val) ||
3581 X86::isPSHUFHWMask(PermMask.Val) ||
3582 X86::isPSHUFLWMask(PermMask.Val)) {
3583 if (V2.getOpcode() != ISD::UNDEF)
3584 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3585 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3590 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
3591 if (VT == MVT::v8i16) {
3592 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
3597 // Handle all 4 wide cases with a number of shuffles.
3598 if (NumElems == 4 && MVT::getSizeInBits(VT) != 64) {
3599 // Don't do this for MMX.
3600 MVT::ValueType MaskVT = PermMask.getValueType();
3601 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3602 SmallVector<std::pair<int, int>, 8> Locs;
3603 Locs.reserve(NumElems);
3604 SmallVector<SDOperand, 8> Mask1(NumElems,
3605 DAG.getNode(ISD::UNDEF, MaskEVT));
3606 SmallVector<SDOperand, 8> Mask2(NumElems,
3607 DAG.getNode(ISD::UNDEF, MaskEVT));
3610 // If no more than two elements come from either vector. This can be
3611 // implemented with two shuffles. First shuffle gather the elements.
3612 // The second shuffle, which takes the first shuffle as both of its
3613 // vector operands, put the elements into the right order.
3614 for (unsigned i = 0; i != NumElems; ++i) {
3615 SDOperand Elt = PermMask.getOperand(i);
3616 if (Elt.getOpcode() == ISD::UNDEF) {
3617 Locs[i] = std::make_pair(-1, -1);
3619 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3620 if (Val < NumElems) {
3621 Locs[i] = std::make_pair(0, NumLo);
3625 Locs[i] = std::make_pair(1, NumHi);
3626 if (2+NumHi < NumElems)
3627 Mask1[2+NumHi] = Elt;
3632 if (NumLo <= 2 && NumHi <= 2) {
3633 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3634 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3635 &Mask1[0], Mask1.size()));
3636 for (unsigned i = 0; i != NumElems; ++i) {
3637 if (Locs[i].first == -1)
3640 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3641 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3642 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3646 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3647 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3648 &Mask2[0], Mask2.size()));
3651 // Break it into (shuffle shuffle_hi, shuffle_lo).
3653 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3654 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3655 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3656 unsigned MaskIdx = 0;
3658 unsigned HiIdx = NumElems/2;
3659 for (unsigned i = 0; i != NumElems; ++i) {
3660 if (i == NumElems/2) {
3666 SDOperand Elt = PermMask.getOperand(i);
3667 if (Elt.getOpcode() == ISD::UNDEF) {
3668 Locs[i] = std::make_pair(-1, -1);
3669 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3670 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3671 (*MaskPtr)[LoIdx] = Elt;
3674 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3675 (*MaskPtr)[HiIdx] = Elt;
3680 SDOperand LoShuffle =
3681 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3682 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3683 &LoMask[0], LoMask.size()));
3684 SDOperand HiShuffle =
3685 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3686 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3687 &HiMask[0], HiMask.size()));
3688 SmallVector<SDOperand, 8> MaskOps;
3689 for (unsigned i = 0; i != NumElems; ++i) {
3690 if (Locs[i].first == -1) {
3691 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3693 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3694 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3697 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3698 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3699 &MaskOps[0], MaskOps.size()));
3706 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op,
3707 SelectionDAG &DAG) {
3708 MVT::ValueType VT = Op.getValueType();
3709 if (MVT::getSizeInBits(VT) == 8) {
3710 SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
3711 Op.getOperand(0), Op.getOperand(1));
3712 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3713 DAG.getValueType(VT));
3714 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3715 } else if (MVT::getSizeInBits(VT) == 16) {
3716 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
3717 Op.getOperand(0), Op.getOperand(1));
3718 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3719 DAG.getValueType(VT));
3720 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3727 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3728 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3731 if (Subtarget->hasSSE41())
3732 return LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
3734 MVT::ValueType VT = Op.getValueType();
3735 // TODO: handle v16i8.
3736 if (MVT::getSizeInBits(VT) == 16) {
3737 SDOperand Vec = Op.getOperand(0);
3738 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3740 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
3741 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3742 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
3744 // Transform it so it match pextrw which produces a 32-bit result.
3745 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3746 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3747 Op.getOperand(0), Op.getOperand(1));
3748 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3749 DAG.getValueType(VT));
3750 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3751 } else if (MVT::getSizeInBits(VT) == 32) {
3752 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3755 // SHUFPS the element to the lowest double word, then movss.
3756 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3757 SmallVector<SDOperand, 8> IdxVec;
3759 push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3761 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3763 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3765 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3766 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3767 &IdxVec[0], IdxVec.size());
3768 SDOperand Vec = Op.getOperand(0);
3769 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3770 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3771 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3772 DAG.getIntPtrConstant(0));
3773 } else if (MVT::getSizeInBits(VT) == 64) {
3774 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
3775 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
3776 // to match extract_elt for f64.
3777 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3781 // UNPCKHPD the element to the lowest double word, then movsd.
3782 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3783 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3784 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3785 SmallVector<SDOperand, 8> IdxVec;
3786 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
3788 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3789 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3790 &IdxVec[0], IdxVec.size());
3791 SDOperand Vec = Op.getOperand(0);
3792 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3793 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3794 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3795 DAG.getIntPtrConstant(0));
3802 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){
3803 MVT::ValueType VT = Op.getValueType();
3804 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3806 SDOperand N0 = Op.getOperand(0);
3807 SDOperand N1 = Op.getOperand(1);
3808 SDOperand N2 = Op.getOperand(2);
3810 if ((MVT::getSizeInBits(EVT) == 8) || (MVT::getSizeInBits(EVT) == 16)) {
3811 unsigned Opc = (MVT::getSizeInBits(EVT) == 8) ? X86ISD::PINSRB
3813 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
3815 if (N1.getValueType() != MVT::i32)
3816 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3817 if (N2.getValueType() != MVT::i32)
3818 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
3819 return DAG.getNode(Opc, VT, N0, N1, N2);
3820 } else if (EVT == MVT::f32) {
3821 // Bits [7:6] of the constant are the source select. This will always be
3822 // zero here. The DAG Combiner may combine an extract_elt index into these
3823 // bits. For example (insert (extract, 3), 2) could be matched by putting
3824 // the '3' into bits [7:6] of X86ISD::INSERTPS.
3825 // Bits [5:4] of the constant are the destination select. This is the
3826 // value of the incoming immediate.
3827 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
3828 // combine either bitwise AND or insert of float 0.0 to set these bits.
3829 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4);
3830 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
3836 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3837 MVT::ValueType VT = Op.getValueType();
3838 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3840 if (Subtarget->hasSSE41())
3841 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
3846 SDOperand N0 = Op.getOperand(0);
3847 SDOperand N1 = Op.getOperand(1);
3848 SDOperand N2 = Op.getOperand(2);
3850 if (MVT::getSizeInBits(EVT) == 16) {
3851 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3852 // as its second argument.
3853 if (N1.getValueType() != MVT::i32)
3854 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3855 if (N2.getValueType() != MVT::i32)
3856 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
3857 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3863 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3864 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3865 MVT::ValueType VT = MVT::v2i32;
3866 switch (Op.getValueType()) {
3873 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
3874 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
3877 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3878 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3879 // one of the above mentioned nodes. It has to be wrapped because otherwise
3880 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3881 // be used to form addressing mode. These wrapped nodes will be selected
3884 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3885 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3886 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3888 CP->getAlignment());
3889 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3890 // With PIC, the address is actually $g + Offset.
3891 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3892 !Subtarget->isPICStyleRIPRel()) {
3893 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3894 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3902 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3903 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3904 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3905 // If it's a debug information descriptor, don't mess with it.
3906 if (DAG.isVerifiedDebugInfoDesc(Op))
3908 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3909 // With PIC, the address is actually $g + Offset.
3910 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3911 !Subtarget->isPICStyleRIPRel()) {
3912 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3913 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3917 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3918 // load the value at address GV, not the value of GV itself. This means that
3919 // the GlobalAddress must be in the base or index register of the address, not
3920 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3921 // The same applies for external symbols during PIC codegen
3922 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3923 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
3924 PseudoSourceValue::getGOT(), 0);
3929 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
3931 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3932 const MVT::ValueType PtrVT) {
3934 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3935 DAG.getNode(X86ISD::GlobalBaseReg,
3937 InFlag = Chain.getValue(1);
3939 // emit leal symbol@TLSGD(,%ebx,1), %eax
3940 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3941 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3942 GA->getValueType(0),
3944 SDOperand Ops[] = { Chain, TGA, InFlag };
3945 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3946 InFlag = Result.getValue(2);
3947 Chain = Result.getValue(1);
3949 // call ___tls_get_addr. This function receives its argument in
3950 // the register EAX.
3951 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3952 InFlag = Chain.getValue(1);
3954 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3955 SDOperand Ops1[] = { Chain,
3956 DAG.getTargetExternalSymbol("___tls_get_addr",
3958 DAG.getRegister(X86::EAX, PtrVT),
3959 DAG.getRegister(X86::EBX, PtrVT),
3961 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3962 InFlag = Chain.getValue(1);
3964 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3967 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3968 // "local exec" model.
3970 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3971 const MVT::ValueType PtrVT) {
3972 // Get the Thread Pointer
3973 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3974 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3976 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3977 GA->getValueType(0),
3979 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
3981 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3982 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
3983 PseudoSourceValue::getGOT(), 0);
3985 // The address of the thread local variable is the add of the thread
3986 // pointer with the offset of the variable.
3987 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3991 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3992 // TODO: implement the "local dynamic" model
3993 // TODO: implement the "initial exec"model for pic executables
3994 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3995 "TLS not implemented for non-ELF and 64-bit targets");
3996 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3997 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3998 // otherwise use the "Local Exec"TLS Model
3999 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4000 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
4002 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4006 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
4007 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4008 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4009 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4010 // With PIC, the address is actually $g + Offset.
4011 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4012 !Subtarget->isPICStyleRIPRel()) {
4013 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4014 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4021 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
4022 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4023 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4024 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4025 // With PIC, the address is actually $g + Offset.
4026 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4027 !Subtarget->isPICStyleRIPRel()) {
4028 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4029 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4036 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4037 /// take a 2 x i32 value to shift plus a shift amount.
4038 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
4039 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4040 MVT::ValueType VT = Op.getValueType();
4041 unsigned VTBits = MVT::getSizeInBits(VT);
4042 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4043 SDOperand ShOpLo = Op.getOperand(0);
4044 SDOperand ShOpHi = Op.getOperand(1);
4045 SDOperand ShAmt = Op.getOperand(2);
4046 SDOperand Tmp1 = isSRA ?
4047 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4048 DAG.getConstant(0, VT);
4050 SDOperand Tmp2, Tmp3;
4051 if (Op.getOpcode() == ISD::SHL_PARTS) {
4052 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4053 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4055 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4056 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4059 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4060 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4061 DAG.getConstant(VTBits, MVT::i8));
4062 SDOperand Cond = DAG.getNode(X86ISD::CMP, VT,
4063 AndNode, DAG.getConstant(0, MVT::i8));
4066 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4067 VTs = DAG.getNodeValueTypes(VT, MVT::Flag);
4068 SmallVector<SDOperand, 4> Ops;
4069 if (Op.getOpcode() == ISD::SHL_PARTS) {
4070 Ops.push_back(Tmp2);
4071 Ops.push_back(Tmp3);
4073 Ops.push_back(Cond);
4074 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4077 Ops.push_back(Tmp3);
4078 Ops.push_back(Tmp1);
4080 Ops.push_back(Cond);
4081 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4083 Ops.push_back(Tmp2);
4084 Ops.push_back(Tmp3);
4086 Ops.push_back(Cond);
4087 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4090 Ops.push_back(Tmp3);
4091 Ops.push_back(Tmp1);
4093 Ops.push_back(Cond);
4094 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4097 VTs = DAG.getNodeValueTypes(VT, VT);
4101 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
4104 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
4105 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
4106 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
4107 "Unknown SINT_TO_FP to lower!");
4109 // These are really Legal; caller falls through into that case.
4110 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4112 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4113 Subtarget->is64Bit())
4116 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
4117 MachineFunction &MF = DAG.getMachineFunction();
4118 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4119 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4120 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4122 PseudoSourceValue::getFixedStack(),
4127 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4129 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4131 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4132 SmallVector<SDOperand, 8> Ops;
4133 Ops.push_back(Chain);
4134 Ops.push_back(StackSlot);
4135 Ops.push_back(DAG.getValueType(SrcVT));
4136 SDOperand Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4137 Tys, &Ops[0], Ops.size());
4140 Chain = Result.getValue(1);
4141 SDOperand InFlag = Result.getValue(2);
4143 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4144 // shouldn't be necessary except that RFP cannot be live across
4145 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4146 MachineFunction &MF = DAG.getMachineFunction();
4147 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4148 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4149 Tys = DAG.getVTList(MVT::Other);
4150 SmallVector<SDOperand, 8> Ops;
4151 Ops.push_back(Chain);
4152 Ops.push_back(Result);
4153 Ops.push_back(StackSlot);
4154 Ops.push_back(DAG.getValueType(Op.getValueType()));
4155 Ops.push_back(InFlag);
4156 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4157 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4158 PseudoSourceValue::getFixedStack(), SSFI);
4164 std::pair<SDOperand,SDOperand> X86TargetLowering::
4165 FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
4166 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
4167 "Unknown FP_TO_SINT to lower!");
4169 // These are really Legal.
4170 if (Op.getValueType() == MVT::i32 &&
4171 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4172 return std::make_pair(SDOperand(), SDOperand());
4173 if (Subtarget->is64Bit() &&
4174 Op.getValueType() == MVT::i64 &&
4175 Op.getOperand(0).getValueType() != MVT::f80)
4176 return std::make_pair(SDOperand(), SDOperand());
4178 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4180 MachineFunction &MF = DAG.getMachineFunction();
4181 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
4182 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4183 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4185 switch (Op.getValueType()) {
4186 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4187 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4188 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4189 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4192 SDOperand Chain = DAG.getEntryNode();
4193 SDOperand Value = Op.getOperand(0);
4194 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4195 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4196 Chain = DAG.getStore(Chain, Value, StackSlot,
4197 PseudoSourceValue::getFixedStack(), SSFI);
4198 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4200 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4202 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4203 Chain = Value.getValue(1);
4204 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4205 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4208 // Build the FP_TO_INT*_IN_MEM
4209 SDOperand Ops[] = { Chain, Value, StackSlot };
4210 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4212 return std::make_pair(FIST, StackSlot);
4215 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
4216 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
4217 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4218 if (FIST.Val == 0) return SDOperand();
4221 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4224 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4225 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
4226 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4227 if (FIST.Val == 0) return 0;
4229 // Return an i64 load from the stack slot.
4230 SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0);
4232 // Use a MERGE_VALUES node to drop the chain result value.
4233 return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val;
4236 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
4237 MVT::ValueType VT = Op.getValueType();
4238 MVT::ValueType EltVT = VT;
4239 if (MVT::isVector(VT))
4240 EltVT = MVT::getVectorElementType(VT);
4241 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
4242 std::vector<Constant*> CV;
4243 if (EltVT == MVT::f64) {
4244 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, ~(1ULL << 63))));
4248 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, ~(1U << 31))));
4254 Constant *C = ConstantVector::get(CV);
4255 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4256 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4257 PseudoSourceValue::getConstantPool(), 0,
4259 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4262 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
4263 MVT::ValueType VT = Op.getValueType();
4264 MVT::ValueType EltVT = VT;
4265 unsigned EltNum = 1;
4266 if (MVT::isVector(VT)) {
4267 EltVT = MVT::getVectorElementType(VT);
4268 EltNum = MVT::getVectorNumElements(VT);
4270 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
4271 std::vector<Constant*> CV;
4272 if (EltVT == MVT::f64) {
4273 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, 1ULL << 63)));
4277 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, 1U << 31)));
4283 Constant *C = ConstantVector::get(CV);
4284 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4285 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4286 PseudoSourceValue::getConstantPool(), 0,
4288 if (MVT::isVector(VT)) {
4289 return DAG.getNode(ISD::BIT_CONVERT, VT,
4290 DAG.getNode(ISD::XOR, MVT::v2i64,
4291 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4292 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4294 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4298 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
4299 SDOperand Op0 = Op.getOperand(0);
4300 SDOperand Op1 = Op.getOperand(1);
4301 MVT::ValueType VT = Op.getValueType();
4302 MVT::ValueType SrcVT = Op1.getValueType();
4303 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
4305 // If second operand is smaller, extend it first.
4306 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
4307 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4309 SrcTy = MVT::getTypeForValueType(SrcVT);
4311 // And if it is bigger, shrink it first.
4312 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4313 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4315 SrcTy = MVT::getTypeForValueType(SrcVT);
4318 // At this point the operands and the result should have the same
4319 // type, and that won't be f80 since that is not custom lowered.
4321 // First get the sign bit of second operand.
4322 std::vector<Constant*> CV;
4323 if (SrcVT == MVT::f64) {
4324 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 1ULL << 63))));
4325 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
4327 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 1U << 31))));
4328 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4329 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4330 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4332 Constant *C = ConstantVector::get(CV);
4333 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4334 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4335 PseudoSourceValue::getConstantPool(), 0,
4337 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4339 // Shift sign bit right or left if the two operands have different types.
4340 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4341 // Op0 is MVT::f32, Op1 is MVT::f64.
4342 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4343 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4344 DAG.getConstant(32, MVT::i32));
4345 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4346 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4347 DAG.getIntPtrConstant(0));
4350 // Clear first operand sign bit.
4352 if (VT == MVT::f64) {
4353 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, ~(1ULL << 63)))));
4354 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
4356 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, ~(1U << 31)))));
4357 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4358 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4359 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4361 C = ConstantVector::get(CV);
4362 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4363 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4364 PseudoSourceValue::getConstantPool(), 0,
4366 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4368 // Or the value with the sign bit.
4369 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4372 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
4373 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4375 SDOperand Op0 = Op.getOperand(0);
4376 SDOperand Op1 = Op.getOperand(1);
4377 SDOperand CC = Op.getOperand(2);
4378 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4379 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
4382 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4384 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4385 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4386 DAG.getConstant(X86CC, MVT::i8), Cond);
4389 assert(isFP && "Illegal integer SetCC!");
4391 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4392 switch (SetCCOpcode) {
4393 default: assert(false && "Illegal floating point SetCC!");
4394 case ISD::SETOEQ: { // !PF & ZF
4395 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4396 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4397 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4398 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4399 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4401 case ISD::SETUNE: { // PF | !ZF
4402 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4403 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4404 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4405 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4406 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4412 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
4413 bool addTest = true;
4414 SDOperand Cond = Op.getOperand(0);
4417 if (Cond.getOpcode() == ISD::SETCC)
4418 Cond = LowerSETCC(Cond, DAG);
4420 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4421 // setting operand in place of the X86ISD::SETCC.
4422 if (Cond.getOpcode() == X86ISD::SETCC) {
4423 CC = Cond.getOperand(0);
4425 SDOperand Cmp = Cond.getOperand(1);
4426 unsigned Opc = Cmp.getOpcode();
4427 MVT::ValueType VT = Op.getValueType();
4429 bool IllegalFPCMov = false;
4430 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) &&
4431 !isScalarFPTypeInSSEReg(VT)) // FPStack?
4432 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4434 if ((Opc == X86ISD::CMP ||
4435 Opc == X86ISD::COMI ||
4436 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4443 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4444 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4447 const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4449 SmallVector<SDOperand, 4> Ops;
4450 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4451 // condition is true.
4452 Ops.push_back(Op.getOperand(2));
4453 Ops.push_back(Op.getOperand(1));
4455 Ops.push_back(Cond);
4456 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4459 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
4460 bool addTest = true;
4461 SDOperand Chain = Op.getOperand(0);
4462 SDOperand Cond = Op.getOperand(1);
4463 SDOperand Dest = Op.getOperand(2);
4466 if (Cond.getOpcode() == ISD::SETCC)
4467 Cond = LowerSETCC(Cond, DAG);
4469 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4470 // setting operand in place of the X86ISD::SETCC.
4471 if (Cond.getOpcode() == X86ISD::SETCC) {
4472 CC = Cond.getOperand(0);
4474 SDOperand Cmp = Cond.getOperand(1);
4475 unsigned Opc = Cmp.getOpcode();
4476 if (Opc == X86ISD::CMP ||
4477 Opc == X86ISD::COMI ||
4478 Opc == X86ISD::UCOMI) {
4485 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4486 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4488 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
4489 Chain, Op.getOperand(2), CC, Cond);
4493 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4494 // Calls to _alloca is needed to probe the stack when allocating more than 4k
4495 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
4496 // that the guard pages used by the OS virtual memory manager are allocated in
4497 // correct sequence.
4499 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
4500 SelectionDAG &DAG) {
4501 assert(Subtarget->isTargetCygMing() &&
4502 "This should be used only on Cygwin/Mingw targets");
4505 SDOperand Chain = Op.getOperand(0);
4506 SDOperand Size = Op.getOperand(1);
4507 // FIXME: Ensure alignment here
4511 MVT::ValueType IntPtr = getPointerTy();
4512 MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
4514 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4515 Flag = Chain.getValue(1);
4517 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4518 SDOperand Ops[] = { Chain,
4519 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4520 DAG.getRegister(X86::EAX, IntPtr),
4522 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
4523 Flag = Chain.getValue(1);
4525 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
4527 std::vector<MVT::ValueType> Tys;
4528 Tys.push_back(SPTy);
4529 Tys.push_back(MVT::Other);
4530 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
4531 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
4534 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
4535 SDOperand InFlag(0, 0);
4536 SDOperand Chain = Op.getOperand(0);
4538 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4539 if (Align == 0) Align = 1;
4541 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4542 // If not DWORD aligned or size is more than the threshold, call memset.
4543 // The libc version is likely to be faster for these cases. It can use the
4544 // address value and run time information about the CPU.
4545 if ((Align & 3) != 0 ||
4546 (I && I->getValue() > Subtarget->getMaxInlineSizeThreshold())) {
4547 MVT::ValueType IntPtr = getPointerTy();
4548 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4549 TargetLowering::ArgListTy Args;
4550 TargetLowering::ArgListEntry Entry;
4551 Entry.Node = Op.getOperand(1);
4552 Entry.Ty = IntPtrTy;
4553 Args.push_back(Entry);
4554 // Extend the unsigned i8 argument to be an int value for the call.
4555 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
4556 Entry.Ty = IntPtrTy;
4557 Args.push_back(Entry);
4558 Entry.Node = Op.getOperand(3);
4559 Args.push_back(Entry);
4560 std::pair<SDOperand,SDOperand> CallResult =
4561 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
4562 false, DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
4563 return CallResult.second;
4568 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4569 unsigned BytesLeft = 0;
4570 bool TwoRepStos = false;
4573 uint64_t Val = ValC->getValue() & 255;
4575 // If the value is a constant, then we can potentially use larger sets.
4576 switch (Align & 3) {
4577 case 2: // WORD aligned
4580 Val = (Val << 8) | Val;
4582 case 0: // DWORD aligned
4585 Val = (Val << 8) | Val;
4586 Val = (Val << 16) | Val;
4587 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
4590 Val = (Val << 32) | Val;
4593 default: // Byte aligned
4596 Count = Op.getOperand(3);
4600 if (AVT > MVT::i8) {
4602 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4603 Count = DAG.getIntPtrConstant(I->getValue() / UBytes);
4604 BytesLeft = I->getValue() % UBytes;
4606 assert(AVT >= MVT::i32 &&
4607 "Do not use rep;stos if not at least DWORD aligned");
4608 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4609 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4614 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4616 InFlag = Chain.getValue(1);
4619 Count = Op.getOperand(3);
4620 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4621 InFlag = Chain.getValue(1);
4624 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4626 InFlag = Chain.getValue(1);
4627 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4628 Op.getOperand(1), InFlag);
4629 InFlag = Chain.getValue(1);
4631 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4632 SmallVector<SDOperand, 8> Ops;
4633 Ops.push_back(Chain);
4634 Ops.push_back(DAG.getValueType(AVT));
4635 Ops.push_back(InFlag);
4636 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4639 InFlag = Chain.getValue(1);
4640 Count = Op.getOperand(3);
4641 MVT::ValueType CVT = Count.getValueType();
4642 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4643 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4644 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4646 InFlag = Chain.getValue(1);
4647 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4649 Ops.push_back(Chain);
4650 Ops.push_back(DAG.getValueType(MVT::i8));
4651 Ops.push_back(InFlag);
4652 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4653 } else if (BytesLeft) {
4654 // Issue stores for the last 1 - 7 bytes.
4656 unsigned Val = ValC->getValue() & 255;
4657 unsigned Offset = I->getValue() - BytesLeft;
4658 SDOperand DstAddr = Op.getOperand(1);
4659 MVT::ValueType AddrVT = DstAddr.getValueType();
4660 if (BytesLeft >= 4) {
4661 Val = (Val << 8) | Val;
4662 Val = (Val << 16) | Val;
4663 Value = DAG.getConstant(Val, MVT::i32);
4664 Chain = DAG.getStore(Chain, Value,
4665 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4666 DAG.getConstant(Offset, AddrVT)),
4671 if (BytesLeft >= 2) {
4672 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
4673 Chain = DAG.getStore(Chain, Value,
4674 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4675 DAG.getConstant(Offset, AddrVT)),
4680 if (BytesLeft == 1) {
4681 Value = DAG.getConstant(Val, MVT::i8);
4682 Chain = DAG.getStore(Chain, Value,
4683 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4684 DAG.getConstant(Offset, AddrVT)),
4692 SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain,
4697 SelectionDAG &DAG) {
4699 unsigned BytesLeft = 0;
4700 switch (Align & 3) {
4701 case 2: // WORD aligned
4704 case 0: // DWORD aligned
4706 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4709 default: // Byte aligned
4714 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4715 SDOperand Count = DAG.getIntPtrConstant(Size / UBytes);
4716 BytesLeft = Size % UBytes;
4718 SDOperand InFlag(0, 0);
4719 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4721 InFlag = Chain.getValue(1);
4722 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4724 InFlag = Chain.getValue(1);
4725 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4727 InFlag = Chain.getValue(1);
4729 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4730 SmallVector<SDOperand, 8> Ops;
4731 Ops.push_back(Chain);
4732 Ops.push_back(DAG.getValueType(AVT));
4733 Ops.push_back(InFlag);
4734 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4737 // Issue loads and stores for the last 1 - 7 bytes.
4738 unsigned Offset = Size - BytesLeft;
4739 SDOperand DstAddr = Dest;
4740 MVT::ValueType DstVT = DstAddr.getValueType();
4741 SDOperand SrcAddr = Source;
4742 MVT::ValueType SrcVT = SrcAddr.getValueType();
4744 if (BytesLeft >= 4) {
4745 Value = DAG.getLoad(MVT::i32, Chain,
4746 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4747 DAG.getConstant(Offset, SrcVT)),
4749 Chain = Value.getValue(1);
4750 Chain = DAG.getStore(Chain, Value,
4751 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4752 DAG.getConstant(Offset, DstVT)),
4757 if (BytesLeft >= 2) {
4758 Value = DAG.getLoad(MVT::i16, Chain,
4759 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4760 DAG.getConstant(Offset, SrcVT)),
4762 Chain = Value.getValue(1);
4763 Chain = DAG.getStore(Chain, Value,
4764 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4765 DAG.getConstant(Offset, DstVT)),
4771 if (BytesLeft == 1) {
4772 Value = DAG.getLoad(MVT::i8, Chain,
4773 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4774 DAG.getConstant(Offset, SrcVT)),
4776 Chain = Value.getValue(1);
4777 Chain = DAG.getStore(Chain, Value,
4778 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4779 DAG.getConstant(Offset, DstVT)),
4787 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
4788 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
4789 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4790 SDOperand TheChain = N->getOperand(0);
4791 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
4792 if (Subtarget->is64Bit()) {
4793 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4794 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
4795 MVT::i64, rax.getValue(2));
4796 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
4797 DAG.getConstant(32, MVT::i8));
4799 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
4802 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4803 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4806 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4807 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
4808 MVT::i32, eax.getValue(2));
4809 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
4810 SDOperand Ops[] = { eax, edx };
4811 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
4813 // Use a MERGE_VALUES to return the value and chain.
4814 Ops[1] = edx.getValue(1);
4815 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4816 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4819 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4820 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4822 if (!Subtarget->is64Bit()) {
4823 // vastart just stores the address of the VarArgsFrameIndex slot into the
4824 // memory location argument.
4825 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4826 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
4830 // gp_offset (0 - 6 * 8)
4831 // fp_offset (48 - 48 + 8 * 16)
4832 // overflow_arg_area (point to parameters coming in memory).
4834 SmallVector<SDOperand, 8> MemOps;
4835 SDOperand FIN = Op.getOperand(1);
4837 SDOperand Store = DAG.getStore(Op.getOperand(0),
4838 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4840 MemOps.push_back(Store);
4843 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
4844 Store = DAG.getStore(Op.getOperand(0),
4845 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4847 MemOps.push_back(Store);
4849 // Store ptr to overflow_arg_area
4850 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
4851 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4852 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
4853 MemOps.push_back(Store);
4855 // Store ptr to reg_save_area.
4856 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
4857 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4858 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
4859 MemOps.push_back(Store);
4860 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4863 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4864 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4865 SDOperand Chain = Op.getOperand(0);
4866 SDOperand DstPtr = Op.getOperand(1);
4867 SDOperand SrcPtr = Op.getOperand(2);
4868 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4869 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
4871 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, SrcSV, 0);
4872 Chain = SrcPtr.getValue(1);
4873 for (unsigned i = 0; i < 3; ++i) {
4874 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, SrcSV, 0);
4875 Chain = Val.getValue(1);
4876 Chain = DAG.getStore(Chain, Val, DstPtr, DstSV, 0);
4879 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4880 DAG.getIntPtrConstant(8));
4881 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4882 DAG.getIntPtrConstant(8));
4888 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4889 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4891 default: return SDOperand(); // Don't custom lower most intrinsics.
4892 // Comparison intrinsics.
4893 case Intrinsic::x86_sse_comieq_ss:
4894 case Intrinsic::x86_sse_comilt_ss:
4895 case Intrinsic::x86_sse_comile_ss:
4896 case Intrinsic::x86_sse_comigt_ss:
4897 case Intrinsic::x86_sse_comige_ss:
4898 case Intrinsic::x86_sse_comineq_ss:
4899 case Intrinsic::x86_sse_ucomieq_ss:
4900 case Intrinsic::x86_sse_ucomilt_ss:
4901 case Intrinsic::x86_sse_ucomile_ss:
4902 case Intrinsic::x86_sse_ucomigt_ss:
4903 case Intrinsic::x86_sse_ucomige_ss:
4904 case Intrinsic::x86_sse_ucomineq_ss:
4905 case Intrinsic::x86_sse2_comieq_sd:
4906 case Intrinsic::x86_sse2_comilt_sd:
4907 case Intrinsic::x86_sse2_comile_sd:
4908 case Intrinsic::x86_sse2_comigt_sd:
4909 case Intrinsic::x86_sse2_comige_sd:
4910 case Intrinsic::x86_sse2_comineq_sd:
4911 case Intrinsic::x86_sse2_ucomieq_sd:
4912 case Intrinsic::x86_sse2_ucomilt_sd:
4913 case Intrinsic::x86_sse2_ucomile_sd:
4914 case Intrinsic::x86_sse2_ucomigt_sd:
4915 case Intrinsic::x86_sse2_ucomige_sd:
4916 case Intrinsic::x86_sse2_ucomineq_sd: {
4918 ISD::CondCode CC = ISD::SETCC_INVALID;
4921 case Intrinsic::x86_sse_comieq_ss:
4922 case Intrinsic::x86_sse2_comieq_sd:
4926 case Intrinsic::x86_sse_comilt_ss:
4927 case Intrinsic::x86_sse2_comilt_sd:
4931 case Intrinsic::x86_sse_comile_ss:
4932 case Intrinsic::x86_sse2_comile_sd:
4936 case Intrinsic::x86_sse_comigt_ss:
4937 case Intrinsic::x86_sse2_comigt_sd:
4941 case Intrinsic::x86_sse_comige_ss:
4942 case Intrinsic::x86_sse2_comige_sd:
4946 case Intrinsic::x86_sse_comineq_ss:
4947 case Intrinsic::x86_sse2_comineq_sd:
4951 case Intrinsic::x86_sse_ucomieq_ss:
4952 case Intrinsic::x86_sse2_ucomieq_sd:
4953 Opc = X86ISD::UCOMI;
4956 case Intrinsic::x86_sse_ucomilt_ss:
4957 case Intrinsic::x86_sse2_ucomilt_sd:
4958 Opc = X86ISD::UCOMI;
4961 case Intrinsic::x86_sse_ucomile_ss:
4962 case Intrinsic::x86_sse2_ucomile_sd:
4963 Opc = X86ISD::UCOMI;
4966 case Intrinsic::x86_sse_ucomigt_ss:
4967 case Intrinsic::x86_sse2_ucomigt_sd:
4968 Opc = X86ISD::UCOMI;
4971 case Intrinsic::x86_sse_ucomige_ss:
4972 case Intrinsic::x86_sse2_ucomige_sd:
4973 Opc = X86ISD::UCOMI;
4976 case Intrinsic::x86_sse_ucomineq_ss:
4977 case Intrinsic::x86_sse2_ucomineq_sd:
4978 Opc = X86ISD::UCOMI;
4984 SDOperand LHS = Op.getOperand(1);
4985 SDOperand RHS = Op.getOperand(2);
4986 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4988 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
4989 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
4990 DAG.getConstant(X86CC, MVT::i8), Cond);
4991 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4996 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4997 // Depths > 0 not supported yet!
4998 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5001 // Just load the return address
5002 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5003 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5006 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
5007 // Depths > 0 not supported yet!
5008 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5011 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5012 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
5013 DAG.getIntPtrConstant(4));
5016 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
5017 SelectionDAG &DAG) {
5018 // Is not yet supported on x86-64
5019 if (Subtarget->is64Bit())
5022 return DAG.getIntPtrConstant(8);
5025 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
5027 assert(!Subtarget->is64Bit() &&
5028 "Lowering of eh_return builtin is not supported yet on x86-64");
5030 MachineFunction &MF = DAG.getMachineFunction();
5031 SDOperand Chain = Op.getOperand(0);
5032 SDOperand Offset = Op.getOperand(1);
5033 SDOperand Handler = Op.getOperand(2);
5035 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
5038 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5039 DAG.getIntPtrConstant(-4UL));
5040 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5041 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5042 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
5043 MF.getRegInfo().addLiveOut(X86::ECX);
5045 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
5046 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
5049 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
5050 SelectionDAG &DAG) {
5051 SDOperand Root = Op.getOperand(0);
5052 SDOperand Trmp = Op.getOperand(1); // trampoline
5053 SDOperand FPtr = Op.getOperand(2); // nested function
5054 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
5056 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5058 const X86InstrInfo *TII =
5059 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5061 if (Subtarget->is64Bit()) {
5062 SDOperand OutChains[6];
5064 // Large code-model.
5066 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5067 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5069 const unsigned char N86R10 =
5070 ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10);
5071 const unsigned char N86R11 =
5072 ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11);
5074 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5076 // Load the pointer to the nested function into R11.
5077 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5078 SDOperand Addr = Trmp;
5079 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5082 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5083 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5085 // Load the 'nest' parameter value into R10.
5086 // R10 is specified in X86CallingConv.td
5087 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5088 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5089 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5092 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5093 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5095 // Jump to the nested function.
5096 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5097 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5098 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5101 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5102 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5103 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5107 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5108 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
5110 const Function *Func =
5111 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5112 unsigned CC = Func->getCallingConv();
5117 assert(0 && "Unsupported calling convention");
5118 case CallingConv::C:
5119 case CallingConv::X86_StdCall: {
5120 // Pass 'nest' parameter in ECX.
5121 // Must be kept in sync with X86CallingConv.td
5124 // Check that ECX wasn't needed by an 'inreg' parameter.
5125 const FunctionType *FTy = Func->getFunctionType();
5126 const PAListPtr &Attrs = Func->getParamAttrs();
5128 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5129 unsigned InRegCount = 0;
5132 for (FunctionType::param_iterator I = FTy->param_begin(),
5133 E = FTy->param_end(); I != E; ++I, ++Idx)
5134 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg))
5135 // FIXME: should only count parameters that are lowered to integers.
5136 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
5138 if (InRegCount > 2) {
5139 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5145 case CallingConv::X86_FastCall:
5146 // Pass 'nest' parameter in EAX.
5147 // Must be kept in sync with X86CallingConv.td
5152 SDOperand OutChains[4];
5153 SDOperand Addr, Disp;
5155 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5156 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5158 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5159 const unsigned char N86Reg =
5160 ((const X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
5161 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
5164 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
5165 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
5167 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
5168 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5169 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
5170 TrmpAddr, 5, false, 1);
5172 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
5173 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
5176 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
5177 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
5181 SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
5183 The rounding mode is in bits 11:10 of FPSR, and has the following
5190 FLT_ROUNDS, on the other hand, expects the following:
5197 To perform the conversion, we do:
5198 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5201 MachineFunction &MF = DAG.getMachineFunction();
5202 const TargetMachine &TM = MF.getTarget();
5203 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5204 unsigned StackAlignment = TFI.getStackAlignment();
5205 MVT::ValueType VT = Op.getValueType();
5207 // Save FP Control Word to stack slot
5208 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
5209 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5211 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
5212 DAG.getEntryNode(), StackSlot);
5214 // Load FP Control Word from stack slot
5215 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
5217 // Transform as necessary
5219 DAG.getNode(ISD::SRL, MVT::i16,
5220 DAG.getNode(ISD::AND, MVT::i16,
5221 CWD, DAG.getConstant(0x800, MVT::i16)),
5222 DAG.getConstant(11, MVT::i8));
5224 DAG.getNode(ISD::SRL, MVT::i16,
5225 DAG.getNode(ISD::AND, MVT::i16,
5226 CWD, DAG.getConstant(0x400, MVT::i16)),
5227 DAG.getConstant(9, MVT::i8));
5230 DAG.getNode(ISD::AND, MVT::i16,
5231 DAG.getNode(ISD::ADD, MVT::i16,
5232 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5233 DAG.getConstant(1, MVT::i16)),
5234 DAG.getConstant(3, MVT::i16));
5237 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
5238 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5241 SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
5242 MVT::ValueType VT = Op.getValueType();
5243 MVT::ValueType OpVT = VT;
5244 unsigned NumBits = MVT::getSizeInBits(VT);
5246 Op = Op.getOperand(0);
5247 if (VT == MVT::i8) {
5248 // Zero extend to i32 since there is not an i8 bsr.
5250 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5253 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5254 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5255 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5257 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5258 SmallVector<SDOperand, 4> Ops;
5260 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5261 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5262 Ops.push_back(Op.getValue(1));
5263 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5265 // Finally xor with NumBits-1.
5266 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5269 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5273 SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
5274 MVT::ValueType VT = Op.getValueType();
5275 MVT::ValueType OpVT = VT;
5276 unsigned NumBits = MVT::getSizeInBits(VT);
5278 Op = Op.getOperand(0);
5279 if (VT == MVT::i8) {
5281 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5284 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5285 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5286 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5288 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5289 SmallVector<SDOperand, 4> Ops;
5291 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5292 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5293 Ops.push_back(Op.getValue(1));
5294 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5297 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5301 SDOperand X86TargetLowering::LowerLCS(SDOperand Op, SelectionDAG &DAG) {
5302 MVT::ValueType T = cast<AtomicSDNode>(Op.Val)->getVT();
5306 case MVT::i8: Reg = X86::AL; size = 1; break;
5307 case MVT::i16: Reg = X86::AX; size = 2; break;
5308 case MVT::i32: Reg = X86::EAX; size = 4; break;
5310 if (Subtarget->is64Bit()) {
5311 Reg = X86::RAX; size = 8;
5312 } else //Should go away when LowerType stuff lands
5313 return SDOperand(ExpandATOMIC_LCS(Op.Val, DAG), 0);
5316 SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
5317 Op.getOperand(3), SDOperand());
5318 SDOperand Ops[] = { cpIn.getValue(0),
5321 DAG.getTargetConstant(size, MVT::i8),
5323 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5324 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5326 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
5330 SDNode* X86TargetLowering::ExpandATOMIC_LCS(SDNode* Op, SelectionDAG &DAG) {
5331 MVT::ValueType T = cast<AtomicSDNode>(Op)->getVT();
5332 assert (T == MVT::i64 && "Only know how to expand i64 CAS");
5333 SDOperand cpInL, cpInH;
5334 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5335 DAG.getConstant(0, MVT::i32));
5336 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5337 DAG.getConstant(1, MVT::i32));
5338 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
5339 cpInL, SDOperand());
5340 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
5341 cpInH, cpInL.getValue(1));
5342 SDOperand swapInL, swapInH;
5343 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5344 DAG.getConstant(0, MVT::i32));
5345 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5346 DAG.getConstant(1, MVT::i32));
5347 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
5348 swapInL, cpInH.getValue(1));
5349 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
5350 swapInH, swapInL.getValue(1));
5351 SDOperand Ops[] = { swapInH.getValue(0),
5353 swapInH.getValue(1)};
5354 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5355 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
5356 SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
5357 Result.getValue(1));
5358 SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
5359 cpOutL.getValue(2));
5360 SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
5361 SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
5362 Tys = DAG.getVTList(MVT::i64, MVT::Other);
5363 return DAG.getNode(ISD::MERGE_VALUES, Tys, ResultVal, cpOutH.getValue(1)).Val;
5366 /// LowerOperation - Provide custom lowering hooks for some operations.
5368 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
5369 switch (Op.getOpcode()) {
5370 default: assert(0 && "Should not custom lower this!");
5371 case ISD::ATOMIC_LCS: return LowerLCS(Op,DAG);
5372 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5373 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5374 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5375 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5376 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5377 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5378 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5379 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5380 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5381 case ISD::SHL_PARTS:
5382 case ISD::SRA_PARTS:
5383 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5384 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5385 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5386 case ISD::FABS: return LowerFABS(Op, DAG);
5387 case ISD::FNEG: return LowerFNEG(Op, DAG);
5388 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5389 case ISD::SETCC: return LowerSETCC(Op, DAG);
5390 case ISD::SELECT: return LowerSELECT(Op, DAG);
5391 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5392 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5393 case ISD::CALL: return LowerCALL(Op, DAG);
5394 case ISD::RET: return LowerRET(Op, DAG);
5395 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5396 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
5397 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
5398 case ISD::VASTART: return LowerVASTART(Op, DAG);
5399 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
5400 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5401 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5402 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5403 case ISD::FRAME_TO_ARGS_OFFSET:
5404 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
5405 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
5406 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
5407 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
5408 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5409 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5410 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
5412 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5413 case ISD::READCYCLECOUNTER:
5414 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
5418 /// ExpandOperation - Provide custom lowering hooks for expanding operations.
5419 SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
5420 switch (N->getOpcode()) {
5421 default: assert(0 && "Should not custom lower this!");
5422 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5423 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
5424 case ISD::ATOMIC_LCS: return ExpandATOMIC_LCS(N, DAG);
5428 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5430 default: return NULL;
5431 case X86ISD::BSF: return "X86ISD::BSF";
5432 case X86ISD::BSR: return "X86ISD::BSR";
5433 case X86ISD::SHLD: return "X86ISD::SHLD";
5434 case X86ISD::SHRD: return "X86ISD::SHRD";
5435 case X86ISD::FAND: return "X86ISD::FAND";
5436 case X86ISD::FOR: return "X86ISD::FOR";
5437 case X86ISD::FXOR: return "X86ISD::FXOR";
5438 case X86ISD::FSRL: return "X86ISD::FSRL";
5439 case X86ISD::FILD: return "X86ISD::FILD";
5440 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
5441 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5442 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5443 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
5444 case X86ISD::FLD: return "X86ISD::FLD";
5445 case X86ISD::FST: return "X86ISD::FST";
5446 case X86ISD::CALL: return "X86ISD::CALL";
5447 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5448 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5449 case X86ISD::CMP: return "X86ISD::CMP";
5450 case X86ISD::COMI: return "X86ISD::COMI";
5451 case X86ISD::UCOMI: return "X86ISD::UCOMI";
5452 case X86ISD::SETCC: return "X86ISD::SETCC";
5453 case X86ISD::CMOV: return "X86ISD::CMOV";
5454 case X86ISD::BRCOND: return "X86ISD::BRCOND";
5455 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
5456 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5457 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
5458 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
5459 case X86ISD::Wrapper: return "X86ISD::Wrapper";
5460 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
5461 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
5462 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
5463 case X86ISD::PINSRB: return "X86ISD::PINSRB";
5464 case X86ISD::PINSRW: return "X86ISD::PINSRW";
5465 case X86ISD::FMAX: return "X86ISD::FMAX";
5466 case X86ISD::FMIN: return "X86ISD::FMIN";
5467 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
5468 case X86ISD::FRCP: return "X86ISD::FRCP";
5469 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
5470 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
5471 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
5472 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
5473 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
5474 case X86ISD::LCMPXCHG_DAG: return "x86ISD::LCMPXCHG_DAG";
5475 case X86ISD::LCMPXCHG8_DAG: return "x86ISD::LCMPXCHG8_DAG";
5479 // isLegalAddressingMode - Return true if the addressing mode represented
5480 // by AM is legal for this target, for a load/store of the specified type.
5481 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5482 const Type *Ty) const {
5483 // X86 supports extremely general addressing modes.
5485 // X86 allows a sign-extended 32-bit immediate field as a displacement.
5486 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
5490 // We can only fold this if we don't need an extra load.
5491 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
5494 // X86-64 only supports addr of globals in small code model.
5495 if (Subtarget->is64Bit()) {
5496 if (getTargetMachine().getCodeModel() != CodeModel::Small)
5498 // If lower 4G is not available, then we must use rip-relative addressing.
5499 if (AM.BaseOffs || AM.Scale > 1)
5510 // These scales always work.
5515 // These scales are formed with basereg+scalereg. Only accept if there is
5520 default: // Other stuff never works.
5528 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
5529 if (!Ty1->isInteger() || !Ty2->isInteger())
5531 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5532 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5533 if (NumBits1 <= NumBits2)
5535 return Subtarget->is64Bit() || NumBits1 < 64;
5538 bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1,
5539 MVT::ValueType VT2) const {
5540 if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2))
5542 unsigned NumBits1 = MVT::getSizeInBits(VT1);
5543 unsigned NumBits2 = MVT::getSizeInBits(VT2);
5544 if (NumBits1 <= NumBits2)
5546 return Subtarget->is64Bit() || NumBits1 < 64;
5549 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5550 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5551 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5552 /// are assumed to be legal.
5554 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
5555 // Only do shuffles on 128-bit vector types for now.
5556 if (MVT::getSizeInBits(VT) == 64) return false;
5557 return (Mask.Val->getNumOperands() <= 4 ||
5558 isIdentityMask(Mask.Val) ||
5559 isIdentityMask(Mask.Val, true) ||
5560 isSplatMask(Mask.Val) ||
5561 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5562 X86::isUNPCKLMask(Mask.Val) ||
5563 X86::isUNPCKHMask(Mask.Val) ||
5564 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
5565 X86::isUNPCKH_v_undef_Mask(Mask.Val));
5568 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
5570 SelectionDAG &DAG) const {
5571 unsigned NumElts = BVOps.size();
5572 // Only do shuffles on 128-bit vector types for now.
5573 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
5574 if (NumElts == 2) return true;
5576 return (isMOVLMask(&BVOps[0], 4) ||
5577 isCommutedMOVL(&BVOps[0], 4, true) ||
5578 isSHUFPMask(&BVOps[0], 4) ||
5579 isCommutedSHUFP(&BVOps[0], 4));
5584 //===----------------------------------------------------------------------===//
5585 // X86 Scheduler Hooks
5586 //===----------------------------------------------------------------------===//
5589 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5590 MachineBasicBlock *BB) {
5591 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5592 switch (MI->getOpcode()) {
5593 default: assert(false && "Unexpected instr type to insert");
5594 case X86::CMOV_FR32:
5595 case X86::CMOV_FR64:
5596 case X86::CMOV_V4F32:
5597 case X86::CMOV_V2F64:
5598 case X86::CMOV_V2I64: {
5599 // To "insert" a SELECT_CC instruction, we actually have to insert the
5600 // diamond control-flow pattern. The incoming instruction knows the
5601 // destination vreg to set, the condition code register to branch on, the
5602 // true/false values to select between, and a branch opcode to use.
5603 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5604 ilist<MachineBasicBlock>::iterator It = BB;
5610 // cmpTY ccX, r1, r2
5612 // fallthrough --> copy0MBB
5613 MachineBasicBlock *thisMBB = BB;
5614 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
5615 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
5617 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
5618 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
5619 MachineFunction *F = BB->getParent();
5620 F->getBasicBlockList().insert(It, copy0MBB);
5621 F->getBasicBlockList().insert(It, sinkMBB);
5622 // Update machine-CFG edges by first adding all successors of the current
5623 // block to the new block which will contain the Phi node for the select.
5624 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
5625 e = BB->succ_end(); i != e; ++i)
5626 sinkMBB->addSuccessor(*i);
5627 // Next, remove all successors of the current block, and add the true
5628 // and fallthrough blocks as its successors.
5629 while(!BB->succ_empty())
5630 BB->removeSuccessor(BB->succ_begin());
5631 BB->addSuccessor(copy0MBB);
5632 BB->addSuccessor(sinkMBB);
5635 // %FalseValue = ...
5636 // # fallthrough to sinkMBB
5639 // Update machine-CFG edges
5640 BB->addSuccessor(sinkMBB);
5643 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5646 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
5647 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5648 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5650 delete MI; // The pseudo instruction is gone now.
5654 case X86::FP32_TO_INT16_IN_MEM:
5655 case X86::FP32_TO_INT32_IN_MEM:
5656 case X86::FP32_TO_INT64_IN_MEM:
5657 case X86::FP64_TO_INT16_IN_MEM:
5658 case X86::FP64_TO_INT32_IN_MEM:
5659 case X86::FP64_TO_INT64_IN_MEM:
5660 case X86::FP80_TO_INT16_IN_MEM:
5661 case X86::FP80_TO_INT32_IN_MEM:
5662 case X86::FP80_TO_INT64_IN_MEM: {
5663 // Change the floating point control register to use "round towards zero"
5664 // mode when truncating to an integer value.
5665 MachineFunction *F = BB->getParent();
5666 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
5667 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
5669 // Load the old value of the high byte of the control word...
5671 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
5672 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
5674 // Set the high part to be round to zero...
5675 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
5678 // Reload the modified control word now...
5679 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
5681 // Restore the memory image of control word to original value
5682 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
5685 // Get the X86 opcode to use.
5687 switch (MI->getOpcode()) {
5688 default: assert(0 && "illegal opcode!");
5689 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
5690 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
5691 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
5692 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
5693 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
5694 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
5695 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
5696 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
5697 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
5701 MachineOperand &Op = MI->getOperand(0);
5702 if (Op.isRegister()) {
5703 AM.BaseType = X86AddressMode::RegBase;
5704 AM.Base.Reg = Op.getReg();
5706 AM.BaseType = X86AddressMode::FrameIndexBase;
5707 AM.Base.FrameIndex = Op.getIndex();
5709 Op = MI->getOperand(1);
5710 if (Op.isImmediate())
5711 AM.Scale = Op.getImm();
5712 Op = MI->getOperand(2);
5713 if (Op.isImmediate())
5714 AM.IndexReg = Op.getImm();
5715 Op = MI->getOperand(3);
5716 if (Op.isGlobalAddress()) {
5717 AM.GV = Op.getGlobal();
5719 AM.Disp = Op.getImm();
5721 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
5722 .addReg(MI->getOperand(4).getReg());
5724 // Reload the original control word now.
5725 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
5727 delete MI; // The pseudo instruction is gone now.
5733 //===----------------------------------------------------------------------===//
5734 // X86 Optimization Hooks
5735 //===----------------------------------------------------------------------===//
5737 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
5741 const SelectionDAG &DAG,
5742 unsigned Depth) const {
5743 unsigned Opc = Op.getOpcode();
5744 assert((Opc >= ISD::BUILTIN_OP_END ||
5745 Opc == ISD::INTRINSIC_WO_CHAIN ||
5746 Opc == ISD::INTRINSIC_W_CHAIN ||
5747 Opc == ISD::INTRINSIC_VOID) &&
5748 "Should use MaskedValueIsZero if you don't know whether Op"
5749 " is a target node!");
5751 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
5755 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
5756 Mask.getBitWidth() - 1);
5761 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5762 /// element of the result of the vector shuffle.
5763 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
5764 MVT::ValueType VT = N->getValueType(0);
5765 SDOperand PermMask = N->getOperand(2);
5766 unsigned NumElems = PermMask.getNumOperands();
5767 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
5769 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5771 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5772 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
5773 SDOperand Idx = PermMask.getOperand(i);
5774 if (Idx.getOpcode() == ISD::UNDEF)
5775 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5776 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
5781 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
5782 /// node is a GlobalAddress + an offset.
5783 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
5784 unsigned Opc = N->getOpcode();
5785 if (Opc == X86ISD::Wrapper) {
5786 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
5787 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
5790 } else if (Opc == ISD::ADD) {
5791 SDOperand N1 = N->getOperand(0);
5792 SDOperand N2 = N->getOperand(1);
5793 if (isGAPlusOffset(N1.Val, GA, Offset)) {
5794 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
5796 Offset += V->getSignExtended();
5799 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
5800 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
5802 Offset += V->getSignExtended();
5810 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
5812 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
5813 MachineFrameInfo *MFI) {
5814 if (N->getOperand(0).Val != Base->getOperand(0).Val)
5817 SDOperand Loc = N->getOperand(1);
5818 SDOperand BaseLoc = Base->getOperand(1);
5819 if (Loc.getOpcode() == ISD::FrameIndex) {
5820 if (BaseLoc.getOpcode() != ISD::FrameIndex)
5822 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
5823 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
5824 int FS = MFI->getObjectSize(FI);
5825 int BFS = MFI->getObjectSize(BFI);
5826 if (FS != BFS || FS != Size) return false;
5827 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
5829 GlobalValue *GV1 = NULL;
5830 GlobalValue *GV2 = NULL;
5831 int64_t Offset1 = 0;
5832 int64_t Offset2 = 0;
5833 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
5834 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
5835 if (isGA1 && isGA2 && GV1 == GV2)
5836 return Offset1 == (Offset2 + Dist*Size);
5842 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
5843 const X86Subtarget *Subtarget) {
5846 if (isGAPlusOffset(Base, GV, Offset))
5847 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
5848 // DAG combine handles the stack object case.
5853 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
5854 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
5855 /// if the load addresses are consecutive, non-overlapping, and in the right
5857 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
5858 const X86Subtarget *Subtarget) {
5859 MachineFunction &MF = DAG.getMachineFunction();
5860 MachineFrameInfo *MFI = MF.getFrameInfo();
5861 MVT::ValueType VT = N->getValueType(0);
5862 MVT::ValueType EVT = MVT::getVectorElementType(VT);
5863 SDOperand PermMask = N->getOperand(2);
5864 int NumElems = (int)PermMask.getNumOperands();
5865 SDNode *Base = NULL;
5866 for (int i = 0; i < NumElems; ++i) {
5867 SDOperand Idx = PermMask.getOperand(i);
5868 if (Idx.getOpcode() == ISD::UNDEF) {
5869 if (!Base) return SDOperand();
5872 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
5873 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
5877 else if (!isConsecutiveLoad(Arg.Val, Base,
5878 i, MVT::getSizeInBits(EVT)/8,MFI))
5883 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
5884 LoadSDNode *LD = cast<LoadSDNode>(Base);
5886 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5887 LD->getSrcValueOffset(), LD->isVolatile());
5889 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5890 LD->getSrcValueOffset(), LD->isVolatile(),
5891 LD->getAlignment());
5895 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
5896 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
5897 const X86Subtarget *Subtarget) {
5898 SDOperand Cond = N->getOperand(0);
5900 // If we have SSE[12] support, try to form min/max nodes.
5901 if (Subtarget->hasSSE2() &&
5902 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
5903 if (Cond.getOpcode() == ISD::SETCC) {
5904 // Get the LHS/RHS of the select.
5905 SDOperand LHS = N->getOperand(1);
5906 SDOperand RHS = N->getOperand(2);
5907 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
5909 unsigned Opcode = 0;
5910 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
5913 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
5916 if (!UnsafeFPMath) break;
5918 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
5920 Opcode = X86ISD::FMIN;
5923 case ISD::SETOGT: // (X > Y) ? X : Y -> max
5926 if (!UnsafeFPMath) break;
5928 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
5930 Opcode = X86ISD::FMAX;
5933 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
5936 case ISD::SETOGT: // (X > Y) ? Y : X -> min
5939 if (!UnsafeFPMath) break;
5941 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
5943 Opcode = X86ISD::FMIN;
5946 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
5949 if (!UnsafeFPMath) break;
5951 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
5953 Opcode = X86ISD::FMAX;
5959 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
5967 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
5968 static SDOperand PerformSTORECombine(StoreSDNode *St, SelectionDAG &DAG,
5969 const X86Subtarget *Subtarget) {
5970 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
5971 // the FP state in cases where an emms may be missing.
5972 // A preferable solution to the general problem is to figure out the right
5973 // places to insert EMMS. This qualifies as a quick hack.
5974 if (MVT::isVector(St->getValue().getValueType()) &&
5975 MVT::getSizeInBits(St->getValue().getValueType()) == 64 &&
5976 isa<LoadSDNode>(St->getValue()) &&
5977 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
5978 St->getChain().hasOneUse() && !St->isVolatile()) {
5979 SDNode* LdVal = St->getValue().Val;
5981 int TokenFactorIndex = -1;
5982 SmallVector<SDOperand, 8> Ops;
5983 SDNode* ChainVal = St->getChain().Val;
5984 // Must be a store of a load. We currently handle two cases: the load
5985 // is a direct child, and it's under an intervening TokenFactor. It is
5986 // possible to dig deeper under nested TokenFactors.
5987 if (ChainVal == LdVal)
5988 Ld = cast<LoadSDNode>(St->getChain());
5989 else if (St->getValue().hasOneUse() &&
5990 ChainVal->getOpcode() == ISD::TokenFactor) {
5991 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
5992 if (ChainVal->getOperand(i).Val == LdVal) {
5993 TokenFactorIndex = i;
5994 Ld = cast<LoadSDNode>(St->getValue());
5996 Ops.push_back(ChainVal->getOperand(i));
6000 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
6001 if (Subtarget->is64Bit()) {
6002 SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
6003 Ld->getBasePtr(), Ld->getSrcValue(),
6004 Ld->getSrcValueOffset(), Ld->isVolatile(),
6005 Ld->getAlignment());
6006 SDOperand NewChain = NewLd.getValue(1);
6007 if (TokenFactorIndex != -1) {
6008 Ops.push_back(NewLd);
6009 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6012 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
6013 St->getSrcValue(), St->getSrcValueOffset(),
6014 St->isVolatile(), St->getAlignment());
6017 // Otherwise, lower to two 32-bit copies.
6018 SDOperand LoAddr = Ld->getBasePtr();
6019 SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6020 DAG.getConstant(MVT::i32, 4));
6022 SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
6023 Ld->getSrcValue(), Ld->getSrcValueOffset(),
6024 Ld->isVolatile(), Ld->getAlignment());
6025 SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
6026 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
6028 MinAlign(Ld->getAlignment(), 4));
6030 SDOperand NewChain = LoLd.getValue(1);
6031 if (TokenFactorIndex != -1) {
6032 Ops.push_back(LoLd);
6033 Ops.push_back(HiLd);
6034 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6038 LoAddr = St->getBasePtr();
6039 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6040 DAG.getConstant(MVT::i32, 4));
6042 SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
6043 St->getSrcValue(), St->getSrcValueOffset(),
6044 St->isVolatile(), St->getAlignment());
6045 SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
6046 St->getSrcValue(), St->getSrcValueOffset()+4,
6048 MinAlign(St->getAlignment(), 4));
6049 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
6055 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
6056 /// X86ISD::FXOR nodes.
6057 static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
6058 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
6059 // F[X]OR(0.0, x) -> x
6060 // F[X]OR(x, 0.0) -> x
6061 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6062 if (C->getValueAPF().isPosZero())
6063 return N->getOperand(1);
6064 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6065 if (C->getValueAPF().isPosZero())
6066 return N->getOperand(0);
6070 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
6071 static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
6072 // FAND(0.0, x) -> 0.0
6073 // FAND(x, 0.0) -> 0.0
6074 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6075 if (C->getValueAPF().isPosZero())
6076 return N->getOperand(0);
6077 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6078 if (C->getValueAPF().isPosZero())
6079 return N->getOperand(1);
6084 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
6085 DAGCombinerInfo &DCI) const {
6086 SelectionDAG &DAG = DCI.DAG;
6087 switch (N->getOpcode()) {
6089 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, Subtarget);
6090 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
6092 return PerformSTORECombine(cast<StoreSDNode>(N), DAG, Subtarget);
6094 case X86ISD::FOR: return PerformFORCombine(N, DAG);
6095 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
6101 //===----------------------------------------------------------------------===//
6102 // X86 Inline Assembly Support
6103 //===----------------------------------------------------------------------===//
6105 /// getConstraintType - Given a constraint letter, return the type of
6106 /// constraint it is for this target.
6107 X86TargetLowering::ConstraintType
6108 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
6109 if (Constraint.size() == 1) {
6110 switch (Constraint[0]) {
6120 return C_RegisterClass;
6125 return TargetLowering::getConstraintType(Constraint);
6128 /// LowerXConstraint - try to replace an X constraint, which matches anything,
6129 /// with another that has more specific requirements based on the type of the
6130 /// corresponding operand.
6131 void X86TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT,
6132 std::string& s) const {
6133 if (MVT::isFloatingPoint(ConstraintVT)) {
6134 if (Subtarget->hasSSE2())
6136 else if (Subtarget->hasSSE1())
6141 return TargetLowering::lowerXConstraint(ConstraintVT, s);
6144 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6145 /// vector. If it is invalid, don't add anything to Ops.
6146 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
6148 std::vector<SDOperand>&Ops,
6149 SelectionDAG &DAG) {
6150 SDOperand Result(0, 0);
6152 switch (Constraint) {
6155 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
6156 if (C->getValue() <= 31) {
6157 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6163 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
6164 if (C->getValue() <= 255) {
6165 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6171 // Literal immediates are always ok.
6172 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
6173 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
6177 // If we are in non-pic codegen mode, we allow the address of a global (with
6178 // an optional displacement) to be used with 'i'.
6179 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
6182 // Match either (GA) or (GA+C)
6184 Offset = GA->getOffset();
6185 } else if (Op.getOpcode() == ISD::ADD) {
6186 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6187 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6189 Offset = GA->getOffset()+C->getValue();
6191 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6192 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6194 Offset = GA->getOffset()+C->getValue();
6201 // If addressing this global requires a load (e.g. in PIC mode), we can't
6203 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
6207 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
6213 // Otherwise, not valid for this mode.
6219 Ops.push_back(Result);
6222 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6225 std::vector<unsigned> X86TargetLowering::
6226 getRegClassForInlineAsmConstraint(const std::string &Constraint,
6227 MVT::ValueType VT) const {
6228 if (Constraint.size() == 1) {
6229 // FIXME: not handling fp-stack yet!
6230 switch (Constraint[0]) { // GCC X86 Constraint Letters
6231 default: break; // Unknown constraint letter
6232 case 'A': // EAX/EDX
6233 if (VT == MVT::i32 || VT == MVT::i64)
6234 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
6236 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
6239 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
6240 else if (VT == MVT::i16)
6241 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
6242 else if (VT == MVT::i8)
6243 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
6244 else if (VT == MVT::i64)
6245 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
6250 return std::vector<unsigned>();
6253 std::pair<unsigned, const TargetRegisterClass*>
6254 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6255 MVT::ValueType VT) const {
6256 // First, see if this is a constraint that directly corresponds to an LLVM
6258 if (Constraint.size() == 1) {
6259 // GCC Constraint Letters
6260 switch (Constraint[0]) {
6262 case 'r': // GENERAL_REGS
6263 case 'R': // LEGACY_REGS
6264 case 'l': // INDEX_REGS
6265 if (VT == MVT::i64 && Subtarget->is64Bit())
6266 return std::make_pair(0U, X86::GR64RegisterClass);
6268 return std::make_pair(0U, X86::GR32RegisterClass);
6269 else if (VT == MVT::i16)
6270 return std::make_pair(0U, X86::GR16RegisterClass);
6271 else if (VT == MVT::i8)
6272 return std::make_pair(0U, X86::GR8RegisterClass);
6274 case 'f': // FP Stack registers.
6275 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
6276 // value to the correct fpstack register class.
6277 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
6278 return std::make_pair(0U, X86::RFP32RegisterClass);
6279 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
6280 return std::make_pair(0U, X86::RFP64RegisterClass);
6281 return std::make_pair(0U, X86::RFP80RegisterClass);
6282 case 'y': // MMX_REGS if MMX allowed.
6283 if (!Subtarget->hasMMX()) break;
6284 return std::make_pair(0U, X86::VR64RegisterClass);
6286 case 'Y': // SSE_REGS if SSE2 allowed
6287 if (!Subtarget->hasSSE2()) break;
6289 case 'x': // SSE_REGS if SSE1 allowed
6290 if (!Subtarget->hasSSE1()) break;
6294 // Scalar SSE types.
6297 return std::make_pair(0U, X86::FR32RegisterClass);
6300 return std::make_pair(0U, X86::FR64RegisterClass);
6308 return std::make_pair(0U, X86::VR128RegisterClass);
6314 // Use the default implementation in TargetLowering to convert the register
6315 // constraint into a member of a register class.
6316 std::pair<unsigned, const TargetRegisterClass*> Res;
6317 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6319 // Not found as a standard register?
6320 if (Res.second == 0) {
6321 // GCC calls "st(0)" just plain "st".
6322 if (StringsEqualNoCase("{st}", Constraint)) {
6323 Res.first = X86::ST0;
6324 Res.second = X86::RFP80RegisterClass;
6330 // Otherwise, check to see if this is a register class of the wrong value
6331 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
6332 // turn into {ax},{dx}.
6333 if (Res.second->hasType(VT))
6334 return Res; // Correct type already, nothing to do.
6336 // All of the single-register GCC register classes map their values onto
6337 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
6338 // really want an 8-bit or 32-bit register, map to the appropriate register
6339 // class and return the appropriate register.
6340 if (Res.second != X86::GR16RegisterClass)
6343 if (VT == MVT::i8) {
6344 unsigned DestReg = 0;
6345 switch (Res.first) {
6347 case X86::AX: DestReg = X86::AL; break;
6348 case X86::DX: DestReg = X86::DL; break;
6349 case X86::CX: DestReg = X86::CL; break;
6350 case X86::BX: DestReg = X86::BL; break;
6353 Res.first = DestReg;
6354 Res.second = Res.second = X86::GR8RegisterClass;
6356 } else if (VT == MVT::i32) {
6357 unsigned DestReg = 0;
6358 switch (Res.first) {
6360 case X86::AX: DestReg = X86::EAX; break;
6361 case X86::DX: DestReg = X86::EDX; break;
6362 case X86::CX: DestReg = X86::ECX; break;
6363 case X86::BX: DestReg = X86::EBX; break;
6364 case X86::SI: DestReg = X86::ESI; break;
6365 case X86::DI: DestReg = X86::EDI; break;
6366 case X86::BP: DestReg = X86::EBP; break;
6367 case X86::SP: DestReg = X86::ESP; break;
6370 Res.first = DestReg;
6371 Res.second = Res.second = X86::GR32RegisterClass;
6373 } else if (VT == MVT::i64) {
6374 unsigned DestReg = 0;
6375 switch (Res.first) {
6377 case X86::AX: DestReg = X86::RAX; break;
6378 case X86::DX: DestReg = X86::RDX; break;
6379 case X86::CX: DestReg = X86::RCX; break;
6380 case X86::BX: DestReg = X86::RBX; break;
6381 case X86::SI: DestReg = X86::RSI; break;
6382 case X86::DI: DestReg = X86::RDI; break;
6383 case X86::BP: DestReg = X86::RBP; break;
6384 case X86::SP: DestReg = X86::RSP; break;
6387 Res.first = DestReg;
6388 Res.second = Res.second = X86::GR64RegisterClass;