1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
41 #include "llvm/Support/CommandLine.h"
45 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
47 // Forward declarations.
48 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
50 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
51 : TargetLowering(TM) {
52 Subtarget = &TM.getSubtarget<X86Subtarget>();
53 X86ScalarSSEf64 = Subtarget->hasSSE2();
54 X86ScalarSSEf32 = Subtarget->hasSSE1();
55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
59 RegInfo = TM.getRegisterInfo();
62 // Set up the TargetLowering object.
64 // X86 is weird, it always uses i8 for shift amounts and setcc results.
65 setShiftAmountType(MVT::i8);
66 setBooleanContents(ZeroOrOneBooleanContent);
67 setSchedulingPreference(SchedulingForRegPressure);
68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
69 setStackPointerRegisterToSaveRestore(X86StackPtr);
71 if (Subtarget->isTargetDarwin()) {
72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(false);
74 setUseUnderscoreLongJmp(false);
75 } else if (Subtarget->isTargetMingw()) {
76 // MS runtime is weird: it exports _setjmp, but longjmp!
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(false);
80 setUseUnderscoreSetJmp(true);
81 setUseUnderscoreLongJmp(true);
84 // Set up the register classes.
85 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
86 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
87 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
88 if (Subtarget->is64Bit())
89 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 // We don't accept any truncstore of integer registers.
94 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
97 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 // SETOEQ and SETUNE require checking two conditions.
102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
115 if (Subtarget->is64Bit()) {
116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
119 if (X86ScalarSSEf64) {
120 // We have an impenetrably clever algorithm for ui64->double only.
121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
123 // We have faster algorithm for ui32->single only.
124 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
126 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
129 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
131 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
132 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
133 // SSE has no i16 to fp conversion, only i32
134 if (X86ScalarSSEf32) {
135 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
136 // f32 and f64 cases are Legal, f80 case is not
137 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
139 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
140 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
143 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
144 // are Legal, f80 is custom lowered.
145 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
146 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
148 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
150 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
151 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
153 if (X86ScalarSSEf32) {
154 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
155 // f32 and f64 cases are Legal, f80 case is not
156 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
158 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
159 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
162 // Handle FP_TO_UINT by promoting the destination to a larger signed
164 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
165 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
166 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
168 if (Subtarget->is64Bit()) {
169 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
170 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
172 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
173 // Expand FP_TO_UINT into a select.
174 // FIXME: We would like to use a Custom expander here eventually to do
175 // the optimal thing for SSE vs. the default expansion in the legalizer.
176 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
178 // With SSE3 we can use fisttpll to convert to a signed i64.
179 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
182 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
183 if (!X86ScalarSSEf64) {
184 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
185 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
188 // Scalar integer divide and remainder are lowered to use operations that
189 // produce two results, to match the available instructions. This exposes
190 // the two-result form to trivial CSE, which is able to combine x/y and x%y
191 // into a single instruction.
193 // Scalar integer multiply-high is also lowered to use two-result
194 // operations, to match the available instructions. However, plain multiply
195 // (low) operations are left as Legal, as there are single-result
196 // instructions for this in x86. Using the two-result multiply instructions
197 // when both high and low results are needed must be arranged by dagcombine.
198 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
199 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
200 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
201 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
202 setOperationAction(ISD::SREM , MVT::i8 , Expand);
203 setOperationAction(ISD::UREM , MVT::i8 , Expand);
204 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
205 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
206 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
207 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
208 setOperationAction(ISD::SREM , MVT::i16 , Expand);
209 setOperationAction(ISD::UREM , MVT::i16 , Expand);
210 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
211 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
212 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
213 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
214 setOperationAction(ISD::SREM , MVT::i32 , Expand);
215 setOperationAction(ISD::UREM , MVT::i32 , Expand);
216 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
217 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
218 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
219 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
220 setOperationAction(ISD::SREM , MVT::i64 , Expand);
221 setOperationAction(ISD::UREM , MVT::i64 , Expand);
223 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
224 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
225 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
226 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
227 if (Subtarget->is64Bit())
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
232 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
233 setOperationAction(ISD::FREM , MVT::f32 , Expand);
234 setOperationAction(ISD::FREM , MVT::f64 , Expand);
235 setOperationAction(ISD::FREM , MVT::f80 , Expand);
236 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
238 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
239 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
240 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
241 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
242 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
243 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
244 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
245 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
246 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
247 if (Subtarget->is64Bit()) {
248 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
249 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
250 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
253 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
254 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
256 // These should be promoted to a larger select which is supported.
257 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
258 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
259 // X86 wants to expand cmov itself.
260 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
261 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
262 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
263 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
264 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
265 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
266 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
267 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
268 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
269 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
270 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
271 if (Subtarget->is64Bit()) {
272 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
273 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
275 // X86 ret instruction may pop stack.
276 setOperationAction(ISD::RET , MVT::Other, Custom);
277 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
280 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
281 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
282 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
283 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
284 if (Subtarget->is64Bit())
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
289 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
290 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
291 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
293 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
294 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
295 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
296 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
297 if (Subtarget->is64Bit()) {
298 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
299 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
300 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
303 if (Subtarget->hasSSE1())
304 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
306 if (!Subtarget->hasSSE2())
307 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
309 // Expand certain atomics
310 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
311 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
312 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
313 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
315 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
316 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
317 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
318 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
320 if (!Subtarget->is64Bit()) {
321 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
324 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
325 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
326 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
327 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
330 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
331 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
332 // FIXME - use subtarget debug flags
333 if (!Subtarget->isTargetDarwin() &&
334 !Subtarget->isTargetELF() &&
335 !Subtarget->isTargetCygMing()) {
336 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
337 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
340 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
341 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
342 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
343 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
344 if (Subtarget->is64Bit()) {
345 setExceptionPointerRegister(X86::RAX);
346 setExceptionSelectorRegister(X86::RDX);
348 setExceptionPointerRegister(X86::EAX);
349 setExceptionSelectorRegister(X86::EDX);
351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
352 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
354 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
356 setOperationAction(ISD::TRAP, MVT::Other, Legal);
358 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
359 setOperationAction(ISD::VASTART , MVT::Other, Custom);
360 setOperationAction(ISD::VAEND , MVT::Other, Expand);
361 if (Subtarget->is64Bit()) {
362 setOperationAction(ISD::VAARG , MVT::Other, Custom);
363 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
365 setOperationAction(ISD::VAARG , MVT::Other, Expand);
366 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
369 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
370 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
371 if (Subtarget->is64Bit())
372 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
373 if (Subtarget->isTargetCygMing())
374 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
376 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
378 if (X86ScalarSSEf64) {
379 // f32 and f64 use SSE.
380 // Set up the FP register classes.
381 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
382 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
384 // Use ANDPD to simulate FABS.
385 setOperationAction(ISD::FABS , MVT::f64, Custom);
386 setOperationAction(ISD::FABS , MVT::f32, Custom);
388 // Use XORP to simulate FNEG.
389 setOperationAction(ISD::FNEG , MVT::f64, Custom);
390 setOperationAction(ISD::FNEG , MVT::f32, Custom);
392 // Use ANDPD and ORPD to simulate FCOPYSIGN.
393 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
394 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
396 // We don't support sin/cos/fmod
397 setOperationAction(ISD::FSIN , MVT::f64, Expand);
398 setOperationAction(ISD::FCOS , MVT::f64, Expand);
399 setOperationAction(ISD::FSIN , MVT::f32, Expand);
400 setOperationAction(ISD::FCOS , MVT::f32, Expand);
402 // Expand FP immediates into loads from the stack, except for the special
404 addLegalFPImmediate(APFloat(+0.0)); // xorpd
405 addLegalFPImmediate(APFloat(+0.0f)); // xorps
407 // Floating truncations from f80 and extensions to f80 go through memory.
408 // If optimizing, we lie about this though and handle it in
409 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
411 setConvertAction(MVT::f32, MVT::f80, Expand);
412 setConvertAction(MVT::f64, MVT::f80, Expand);
413 setConvertAction(MVT::f80, MVT::f32, Expand);
414 setConvertAction(MVT::f80, MVT::f64, Expand);
416 } else if (X86ScalarSSEf32) {
417 // Use SSE for f32, x87 for f64.
418 // Set up the FP register classes.
419 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
420 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
422 // Use ANDPS to simulate FABS.
423 setOperationAction(ISD::FABS , MVT::f32, Custom);
425 // Use XORP to simulate FNEG.
426 setOperationAction(ISD::FNEG , MVT::f32, Custom);
428 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
430 // Use ANDPS and ORPS to simulate FCOPYSIGN.
431 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
432 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
434 // We don't support sin/cos/fmod
435 setOperationAction(ISD::FSIN , MVT::f32, Expand);
436 setOperationAction(ISD::FCOS , MVT::f32, Expand);
438 // Special cases we handle for FP constants.
439 addLegalFPImmediate(APFloat(+0.0f)); // xorps
440 addLegalFPImmediate(APFloat(+0.0)); // FLD0
441 addLegalFPImmediate(APFloat(+1.0)); // FLD1
442 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
443 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
445 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
446 // this though and handle it in InstructionSelectPreprocess so that
447 // dagcombine2 can hack on these.
449 setConvertAction(MVT::f32, MVT::f64, Expand);
450 setConvertAction(MVT::f32, MVT::f80, Expand);
451 setConvertAction(MVT::f80, MVT::f32, Expand);
452 setConvertAction(MVT::f64, MVT::f32, Expand);
453 // And x87->x87 truncations also.
454 setConvertAction(MVT::f80, MVT::f64, Expand);
458 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
459 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
462 // f32 and f64 in x87.
463 // Set up the FP register classes.
464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
465 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
467 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
468 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
469 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
470 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
472 // Floating truncations go through memory. If optimizing, we lie about
473 // this though and handle it in InstructionSelectPreprocess so that
474 // dagcombine2 can hack on these.
476 setConvertAction(MVT::f80, MVT::f32, Expand);
477 setConvertAction(MVT::f64, MVT::f32, Expand);
478 setConvertAction(MVT::f80, MVT::f64, Expand);
482 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
483 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
485 addLegalFPImmediate(APFloat(+0.0)); // FLD0
486 addLegalFPImmediate(APFloat(+1.0)); // FLD1
487 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
488 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
489 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
490 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
491 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
492 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
495 // Long double always uses X87.
496 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
497 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
498 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
501 APFloat TmpFlt(+0.0);
502 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
504 addLegalFPImmediate(TmpFlt); // FLD0
506 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
507 APFloat TmpFlt2(+1.0);
508 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
510 addLegalFPImmediate(TmpFlt2); // FLD1
511 TmpFlt2.changeSign();
512 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
516 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
517 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
520 // Always use a library call for pow.
521 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
522 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
523 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
525 setOperationAction(ISD::FLOG, MVT::f80, Expand);
526 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
527 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
528 setOperationAction(ISD::FEXP, MVT::f80, Expand);
529 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
531 // First set operation action for all vector types to either promote
532 // (for widening) or expand (for scalarization). Then we will selectively
533 // turn on ones that can be effectively codegen'd.
534 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
535 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
536 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
551 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
581 if (!DisableMMX && Subtarget->hasMMX()) {
582 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
583 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
584 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
585 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
586 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
588 // FIXME: add MMX packed arithmetics
590 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
591 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
592 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
593 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
595 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
596 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
597 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
598 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
600 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
601 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
603 setOperationAction(ISD::AND, MVT::v8i8, Promote);
604 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
605 setOperationAction(ISD::AND, MVT::v4i16, Promote);
606 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
607 setOperationAction(ISD::AND, MVT::v2i32, Promote);
608 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
609 setOperationAction(ISD::AND, MVT::v1i64, Legal);
611 setOperationAction(ISD::OR, MVT::v8i8, Promote);
612 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
613 setOperationAction(ISD::OR, MVT::v4i16, Promote);
614 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
615 setOperationAction(ISD::OR, MVT::v2i32, Promote);
616 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
617 setOperationAction(ISD::OR, MVT::v1i64, Legal);
619 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
620 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
621 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
622 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
623 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
624 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
625 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
627 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
628 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
629 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
630 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
631 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
632 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
633 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
634 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
635 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
638 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
639 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
640 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
641 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
646 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
653 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
655 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
656 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
657 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
658 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
659 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
660 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
663 if (Subtarget->hasSSE1()) {
664 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
666 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
667 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
668 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
669 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
670 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
671 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
672 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
673 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
675 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
676 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
677 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
680 if (Subtarget->hasSSE2()) {
681 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
682 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
683 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
684 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
685 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
687 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
688 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
689 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
690 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
691 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
692 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
693 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
694 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
695 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
696 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
697 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
698 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
699 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
700 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
701 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
702 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
704 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
705 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
706 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
707 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
709 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
710 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
711 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
712 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
715 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
716 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
717 MVT VT = (MVT::SimpleValueType)i;
718 // Do not attempt to custom lower non-power-of-2 vectors
719 if (!isPowerOf2_32(VT.getVectorNumElements()))
721 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
722 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
723 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
725 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
726 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
727 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
728 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
729 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
731 if (Subtarget->is64Bit()) {
732 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
733 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
736 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
737 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
738 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
739 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
740 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
741 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
742 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
743 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
744 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
745 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
746 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
747 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
750 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
752 // Custom lower v2i64 and v2f64 selects.
753 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
754 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
755 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
756 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
760 if (Subtarget->hasSSE41()) {
761 // FIXME: Do we need to handle scalar-to-vector here?
762 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
764 // i8 and i16 vectors are custom , because the source register and source
765 // source memory operand types are not the same width. f32 vectors are
766 // custom since the immediate controlling the insert encodes additional
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
774 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
778 if (Subtarget->is64Bit()) {
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
784 if (Subtarget->hasSSE42()) {
785 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
788 // We want to custom lower some of our intrinsics.
789 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
791 // Add/Sub/Mul with overflow operations are custom lowered.
792 setOperationAction(ISD::SADDO, MVT::i32, Custom);
793 setOperationAction(ISD::SADDO, MVT::i64, Custom);
794 setOperationAction(ISD::UADDO, MVT::i32, Custom);
795 setOperationAction(ISD::UADDO, MVT::i64, Custom);
796 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
797 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
798 setOperationAction(ISD::USUBO, MVT::i32, Custom);
799 setOperationAction(ISD::USUBO, MVT::i64, Custom);
800 setOperationAction(ISD::SMULO, MVT::i32, Custom);
801 setOperationAction(ISD::SMULO, MVT::i64, Custom);
802 setOperationAction(ISD::UMULO, MVT::i32, Custom);
803 setOperationAction(ISD::UMULO, MVT::i64, Custom);
805 // We have target-specific dag combine patterns for the following nodes:
806 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
807 setTargetDAGCombine(ISD::BUILD_VECTOR);
808 setTargetDAGCombine(ISD::SELECT);
809 setTargetDAGCombine(ISD::SHL);
810 setTargetDAGCombine(ISD::SRA);
811 setTargetDAGCombine(ISD::SRL);
812 setTargetDAGCombine(ISD::STORE);
814 computeRegisterProperties();
816 // FIXME: These should be based on subtarget info. Plus, the values should
817 // be smaller when we are in optimizing for size mode.
818 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
819 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
820 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
821 allowUnalignedMemoryAccesses = true; // x86 supports it!
822 setPrefLoopAlignment(16);
826 MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
831 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
832 /// the desired ByVal argument alignment.
833 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
836 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
837 if (VTy->getBitWidth() == 128)
839 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
840 unsigned EltAlign = 0;
841 getMaxByValAlign(ATy->getElementType(), EltAlign);
842 if (EltAlign > MaxAlign)
844 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
845 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
846 unsigned EltAlign = 0;
847 getMaxByValAlign(STy->getElementType(i), EltAlign);
848 if (EltAlign > MaxAlign)
857 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
858 /// function arguments in the caller parameter area. For X86, aggregates
859 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
860 /// are at 4-byte boundaries.
861 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
862 if (Subtarget->is64Bit()) {
863 // Max of 8 and alignment of type.
864 unsigned TyAlign = TD->getABITypeAlignment(Ty);
871 if (Subtarget->hasSSE1())
872 getMaxByValAlign(Ty, Align);
876 /// getOptimalMemOpType - Returns the target specific optimal type for load
877 /// and store operations as a result of memset, memcpy, and memmove
878 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
881 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
882 bool isSrcConst, bool isSrcStr) const {
883 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
884 // linux. This is because the stack realignment code can't handle certain
885 // cases like PR2962. This should be removed when PR2962 is fixed.
886 if (Subtarget->getStackAlignment() >= 16) {
887 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
889 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
892 if (Subtarget->is64Bit() && Size >= 8)
898 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
900 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
901 SelectionDAG &DAG) const {
902 if (usesGlobalOffsetTable())
903 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
904 if (!Subtarget->isPICStyleRIPRel())
905 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
909 //===----------------------------------------------------------------------===//
910 // Return Value Calling Convention Implementation
911 //===----------------------------------------------------------------------===//
913 #include "X86GenCallingConv.inc"
915 /// LowerRET - Lower an ISD::RET node.
916 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
917 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
919 SmallVector<CCValAssign, 16> RVLocs;
920 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
921 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
922 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
923 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
925 // If this is the first return lowered for this function, add the regs to the
926 // liveout set for the function.
927 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
928 for (unsigned i = 0; i != RVLocs.size(); ++i)
929 if (RVLocs[i].isRegLoc())
930 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
932 SDValue Chain = Op.getOperand(0);
934 // Handle tail call return.
935 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
936 if (Chain.getOpcode() == X86ISD::TAILCALL) {
937 SDValue TailCall = Chain;
938 SDValue TargetAddress = TailCall.getOperand(1);
939 SDValue StackAdjustment = TailCall.getOperand(2);
940 assert(((TargetAddress.getOpcode() == ISD::Register &&
941 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
942 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
943 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
944 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
945 "Expecting an global address, external symbol, or register");
946 assert(StackAdjustment.getOpcode() == ISD::Constant &&
947 "Expecting a const value");
949 SmallVector<SDValue,8> Operands;
950 Operands.push_back(Chain.getOperand(0));
951 Operands.push_back(TargetAddress);
952 Operands.push_back(StackAdjustment);
953 // Copy registers used by the call. Last operand is a flag so it is not
955 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
956 Operands.push_back(Chain.getOperand(i));
958 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
965 SmallVector<SDValue, 6> RetOps;
966 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
967 // Operand #1 = Bytes To Pop
968 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
970 // Copy the result values into the output registers.
971 for (unsigned i = 0; i != RVLocs.size(); ++i) {
972 CCValAssign &VA = RVLocs[i];
973 assert(VA.isRegLoc() && "Can only return in registers!");
974 SDValue ValToCopy = Op.getOperand(i*2+1);
976 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
977 // the RET instruction and handled by the FP Stackifier.
978 if (RVLocs[i].getLocReg() == X86::ST0 ||
979 RVLocs[i].getLocReg() == X86::ST1) {
980 // If this is a copy from an xmm register to ST(0), use an FPExtend to
981 // change the value to the FP stack register class.
982 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
983 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
984 RetOps.push_back(ValToCopy);
985 // Don't emit a copytoreg.
989 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
990 Flag = Chain.getValue(1);
993 // The x86-64 ABI for returning structs by value requires that we copy
994 // the sret argument into %rax for the return. We saved the argument into
995 // a virtual register in the entry block, so now we copy the value out
997 if (Subtarget->is64Bit() &&
998 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
999 MachineFunction &MF = DAG.getMachineFunction();
1000 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1001 unsigned Reg = FuncInfo->getSRetReturnReg();
1003 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1004 FuncInfo->setSRetReturnReg(Reg);
1006 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
1008 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
1009 Flag = Chain.getValue(1);
1012 RetOps[0] = Chain; // Update chain.
1014 // Add the flag if we have it.
1016 RetOps.push_back(Flag);
1018 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
1022 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1023 /// appropriate copies out of appropriate physical registers. This assumes that
1024 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1025 /// being lowered. The returns a SDNode with the same number of values as the
1027 SDNode *X86TargetLowering::
1028 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1029 unsigned CallingConv, SelectionDAG &DAG) {
1031 // Assign locations to each value returned by this call.
1032 SmallVector<CCValAssign, 16> RVLocs;
1033 bool isVarArg = TheCall->isVarArg();
1034 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
1035 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1037 SmallVector<SDValue, 8> ResultVals;
1039 // Copy all of the result registers out of their specified physreg.
1040 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1041 MVT CopyVT = RVLocs[i].getValVT();
1043 // If this is a call to a function that returns an fp value on the floating
1044 // point stack, but where we prefer to use the value in xmm registers, copy
1045 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1046 if ((RVLocs[i].getLocReg() == X86::ST0 ||
1047 RVLocs[i].getLocReg() == X86::ST1) &&
1048 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
1052 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
1053 CopyVT, InFlag).getValue(1);
1054 SDValue Val = Chain.getValue(0);
1055 InFlag = Chain.getValue(2);
1057 if (CopyVT != RVLocs[i].getValVT()) {
1058 // Round the F80 the right size, which also moves to the appropriate xmm
1060 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
1061 // This truncation won't change the value.
1062 DAG.getIntPtrConstant(1));
1065 ResultVals.push_back(Val);
1068 // Merge everything together with a MERGE_VALUES node.
1069 ResultVals.push_back(Chain);
1070 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0],
1071 ResultVals.size()).getNode();
1075 //===----------------------------------------------------------------------===//
1076 // C & StdCall & Fast Calling Convention implementation
1077 //===----------------------------------------------------------------------===//
1078 // StdCall calling convention seems to be standard for many Windows' API
1079 // routines and around. It differs from C calling convention just a little:
1080 // callee should clean up the stack, not caller. Symbols should be also
1081 // decorated in some fancy way :) It doesn't support any vector arguments.
1082 // For info on fast calling convention see Fast Calling Convention (tail call)
1083 // implementation LowerX86_32FastCCCallTo.
1085 /// AddLiveIn - This helper function adds the specified physical register to the
1086 /// MachineFunction as a live in value. It also creates a corresponding virtual
1087 /// register for it.
1088 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1089 const TargetRegisterClass *RC) {
1090 assert(RC->contains(PReg) && "Not the correct regclass!");
1091 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1092 MF.getRegInfo().addLiveIn(PReg, VReg);
1096 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1098 static bool CallIsStructReturn(CallSDNode *TheCall) {
1099 unsigned NumOps = TheCall->getNumArgs();
1103 return TheCall->getArgFlags(0).isSRet();
1106 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1107 /// return semantics.
1108 static bool ArgsAreStructReturn(SDValue Op) {
1109 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1113 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1116 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1117 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1119 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1123 switch (CallingConv) {
1126 case CallingConv::X86_StdCall:
1127 return !Subtarget->is64Bit();
1128 case CallingConv::X86_FastCall:
1129 return !Subtarget->is64Bit();
1130 case CallingConv::Fast:
1131 return PerformTailCallOpt;
1135 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1136 /// given CallingConvention value.
1137 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1138 if (Subtarget->is64Bit()) {
1139 if (Subtarget->isTargetWin64())
1140 return CC_X86_Win64_C;
1141 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1142 return CC_X86_64_TailCall;
1147 if (CC == CallingConv::X86_FastCall)
1148 return CC_X86_32_FastCall;
1149 else if (CC == CallingConv::Fast)
1150 return CC_X86_32_FastCC;
1155 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1156 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1158 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1159 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1160 if (CC == CallingConv::X86_FastCall)
1162 else if (CC == CallingConv::X86_StdCall)
1168 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1169 /// in a register before calling.
1170 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1171 return !IsTailCall && !Is64Bit &&
1172 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1173 Subtarget->isPICStyleGOT();
1176 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1177 /// address to be loaded in a register.
1179 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1180 return !Is64Bit && IsTailCall &&
1181 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1182 Subtarget->isPICStyleGOT();
1185 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1186 /// by "Src" to address "Dst" with size and alignment information specified by
1187 /// the specific parameter attribute. The copy will be passed as a byval
1188 /// function parameter.
1190 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1191 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1192 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1193 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1194 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1197 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1198 const CCValAssign &VA,
1199 MachineFrameInfo *MFI,
1201 SDValue Root, unsigned i) {
1202 // Create the nodes corresponding to a load from this parameter slot.
1203 ISD::ArgFlagsTy Flags =
1204 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1205 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1206 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1208 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1209 // changed with more analysis.
1210 // In case of tail call optimization mark all arguments mutable. Since they
1211 // could be overwritten by lowering of arguments in case of a tail call.
1212 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1213 VA.getLocMemOffset(), isImmutable);
1214 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1215 if (Flags.isByVal())
1217 return DAG.getLoad(VA.getValVT(), Root, FIN,
1218 PseudoSourceValue::getFixedStack(FI), 0);
1222 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1223 MachineFunction &MF = DAG.getMachineFunction();
1224 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1226 const Function* Fn = MF.getFunction();
1227 if (Fn->hasExternalLinkage() &&
1228 Subtarget->isTargetCygMing() &&
1229 Fn->getName() == "main")
1230 FuncInfo->setForceFramePointer(true);
1232 // Decorate the function name.
1233 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1235 MachineFrameInfo *MFI = MF.getFrameInfo();
1236 SDValue Root = Op.getOperand(0);
1237 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1238 unsigned CC = MF.getFunction()->getCallingConv();
1239 bool Is64Bit = Subtarget->is64Bit();
1240 bool IsWin64 = Subtarget->isTargetWin64();
1242 assert(!(isVarArg && CC == CallingConv::Fast) &&
1243 "Var args not supported with calling convention fastcc");
1245 // Assign locations to all of the incoming arguments.
1246 SmallVector<CCValAssign, 16> ArgLocs;
1247 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1248 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1250 SmallVector<SDValue, 8> ArgValues;
1251 unsigned LastVal = ~0U;
1252 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1253 CCValAssign &VA = ArgLocs[i];
1254 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1256 assert(VA.getValNo() != LastVal &&
1257 "Don't support value assigned to multiple locs yet");
1258 LastVal = VA.getValNo();
1260 if (VA.isRegLoc()) {
1261 MVT RegVT = VA.getLocVT();
1262 TargetRegisterClass *RC = NULL;
1263 if (RegVT == MVT::i32)
1264 RC = X86::GR32RegisterClass;
1265 else if (Is64Bit && RegVT == MVT::i64)
1266 RC = X86::GR64RegisterClass;
1267 else if (RegVT == MVT::f32)
1268 RC = X86::FR32RegisterClass;
1269 else if (RegVT == MVT::f64)
1270 RC = X86::FR64RegisterClass;
1271 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1272 RC = X86::VR128RegisterClass;
1273 else if (RegVT.isVector()) {
1274 assert(RegVT.getSizeInBits() == 64);
1276 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1278 // Darwin calling convention passes MMX values in either GPRs or
1279 // XMMs in x86-64. Other targets pass them in memory.
1280 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1281 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1284 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1289 assert(0 && "Unknown argument type!");
1292 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1293 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1295 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1296 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1298 if (VA.getLocInfo() == CCValAssign::SExt)
1299 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1300 DAG.getValueType(VA.getValVT()));
1301 else if (VA.getLocInfo() == CCValAssign::ZExt)
1302 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1303 DAG.getValueType(VA.getValVT()));
1305 if (VA.getLocInfo() != CCValAssign::Full)
1306 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1308 // Handle MMX values passed in GPRs.
1309 if (Is64Bit && RegVT != VA.getLocVT()) {
1310 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1311 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1312 else if (RC == X86::VR128RegisterClass) {
1313 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1314 DAG.getConstant(0, MVT::i64));
1315 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1319 ArgValues.push_back(ArgValue);
1321 assert(VA.isMemLoc());
1322 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1326 // The x86-64 ABI for returning structs by value requires that we copy
1327 // the sret argument into %rax for the return. Save the argument into
1328 // a virtual register so that we can access it from the return points.
1329 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1330 MachineFunction &MF = DAG.getMachineFunction();
1331 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1332 unsigned Reg = FuncInfo->getSRetReturnReg();
1334 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1335 FuncInfo->setSRetReturnReg(Reg);
1337 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1338 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1341 unsigned StackSize = CCInfo.getNextStackOffset();
1342 // align stack specially for tail calls
1343 if (PerformTailCallOpt && CC == CallingConv::Fast)
1344 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1346 // If the function takes variable number of arguments, make a frame index for
1347 // the start of the first vararg value... for expansion of llvm.va_start.
1349 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1350 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1353 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1355 // FIXME: We should really autogenerate these arrays
1356 static const unsigned GPR64ArgRegsWin64[] = {
1357 X86::RCX, X86::RDX, X86::R8, X86::R9
1359 static const unsigned XMMArgRegsWin64[] = {
1360 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1362 static const unsigned GPR64ArgRegs64Bit[] = {
1363 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1365 static const unsigned XMMArgRegs64Bit[] = {
1366 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1367 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1369 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1372 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1373 GPR64ArgRegs = GPR64ArgRegsWin64;
1374 XMMArgRegs = XMMArgRegsWin64;
1376 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1377 GPR64ArgRegs = GPR64ArgRegs64Bit;
1378 XMMArgRegs = XMMArgRegs64Bit;
1380 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1382 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1385 // For X86-64, if there are vararg parameters that are passed via
1386 // registers, then we must store them to their spots on the stack so they
1387 // may be loaded by deferencing the result of va_next.
1388 VarArgsGPOffset = NumIntRegs * 8;
1389 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1390 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1391 TotalNumXMMRegs * 16, 16);
1393 // Store the integer parameter registers.
1394 SmallVector<SDValue, 8> MemOps;
1395 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1396 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1397 DAG.getIntPtrConstant(VarArgsGPOffset));
1398 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1399 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1400 X86::GR64RegisterClass);
1401 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1403 DAG.getStore(Val.getValue(1), Val, FIN,
1404 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1405 MemOps.push_back(Store);
1406 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1407 DAG.getIntPtrConstant(8));
1410 // Now store the XMM (fp + vector) parameter registers.
1411 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1412 DAG.getIntPtrConstant(VarArgsFPOffset));
1413 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1414 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1415 X86::VR128RegisterClass);
1416 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1418 DAG.getStore(Val.getValue(1), Val, FIN,
1419 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1420 MemOps.push_back(Store);
1421 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1422 DAG.getIntPtrConstant(16));
1424 if (!MemOps.empty())
1425 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1426 &MemOps[0], MemOps.size());
1430 ArgValues.push_back(Root);
1432 // Some CCs need callee pop.
1433 if (IsCalleePop(isVarArg, CC)) {
1434 BytesToPopOnReturn = StackSize; // Callee pops everything.
1435 BytesCallerReserves = 0;
1437 BytesToPopOnReturn = 0; // Callee pops nothing.
1438 // If this is an sret function, the return should pop the hidden pointer.
1439 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1440 BytesToPopOnReturn = 4;
1441 BytesCallerReserves = StackSize;
1445 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1446 if (CC == CallingConv::X86_FastCall)
1447 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1450 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1452 // Return the new list of results.
1453 return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
1454 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1458 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1459 const SDValue &StackPtr,
1460 const CCValAssign &VA,
1462 SDValue Arg, ISD::ArgFlagsTy Flags) {
1463 unsigned LocMemOffset = VA.getLocMemOffset();
1464 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1465 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1466 if (Flags.isByVal()) {
1467 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1469 return DAG.getStore(Chain, Arg, PtrOff,
1470 PseudoSourceValue::getStack(), LocMemOffset);
1473 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1474 /// optimization is performed and it is required.
1476 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1477 SDValue &OutRetAddr,
1482 if (!IsTailCall || FPDiff==0) return Chain;
1484 // Adjust the Return address stack slot.
1485 MVT VT = getPointerTy();
1486 OutRetAddr = getReturnAddressFrameIndex(DAG);
1488 // Load the "old" Return address.
1489 OutRetAddr = DAG.getLoad(VT, Chain, OutRetAddr, NULL, 0);
1490 return SDValue(OutRetAddr.getNode(), 1);
1493 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1494 /// optimization is performed and it is required (FPDiff!=0).
1496 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1497 SDValue Chain, SDValue RetAddrFrIdx,
1498 bool Is64Bit, int FPDiff) {
1499 // Store the return address to the appropriate stack slot.
1500 if (!FPDiff) return Chain;
1501 // Calculate the new stack slot for the return address.
1502 int SlotSize = Is64Bit ? 8 : 4;
1503 int NewReturnAddrFI =
1504 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1505 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1506 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1507 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1508 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1512 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1513 MachineFunction &MF = DAG.getMachineFunction();
1514 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1515 SDValue Chain = TheCall->getChain();
1516 unsigned CC = TheCall->getCallingConv();
1517 bool isVarArg = TheCall->isVarArg();
1518 bool IsTailCall = TheCall->isTailCall() &&
1519 CC == CallingConv::Fast && PerformTailCallOpt;
1520 SDValue Callee = TheCall->getCallee();
1521 bool Is64Bit = Subtarget->is64Bit();
1522 bool IsStructRet = CallIsStructReturn(TheCall);
1524 assert(!(isVarArg && CC == CallingConv::Fast) &&
1525 "Var args not supported with calling convention fastcc");
1527 // Analyze operands of the call, assigning locations to each operand.
1528 SmallVector<CCValAssign, 16> ArgLocs;
1529 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1530 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1532 // Get a count of how many bytes are to be pushed on the stack.
1533 unsigned NumBytes = CCInfo.getNextStackOffset();
1534 if (PerformTailCallOpt && CC == CallingConv::Fast)
1535 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1539 // Lower arguments at fp - stackoffset + fpdiff.
1540 unsigned NumBytesCallerPushed =
1541 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1542 FPDiff = NumBytesCallerPushed - NumBytes;
1544 // Set the delta of movement of the returnaddr stackslot.
1545 // But only set if delta is greater than previous delta.
1546 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1547 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1550 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1552 SDValue RetAddrFrIdx;
1553 // Load return adress for tail calls.
1554 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1557 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1558 SmallVector<SDValue, 8> MemOpChains;
1561 // Walk the register/memloc assignments, inserting copies/loads. In the case
1562 // of tail call optimization arguments are handle later.
1563 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1564 CCValAssign &VA = ArgLocs[i];
1565 SDValue Arg = TheCall->getArg(i);
1566 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1567 bool isByVal = Flags.isByVal();
1569 // Promote the value if needed.
1570 switch (VA.getLocInfo()) {
1571 default: assert(0 && "Unknown loc info!");
1572 case CCValAssign::Full: break;
1573 case CCValAssign::SExt:
1574 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1576 case CCValAssign::ZExt:
1577 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1579 case CCValAssign::AExt:
1580 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1584 if (VA.isRegLoc()) {
1586 MVT RegVT = VA.getLocVT();
1587 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1588 switch (VA.getLocReg()) {
1591 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1593 // Special case: passing MMX values in GPR registers.
1594 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1597 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1598 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1599 // Special case: passing MMX values in XMM registers.
1600 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1601 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1602 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1603 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1604 getMOVLMask(2, DAG));
1609 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1611 if (!IsTailCall || (IsTailCall && isByVal)) {
1612 assert(VA.isMemLoc());
1613 if (StackPtr.getNode() == 0)
1614 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1616 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1617 Chain, Arg, Flags));
1622 if (!MemOpChains.empty())
1623 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1624 &MemOpChains[0], MemOpChains.size());
1626 // Build a sequence of copy-to-reg nodes chained together with token chain
1627 // and flag operands which copy the outgoing args into registers.
1629 // Tail call byval lowering might overwrite argument registers so in case of
1630 // tail call optimization the copies to registers are lowered later.
1632 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1633 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1635 InFlag = Chain.getValue(1);
1638 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1640 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1641 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1642 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1644 InFlag = Chain.getValue(1);
1646 // If we are tail calling and generating PIC/GOT style code load the address
1647 // of the callee into ecx. The value in ecx is used as target of the tail
1648 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1649 // calls on PIC/GOT architectures. Normally we would just put the address of
1650 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1651 // restored (since ebx is callee saved) before jumping to the target@PLT.
1652 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1653 // Note: The actual moving to ecx is done further down.
1654 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1655 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1656 !G->getGlobal()->hasProtectedVisibility())
1657 Callee = LowerGlobalAddress(Callee, DAG);
1658 else if (isa<ExternalSymbolSDNode>(Callee))
1659 Callee = LowerExternalSymbol(Callee,DAG);
1662 if (Is64Bit && isVarArg) {
1663 // From AMD64 ABI document:
1664 // For calls that may call functions that use varargs or stdargs
1665 // (prototype-less calls or calls to functions containing ellipsis (...) in
1666 // the declaration) %al is used as hidden argument to specify the number
1667 // of SSE registers used. The contents of %al do not need to match exactly
1668 // the number of registers, but must be an ubound on the number of SSE
1669 // registers used and is in the range 0 - 8 inclusive.
1671 // FIXME: Verify this on Win64
1672 // Count the number of XMM registers allocated.
1673 static const unsigned XMMArgRegs[] = {
1674 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1675 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1677 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1679 Chain = DAG.getCopyToReg(Chain, X86::AL,
1680 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1681 InFlag = Chain.getValue(1);
1685 // For tail calls lower the arguments to the 'real' stack slot.
1687 SmallVector<SDValue, 8> MemOpChains2;
1690 // Do not flag preceeding copytoreg stuff together with the following stuff.
1692 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1693 CCValAssign &VA = ArgLocs[i];
1694 if (!VA.isRegLoc()) {
1695 assert(VA.isMemLoc());
1696 SDValue Arg = TheCall->getArg(i);
1697 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1698 // Create frame index.
1699 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1700 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1701 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1702 FIN = DAG.getFrameIndex(FI, getPointerTy());
1704 if (Flags.isByVal()) {
1705 // Copy relative to framepointer.
1706 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1707 if (StackPtr.getNode() == 0)
1708 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1709 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1711 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1714 // Store relative to framepointer.
1715 MemOpChains2.push_back(
1716 DAG.getStore(Chain, Arg, FIN,
1717 PseudoSourceValue::getFixedStack(FI), 0));
1722 if (!MemOpChains2.empty())
1723 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1724 &MemOpChains2[0], MemOpChains2.size());
1726 // Copy arguments to their registers.
1727 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1728 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1730 InFlag = Chain.getValue(1);
1734 // Store the return address to the appropriate stack slot.
1735 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1739 // If the callee is a GlobalAddress node (quite common, every direct call is)
1740 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1741 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1742 // We should use extra load for direct calls to dllimported functions in
1744 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1745 getTargetMachine(), true))
1746 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1748 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1749 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1750 } else if (IsTailCall) {
1751 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
1753 Chain = DAG.getCopyToReg(Chain,
1754 DAG.getRegister(Opc, getPointerTy()),
1756 Callee = DAG.getRegister(Opc, getPointerTy());
1757 // Add register as live out.
1758 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1761 // Returns a chain & a flag for retval copy to use.
1762 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1763 SmallVector<SDValue, 8> Ops;
1766 Ops.push_back(Chain);
1767 Ops.push_back(DAG.getIntPtrConstant(NumBytes, true));
1768 Ops.push_back(DAG.getIntPtrConstant(0, true));
1769 if (InFlag.getNode())
1770 Ops.push_back(InFlag);
1771 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1772 InFlag = Chain.getValue(1);
1774 // Returns a chain & a flag for retval copy to use.
1775 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1779 Ops.push_back(Chain);
1780 Ops.push_back(Callee);
1783 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1785 // Add argument registers to the end of the list so that they are known live
1787 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1788 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1789 RegsToPass[i].second.getValueType()));
1791 // Add an implicit use GOT pointer in EBX.
1792 if (!IsTailCall && !Is64Bit &&
1793 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1794 Subtarget->isPICStyleGOT())
1795 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1797 // Add an implicit use of AL for x86 vararg functions.
1798 if (Is64Bit && isVarArg)
1799 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1801 if (InFlag.getNode())
1802 Ops.push_back(InFlag);
1805 assert(InFlag.getNode() &&
1806 "Flag must be set. Depend on flag being set in LowerRET");
1807 Chain = DAG.getNode(X86ISD::TAILCALL,
1808 TheCall->getVTList(), &Ops[0], Ops.size());
1810 return SDValue(Chain.getNode(), Op.getResNo());
1813 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1814 InFlag = Chain.getValue(1);
1816 // Create the CALLSEQ_END node.
1817 unsigned NumBytesForCalleeToPush;
1818 if (IsCalleePop(isVarArg, CC))
1819 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1820 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1821 // If this is is a call to a struct-return function, the callee
1822 // pops the hidden struct pointer, so we have to push it back.
1823 // This is common for Darwin/X86, Linux & Mingw32 targets.
1824 NumBytesForCalleeToPush = 4;
1826 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1828 // Returns a flag for retval copy to use.
1829 Chain = DAG.getCALLSEQ_END(Chain,
1830 DAG.getIntPtrConstant(NumBytes, true),
1831 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1834 InFlag = Chain.getValue(1);
1836 // Handle result values, copying them out of physregs into vregs that we
1838 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1843 //===----------------------------------------------------------------------===//
1844 // Fast Calling Convention (tail call) implementation
1845 //===----------------------------------------------------------------------===//
1847 // Like std call, callee cleans arguments, convention except that ECX is
1848 // reserved for storing the tail called function address. Only 2 registers are
1849 // free for argument passing (inreg). Tail call optimization is performed
1851 // * tailcallopt is enabled
1852 // * caller/callee are fastcc
1853 // On X86_64 architecture with GOT-style position independent code only local
1854 // (within module) calls are supported at the moment.
1855 // To keep the stack aligned according to platform abi the function
1856 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1857 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1858 // If a tail called function callee has more arguments than the caller the
1859 // caller needs to make sure that there is room to move the RETADDR to. This is
1860 // achieved by reserving an area the size of the argument delta right after the
1861 // original REtADDR, but before the saved framepointer or the spilled registers
1862 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1874 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1875 /// for a 16 byte align requirement.
1876 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1877 SelectionDAG& DAG) {
1878 MachineFunction &MF = DAG.getMachineFunction();
1879 const TargetMachine &TM = MF.getTarget();
1880 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1881 unsigned StackAlignment = TFI.getStackAlignment();
1882 uint64_t AlignMask = StackAlignment - 1;
1883 int64_t Offset = StackSize;
1884 uint64_t SlotSize = TD->getPointerSize();
1885 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1886 // Number smaller than 12 so just add the difference.
1887 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1889 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1890 Offset = ((~AlignMask) & Offset) + StackAlignment +
1891 (StackAlignment-SlotSize);
1896 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1897 /// following the call is a return. A function is eligible if caller/callee
1898 /// calling conventions match, currently only fastcc supports tail calls, and
1899 /// the function CALL is immediatly followed by a RET.
1900 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1902 SelectionDAG& DAG) const {
1903 if (!PerformTailCallOpt)
1906 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1907 MachineFunction &MF = DAG.getMachineFunction();
1908 unsigned CallerCC = MF.getFunction()->getCallingConv();
1909 unsigned CalleeCC= TheCall->getCallingConv();
1910 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1911 SDValue Callee = TheCall->getCallee();
1912 // On x86/32Bit PIC/GOT tail calls are supported.
1913 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1914 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1917 // Can only do local tail calls (in same module, hidden or protected) on
1918 // x86_64 PIC/GOT at the moment.
1919 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1920 return G->getGlobal()->hasHiddenVisibility()
1921 || G->getGlobal()->hasProtectedVisibility();
1929 X86TargetLowering::createFastISel(MachineFunction &mf,
1930 MachineModuleInfo *mmo,
1932 DenseMap<const Value *, unsigned> &vm,
1933 DenseMap<const BasicBlock *,
1934 MachineBasicBlock *> &bm,
1935 DenseMap<const AllocaInst *, int> &am
1937 , SmallSet<Instruction*, 8> &cil
1940 return X86::createFastISel(mf, mmo, dw, vm, bm, am
1948 //===----------------------------------------------------------------------===//
1949 // Other Lowering Hooks
1950 //===----------------------------------------------------------------------===//
1953 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1954 MachineFunction &MF = DAG.getMachineFunction();
1955 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1956 int ReturnAddrIndex = FuncInfo->getRAIndex();
1958 if (ReturnAddrIndex == 0) {
1959 // Set up a frame object for the return address.
1960 uint64_t SlotSize = TD->getPointerSize();
1961 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
1962 FuncInfo->setRAIndex(ReturnAddrIndex);
1965 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1969 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
1970 /// specific condition code, returning the condition code and the LHS/RHS of the
1971 /// comparison to make.
1972 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1973 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
1975 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1976 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1977 // X > -1 -> X == 0, jump !sign.
1978 RHS = DAG.getConstant(0, RHS.getValueType());
1979 return X86::COND_NS;
1980 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1981 // X < 0 -> X == 0, jump on sign.
1983 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1985 RHS = DAG.getConstant(0, RHS.getValueType());
1986 return X86::COND_LE;
1990 switch (SetCCOpcode) {
1991 default: assert(0 && "Invalid integer condition!");
1992 case ISD::SETEQ: return X86::COND_E;
1993 case ISD::SETGT: return X86::COND_G;
1994 case ISD::SETGE: return X86::COND_GE;
1995 case ISD::SETLT: return X86::COND_L;
1996 case ISD::SETLE: return X86::COND_LE;
1997 case ISD::SETNE: return X86::COND_NE;
1998 case ISD::SETULT: return X86::COND_B;
1999 case ISD::SETUGT: return X86::COND_A;
2000 case ISD::SETULE: return X86::COND_BE;
2001 case ISD::SETUGE: return X86::COND_AE;
2005 // First determine if it is required or is profitable to flip the operands.
2007 // If LHS is a foldable load, but RHS is not, flip the condition.
2008 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2009 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2010 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2011 std::swap(LHS, RHS);
2014 switch (SetCCOpcode) {
2020 std::swap(LHS, RHS);
2024 // On a floating point condition, the flags are set as follows:
2026 // 0 | 0 | 0 | X > Y
2027 // 0 | 0 | 1 | X < Y
2028 // 1 | 0 | 0 | X == Y
2029 // 1 | 1 | 1 | unordered
2030 switch (SetCCOpcode) {
2031 default: assert(0 && "Condcode should be pre-legalized away");
2033 case ISD::SETEQ: return X86::COND_E;
2034 case ISD::SETOLT: // flipped
2036 case ISD::SETGT: return X86::COND_A;
2037 case ISD::SETOLE: // flipped
2039 case ISD::SETGE: return X86::COND_AE;
2040 case ISD::SETUGT: // flipped
2042 case ISD::SETLT: return X86::COND_B;
2043 case ISD::SETUGE: // flipped
2045 case ISD::SETLE: return X86::COND_BE;
2047 case ISD::SETNE: return X86::COND_NE;
2048 case ISD::SETUO: return X86::COND_P;
2049 case ISD::SETO: return X86::COND_NP;
2053 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2054 /// code. Current x86 isa includes the following FP cmov instructions:
2055 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2056 static bool hasFPCMov(unsigned X86CC) {
2072 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2073 /// true if Op is undef or if its value falls within the specified range (L, H].
2074 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2075 if (Op.getOpcode() == ISD::UNDEF)
2078 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2079 return (Val >= Low && Val < Hi);
2082 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2083 /// true if Op is undef or if its value equal to the specified value.
2084 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2085 if (Op.getOpcode() == ISD::UNDEF)
2087 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2090 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2091 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2092 bool X86::isPSHUFDMask(SDNode *N) {
2093 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2095 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2098 // Check if the value doesn't reference the second vector.
2099 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2100 SDValue Arg = N->getOperand(i);
2101 if (Arg.getOpcode() == ISD::UNDEF) continue;
2102 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2103 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2110 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2111 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2112 bool X86::isPSHUFHWMask(SDNode *N) {
2113 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2115 if (N->getNumOperands() != 8)
2118 // Lower quadword copied in order.
2119 for (unsigned i = 0; i != 4; ++i) {
2120 SDValue Arg = N->getOperand(i);
2121 if (Arg.getOpcode() == ISD::UNDEF) continue;
2122 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2123 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2127 // Upper quadword shuffled.
2128 for (unsigned i = 4; i != 8; ++i) {
2129 SDValue Arg = N->getOperand(i);
2130 if (Arg.getOpcode() == ISD::UNDEF) continue;
2131 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2132 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2133 if (Val < 4 || Val > 7)
2140 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2141 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2142 bool X86::isPSHUFLWMask(SDNode *N) {
2143 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2145 if (N->getNumOperands() != 8)
2148 // Upper quadword copied in order.
2149 for (unsigned i = 4; i != 8; ++i)
2150 if (!isUndefOrEqual(N->getOperand(i), i))
2153 // Lower quadword shuffled.
2154 for (unsigned i = 0; i != 4; ++i)
2155 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2161 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2162 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2163 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2164 if (NumElems != 2 && NumElems != 4) return false;
2166 unsigned Half = NumElems / 2;
2167 for (unsigned i = 0; i < Half; ++i)
2168 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2170 for (unsigned i = Half; i < NumElems; ++i)
2171 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2177 bool X86::isSHUFPMask(SDNode *N) {
2178 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2179 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2182 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2183 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2184 /// half elements to come from vector 1 (which would equal the dest.) and
2185 /// the upper half to come from vector 2.
2186 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2187 if (NumOps != 2 && NumOps != 4) return false;
2189 unsigned Half = NumOps / 2;
2190 for (unsigned i = 0; i < Half; ++i)
2191 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2193 for (unsigned i = Half; i < NumOps; ++i)
2194 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2199 static bool isCommutedSHUFP(SDNode *N) {
2200 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2201 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2204 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2205 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2206 bool X86::isMOVHLPSMask(SDNode *N) {
2207 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2209 if (N->getNumOperands() != 4)
2212 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2213 return isUndefOrEqual(N->getOperand(0), 6) &&
2214 isUndefOrEqual(N->getOperand(1), 7) &&
2215 isUndefOrEqual(N->getOperand(2), 2) &&
2216 isUndefOrEqual(N->getOperand(3), 3);
2219 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2220 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2222 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2223 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2225 if (N->getNumOperands() != 4)
2228 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2229 return isUndefOrEqual(N->getOperand(0), 2) &&
2230 isUndefOrEqual(N->getOperand(1), 3) &&
2231 isUndefOrEqual(N->getOperand(2), 2) &&
2232 isUndefOrEqual(N->getOperand(3), 3);
2235 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2236 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2237 bool X86::isMOVLPMask(SDNode *N) {
2238 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2240 unsigned NumElems = N->getNumOperands();
2241 if (NumElems != 2 && NumElems != 4)
2244 for (unsigned i = 0; i < NumElems/2; ++i)
2245 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2248 for (unsigned i = NumElems/2; i < NumElems; ++i)
2249 if (!isUndefOrEqual(N->getOperand(i), i))
2255 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2256 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2258 bool X86::isMOVHPMask(SDNode *N) {
2259 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2261 unsigned NumElems = N->getNumOperands();
2262 if (NumElems != 2 && NumElems != 4)
2265 for (unsigned i = 0; i < NumElems/2; ++i)
2266 if (!isUndefOrEqual(N->getOperand(i), i))
2269 for (unsigned i = 0; i < NumElems/2; ++i) {
2270 SDValue Arg = N->getOperand(i + NumElems/2);
2271 if (!isUndefOrEqual(Arg, i + NumElems))
2278 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2279 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2280 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2281 bool V2IsSplat = false) {
2282 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2285 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2286 SDValue BitI = Elts[i];
2287 SDValue BitI1 = Elts[i+1];
2288 if (!isUndefOrEqual(BitI, j))
2291 if (isUndefOrEqual(BitI1, NumElts))
2294 if (!isUndefOrEqual(BitI1, j + NumElts))
2302 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2303 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2304 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2307 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2308 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2309 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2310 bool V2IsSplat = false) {
2311 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2314 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2315 SDValue BitI = Elts[i];
2316 SDValue BitI1 = Elts[i+1];
2317 if (!isUndefOrEqual(BitI, j + NumElts/2))
2320 if (isUndefOrEqual(BitI1, NumElts))
2323 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2331 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2332 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2333 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2336 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2337 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2339 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2340 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2342 unsigned NumElems = N->getNumOperands();
2343 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2346 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2347 SDValue BitI = N->getOperand(i);
2348 SDValue BitI1 = N->getOperand(i+1);
2350 if (!isUndefOrEqual(BitI, j))
2352 if (!isUndefOrEqual(BitI1, j))
2359 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2360 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2362 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2363 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2365 unsigned NumElems = N->getNumOperands();
2366 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2369 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2370 SDValue BitI = N->getOperand(i);
2371 SDValue BitI1 = N->getOperand(i + 1);
2373 if (!isUndefOrEqual(BitI, j))
2375 if (!isUndefOrEqual(BitI1, j))
2382 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2383 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2384 /// MOVSD, and MOVD, i.e. setting the lowest element.
2385 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2386 if (NumElts != 2 && NumElts != 4)
2389 if (!isUndefOrEqual(Elts[0], NumElts))
2392 for (unsigned i = 1; i < NumElts; ++i) {
2393 if (!isUndefOrEqual(Elts[i], i))
2400 bool X86::isMOVLMask(SDNode *N) {
2401 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2402 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2405 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2406 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2407 /// element of vector 2 and the other elements to come from vector 1 in order.
2408 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2409 bool V2IsSplat = false,
2410 bool V2IsUndef = false) {
2411 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2414 if (!isUndefOrEqual(Ops[0], 0))
2417 for (unsigned i = 1; i < NumOps; ++i) {
2418 SDValue Arg = Ops[i];
2419 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2420 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2421 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2428 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2429 bool V2IsUndef = false) {
2430 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2431 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2432 V2IsSplat, V2IsUndef);
2435 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2436 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2437 bool X86::isMOVSHDUPMask(SDNode *N) {
2438 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2440 if (N->getNumOperands() != 4)
2443 // Expect 1, 1, 3, 3
2444 for (unsigned i = 0; i < 2; ++i) {
2445 SDValue Arg = N->getOperand(i);
2446 if (Arg.getOpcode() == ISD::UNDEF) continue;
2447 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2448 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2449 if (Val != 1) return false;
2453 for (unsigned i = 2; i < 4; ++i) {
2454 SDValue Arg = N->getOperand(i);
2455 if (Arg.getOpcode() == ISD::UNDEF) continue;
2456 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2457 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2458 if (Val != 3) return false;
2462 // Don't use movshdup if it can be done with a shufps.
2466 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2467 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2468 bool X86::isMOVSLDUPMask(SDNode *N) {
2469 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2471 if (N->getNumOperands() != 4)
2474 // Expect 0, 0, 2, 2
2475 for (unsigned i = 0; i < 2; ++i) {
2476 SDValue Arg = N->getOperand(i);
2477 if (Arg.getOpcode() == ISD::UNDEF) continue;
2478 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2479 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2480 if (Val != 0) return false;
2484 for (unsigned i = 2; i < 4; ++i) {
2485 SDValue Arg = N->getOperand(i);
2486 if (Arg.getOpcode() == ISD::UNDEF) continue;
2487 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2488 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2489 if (Val != 2) return false;
2493 // Don't use movshdup if it can be done with a shufps.
2497 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2498 /// specifies a identity operation on the LHS or RHS.
2499 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2500 unsigned NumElems = N->getNumOperands();
2501 for (unsigned i = 0; i < NumElems; ++i)
2502 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2507 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2508 /// a splat of a single element.
2509 static bool isSplatMask(SDNode *N) {
2510 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2512 // This is a splat operation if each element of the permute is the same, and
2513 // if the value doesn't reference the second vector.
2514 unsigned NumElems = N->getNumOperands();
2515 SDValue ElementBase;
2517 for (; i != NumElems; ++i) {
2518 SDValue Elt = N->getOperand(i);
2519 if (isa<ConstantSDNode>(Elt)) {
2525 if (!ElementBase.getNode())
2528 for (; i != NumElems; ++i) {
2529 SDValue Arg = N->getOperand(i);
2530 if (Arg.getOpcode() == ISD::UNDEF) continue;
2531 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2532 if (Arg != ElementBase) return false;
2535 // Make sure it is a splat of the first vector operand.
2536 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2539 /// getSplatMaskEltNo - Given a splat mask, return the index to the element
2540 /// we want to splat.
2541 static SDValue getSplatMaskEltNo(SDNode *N) {
2542 assert(isSplatMask(N) && "Not a splat mask");
2543 unsigned NumElems = N->getNumOperands();
2544 SDValue ElementBase;
2546 for (; i != NumElems; ++i) {
2547 SDValue Elt = N->getOperand(i);
2548 if (isa<ConstantSDNode>(Elt))
2551 assert(0 && " No splat value found!");
2556 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2557 /// a splat of a single element and it's a 2 or 4 element mask.
2558 bool X86::isSplatMask(SDNode *N) {
2559 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2561 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2562 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2564 return ::isSplatMask(N);
2567 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2568 /// specifies a splat of zero element.
2569 bool X86::isSplatLoMask(SDNode *N) {
2570 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2572 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2573 if (!isUndefOrEqual(N->getOperand(i), 0))
2578 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2579 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2580 bool X86::isMOVDDUPMask(SDNode *N) {
2581 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2583 unsigned e = N->getNumOperands() / 2;
2584 for (unsigned i = 0; i < e; ++i)
2585 if (!isUndefOrEqual(N->getOperand(i), i))
2587 for (unsigned i = 0; i < e; ++i)
2588 if (!isUndefOrEqual(N->getOperand(e+i), i))
2593 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2594 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2596 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2597 unsigned NumOperands = N->getNumOperands();
2598 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2600 for (unsigned i = 0; i < NumOperands; ++i) {
2602 SDValue Arg = N->getOperand(NumOperands-i-1);
2603 if (Arg.getOpcode() != ISD::UNDEF)
2604 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2605 if (Val >= NumOperands) Val -= NumOperands;
2607 if (i != NumOperands - 1)
2614 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2615 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2617 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2619 // 8 nodes, but we only care about the last 4.
2620 for (unsigned i = 7; i >= 4; --i) {
2622 SDValue Arg = N->getOperand(i);
2623 if (Arg.getOpcode() != ISD::UNDEF)
2624 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2633 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2634 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2636 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2638 // 8 nodes, but we only care about the first 4.
2639 for (int i = 3; i >= 0; --i) {
2641 SDValue Arg = N->getOperand(i);
2642 if (Arg.getOpcode() != ISD::UNDEF)
2643 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2652 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2653 /// specifies a 8 element shuffle that can be broken into a pair of
2654 /// PSHUFHW and PSHUFLW.
2655 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2656 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2658 if (N->getNumOperands() != 8)
2661 // Lower quadword shuffled.
2662 for (unsigned i = 0; i != 4; ++i) {
2663 SDValue Arg = N->getOperand(i);
2664 if (Arg.getOpcode() == ISD::UNDEF) continue;
2665 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2666 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2671 // Upper quadword shuffled.
2672 for (unsigned i = 4; i != 8; ++i) {
2673 SDValue Arg = N->getOperand(i);
2674 if (Arg.getOpcode() == ISD::UNDEF) continue;
2675 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2676 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2677 if (Val < 4 || Val > 7)
2684 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2685 /// values in ther permute mask.
2686 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2687 SDValue &V2, SDValue &Mask,
2688 SelectionDAG &DAG) {
2689 MVT VT = Op.getValueType();
2690 MVT MaskVT = Mask.getValueType();
2691 MVT EltVT = MaskVT.getVectorElementType();
2692 unsigned NumElems = Mask.getNumOperands();
2693 SmallVector<SDValue, 8> MaskVec;
2695 for (unsigned i = 0; i != NumElems; ++i) {
2696 SDValue Arg = Mask.getOperand(i);
2697 if (Arg.getOpcode() == ISD::UNDEF) {
2698 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2701 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2702 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2704 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2706 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2710 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2711 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2714 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2715 /// the two vector operands have swapped position.
2717 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
2718 MVT MaskVT = Mask.getValueType();
2719 MVT EltVT = MaskVT.getVectorElementType();
2720 unsigned NumElems = Mask.getNumOperands();
2721 SmallVector<SDValue, 8> MaskVec;
2722 for (unsigned i = 0; i != NumElems; ++i) {
2723 SDValue Arg = Mask.getOperand(i);
2724 if (Arg.getOpcode() == ISD::UNDEF) {
2725 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2728 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2729 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2731 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2733 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2735 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2739 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2740 /// match movhlps. The lower half elements should come from upper half of
2741 /// V1 (and in order), and the upper half elements should come from the upper
2742 /// half of V2 (and in order).
2743 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2744 unsigned NumElems = Mask->getNumOperands();
2747 for (unsigned i = 0, e = 2; i != e; ++i)
2748 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2750 for (unsigned i = 2; i != 4; ++i)
2751 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2756 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2757 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2759 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2760 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2762 N = N->getOperand(0).getNode();
2763 if (!ISD::isNON_EXTLoad(N))
2766 *LD = cast<LoadSDNode>(N);
2770 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2771 /// match movlp{s|d}. The lower half elements should come from lower half of
2772 /// V1 (and in order), and the upper half elements should come from the upper
2773 /// half of V2 (and in order). And since V1 will become the source of the
2774 /// MOVLP, it must be either a vector load or a scalar load to vector.
2775 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2776 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2778 // Is V2 is a vector load, don't do this transformation. We will try to use
2779 // load folding shufps op.
2780 if (ISD::isNON_EXTLoad(V2))
2783 unsigned NumElems = Mask->getNumOperands();
2784 if (NumElems != 2 && NumElems != 4)
2786 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2787 if (!isUndefOrEqual(Mask->getOperand(i), i))
2789 for (unsigned i = NumElems/2; i != NumElems; ++i)
2790 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2795 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2797 static bool isSplatVector(SDNode *N) {
2798 if (N->getOpcode() != ISD::BUILD_VECTOR)
2801 SDValue SplatValue = N->getOperand(0);
2802 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2803 if (N->getOperand(i) != SplatValue)
2808 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2810 static bool isUndefShuffle(SDNode *N) {
2811 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2814 SDValue V1 = N->getOperand(0);
2815 SDValue V2 = N->getOperand(1);
2816 SDValue Mask = N->getOperand(2);
2817 unsigned NumElems = Mask.getNumOperands();
2818 for (unsigned i = 0; i != NumElems; ++i) {
2819 SDValue Arg = Mask.getOperand(i);
2820 if (Arg.getOpcode() != ISD::UNDEF) {
2821 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2822 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2824 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2831 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2833 static inline bool isZeroNode(SDValue Elt) {
2834 return ((isa<ConstantSDNode>(Elt) &&
2835 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2836 (isa<ConstantFPSDNode>(Elt) &&
2837 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2840 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2841 /// to an zero vector.
2842 static bool isZeroShuffle(SDNode *N) {
2843 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2846 SDValue V1 = N->getOperand(0);
2847 SDValue V2 = N->getOperand(1);
2848 SDValue Mask = N->getOperand(2);
2849 unsigned NumElems = Mask.getNumOperands();
2850 for (unsigned i = 0; i != NumElems; ++i) {
2851 SDValue Arg = Mask.getOperand(i);
2852 if (Arg.getOpcode() == ISD::UNDEF)
2855 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2856 if (Idx < NumElems) {
2857 unsigned Opc = V1.getNode()->getOpcode();
2858 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2860 if (Opc != ISD::BUILD_VECTOR ||
2861 !isZeroNode(V1.getNode()->getOperand(Idx)))
2863 } else if (Idx >= NumElems) {
2864 unsigned Opc = V2.getNode()->getOpcode();
2865 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2867 if (Opc != ISD::BUILD_VECTOR ||
2868 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2875 /// getZeroVector - Returns a vector of specified type with all zero elements.
2877 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2878 assert(VT.isVector() && "Expected a vector type");
2880 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2881 // type. This ensures they get CSE'd.
2883 if (VT.getSizeInBits() == 64) { // MMX
2884 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2885 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2886 } else if (HasSSE2) { // SSE2
2887 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2888 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2890 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2891 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2893 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2896 /// getOnesVector - Returns a vector of specified type with all bits set.
2898 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
2899 assert(VT.isVector() && "Expected a vector type");
2901 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2902 // type. This ensures they get CSE'd.
2903 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2905 if (VT.getSizeInBits() == 64) // MMX
2906 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2908 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2909 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2913 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2914 /// that point to V2 points to its first element.
2915 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2916 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2918 bool Changed = false;
2919 SmallVector<SDValue, 8> MaskVec;
2920 unsigned NumElems = Mask.getNumOperands();
2921 for (unsigned i = 0; i != NumElems; ++i) {
2922 SDValue Arg = Mask.getOperand(i);
2923 if (Arg.getOpcode() != ISD::UNDEF) {
2924 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2925 if (Val > NumElems) {
2926 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2930 MaskVec.push_back(Arg);
2934 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2935 &MaskVec[0], MaskVec.size());
2939 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2940 /// operation of specified width.
2941 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2942 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2943 MVT BaseVT = MaskVT.getVectorElementType();
2945 SmallVector<SDValue, 8> MaskVec;
2946 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2947 for (unsigned i = 1; i != NumElems; ++i)
2948 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2949 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2952 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2953 /// of specified width.
2954 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2955 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2956 MVT BaseVT = MaskVT.getVectorElementType();
2957 SmallVector<SDValue, 8> MaskVec;
2958 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2959 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2960 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2962 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2965 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2966 /// of specified width.
2967 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2968 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2969 MVT BaseVT = MaskVT.getVectorElementType();
2970 unsigned Half = NumElems/2;
2971 SmallVector<SDValue, 8> MaskVec;
2972 for (unsigned i = 0; i != Half; ++i) {
2973 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2974 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2976 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2979 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2980 /// element #0 of a vector with the specified index, leaving the rest of the
2981 /// elements in place.
2982 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2983 SelectionDAG &DAG) {
2984 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2985 MVT BaseVT = MaskVT.getVectorElementType();
2986 SmallVector<SDValue, 8> MaskVec;
2987 // Element #0 of the result gets the elt we are replacing.
2988 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2989 for (unsigned i = 1; i != NumElems; ++i)
2990 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2991 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2994 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2995 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
2996 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2997 MVT VT = Op.getValueType();
3000 SDValue V1 = Op.getOperand(0);
3001 SDValue Mask = Op.getOperand(2);
3002 unsigned MaskNumElems = Mask.getNumOperands();
3003 unsigned NumElems = MaskNumElems;
3004 // Special handling of v4f32 -> v4i32.
3005 if (VT != MVT::v4f32) {
3006 // Find which element we want to splat.
3007 SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode();
3008 unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue();
3009 // unpack elements to the correct location
3010 while (NumElems > 4) {
3011 if (EltNo < NumElems/2) {
3012 Mask = getUnpacklMask(MaskNumElems, DAG);
3014 Mask = getUnpackhMask(MaskNumElems, DAG);
3015 EltNo -= NumElems/2;
3017 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
3020 SDValue Cst = DAG.getConstant(EltNo, MVT::i32);
3021 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
3024 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3025 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3026 DAG.getNode(ISD::UNDEF, PVT), Mask);
3027 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3030 /// isVectorLoad - Returns true if the node is a vector load, a scalar
3031 /// load that's promoted to vector, or a load bitcasted.
3032 static bool isVectorLoad(SDValue Op) {
3033 assert(Op.getValueType().isVector() && "Expected a vector type");
3034 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
3035 Op.getOpcode() == ISD::BIT_CONVERT) {
3036 return isa<LoadSDNode>(Op.getOperand(0));
3038 return isa<LoadSDNode>(Op);
3042 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
3044 static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
3045 SelectionDAG &DAG, bool HasSSE3) {
3046 // If we have sse3 and shuffle has more than one use or input is a load, then
3047 // use movddup. Otherwise, use movlhps.
3048 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
3049 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
3050 MVT VT = Op.getValueType();
3053 unsigned NumElems = PVT.getVectorNumElements();
3054 if (NumElems == 2) {
3055 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3056 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
3058 assert(NumElems == 4);
3059 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
3060 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
3061 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1);
3064 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3065 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3066 DAG.getNode(ISD::UNDEF, PVT), Mask);
3067 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3070 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3071 /// vector of zero or undef vector. This produces a shuffle where the low
3072 /// element of V2 is swizzled into the zero/undef vector, landing at element
3073 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3074 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3075 bool isZero, bool HasSSE2,
3076 SelectionDAG &DAG) {
3077 MVT VT = V2.getValueType();
3079 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
3080 unsigned NumElems = V2.getValueType().getVectorNumElements();
3081 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3082 MVT EVT = MaskVT.getVectorElementType();
3083 SmallVector<SDValue, 16> MaskVec;
3084 for (unsigned i = 0; i != NumElems; ++i)
3085 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
3086 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
3088 MaskVec.push_back(DAG.getConstant(i, EVT));
3089 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3090 &MaskVec[0], MaskVec.size());
3091 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3094 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3095 /// a shuffle that is zero.
3097 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
3098 unsigned NumElems, bool Low,
3099 SelectionDAG &DAG) {
3100 unsigned NumZeros = 0;
3101 for (unsigned i = 0; i < NumElems; ++i) {
3102 unsigned Index = Low ? i : NumElems-i-1;
3103 SDValue Idx = Mask.getOperand(Index);
3104 if (Idx.getOpcode() == ISD::UNDEF) {
3108 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3109 if (Elt.getNode() && isZeroNode(Elt))
3117 /// isVectorShift - Returns true if the shuffle can be implemented as a
3118 /// logical left or right shift of a vector.
3119 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3120 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3121 unsigned NumElems = Mask.getNumOperands();
3124 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3127 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3132 bool SeenV1 = false;
3133 bool SeenV2 = false;
3134 for (unsigned i = NumZeros; i < NumElems; ++i) {
3135 unsigned Val = isLeft ? (i - NumZeros) : i;
3136 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3137 if (Idx.getOpcode() == ISD::UNDEF)
3139 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3140 if (Index < NumElems)
3149 if (SeenV1 && SeenV2)
3152 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3158 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3160 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3161 unsigned NumNonZero, unsigned NumZero,
3162 SelectionDAG &DAG, TargetLowering &TLI) {
3168 for (unsigned i = 0; i < 16; ++i) {
3169 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3170 if (ThisIsNonZero && First) {
3172 V = getZeroVector(MVT::v8i16, true, DAG);
3174 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3179 SDValue ThisElt(0, 0), LastElt(0, 0);
3180 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3181 if (LastIsNonZero) {
3182 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3184 if (ThisIsNonZero) {
3185 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3186 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3187 ThisElt, DAG.getConstant(8, MVT::i8));
3189 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3193 if (ThisElt.getNode())
3194 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3195 DAG.getIntPtrConstant(i/2));
3199 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3202 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3204 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3205 unsigned NumNonZero, unsigned NumZero,
3206 SelectionDAG &DAG, TargetLowering &TLI) {
3212 for (unsigned i = 0; i < 8; ++i) {
3213 bool isNonZero = (NonZeros & (1 << i)) != 0;
3217 V = getZeroVector(MVT::v8i16, true, DAG);
3219 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3222 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3223 DAG.getIntPtrConstant(i));
3230 /// getVShift - Return a vector logical shift node.
3232 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3233 unsigned NumBits, SelectionDAG &DAG,
3234 const TargetLowering &TLI) {
3235 bool isMMX = VT.getSizeInBits() == 64;
3236 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3237 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3238 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3239 return DAG.getNode(ISD::BIT_CONVERT, VT,
3240 DAG.getNode(Opc, ShVT, SrcOp,
3241 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3245 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3246 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3247 if (ISD::isBuildVectorAllZeros(Op.getNode())
3248 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3249 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3250 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3251 // eliminated on x86-32 hosts.
3252 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3255 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3256 return getOnesVector(Op.getValueType(), DAG);
3257 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3260 MVT VT = Op.getValueType();
3261 MVT EVT = VT.getVectorElementType();
3262 unsigned EVTBits = EVT.getSizeInBits();
3264 unsigned NumElems = Op.getNumOperands();
3265 unsigned NumZero = 0;
3266 unsigned NumNonZero = 0;
3267 unsigned NonZeros = 0;
3268 bool IsAllConstants = true;
3269 SmallSet<SDValue, 8> Values;
3270 for (unsigned i = 0; i < NumElems; ++i) {
3271 SDValue Elt = Op.getOperand(i);
3272 if (Elt.getOpcode() == ISD::UNDEF)
3275 if (Elt.getOpcode() != ISD::Constant &&
3276 Elt.getOpcode() != ISD::ConstantFP)
3277 IsAllConstants = false;
3278 if (isZeroNode(Elt))
3281 NonZeros |= (1 << i);
3286 if (NumNonZero == 0) {
3287 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3288 return DAG.getNode(ISD::UNDEF, VT);
3291 // Special case for single non-zero, non-undef, element.
3292 if (NumNonZero == 1 && NumElems <= 4) {
3293 unsigned Idx = CountTrailingZeros_32(NonZeros);
3294 SDValue Item = Op.getOperand(Idx);
3296 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3297 // the value are obviously zero, truncate the value to i32 and do the
3298 // insertion that way. Only do this if the value is non-constant or if the
3299 // value is a constant being inserted into element 0. It is cheaper to do
3300 // a constant pool load than it is to do a movd + shuffle.
3301 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3302 (!IsAllConstants || Idx == 0)) {
3303 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3304 // Handle MMX and SSE both.
3305 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3306 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3308 // Truncate the value (which may itself be a constant) to i32, and
3309 // convert it to a vector with movd (S2V+shuffle to zero extend).
3310 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3311 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3312 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3313 Subtarget->hasSSE2(), DAG);
3315 // Now we have our 32-bit value zero extended in the low element of
3316 // a vector. If Idx != 0, swizzle it into place.
3319 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3320 getSwapEltZeroMask(VecElts, Idx, DAG)
3322 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3324 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3328 // If we have a constant or non-constant insertion into the low element of
3329 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3330 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3331 // depending on what the source datatype is. Because we can only get here
3332 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3334 // Don't do this for i64 values on x86-32.
3335 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3336 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3337 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3338 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3339 Subtarget->hasSSE2(), DAG);
3342 // Is it a vector logical left shift?
3343 if (NumElems == 2 && Idx == 1 &&
3344 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3345 unsigned NumBits = VT.getSizeInBits();
3346 return getVShift(true, VT,
3347 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3348 NumBits/2, DAG, *this);
3351 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3354 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3355 // is a non-constant being inserted into an element other than the low one,
3356 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3357 // movd/movss) to move this into the low element, then shuffle it into
3359 if (EVTBits == 32) {
3360 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3362 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3363 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3364 Subtarget->hasSSE2(), DAG);
3365 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3366 MVT MaskEVT = MaskVT.getVectorElementType();
3367 SmallVector<SDValue, 8> MaskVec;
3368 for (unsigned i = 0; i < NumElems; i++)
3369 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3370 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3371 &MaskVec[0], MaskVec.size());
3372 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3373 DAG.getNode(ISD::UNDEF, VT), Mask);
3377 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3378 if (Values.size() == 1)
3381 // A vector full of immediates; various special cases are already
3382 // handled, so this is best done with a single constant-pool load.
3386 // Let legalizer expand 2-wide build_vectors.
3387 if (EVTBits == 64) {
3388 if (NumNonZero == 1) {
3389 // One half is zero or undef.
3390 unsigned Idx = CountTrailingZeros_32(NonZeros);
3391 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3392 Op.getOperand(Idx));
3393 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3394 Subtarget->hasSSE2(), DAG);
3399 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3400 if (EVTBits == 8 && NumElems == 16) {
3401 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3403 if (V.getNode()) return V;
3406 if (EVTBits == 16 && NumElems == 8) {
3407 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3409 if (V.getNode()) return V;
3412 // If element VT is == 32 bits, turn it into a number of shuffles.
3413 SmallVector<SDValue, 8> V;
3415 if (NumElems == 4 && NumZero > 0) {
3416 for (unsigned i = 0; i < 4; ++i) {
3417 bool isZero = !(NonZeros & (1 << i));
3419 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3421 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3424 for (unsigned i = 0; i < 2; ++i) {
3425 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3428 V[i] = V[i*2]; // Must be a zero vector.
3431 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3432 getMOVLMask(NumElems, DAG));
3435 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3436 getMOVLMask(NumElems, DAG));
3439 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3440 getUnpacklMask(NumElems, DAG));
3445 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3446 MVT EVT = MaskVT.getVectorElementType();
3447 SmallVector<SDValue, 8> MaskVec;
3448 bool Reverse = (NonZeros & 0x3) == 2;
3449 for (unsigned i = 0; i < 2; ++i)
3451 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3453 MaskVec.push_back(DAG.getConstant(i, EVT));
3454 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3455 for (unsigned i = 0; i < 2; ++i)
3457 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3459 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3460 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3461 &MaskVec[0], MaskVec.size());
3462 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3465 if (Values.size() > 2) {
3466 // Expand into a number of unpckl*.
3468 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3469 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3470 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3471 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
3472 for (unsigned i = 0; i < NumElems; ++i)
3473 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3475 while (NumElems != 0) {
3476 for (unsigned i = 0; i < NumElems; ++i)
3477 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3488 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3489 SDValue PermMask, SelectionDAG &DAG,
3490 TargetLowering &TLI) {
3492 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3493 MVT MaskEVT = MaskVT.getVectorElementType();
3494 MVT PtrVT = TLI.getPointerTy();
3495 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3496 PermMask.getNode()->op_end());
3498 // First record which half of which vector the low elements come from.
3499 SmallVector<unsigned, 4> LowQuad(4);
3500 for (unsigned i = 0; i < 4; ++i) {
3501 SDValue Elt = MaskElts[i];
3502 if (Elt.getOpcode() == ISD::UNDEF)
3504 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3505 int QuadIdx = EltIdx / 4;
3509 int BestLowQuad = -1;
3510 unsigned MaxQuad = 1;
3511 for (unsigned i = 0; i < 4; ++i) {
3512 if (LowQuad[i] > MaxQuad) {
3514 MaxQuad = LowQuad[i];
3518 // Record which half of which vector the high elements come from.
3519 SmallVector<unsigned, 4> HighQuad(4);
3520 for (unsigned i = 4; i < 8; ++i) {
3521 SDValue Elt = MaskElts[i];
3522 if (Elt.getOpcode() == ISD::UNDEF)
3524 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3525 int QuadIdx = EltIdx / 4;
3526 ++HighQuad[QuadIdx];
3529 int BestHighQuad = -1;
3531 for (unsigned i = 0; i < 4; ++i) {
3532 if (HighQuad[i] > MaxQuad) {
3534 MaxQuad = HighQuad[i];
3538 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3539 if (BestLowQuad != -1 || BestHighQuad != -1) {
3540 // First sort the 4 chunks in order using shufpd.
3541 SmallVector<SDValue, 8> MaskVec;
3543 if (BestLowQuad != -1)
3544 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3546 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3548 if (BestHighQuad != -1)
3549 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3551 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3553 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3554 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3555 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3556 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3557 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3559 // Now sort high and low parts separately.
3560 BitVector InOrder(8);
3561 if (BestLowQuad != -1) {
3562 // Sort lower half in order using PSHUFLW.
3564 bool AnyOutOrder = false;
3566 for (unsigned i = 0; i != 4; ++i) {
3567 SDValue Elt = MaskElts[i];
3568 if (Elt.getOpcode() == ISD::UNDEF) {
3569 MaskVec.push_back(Elt);
3572 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3576 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3578 // If this element is in the right place after this shuffle, then
3580 if ((int)(EltIdx / 4) == BestLowQuad)
3585 for (unsigned i = 4; i != 8; ++i)
3586 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3587 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3588 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3592 if (BestHighQuad != -1) {
3593 // Sort high half in order using PSHUFHW if possible.
3596 for (unsigned i = 0; i != 4; ++i)
3597 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3599 bool AnyOutOrder = false;
3600 for (unsigned i = 4; i != 8; ++i) {
3601 SDValue Elt = MaskElts[i];
3602 if (Elt.getOpcode() == ISD::UNDEF) {
3603 MaskVec.push_back(Elt);
3606 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3610 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3612 // If this element is in the right place after this shuffle, then
3614 if ((int)(EltIdx / 4) == BestHighQuad)
3620 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3621 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3625 // The other elements are put in the right place using pextrw and pinsrw.
3626 for (unsigned i = 0; i != 8; ++i) {
3629 SDValue Elt = MaskElts[i];
3630 if (Elt.getOpcode() == ISD::UNDEF)
3632 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3633 SDValue ExtOp = (EltIdx < 8)
3634 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3635 DAG.getConstant(EltIdx, PtrVT))
3636 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3637 DAG.getConstant(EltIdx - 8, PtrVT));
3638 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3639 DAG.getConstant(i, PtrVT));
3645 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3646 // few as possible. First, let's find out how many elements are already in the
3648 unsigned V1InOrder = 0;
3649 unsigned V1FromV1 = 0;
3650 unsigned V2InOrder = 0;
3651 unsigned V2FromV2 = 0;
3652 SmallVector<SDValue, 8> V1Elts;
3653 SmallVector<SDValue, 8> V2Elts;
3654 for (unsigned i = 0; i < 8; ++i) {
3655 SDValue Elt = MaskElts[i];
3656 if (Elt.getOpcode() == ISD::UNDEF) {
3657 V1Elts.push_back(Elt);
3658 V2Elts.push_back(Elt);
3663 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3665 V1Elts.push_back(Elt);
3666 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3668 } else if (EltIdx == i+8) {
3669 V1Elts.push_back(Elt);
3670 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3672 } else if (EltIdx < 8) {
3673 V1Elts.push_back(Elt);
3674 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3677 V1Elts.push_back(Elt);
3678 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3683 if (V2InOrder > V1InOrder) {
3684 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3686 std::swap(V1Elts, V2Elts);
3687 std::swap(V1FromV1, V2FromV2);
3690 if ((V1FromV1 + V1InOrder) != 8) {
3691 // Some elements are from V2.
3693 // If there are elements that are from V1 but out of place,
3694 // then first sort them in place
3695 SmallVector<SDValue, 8> MaskVec;
3696 for (unsigned i = 0; i < 8; ++i) {
3697 SDValue Elt = V1Elts[i];
3698 if (Elt.getOpcode() == ISD::UNDEF) {
3699 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3702 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3704 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3706 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3708 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3709 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3713 for (unsigned i = 0; i < 8; ++i) {
3714 SDValue Elt = V1Elts[i];
3715 if (Elt.getOpcode() == ISD::UNDEF)
3717 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3720 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3721 DAG.getConstant(EltIdx - 8, PtrVT));
3722 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3723 DAG.getConstant(i, PtrVT));
3727 // All elements are from V1.
3729 for (unsigned i = 0; i < 8; ++i) {
3730 SDValue Elt = V1Elts[i];
3731 if (Elt.getOpcode() == ISD::UNDEF)
3733 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3734 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3735 DAG.getConstant(EltIdx, PtrVT));
3736 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3737 DAG.getConstant(i, PtrVT));
3743 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3744 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3745 /// done when every pair / quad of shuffle mask elements point to elements in
3746 /// the right sequence. e.g.
3747 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3749 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3751 SDValue PermMask, SelectionDAG &DAG,
3752 TargetLowering &TLI) {
3753 unsigned NumElems = PermMask.getNumOperands();
3754 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3755 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3756 MVT MaskEltVT = MaskVT.getVectorElementType();
3758 switch (VT.getSimpleVT()) {
3759 default: assert(false && "Unexpected!");
3760 case MVT::v4f32: NewVT = MVT::v2f64; break;
3761 case MVT::v4i32: NewVT = MVT::v2i64; break;
3762 case MVT::v8i16: NewVT = MVT::v4i32; break;
3763 case MVT::v16i8: NewVT = MVT::v4i32; break;
3766 if (NewWidth == 2) {
3772 unsigned Scale = NumElems / NewWidth;
3773 SmallVector<SDValue, 8> MaskVec;
3774 for (unsigned i = 0; i < NumElems; i += Scale) {
3775 unsigned StartIdx = ~0U;
3776 for (unsigned j = 0; j < Scale; ++j) {
3777 SDValue Elt = PermMask.getOperand(i+j);
3778 if (Elt.getOpcode() == ISD::UNDEF)
3780 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3781 if (StartIdx == ~0U)
3782 StartIdx = EltIdx - (EltIdx % Scale);
3783 if (EltIdx != StartIdx + j)
3786 if (StartIdx == ~0U)
3787 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
3789 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3792 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3793 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3794 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3795 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3796 &MaskVec[0], MaskVec.size()));
3799 /// getVZextMovL - Return a zero-extending vector move low node.
3801 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3802 SDValue SrcOp, SelectionDAG &DAG,
3803 const X86Subtarget *Subtarget) {
3804 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3805 LoadSDNode *LD = NULL;
3806 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3807 LD = dyn_cast<LoadSDNode>(SrcOp);
3809 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3811 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3812 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3813 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3814 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3815 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3817 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3818 return DAG.getNode(ISD::BIT_CONVERT, VT,
3819 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3820 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3827 return DAG.getNode(ISD::BIT_CONVERT, VT,
3828 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3829 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3832 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3835 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3836 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
3837 MVT MaskVT = PermMask.getValueType();
3838 MVT MaskEVT = MaskVT.getVectorElementType();
3839 SmallVector<std::pair<int, int>, 8> Locs;
3841 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3844 for (unsigned i = 0; i != 4; ++i) {
3845 SDValue Elt = PermMask.getOperand(i);
3846 if (Elt.getOpcode() == ISD::UNDEF) {
3847 Locs[i] = std::make_pair(-1, -1);
3849 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3850 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3852 Locs[i] = std::make_pair(0, NumLo);
3856 Locs[i] = std::make_pair(1, NumHi);
3858 Mask1[2+NumHi] = Elt;
3864 if (NumLo <= 2 && NumHi <= 2) {
3865 // If no more than two elements come from either vector. This can be
3866 // implemented with two shuffles. First shuffle gather the elements.
3867 // The second shuffle, which takes the first shuffle as both of its
3868 // vector operands, put the elements into the right order.
3869 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3870 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3871 &Mask1[0], Mask1.size()));
3873 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3874 for (unsigned i = 0; i != 4; ++i) {
3875 if (Locs[i].first == -1)
3878 unsigned Idx = (i < 2) ? 0 : 4;
3879 Idx += Locs[i].first * 2 + Locs[i].second;
3880 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3884 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3885 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3886 &Mask2[0], Mask2.size()));
3887 } else if (NumLo == 3 || NumHi == 3) {
3888 // Otherwise, we must have three elements from one vector, call it X, and
3889 // one element from the other, call it Y. First, use a shufps to build an
3890 // intermediate vector with the one element from Y and the element from X
3891 // that will be in the same half in the final destination (the indexes don't
3892 // matter). Then, use a shufps to build the final vector, taking the half
3893 // containing the element from Y from the intermediate, and the other half
3896 // Normalize it so the 3 elements come from V1.
3897 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3901 // Find the element from V2.
3903 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3904 SDValue Elt = PermMask.getOperand(HiIndex);
3905 if (Elt.getOpcode() == ISD::UNDEF)
3907 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3912 Mask1[0] = PermMask.getOperand(HiIndex);
3913 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3914 Mask1[2] = PermMask.getOperand(HiIndex^1);
3915 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3916 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3917 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3920 Mask1[0] = PermMask.getOperand(0);
3921 Mask1[1] = PermMask.getOperand(1);
3922 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3923 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3924 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3925 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3927 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3928 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3929 Mask1[2] = PermMask.getOperand(2);
3930 Mask1[3] = PermMask.getOperand(3);
3931 if (Mask1[2].getOpcode() != ISD::UNDEF)
3933 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
3935 if (Mask1[3].getOpcode() != ISD::UNDEF)
3937 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
3939 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3940 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3944 // Break it into (shuffle shuffle_hi, shuffle_lo).
3946 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3947 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3948 SmallVector<SDValue,8> *MaskPtr = &LoMask;
3949 unsigned MaskIdx = 0;
3952 for (unsigned i = 0; i != 4; ++i) {
3959 SDValue Elt = PermMask.getOperand(i);
3960 if (Elt.getOpcode() == ISD::UNDEF) {
3961 Locs[i] = std::make_pair(-1, -1);
3962 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
3963 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3964 (*MaskPtr)[LoIdx] = Elt;
3967 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3968 (*MaskPtr)[HiIdx] = Elt;
3973 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3974 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3975 &LoMask[0], LoMask.size()));
3976 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3977 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3978 &HiMask[0], HiMask.size()));
3979 SmallVector<SDValue, 8> MaskOps;
3980 for (unsigned i = 0; i != 4; ++i) {
3981 if (Locs[i].first == -1) {
3982 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3984 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3985 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3988 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3989 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3990 &MaskOps[0], MaskOps.size()));
3994 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3995 SDValue V1 = Op.getOperand(0);
3996 SDValue V2 = Op.getOperand(1);
3997 SDValue PermMask = Op.getOperand(2);
3998 MVT VT = Op.getValueType();
3999 unsigned NumElems = PermMask.getNumOperands();
4000 bool isMMX = VT.getSizeInBits() == 64;
4001 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4002 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4003 bool V1IsSplat = false;
4004 bool V2IsSplat = false;
4006 if (isUndefShuffle(Op.getNode()))
4007 return DAG.getNode(ISD::UNDEF, VT);
4009 if (isZeroShuffle(Op.getNode()))
4010 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
4012 if (isIdentityMask(PermMask.getNode()))
4014 else if (isIdentityMask(PermMask.getNode(), true))
4017 // Canonicalize movddup shuffles.
4018 if (V2IsUndef && Subtarget->hasSSE2() &&
4019 VT.getSizeInBits() == 128 &&
4020 X86::isMOVDDUPMask(PermMask.getNode()))
4021 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
4023 if (isSplatMask(PermMask.getNode())) {
4024 if (isMMX || NumElems < 4) return Op;
4025 // Promote it to a v4{if}32 splat.
4026 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
4029 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4031 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4032 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
4033 if (NewOp.getNode())
4034 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
4035 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4036 // FIXME: Figure out a cleaner way to do this.
4037 // Try to make use of movq to zero out the top part.
4038 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4039 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4041 if (NewOp.getNode()) {
4042 SDValue NewV1 = NewOp.getOperand(0);
4043 SDValue NewV2 = NewOp.getOperand(1);
4044 SDValue NewMask = NewOp.getOperand(2);
4045 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
4046 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
4047 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
4050 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4051 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4053 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
4054 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4059 // Check if this can be converted into a logical shift.
4060 bool isLeft = false;
4063 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
4064 if (isShift && ShVal.hasOneUse()) {
4065 // If the shifted value has multiple uses, it may be cheaper to use
4066 // v_set0 + movlhps or movhlps, etc.
4067 MVT EVT = VT.getVectorElementType();
4068 ShAmt *= EVT.getSizeInBits();
4069 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4072 if (X86::isMOVLMask(PermMask.getNode())) {
4075 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4076 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
4081 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
4082 X86::isMOVSLDUPMask(PermMask.getNode()) ||
4083 X86::isMOVHLPSMask(PermMask.getNode()) ||
4084 X86::isMOVHPMask(PermMask.getNode()) ||
4085 X86::isMOVLPMask(PermMask.getNode())))
4088 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
4089 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
4090 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4093 // No better options. Use a vshl / vsrl.
4094 MVT EVT = VT.getVectorElementType();
4095 ShAmt *= EVT.getSizeInBits();
4096 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4099 bool Commuted = false;
4100 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4101 // 1,1,1,1 -> v8i16 though.
4102 V1IsSplat = isSplatVector(V1.getNode());
4103 V2IsSplat = isSplatVector(V2.getNode());
4105 // Canonicalize the splat or undef, if present, to be on the RHS.
4106 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4107 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4108 std::swap(V1IsSplat, V2IsSplat);
4109 std::swap(V1IsUndef, V2IsUndef);
4113 // FIXME: Figure out a cleaner way to do this.
4114 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
4115 if (V2IsUndef) return V1;
4116 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4118 // V2 is a splat, so the mask may be malformed. That is, it may point
4119 // to any V2 element. The instruction selectior won't like this. Get
4120 // a corrected mask and commute to form a proper MOVS{S|D}.
4121 SDValue NewMask = getMOVLMask(NumElems, DAG);
4122 if (NewMask.getNode() != PermMask.getNode())
4123 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4128 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4129 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4130 X86::isUNPCKLMask(PermMask.getNode()) ||
4131 X86::isUNPCKHMask(PermMask.getNode()))
4135 // Normalize mask so all entries that point to V2 points to its first
4136 // element then try to match unpck{h|l} again. If match, return a
4137 // new vector_shuffle with the corrected mask.
4138 SDValue NewMask = NormalizeMask(PermMask, DAG);
4139 if (NewMask.getNode() != PermMask.getNode()) {
4140 if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
4141 SDValue NewMask = getUnpacklMask(NumElems, DAG);
4142 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4143 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
4144 SDValue NewMask = getUnpackhMask(NumElems, DAG);
4145 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4150 // Normalize the node to match x86 shuffle ops if needed
4151 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4152 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4155 // Commute is back and try unpck* again.
4156 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4157 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4158 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4159 X86::isUNPCKLMask(PermMask.getNode()) ||
4160 X86::isUNPCKHMask(PermMask.getNode()))
4164 // Try PSHUF* first, then SHUFP*.
4165 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4166 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4167 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4168 if (V2.getOpcode() != ISD::UNDEF)
4169 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
4170 DAG.getNode(ISD::UNDEF, VT), PermMask);
4175 if (Subtarget->hasSSE2() &&
4176 (X86::isPSHUFDMask(PermMask.getNode()) ||
4177 X86::isPSHUFHWMask(PermMask.getNode()) ||
4178 X86::isPSHUFLWMask(PermMask.getNode()))) {
4180 if (VT == MVT::v4f32) {
4182 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4183 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4184 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4185 } else if (V2.getOpcode() != ISD::UNDEF)
4186 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4187 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4189 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
4193 // Binary or unary shufps.
4194 if (X86::isSHUFPMask(PermMask.getNode()) ||
4195 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4199 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4200 if (VT == MVT::v8i16) {
4201 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
4202 if (NewOp.getNode())
4206 // Handle all 4 wide cases with a number of shuffles except for MMX.
4207 if (NumElems == 4 && !isMMX)
4208 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
4214 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4215 SelectionDAG &DAG) {
4216 MVT VT = Op.getValueType();
4217 if (VT.getSizeInBits() == 8) {
4218 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
4219 Op.getOperand(0), Op.getOperand(1));
4220 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4221 DAG.getValueType(VT));
4222 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4223 } else if (VT.getSizeInBits() == 16) {
4224 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4225 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4227 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4228 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4229 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
4232 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
4233 Op.getOperand(0), Op.getOperand(1));
4234 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4235 DAG.getValueType(VT));
4236 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4237 } else if (VT == MVT::f32) {
4238 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4239 // the result back to FR32 register. It's only worth matching if the
4240 // result has a single use which is a store or a bitcast to i32. And in
4241 // the case of a store, it's not worth it if the index is a constant 0,
4242 // because a MOVSSmr can be used instead, which is smaller and faster.
4243 if (!Op.hasOneUse())
4245 SDNode *User = *Op.getNode()->use_begin();
4246 if ((User->getOpcode() != ISD::STORE ||
4247 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4248 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4249 (User->getOpcode() != ISD::BIT_CONVERT ||
4250 User->getValueType(0) != MVT::i32))
4252 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4253 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4255 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
4256 } else if (VT == MVT::i32) {
4257 // ExtractPS works with constant index.
4258 if (isa<ConstantSDNode>(Op.getOperand(1)))
4266 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4267 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4270 if (Subtarget->hasSSE41()) {
4271 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4276 MVT VT = Op.getValueType();
4277 // TODO: handle v16i8.
4278 if (VT.getSizeInBits() == 16) {
4279 SDValue Vec = Op.getOperand(0);
4280 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4282 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4283 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4284 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4286 // Transform it so it match pextrw which produces a 32-bit result.
4287 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4288 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4289 Op.getOperand(0), Op.getOperand(1));
4290 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4291 DAG.getValueType(VT));
4292 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4293 } else if (VT.getSizeInBits() == 32) {
4294 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4297 // SHUFPS the element to the lowest double word, then movss.
4298 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4299 SmallVector<SDValue, 8> IdxVec;
4301 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4303 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4305 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4307 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4308 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4309 &IdxVec[0], IdxVec.size());
4310 SDValue Vec = Op.getOperand(0);
4311 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4312 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4314 DAG.getIntPtrConstant(0));
4315 } else if (VT.getSizeInBits() == 64) {
4316 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4317 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4318 // to match extract_elt for f64.
4319 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4323 // UNPCKHPD the element to the lowest double word, then movsd.
4324 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4325 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4326 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4327 SmallVector<SDValue, 8> IdxVec;
4328 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4330 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4331 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4332 &IdxVec[0], IdxVec.size());
4333 SDValue Vec = Op.getOperand(0);
4334 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4335 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4336 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4337 DAG.getIntPtrConstant(0));
4344 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4345 MVT VT = Op.getValueType();
4346 MVT EVT = VT.getVectorElementType();
4348 SDValue N0 = Op.getOperand(0);
4349 SDValue N1 = Op.getOperand(1);
4350 SDValue N2 = Op.getOperand(2);
4352 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4353 isa<ConstantSDNode>(N2)) {
4354 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4356 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4358 if (N1.getValueType() != MVT::i32)
4359 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4360 if (N2.getValueType() != MVT::i32)
4361 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4362 return DAG.getNode(Opc, VT, N0, N1, N2);
4363 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4364 // Bits [7:6] of the constant are the source select. This will always be
4365 // zero here. The DAG Combiner may combine an extract_elt index into these
4366 // bits. For example (insert (extract, 3), 2) could be matched by putting
4367 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4368 // Bits [5:4] of the constant are the destination select. This is the
4369 // value of the incoming immediate.
4370 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4371 // combine either bitwise AND or insert of float 0.0 to set these bits.
4372 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4373 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4374 } else if (EVT == MVT::i32) {
4375 // InsertPS works with constant index.
4376 if (isa<ConstantSDNode>(N2))
4383 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4384 MVT VT = Op.getValueType();
4385 MVT EVT = VT.getVectorElementType();
4387 if (Subtarget->hasSSE41())
4388 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4393 SDValue N0 = Op.getOperand(0);
4394 SDValue N1 = Op.getOperand(1);
4395 SDValue N2 = Op.getOperand(2);
4397 if (EVT.getSizeInBits() == 16) {
4398 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4399 // as its second argument.
4400 if (N1.getValueType() != MVT::i32)
4401 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4402 if (N2.getValueType() != MVT::i32)
4403 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4404 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4410 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4411 if (Op.getValueType() == MVT::v2f32)
4412 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4413 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4414 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4415 Op.getOperand(0))));
4417 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4418 MVT VT = MVT::v2i32;
4419 switch (Op.getValueType().getSimpleVT()) {
4426 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4427 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4430 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4431 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4432 // one of the above mentioned nodes. It has to be wrapped because otherwise
4433 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4434 // be used to form addressing mode. These wrapped nodes will be selected
4437 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4438 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4439 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4441 CP->getAlignment());
4442 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4443 // With PIC, the address is actually $g + Offset.
4444 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4445 !Subtarget->isPICStyleRIPRel()) {
4446 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4447 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4455 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV,
4457 SelectionDAG &DAG) const {
4458 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4459 bool ExtraLoadRequired =
4460 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4462 // Create the TargetGlobalAddress node, folding in the constant
4463 // offset if it is legal.
4465 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
4466 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4469 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
4470 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4472 // With PIC, the address is actually $g + Offset.
4473 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4474 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4475 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4479 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4480 // load the value at address GV, not the value of GV itself. This means that
4481 // the GlobalAddress must be in the base or index register of the address, not
4482 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4483 // The same applies for external symbols during PIC codegen
4484 if (ExtraLoadRequired)
4485 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4486 PseudoSourceValue::getGOT(), 0);
4488 // If there was a non-zero offset that we didn't fold, create an explicit
4491 Result = DAG.getNode(ISD::ADD, getPointerTy(), Result,
4492 DAG.getConstant(Offset, getPointerTy()));
4498 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4499 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4500 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4501 return LowerGlobalAddress(GV, Offset, DAG);
4504 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4506 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4509 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4510 DAG.getNode(X86ISD::GlobalBaseReg,
4512 InFlag = Chain.getValue(1);
4514 // emit leal symbol@TLSGD(,%ebx,1), %eax
4515 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4516 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4517 GA->getValueType(0),
4519 SDValue Ops[] = { Chain, TGA, InFlag };
4520 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4521 InFlag = Result.getValue(2);
4522 Chain = Result.getValue(1);
4524 // call ___tls_get_addr. This function receives its argument in
4525 // the register EAX.
4526 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4527 InFlag = Chain.getValue(1);
4529 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4530 SDValue Ops1[] = { Chain,
4531 DAG.getTargetExternalSymbol("___tls_get_addr",
4533 DAG.getRegister(X86::EAX, PtrVT),
4534 DAG.getRegister(X86::EBX, PtrVT),
4536 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4537 InFlag = Chain.getValue(1);
4539 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4542 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4544 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4546 SDValue InFlag, Chain;
4548 // emit leaq symbol@TLSGD(%rip), %rdi
4549 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4550 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4551 GA->getValueType(0),
4553 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4554 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4555 Chain = Result.getValue(1);
4556 InFlag = Result.getValue(2);
4558 // call __tls_get_addr. This function receives its argument in
4559 // the register RDI.
4560 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4561 InFlag = Chain.getValue(1);
4563 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4564 SDValue Ops1[] = { Chain,
4565 DAG.getTargetExternalSymbol("__tls_get_addr",
4567 DAG.getRegister(X86::RDI, PtrVT),
4569 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4570 InFlag = Chain.getValue(1);
4572 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4575 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4576 // "local exec" model.
4577 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4579 // Get the Thread Pointer
4580 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4581 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4583 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4584 GA->getValueType(0),
4586 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4588 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4589 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4590 PseudoSourceValue::getGOT(), 0);
4592 // The address of the thread local variable is the add of the thread
4593 // pointer with the offset of the variable.
4594 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4598 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4599 // TODO: implement the "local dynamic" model
4600 // TODO: implement the "initial exec"model for pic executables
4601 assert(Subtarget->isTargetELF() &&
4602 "TLS not implemented for non-ELF targets");
4603 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4604 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4605 // otherwise use the "Local Exec"TLS Model
4606 if (Subtarget->is64Bit()) {
4607 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4609 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4610 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4612 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4617 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4618 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4619 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4620 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4621 // With PIC, the address is actually $g + Offset.
4622 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4623 !Subtarget->isPICStyleRIPRel()) {
4624 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4625 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4632 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4633 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4634 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4635 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4636 // With PIC, the address is actually $g + Offset.
4637 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4638 !Subtarget->isPICStyleRIPRel()) {
4639 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4640 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4647 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4648 /// take a 2 x i32 value to shift plus a shift amount.
4649 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4650 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4651 MVT VT = Op.getValueType();
4652 unsigned VTBits = VT.getSizeInBits();
4653 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4654 SDValue ShOpLo = Op.getOperand(0);
4655 SDValue ShOpHi = Op.getOperand(1);
4656 SDValue ShAmt = Op.getOperand(2);
4657 SDValue Tmp1 = isSRA ?
4658 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4659 DAG.getConstant(0, VT);
4662 if (Op.getOpcode() == ISD::SHL_PARTS) {
4663 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4664 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4666 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4667 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4670 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4671 DAG.getConstant(VTBits, MVT::i8));
4672 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
4673 AndNode, DAG.getConstant(0, MVT::i8));
4676 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4677 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4678 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4680 if (Op.getOpcode() == ISD::SHL_PARTS) {
4681 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4682 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4684 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4685 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4688 SDValue Ops[2] = { Lo, Hi };
4689 return DAG.getMergeValues(Ops, 2);
4692 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4693 MVT SrcVT = Op.getOperand(0).getValueType();
4694 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4695 "Unknown SINT_TO_FP to lower!");
4697 // These are really Legal; caller falls through into that case.
4698 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4700 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4701 Subtarget->is64Bit())
4704 unsigned Size = SrcVT.getSizeInBits()/8;
4705 MachineFunction &MF = DAG.getMachineFunction();
4706 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4707 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4708 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4710 PseudoSourceValue::getFixedStack(SSFI), 0);
4714 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4716 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4718 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4719 SmallVector<SDValue, 8> Ops;
4720 Ops.push_back(Chain);
4721 Ops.push_back(StackSlot);
4722 Ops.push_back(DAG.getValueType(SrcVT));
4723 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4724 Tys, &Ops[0], Ops.size());
4727 Chain = Result.getValue(1);
4728 SDValue InFlag = Result.getValue(2);
4730 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4731 // shouldn't be necessary except that RFP cannot be live across
4732 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4733 MachineFunction &MF = DAG.getMachineFunction();
4734 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4735 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4736 Tys = DAG.getVTList(MVT::Other);
4737 SmallVector<SDValue, 8> Ops;
4738 Ops.push_back(Chain);
4739 Ops.push_back(Result);
4740 Ops.push_back(StackSlot);
4741 Ops.push_back(DAG.getValueType(Op.getValueType()));
4742 Ops.push_back(InFlag);
4743 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4744 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4745 PseudoSourceValue::getFixedStack(SSFI), 0);
4751 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4752 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4753 // This algorithm is not obvious. Here it is in C code, more or less:
4755 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4756 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4757 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4759 // Copy ints to xmm registers.
4760 __m128i xh = _mm_cvtsi32_si128( hi );
4761 __m128i xl = _mm_cvtsi32_si128( lo );
4763 // Combine into low half of a single xmm register.
4764 __m128i x = _mm_unpacklo_epi32( xh, xl );
4768 // Merge in appropriate exponents to give the integer bits the right
4770 x = _mm_unpacklo_epi32( x, exp );
4772 // Subtract away the biases to deal with the IEEE-754 double precision
4774 d = _mm_sub_pd( (__m128d) x, bias );
4776 // All conversions up to here are exact. The correctly rounded result is
4777 // calculated using the current rounding mode using the following
4779 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4780 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4781 // store doesn't really need to be here (except
4782 // maybe to zero the other double)
4787 // Build some magic constants.
4788 std::vector<Constant*> CV0;
4789 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
4790 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
4791 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4792 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4793 Constant *C0 = ConstantVector::get(CV0);
4794 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4);
4796 std::vector<Constant*> CV1;
4797 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
4798 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
4799 Constant *C1 = ConstantVector::get(CV1);
4800 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4);
4802 SmallVector<SDValue, 4> MaskVec;
4803 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
4804 MaskVec.push_back(DAG.getConstant(4, MVT::i32));
4805 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
4806 MaskVec.push_back(DAG.getConstant(5, MVT::i32));
4807 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0],
4809 SmallVector<SDValue, 4> MaskVec2;
4810 MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
4811 MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
4812 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec2[0],
4815 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4816 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4818 DAG.getIntPtrConstant(1)));
4819 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4820 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4822 DAG.getIntPtrConstant(0)));
4823 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4824 XR1, XR2, UnpcklMask);
4825 SDValue CLod0 = DAG.getLoad(MVT::v4i32, DAG.getEntryNode(), CPIdx0,
4826 PseudoSourceValue::getConstantPool(), 0,
4828 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4829 Unpck1, CLod0, UnpcklMask);
4830 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Unpck2);
4831 SDValue CLod1 = DAG.getLoad(MVT::v2f64, CLod0.getValue(1), CPIdx1,
4832 PseudoSourceValue::getConstantPool(), 0,
4834 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::v2f64, XR2F, CLod1);
4836 // Add the halves; easiest way is to swap them into another reg first.
4837 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2f64,
4838 Sub, Sub, ShufMask);
4839 SDValue Add = DAG.getNode(ISD::FADD, MVT::v2f64, Shuf, Sub);
4840 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, Add,
4841 DAG.getIntPtrConstant(0));
4844 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4845 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
4846 // FP constant to bias correct the final result.
4847 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
4850 // Load the 32-bit value into an XMM register.
4851 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4852 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4854 DAG.getIntPtrConstant(0)));
4856 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64,
4857 DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Load),
4858 DAG.getIntPtrConstant(0));
4860 // Or the load with the bias.
4861 SDValue Or = DAG.getNode(ISD::OR, MVT::v2i64,
4862 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
4863 DAG.getNode(ISD::SCALAR_TO_VECTOR,
4865 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
4866 DAG.getNode(ISD::SCALAR_TO_VECTOR,
4867 MVT::v2f64, Bias)));
4868 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64,
4869 DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Or),
4870 DAG.getIntPtrConstant(0));
4872 // Subtract the bias.
4873 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Or, Bias);
4875 // Handle final rounding.
4876 MVT DestVT = Op.getValueType();
4878 if (DestVT.bitsLT(MVT::f64)) {
4879 return DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
4880 DAG.getIntPtrConstant(0));
4881 } else if (DestVT.bitsGT(MVT::f64)) {
4882 return DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
4885 // Handle final rounding.
4889 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4890 SDValue N0 = Op.getOperand(0);
4892 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
4893 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
4894 // the optimization here.
4895 if (DAG.SignBitIsZero(N0))
4896 return DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), N0);
4898 MVT SrcVT = N0.getValueType();
4899 if (SrcVT == MVT::i64) {
4900 // We only handle SSE2 f64 target here; caller can handle the rest.
4901 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
4904 return LowerUINT_TO_FP_i64(Op, DAG);
4905 } else if (SrcVT == MVT::i32) {
4906 return LowerUINT_TO_FP_i32(Op, DAG);
4909 assert(0 && "Unknown UINT_TO_FP to lower!");
4913 std::pair<SDValue,SDValue> X86TargetLowering::
4914 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
4915 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4916 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4917 "Unknown FP_TO_SINT to lower!");
4919 // These are really Legal.
4920 if (Op.getValueType() == MVT::i32 &&
4921 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4922 return std::make_pair(SDValue(), SDValue());
4923 if (Subtarget->is64Bit() &&
4924 Op.getValueType() == MVT::i64 &&
4925 Op.getOperand(0).getValueType() != MVT::f80)
4926 return std::make_pair(SDValue(), SDValue());
4928 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4930 MachineFunction &MF = DAG.getMachineFunction();
4931 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4932 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4933 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4935 switch (Op.getValueType().getSimpleVT()) {
4936 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4937 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4938 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4939 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4942 SDValue Chain = DAG.getEntryNode();
4943 SDValue Value = Op.getOperand(0);
4944 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4945 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4946 Chain = DAG.getStore(Chain, Value, StackSlot,
4947 PseudoSourceValue::getFixedStack(SSFI), 0);
4948 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4950 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4952 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4953 Chain = Value.getValue(1);
4954 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4955 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4958 // Build the FP_TO_INT*_IN_MEM
4959 SDValue Ops[] = { Chain, Value, StackSlot };
4960 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4962 return std::make_pair(FIST, StackSlot);
4965 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4966 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4967 SDValue FIST = Vals.first, StackSlot = Vals.second;
4968 if (FIST.getNode() == 0) return SDValue();
4971 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4974 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
4975 MVT VT = Op.getValueType();
4978 EltVT = VT.getVectorElementType();
4979 std::vector<Constant*> CV;
4980 if (EltVT == MVT::f64) {
4981 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4985 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4991 Constant *C = ConstantVector::get(CV);
4992 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4993 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4994 PseudoSourceValue::getConstantPool(), 0,
4996 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4999 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5000 MVT VT = Op.getValueType();
5002 unsigned EltNum = 1;
5003 if (VT.isVector()) {
5004 EltVT = VT.getVectorElementType();
5005 EltNum = VT.getVectorNumElements();
5007 std::vector<Constant*> CV;
5008 if (EltVT == MVT::f64) {
5009 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
5013 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
5019 Constant *C = ConstantVector::get(CV);
5020 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5021 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5022 PseudoSourceValue::getConstantPool(), 0,
5024 if (VT.isVector()) {
5025 return DAG.getNode(ISD::BIT_CONVERT, VT,
5026 DAG.getNode(ISD::XOR, MVT::v2i64,
5027 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
5028 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
5030 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
5034 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5035 SDValue Op0 = Op.getOperand(0);
5036 SDValue Op1 = Op.getOperand(1);
5037 MVT VT = Op.getValueType();
5038 MVT SrcVT = Op1.getValueType();
5040 // If second operand is smaller, extend it first.
5041 if (SrcVT.bitsLT(VT)) {
5042 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
5045 // And if it is bigger, shrink it first.
5046 if (SrcVT.bitsGT(VT)) {
5047 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
5051 // At this point the operands and the result should have the same
5052 // type, and that won't be f80 since that is not custom lowered.
5054 // First get the sign bit of second operand.
5055 std::vector<Constant*> CV;
5056 if (SrcVT == MVT::f64) {
5057 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
5058 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5060 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
5061 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5062 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5063 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5065 Constant *C = ConstantVector::get(CV);
5066 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5067 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
5068 PseudoSourceValue::getConstantPool(), 0,
5070 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
5072 // Shift sign bit right or left if the two operands have different types.
5073 if (SrcVT.bitsGT(VT)) {
5074 // Op0 is MVT::f32, Op1 is MVT::f64.
5075 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
5076 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
5077 DAG.getConstant(32, MVT::i32));
5078 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
5079 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
5080 DAG.getIntPtrConstant(0));
5083 // Clear first operand sign bit.
5085 if (VT == MVT::f64) {
5086 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
5087 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5089 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
5090 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5091 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5092 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5094 C = ConstantVector::get(CV);
5095 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5096 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5097 PseudoSourceValue::getConstantPool(), 0,
5099 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
5101 // Or the value with the sign bit.
5102 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
5105 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5106 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5107 SDValue Op0 = Op.getOperand(0);
5108 SDValue Op1 = Op.getOperand(1);
5109 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5111 // Lower (X & (1 << N)) == 0 to BT.
5112 // Lower ((X >>u N) & 1) != 0 to BT.
5113 // Lower ((X >>s N) & 1) != 0 to BT.
5114 if (Op0.getOpcode() == ISD::AND &&
5116 Op1.getOpcode() == ISD::Constant &&
5117 Op0.getOperand(1).getOpcode() == ISD::Constant &&
5118 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5119 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5120 ConstantSDNode *CmpRHS = cast<ConstantSDNode>(Op1);
5121 SDValue AndLHS = Op0.getOperand(0);
5122 if (CmpRHS->getZExtValue() == 0 && AndRHS->getZExtValue() == 1 &&
5123 AndLHS.getOpcode() == ISD::SRL) {
5124 SDValue LHS = AndLHS.getOperand(0);
5125 SDValue RHS = AndLHS.getOperand(1);
5127 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5128 // instruction. Since the shift amount is in-range-or-undefined, we know
5129 // that doing a bittest on the i16 value is ok. We extend to i32 because
5130 // the encoding for the i16 version is larger than the i32 version.
5131 if (LHS.getValueType() == MVT::i8)
5132 LHS = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, LHS);
5134 // If the operand types disagree, extend the shift amount to match. Since
5135 // BT ignores high bits (like shifts) we can use anyextend.
5136 if (LHS.getValueType() != RHS.getValueType())
5137 RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS);
5139 SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS);
5140 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5141 return DAG.getNode(X86ISD::SETCC, MVT::i8,
5142 DAG.getConstant(Cond, MVT::i8), BT);
5146 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5147 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5149 SDValue Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
5150 return DAG.getNode(X86ISD::SETCC, MVT::i8,
5151 DAG.getConstant(X86CC, MVT::i8), Cond);
5154 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5156 SDValue Op0 = Op.getOperand(0);
5157 SDValue Op1 = Op.getOperand(1);
5158 SDValue CC = Op.getOperand(2);
5159 MVT VT = Op.getValueType();
5160 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5161 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5165 MVT VT0 = Op0.getValueType();
5166 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5167 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5170 switch (SetCCOpcode) {
5173 case ISD::SETEQ: SSECC = 0; break;
5175 case ISD::SETGT: Swap = true; // Fallthrough
5177 case ISD::SETOLT: SSECC = 1; break;
5179 case ISD::SETGE: Swap = true; // Fallthrough
5181 case ISD::SETOLE: SSECC = 2; break;
5182 case ISD::SETUO: SSECC = 3; break;
5184 case ISD::SETNE: SSECC = 4; break;
5185 case ISD::SETULE: Swap = true;
5186 case ISD::SETUGE: SSECC = 5; break;
5187 case ISD::SETULT: Swap = true;
5188 case ISD::SETUGT: SSECC = 6; break;
5189 case ISD::SETO: SSECC = 7; break;
5192 std::swap(Op0, Op1);
5194 // In the two special cases we can't handle, emit two comparisons.
5196 if (SetCCOpcode == ISD::SETUEQ) {
5198 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5199 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5200 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
5202 else if (SetCCOpcode == ISD::SETONE) {
5204 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5205 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5206 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
5208 assert(0 && "Illegal FP comparison");
5210 // Handle all other FP comparisons here.
5211 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5214 // We are handling one of the integer comparisons here. Since SSE only has
5215 // GT and EQ comparisons for integer, swapping operands and multiple
5216 // operations may be required for some comparisons.
5217 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5218 bool Swap = false, Invert = false, FlipSigns = false;
5220 switch (VT.getSimpleVT()) {
5222 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5223 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5224 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5225 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5228 switch (SetCCOpcode) {
5230 case ISD::SETNE: Invert = true;
5231 case ISD::SETEQ: Opc = EQOpc; break;
5232 case ISD::SETLT: Swap = true;
5233 case ISD::SETGT: Opc = GTOpc; break;
5234 case ISD::SETGE: Swap = true;
5235 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5236 case ISD::SETULT: Swap = true;
5237 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5238 case ISD::SETUGE: Swap = true;
5239 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5242 std::swap(Op0, Op1);
5244 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5245 // bits of the inputs before performing those operations.
5247 MVT EltVT = VT.getVectorElementType();
5248 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
5249 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5250 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
5252 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
5253 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
5256 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
5258 // If the logical-not of the result is required, perform that now.
5260 Result = DAG.getNOT(Result, VT);
5265 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5266 static bool isX86LogicalCmp(unsigned Opc) {
5267 return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI;
5270 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5271 bool addTest = true;
5272 SDValue Cond = Op.getOperand(0);
5275 if (Cond.getOpcode() == ISD::SETCC)
5276 Cond = LowerSETCC(Cond, DAG);
5278 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5279 // setting operand in place of the X86ISD::SETCC.
5280 if (Cond.getOpcode() == X86ISD::SETCC) {
5281 CC = Cond.getOperand(0);
5283 SDValue Cmp = Cond.getOperand(1);
5284 unsigned Opc = Cmp.getOpcode();
5285 MVT VT = Op.getValueType();
5287 bool IllegalFPCMov = false;
5288 if (VT.isFloatingPoint() && !VT.isVector() &&
5289 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5290 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5292 if (isX86LogicalCmp(Opc) && !IllegalFPCMov) {
5299 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5300 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5303 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
5305 SmallVector<SDValue, 4> Ops;
5306 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5307 // condition is true.
5308 Ops.push_back(Op.getOperand(2));
5309 Ops.push_back(Op.getOperand(1));
5311 Ops.push_back(Cond);
5312 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
5315 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5316 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5317 // from the AND / OR.
5318 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5319 Opc = Op.getOpcode();
5320 if (Opc != ISD::OR && Opc != ISD::AND)
5322 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5323 Op.getOperand(0).hasOneUse() &&
5324 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5325 Op.getOperand(1).hasOneUse());
5328 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5329 bool addTest = true;
5330 SDValue Chain = Op.getOperand(0);
5331 SDValue Cond = Op.getOperand(1);
5332 SDValue Dest = Op.getOperand(2);
5335 if (Cond.getOpcode() == ISD::SETCC)
5336 Cond = LowerSETCC(Cond, DAG);
5338 // FIXME: LowerXALUO doesn't handle these!!
5339 else if (Cond.getOpcode() == X86ISD::ADD ||
5340 Cond.getOpcode() == X86ISD::SUB ||
5341 Cond.getOpcode() == X86ISD::SMUL ||
5342 Cond.getOpcode() == X86ISD::UMUL)
5343 Cond = LowerXALUO(Cond, DAG);
5346 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5347 // setting operand in place of the X86ISD::SETCC.
5348 if (Cond.getOpcode() == X86ISD::SETCC) {
5349 CC = Cond.getOperand(0);
5351 SDValue Cmp = Cond.getOperand(1);
5352 unsigned Opc = Cmp.getOpcode();
5353 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5354 if (isX86LogicalCmp(Opc) || Opc == X86ISD::BT) {
5358 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5362 // These can only come from an arithmetic instruction with overflow,
5363 // e.g. SADDO, UADDO.
5364 Cond = Cond.getNode()->getOperand(1);
5371 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5372 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5373 unsigned Opc = Cmp.getOpcode();
5374 if (CondOpc == ISD::OR) {
5375 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5376 // two branches instead of an explicit OR instruction with a
5378 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5379 isX86LogicalCmp(Opc)) {
5380 CC = Cond.getOperand(0).getOperand(0);
5381 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5382 Chain, Dest, CC, Cmp);
5383 CC = Cond.getOperand(1).getOperand(0);
5387 } else { // ISD::AND
5388 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5389 // two branches instead of an explicit AND instruction with a
5390 // separate test. However, we only do this if this block doesn't
5391 // have a fall-through edge, because this requires an explicit
5392 // jmp when the condition is false.
5393 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5394 isX86LogicalCmp(Opc) &&
5395 Op.getNode()->hasOneUse()) {
5396 X86::CondCode CCode =
5397 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5398 CCode = X86::GetOppositeBranchCondition(CCode);
5399 CC = DAG.getConstant(CCode, MVT::i8);
5400 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5401 // Look for an unconditional branch following this conditional branch.
5402 // We need this because we need to reverse the successors in order
5403 // to implement FCMP_OEQ.
5404 if (User.getOpcode() == ISD::BR) {
5405 SDValue FalseBB = User.getOperand(1);
5407 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5408 assert(NewBR == User);
5411 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5412 Chain, Dest, CC, Cmp);
5413 X86::CondCode CCode =
5414 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5415 CCode = X86::GetOppositeBranchCondition(CCode);
5416 CC = DAG.getConstant(CCode, MVT::i8);
5426 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5427 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5429 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5430 Chain, Dest, CC, Cond);
5434 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5435 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5436 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5437 // that the guard pages used by the OS virtual memory manager are allocated in
5438 // correct sequence.
5440 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5441 SelectionDAG &DAG) {
5442 assert(Subtarget->isTargetCygMing() &&
5443 "This should be used only on Cygwin/Mingw targets");
5446 SDValue Chain = Op.getOperand(0);
5447 SDValue Size = Op.getOperand(1);
5448 // FIXME: Ensure alignment here
5452 MVT IntPtr = getPointerTy();
5453 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5455 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5457 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
5458 Flag = Chain.getValue(1);
5460 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5461 SDValue Ops[] = { Chain,
5462 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5463 DAG.getRegister(X86::EAX, IntPtr),
5464 DAG.getRegister(X86StackPtr, SPTy),
5466 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
5467 Flag = Chain.getValue(1);
5469 Chain = DAG.getCALLSEQ_END(Chain,
5470 DAG.getIntPtrConstant(0, true),
5471 DAG.getIntPtrConstant(0, true),
5474 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
5476 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5477 return DAG.getMergeValues(Ops1, 2);
5481 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
5483 SDValue Dst, SDValue Src,
5484 SDValue Size, unsigned Align,
5486 uint64_t DstSVOff) {
5487 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5489 // If not DWORD aligned or size is more than the threshold, call the library.
5490 // The libc version is likely to be faster for these cases. It can use the
5491 // address value and run time information about the CPU.
5492 if ((Align & 3) != 0 ||
5494 ConstantSize->getZExtValue() >
5495 getSubtarget()->getMaxInlineSizeThreshold()) {
5496 SDValue InFlag(0, 0);
5498 // Check to see if there is a specialized entry-point for memory zeroing.
5499 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5501 if (const char *bzeroEntry = V &&
5502 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5503 MVT IntPtr = getPointerTy();
5504 const Type *IntPtrTy = TD->getIntPtrType();
5505 TargetLowering::ArgListTy Args;
5506 TargetLowering::ArgListEntry Entry;
5508 Entry.Ty = IntPtrTy;
5509 Args.push_back(Entry);
5511 Args.push_back(Entry);
5512 std::pair<SDValue,SDValue> CallResult =
5513 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5514 CallingConv::C, false,
5515 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG);
5516 return CallResult.second;
5519 // Otherwise have the target-independent code call memset.
5523 uint64_t SizeVal = ConstantSize->getZExtValue();
5524 SDValue InFlag(0, 0);
5527 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5528 unsigned BytesLeft = 0;
5529 bool TwoRepStos = false;
5532 uint64_t Val = ValC->getZExtValue() & 255;
5534 // If the value is a constant, then we can potentially use larger sets.
5535 switch (Align & 3) {
5536 case 2: // WORD aligned
5539 Val = (Val << 8) | Val;
5541 case 0: // DWORD aligned
5544 Val = (Val << 8) | Val;
5545 Val = (Val << 16) | Val;
5546 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5549 Val = (Val << 32) | Val;
5552 default: // Byte aligned
5555 Count = DAG.getIntPtrConstant(SizeVal);
5559 if (AVT.bitsGT(MVT::i8)) {
5560 unsigned UBytes = AVT.getSizeInBits() / 8;
5561 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5562 BytesLeft = SizeVal % UBytes;
5565 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5567 InFlag = Chain.getValue(1);
5570 Count = DAG.getIntPtrConstant(SizeVal);
5571 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
5572 InFlag = Chain.getValue(1);
5575 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5577 InFlag = Chain.getValue(1);
5578 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5580 InFlag = Chain.getValue(1);
5582 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5583 SmallVector<SDValue, 8> Ops;
5584 Ops.push_back(Chain);
5585 Ops.push_back(DAG.getValueType(AVT));
5586 Ops.push_back(InFlag);
5587 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5590 InFlag = Chain.getValue(1);
5592 MVT CVT = Count.getValueType();
5593 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
5594 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5595 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5597 InFlag = Chain.getValue(1);
5598 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5600 Ops.push_back(Chain);
5601 Ops.push_back(DAG.getValueType(MVT::i8));
5602 Ops.push_back(InFlag);
5603 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5604 } else if (BytesLeft) {
5605 // Handle the last 1 - 7 bytes.
5606 unsigned Offset = SizeVal - BytesLeft;
5607 MVT AddrVT = Dst.getValueType();
5608 MVT SizeVT = Size.getValueType();
5610 Chain = DAG.getMemset(Chain,
5611 DAG.getNode(ISD::ADD, AddrVT, Dst,
5612 DAG.getConstant(Offset, AddrVT)),
5614 DAG.getConstant(BytesLeft, SizeVT),
5615 Align, DstSV, DstSVOff + Offset);
5618 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5623 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
5624 SDValue Chain, SDValue Dst, SDValue Src,
5625 SDValue Size, unsigned Align,
5627 const Value *DstSV, uint64_t DstSVOff,
5628 const Value *SrcSV, uint64_t SrcSVOff) {
5629 // This requires the copy size to be a constant, preferrably
5630 // within a subtarget-specific limit.
5631 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5634 uint64_t SizeVal = ConstantSize->getZExtValue();
5635 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5638 /// If not DWORD aligned, call the library.
5639 if ((Align & 3) != 0)
5644 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5647 unsigned UBytes = AVT.getSizeInBits() / 8;
5648 unsigned CountVal = SizeVal / UBytes;
5649 SDValue Count = DAG.getIntPtrConstant(CountVal);
5650 unsigned BytesLeft = SizeVal % UBytes;
5652 SDValue InFlag(0, 0);
5653 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5655 InFlag = Chain.getValue(1);
5656 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5658 InFlag = Chain.getValue(1);
5659 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5661 InFlag = Chain.getValue(1);
5663 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5664 SmallVector<SDValue, 8> Ops;
5665 Ops.push_back(Chain);
5666 Ops.push_back(DAG.getValueType(AVT));
5667 Ops.push_back(InFlag);
5668 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5670 SmallVector<SDValue, 4> Results;
5671 Results.push_back(RepMovs);
5673 // Handle the last 1 - 7 bytes.
5674 unsigned Offset = SizeVal - BytesLeft;
5675 MVT DstVT = Dst.getValueType();
5676 MVT SrcVT = Src.getValueType();
5677 MVT SizeVT = Size.getValueType();
5678 Results.push_back(DAG.getMemcpy(Chain,
5679 DAG.getNode(ISD::ADD, DstVT, Dst,
5680 DAG.getConstant(Offset, DstVT)),
5681 DAG.getNode(ISD::ADD, SrcVT, Src,
5682 DAG.getConstant(Offset, SrcVT)),
5683 DAG.getConstant(BytesLeft, SizeVT),
5684 Align, AlwaysInline,
5685 DstSV, DstSVOff + Offset,
5686 SrcSV, SrcSVOff + Offset));
5689 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5692 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5693 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5695 if (!Subtarget->is64Bit()) {
5696 // vastart just stores the address of the VarArgsFrameIndex slot into the
5697 // memory location argument.
5698 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5699 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5703 // gp_offset (0 - 6 * 8)
5704 // fp_offset (48 - 48 + 8 * 16)
5705 // overflow_arg_area (point to parameters coming in memory).
5707 SmallVector<SDValue, 8> MemOps;
5708 SDValue FIN = Op.getOperand(1);
5710 SDValue Store = DAG.getStore(Op.getOperand(0),
5711 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5713 MemOps.push_back(Store);
5716 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5717 Store = DAG.getStore(Op.getOperand(0),
5718 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5720 MemOps.push_back(Store);
5722 // Store ptr to overflow_arg_area
5723 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5724 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5725 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5726 MemOps.push_back(Store);
5728 // Store ptr to reg_save_area.
5729 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5730 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5731 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5732 MemOps.push_back(Store);
5733 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5736 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5737 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5738 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5739 SDValue Chain = Op.getOperand(0);
5740 SDValue SrcPtr = Op.getOperand(1);
5741 SDValue SrcSV = Op.getOperand(2);
5743 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5748 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5749 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5750 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5751 SDValue Chain = Op.getOperand(0);
5752 SDValue DstPtr = Op.getOperand(1);
5753 SDValue SrcPtr = Op.getOperand(2);
5754 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5755 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5757 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5758 DAG.getIntPtrConstant(24), 8, false,
5759 DstSV, 0, SrcSV, 0);
5763 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5764 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5766 default: return SDValue(); // Don't custom lower most intrinsics.
5767 // Comparison intrinsics.
5768 case Intrinsic::x86_sse_comieq_ss:
5769 case Intrinsic::x86_sse_comilt_ss:
5770 case Intrinsic::x86_sse_comile_ss:
5771 case Intrinsic::x86_sse_comigt_ss:
5772 case Intrinsic::x86_sse_comige_ss:
5773 case Intrinsic::x86_sse_comineq_ss:
5774 case Intrinsic::x86_sse_ucomieq_ss:
5775 case Intrinsic::x86_sse_ucomilt_ss:
5776 case Intrinsic::x86_sse_ucomile_ss:
5777 case Intrinsic::x86_sse_ucomigt_ss:
5778 case Intrinsic::x86_sse_ucomige_ss:
5779 case Intrinsic::x86_sse_ucomineq_ss:
5780 case Intrinsic::x86_sse2_comieq_sd:
5781 case Intrinsic::x86_sse2_comilt_sd:
5782 case Intrinsic::x86_sse2_comile_sd:
5783 case Intrinsic::x86_sse2_comigt_sd:
5784 case Intrinsic::x86_sse2_comige_sd:
5785 case Intrinsic::x86_sse2_comineq_sd:
5786 case Intrinsic::x86_sse2_ucomieq_sd:
5787 case Intrinsic::x86_sse2_ucomilt_sd:
5788 case Intrinsic::x86_sse2_ucomile_sd:
5789 case Intrinsic::x86_sse2_ucomigt_sd:
5790 case Intrinsic::x86_sse2_ucomige_sd:
5791 case Intrinsic::x86_sse2_ucomineq_sd: {
5793 ISD::CondCode CC = ISD::SETCC_INVALID;
5796 case Intrinsic::x86_sse_comieq_ss:
5797 case Intrinsic::x86_sse2_comieq_sd:
5801 case Intrinsic::x86_sse_comilt_ss:
5802 case Intrinsic::x86_sse2_comilt_sd:
5806 case Intrinsic::x86_sse_comile_ss:
5807 case Intrinsic::x86_sse2_comile_sd:
5811 case Intrinsic::x86_sse_comigt_ss:
5812 case Intrinsic::x86_sse2_comigt_sd:
5816 case Intrinsic::x86_sse_comige_ss:
5817 case Intrinsic::x86_sse2_comige_sd:
5821 case Intrinsic::x86_sse_comineq_ss:
5822 case Intrinsic::x86_sse2_comineq_sd:
5826 case Intrinsic::x86_sse_ucomieq_ss:
5827 case Intrinsic::x86_sse2_ucomieq_sd:
5828 Opc = X86ISD::UCOMI;
5831 case Intrinsic::x86_sse_ucomilt_ss:
5832 case Intrinsic::x86_sse2_ucomilt_sd:
5833 Opc = X86ISD::UCOMI;
5836 case Intrinsic::x86_sse_ucomile_ss:
5837 case Intrinsic::x86_sse2_ucomile_sd:
5838 Opc = X86ISD::UCOMI;
5841 case Intrinsic::x86_sse_ucomigt_ss:
5842 case Intrinsic::x86_sse2_ucomigt_sd:
5843 Opc = X86ISD::UCOMI;
5846 case Intrinsic::x86_sse_ucomige_ss:
5847 case Intrinsic::x86_sse2_ucomige_sd:
5848 Opc = X86ISD::UCOMI;
5851 case Intrinsic::x86_sse_ucomineq_ss:
5852 case Intrinsic::x86_sse2_ucomineq_sd:
5853 Opc = X86ISD::UCOMI;
5858 SDValue LHS = Op.getOperand(1);
5859 SDValue RHS = Op.getOperand(2);
5860 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
5861 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5862 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5863 DAG.getConstant(X86CC, MVT::i8), Cond);
5864 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
5867 // Fix vector shift instructions where the last operand is a non-immediate
5869 case Intrinsic::x86_sse2_pslli_w:
5870 case Intrinsic::x86_sse2_pslli_d:
5871 case Intrinsic::x86_sse2_pslli_q:
5872 case Intrinsic::x86_sse2_psrli_w:
5873 case Intrinsic::x86_sse2_psrli_d:
5874 case Intrinsic::x86_sse2_psrli_q:
5875 case Intrinsic::x86_sse2_psrai_w:
5876 case Intrinsic::x86_sse2_psrai_d:
5877 case Intrinsic::x86_mmx_pslli_w:
5878 case Intrinsic::x86_mmx_pslli_d:
5879 case Intrinsic::x86_mmx_pslli_q:
5880 case Intrinsic::x86_mmx_psrli_w:
5881 case Intrinsic::x86_mmx_psrli_d:
5882 case Intrinsic::x86_mmx_psrli_q:
5883 case Intrinsic::x86_mmx_psrai_w:
5884 case Intrinsic::x86_mmx_psrai_d: {
5885 SDValue ShAmt = Op.getOperand(2);
5886 if (isa<ConstantSDNode>(ShAmt))
5889 unsigned NewIntNo = 0;
5890 MVT ShAmtVT = MVT::v4i32;
5892 case Intrinsic::x86_sse2_pslli_w:
5893 NewIntNo = Intrinsic::x86_sse2_psll_w;
5895 case Intrinsic::x86_sse2_pslli_d:
5896 NewIntNo = Intrinsic::x86_sse2_psll_d;
5898 case Intrinsic::x86_sse2_pslli_q:
5899 NewIntNo = Intrinsic::x86_sse2_psll_q;
5901 case Intrinsic::x86_sse2_psrli_w:
5902 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5904 case Intrinsic::x86_sse2_psrli_d:
5905 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5907 case Intrinsic::x86_sse2_psrli_q:
5908 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5910 case Intrinsic::x86_sse2_psrai_w:
5911 NewIntNo = Intrinsic::x86_sse2_psra_w;
5913 case Intrinsic::x86_sse2_psrai_d:
5914 NewIntNo = Intrinsic::x86_sse2_psra_d;
5917 ShAmtVT = MVT::v2i32;
5919 case Intrinsic::x86_mmx_pslli_w:
5920 NewIntNo = Intrinsic::x86_mmx_psll_w;
5922 case Intrinsic::x86_mmx_pslli_d:
5923 NewIntNo = Intrinsic::x86_mmx_psll_d;
5925 case Intrinsic::x86_mmx_pslli_q:
5926 NewIntNo = Intrinsic::x86_mmx_psll_q;
5928 case Intrinsic::x86_mmx_psrli_w:
5929 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5931 case Intrinsic::x86_mmx_psrli_d:
5932 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5934 case Intrinsic::x86_mmx_psrli_q:
5935 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5937 case Intrinsic::x86_mmx_psrai_w:
5938 NewIntNo = Intrinsic::x86_mmx_psra_w;
5940 case Intrinsic::x86_mmx_psrai_d:
5941 NewIntNo = Intrinsic::x86_mmx_psra_d;
5943 default: abort(); // Can't reach here.
5948 MVT VT = Op.getValueType();
5949 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5950 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5951 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5952 DAG.getConstant(NewIntNo, MVT::i32),
5953 Op.getOperand(1), ShAmt);
5958 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5959 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5962 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5964 DAG.getConstant(TD->getPointerSize(),
5965 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
5966 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(),
5967 DAG.getNode(ISD::ADD, getPointerTy(), FrameAddr, Offset),
5971 // Just load the return address.
5972 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5973 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5976 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5977 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5978 MFI->setFrameAddressIsTaken(true);
5979 MVT VT = Op.getValueType();
5980 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5981 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
5982 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT);
5984 FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0);
5988 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
5989 SelectionDAG &DAG) {
5990 return DAG.getIntPtrConstant(2*TD->getPointerSize());
5993 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
5995 MachineFunction &MF = DAG.getMachineFunction();
5996 SDValue Chain = Op.getOperand(0);
5997 SDValue Offset = Op.getOperand(1);
5998 SDValue Handler = Op.getOperand(2);
6000 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6002 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6004 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
6005 DAG.getIntPtrConstant(-TD->getPointerSize()));
6006 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
6007 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
6008 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
6009 MF.getRegInfo().addLiveOut(StoreAddrReg);
6011 return DAG.getNode(X86ISD::EH_RETURN,
6013 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6016 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6017 SelectionDAG &DAG) {
6018 SDValue Root = Op.getOperand(0);
6019 SDValue Trmp = Op.getOperand(1); // trampoline
6020 SDValue FPtr = Op.getOperand(2); // nested function
6021 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6023 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6025 const X86InstrInfo *TII =
6026 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6028 if (Subtarget->is64Bit()) {
6029 SDValue OutChains[6];
6031 // Large code-model.
6033 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6034 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6036 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6037 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6039 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6041 // Load the pointer to the nested function into R11.
6042 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6043 SDValue Addr = Trmp;
6044 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
6047 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
6048 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
6050 // Load the 'nest' parameter value into R10.
6051 // R10 is specified in X86CallingConv.td
6052 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6053 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
6054 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
6057 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
6058 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
6060 // Jump to the nested function.
6061 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6062 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
6063 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
6066 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6067 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
6068 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
6072 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
6073 return DAG.getMergeValues(Ops, 2);
6075 const Function *Func =
6076 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6077 unsigned CC = Func->getCallingConv();
6082 assert(0 && "Unsupported calling convention");
6083 case CallingConv::C:
6084 case CallingConv::X86_StdCall: {
6085 // Pass 'nest' parameter in ECX.
6086 // Must be kept in sync with X86CallingConv.td
6089 // Check that ECX wasn't needed by an 'inreg' parameter.
6090 const FunctionType *FTy = Func->getFunctionType();
6091 const AttrListPtr &Attrs = Func->getAttributes();
6093 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6094 unsigned InRegCount = 0;
6097 for (FunctionType::param_iterator I = FTy->param_begin(),
6098 E = FTy->param_end(); I != E; ++I, ++Idx)
6099 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6100 // FIXME: should only count parameters that are lowered to integers.
6101 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6103 if (InRegCount > 2) {
6104 cerr << "Nest register in use - reduce number of inreg parameters!\n";
6110 case CallingConv::X86_FastCall:
6111 case CallingConv::Fast:
6112 // Pass 'nest' parameter in EAX.
6113 // Must be kept in sync with X86CallingConv.td
6118 SDValue OutChains[4];
6121 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
6122 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
6124 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6125 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6126 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6129 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
6130 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
6132 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6133 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
6134 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
6135 TrmpAddr, 5, false, 1);
6137 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
6138 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
6141 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
6142 return DAG.getMergeValues(Ops, 2);
6146 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6148 The rounding mode is in bits 11:10 of FPSR, and has the following
6155 FLT_ROUNDS, on the other hand, expects the following:
6162 To perform the conversion, we do:
6163 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6166 MachineFunction &MF = DAG.getMachineFunction();
6167 const TargetMachine &TM = MF.getTarget();
6168 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6169 unsigned StackAlignment = TFI.getStackAlignment();
6170 MVT VT = Op.getValueType();
6172 // Save FP Control Word to stack slot
6173 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6174 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6176 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
6177 DAG.getEntryNode(), StackSlot);
6179 // Load FP Control Word from stack slot
6180 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
6182 // Transform as necessary
6184 DAG.getNode(ISD::SRL, MVT::i16,
6185 DAG.getNode(ISD::AND, MVT::i16,
6186 CWD, DAG.getConstant(0x800, MVT::i16)),
6187 DAG.getConstant(11, MVT::i8));
6189 DAG.getNode(ISD::SRL, MVT::i16,
6190 DAG.getNode(ISD::AND, MVT::i16,
6191 CWD, DAG.getConstant(0x400, MVT::i16)),
6192 DAG.getConstant(9, MVT::i8));
6195 DAG.getNode(ISD::AND, MVT::i16,
6196 DAG.getNode(ISD::ADD, MVT::i16,
6197 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
6198 DAG.getConstant(1, MVT::i16)),
6199 DAG.getConstant(3, MVT::i16));
6202 return DAG.getNode((VT.getSizeInBits() < 16 ?
6203 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
6206 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6207 MVT VT = Op.getValueType();
6209 unsigned NumBits = VT.getSizeInBits();
6211 Op = Op.getOperand(0);
6212 if (VT == MVT::i8) {
6213 // Zero extend to i32 since there is not an i8 bsr.
6215 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6218 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6219 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6220 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
6222 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6223 SmallVector<SDValue, 4> Ops;
6225 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6226 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6227 Ops.push_back(Op.getValue(1));
6228 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6230 // Finally xor with NumBits-1.
6231 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6234 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6238 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6239 MVT VT = Op.getValueType();
6241 unsigned NumBits = VT.getSizeInBits();
6243 Op = Op.getOperand(0);
6244 if (VT == MVT::i8) {
6246 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6249 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6250 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6251 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
6253 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6254 SmallVector<SDValue, 4> Ops;
6256 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6257 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6258 Ops.push_back(Op.getValue(1));
6259 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6262 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6266 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6267 MVT VT = Op.getValueType();
6268 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6270 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6271 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6272 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6273 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6274 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6276 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6277 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6278 // return AloBlo + AloBhi + AhiBlo;
6280 SDValue A = Op.getOperand(0);
6281 SDValue B = Op.getOperand(1);
6283 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6284 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6285 A, DAG.getConstant(32, MVT::i32));
6286 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6287 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6288 B, DAG.getConstant(32, MVT::i32));
6289 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6290 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6292 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6293 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6295 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6296 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6298 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6299 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6300 AloBhi, DAG.getConstant(32, MVT::i32));
6301 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6302 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6303 AhiBlo, DAG.getConstant(32, MVT::i32));
6304 SDValue Res = DAG.getNode(ISD::ADD, VT, AloBlo, AloBhi);
6305 Res = DAG.getNode(ISD::ADD, VT, Res, AhiBlo);
6310 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6311 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6312 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6313 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6314 // has only one use.
6315 SDNode *N = Op.getNode();
6316 SDValue LHS = N->getOperand(0);
6317 SDValue RHS = N->getOperand(1);
6318 unsigned BaseOp = 0;
6321 switch (Op.getOpcode()) {
6322 default: assert(0 && "Unknown ovf instruction!");
6324 BaseOp = X86ISD::ADD;
6328 BaseOp = X86ISD::ADD;
6332 BaseOp = X86ISD::SUB;
6336 BaseOp = X86ISD::SUB;
6340 BaseOp = X86ISD::SMUL;
6344 BaseOp = X86ISD::UMUL;
6349 // Also sets EFLAGS.
6350 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6351 SDValue Sum = DAG.getNode(BaseOp, VTs, LHS, RHS);
6354 DAG.getNode(X86ISD::SETCC, N->getValueType(1),
6355 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6357 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6361 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6362 MVT T = Op.getValueType();
6365 switch(T.getSimpleVT()) {
6367 assert(false && "Invalid value type!");
6368 case MVT::i8: Reg = X86::AL; size = 1; break;
6369 case MVT::i16: Reg = X86::AX; size = 2; break;
6370 case MVT::i32: Reg = X86::EAX; size = 4; break;
6372 assert(Subtarget->is64Bit() && "Node not type legal!");
6373 Reg = X86::RAX; size = 8;
6376 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
6377 Op.getOperand(2), SDValue());
6378 SDValue Ops[] = { cpIn.getValue(0),
6381 DAG.getTargetConstant(size, MVT::i8),
6383 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6384 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
6386 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
6390 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6391 SelectionDAG &DAG) {
6392 assert(Subtarget->is64Bit() && "Result not type legalized?");
6393 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6394 SDValue TheChain = Op.getOperand(0);
6395 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
6396 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
6397 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64,
6399 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
6400 DAG.getConstant(32, MVT::i8));
6402 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp),
6405 return DAG.getMergeValues(Ops, 2);
6408 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6409 SDNode *Node = Op.getNode();
6410 MVT T = Node->getValueType(0);
6411 SDValue negOp = DAG.getNode(ISD::SUB, T,
6412 DAG.getConstant(0, T), Node->getOperand(2));
6413 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD,
6414 cast<AtomicSDNode>(Node)->getMemoryVT(),
6415 Node->getOperand(0),
6416 Node->getOperand(1), negOp,
6417 cast<AtomicSDNode>(Node)->getSrcValue(),
6418 cast<AtomicSDNode>(Node)->getAlignment());
6421 /// LowerOperation - Provide custom lowering hooks for some operations.
6423 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6424 switch (Op.getOpcode()) {
6425 default: assert(0 && "Should not custom lower this!");
6426 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6427 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6428 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6429 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6430 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6431 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6432 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6433 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6434 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6435 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6436 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6437 case ISD::SHL_PARTS:
6438 case ISD::SRA_PARTS:
6439 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6440 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6441 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6442 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6443 case ISD::FABS: return LowerFABS(Op, DAG);
6444 case ISD::FNEG: return LowerFNEG(Op, DAG);
6445 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6446 case ISD::SETCC: return LowerSETCC(Op, DAG);
6447 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6448 case ISD::SELECT: return LowerSELECT(Op, DAG);
6449 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6450 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6451 case ISD::CALL: return LowerCALL(Op, DAG);
6452 case ISD::RET: return LowerRET(Op, DAG);
6453 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6454 case ISD::VASTART: return LowerVASTART(Op, DAG);
6455 case ISD::VAARG: return LowerVAARG(Op, DAG);
6456 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6457 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6458 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6459 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6460 case ISD::FRAME_TO_ARGS_OFFSET:
6461 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6462 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6463 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6464 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6465 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6466 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6467 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6468 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6474 case ISD::UMULO: return LowerXALUO(Op, DAG);
6475 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6479 void X86TargetLowering::
6480 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6481 SelectionDAG &DAG, unsigned NewOp) {
6482 MVT T = Node->getValueType(0);
6483 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6485 SDValue Chain = Node->getOperand(0);
6486 SDValue In1 = Node->getOperand(1);
6487 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6488 Node->getOperand(2), DAG.getIntPtrConstant(0));
6489 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6490 Node->getOperand(2), DAG.getIntPtrConstant(1));
6491 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6492 // have a MemOperand. Pass the info through as a normal operand.
6493 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6494 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6495 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6496 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5);
6497 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6498 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
6499 Results.push_back(Result.getValue(2));
6502 /// ReplaceNodeResults - Replace a node with an illegal result type
6503 /// with a new node built out of custom code.
6504 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6505 SmallVectorImpl<SDValue>&Results,
6506 SelectionDAG &DAG) {
6507 switch (N->getOpcode()) {
6509 assert(false && "Do not know how to custom type legalize this operation!");
6511 case ISD::FP_TO_SINT: {
6512 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
6513 SDValue FIST = Vals.first, StackSlot = Vals.second;
6514 if (FIST.getNode() != 0) {
6515 MVT VT = N->getValueType(0);
6516 // Return a load from the stack slot.
6517 Results.push_back(DAG.getLoad(VT, FIST, StackSlot, NULL, 0));
6521 case ISD::READCYCLECOUNTER: {
6522 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6523 SDValue TheChain = N->getOperand(0);
6524 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
6525 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
6526 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32,
6528 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6529 SDValue Ops[] = { eax, edx };
6530 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2));
6531 Results.push_back(edx.getValue(1));
6534 case ISD::ATOMIC_CMP_SWAP: {
6535 MVT T = N->getValueType(0);
6536 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6537 SDValue cpInL, cpInH;
6538 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
6539 DAG.getConstant(0, MVT::i32));
6540 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
6541 DAG.getConstant(1, MVT::i32));
6542 cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue());
6543 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH,
6545 SDValue swapInL, swapInH;
6546 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
6547 DAG.getConstant(0, MVT::i32));
6548 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
6549 DAG.getConstant(1, MVT::i32));
6550 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL,
6552 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH,
6553 swapInL.getValue(1));
6554 SDValue Ops[] = { swapInH.getValue(0),
6556 swapInH.getValue(1) };
6557 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6558 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
6559 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
6560 Result.getValue(1));
6561 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
6562 cpOutL.getValue(2));
6563 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6564 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
6565 Results.push_back(cpOutH.getValue(1));
6568 case ISD::ATOMIC_LOAD_ADD:
6569 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6571 case ISD::ATOMIC_LOAD_AND:
6572 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6574 case ISD::ATOMIC_LOAD_NAND:
6575 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6577 case ISD::ATOMIC_LOAD_OR:
6578 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6580 case ISD::ATOMIC_LOAD_SUB:
6581 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6583 case ISD::ATOMIC_LOAD_XOR:
6584 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6586 case ISD::ATOMIC_SWAP:
6587 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
6592 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6594 default: return NULL;
6595 case X86ISD::BSF: return "X86ISD::BSF";
6596 case X86ISD::BSR: return "X86ISD::BSR";
6597 case X86ISD::SHLD: return "X86ISD::SHLD";
6598 case X86ISD::SHRD: return "X86ISD::SHRD";
6599 case X86ISD::FAND: return "X86ISD::FAND";
6600 case X86ISD::FOR: return "X86ISD::FOR";
6601 case X86ISD::FXOR: return "X86ISD::FXOR";
6602 case X86ISD::FSRL: return "X86ISD::FSRL";
6603 case X86ISD::FILD: return "X86ISD::FILD";
6604 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6605 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6606 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6607 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6608 case X86ISD::FLD: return "X86ISD::FLD";
6609 case X86ISD::FST: return "X86ISD::FST";
6610 case X86ISD::CALL: return "X86ISD::CALL";
6611 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6612 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6613 case X86ISD::BT: return "X86ISD::BT";
6614 case X86ISD::CMP: return "X86ISD::CMP";
6615 case X86ISD::COMI: return "X86ISD::COMI";
6616 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6617 case X86ISD::SETCC: return "X86ISD::SETCC";
6618 case X86ISD::CMOV: return "X86ISD::CMOV";
6619 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6620 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6621 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6622 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6623 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6624 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6625 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6626 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6627 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6628 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6629 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6630 case X86ISD::FMAX: return "X86ISD::FMAX";
6631 case X86ISD::FMIN: return "X86ISD::FMIN";
6632 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6633 case X86ISD::FRCP: return "X86ISD::FRCP";
6634 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6635 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6636 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6637 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6638 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6639 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6640 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6641 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
6642 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
6643 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
6644 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
6645 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
6646 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
6647 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6648 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6649 case X86ISD::VSHL: return "X86ISD::VSHL";
6650 case X86ISD::VSRL: return "X86ISD::VSRL";
6651 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6652 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6653 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6654 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6655 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6656 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6657 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6658 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6659 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6660 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6661 case X86ISD::ADD: return "X86ISD::ADD";
6662 case X86ISD::SUB: return "X86ISD::SUB";
6663 case X86ISD::SMUL: return "X86ISD::SMUL";
6664 case X86ISD::UMUL: return "X86ISD::UMUL";
6668 // isLegalAddressingMode - Return true if the addressing mode represented
6669 // by AM is legal for this target, for a load/store of the specified type.
6670 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6671 const Type *Ty) const {
6672 // X86 supports extremely general addressing modes.
6674 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6675 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6679 // We can only fold this if we don't need an extra load.
6680 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6682 // If BaseGV requires a register, we cannot also have a BaseReg.
6683 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
6687 // X86-64 only supports addr of globals in small code model.
6688 if (Subtarget->is64Bit()) {
6689 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6691 // If lower 4G is not available, then we must use rip-relative addressing.
6692 if (AM.BaseOffs || AM.Scale > 1)
6703 // These scales always work.
6708 // These scales are formed with basereg+scalereg. Only accept if there is
6713 default: // Other stuff never works.
6721 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6722 if (!Ty1->isInteger() || !Ty2->isInteger())
6724 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6725 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6726 if (NumBits1 <= NumBits2)
6728 return Subtarget->is64Bit() || NumBits1 < 64;
6731 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6732 if (!VT1.isInteger() || !VT2.isInteger())
6734 unsigned NumBits1 = VT1.getSizeInBits();
6735 unsigned NumBits2 = VT2.getSizeInBits();
6736 if (NumBits1 <= NumBits2)
6738 return Subtarget->is64Bit() || NumBits1 < 64;
6741 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6742 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6743 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6744 /// are assumed to be legal.
6746 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6747 // Only do shuffles on 128-bit vector types for now.
6748 if (VT.getSizeInBits() == 64) return false;
6749 return (Mask.getNode()->getNumOperands() <= 4 ||
6750 isIdentityMask(Mask.getNode()) ||
6751 isIdentityMask(Mask.getNode(), true) ||
6752 isSplatMask(Mask.getNode()) ||
6753 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6754 X86::isUNPCKLMask(Mask.getNode()) ||
6755 X86::isUNPCKHMask(Mask.getNode()) ||
6756 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6757 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
6761 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6762 MVT EVT, SelectionDAG &DAG) const {
6763 unsigned NumElts = BVOps.size();
6764 // Only do shuffles on 128-bit vector types for now.
6765 if (EVT.getSizeInBits() * NumElts == 64) return false;
6766 if (NumElts == 2) return true;
6768 return (isMOVLMask(&BVOps[0], 4) ||
6769 isCommutedMOVL(&BVOps[0], 4, true) ||
6770 isSHUFPMask(&BVOps[0], 4) ||
6771 isCommutedSHUFP(&BVOps[0], 4));
6776 //===----------------------------------------------------------------------===//
6777 // X86 Scheduler Hooks
6778 //===----------------------------------------------------------------------===//
6780 // private utility function
6782 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6783 MachineBasicBlock *MBB,
6791 TargetRegisterClass *RC,
6793 // For the atomic bitwise operator, we generate
6796 // ld t1 = [bitinstr.addr]
6797 // op t2 = t1, [bitinstr.val]
6799 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6801 // fallthrough -->nextMBB
6802 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6803 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6804 MachineFunction::iterator MBBIter = MBB;
6807 /// First build the CFG
6808 MachineFunction *F = MBB->getParent();
6809 MachineBasicBlock *thisMBB = MBB;
6810 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6811 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6812 F->insert(MBBIter, newMBB);
6813 F->insert(MBBIter, nextMBB);
6815 // Move all successors to thisMBB to nextMBB
6816 nextMBB->transferSuccessors(thisMBB);
6818 // Update thisMBB to fall through to newMBB
6819 thisMBB->addSuccessor(newMBB);
6821 // newMBB jumps to itself and fall through to nextMBB
6822 newMBB->addSuccessor(nextMBB);
6823 newMBB->addSuccessor(newMBB);
6825 // Insert instructions into newMBB based on incoming instruction
6826 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6827 MachineOperand& destOper = bInstr->getOperand(0);
6828 MachineOperand* argOpers[6];
6829 int numArgs = bInstr->getNumOperands() - 1;
6830 for (int i=0; i < numArgs; ++i)
6831 argOpers[i] = &bInstr->getOperand(i+1);
6833 // x86 address has 4 operands: base, index, scale, and displacement
6834 int lastAddrIndx = 3; // [0,3]
6837 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6838 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
6839 for (int i=0; i <= lastAddrIndx; ++i)
6840 (*MIB).addOperand(*argOpers[i]);
6842 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
6844 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
6849 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6850 assert((argOpers[valArgIndx]->isReg() ||
6851 argOpers[valArgIndx]->isImm()) &&
6853 if (argOpers[valArgIndx]->isReg())
6854 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6856 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6858 (*MIB).addOperand(*argOpers[valArgIndx]);
6860 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
6863 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
6864 for (int i=0; i <= lastAddrIndx; ++i)
6865 (*MIB).addOperand(*argOpers[i]);
6867 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6868 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6870 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6874 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6876 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6880 // private utility function: 64 bit atomics on 32 bit host.
6882 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
6883 MachineBasicBlock *MBB,
6889 // For the atomic bitwise operator, we generate
6890 // thisMBB (instructions are in pairs, except cmpxchg8b)
6891 // ld t1,t2 = [bitinstr.addr]
6893 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
6894 // op t5, t6 <- out1, out2, [bitinstr.val]
6895 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
6896 // mov ECX, EBX <- t5, t6
6897 // mov EAX, EDX <- t1, t2
6898 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
6899 // mov t3, t4 <- EAX, EDX
6901 // result in out1, out2
6902 // fallthrough -->nextMBB
6904 const TargetRegisterClass *RC = X86::GR32RegisterClass;
6905 const unsigned LoadOpc = X86::MOV32rm;
6906 const unsigned copyOpc = X86::MOV32rr;
6907 const unsigned NotOpc = X86::NOT32r;
6908 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6909 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6910 MachineFunction::iterator MBBIter = MBB;
6913 /// First build the CFG
6914 MachineFunction *F = MBB->getParent();
6915 MachineBasicBlock *thisMBB = MBB;
6916 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6917 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6918 F->insert(MBBIter, newMBB);
6919 F->insert(MBBIter, nextMBB);
6921 // Move all successors to thisMBB to nextMBB
6922 nextMBB->transferSuccessors(thisMBB);
6924 // Update thisMBB to fall through to newMBB
6925 thisMBB->addSuccessor(newMBB);
6927 // newMBB jumps to itself and fall through to nextMBB
6928 newMBB->addSuccessor(nextMBB);
6929 newMBB->addSuccessor(newMBB);
6931 // Insert instructions into newMBB based on incoming instruction
6932 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
6933 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
6934 MachineOperand& dest1Oper = bInstr->getOperand(0);
6935 MachineOperand& dest2Oper = bInstr->getOperand(1);
6936 MachineOperand* argOpers[6];
6937 for (int i=0; i < 6; ++i)
6938 argOpers[i] = &bInstr->getOperand(i+2);
6940 // x86 address has 4 operands: base, index, scale, and displacement
6941 int lastAddrIndx = 3; // [0,3]
6943 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6944 MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1);
6945 for (int i=0; i <= lastAddrIndx; ++i)
6946 (*MIB).addOperand(*argOpers[i]);
6947 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6948 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2);
6949 // add 4 to displacement.
6950 for (int i=0; i <= lastAddrIndx-1; ++i)
6951 (*MIB).addOperand(*argOpers[i]);
6952 MachineOperand newOp3 = *(argOpers[3]);
6954 newOp3.setImm(newOp3.getImm()+4);
6956 newOp3.setOffset(newOp3.getOffset()+4);
6957 (*MIB).addOperand(newOp3);
6959 // t3/4 are defined later, at the bottom of the loop
6960 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
6961 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
6962 BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg())
6963 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
6964 BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg())
6965 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
6967 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
6968 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
6970 MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1);
6971 MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2);
6977 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
6979 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
6980 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
6981 if (argOpers[4]->isReg())
6982 MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
6984 MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
6985 if (regOpcL != X86::MOV32rr)
6987 (*MIB).addOperand(*argOpers[4]);
6988 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
6989 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
6990 if (argOpers[5]->isReg())
6991 MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
6993 MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
6994 if (regOpcH != X86::MOV32rr)
6996 (*MIB).addOperand(*argOpers[5]);
6998 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX);
7000 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX);
7003 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX);
7005 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX);
7008 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B));
7009 for (int i=0; i <= lastAddrIndx; ++i)
7010 (*MIB).addOperand(*argOpers[i]);
7012 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7013 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7015 MIB = BuildMI(newMBB, TII->get(copyOpc), t3);
7016 MIB.addReg(X86::EAX);
7017 MIB = BuildMI(newMBB, TII->get(copyOpc), t4);
7018 MIB.addReg(X86::EDX);
7021 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
7023 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7027 // private utility function
7029 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7030 MachineBasicBlock *MBB,
7032 // For the atomic min/max operator, we generate
7035 // ld t1 = [min/max.addr]
7036 // mov t2 = [min/max.val]
7038 // cmov[cond] t2 = t1
7040 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7042 // fallthrough -->nextMBB
7044 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7045 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7046 MachineFunction::iterator MBBIter = MBB;
7049 /// First build the CFG
7050 MachineFunction *F = MBB->getParent();
7051 MachineBasicBlock *thisMBB = MBB;
7052 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7053 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7054 F->insert(MBBIter, newMBB);
7055 F->insert(MBBIter, nextMBB);
7057 // Move all successors to thisMBB to nextMBB
7058 nextMBB->transferSuccessors(thisMBB);
7060 // Update thisMBB to fall through to newMBB
7061 thisMBB->addSuccessor(newMBB);
7063 // newMBB jumps to newMBB and fall through to nextMBB
7064 newMBB->addSuccessor(nextMBB);
7065 newMBB->addSuccessor(newMBB);
7067 // Insert instructions into newMBB based on incoming instruction
7068 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
7069 MachineOperand& destOper = mInstr->getOperand(0);
7070 MachineOperand* argOpers[6];
7071 int numArgs = mInstr->getNumOperands() - 1;
7072 for (int i=0; i < numArgs; ++i)
7073 argOpers[i] = &mInstr->getOperand(i+1);
7075 // x86 address has 4 operands: base, index, scale, and displacement
7076 int lastAddrIndx = 3; // [0,3]
7079 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7080 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
7081 for (int i=0; i <= lastAddrIndx; ++i)
7082 (*MIB).addOperand(*argOpers[i]);
7084 // We only support register and immediate values
7085 assert((argOpers[valArgIndx]->isReg() ||
7086 argOpers[valArgIndx]->isImm()) &&
7089 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7090 if (argOpers[valArgIndx]->isReg())
7091 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
7093 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
7094 (*MIB).addOperand(*argOpers[valArgIndx]);
7096 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
7099 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
7104 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7105 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
7109 // Cmp and exchange if none has modified the memory location
7110 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
7111 for (int i=0; i <= lastAddrIndx; ++i)
7112 (*MIB).addOperand(*argOpers[i]);
7114 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7115 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7117 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
7118 MIB.addReg(X86::EAX);
7121 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
7123 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7129 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7130 MachineBasicBlock *BB) {
7131 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7132 switch (MI->getOpcode()) {
7133 default: assert(false && "Unexpected instr type to insert");
7134 case X86::CMOV_V1I64:
7135 case X86::CMOV_FR32:
7136 case X86::CMOV_FR64:
7137 case X86::CMOV_V4F32:
7138 case X86::CMOV_V2F64:
7139 case X86::CMOV_V2I64: {
7140 // To "insert" a SELECT_CC instruction, we actually have to insert the
7141 // diamond control-flow pattern. The incoming instruction knows the
7142 // destination vreg to set, the condition code register to branch on, the
7143 // true/false values to select between, and a branch opcode to use.
7144 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7145 MachineFunction::iterator It = BB;
7151 // cmpTY ccX, r1, r2
7153 // fallthrough --> copy0MBB
7154 MachineBasicBlock *thisMBB = BB;
7155 MachineFunction *F = BB->getParent();
7156 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7157 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7159 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7160 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
7161 F->insert(It, copy0MBB);
7162 F->insert(It, sinkMBB);
7163 // Update machine-CFG edges by transferring all successors of the current
7164 // block to the new block which will contain the Phi node for the select.
7165 sinkMBB->transferSuccessors(BB);
7167 // Add the true and fallthrough blocks as its successors.
7168 BB->addSuccessor(copy0MBB);
7169 BB->addSuccessor(sinkMBB);
7172 // %FalseValue = ...
7173 // # fallthrough to sinkMBB
7176 // Update machine-CFG edges
7177 BB->addSuccessor(sinkMBB);
7180 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7183 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
7184 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7185 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7187 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7191 case X86::FP32_TO_INT16_IN_MEM:
7192 case X86::FP32_TO_INT32_IN_MEM:
7193 case X86::FP32_TO_INT64_IN_MEM:
7194 case X86::FP64_TO_INT16_IN_MEM:
7195 case X86::FP64_TO_INT32_IN_MEM:
7196 case X86::FP64_TO_INT64_IN_MEM:
7197 case X86::FP80_TO_INT16_IN_MEM:
7198 case X86::FP80_TO_INT32_IN_MEM:
7199 case X86::FP80_TO_INT64_IN_MEM: {
7200 // Change the floating point control register to use "round towards zero"
7201 // mode when truncating to an integer value.
7202 MachineFunction *F = BB->getParent();
7203 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7204 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7206 // Load the old value of the high byte of the control word...
7208 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7209 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
7211 // Set the high part to be round to zero...
7212 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
7215 // Reload the modified control word now...
7216 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
7218 // Restore the memory image of control word to original value
7219 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
7222 // Get the X86 opcode to use.
7224 switch (MI->getOpcode()) {
7225 default: assert(0 && "illegal opcode!");
7226 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7227 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7228 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7229 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7230 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7231 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7232 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7233 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7234 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7238 MachineOperand &Op = MI->getOperand(0);
7240 AM.BaseType = X86AddressMode::RegBase;
7241 AM.Base.Reg = Op.getReg();
7243 AM.BaseType = X86AddressMode::FrameIndexBase;
7244 AM.Base.FrameIndex = Op.getIndex();
7246 Op = MI->getOperand(1);
7248 AM.Scale = Op.getImm();
7249 Op = MI->getOperand(2);
7251 AM.IndexReg = Op.getImm();
7252 Op = MI->getOperand(3);
7253 if (Op.isGlobal()) {
7254 AM.GV = Op.getGlobal();
7256 AM.Disp = Op.getImm();
7258 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
7259 .addReg(MI->getOperand(4).getReg());
7261 // Reload the original control word now.
7262 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
7264 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7267 case X86::ATOMAND32:
7268 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7269 X86::AND32ri, X86::MOV32rm,
7270 X86::LCMPXCHG32, X86::MOV32rr,
7271 X86::NOT32r, X86::EAX,
7272 X86::GR32RegisterClass);
7274 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7275 X86::OR32ri, X86::MOV32rm,
7276 X86::LCMPXCHG32, X86::MOV32rr,
7277 X86::NOT32r, X86::EAX,
7278 X86::GR32RegisterClass);
7279 case X86::ATOMXOR32:
7280 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7281 X86::XOR32ri, X86::MOV32rm,
7282 X86::LCMPXCHG32, X86::MOV32rr,
7283 X86::NOT32r, X86::EAX,
7284 X86::GR32RegisterClass);
7285 case X86::ATOMNAND32:
7286 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7287 X86::AND32ri, X86::MOV32rm,
7288 X86::LCMPXCHG32, X86::MOV32rr,
7289 X86::NOT32r, X86::EAX,
7290 X86::GR32RegisterClass, true);
7291 case X86::ATOMMIN32:
7292 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7293 case X86::ATOMMAX32:
7294 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7295 case X86::ATOMUMIN32:
7296 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7297 case X86::ATOMUMAX32:
7298 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7300 case X86::ATOMAND16:
7301 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7302 X86::AND16ri, X86::MOV16rm,
7303 X86::LCMPXCHG16, X86::MOV16rr,
7304 X86::NOT16r, X86::AX,
7305 X86::GR16RegisterClass);
7307 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7308 X86::OR16ri, X86::MOV16rm,
7309 X86::LCMPXCHG16, X86::MOV16rr,
7310 X86::NOT16r, X86::AX,
7311 X86::GR16RegisterClass);
7312 case X86::ATOMXOR16:
7313 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7314 X86::XOR16ri, X86::MOV16rm,
7315 X86::LCMPXCHG16, X86::MOV16rr,
7316 X86::NOT16r, X86::AX,
7317 X86::GR16RegisterClass);
7318 case X86::ATOMNAND16:
7319 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7320 X86::AND16ri, X86::MOV16rm,
7321 X86::LCMPXCHG16, X86::MOV16rr,
7322 X86::NOT16r, X86::AX,
7323 X86::GR16RegisterClass, true);
7324 case X86::ATOMMIN16:
7325 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7326 case X86::ATOMMAX16:
7327 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7328 case X86::ATOMUMIN16:
7329 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7330 case X86::ATOMUMAX16:
7331 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7334 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7335 X86::AND8ri, X86::MOV8rm,
7336 X86::LCMPXCHG8, X86::MOV8rr,
7337 X86::NOT8r, X86::AL,
7338 X86::GR8RegisterClass);
7340 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7341 X86::OR8ri, X86::MOV8rm,
7342 X86::LCMPXCHG8, X86::MOV8rr,
7343 X86::NOT8r, X86::AL,
7344 X86::GR8RegisterClass);
7346 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7347 X86::XOR8ri, X86::MOV8rm,
7348 X86::LCMPXCHG8, X86::MOV8rr,
7349 X86::NOT8r, X86::AL,
7350 X86::GR8RegisterClass);
7351 case X86::ATOMNAND8:
7352 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7353 X86::AND8ri, X86::MOV8rm,
7354 X86::LCMPXCHG8, X86::MOV8rr,
7355 X86::NOT8r, X86::AL,
7356 X86::GR8RegisterClass, true);
7357 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7358 // This group is for 64-bit host.
7359 case X86::ATOMAND64:
7360 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7361 X86::AND64ri32, X86::MOV64rm,
7362 X86::LCMPXCHG64, X86::MOV64rr,
7363 X86::NOT64r, X86::RAX,
7364 X86::GR64RegisterClass);
7366 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7367 X86::OR64ri32, X86::MOV64rm,
7368 X86::LCMPXCHG64, X86::MOV64rr,
7369 X86::NOT64r, X86::RAX,
7370 X86::GR64RegisterClass);
7371 case X86::ATOMXOR64:
7372 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7373 X86::XOR64ri32, X86::MOV64rm,
7374 X86::LCMPXCHG64, X86::MOV64rr,
7375 X86::NOT64r, X86::RAX,
7376 X86::GR64RegisterClass);
7377 case X86::ATOMNAND64:
7378 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7379 X86::AND64ri32, X86::MOV64rm,
7380 X86::LCMPXCHG64, X86::MOV64rr,
7381 X86::NOT64r, X86::RAX,
7382 X86::GR64RegisterClass, true);
7383 case X86::ATOMMIN64:
7384 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7385 case X86::ATOMMAX64:
7386 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7387 case X86::ATOMUMIN64:
7388 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7389 case X86::ATOMUMAX64:
7390 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7392 // This group does 64-bit operations on a 32-bit host.
7393 case X86::ATOMAND6432:
7394 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7395 X86::AND32rr, X86::AND32rr,
7396 X86::AND32ri, X86::AND32ri,
7398 case X86::ATOMOR6432:
7399 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7400 X86::OR32rr, X86::OR32rr,
7401 X86::OR32ri, X86::OR32ri,
7403 case X86::ATOMXOR6432:
7404 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7405 X86::XOR32rr, X86::XOR32rr,
7406 X86::XOR32ri, X86::XOR32ri,
7408 case X86::ATOMNAND6432:
7409 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7410 X86::AND32rr, X86::AND32rr,
7411 X86::AND32ri, X86::AND32ri,
7413 case X86::ATOMADD6432:
7414 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7415 X86::ADD32rr, X86::ADC32rr,
7416 X86::ADD32ri, X86::ADC32ri,
7418 case X86::ATOMSUB6432:
7419 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7420 X86::SUB32rr, X86::SBB32rr,
7421 X86::SUB32ri, X86::SBB32ri,
7423 case X86::ATOMSWAP6432:
7424 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7425 X86::MOV32rr, X86::MOV32rr,
7426 X86::MOV32ri, X86::MOV32ri,
7431 //===----------------------------------------------------------------------===//
7432 // X86 Optimization Hooks
7433 //===----------------------------------------------------------------------===//
7435 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7439 const SelectionDAG &DAG,
7440 unsigned Depth) const {
7441 unsigned Opc = Op.getOpcode();
7442 assert((Opc >= ISD::BUILTIN_OP_END ||
7443 Opc == ISD::INTRINSIC_WO_CHAIN ||
7444 Opc == ISD::INTRINSIC_W_CHAIN ||
7445 Opc == ISD::INTRINSIC_VOID) &&
7446 "Should use MaskedValueIsZero if you don't know whether Op"
7447 " is a target node!");
7449 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7453 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7454 Mask.getBitWidth() - 1);
7459 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7460 /// node is a GlobalAddress + offset.
7461 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7462 GlobalValue* &GA, int64_t &Offset) const{
7463 if (N->getOpcode() == X86ISD::Wrapper) {
7464 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7465 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7466 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7470 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7473 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7474 const TargetLowering &TLI) {
7477 if (TLI.isGAPlusOffset(Base, GV, Offset))
7478 return (GV->getAlignment() >= N && (Offset % N) == 0);
7479 // DAG combine handles the stack object case.
7483 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
7484 unsigned NumElems, MVT EVT,
7486 SelectionDAG &DAG, MachineFrameInfo *MFI,
7487 const TargetLowering &TLI) {
7489 for (unsigned i = 0; i < NumElems; ++i) {
7490 SDValue Idx = PermMask.getOperand(i);
7491 if (Idx.getOpcode() == ISD::UNDEF) {
7497 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7498 if (!Elt.getNode() ||
7499 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7502 Base = Elt.getNode();
7503 if (Base->getOpcode() == ISD::UNDEF)
7507 if (Elt.getOpcode() == ISD::UNDEF)
7510 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
7511 EVT.getSizeInBits()/8, i, MFI))
7517 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7518 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7519 /// if the load addresses are consecutive, non-overlapping, and in the right
7521 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7522 const TargetLowering &TLI) {
7523 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7524 MVT VT = N->getValueType(0);
7525 MVT EVT = VT.getVectorElementType();
7526 SDValue PermMask = N->getOperand(2);
7527 unsigned NumElems = PermMask.getNumOperands();
7528 SDNode *Base = NULL;
7529 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
7533 LoadSDNode *LD = cast<LoadSDNode>(Base);
7534 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
7535 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7536 LD->getSrcValueOffset(), LD->isVolatile());
7537 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7538 LD->getSrcValueOffset(), LD->isVolatile(),
7539 LD->getAlignment());
7542 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
7543 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
7544 const X86Subtarget *Subtarget,
7545 const TargetLowering &TLI) {
7546 unsigned NumOps = N->getNumOperands();
7548 // Ignore single operand BUILD_VECTOR.
7552 MVT VT = N->getValueType(0);
7553 MVT EVT = VT.getVectorElementType();
7554 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
7555 // We are looking for load i64 and zero extend. We want to transform
7556 // it before legalizer has a chance to expand it. Also look for i64
7557 // BUILD_PAIR bit casted to f64.
7559 // This must be an insertion into a zero vector.
7560 SDValue HighElt = N->getOperand(1);
7561 if (!isZeroNode(HighElt))
7564 // Value must be a load.
7565 SDNode *Base = N->getOperand(0).getNode();
7566 if (!isa<LoadSDNode>(Base)) {
7567 if (Base->getOpcode() != ISD::BIT_CONVERT)
7569 Base = Base->getOperand(0).getNode();
7570 if (!isa<LoadSDNode>(Base))
7574 // Transform it into VZEXT_LOAD addr.
7575 LoadSDNode *LD = cast<LoadSDNode>(Base);
7577 // Load must not be an extload.
7578 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
7581 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
7582 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7583 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
7584 DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1));
7588 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7589 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7590 const X86Subtarget *Subtarget) {
7591 SDValue Cond = N->getOperand(0);
7593 // If we have SSE[12] support, try to form min/max nodes.
7594 if (Subtarget->hasSSE2() &&
7595 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
7596 if (Cond.getOpcode() == ISD::SETCC) {
7597 // Get the LHS/RHS of the select.
7598 SDValue LHS = N->getOperand(1);
7599 SDValue RHS = N->getOperand(2);
7600 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
7602 unsigned Opcode = 0;
7603 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7606 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
7609 if (!UnsafeFPMath) break;
7611 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
7613 Opcode = X86ISD::FMIN;
7616 case ISD::SETOGT: // (X > Y) ? X : Y -> max
7619 if (!UnsafeFPMath) break;
7621 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
7623 Opcode = X86ISD::FMAX;
7626 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
7629 case ISD::SETOGT: // (X > Y) ? Y : X -> min
7632 if (!UnsafeFPMath) break;
7634 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
7636 Opcode = X86ISD::FMIN;
7639 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
7642 if (!UnsafeFPMath) break;
7644 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
7646 Opcode = X86ISD::FMAX;
7652 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
7660 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
7662 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
7663 const X86Subtarget *Subtarget) {
7664 // On X86 with SSE2 support, we can transform this to a vector shift if
7665 // all elements are shifted by the same amount. We can't do this in legalize
7666 // because the a constant vector is typically transformed to a constant pool
7667 // so we have no knowledge of the shift amount.
7668 MVT VT = N->getValueType(0);
7669 if (Subtarget->hasSSE2() &&
7670 (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16)) {
7671 SDValue ValOp = N->getOperand(0);
7672 SDValue ShAmtOp = N->getOperand(1);
7673 unsigned NumElts = VT.getVectorNumElements();
7675 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
7678 for (; i != NumElts; ++i) {
7679 SDValue Arg = ShAmtOp.getOperand(i);
7680 if (Arg.getOpcode() == ISD::UNDEF) continue;
7684 for (; i != NumElts; ++i) {
7685 SDValue Arg = ShAmtOp.getOperand(i);
7686 if (Arg.getOpcode() == ISD::UNDEF) continue;
7687 if (Arg != BaseShAmt) {
7692 MVT EltVT = VT.getVectorElementType();
7693 if (EltVT.bitsGT(MVT::i32))
7694 BaseShAmt = DAG.getNode(ISD::TRUNCATE, MVT::i32, BaseShAmt);
7695 else if (EltVT.bitsLT(MVT::i32))
7696 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BaseShAmt);
7698 // The shift amount is identical so we can do a vector shift.
7699 switch (N->getOpcode()) {
7701 assert(0 && "Unknown shift opcode!");
7704 if (VT == MVT::v2i64)
7705 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7706 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7708 else if (VT == MVT::v4i32)
7709 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7710 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
7712 else if (VT == MVT::v8i16)
7713 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7714 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
7718 if (VT == MVT::v4i32)
7719 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7720 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
7722 else if (VT == MVT::v8i16)
7723 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7724 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
7728 if (VT == MVT::v2i64)
7729 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7730 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7732 else if (VT == MVT::v4i32)
7733 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7734 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
7736 else if (VT == MVT::v8i16)
7737 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7738 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
7747 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
7748 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
7749 const X86Subtarget *Subtarget) {
7750 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
7751 // the FP state in cases where an emms may be missing.
7752 // A preferable solution to the general problem is to figure out the right
7753 // places to insert EMMS. This qualifies as a quick hack.
7754 StoreSDNode *St = cast<StoreSDNode>(N);
7755 if (St->getValue().getValueType().isVector() &&
7756 St->getValue().getValueType().getSizeInBits() == 64 &&
7757 isa<LoadSDNode>(St->getValue()) &&
7758 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
7759 St->getChain().hasOneUse() && !St->isVolatile()) {
7760 SDNode* LdVal = St->getValue().getNode();
7762 int TokenFactorIndex = -1;
7763 SmallVector<SDValue, 8> Ops;
7764 SDNode* ChainVal = St->getChain().getNode();
7765 // Must be a store of a load. We currently handle two cases: the load
7766 // is a direct child, and it's under an intervening TokenFactor. It is
7767 // possible to dig deeper under nested TokenFactors.
7768 if (ChainVal == LdVal)
7769 Ld = cast<LoadSDNode>(St->getChain());
7770 else if (St->getValue().hasOneUse() &&
7771 ChainVal->getOpcode() == ISD::TokenFactor) {
7772 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
7773 if (ChainVal->getOperand(i).getNode() == LdVal) {
7774 TokenFactorIndex = i;
7775 Ld = cast<LoadSDNode>(St->getValue());
7777 Ops.push_back(ChainVal->getOperand(i));
7781 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
7782 if (Subtarget->is64Bit()) {
7783 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
7784 Ld->getBasePtr(), Ld->getSrcValue(),
7785 Ld->getSrcValueOffset(), Ld->isVolatile(),
7786 Ld->getAlignment());
7787 SDValue NewChain = NewLd.getValue(1);
7788 if (TokenFactorIndex != -1) {
7789 Ops.push_back(NewChain);
7790 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7793 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
7794 St->getSrcValue(), St->getSrcValueOffset(),
7795 St->isVolatile(), St->getAlignment());
7798 // Otherwise, lower to two 32-bit copies.
7799 SDValue LoAddr = Ld->getBasePtr();
7800 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7801 DAG.getConstant(4, MVT::i32));
7803 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
7804 Ld->getSrcValue(), Ld->getSrcValueOffset(),
7805 Ld->isVolatile(), Ld->getAlignment());
7806 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
7807 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
7809 MinAlign(Ld->getAlignment(), 4));
7811 SDValue NewChain = LoLd.getValue(1);
7812 if (TokenFactorIndex != -1) {
7813 Ops.push_back(LoLd);
7814 Ops.push_back(HiLd);
7815 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7819 LoAddr = St->getBasePtr();
7820 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7821 DAG.getConstant(4, MVT::i32));
7823 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
7824 St->getSrcValue(), St->getSrcValueOffset(),
7825 St->isVolatile(), St->getAlignment());
7826 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
7828 St->getSrcValueOffset() + 4,
7830 MinAlign(St->getAlignment(), 4));
7831 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
7837 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
7838 /// X86ISD::FXOR nodes.
7839 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
7840 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
7841 // F[X]OR(0.0, x) -> x
7842 // F[X]OR(x, 0.0) -> x
7843 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7844 if (C->getValueAPF().isPosZero())
7845 return N->getOperand(1);
7846 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7847 if (C->getValueAPF().isPosZero())
7848 return N->getOperand(0);
7852 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
7853 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
7854 // FAND(0.0, x) -> 0.0
7855 // FAND(x, 0.0) -> 0.0
7856 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7857 if (C->getValueAPF().isPosZero())
7858 return N->getOperand(0);
7859 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7860 if (C->getValueAPF().isPosZero())
7861 return N->getOperand(1);
7866 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
7867 DAGCombinerInfo &DCI) const {
7868 SelectionDAG &DAG = DCI.DAG;
7869 switch (N->getOpcode()) {
7871 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
7872 case ISD::BUILD_VECTOR:
7873 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
7874 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
7877 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
7878 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
7880 case X86ISD::FOR: return PerformFORCombine(N, DAG);
7881 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
7887 //===----------------------------------------------------------------------===//
7888 // X86 Inline Assembly Support
7889 //===----------------------------------------------------------------------===//
7891 /// getConstraintType - Given a constraint letter, return the type of
7892 /// constraint it is for this target.
7893 X86TargetLowering::ConstraintType
7894 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
7895 if (Constraint.size() == 1) {
7896 switch (Constraint[0]) {
7908 return C_RegisterClass;
7913 return TargetLowering::getConstraintType(Constraint);
7916 /// LowerXConstraint - try to replace an X constraint, which matches anything,
7917 /// with another that has more specific requirements based on the type of the
7918 /// corresponding operand.
7919 const char *X86TargetLowering::
7920 LowerXConstraint(MVT ConstraintVT) const {
7921 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
7922 // 'f' like normal targets.
7923 if (ConstraintVT.isFloatingPoint()) {
7924 if (Subtarget->hasSSE2())
7926 if (Subtarget->hasSSE1())
7930 return TargetLowering::LowerXConstraint(ConstraintVT);
7933 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7934 /// vector. If it is invalid, don't add anything to Ops.
7935 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7938 std::vector<SDValue>&Ops,
7939 SelectionDAG &DAG) const {
7940 SDValue Result(0, 0);
7942 switch (Constraint) {
7945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7946 if (C->getZExtValue() <= 31) {
7947 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7953 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7954 if (C->getZExtValue() <= 63) {
7955 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7961 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7962 if (C->getZExtValue() <= 255) {
7963 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7969 // Literal immediates are always ok.
7970 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
7971 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
7975 // If we are in non-pic codegen mode, we allow the address of a global (with
7976 // an optional displacement) to be used with 'i'.
7977 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
7980 // Match either (GA) or (GA+C)
7982 Offset = GA->getOffset();
7983 } else if (Op.getOpcode() == ISD::ADD) {
7984 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7985 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7987 Offset = GA->getOffset()+C->getZExtValue();
7989 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7990 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7992 Offset = GA->getOffset()+C->getZExtValue();
8000 Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG);
8002 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
8008 // Otherwise, not valid for this mode.
8013 if (Result.getNode()) {
8014 Ops.push_back(Result);
8017 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8021 std::vector<unsigned> X86TargetLowering::
8022 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8024 if (Constraint.size() == 1) {
8025 // FIXME: not handling fp-stack yet!
8026 switch (Constraint[0]) { // GCC X86 Constraint Letters
8027 default: break; // Unknown constraint letter
8028 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
8031 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
8032 else if (VT == MVT::i16)
8033 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
8034 else if (VT == MVT::i8)
8035 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
8036 else if (VT == MVT::i64)
8037 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
8042 return std::vector<unsigned>();
8045 std::pair<unsigned, const TargetRegisterClass*>
8046 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8048 // First, see if this is a constraint that directly corresponds to an LLVM
8050 if (Constraint.size() == 1) {
8051 // GCC Constraint Letters
8052 switch (Constraint[0]) {
8054 case 'r': // GENERAL_REGS
8055 case 'R': // LEGACY_REGS
8056 case 'l': // INDEX_REGS
8058 return std::make_pair(0U, X86::GR8RegisterClass);
8060 return std::make_pair(0U, X86::GR16RegisterClass);
8061 if (VT == MVT::i32 || !Subtarget->is64Bit())
8062 return std::make_pair(0U, X86::GR32RegisterClass);
8063 return std::make_pair(0U, X86::GR64RegisterClass);
8064 case 'f': // FP Stack registers.
8065 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
8066 // value to the correct fpstack register class.
8067 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
8068 return std::make_pair(0U, X86::RFP32RegisterClass);
8069 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
8070 return std::make_pair(0U, X86::RFP64RegisterClass);
8071 return std::make_pair(0U, X86::RFP80RegisterClass);
8072 case 'y': // MMX_REGS if MMX allowed.
8073 if (!Subtarget->hasMMX()) break;
8074 return std::make_pair(0U, X86::VR64RegisterClass);
8075 case 'Y': // SSE_REGS if SSE2 allowed
8076 if (!Subtarget->hasSSE2()) break;
8078 case 'x': // SSE_REGS if SSE1 allowed
8079 if (!Subtarget->hasSSE1()) break;
8081 switch (VT.getSimpleVT()) {
8083 // Scalar SSE types.
8086 return std::make_pair(0U, X86::FR32RegisterClass);
8089 return std::make_pair(0U, X86::FR64RegisterClass);
8097 return std::make_pair(0U, X86::VR128RegisterClass);
8103 // Use the default implementation in TargetLowering to convert the register
8104 // constraint into a member of a register class.
8105 std::pair<unsigned, const TargetRegisterClass*> Res;
8106 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8108 // Not found as a standard register?
8109 if (Res.second == 0) {
8110 // GCC calls "st(0)" just plain "st".
8111 if (StringsEqualNoCase("{st}", Constraint)) {
8112 Res.first = X86::ST0;
8113 Res.second = X86::RFP80RegisterClass;
8115 // 'A' means EAX + EDX.
8116 if (Constraint == "A") {
8117 Res.first = X86::EAX;
8118 Res.second = X86::GRADRegisterClass;
8123 // Otherwise, check to see if this is a register class of the wrong value
8124 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
8125 // turn into {ax},{dx}.
8126 if (Res.second->hasType(VT))
8127 return Res; // Correct type already, nothing to do.
8129 // All of the single-register GCC register classes map their values onto
8130 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
8131 // really want an 8-bit or 32-bit register, map to the appropriate register
8132 // class and return the appropriate register.
8133 if (Res.second == X86::GR16RegisterClass) {
8134 if (VT == MVT::i8) {
8135 unsigned DestReg = 0;
8136 switch (Res.first) {
8138 case X86::AX: DestReg = X86::AL; break;
8139 case X86::DX: DestReg = X86::DL; break;
8140 case X86::CX: DestReg = X86::CL; break;
8141 case X86::BX: DestReg = X86::BL; break;
8144 Res.first = DestReg;
8145 Res.second = Res.second = X86::GR8RegisterClass;
8147 } else if (VT == MVT::i32) {
8148 unsigned DestReg = 0;
8149 switch (Res.first) {
8151 case X86::AX: DestReg = X86::EAX; break;
8152 case X86::DX: DestReg = X86::EDX; break;
8153 case X86::CX: DestReg = X86::ECX; break;
8154 case X86::BX: DestReg = X86::EBX; break;
8155 case X86::SI: DestReg = X86::ESI; break;
8156 case X86::DI: DestReg = X86::EDI; break;
8157 case X86::BP: DestReg = X86::EBP; break;
8158 case X86::SP: DestReg = X86::ESP; break;
8161 Res.first = DestReg;
8162 Res.second = Res.second = X86::GR32RegisterClass;
8164 } else if (VT == MVT::i64) {
8165 unsigned DestReg = 0;
8166 switch (Res.first) {
8168 case X86::AX: DestReg = X86::RAX; break;
8169 case X86::DX: DestReg = X86::RDX; break;
8170 case X86::CX: DestReg = X86::RCX; break;
8171 case X86::BX: DestReg = X86::RBX; break;
8172 case X86::SI: DestReg = X86::RSI; break;
8173 case X86::DI: DestReg = X86::RDI; break;
8174 case X86::BP: DestReg = X86::RBP; break;
8175 case X86::SP: DestReg = X86::RSP; break;
8178 Res.first = DestReg;
8179 Res.second = Res.second = X86::GR64RegisterClass;
8182 } else if (Res.second == X86::FR32RegisterClass ||
8183 Res.second == X86::FR64RegisterClass ||
8184 Res.second == X86::VR128RegisterClass) {
8185 // Handle references to XMM physical registers that got mapped into the
8186 // wrong class. This can happen with constraints like {xmm0} where the
8187 // target independent register mapper will just pick the first match it can
8188 // find, ignoring the required type.
8190 Res.second = X86::FR32RegisterClass;
8191 else if (VT == MVT::f64)
8192 Res.second = X86::FR64RegisterClass;
8193 else if (X86::VR128RegisterClass->hasType(VT))
8194 Res.second = X86::VR128RegisterClass;
8200 //===----------------------------------------------------------------------===//
8201 // X86 Widen vector type
8202 //===----------------------------------------------------------------------===//
8204 /// getWidenVectorType: given a vector type, returns the type to widen
8205 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
8206 /// If there is no vector type that we want to widen to, returns MVT::Other
8207 /// When and where to widen is target dependent based on the cost of
8208 /// scalarizing vs using the wider vector type.
8210 MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
8211 assert(VT.isVector());
8212 if (isTypeLegal(VT))
8215 // TODO: In computeRegisterProperty, we can compute the list of legal vector
8216 // type based on element type. This would speed up our search (though
8217 // it may not be worth it since the size of the list is relatively
8219 MVT EltVT = VT.getVectorElementType();
8220 unsigned NElts = VT.getVectorNumElements();
8222 // On X86, it make sense to widen any vector wider than 1
8226 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
8227 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
8228 MVT SVT = (MVT::SimpleValueType)nVT;
8230 if (isTypeLegal(SVT) &&
8231 SVT.getVectorElementType() == EltVT &&
8232 SVT.getVectorNumElements() > NElts)